Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device that can be manufactured by a simple process, in which a thick gate insulating film can be formed.SOLUTION: A semiconductor device including a first semiconductor element and a second semiconductor element is formed on a substrate. The second semiconductor element includes a second multilayer body including a second Si layer and a second gate electrode that covers the periphery of the second Si layer at a cross section of the second semiconductor element in a gate width direction, a second gate insulating film held between the second Si layer and the second gate electrode and having a larger thickness than a first gate insulating film, a second source-drain region formed at a side surface of the second multilayer body in a gate length direction, and a third Si layer and a second insulating layer formed between the second gate electrode disposed in the interlayer of the second Si layer and a side surface of the second source-drain region.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In a semiconductor device having a GAA-FET (Gate All Around Field Effect Transistor) using a nanosheet structure, an input / output (IO) device is formed in the vicinity of a logic device using the GAA-FET. The input / output device needs to operate at a voltage higher than that of the GAA-FET constituting the logic device. For this reason, when trying to form the input / output device with a GAA-FET, it is necessary to make the gate insulating film thicker than before.

[0003] However, when manufacturing an input / output device with a GAA-FET structure by a conventional method for manufacturing a GAA-FET using a nanosheet, it is difficult to form a gate insulating film with a sufficient thickness to withstand a high voltage. For example, when forming a thick gate insulating film on a GAA-FET using a nanosheet in the input / output section, the laminated Si layers (Si nanosheet layers) will be filled with the insulating film. In this case, it is difficult to form a gate electrode between the Si layers, and the performance of the semiconductor device is significantly reduced.

[0004] In response to such problems, a technique has been proposed in which, in an input / output device with a GAA-FET structure using a nanosheet structure, the thickness of the SiGe layer laminated between the Si layers is made larger than that of the SiGe layer of the logic device (see, for example, Patent Document 1). In this technique, in the manufacturing process of the GAA-FET, when forming the SiGe layer disposed between the Si layers, an epitaxial growth process in a separate process is added only on the input / output device side. By this additional epitaxial growth process, only on the input / output device side, the thickness of the SiGe layer laminated between the Si nanosheets is increased. Thereby, a larger space is formed between the Si layers, and a space for forming a gate electrode is ensured even in a configuration in which a thick gate insulating film is formed.

[0005] In addition, in a GAA-FET having a structure in which three or more Si nanosheet layers are stacked, a method has been proposed to remove the Si layer disposed in the middle only on the input / output device side (see, for example, Patent Document 2). In this method, for example, a stacked structure of [Si layer / SiGe layer / Si layer / SiGe layer / Si layer] is formed, and the SiGe layer in contact with the Si layer disposed in the middle is selectively oxidized. By this selective oxidation of the SiGe layer, in the Si layer in contact with this SiGe layer, Si is replaced by SiGe. For this reason, the Si layer is replaced by SiGe, and furthermore, the nanosheet itself replaced by SiGe is also selectively oxidized. As a result, the Si layer formed in the middle can be selectively removed together with the SiGe layer, and the other Si layers (the first layer and the third layer) can be left to remain. For this reason, a large space can be formed between the first Si layer and the third Si layer, and even in a configuration in which a thick gate insulating film is formed, a space for forming a gate electrode can be secured.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, in the semiconductor device having the configuration described in Patent Document 1 above, it is necessary to form a thick film portion of the SiGe epitaxial growth layer of the input / output device in a process separate from the logic device. For this reason, it is difficult to match the heights of the Si layer and the like formed on the upper layer of the SiGe layer between the input / output device and the logic device. This difference in height causes variations in the processing height in subsequent processes. In addition, since the thickness of some of the SiGe layers is very large, it is difficult to coat the wall surface of the thick SiGe layer with an insulating layer when forming the insulating layer on the wall surface of the SiGe layer. Therefore, in a configuration in which SiGe layers having a large difference in thickness are stacked, film formation problems are likely to occur. Also, in the semiconductor device having the configuration described in Patent Document 2 above, it is very difficult to perform the substitution process of Si with SiGe by selective oxidation of the SiGe layer and to control this process. Further, after forming the source and drain, since the SiGe layer is oxidized, the source and drain are deteriorated by the influence of the oxidation process. Furthermore, it cannot be applied to a configuration using two types of SiGe having different compositions. As described above, in the semiconductor device having the conventional configuration, the manufacturing process becomes complicated.

[0008] In order to solve the above-described problems, the present invention provides a semiconductor device capable of forming a thick gate insulating film that can be manufactured in an easier process, and a method of manufacturing the semiconductor device.

Means for Solving the Problems

[0009] The semiconductor device of the present invention includes a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element includes a first laminated body composed of a first Si layer and a first gate electrode that covers the periphery of the first Si layer in a cross-section in the gate width direction of the first semiconductor element, a first gate insulating film interposed between the first Si layer and the first gate electrode, a first source / drain region formed on a side surface in the gate length direction of the first laminated body, and a first insulating layer formed between the first gate electrode disposed between the layers of the first Si layer and the side surfaces of the first source / drain region. The second semiconductor element includes a second laminated body composed of a second Si layer and a second gate electrode that covers the periphery of the second Si layer in a cross-section in the gate width direction of the second semiconductor element, a second gate insulating film thicker than the first gate insulating film interposed between the second Si layer and the second gate electrode, a second source / drain region formed on a side surface in the gate length direction of the second laminated body, a third Si layer formed between the second gate electrode disposed between the layers of the second Si layer and the side surfaces of the second source / drain region, and a second insulating layer.

[0010] Also, a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate. The method includes a step of laminating an Si layer and an SiGe layer to form an Si / SiGe laminated body in a formation region of the first semiconductor element and a formation region of the second semiconductor element, a step of ion-implanting impurities into the Si layer in the formation region of the second semiconductor element, a step of forming an insulating layer on a side wall of the SiGe layer, a step of removing the SiGe layer in the formation region of the first semiconductor element, a step of forming a first gate electrode via a first gate insulating film in the formation region of the first semiconductor element, a step of removing the SiGe layer in the formation region of the second semiconductor element, a step of removing the Si layer into which impurities have been ion-implanted so as to remain only between the insulating layers, a step of forming a second gate insulating film thicker than the first gate insulating film in the formation region of the second semiconductor element, and a step of forming a second gate electrode on the gate insulating film of the second semiconductor element.

Advantages of the Invention

[0011] According to the present invention, it is possible to provide a semiconductor device capable of forming a thick film gate insulating film through an easy process and a method for manufacturing the semiconductor device.

Brief Description of the Drawings

[0012]

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. Note that the description will be made in the following order. 1. First Embodiment of Semiconductor Device 2. Manufacturing Method of Semiconductor Device 3. Second Embodiment of Semiconductor Device

[0014] 〈1. First Embodiment of Semiconductor Device〉 Hereinafter, specific embodiments of the semiconductor device of the present invention will be described. FIGS. 1-5 show schematic configuration diagrams of the semiconductor device of the first embodiment. [Configuration of Semiconductor Device] FIG. 1 is a plan view (top view) of the semiconductor device. FIG. 2 is an X1 line cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1. Further, FIG. 3 is a Y1 line cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1. FIG. 4 is an X2 line cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1. Further, FIG. 5 is a Y2 line cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1.

[0015] The semiconductor device 10 shown in FIG. 1 includes a first semiconductor element 100 and a second semiconductor element 200 on a substrate 11. Also, as shown in FIGS. 2-5, the first semiconductor element 100 is composed of a GAA (Gate All Around)-FET formed from a first stacked body formed by laminating Si layers (first Si layers) 101, 102, 103 and gate electrodes 112, 113, 114, 115. The second semiconductor element 200 is composed of a GAA-FET formed from a second stacked body in which Si layers (second Si layers) 201, 203 and gate electrodes 212, 213, 214 are laminated. Further, the Si layers 101, 102, 103 of the first semiconductor element 100 and the Si layers 201, 203 of the second semiconductor element 200 are both composed of nanosheet layers.

[0016] As shown in FIG. 1, the first semiconductor element 100 includes a gate electrode 112 (first gate electrode) formed on the substrate 11, a source region 108, and a drain region 109 (first source / drain region). The second semiconductor element 200 includes a gate electrode 212 (second gate electrode) formed on the substrate 11, a source region 208, and a drain region 209 (second source / drain region).

[0017] As shown in FIG. 1, the second semiconductor element 200 has a longer gate length than the first semiconductor element 100. Since the second semiconductor element 200 is an input / output device, the voltage applied to the gate electrode 112 is higher than that of the first semiconductor element 100. Therefore, in order to suppress the through-current between the source region 108 and the drain region 109, so-called punch-through, it is preferable to make the gate length of the second semiconductor element 200 larger than that of the second semiconductor element 200. On the other hand, the first semiconductor element 100 serving as a logic device preferably has a shorter gate length in order to improve the switching speed.

[0018] Also, as shown in the cross-sectional views in the gate length direction of the first semiconductor element 100 and the second semiconductor element 200 in FIGS. 2 and 4, the second semiconductor element 200 and the first semiconductor element 100 are entirely sealed by an insulating layer 41 on the substrate 11. Further, a STI (Shallow Trench Isolation) 42 is formed as an element isolation region on the surface of the substrate 11. The STI 42 is composed of an insulating layer 41 embedded in the substrate 11. The STI 42 is formed between the first semiconductor element 100 and the second semiconductor element 200. Also, the STI 42 is formed outside the regions where the first semiconductor element 100 and the second semiconductor element 200 are formed.

[0019] (First Semiconductor Element) In the cross-sectional view in the gate length direction shown in FIG. 2, the first semiconductor element 100 has a bottommost gate electrode 113 on the substrate 11. And the first semiconductor element 100 has a first laminate composed of a laminated structure of [gate electrode 113 / Si layer 101 / gate electrode 114 / Si layer 102 / gate electrode 115 / Si layer 103] including the gate electrode 113.

[0020] Also, in the cross-sectional view in the gate length direction shown in FIG. 2, the first semiconductor element 100 has a gate electrode 112 and a sidewall 106 above the uppermost Si layer 103. The gate electrode 112 is formed at the center of the Si layer 103, and the sidewall 106 is formed around the gate electrode 112. The gate electrode 112 includes a metal layer 104. Also, a high-k dielectric material layer (first high-k dielectric layer) 105 is provided on the bottom and side surfaces of the gate electrode 112, that is, on the contact surfaces with the Si layer 103 and the sidewall 106. And the metal layer 104 is filled in the high-k dielectric material layer 105. In the first semiconductor element 100, as the high-k dielectric material layer 105, for example, a layer (not shown) made of a low-k dielectric material that is thinner than the high-k dielectric material layer 105 and has a lower dielectric constant than the high-k dielectric material layer 105 may be combined and used together with the high-k dielectric material layer 105. And in the first semiconductor element 100, the laminated film of the high-k dielectric material layer 105 and the layer made of the low-k dielectric material functions as a gate insulating film (first gate insulating film).

[0021] The first semiconductor element 100 includes a source region 108 and a drain region 109 on the side surfaces of the first laminate composed of the Si layers 101, 102, 103 and the gate electrodes 113, 114, 115. The Si layers 101, 102, 103 are connected to the source region 108 and the drain region 109. An inner spacer 107 (first inner spacer) made of an insulating layer (first insulating layer) is formed between the gate electrodes 113, 114, 115 and the source region 108 and the drain region 109.

[0022] Also, in the cross-sectional view in the gate length direction shown in FIG. 2, the gate electrodes 113, 114, 115 formed between the Si layers 101, 102, 103 are formed by the metal layer 104. Also, the contact surfaces of the gate electrodes 113, 114, 115 with the Si layers 101, 102, 103 and the inner spacer 107 are covered by the high-k dielectric material layer 105. And the metal layer 104 is filled inside the high-k dielectric material layer 105. The metal layer 104 is continuously formed by the gate electrodes 113, 114, 115 and the gate electrode 112.

[0023] In the cross-sectional view in the gate width direction shown in FIG. 3, the first semiconductor element 100 has a high-k dielectric layer 105 formed on the substrate 11 and the STI 42. And the first semiconductor element 100 has Si layers 101, 102, 103 laminated via a metal layer 104 constituting a gate electrode 112 on the high-k dielectric layer 105. Also, a high-k dielectric layer 105 is formed between the metal layer 104 and the Si layers 101, 102, 103. Therefore, in the cross-sectional view in the gate width direction, the Si layers 101, 102, 103 are each surrounded by the high-k dielectric layer 105.

[0024] Also, as can be seen from the cross-sectional view in the gate width direction shown in FIG. 3, the metal layer 104 is continuously formed by the gate electrodes 113, 114, 115 shown in FIG. 2 and the gate electrode 112. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3, the Si layers 101, 102, 103 are surrounded by the gate electrodes 113, 114, 115 and the gate electrode 112. That is, in the first semiconductor element 100, the entire cross-section in the gate length direction of the Si layers 101, 102, 103 that become the channel portion is surrounded by the gate electrodes 112, 113, 114, 115 as shown in FIG. 3.

[0025] (Second Semiconductor Element) In the cross-sectional view in the gate length direction shown in FIG. 4, the second semiconductor element 200 has a bottommost gate electrode 213 on the substrate 11. And the second semiconductor element 200 has a second laminate including a laminate structure of [gate electrode 213 / Si layer 201 / gate electrode 214 / Si layer 203] including the gate electrode 213.

[0026] Also, in the cross-sectional view in the gate length direction shown in FIG. 4, the second semiconductor element 200 has a gate insulating film 210 (second gate insulating film), a gate electrode 212, and a sidewall 206 above the uppermost Si layer 203. The gate insulating film 210 and the gate electrode 212 are formed at the center of the Si layer 203, and the sidewall 206 is formed around the gate insulating film 210 and the gate electrode 212.

[0027] The gate electrode 212 includes a metal layer 204. Also, a high-k dielectric material layer 205 (second high-k dielectric material layer) is provided on the bottom surface and side surfaces of the gate electrode 212, that is, the contact surfaces with the gate insulating film 210. And the metal layer 204 is filled within the high-k dielectric material layer 205.

[0028] The gate insulating film 210 is formed between the Si layers 203 and sidewall 216 and the gate electrode 212. The gate insulating film 210 has a sufficient thickness capable of withstanding the high voltage applied to the second semiconductor element 200 serving as an input / output device. For this reason, the gate insulating film 210 is formed to be sufficiently thicker than the high-k dielectric material layer 205.

[0029] The second semiconductor element 200 includes a source region 208 and a drain region 209 on the side surfaces of the second stacked body composed of the Si layers 201 and 203 and the gate electrodes 213 and 214. The Si layers 201 and 203 are connected to the source region 208 and the drain region 209.

[0030] Also, a gate insulating film 210 is formed between the gate electrodes 213 and 214 and the Si layers 201 and 203. The gate insulating film 210 is formed so as to cover the entire periphery of the gate electrodes 213 and 214 in the gate length direction cross-sectional view shown in FIG. 4. Even in the gate insulating film 210 that covers the entire periphery of the gate electrodes 213 and 214, it has a sufficient thickness capable of withstanding the high voltage applied to the second semiconductor element 200.

[0031] Also, between the gate insulating film 210 covering the gate electrodes 213 and 214 and the source region 208 and the drain region 209, an inner spacer 207 (second inner spacer) made of an insulating layer (second insulating layer) is formed. Also, between the gate electrode 214 and the source region 208 and the drain region 209, a Si layer 202 is formed via the gate insulating film 210. Therefore, between the gate electrodes 213 and 214 and the source region 208 and the drain region 209, the gate insulating film 210, the inner spacer 207, and the Si layer (third Si layer) 202 are interposed. Also, the gate insulating film 210 covering the gate electrodes 213 and 214 is interposed between the gate electrodes 213 and 214 and the source region 208 and the drain region 209.

[0032] Also, in the cross-sectional view in the gate length direction shown in FIG. 4, the gate electrodes 213 and 114 formed between the Si layers 201 and 203 are formed by the metal layer 204. Also, the contact surfaces of the gate electrodes 213 and 214 with the gate insulating film 210 are covered by the high-k material layer 205. And the metal layer 204 is filled inside the high-k material layer 205. The metal layer 204 is continuously formed by the gate electrodes 213 and 214 and the gate electrode 212 (see FIG. 5).

[0033] Also, in the cross-sectional view in the gate width direction shown in FIG. 5, the second semiconductor element 200 has a high-k material layer 205 formed on the substrate 11 and the STI 42. And the second semiconductor element 200 has Si layers 201 and 203 laminated on the high-k material layer 205 via the metal layer 204 constituting the gate electrode 212. The Si layers 201 and 203 are each surrounded by the gate insulating film 210. And the periphery of the gate insulating film 210 is covered by the high-k material layer 205. Therefore, in the cross-sectional view in the gate width direction, the Si layers 201 and 203 are each surrounded by the gate insulating film 210 and the high-k material layer 205. The high-k material layer 205 covers the entire area of the contact surface between the gate insulating film 210 and the metal layer 204.

[0034] Also, as can be seen from FIGS. 4 and 5, in the cross-sectional view in the gate width direction shown in FIG. 5, the metal layer 204 is continuously formed by the gate electrodes 213, 214 and the gate electrode 212. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 5, the Si layers 201, 203 are covered by the gate electrodes 213, 214 and the gate electrode 212 on the periphery. That is, in the second semiconductor element 200, the entire cross-section in the gate length direction of the Si layers 201, 203 that serve as the channel portion is surrounded by the gate electrodes 212, 113, 214 as shown in FIG. 5.

[0035] (Layer structure of the second semiconductor element) The gate electrode 214 of the second semiconductor element 200 is formed at substantially the same height as the Si layer 102 of the first semiconductor element 100 with respect to the upper surface of the substrate 11. In particular, the center in the height direction of the metal layer 204 of the gate electrode 214 and the center in the height direction of the Si layer 102 are located at substantially the same height.

[0036] A Si layer 202 is formed between the gate electrode 214 and the source region 208 and the drain region 209 via a gate insulating film 210. Also, the Si layer 202 is formed on both sides of the gate electrode 214. That is, the second semiconductor element 200 includes a Si layer 202 in contact with the source region 208 and a Si layer 202 in contact with the drain region 209. The Si layer 202 on the source region 208 side and the Si layer 202 on the drain region 209 side are separated.

[0037] In the second semiconductor element 200, the inner spacer 207 is divided into at least two in the stacking direction by the Si layer 202. Therefore, in the region between the Si layer 201 and the Si layer 203 where the gate electrode 214 is formed, the inner spacer 207 is formed divided into two or more in the stacking direction. And the Si layer 202 is interposed between the stacks of this inner spacer 207.

[0038] The Si layer 202 is formed with a thickness in the plane direction of the substrate 11 smaller than that of the inner spacer 207. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3, the Si layer 202 and the inner spacer 207 have a step on the wall surface in the central direction of the second semiconductor element 200. And due to this step, a recess is formed on the side surface side of the Si layer 202. An insulating film 210 is embedded in the recess on the side surface side of the Si layer 202. As a result, the Si layer 202 and the insulating film 210 are disposed between the stacked inner spacers 207. The Si layer 202 is in contact with the insulating film 210, the inner spacer 207, and the source region 208 or the drain region 209.

[0039] Note that the Si layer 202 may have the same thickness as the inner spacer 207, or may have a thickness equal to or less than that of the inner spacer 207. When the Si layer 202 and the inner spacer 207 have the same thickness, the above-mentioned recess is not formed. Therefore, the gate insulating film 210 embedded in the recess also does not exist. And only the Si layer 202 is disposed between the stacked inner spacers 207.

[0040] Also, since the Si layer 202 remains between the stacked inner spacers 207, the source region 208 and the drain region 209 are not exposed. Therefore, in the manufacturing process of the semiconductor device described later, in the process of removing the Si layer 202, the process of removing the SiGe layer, the process of forming the gate electrode, etc., damage to the source region 208 and the drain region 209 can be suppressed.

[0041] In the second semiconductor element 200, the Si layer 202 and the metal layer 204 of the gate electrode 214 are formed at substantially the same height with reference to the upper surface of the substrate 11. In particular, the center in the height direction of the metal layer 204 of the gate electrode 214 and the center in the height direction of the Si layer 202 are located at substantially the same height. Further, the Si layer 202 and the metal layer 204 of the second semiconductor element 200 are formed at substantially the same height with respect to the Si layer 102 of the first semiconductor element 100 and the upper surface of the substrate 11. For this reason, the Si layer 202 is formed at substantially the same height with respect to the upper surface of the substrate 11, the gate electrode 214 of the second semiconductor element 200, and the Si layer 102 of the first semiconductor element 100. In particular, the center in the height direction of the Si layer 202, the center in the height direction of the metal layer 204 of the gate electrode 214, and the center in the height direction of the Si layer 102 are located at substantially the same height.

[0042] The Si layer 201 of the second semiconductor element 200 is formed at substantially the same height with respect to the Si layer 101 of the first semiconductor element 100 and the upper surface of the substrate 11. The Si layer 203 of the second semiconductor element 200 is formed at substantially the same height with respect to the Si layer 103 of the first semiconductor element 100 and the upper surface of the substrate 11.

[0043] Further, the distance between the Si layer 101 and the Si layer 102 of the first semiconductor element 100, and the distance between the Si layer 102 and the Si layer 103 are substantially the same. Similarly, the distance between the Si layer 201 and the Si layer 202 and the metal layer 204 of the second semiconductor element 200, and the distance between the Si layer 202 and the metal layer 204 and the Si layer 203 are substantially the same. In contrast, in the first semiconductor element 100, the distance from the upper surface of the substrate 11 to the Si layer 101 is larger than the distance between the Si layer 101 and the Si layer 102, and the distance between the Si layer 102 and the Si layer 103. Similarly, in the second semiconductor element 200, the distance from the upper surface of the substrate 11 to the Si layer 201 is larger than the distance between the Si layer 201 and the Si layer 202 and the metal layer 204, and the distance between the Si layer 202 and the metal layer 204 and the Si layer 203.

[0044] Therefore, in the second semiconductor element 200, the region where the gate electrode 214 is formed between the Si layer 201 and the Si layer 203 and the gate insulating film 210 is formed is the same as the region where the Si layer 102 and the gate electrodes 114 and 115 are formed in the first semiconductor element 100. For this reason, the gate electrode 214 and the gate insulating film 210 of the second semiconductor element 200 are formed in a sufficiently wider region than the gate electrodes 114 and 115 of the first semiconductor element 100.

[0045] Also, in the first semiconductor element 100 and the second semiconductor element 200, the distance from the upper surface of the substrate 11 to the Si layer 101 and the Si layer 201 is larger than the respective distances between the Si layer 101, the Si layer 102, and the Si layer 103. For this reason, the gate electrode 113 of the first semiconductor element 100 and the gate electrode 213 of the second semiconductor element 200 are formed in a sufficiently wider region than the gate electrodes 114 and 115 of the first semiconductor element 100.

[0046] According to the above configuration, the second semiconductor element 200 has an area secured for forming a gate insulating film with a sufficient thickness that can withstand the high voltage applied to the second semiconductor element 200 serving as an input / output device. With this structure, the second semiconductor element 200 can operate at a voltage higher than that of the first semiconductor element 100 constituting the logic device while having the shape of a GAA-FET. Therefore, a decrease in the reliability of the second semiconductor element 200 can be suppressed.

[0047] In addition, in the first semiconductor element 100 and the second semiconductor element 200, the Si layers 101, 102, 103 and the Si layers 201, 202, 203 are formed at the same height. Therefore, the lamination formation process of the Si layers 101, 102, 103 and the Si layers 201, 202, 203 can be shared between the first semiconductor element 100 and the second semiconductor element 200. As a result, variations in the height of the Si layers 101, 102, 103 and the Si layers 201, 202, 203 can be suppressed. Furthermore, by sharing the lamination formation process of the Si layers 101, 102, 103 and the Si layers 201, 202, 203, complication of the manufacturing process and increase in manufacturing cost can be suppressed.

[0048] 〈2. Method for manufacturing semiconductor device〉 Next, a method for manufacturing the semiconductor device 10 shown in FIGS. 1-5 described above will be explained. Manufacturing process diagrams of the semiconductor device 10 are shown in FIGS. 6-37. In the manufacturing processes of the semiconductor device 10 shown in FIGS. 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, an X1-line cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 is shown on the left side (a) of the drawing, and an X2-line cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200 is shown on the right side (b) of the drawing. In the manufacturing processes of the semiconductor device 10 shown in FIGS. 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, a Y1-line cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 is shown on the left side (a) of the drawing, and a Y2-line cross-sectional view (cross-sectional view in the gate width direction) of the second semiconductor element 200 is shown on the right side (b) of the drawing.

[0049] First, as shown in FIGS. 6 and 7, an SiGe layer 12, an Si layer 13, an SiGe layer 14, and an Si layer 15 are stacked on a substrate 11. The SiGe layers 12 and 14 and the Si layers 13 and 15 are formed by using epitaxial growth of Si and SiGe. The SiGe layer 12 is formed to have a thickness of, for example, about 20 - 30 nm. The SiGe layer 14 is formed to have a thickness of, for example, about 10 - 15 nm. The Si layers 13 and 15 are formed to have a thickness of, for example, about 5 nm. In this way, the bottom SiGe layer 12 is formed thicker than the upper SiGe layer 14. The SiGe layer 12 preferably has a thickness that enables formation of a gate insulating film 210 and a metal layer 204 having sufficient thickness in the second semiconductor element 200 shown in FIG. 4.

[0050] Next, as shown in FIGS. 8 and 9, a resist layer 16 is patterned on the Si layer 15 except for the region where the second semiconductor element 200 is to be formed. For patterning the resist layer 16, for example, after forming the resist layer 16 on the front surface, exposure and development processes are performed using a photomask on which a predetermined pattern is formed. Then, using the resist layer 16 as a mask, high - concentration ion implantation is performed on the Si layer 15 in the region where the second semiconductor element 200 is to be formed. The impurity used for ion implantation is not particularly limited, and impurities such as B, P, As, and Ge can be used regardless of the conductivity type of the second semiconductor element 200. After ion implantation, annealing and surface treatment are performed on the Si layer 15 to recover the crystallinity of the Si layer 15. Thereby, an Si layer 15A into which impurities are implanted is formed in the region where the second semiconductor element 200 is to be formed.

[0051] Next, as shown in FIGS. 10 and 11, an SiGe layer 17 and an Si layer 18 are stacked on the Si layers 15 and 15A. The SiGe layer 17 and the Si layer 18 are formed by using epitaxial growth of Si and SiGe. The SiGe layer 17 is formed to have a thickness of, for example, about 10 - 15 nm. The Si layer 18 is formed to have a thickness of, for example, about 5 nm. Thereby, a laminate composed of the SiGe layer 12, the Si layer 13, the SiGe layer 14, the Si layers 15 and 15A, the SiGe layer 17, and the Si layer 18 is formed.

[0052] Next, the STI is formed on the substrate 11, and the dummy gate insulating film 19, dummy gate 20, hard mask 21, and sidewalls 106 and 206 are formed. Then, the stacked bodies of the SiGe layer 12, Si layer 13, SiGe layer 14, Si layers 15 and 15A, SiGe layer 17, and Si layer 18 are etched using reactive ion etching (RIE) or the like. Thus, as shown in FIGS. 12 and 13, independent Si / SiGe stacked bodies (pillars) are formed in the first semiconductor element 100 and the second semiconductor element 200, respectively. Here, a stacked body of the SiGe layer 12, Si layer 101, SiGe layer 14, Si layer 102, SiGe layer 17, and Si layer 103 is formed in the first semiconductor element 100. Also, a stacked body of the SiGe layer 12, Si layer 201, SiGe layer 14, Si layer 15A, SiGe layer 17, and Si layer 203 is formed in the second semiconductor element 200. Also, inner spacers 107 and 207 are formed on the Si / SiGe stacked body. Then, the STI 42 embedded in the substrate 11 is formed between the region where the first semiconductor element 100 is formed and the region where the second semiconductor element 200 is formed. Then, after forming the insulating layer 41 covering the entire substrate 11, the insulating layer 41 is polished and planarized by CMP or the like to expose and planarize the upper surface of the hard mask 21. Furthermore, source regions 108 and 208, and drain regions 109 and 209 are formed on the side surfaces of the Si / SiGe stacked body. Each of these steps is performed by a conventionally known method. By these processes, on the substrate 11 having the structure shown in FIGS. 12 and 13, an Si / SiGe stacked body, a dummy gate insulating film 19, a dummy gate 20, a hard mask 21, sidewalls 106 and 206, inner spacers 107 and 207, source regions 108 and 208, and drain regions 109 and 209 are formed.

[0053] Next, as shown in FIGS. 14 and 15, the hard mask 21 and the dummy gate 20 are removed. The hard mask 21 is formed of, for example, SiN. Therefore, the hard mask 21 is selectively etched using a chemical such as hydrogen fluoride that can selectively wet-etch SiN with respect to SiO and Si. The dummy gate 20 is formed of, for example, polysilicon (p-Si) or amorphous silicon (α-Si). Therefore, for example, plasma etching or the like that can selectively etch polysilicon (p-Si) or amorphous silicon (α-Si) is used.

[0054] Next, after the entire surface on the substrate 11 is filled with the resist layer 22, as shown in FIGS. 16 and 17, the resist layer 22 is patterned so as to open only the formation region of the second semiconductor element 200. Next, the SiGe layers 12, 14, and 17 of the second semiconductor element 200 shown in FIGS. 16 and 17 are selectively etched. Also, in this step, the dummy gate insulating film 19 is removed. As a result, as shown in FIGS. 18 and 19, the interlayer of the Si layers 201, 15A, and 203 of the second semiconductor element 200 is exposed. The selective etching of the SiGe layers 12, 14, and 17 uses, for example, dry etching with a mixed gas containing hydrogen fluoride and oxygen or wet etching with a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0055] Next, as shown in FIGS. 20 and 21, the Si layer 15A into which impurities have been implanted is selectively removed. In this step, wet etching is performed using tetramethylammonium hydroxide (TMAH), trimethyl-2-hydroxyethylammonium hydroxide (TMY), or the like that can selectively remove the Si layer 15A into which impurities have been implanted with respect to the Si layers 201 and 203. By this step, the Si layer 202 remains at a position that is between the inner spacers 207 and in contact with the source region 208 or the drain region 209. Also, in the step of selectively removing the Si layer 15A, the remaining amount of the Si layer 202 between the inner spacers 207 is adjusted by adjusting the conditions and time. When all of the Si layer 202 is removed, the source region 208 and the drain region 209 are exposed inside the element. In this case, in the step of removing the Si layer 15A, the source region 208 and the drain region 209 are damaged, and the characteristics of the semiconductor element are likely to deteriorate. Also, when the subsequent manufacturing steps are performed with the source region 208 and the drain region 209 exposed, the source region 208 and the drain region 209 are damaged, and the characteristics of the semiconductor element are likely to deteriorate. For this reason, in the step of selectively removing the Si layer 15A, it is preferable to leave at least a part of the Si layer 202 between the inner spacers 207 so that the source region 208 and the drain region 209 are not exposed.

[0056] Next, after removing the resist layer 22, as shown in FIGS. 22 and 23, an insulating layer 23 is formed on the entire surface of the substrate 11. The insulating layer 23 is formed of, for example, SiO2 or the like. For forming the insulating layer 23, for example, CVD or the like is used. The insulating layer 23 is a film that becomes the gate insulating film 201 in the second semiconductor element 200 shown in FIGS. 4 and 5. For this reason, the insulating layer 23 is formed to have a sufficient thickness that can withstand the high voltage applied to the second semiconductor element 200.

[0057] Next, after embedding the entire surface on the substrate 11 with the resist layer 24, as shown in FIGS. 24 and 25, the resist layer 24 is patterned so as to open only the first semiconductor element 100. Then, as shown in FIGS. 26 and 27, the insulating layer 23 of the first semiconductor element 100 is selectively removed. Also, in this step, the dummy gate insulating film 19 is removed. As a result, the Si layer 103 of the first semiconductor element 100 and the inner walls of the sidewalls 106 are exposed.

[0058] Next, the SiGe layers 12, 14, 17 of the first semiconductor element 100 shown in FIGS. 26 and 27 are selectively etched. As a result, as shown in FIGS. 28 and 29, the interfaces between the Si layers 101, 102, 103 of the first semiconductor element 100 are exposed. The selective etching of the SiGe layers 12, 14, 17 uses, for example, dry etching with a mixed gas containing hydrogen fluoride and oxygen, or wet etching with a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0059] Next, as shown in FIGS. 30 and 31, the resist layer 24 is peeled off to expose the second semiconductor element 200. Then, as shown in FIGS. 32 and 33, a high-k dielectric material layer 25 is formed over the entire surface of the substrate 11. The high-k dielectric material layer 25 is formed of, for example, hafnium dioxide (HfO2), hafnium oxynitride (HfON), or the like. For the formation of the high-k dielectric material layer 25, for example, ALD (Atomic Layer Deposition) or the like is used.

[0060] Next, as shown in FIGS. 34 and 35, a metal layer 26 is formed over the high-k dielectric material layer 25. The metal layer 26 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), or the like. The metal layer 26 is formed using, for example, CVD. By this step, in the first semiconductor element 100, gate electrodes 113, 114, 115 (see FIG. 2) made of the metal layer 104 are formed between the substrate 11 and the Si layers 101, 102, 103 via the high-k dielectric material layer 105. Also, in the second semiconductor element 200, gate electrodes 213, 214 (see FIG. 2) made of the metal layer 204 are formed between the substrate 11 and the Si layers 201, 203 via the high-k dielectric material layer 205.

[0061] Next, as shown in FIGS. 36 and 37, the insulating layer 23, the high dielectric constant material layer 25, and the metal layer 26 above the insulating layer 41 are removed. Further, the surfaces of the insulating layer 41, the insulating layer 23, the high dielectric constant material layer 25, and the metal layer 26 are planarized. For the removal of the insulating layer 23, the high dielectric constant material layer 25, and the metal layer 26, for example, CMP is used. Thereby, a gate electrode 112 composed of a high dielectric constant material layer 105 and a metal layer 104 is formed on the first semiconductor element 100. Further, a gate electrode 212 composed of a high dielectric constant material layer and a metal layer 204 is formed on the second semiconductor element 200. Also, in the second semiconductor element 200, the planarized insulating layer 23 becomes an insulating film 210. Through the above steps, the semiconductor device 10 in which the first semiconductor element 100 and the second semiconductor element 200 are formed on the substrate 11 as shown in FIGS. 2-5 can be manufactured.

[0062] In the above-described method for manufacturing the semiconductor device 10, the epitaxial growth of the Si layer and the SiGe layer can be commonly performed for the first semiconductor element 100 and the second semiconductor element 200. Therefore, it becomes easy to control the formation process of the Si / SiGe laminate and the processing process of the Si / SiGe laminate. Further, since there is no large difference in the thickness of the SiGe layer, the film forming property of the insulating layer on the wall surface when forming the inner spacers 107 and 207 is good. Also, after the formation of the source regions 108 and 208 and the drain regions 109 and 209, there is no oxidation process that causes device degradation. Therefore, a decrease in the performance of the semiconductor device can be suppressed.

[0063] [Modification Example of Manufacturing Method] Next, a modification example of the above-described method for manufacturing the semiconductor device 10 will be described. This modification example of the manufacturing method is performed in the same manner as the above-described method for manufacturing the semiconductor device, except that the ion implantation into the Si layer 15 (FIGS. 8 and 9) and the removal of the Si layer 15A into which impurities are implanted (FIGS. 20 and 21) are changed. Therefore, in the following description of the modification example, only the impurity ion implantation process (ion implantation process) into the Si layer 15 and the selective removal process (selective removal process) of the Si layer 15A into which impurities are implanted will be described.

[0064] In a modified example of the manufacturing method, first, in the ion implantation step shown in FIGS. 8 and 9, a mask (not shown) covering the end portion of the Si layer 15 is formed in the region where the second semiconductor element 200 is formed. Then, impurities are implanted only into the central portion of the Si layer 15 to form the Si layer 15A. Here, the end portion of the Si layer 15 is preferably a region having a thickness equal to or less than that of the inner spacer 207 in the second semiconductor element 200. That is, it is preferable to form a mask in the region of the Si layer 202 remaining between the inner spacers 207. In the selective removal step of the Si layer 15A, only the central portion of the Si layer 15A into which impurities are implanted is selectively removed. As a result, the Si layer 202 remains between the inner spacers 207. The Si layer 202 formed by this manufacturing method is formed of Si that does not contain the implanted impurities.

[0065] In the manufacturing method of the semiconductor device 10 described above, the ion implantation step of impurities into the Si layer and the selective removal step of the Si layer into which impurities are implanted are performed on the second layer (intermediate layer) of the three-layer stacked Si layer. However, the Si layer on which the ion implantation step and the selective removal step are performed is not limited to the second layer. For example, in a semiconductor device having two stacked Si layers, the ion implantation step and the selective removal step may be performed on the first Si layer. In a configuration in which four or more Si layers are stacked, the ion implantation and selective removal steps are performed on every other Si layer. That is, the ion implantation and selective removal steps may be performed on the Si layers that are even-numbered layers or odd-numbered layers.

[0066] <3. Second Embodiment of Semiconductor Device> Next, a second embodiment of the semiconductor device will be described. The semiconductor device according to the second embodiment described below has the same configuration as the semiconductor device according to the first embodiment described above. Therefore, the description of the same configuration as that of the semiconductor device according to the first embodiment described above will be omitted.

[0067] [Semiconductor Device of Second Embodiment] FIG. 38 and FIG. 39 show the configuration of the semiconductor device of the second embodiment. FIG. 38 corresponds to the X1-line cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1. Further, FIG. 39 corresponds to the X2-line cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1. In the description of the second embodiment, the configurations of the Y1-line cross-sectional view (cross-sectional view in the gate width direction) and the Y2-line cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 are omitted from illustration. The cross-sectional view in the gate width direction also has a configuration in which the first semiconductor element 100 and the second semiconductor element 200 shown in FIG. 3 or FIG. 5 are stacked, similar to FIGS. 38 and 39.

[0068] In the semiconductor device of the second embodiment, a first semiconductor element 100A shown in FIG. 38 and a second semiconductor element 200A shown in FIG. 39 are formed on a common substrate 11. The first semiconductor element 100A shown in FIG. 38 has a third semiconductor element 100B and a fourth semiconductor element 100C, which have the same configuration as the first semiconductor element 100 shown in FIG. 2 above, stacked on the substrate 11. In the first semiconductor element 100A, the fourth semiconductor element 100C is formed on the third semiconductor element 100B. Further, in the first semiconductor element 100A, an MDI (middle dielectric isolation) 130 is formed on the third semiconductor element 100B. And the fourth semiconductor element 100C is provided on the MDI 130. Note that in the third semiconductor element 100B, an inner spacer 107 is formed as a sidewall of the gate electrode 112. Also, the fourth semiconductor element 100C is formed on the MDI 130, not directly above the substrate 11.

[0069] The second semiconductor element 200A shown in FIG. 39 has a fifth semiconductor element 200B and a sixth semiconductor element 200C, which have the same configuration as the second semiconductor element 200 shown in FIG. 4 above, stacked on the substrate 11. In the second semiconductor element 200A, the sixth semiconductor element 200C is formed on the fifth semiconductor element 200B. Further, in the second semiconductor element 200A, MDI (middle dielectric isolation) 230 is formed on the fifth semiconductor element 200B. And, a sixth semiconductor element 200C is provided on the MDI 230. Note that, in the fifth semiconductor element 200B, an inner spacer 207 is formed as a sidewall of the gate electrode 212. Also, the sixth semiconductor element 200C is formed on the MDI 230 instead of directly above the substrate 11.

[0070] In the semiconductor device of the second embodiment, the third semiconductor element 100B and the fourth semiconductor element 100C of the first semiconductor element 100A may be any combination of PMOS and NMOS, PMOS and PMOS, and NMOS and NMOS. Similarly, the fifth semiconductor element 200B and the sixth semiconductor element 200C of the second semiconductor element 200A may be any combination of PMOS and NMOS, PMOS and PMOS, and NMOS and NMOS.

[0071] The semiconductor device of the second embodiment has the same effects as the semiconductor device of the first embodiment described above. Also, in the semiconductor device of the second embodiment, when epitaxially growing the Si / SiGe stack, SiGe layers with different Ge concentrations are not added. Therefore, it is possible to realize a structure using the SASI (Self-Aligned Substrate Isolation) process to which a manufacturing method that utilizes the difference in the etching rate of SiGe layers due to the difference in Ge concentration is applied, and a monolithic CFET (Monolithic Complementary Field Effect Transistor) using MDI.

[0072] [Manufacturing Method] Next, a manufacturing method of the semiconductor device of the second embodiment will be described. The semiconductor device of the second embodiment can be manufactured by repeating the same steps as the manufacturing method of the semiconductor device of the first embodiment and modified examples of the manufacturing method. Therefore, in the following description, only the main points of the manufacturing method of the semiconductor device of the second embodiment will be described.

[0073] First, the process of performing high-concentration impurity ion implantation on the Si layer 15 will be described with reference to FIG. 40. This process corresponds to the processes shown in FIGS. 8-11 in the manufacturing method of the semiconductor device of the first embodiment described above. First, an SiGe layer 12, an Si layer 13, an SiGe layer 14, and an Si layer 15 are stacked on the substrate 11. Then, except for the region where the second semiconductor element 200A is to be formed, a resist layer 16 is patterned on the Si layer 15. Further, using the resist layer 16 as a mask, high-concentration ion implantation, annealing, and surface treatment are performed on the Si layer 15 in the region where the second semiconductor element 200A is to be formed, to form an Si layer 15A into which impurities are implanted. Next, after peeling off the resist layer 16, an SiGe layer 17 and an Si layer 18 are stacked on the Si layers 15 and 15A. Further, an SiGe layer 30, an MDI 31, an SiGe layer 32, an Si layer 33, an SiGe layer 34, and an Si layer 35 are stacked on the Si layer 18. Then, except for the region where the second semiconductor element 200A is to be formed, a resist layer 36 is patterned on the Si layer 35. Further, using the resist layer 36 as a mask, high-concentration ion implantation, annealing, and surface treatment are performed on the Si layer 35 in the region where the second semiconductor element 200A is to be formed, to form an Si layer 35A into which impurities are implanted. Next, after peeling off the resist layer 36, an SiGe layer 37 and an Si layer 38 are stacked on the Si layers 15 and 15A.

[0074] Next, the process of removing the Si layers 15A and 35A into which impurities are implanted will be described with reference to FIG. 41. This process corresponds to the processes shown in FIGS. 16-21 in the manufacturing method of the semiconductor device of the first embodiment described above. In particular, FIG. 41 corresponds to the processes shown in FIGS. 20 and 21. First, the resist layer 22 is patterned so as to open only the second semiconductor element 200A. Then, the SiGe layers 12, 14, 17, 30, 32, 34, and 37 of the second semiconductor element 200A are selectively etched, to expose the interlayers of the Si layers 201, 202, and 203 of the second semiconductor element 200A. Next, the Si layers 15A and 35A into which impurities are implanted are selectively removed. By this step, the Si layer 202 is left at a position between the inner spacers 207 and in contact with the source region 208 or the drain region 209.

[0075] Except for the steps shown in FIGS. 40 and 41 described above, the semiconductor device of the second embodiment can be manufactured by appropriately applying the steps shown in FIGS. 6-39 in the manufacturing method of the semiconductor device of the first embodiment described above. Also, in the manufacturing method of the semiconductor device of the second embodiment, the same effects as those of the manufacturing method of the semiconductor device of the first embodiment described above can be obtained.

[0076] Note that the present invention is not limited to the configurations described in the above-described embodiment examples, and various modifications and changes can be made without departing from the configuration of the present invention.

Explanation of Reference Numerals

[0077] 10 Semiconductor device, 11 Substrate, 112, 113, 114, 115, 212, 213, 214 Gate electrode, 12, 14, 17, 30, 32, 34, 37 SiGe layer, 13, 15, 15A, 18, 33, 35, 35A, 38, 101, 102, 103, 201, 202, 203 Si layer, 16, 22, 24, 36 Resist layer, 19Dummy gate insulating film, 20Dummy gate, 21Hard mask, 210 Gate insulating film, 23, 41 Insulating layer, 25, 105, 205 High-k dielectric material layer, 26, 104, 204 Metal layer, 31, 130, 230 MDI, 42 STI, 100, 100A First semiconductor element, 100B Third semiconductor element, 100C Fourth semiconductor element, 106, 206, 216 Sidewall, 107, 207 Inner spacer, 108, 208 Source region, 109, 209 Drain region, 200, 200A Second semiconductor element, 200B Fifth semiconductor element, 200C Sixth semiconductor element

Claims

1. A semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, wherein the first semiconductor element includes a first laminate composed of a first Si layer and a first gate electrode covering the periphery of the first Si layer in a cross-section in the gate width direction of the first semiconductor element, a first gate insulating film interposed between the first Si layer and the first gate electrode, a first source / drain region formed on a side surface in the gate length direction of the first laminate, and a first insulating layer formed between the first gate electrode disposed between the layers of the first Si layer and a side surface of the first source / drain region; wherein the second semiconductor element includes a second laminate composed of a second Si layer and a second gate electrode covering the periphery of the second Si layer in a cross-section in the gate width direction of the second semiconductor element, a second gate insulating film interposed between the second Si layer and the second gate electrode and thicker than the first gate insulating film, a second source / drain region formed on a side surface in the gate length direction of the second laminate, and a third Si layer and a second insulating layer formed between the second gate electrode disposed between the layers of the second Si layer and a side surface of the second source / drain region; a semiconductor device.

2. In the second semiconductor element, the second insulating layer is separated in the stacking direction of the second laminate by the third Si layer. The semiconductor device according to Claim 1.

3. In the second semiconductor element, a center in the height direction of the second gate electrode disposed between the layers of the second Si layer with reference to the upper surface of the substrate and a center in the height direction of the third Si layer are formed at the same height. The semiconductor device according to Claim 1.

4. The first semiconductor element includes the first Si layer at the same height as the third Si layer of the second semiconductor element with reference to the upper surface of the substrate. The semiconductor device according to Claim 1.

5. In the second semiconductor element, a distance between the upper surface of the substrate and the lowermost second Si layer is larger than a distance between the lowermost Si layer and the third Si layer. The semiconductor device according to Claim 1.

6. In the first semiconductor element, a distance between the upper surface of the substrate and the lowermost first Si layer is larger than a distance between the lowermost first Si layer and the second first Si layer. The semiconductor device according to Claim 1.

7. The first semiconductor element includes a first Si layer at the same height as the second Si layer of the second semiconductor element with reference to the upper surface of the substrate. The semiconductor device according to claim 1.

8. The third Si layer has a thickness in the plane direction of the substrate that is equal to or less than that of the second insulating layer. The semiconductor device according to claim 1.

9. The first semiconductor element includes a third semiconductor element and a fourth semiconductor element formed on the third semiconductor element. The two semiconductor elements have a structure in which a fifth semiconductor element and a sixth semiconductor element formed on the fifth semiconductor element are stacked. The third semiconductor element and the fourth semiconductor element include the first laminate the first source / drain region and the first insulating layer. In a cross-section in the gate width direction of the first semiconductor element, the first semiconductor element has a first gate electrode that covers the periphery of the first Si layer. The fifth semiconductor element and the sixth semiconductor element include the second laminate the second source / drain region a third Si layer and a second insulating layer. In a cross-section in the gate width direction of the second semiconductor element, the second semiconductor element has a second gate electrode that covers the periphery of the second Si layer. The semiconductor device according to claim 1.

10. A method for manufacturing a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, the method including: forming a Si / SiGe laminate by laminating a Si layer and a SiGe layer in a formation region of the first semiconductor element and a formation region of the second semiconductor element; ion implanting impurities into the Si layer in the formation region of the second semiconductor element; forming an insulating layer on sidewalls of the SiGe layer; removing the SiGe layer in the formation region of the first semiconductor element; forming a first gate electrode via a first gate insulating film in the formation region of the first semiconductor element; removing the SiGe layer in the formation region of the second semiconductor element; removing the Si layer implanted with impurities so that it remains only between the insulating layers; forming a second gate insulating film thicker than the first gate insulating film in the formation region of the second semiconductor element; forming a second gate electrode on the gate insulating film of the second semiconductor element. A method for manufacturing a semiconductor device.

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