Semiconductor device and manufacturing method thereof

Abstract

To prevent a vibration film 10d from being broken by generating a pressure difference between both surfaces of the vibration film 10d in a manufacturing process of a piezoelectric element 40 and to miniaturize the piezoelectric element 40.SOLUTION: A piezoelectric element 40 comprises: a first laminate 10 in which a first vibration film 10d is formed to be able to vibrate in a height direction between a top surface 10b and a first cavity 10c formed on a bottom surface 10a and a slit 10e that communicates between the top surface 10b and the first cavity 10c remaining a fixed-end 10f around the vibration film 10d is formed; and a second semiconductor substrate 31 in which a bottom surface 31a is arranged to face the top surface 10b of the first laminate 10 and surrounds the vibration film 10d in the predetermined height, and a communication groove 31f that communicates between an inner surface 31d and an outer surface 31e facing the vibration film 10d and is opened for the fixed-end 10f in the inner surface 31d is formed on the bottom surface 31a.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Conventionally, a technology of a micro electro mechanical system (MEMS) for fabricating a mechanical structure on a semiconductor substrate such as silicon using semiconductor manufacturing technology has been provided. In a MEMS device to which MEMS technology is applied, for example, there is a piezoelectric element in which a transducer that drives a vibrating membrane with a piezoelectric body and a sub-frame that forms a frame surrounding the vibrating membrane are each formed on a silicon substrate, and these are bonded together so as to be laminated (see Patent Document 1).

[0003] In such a piezoelectric element, a technology has been provided for forming air holes in the sub-frame that communicate the inside and outside of the frame so that a pressure difference does not occur between both surfaces of the vibrating membrane of the transducer during the manufacturing process and the vibrating membrane is not damaged (see Patent Document 2). In addition, a technology has also been provided for miniaturizing the piezoelectric element by removing the frame of the sub-frame at the fixed end of the vibrating membrane and providing an electrode pad at this portion (see Patent Document 3).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

[0005] [Summary] In the manufacturing process of a piezoelectric element, it is required to prevent a pressure difference from occurring between both surfaces of the vibrating membrane of the transducer and to prevent the vibrating membrane from being damaged, and to miniaturize the piezoelectric element.

[0006] The present disclosure is proposed in view of the above circumstances, and aims to provide a semiconductor device and a method for manufacturing the same that prevent a pressure difference from occurring between both sides of a diaphragm of a transducer in a manufacturing process and prevent the diaphragm from being damaged, and enable miniaturization.

[0007] To solve the above problems, a semiconductor device according to the present disclosure includes a first substrate having a first bottom surface and a first top surface, wherein a diaphragm is formed so as to be able to vibrate in the height direction between the first top surface and a recess formed in the first bottom surface, and a slit that communicates the first top surface and the recess is formed around the diaphragm leaving a fixed end. The semiconductor device further includes a second substrate having a second bottom surface and a second top surface, wherein the second bottom surface is disposed to face the first top surface, surrounds the diaphragm at a predetermined height, and a communication groove that communicates an inner surface and an outer surface facing the diaphragm and opens at the fixed end is formed in the second bottom surface.

[0008] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming, in a first substrate having a first bottom surface and a first top surface, a groove that surrounds a predetermined region where a diaphragm is to be formed on the first top surface, leaving a portion that will be a fixed end of the diaphragm; forming air holes penetrating the first substrate at positions away from the predetermined region; forming, in a second substrate having a second bottom surface and a second top surface, a first opening penetrating the second substrate; forming an air groove that includes a circumferential groove surrounding the first opening along the periphery of the first opening in the second bottom surface and a communication groove that communicates the first opening and the circumferential groove to constitute an air passage; attaching the second bottom surface to the first top surface such that a predetermined region of the first top surface is exposed in the first opening, the communication groove opens at the fixed end, and the air groove communicates with the air holes; and forming a recess reaching a predetermined height in the first bottom surface, forming a diaphragm between the first top surface and the recess in the predetermined region, and forming a slit that communicates the groove and the recess leaving a fixed end around the diaphragm.

Brief Description of the Drawings

[0009]

Figure 1A

Figure 1B

Figure 1C

Figure 2

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Figure 11

[0010] [Detailed Description] Hereinafter, the semiconductor device and the method for manufacturing the same according to the present disclosure will be described in detail with reference to the drawings using an example of a piezoelectric element. It goes without saying that the semiconductor device and the method for manufacturing the same according to the present disclosure are not limited to piezoelectric elements and can be applied to other types of semiconductor devices and the methods for manufacturing the same.

[0011] The embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, installation positions of the components, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Among the components in the following embodiments, the components not described in the independent claims indicating the most basic concept are described as optional components. Furthermore, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may be different from the actual ratios. In addition, the following embodiments and their modified examples may include similar components. The same reference numerals are given to the similar components, and redundant descriptions are omitted.

[0012] (Piezoelectric Element) Figures 1A to 1C are three views of the piezoelectric element 40 of the present embodiment. Figure 1A is a plan view, Figure 1B is a front view, and Figure 1C is a left side view. Figure 2 is a cross-sectional view showing a cross-section of the piezoelectric element 40 shown in the plan view of Figure 1A cut along the cutting line II-II in the figure. The piezoelectric element 40 of the present embodiment is a MEMS using semiconductor manufacturing technology, and the top surface 10b of the first laminate 10 including the first semiconductor substrate 11 and the bottom surface 31a of the second semiconductor substrate 31 are bonded together by an adhesive layer 45. In the piezoelectric element 40, the first laminate 10 constitutes a transducer, and the second semiconductor substrate 31 constitutes a subframe.

[0013] The first laminate 10 is configured by laminating, in order, a first semiconductor substrate 11, a first insulating layer 12, a semiconductor layer 13, a second insulating layer 14, a first protective layer 15, a first metal layer 17, a piezoelectric layer 18, a second metal layer 19, and a second protective layer 16. On the bottom surface 10a of the first laminate 10, a first cavity 10c, which is a recess reaching the semiconductor layer 13, is formed so as to form a diaphragm 10d that vibrates in the height direction from the bottom surface 10a toward the top surface 10b in the semiconductor layer 13. On the top surface 10b of the first laminate 10, a slit 10e reaching the first cavity 10c is formed around the diaphragm 10d leaving a fixed end so that the diaphragm 10d forms a rectangular cantilever structure in plan view. The first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 laminated on the semiconductor layer 13 forming the diaphragm 10d constitute a drive layer that vibrates the diaphragm 10d according to the applied voltage. The first metal layer 17 and the second metal layer 19 are each connected to a pair of electrode pads 22 formed on the second protective layer 16 through wiring.

[0014] In the first laminate 10, the first semiconductor substrate 11 may be made of silicon (Si). The first insulating layer 12 may be made of silicon dioxide (SiO2). The second insulating layer 14 may have aluminum oxide (Al2O3) and SiO2 laminated in this order. The first metal layer 17 may have titanium dioxide (TiO2) and platinum (Pt) laminated in this order. TiO2 is interposed between the upper Pt and the lower second insulating layer 14 and adhered thereto. The piezoelectric layer 18 may be made of lead zirconate titanate (PZT). The second metal layer 19 may have iridium oxide (IrO2) and iridium (Ir) laminated in this order. The first protective layer 15 and the second protective layer 16 may have Al2O3 and SiO2 laminated in this order. Here, SiO2 serves as an interlayer insulating film, and Al2O3 serves as a hydrogen barrier film. Note that the first semiconductor substrate 11, the first insulating layer 12, and the semiconductor layer 13 may form a silicon on insulator (SOI) wafer, and the semiconductor layer 13 may form a buried oxide (BOX) layer.

[0015] The second semiconductor substrate 31 has a frame shape surrounding the diaphragm 10d at a predetermined height, and a second cavity 31c is formed above the diaphragm 10d by an opening penetrating the second semiconductor substrate 31. On the bottom surface 31a of the second semiconductor substrate 31, a communication groove 31f is formed that connects the inner surface 31d of the second cavity 31c facing the diaphragm 10d and the outer surface 31e of the second semiconductor substrate 31 and opens at the fixed end 10f of the diaphragm 10d on the top surface 10b of the first laminate 10. Further, a notch 31g having a predetermined height from the bottom surface 31a and a predetermined depth from the outer surface 31e is formed so as to go around the second semiconductor substrate 31 along the outer surface 31e of the second semiconductor substrate 31. The notch 31g is connected to the communication groove 31f opening to the outer surface 31e.

[0016] On the outer surface 31e of the second semiconductor substrate 31, a pair of notches 31h are formed so that the electrode pads 22 formed in the second protective layer 16 of the first laminate 10 are exposed. The notches 31h are formed by notching ridges extending in the height direction on the outer surface 31e of the second semiconductor substrate 31 so that the electrode pads 22 formed at the positions of the corners facing each other with the communication groove 31f interposed therebetween in the first laminate 10 having a rectangular shape in plan view are exposed.

[0017] The outer surface 31e of the second semiconductor substrate 31 constitutes the outer surface 40a of the piezoelectric element 40 together with the outer surface 10g of the first laminate 10. The communication groove 31f constitutes a communication hole 40b that communicates the second cavity 31c and the outer surface 40a. The notch 31g constitutes a circumferential groove 40c that encircles the outer surface 40a of the piezoelectric element 40 along the side wall. The bottom surface 31a of the second semiconductor substrate 31 is bonded by an adhesive layer 45 interposed between the bottom surface 31a and the top surface 10b of the first laminate 10. The second semiconductor substrate 31 may be made of Si.

[0018] In the piezoelectric element 40 of the present embodiment, the second cavity 31c surrounded by the inner surface 31d of the second semiconductor substrate 31 and facing the vibration film 10d communicates with the outer surface 40a of the piezoelectric element 40 through the communication hole 40b. The communication hole 40b serves as an air passage, and the pressure in the second cavity 31c is maintained at the external air pressure even when the temperature of the piezoelectric element 40 rises during the manufacturing process. Therefore, damage to the vibration film 10d is prevented due to the pressure difference between the pressure in the second cavity 31c applied to one surface of the vibration film 10d and the external air pressure applied to the other surface.

[0019] Further, since the communication hole 40b is provided at the fixed end 10f of the vibration film 10d, the influence of air leakage due to the vibration of the vibration film 10d can be suppressed to a small level. Therefore, it is possible to reduce the loss of the vibration energy of the vibration film 10d by providing the communication hole 40b.

[0020] In the piezoelectric element 40 of the present embodiment, the vibrating membrane 10d forms a cantilever beam, but the present disclosure is not limited to this. For example, like a double-cantilever beam, it may have a slit 10e that surrounds the vibrating membrane 10d leaving a fixed end 10f, and the communication hole 40b may open to the fixed end 10f of the vibrating membrane 10d on the inner surface 31d of the second semiconductor substrate 31 facing the vibrating membrane 10d.

[0021] (Modification example) Figs. 3A to 3C are three views of the piezoelectric element 41 of the modification example. Fig. 3A is a plan view, Fig. 3B is a front view, and Fig. 3C is a left side view. Fig. 4 is a cross-sectional view showing a cross-section of the piezoelectric element 41 shown in the plan view of Fig. 3A cut along the cutting line IV-IV in the figure. The piezoelectric element 41 of the modification example is different from the piezoelectric element 40 of the present embodiment in that the depth of the communication groove 31f formed on the bottom surface 31a of the second semiconductor substrate 31 reaches the top surface 31b and the upper part of the communication hole 40b is opened, and the electrode pad 22 is formed on the second protective layer 16 exposed in the communication hole 40b, and a notch 31h is provided at the edge of the outer surface 31e of the second semiconductor substrate 31 to expose the electrode pad 22. Since other configurations are the same as those of the piezoelectric element 40 of the present embodiment, corresponding components are given common reference numerals to clarify the correspondence.

[0022] In the piezoelectric element 41 of the modification example, the upper part of the communication groove 31f is opened, and a communication part 40d that communicates the second cavity 31c of the piezoelectric element 41 and the outer surface 40a is formed. Since the electrode pad 22 can be provided on the second protective layer 16 exposed in the communication part 40d, it is not necessary to provide a notch 31h on the outer surface 40a to expose the electrode pad 22 as in the piezoelectric element 40 shown in Figs. 1A to 1C, and the width of the frame can be narrowed in the second semiconductor substrate 31 having a frame shape. By narrowing the width of the frame, the area of the vibrating membrane 10d will relatively increase, and the top surface 10b of the first laminate 10 can be effectively utilized as the vibrating membrane 10d.

[0023] (Manufacturing method) Next, a method for manufacturing the piezoelectric element 40 according to the present embodiment will be described. First, a process for manufacturing a first laminate 10 that will constitute a transducer will be described with reference to FIGS. 5A to 5G. As shown in FIG. 5A, a third insulating layer 27 is laminated on the bottom surface of the first semiconductor substrate 11, and a first insulating layer 12, a semiconductor layer 13, a second insulating layer 14, a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19 are laminated in order on the top surface to form the first laminate 10. For the laminate composed of the third insulating layer 27, the first semiconductor substrate 11, the first insulating layer 12, and the semiconductor layer 13, an SOI wafer may be used. In the SOI wafer, the semiconductor layer 13 may form a BOX layer.

[0024] As shown in FIG. 5B, unnecessary portions are removed by etching so that the first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 laminated in order on the second insulating layer 14 are formed in appropriate shapes. As shown in FIG. 5C, a first protective layer 15 is formed to cover the second insulating layer 14 on which the first metal layer 17, the piezoelectric layer 18, and the second metal layer 19 processed into appropriate shapes by etching are laminated. As shown in FIG. 5D, a first opening 15a is formed in the first protective layer 15 so that electrodes can be connected to the first metal layer 17 and the second metal layer 19, respectively. Further, in the first protective layer 15, a second opening 15b is formed at a position where a slit 10e is formed in the first laminate 10, and a third opening 15c is formed at a position where an air hole penetrating the first semiconductor substrate 11 is formed.

[0025] As shown in FIG. 5E, an electrode 21 and a wiring (not shown) connected to the electrode 21 are formed. The electrode 21 and the wiring may be laminated with an aluminum (Al) - copper (Cu) alloy and titanium nitride (TiN). TiN is a barrier metal. As shown in FIG. 5F, after covering the first protective layer 15 in which the electrode 21, the second opening 15b, and the third opening 15c are formed with a second protective layer 16, the second protective layer 16 covering the second opening 15b and the third opening 15c is removed by etching.

[0026] As shown in FIG. 5G, the second opening 15b and the third opening 15c are dug down to reach the top surface of the first semiconductor substrate 11 by etching, and a groove 46 surrounding the diaphragm 10d is formed leaving the fixed end 10f, and the first laminate 10 is obtained by forming air holes 47 serving as air passages. A third insulating layer 27 is further laminated on the bottom surface 10a of the first laminate 10.

[0027] FIG. 6 is a plan view of the first laminate 10 formed in the process from FIG. 5A to FIG. 5E. The process diagram of FIG. 5G corresponds to a cross section cut along the cutting line VG-VG in FIG. 6. A groove 46 surrounding the diaphragm 10d is formed on the top surface 10b of the first laminate 10 shown in FIG. 6, leaving the fixed end 10f. The first metal layer 17 and the second metal layer 19 (not shown) of the driving layer for driving the diaphragm 10d are connected to the electrode pads 22 via wirings 23, respectively. Air holes 47 are formed at positions away from the diaphragm 10d on the top surface 10b.

[0028] A process of processing the second semiconductor substrate 31 that will constitute the sub-frame using FIGS. 7A to 7F will be described. As shown in FIG. 7A, a fourth insulating layer 32 and a fifth insulating layer 33 are laminated on the bottom surface 31a and the top surface 31b of the second semiconductor substrate 31. The second semiconductor substrate 31 may be made of Si, and the fourth insulating layer 32 and the fifth insulating layer 33 may be made of SiO2. In this case, the SiO2 of the fourth insulating layer 32 and the fifth insulating layer 33 may be formed by oxidizing the surface of the second semiconductor substrate 31 made of Si.

[0029] As shown in FIG. 7B, openings 35 are formed in the fourth insulating layer 32 and the fifth insulating layer 33. The openings 35 are formed at positions for forming a separation groove penetrating the second semiconductor substrate 31 to cut off an unnecessary portion of the second semiconductor substrate 31, positions for forming a communication groove 31f, a notch 31g, and an air groove, respectively.

[0030] As shown in FIG. 7C, a support substrate 51 is attached onto the fifth insulating layer 33 laminated on the top surface 31b of the second semiconductor substrate 31 with an adhesive layer 52 such as a tape interposed therebetween. Then, a mask 53 is laminated on the fourth insulating layer 32 laminated on the bottom surface 31a of the second semiconductor substrate 31 and etched so as to expose an opening 35 corresponding to a separation groove penetrating the second semiconductor substrate 31. By etching, a separation groove 36 is formed which penetrates the second semiconductor substrate 31 from the opening of the mask 53 and reaches the adhesive layer 52.

[0031] As shown in FIG. 7D, the mask 53 laminated on the fourth insulating layer 32 is removed, and the portion from the opening 35 covered by the mask 53 where the separation groove 36 was not formed to a predetermined height is removed by etching to form a communication groove 31f, a notch 31g, and an air groove 37. As shown in FIG. 7E, after removing the support substrate 51 leaving the adhesive layer 52, the portion separated from the second semiconductor substrate 31 by the separation groove 36 is removed together with the adhesive layer 52. Further, the fourth insulating layer 32 and the fifth insulating layer 33 are also removed. As shown in FIG. 7F, a second cavity 31c is formed in the second semiconductor substrate 31. Also, a communication groove 31f, a notch 31g, and an air groove 37 are formed in the bottom surface 31a of the second semiconductor substrate 31.

[0032] FIG. 8 is a bottom view of the second semiconductor substrate 31 processed in the steps from FIGS. 7A to 7F. The process diagram of FIG. 7F corresponds to a cross section cut along the cutting line VIIF-VIIF in FIG. 8. A frame-shaped shape surrounding the second cavity 31c is formed in the bottom surface 31a of the second semiconductor substrate 31 shown in FIG. 8, and notches 31h are also formed at the corners of the frame. The notches 31h are formed simultaneously with the second cavity 31c. Also, a communication groove 31f, a notch 31g, and an air groove 37 communicating with the second cavity 31c extend in the bottom surface 31a.

[0033] A process for manufacturing a second laminate 60 including a piezoelectric element 40 of the present embodiment composed of a first laminate 10 and a second semiconductor substrate 31 will be described with reference to FIGS. 9A to 9D. As shown in FIG. 9A, the first laminate 10 shown in FIG. 5G and the second semiconductor substrate 31 shown in FIG. 7F are bonded together to form the second laminate 60. Specifically, the top surface 10b of the first laminate 10 shown in FIG. 5G and the bottom surface 31a of the second semiconductor substrate 31 shown in FIG. 7F are bonded together with an adhesive layer 45 interposed therebetween so that they face each other. Further, a support substrate 56 is attached to the top surface of the second semiconductor substrate 31 with an adhesive layer 55 interposed therebetween.

[0034] The groove 46 of the first laminate 10 and the inner surface 31d of the second cavity 31c of the second semiconductor substrate 31 are formed so as to be aligned with each other within the plane where the top surface 10b of the first laminate 10 and the bottom surface 31a of the second semiconductor substrate 31 are bonded together. Also, the air holes 47 of the first laminate 10 and the air grooves 37 of the second semiconductor substrate 31 are formed so as to communicate with each other.

[0035] As shown in FIG. 9B, a part of the third insulating layer 27 and the first semiconductor substrate 11 is removed from the bottom surface 10a of the first laminate 10 by grinding and polishing so that the first semiconductor substrate 11 has a predetermined thickness. Thereafter, the bottom surface of the first semiconductor substrate 11 is etched so that the air holes 47 formed from the bottom surface of the second protective layer 16 to the top surface of the first semiconductor substrate 11 extend through the first semiconductor substrate 11. As a result, the communication groove 31f, the air groove 37, and the air holes 47 constitute an air passage 65 that communicates the second cavity 31c with the bottom surface of the first semiconductor substrate 11.

[0036] As shown in FIG. 9C, the first semiconductor substrate 11 and the first insulating layer 12 in the portion directly below the diaphragm 10d in the first laminate 10 are removed by dry etching to form a first cavity 10c between the bottom surface 10a of the first laminate 10 and the diaphragm 10d. The first cavity 10c communicates with the groove 46, and a slit 10e is formed that surrounds the diaphragm 10d leaving the fixed end 10f.

[0037] As shown in FIG. 9D, when the support substrate 56 and the adhesive layer 55 are removed, the second laminate 60 is obtained. The second laminate 60 includes the piezoelectric element 40, and the piezoelectric element 40 communicates with the bottom surface of the second laminate 60 through the air passage 65.

[0038] FIG. 10 is a plan view of the second laminate 60. The second laminate 60 shown in FIG. 10 is manufactured by the process shown in FIGS. 9A to 9D. Along the main surface 63 of the second laminate 60, four piezoelectric elements 40 having a rectangular outer surface 40a in plan view are formed in two rows and two columns such that their long sides are adjacent to each other.

[0039] In the piezoelectric element 40, a communication groove 31f is formed toward one short side, and a notch 31h and an electrode pad 22 are formed at opposite corners sandwiching the communication groove 31f along the short side. The air groove 37 and the air hole 47, and the communication groove 31f and the notch 31g of each piezoelectric element 40 constitute an air passage 65 that communicates the second cavity 31c of the piezoelectric element 40 with the bottom surface of the second laminate 60.

[0040] Piezoelectric elements 40 obtained by dicing the piezoelectric elements 40 included in the second laminate 60 along a scribe line 62 along the outer surface 40a where the peripheral groove 40c or the peripheral groove 40c is formed can be obtained. For dicing, a wire saw may be used, or a method also called stealth dicing in which a region modified by condensing a laser beam is cut may be used.

[0041] In the method for manufacturing the piezoelectric element 40 of the present embodiment, in the step of removing the portion directly below the vibration film 10d as shown in FIG. 9C by dry etching, the second laminate 60 and the support substrate 56 are heated. Although the second cavity 31c above the vibration film 10d is surrounded by the vibration film 10d, the second semiconductor substrate 31, and the support substrate 56, as shown in FIG. 10, the second cavity 31c communicates with the bottom surface of the first semiconductor substrate 11 through the air passage 65. Therefore, even when the second laminate 60 and the support substrate 56 are heated by dry etching, the pressure in the second cavity 31c is maintained at the external atmospheric pressure, and damage to the vibration film 10d due to the pressure difference between the pressure in the second cavity 31c applied to one surface and the external atmospheric pressure applied to the other surface is prevented.

[0042] In addition, since the communication hole 40b that connects the second cavity 31c of the piezoelectric element 40 to the outer surface 40a opens at the fixed end 10f of the vibration film 10d on the inner surface 31d of the second semiconductor substrate 31 facing the vibration film 10d, the influence of air leakage due to the vibration of the vibration film 10d is suppressed to a small level.

[0043] (Modification example) FIG. 11 is a plan view of the second laminate 61 including the piezoelectric element 41 of the modification example. As described above, the piezoelectric element 41 of the modification example has the same configuration as the piezoelectric element 40 shown in FIGS. 1A to 1C except that the electrode pad 22 is formed on the second protective layer 16 that is open at the top and exposed in the communication portion 40d. The process for manufacturing the piezoelectric element 41 of the modification example is the same as the process for manufacturing the piezoelectric element 40 of the present embodiment except for the step of forming the communication portion 40d and the like. Therefore, also in FIG. 13, the components corresponding to the second laminate 60 including the piezoelectric element 40 of the present embodiment shown in FIG. 12 are denoted by common reference numerals to clarify the correspondence.

[0044] In FIG. 11, since the electrode pad 22 can be provided on the second protective layer 16 exposed in the communication portion 40d, in the second semiconductor substrate 31 having a frame-like shape surrounding the diaphragm 10d, the width of the frame can be reduced. By reducing the width of the frame, the area of the diaphragm 10d will relatively increase. Therefore, the main surface of the piezoelectric element 41 can be effectively utilized as the diaphragm 10d, and the range of the main surface 63 of the second laminate 61 can also be effectively utilized.

[0045] As described above, the present disclosure has been described in detail. However, it is obvious to those skilled in the art that the present disclosure is not limited to the embodiments described in the present disclosure. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented as a modified and changed aspect without departing from the spirit and scope of the present disclosure defined by the description of the claims. Therefore, the description of the present disclosure is for illustrative purposes and has no restrictive meaning for the present disclosure.

[0046] (Appendix 1) The piezoelectric element 40 includes a first laminate 10 in which a diaphragm 10d is formed so as to be able to vibrate in the height direction between the first cavity 10c formed on the top surface 10b and the bottom surface 10a, and a slit 10e is formed around the diaphragm 10d to communicate the top surface 10b and the first cavity 10c leaving a fixed end 10f; and a second semiconductor substrate 31 arranged such that the bottom surface 31a faces the top surface 10b of the first laminate 10, surrounds the diaphragm 10d at a predetermined height, and on the bottom surface 31a, a communication groove 31f is formed to communicate the inner surface 31d and the outer surface 31e facing the diaphragm 10d, and the communication groove 31f opens to the fixed end 10f on the inner surface 31d.

[0047] The communication groove 31f communicates the inner surface 31d and the outer surface 31e of the second semiconductor substrate 31, and can prevent the diaphragm 10d from being damaged due to a pressure difference generated between both surfaces of the diaphragm 10d in the process of manufacturing the piezoelectric element 40. Further, since the communication groove 31f is provided at the fixed end 10f of the diaphragm 10d, the influence of air leakage can be suppressed to a small level.

[0048] (Appendix 2) In the piezoelectric element 40 described in Appendix 1, a notch 31g having a predetermined height along the periphery of the outer surface 31e and a predetermined depth from the outer surface 31e is formed in the second semiconductor substrate 31. The notch 31g can form an air passage.

[0049] (Appendix 3) In the piezoelectric element 40 described in claim 2, the notch 31g communicates with a communication groove 31f that opens to the outer surface 31e. The notch 31g can form an air passage communicating with the communication groove 31f.

[0050] (Appendix 4) In the piezoelectric element 40 described in any one of Appendices 1 to 3, a drive layer for driving the diaphragm 10d in accordance with the applied voltage is laminated on the diaphragm 10d. The drive layer can drive the diaphragm 10d to vibrate in accordance with the applied voltage.

[0051] (Appendix 5) In the piezoelectric element 40 described in Appendix 4, the communication groove 31f has a predetermined height that does not reach from the bottom surface 31a to the top surface 31b in the height direction. The upper part of the communication groove 31f is covered by the second semiconductor substrate 31.

[0052] (Appendix 6) In the piezoelectric element 40 described in Appendix 5, an electrode pad 22 electrically connected to the drive layer is disposed on the top surface 10b of the second semiconductor substrate 31, and a notch 31h is formed in the outer surface 31e of the second semiconductor substrate 31 so that the electrode pad 22 is exposed. The notch 31h secures a range for disposing the electrode pad 22 on the top surface 10b of the second semiconductor substrate 31.

[0053] (Appendix 7) In the piezoelectric element 40 described in Appendix 4, the communication groove 31f reaches from the bottom surface 31a to the top surface 31b in the height direction, and the top surface 10b of the first laminate 10 is exposed in the communication groove 31f. The upper part of the communication groove 31f is open.

[0054] (Appendix 8) In the piezoelectric element 40 described in Appendix 7, an electrode pad 22 electrically connected to the drive layer is disposed on the top surface 10b of the first laminate 10 within the communication groove 31f. The upper part of the communication groove 31f is open, and the electrode pad 22 disposed on the top surface 31b of the first laminate 10 within the communication groove 31f is exposed.

[0055] (Appendix 9) In the piezoelectric element 40 according to any one of Appendices 1 to 8, the diaphragm 10d constitutes a cantilever beam having a fixed end 10f. The diaphragm 10d is surrounded by a slit 10e leaving the fixed end 10f.

[0056] (Appendix 10) The method for manufacturing the piezoelectric element 40 includes, in the first laminate 10 having a bottom surface 10a and a top surface 10b, a step of forming a groove 46 that surrounds the periphery of a predetermined region where the diaphragm 10d is formed on the top surface 10b, leaving a portion that will become the fixed end 10f of the diaphragm 10d; a step of forming air holes 47 penetrating the first laminate 10 at positions away from the predetermined region; a step of forming a second cavity 31c penetrating the second semiconductor substrate 31 in the second semiconductor substrate 31 having a bottom surface 31a and a top surface 31b; a step of forming an air groove 37 that includes a peripheral groove 40c surrounding the second cavity 31c along the periphery of the second cavity 31c on the bottom surface 31a of the second semiconductor substrate 31 and a communication groove 31f that communicates the second cavity 31c and the peripheral groove 40c to constitute an air passage; a step of attaching the bottom surface 31a of the second semiconductor substrate 31 to the top surface 10b of the first laminate 10 such that a predetermined region of the top surface 10b of the first laminate 10 is exposed in the second cavity 31c, the communication groove 31f opens at the fixed end 10f on the top surface 10b of the first laminate 10, and the air groove 37 communicates with the air holes 47; and a step of forming a first cavity 10c reaching a predetermined height on the bottom surface 10a of the first laminate 10 such that the diaphragm 10d is formed between the top surface 10b of the first laminate 10 and the first cavity 10c in the predetermined region, and a slit 10e that communicates the groove 46 and the first cavity 10c is formed around the diaphragm 10d leaving the fixed end 10f.

[0057] The air groove 37 and the air holes 47 communicate the second cavity 31c of the second semiconductor substrate 31 with the bottom surface of the first laminate 10, and a pressure difference is generated between both surfaces of the diaphragm 10d in the process of manufacturing the piezoelectric element 40, thereby preventing the diaphragm 10d from being damaged. Further, since the communication groove 31f is provided at the fixed end 10f of the diaphragm 10d, the influence of air leakage can be suppressed to a small extent.

[0058] (Appendix 11) The method for manufacturing the piezoelectric element 40 according to Appendix 10 further includes a step of attaching the support substrate 56 to the top surface 31b of the second semiconductor substrate 31 before the step of forming the first cavity 10c in the bottom surface 10a of the first laminate 10, and a step of removing the support substrate 56 attached to the top surface 31b of the second semiconductor substrate 31 after the step of forming the first cavity 10c in the bottom surface 10a of the first laminate 10. In the step of forming the first cavity 10c, a space surrounded by the second semiconductor substrate 31 and the support substrate 56 is formed above a predetermined region of the top surface 10b of the first laminate 10. The support substrate 56 can support the first laminate 10 and the second semiconductor substrate 31 during the step of forming the first cavity 10c.

[0059] (Appendix 12) The method for manufacturing the piezoelectric element 40 according to Appendix 10 or 11 further includes a step of forming a driving layer for driving the diaphragm 10d in a predetermined region of the top surface 10b of the first laminate 10, and a step of forming an electrode pad 22 electrically connected to the driving layer at a position away from the predetermined region of the top surface 10b of the first laminate 10. In the step of forming the second cavity 31c in the second semiconductor substrate 31, a notch 31h penetrating the second semiconductor substrate 31 or a communication groove 31f with an open upper portion is also formed. In the step of attaching the bottom surface 31a of the second semiconductor substrate 31 to the top surface 10b of the first laminate 10, the electrode pad 22 is exposed in the notch 31h or the communication groove 31f with an open upper portion. The electrode pad 22 disposed on the top surface 10b of the first laminate 10 can be reached from above.

[0060] (Appendix 13) In the method for manufacturing the piezoelectric element 40 described in Supplementary Note 12, the electrode pad 22 is formed on the top surface 10b of the first laminate 10 so as to be located inside the peripheral groove 40c formed on the bottom surface 31a of the second semiconductor substrate 31 when the bottom surface 31a of the second semiconductor substrate 31 is attached to the top surface 10b of the first laminate 10. Since the piezoelectric element 40 is divided by the scribe line 62 along the peripheral groove 40c, the electrode pad 22 that is electrically connected to the drive layer of each piezoelectric element 40 is secured.

[0061] (Supplementary Note 14) In the method for manufacturing the piezoelectric element 40 described in Supplementary Note 13, the electrode pad 22 is formed on the top surface 10b of the first laminate 10 so as to be located inside the communication groove 31f formed on the bottom surface 31a of the second semiconductor substrate 31 when the bottom surface 31a of the second semiconductor substrate 31 is attached to the top surface 10b of the first laminate 10. The communication groove 31f that is open at the upper part of the second semiconductor substrate 31 is connected to the second cavity 31c to constitute a single opening. Since the electrode pad 22 is provided on the top surface 10b of the first laminate 10 that is exposed inside the communication groove 31f with an open upper part, the width of the frame of the second semiconductor substrate having a frame shape can be narrowed, and the top surface 10b of the first laminate 10 can be effectively utilized as the vibrating membrane 10d.

[0062] (Supplementary Note 15) The method for manufacturing the piezoelectric element 40 according to any one of Supplementary Notes 10 to 14 further includes a step of separating and individualizing the portions surrounded by the peripheral groove 40c in the first laminate 10 and the second semiconductor substrate 31 after the step of forming the first cavity 10c on the bottom surface 10a of the first laminate 10. By separating the piezoelectric elements 40 included in the first laminate 10 and the second semiconductor substrate 31, individual piezoelectric elements 40 are obtained.

Explanation of Reference Numerals

[0063] 10 First laminate 10a Bottom surface of the first laminate 10b Top surface of the first laminate 10c First cavity 10d Vibrating membrane 10e Slit 10f Fixed end 11 First semiconductor substrate 12 First insulating layer 13 Semiconductor layer 14 Second insulating layer 15 First protective layer 16 Second protective layer 17 First metal layer 18 Piezoelectric layer 19 Second metal layer 21 Electrode 22 Electrode pad 23 Wiring 31 Second semiconductor substrate 31a Bottom surface of the second semiconductor layer 31b Top surface of the second semiconductor layer 31c Second cavity 31d Inner surface 31e Outer surface 31f Communication groove 31g Notch

Claims

1. A first substrate having a first bottom surface and a first top surface, wherein a diaphragm is formed between the first top surface and a recess formed in the first bottom surface so as to be able to vibrate in the height direction, and a slit that communicates the first top surface and the recess is formed around the diaphragm leaving a fixed end. A first substrate, A second substrate having a second bottom surface and a second top surface, wherein the second bottom surface is arranged to face the first top surface, surrounds the diaphragm at a predetermined height, and on the second bottom surface, an inner surface facing the diaphragm and an outer surface communicate with each other, and a communication groove that opens to the fixed end on the inner surface is formed. A second substrate A semiconductor device including the above.

2. The semiconductor device according to claim 1, wherein a notch having a predetermined height from the second bottom surface and a predetermined depth from the outer surface is formed along the periphery of the outer surface on the second substrate.

3. The semiconductor device according to claim 2, wherein the notch communicates with the communication groove that opens to the outer surface.

4. The semiconductor device according to any one of claims 1 to 3, wherein a driving layer that drives the diaphragm according to an applied voltage is laminated on the diaphragm.

5. The semiconductor device according to claim 4, wherein the communication groove has a predetermined height that does not reach from the second bottom surface to the second top surface in the height direction.

6. The semiconductor device according to claim 5, wherein an electrode pad electrically connected to the driving layer is arranged on the first top surface, and a notch is formed on the outer surface of the second substrate so that the electrode pad is exposed.

7. The semiconductor device according to claim 5, wherein the communication groove reaches from the second bottom surface to the second top surface in the height direction, and the first top surface is exposed in the communication groove.

8. The semiconductor device according to claim 7, wherein an electrode pad electrically connected to the driving layer is arranged on the first top surface in the communication groove.

9. The semiconductor device according to claim 1, wherein the diaphragm constitutes a cantilever beam having the fixed end.

10. In a first substrate having a first bottom surface and a first top surface, a step of forming a groove that surrounds a predetermined region where a diaphragm is formed on the first top surface, leaving a portion that becomes the fixed end of the diaphragm; A step of forming air holes penetrating the first substrate at positions away from the predetermined region; In a second substrate having a second bottom surface and a second top surface, a step of forming a first opening penetrating the second substrate; Forming an air groove that forms an air passage including a circumferential groove that surrounds the first opening along the circumference of the first opening on the second bottom surface and a communication groove that communicates the first opening and the circumferential groove; Attaching the second bottom surface to the first top surface such that the predetermined region of the first top surface is exposed in the first opening, the communication groove opens at the fixed end, and the air groove communicates with the air hole; Forming a recess reaching a predetermined height on the first bottom surface, forming a diaphragm between the first top surface and the recess in the predetermined region, and forming a slit that communicates the groove and the recess while leaving a fixed end around the diaphragm; A method of manufacturing a semiconductor device including the above steps.

11. Before the step of forming the recess on the first bottom surface, attaching a support substrate to the second top surface; After the step of forming the recess on the first bottom surface, removing the support substrate attached to the second top surface; Further including the above steps, and in the step of forming the recess, a space surrounded by the second substrate and the support substrate is formed above the predetermined region of the first top surface. The method of manufacturing a semiconductor device according to claim 10.

12. Forming a driving layer that drives the diaphragm in the predetermined region of the first top surface; Forming an electrode pad electrically connected to the driving layer at a position away from the predetermined region of the first top surface; Further including the above steps; In the step of forming the first opening in the second substrate, a second opening penetrating the second substrate is also formed, and in the step of attaching the second bottom surface to the first top surface, the electrode pad is exposed in the second opening. The method of manufacturing a semiconductor device according to claim 10.

13. The electrode pad is formed on the first top surface so as to be located inside the circumferential groove formed on the second bottom surface when the second bottom surface is attached to the first top surface. The method of manufacturing a semiconductor device according to claim 12.

14. The electrode pad is formed on the first top surface so as to be located in the communication groove formed on the second bottom surface when the second bottom surface is attached to the first top surface. The second opening overlaps the communication groove and connects to the first opening to form a single opening. The method of manufacturing a semiconductor device according to claim 13.

15. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of separating and individualizing portions surrounded by the peripheral groove in the first substrate and the second substrate after the step of forming a concave portion in the first bottom surface.

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