Imaging element and mother board

Abstract

To provide an imaging element and a mother board that can be inspected at low cost.SOLUTION: An imaging element has an imaging area 110 divided into a first area 110a and a second area 110b, and a peripheral area 112 surrounding the imaging area 110. The imaging element includes a plurality of pixels PX1 and a wiring connected to each of the pixels PX1 in the first region 110a, and a plurality of pixels PX2 and a wiring connected to each of the plurality of pixels PX2 in the second region 110b, and a terminal connected to the wiring in the peripheral region 112. When rotated 180° in a plan view, the positions of the terminal connected to the wiring arranged in the first area 110a and the terminal connected to the wiring arranged in the second area 110b are swapped.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a mother substrate.

Background Art

[0002] An imaging device (image sensor) including pixels having a photoelectric conversion element and a switching element is known. For example, Patent Document 1 discloses a moving image X-ray detection panel including a plurality of pixels arranged in a matrix, each pixel including a lead-out thin film transistor, a reset thin film transistor, and a photodiode.

[0003] The moving image X-ray detection panel of Patent Document 1 includes a plurality of pixels, a plurality of lead-out gate pads, a plurality of lead-out pads, a plurality of reset gate pads, at least one reset drain pad, and a bias pad. The lead-out gate pads are commonly connected to the gates of the respective lead-out thin film transistors in each pixel of one row. The lead-out pads are respectively connected to the drains of the respective lead-out thin film transistors in each pixel of one row. The reset gate pads are commonly connected to the gates of the respective reset thin film transistors in each pixel of one row. The reset drain pad is commonly connected to the drains of the respective reset thin film transistors in a plurality of pixels. The bias pad is commonly connected to the photodiodes in a plurality of pixels. In Patent Document 1, for each row, by sequentially performing line reset, window time, and lead-out operations, the time delay occurring between the window time and the lead-out is suppressed, and high-speed moving image shooting is achieved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the video X-ray detection panel of Patent Document 1, since a reset gate pad is provided in addition to the readout gate pad and the readout pad, a large number of probe pins are also required for the probe bar used when inspecting the video X-ray detection panel. A probe bar having a large number of probe pins is expensive, and the cost of inspection increases.

[0006] The present disclosure has been made in view of the above circumstances, and an object thereof is to provide an imaging device and a mother board that can be inspected at low cost.

Means for Solving the Problems

[0007] In order to achieve the above object, an imaging device according to a first aspect of the present disclosure includes: an imaging region divided into a first region and a second region in a predetermined first direction, and a peripheral region surrounding the imaging region; a plurality of pixels disposed in the imaging region, having a first switching element, a second switching element, and a photoelectric conversion element connected to a source electrode of the first switching element and a source electrode of the second switching element; a plurality of first gate wirings disposed in the first region, connected to respective gate electrodes of the first switching elements of the pixels disposed in the first region, extending in a predetermined second direction perpendicular to the predetermined first direction, and connected to respective ones of a plurality of first gate terminals disposed in the peripheral region; a plurality of first reset gate wirings disposed in the first region, connected to respective gate electrodes of the second switching elements of the pixels disposed in the first region, extending in the predetermined second direction, and connected to respective ones of a plurality of first reset gate terminals disposed in the peripheral region; a plurality of first data wirings disposed in the first region, connected to respective drain electrodes of the first switching elements of the pixels disposed in the first region, extending in the predetermined first direction, and connected to respective ones of a plurality of first data terminals disposed in the peripheral region; A plurality of first reset wirings, which are disposed in the first region, are connected to respective drain electrodes of the second switching elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to a first reset terminal disposed in the peripheral region. A plurality of first bias wirings, which are disposed in the first region, are connected to respective photoelectric conversion elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to a first bias terminal disposed in the peripheral region. A plurality of second gate wirings, which are disposed in the second region, are connected to respective gate electrodes of the first switching elements of the pixels disposed in the second region, extend in the predetermined second direction, and are connected to respective ones of a plurality of second gate terminals disposed in the peripheral region. A plurality of second reset gate wirings, which are disposed in the second region, are connected to respective gate electrodes of the second switching elements of the pixels disposed in the second region, extend in the predetermined second direction, and are connected to respective ones of a plurality of second reset gate terminals disposed in the peripheral region. A plurality of second data wirings, which are disposed in the second region, are connected to respective drain electrodes of the first switching elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to respective ones of a plurality of second data terminals disposed in the peripheral region. A plurality of second reset wirings, which are disposed in the second region, are connected to respective drain electrodes of the second switching elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to a second reset terminal disposed in the peripheral region. A plurality of second bias wirings, which are disposed in the second region, are connected to respective photoelectric conversion elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to a second bias terminal disposed in the peripheral region. The first gate terminal and the first reset gate terminal are disposed in the peripheral regions on opposite sides of each other with the first region therebetween. The second gate terminal and the second reset gate terminal are disposed in the peripheral regions on opposite sides of each other with the second region therebetween. The first gate terminal and the second reset gate terminal are arranged in the peripheral region on the same side with respect to the imaging region. The first reset gate terminal and the second gate terminal are arranged in the peripheral region on the same side with respect to the imaging region. When rotated 180° in a plan view, the positions of the first gate terminal and the second gate terminal are interchanged, the positions of the first reset gate terminal and the second reset gate terminal are interchanged, the positions of the first data terminal and the second data terminal are interchanged, the positions of the first reset terminal and the second reset terminal are interchanged, the positions of the first bias terminal and the second bias terminal are interchanged.

[0008] The mother substrate according to the second aspect of the present disclosure has an imaging region divided into a first region and a second region in a predetermined first direction, a peripheral region surrounding the imaging region, and an inspection terminal region surrounding the peripheral region. A plurality of pixels arranged in the imaging region, having a first switching element, a second switching element, and a photoelectric conversion element connected to the source electrodes of the first switching element and the second switching element. A plurality of first gate wirings arranged in the first region, connected to the gate electrodes of the first switching elements of the pixels arranged in the first region, extending in a predetermined second direction perpendicular to the predetermined first direction, and connected to the respective first gate terminals arranged in the peripheral region. A plurality of first reset gate wirings arranged in the first region, connected to the gate electrodes of the second switching elements of the pixels arranged in the first region, extending in the predetermined second direction, and connected to the respective first reset gate terminals arranged in the peripheral region. A plurality of first data wirings, which are disposed in the first region, are connected to respective drain electrodes of the first switching elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to respective ones of a plurality of first data terminals disposed in the peripheral region. A plurality of first reset wirings, which are disposed in the first region, are connected to respective drain electrodes of the second switching elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to a first reset terminal disposed in the peripheral region. A plurality of first bias wirings, which are disposed in the first region, are connected to respective photoelectric conversion elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to a first bias terminal disposed in the peripheral region. A plurality of second gate wirings, which are disposed in the second region, are connected to respective gate electrodes of the first switching elements of the pixels disposed in the second region, extend in the predetermined second direction, and are connected to respective ones of a plurality of second gate terminals disposed in the peripheral region. A plurality of second reset gate wirings, which are disposed in the second region, are connected to respective gate electrodes of the second switching elements of the pixels disposed in the second region, extend in the predetermined second direction, and are connected to respective ones of a plurality of second reset gate terminals disposed in the peripheral region. A plurality of second data wirings, which are disposed in the second region, are connected to respective drain electrodes of the first switching elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to respective ones of a plurality of second data terminals disposed in the peripheral region. A plurality of second reset wirings, which are disposed in the second region, are connected to respective drain electrodes of the second switching elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to a second reset terminal disposed in the peripheral region. A plurality of second bias wirings, which are disposed in the second region, are connected to respective photoelectric conversion elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to a second bias terminal disposed in the peripheral region. A first reset gate inspection terminal that is connected to the plurality of first reset gate terminals and is disposed in the inspection terminal region; A plurality of first data inspection terminals that are connected to respective ones of the plurality of first data terminals and are disposed in the inspection terminal region; A first reset inspection terminal that is connected to the first reset terminal and is disposed in the inspection terminal region; A first bias inspection terminal that is connected to the first bias terminal and is disposed in the inspection terminal region; A second reset gate inspection terminal that is connected to the plurality of second reset gate terminals and is disposed in the inspection terminal region; A plurality of second data inspection terminals that are connected to respective ones of the plurality of second data terminals and are disposed in the inspection terminal region; A second reset inspection terminal that is connected to the second reset terminal and is disposed in the inspection terminal region; A second bias inspection terminal that is connected to the second bias terminal and is disposed in the inspection terminal region, and The first data terminal, the first reset terminal, and the first bias terminal are disposed in the peripheral region on the first region side among the peripheral regions on opposite sides sandwiching the first region and the second region; The second data terminal, the second reset terminal, and the second bias terminal are disposed in the peripheral region on the second region side among the peripheral regions on opposite sides sandwiching the first region and the second region; The first gate terminal and the first reset gate terminal are disposed in the peripheral regions on opposite sides sandwiching the first region; The second gate terminal and the second reset gate terminal are disposed in the peripheral regions on opposite sides sandwiching the second region; The first gate terminal and the second reset gate terminal are disposed in the peripheral region on the same side with respect to the imaging region, and the first reset gate terminal and the second gate terminal are disposed in the peripheral region on the same side with respect to the imaging region; Each of the first data inspection terminal, the first reset inspection terminal, and the first bias inspection terminal is disposed outside each of the first data terminal, the first reset terminal, and the first bias terminal. Each of the second data inspection terminal, the second reset inspection terminal, and the second bias inspection terminal is disposed outside each of the second data terminal, the second reset terminal, and the second bias terminal. The first reset gate inspection terminal is disposed side by side with the first data inspection terminal, the first reset inspection terminal, and the first bias inspection terminal. The second reset gate inspection terminal is disposed side by side with the second data inspection terminal, the second reset inspection terminal, and the second bias inspection terminal. When rotated 180° in plan view, the positions of the first data inspection terminal and the second data inspection terminal are interchanged, the positions of the first reset inspection terminal and the second reset inspection terminal are interchanged, the positions of the first bias inspection terminal and the second bias inspection terminal are interchanged, the positions of the first reset gate inspection terminal and the second reset gate inspection terminal are interchanged.

Advantages of the Invention

[0009] According to the present disclosure, when rotated 180° in plan view, the positions of the terminals connected to the wirings arranged in the first region and the terminals connected to the wirings arranged in the second region, which have the same functions, are interchanged. Thereby, with one probe bar having probe pins corresponding to the terminals connected to the wirings arranged in one region, both the first region and the second region can be inspected, and the inspection cost can be reduced.

Brief Description of the Drawings

[0010]

Figure 1

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Figure 17

Mode for Carrying Out the Invention

[0011] Hereinafter, an image pickup device and an image pickup device substrate according to an embodiment will be described with reference to the drawings.

[0012] <Embodiment 1> Referring to FIGS. 1 to 10, the image sensor 10 according to this embodiment will be described. The image sensor 10 captures an X-ray image. As shown in FIG. 1, the image sensor 10 includes an element substrate 100 and a scintillator SC. The element substrate 100 has an imaging region 110 and a peripheral region 112. The scintillator SC is disposed on the imaging region 110 of the element substrate 100. The scintillator SC is formed of a phosphor and converts X-rays into visible light.

[0013] As shown in FIGS. 1 and 2, the element substrate 100 of the image sensor 10 has an imaging region 110 and a peripheral region 112 on a main surface 100a. The element substrate 100 is, for example, a glass substrate. In this specification, for ease of understanding, the right direction of the element substrate 100 in FIG. 2 is defined as the +X direction, the upward direction as the +Y direction, and the direction perpendicular to the +X direction and the +Y direction as the +Z direction for description.

[0014] The imaging region 110 is bisected in the Y direction into a first region 110a and a second region 110b. The peripheral region 112 surrounds the imaging region 110. The Y direction corresponds to a predetermined first direction.

[0015] As shown in FIG. 2, the element substrate 100 includes pixels PX (pixels PX1, PX2), wirings such as a first gate wiring 132, a first data wiring 152, and a second gate wiring 232, and terminals such as a first gate terminal 132P, a first data terminal 152P, and a second gate terminal 232P. In this embodiment, the first gate wiring 132, the first data wiring 152, etc. that are directly connected to any one of a first switching element 122, a second switching element 124, and a photoelectric conversion element E1 of the pixel PX, which will be described later, are collectively referred to as wirings. Also, the first gate terminal 132P, the first data terminal 152P, etc. that are connected to the wirings via a connection wiring 190 are collectively referred to as terminals. The terminals are electrodes (pads) for connecting the wirings to the outside of the element substrate 100. The outside of the element substrate 100 refers to devices, members, drive circuits, drive ICs (Integrated Circuits), etc. other than the element substrate 100.

[0016] First, the pixel PX of the element substrate 100 will be described. The pixels PX are arranged in a matrix in the imaging region 110. In the present embodiment, the pixel PX arranged in the first region 110a of the imaging region 110 is defined as pixel PX1, and the pixel PX arranged in the second region 110b of the imaging region 110 is defined as pixel PX2.

[0017] As shown in FIGS. 2 to 4, the pixel PX (pixels PX1 and PX2) includes a photoelectric conversion element E1, a first switching element 122, and a second switching element 124. The photoelectric conversion element E1 is, for example, a PIN photodiode. The first switching element 122 and the second switching element 124 are, for example, TFT (Thin Film Transistor) elements. The first switching element 122 is a switching element for reading out the charges of the photoelectric conversion element E1. The second switching element 124 is a switching element for resetting the residual charges in the pixel PX.

[0018] The photoelectric conversion element (PIN photodiode) E1 accumulates charges according to the amount of visible light converted from X-rays by the scintillator. The photoelectric conversion element E1 includes a cathode electrode, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, and an anode electrode (none of which are shown). The n-type amorphous silicon layer is formed on the cathode electrode, and the intrinsic amorphous silicon layer is formed on the n-type amorphous silicon layer. The p-type amorphous silicon layer is formed on the intrinsic amorphous silicon layer. The anode electrode is formed on the p-type amorphous silicon layer. The cathode electrode is formed of chromium (Cr), molybdenum, aluminum, etc., and is connected to the source electrode 122S of the first switching element 122 and the source electrode 124S of the second switching element 124. The anode electrode is formed of, for example, ITO (Indium Tin Oxide). The anode electrode of the photoelectric conversion element E1 of the pixel PX1 is connected to the first bias wiring 172 (FIG. 3), and the anode electrode of the photoelectric conversion element E1 of the pixel PX2 is connected to the second bias wiring 272 (FIG. 4).

[0019] The first switching element 122 is sequentially driven based on a scanning signal supplied via the first gate wiring 132 or the second gate wiring 232, which will be described later. The first switching element 122 includes a gate electrode 122G, a source electrode 122S, a drain electrode 122D, a semiconductor layer (not shown), and an insulating layer (not shown). The gate electrode 122G, the source electrode 122S, and the drain electrode 122D are formed of a metal such as aluminum or molybdenum. The semiconductor layer is formed of amorphous silicon, an oxide containing indium (In), gallium (Ga), and zinc (Zn), or the like. The source electrode 122S is connected to the cathode electrode of the photoelectric conversion element E1. The gate electrode 122G of the first switching element 122 of the pixel PX1 is connected to the first gate wiring 132 (FIG. 3), and the gate electrode 122G of the first switching element 122 of the pixel PX2 is connected to the second gate wiring 232 (FIG. 4). Also, the drain electrode 122D of the first switching element 122 of the pixel PX1 is connected to the first data wiring 152 (FIG. 3), and the drain electrode 122D of the first switching element 122 of the pixel PX2 is connected to the second data wiring 252 (FIG. 4).

[0020] The second switching element 124 is sequentially driven based on a scanning signal supplied via the first reset gate wiring 144 or the second reset gate wiring 244, which will be described later. The second switching element 124 includes a gate electrode 124G, a source electrode 124S, a drain electrode 124D, a semiconductor layer (not shown), and an insulating layer (not shown). The source electrode 124S is connected to the cathode electrode of the photoelectric conversion element E1. The gate electrode 124G of the second switching element 124 of the pixel PX1 is connected to the first reset gate wiring 144 (FIG. 3), and the gate electrode 124G of the second switching element 124 of the pixel PX2 is connected to the second reset gate wiring 244 (FIG. 4). Also, the drain electrode 124D of the second switching element 124 of the pixel PX1 is connected to the first reset wiring 164 (FIG. 3), and the drain electrode 124D of the second switching element 124 of the pixel PX2 is connected to the second reset wiring 264 (FIG. 4). Other configurations of the second switching element 124 are the same as those of the first switching element 122.

[0021] The wiring of the element substrate 100 will be described. The wiring is formed of a metal such as aluminum (Al) or molybdenum (Mo).

[0022] First, the wiring disposed in the first region 110a of the imaging region 110 will be described. As shown in FIG. 2, in the first region 110a, a first gate wiring 132, a first reset gate wiring 144, a first data wiring 152, a first reset wiring 164, and a first bias wiring 172 are disposed.

[0023] The first gate wiring 132 supplies a scanning signal to the gate electrode 122G of the first switching element 122. The first gate wiring 132 extends in the X direction and is arranged in the Y direction. The first gate wiring 132 is connected to the gate electrode 122G of the first switching element 122 of the pixels PX1 arranged in the X direction. Further, each of the first gate wirings 132 is connected to each of the first gate terminals 132P via a connection wiring 190. The X direction corresponds to a predetermined second direction.

[0024] The first reset gate wiring 144 supplies a scanning signal to the gate electrode 124G of the second switching element 124. The first reset gate wiring 144 extends in the X direction and is arranged in the Y direction. The first reset gate wiring 144 is connected to the gate electrode 124G of the second switching element 124 of the pixels PX1 arranged in the X direction. Further, each of the first reset gate wirings 144 is connected to each of the first reset gate terminals 144P via a connection wiring 190.

[0025] The first data wiring 152 sends out the charge accumulated by the photoelectric conversion element E1 to the outside. The first data wiring 152 extends in the Y direction and is arranged in the X direction. The first data wiring 152 is connected to the drain electrode 122D of the first switching element 122 of the pixels PX1 arranged in the Y direction. Further, each of the first data wirings 152 is connected to each of the first data terminals 152P via a connection wiring 190.

[0026] The first reset wiring 164 removes residual charges in the pixel PX1. The first reset wiring 164 extends in the Y direction and is arranged in the X direction. The first reset wiring 164 is connected to the drain electrode 124D of the second switching element 124 of the pixels PX1 arranged in the Y direction. The first reset wiring 164 is commonly connected to the first reset terminal 164P via the connection wiring 190.

[0027] The first bias wiring 172 supplies a bias voltage to the photoelectric conversion element E1. The first bias wiring 172 extends in the Y direction and is arranged in the X direction. The first bias wiring 172 is connected to the anode electrode of the photoelectric conversion element E1 of the pixels PX1 arranged in the Y direction. The first bias wiring 172 is commonly connected to the first bias terminal 172P via the connection wiring 190.

[0028] In the second region 110b of the imaging region 110, a second gate wiring 232, a second reset gate wiring 244, a second data wiring 252, a second reset wiring 264, and a second bias wiring 272 are arranged.

[0029] The second gate wiring 232 supplies a scanning signal to the gate electrode 122G of the first switching element 122. The second gate wiring 232 extends in the X direction and is arranged in the Y direction. The second gate wiring 232 is connected to the gate electrode 122G of the first switching element 122 of the pixels PX2 arranged in the X direction. Each of the second gate wirings 232 is connected to each of the second gate terminals 232P via the connection wiring 190.

[0030] The second reset gate wiring 244 supplies a scanning signal to the gate electrode 124G of the second switching element 124. The second reset gate wiring 244 extends in the X direction and is arranged in the Y direction. The second reset gate wiring 244 is connected to the gate electrode 124G of the second switching element 124 of the pixels PX2 arranged in the X direction. Each of the second reset gate wirings 244 is connected to each of the second reset gate terminals 244P via the connection wiring 190.

[0031] The second data wiring 252 sends out the charges accumulated by the photoelectric conversion element E1 to the outside. The second data wiring 252 extends in the Y direction and is arranged in the X direction. The second data wiring 252 is connected to the drain electrode 122D of the first switching element 122 of the pixels PX2 arranged in the Y direction. Each of the second data wirings 252 is connected to each of the second data terminals 252P via the connection wiring 190.

[0032] The second reset wiring 264 removes the residual charges in the pixel PX2. The second reset wiring 264 extends in the Y direction and is arranged in the X direction. The second reset wiring 264 is connected to the drain electrode 124D of the second switching element 124 of the pixels PX2 arranged in the Y direction. The second reset wiring 264 is commonly connected to the second reset terminal 264P via the connection wiring 190.

[0033] The second bias wiring 272 supplies a bias voltage to the photoelectric conversion element E1. The second bias wiring 272 extends in the Y direction and is arranged in the X direction. The second bias wiring 272 is connected to the anode electrode of the photoelectric conversion element E1 of the pixels PX2 arranged in the Y direction. The second bias wiring 272 is commonly connected to the second bias terminal 272P via the connection wiring 190.

[0034] The terminals of the element substrate 100 will be described. The terminals are arranged in the peripheral region 112. The arrangement of the terminals will be described later in summary.

[0035] Terminals connected to the wirings arranged in the first region 110a of the imaging region 110 will be described. Each of the first gate terminals 132P is connected to each of the first gate wirings 132. The first gate terminals 132P are arranged in a row in the Y direction and form the first gate terminal group 132PU.

[0036] Each of the first reset gate terminals 144P is connected to each of the first reset gate wirings 144. The first reset gate terminals 144P are arranged in a row in the Y direction and form the first reset gate terminal group 144PU.

[0037] Each of the first data terminals 152P is connected to each of the first data wirings 152. The first data terminals 152P connected to the first data wirings 152 arranged on the -X side are arranged in a row in the X direction and form the first data terminal group 152PU1. Also, the first data terminals 152P connected to the first data wirings 152 arranged on the +X side are arranged in a row in the X direction and form the first data terminal group 152PU2.

[0038] The first reset terminals 164P are connected to a plurality of first reset wirings 164. In the present embodiment, two first reset terminals 164P are provided in the peripheral region 112, and all the first reset wirings 164 are connected to the two first reset terminals 164P.

[0039] The first bias terminals 172P are connected to a plurality of first bias wirings 172. In the present embodiment, two first bias terminals 172P are provided in the peripheral region 112, and all the first bias wirings 172 are connected to the two first bias terminals 172P.

[0040] Terminals connected to wirings arranged in the second region 110b of the imaging region 110 will be described. Each of the second gate terminals 232P is connected to each of the second gate wirings 232. The second gate terminals 232P are arranged in a row in the Y direction and form the second gate terminal group 232PU.

[0041] Each of the second reset gate terminals 244P is connected to each of the second reset gate wirings 244. The second reset gate terminals 244P are arranged in a row in the Y direction and form the second reset gate group terminals 244PU.

[0042] Each of the second data terminals 252P is connected to each of the second data wirings 252. The second data terminals 252P connected to the second data wirings 252 arranged on the -X side are arranged in a row in the X direction, forming a second data terminal group 252PU1. Also, the second data terminals 252P connected to the second data wirings 252 arranged on the +X side are arranged in a row in the X direction, forming a second data terminal group 252PU2.

[0043] The second reset terminals 264P are connected to a plurality of second reset wirings 264. In the present embodiment, two second reset terminals 264P are provided in the peripheral region 112, and all the second reset wirings 264 are connected to the two second reset terminals 264P.

[0044] The second bias terminals 272P are connected to a plurality of second bias wirings 272. In the present embodiment, two second bias terminals 272P are provided in the peripheral region 112, and all the second bias wirings 272 are connected to the two second bias terminals 272P.

[0045] Next, with reference to FIG. 5, the arrangement of the terminals will be described. Note that in FIG. 5, the pixels PX and the wirings are omitted for ease of understanding. The pixels PX and the wirings may also be omitted in the following figures.

[0046] The arrangement of the first data terminals 152P (first data terminal groups 152PU1, 152PU2), two first reset terminals 164P, two first bias terminals 172P, the second data terminals 252P (second data terminal groups 252PU1, 252PU2), two second reset terminals 264P, and two second bias terminals 272P will be described. These terminals are connected to the wirings extending in the Y direction. Also, the wirings to which the first data terminals 152P, the first reset terminals 164P, and the first bias terminals 172P are connected are arranged in the first region 110a. The wirings to which the second data terminals 252P, the second reset terminals 264P, and the second bias terminals 272P are connected are arranged in the second region 110b.

[0047] The first data terminal 152P, the two first reset terminals 164P, the two first bias terminals 172P, the second data terminal 252P, the two second reset terminals 264P, and the two second bias terminals 272P are arranged in the peripheral regions 112 on opposite sides across the first region 110a and the second region 110b of the imaging region 110. Specifically, the first data terminal 152P, the two first reset terminals 164P, and the two first bias terminals 172P are arranged in the region 112a on the first region 110a side (+Y side) of the peripheral regions 112 on opposite sides across the first region 110a and the second region 110b. On the other hand, the second data terminal 252P, the two second reset terminals 264P, and the two second bias terminals 272P are arranged in the region 112b on the second region 110b side (-Y side) of the peripheral regions 112 on opposite sides across the first region 110a and the second region 110b.

[0048] Furthermore, the first data terminal 152P, the two first reset terminals 164P, and the two first bias terminals 172P arranged in the region 112a are arranged in the order of the first bias terminal 172P, the first data terminal group 152PU1, the first reset terminal 164P, the first bias terminal 172P, the first data terminal group 152PU2, and the first reset terminal 164P in the +X direction. On the other hand, the second data terminal 252P, the two second reset terminals 264P, and the two second bias terminals 272P arranged in the region 112b are arranged in the order of the second reset terminal 264P, the second data terminal group 252PU1, the second bias terminal 272P, the second reset terminal 264P, the second data terminal group 252PU2, and the second bias terminal 272P in the +X direction.

[0049] Next, the arrangement of the first gate terminal 132P (first gate terminal group 132PU), the first reset gate terminal 144P (first reset gate terminal group 144PU), the second gate terminal 232P (second gate terminal group 232PU), and the second reset gate terminal 244P (second reset gate terminal group 244PU) will be described. These terminals are connected to wirings extending in the X direction. Also, the wiring to which the first gate terminal 132P and the first reset gate terminal 144P are connected is arranged in the first region 110a. The wiring to which the second gate terminal 232P and the second reset gate terminal 244P are connected is arranged in the second region 110b.

[0050] The first gate terminal 132P and the first reset gate terminal 144P are arranged in the peripheral regions 112 on opposite sides across the first region 110a. In the present embodiment, the first gate terminal 132P is arranged in the region 112c on the -X side sandwiching the first region 110a, and the first reset gate terminal 144P is arranged in the region 112d on the +X side sandwiching the first region 110a.

[0051] The second gate terminal 232P and the second reset gate terminal 244P are arranged in the peripheral regions 112 on opposite sides across the second region 110b, and the second gate terminal 232P is on the same side as the first reset gate terminal 144P with respect to the imaging region 110, and the second reset gate terminal 244P is on the same side as the first gate terminal 132P with respect to the imaging region 110. In the present embodiment, the second gate terminal 232P is arranged in the region 112f on the +X side sandwiching the second region 110b, and the second reset gate terminal 244P is arranged in the region 112e on the -X side sandwiching the second region 110b.

[0052] The terminals are arranged as described above. As shown in FIG. 6, when the element substrate 100 is rotated 180° in plan view, the second gate terminal group 232PU is located at the position of the first gate terminal group 132PU before rotation, and the first gate terminal group 132PU is located at the position of the second gate terminal group 232PU before rotation. Further, the second reset gate terminal group 244PU is located at the position of the first reset gate terminal group 144PU before rotation, and the first reset gate terminal group 144PU is located at the position of the second reset gate terminal group 244PU before rotation. The second data terminal group 252PU2 is located at the position of the first data terminal group 152PU1 before rotation, and the first data terminal group 152PU1 is located at the position of the second data terminal group 252PU2 before rotation. The second data terminal group 252PU1 is located at the position of the first data terminal group 152PU2 before rotation, and the first data terminal group 152PU2 is located at the position of the second data terminal group 252PU1 before rotation. The second reset terminal 264P is located at the position of the first reset terminal 164P before rotation, and the first reset terminal 164P is located at the position of the second reset terminal 264P before rotation. The second bias terminal 272P is located at the position of the first bias terminal 172P before rotation, and the first bias terminal 172P is located at the position of the second bias terminal 272P before rotation.

[0053] In other words, when the element substrate 100 is rotated 180° in plan view, the positions of the second gate terminal group 232PU and the first gate terminal group 132PU, the second reset gate terminal group 244PU and the first reset gate terminal group 144PU, the second data terminal group 252PU2 and the first data terminal group 152PU1, the second data terminal group 252PU1 and the first data terminal group 152PU2, the second reset terminal 264P and the first reset terminal 164P, and the second bias terminal 272P and the first bias terminal 172P are interchanged. That is, when the element substrate 100 is rotated 180° in plan view, the positions of the terminals connected to the wirings arranged in the first region 110a and having the same function and the terminals connected to the wirings arranged in the second region 110b are interchanged.

[0054] In this embodiment, as described above, when the element substrate 100 is rotated 180° in a plan view, the positions of the terminals connected to the wirings arranged in the first region 110a and the terminals connected to the wirings arranged in the second region 110b, which have the same functions, are swapped. Therefore, as shown in FIGS. 7 and 8, by rotating the element substrate 100 (imaging element 10) 180°, the element substrate 100 (imaging element 10) can be inspected with one probe bar 900.

[0055] Note that FIGS. 7 and 8 show a state where the position of the probe bar 900 is fixed and the element substrates 100 are rotated 180° relative to each other. Also, for ease of understanding, the probe bar 900 is shown by a dashed line. The probe bar 900 includes probe units 910 to 940, and the probe units 910 to 940 have probe pins corresponding to either the terminals connected to the wirings arranged in the first region 110a or the terminals connected to the wirings arranged in the second region 110b. The probe pins are connected to the signal circuit of the probe bar 900, the control unit of the inspection apparatus, etc., and the inspection apparatus inspects the operation of the element substrate 100 (imaging element 10) via the probe pins.

[0056] On the other hand, in the conventional terminal arrangement, the terminals having the same functions are grouped and arranged on the same side with respect to the imaging region 110. For example, like the element substrate 600 of the comparative example shown in FIG. 9, the first gate terminal group 132PU and the second gate terminal group 232PU are grouped and arranged on the -X side of the imaging region 110, and the first reset gate terminal group 144PU and the second reset gate terminal group 244PU are grouped and arranged on the +X side of the imaging region 110. In this case, even if the element substrate 600 is rotated 180° in a plan view, the positions of the terminals connected to the wirings arranged in the first region 110a and the positions of the terminals connected to the wirings arranged in the second region 110b do not swap. Therefore, in order to inspect the first region 110a and the second region 110b of the element substrate 600 of the comparative example, two different probe bars are required.

[0057] As described above, by rotating the element substrate 100 (image pickup element 10) by 180° in plan view, one probe bar 900 having probe pins corresponding to the terminals connected to the wirings arranged in one of the first region 110a and the second region 110b can inspect both the first region 110a and the second region 110b. Therefore, a probe bar 900 with fewer probe pins can be inexpensively prepared, and the element substrate 100 (image pickup element 10) can be easily inspected. That is, the inspection cost of the element substrate 100 (image pickup element 10) can be reduced.

[0058] Also, in the element substrate 100, the first gate terminal 132P (first gate terminal group 132PU) and the second reset gate terminal 244P (second reset gate terminal group 244PU) are located on the same side (-X side) with respect to the imaging region 110, and the second gate terminal 232P (second gate terminal group 232PU) and the first reset gate terminal 144P (first reset gate terminal group 144PU) are located on the same side (+X side) with respect to the imaging region 110.

[0059] Therefore, as shown in FIG. 10, a circuit board (circuit board 700) having a gate drive circuit 712 that drives the gate electrode 122G of the first switching element 122 via the first gate terminal 132P and a reset gate drive circuit 714 that drives the gate electrode 124G of the second switching element 124 via the second reset gate terminal 244P, and a circuit board (circuit board 700) having a gate drive circuit 712 that drives the gate electrode 122G of the first switching element 122 via the second gate terminal 232P and a reset gate drive circuit 714 that drives the gate electrode 124G of the second switching element 124 via the first reset gate terminal 144P can be made common. Also, the flexible wiring board 716 that connects the circuit board 700 and the terminals can be made common. Since the circuit board 700 and the flexible wiring board 716 can be made common, the manufacturing cost can be reduced. Note that in FIG. 10, the flexible wiring board 716 is shown by a broken line.

[0060] The operation of the imaging element 10 will be described. In the present embodiment, since the imaging region 110 is bisected into a first region 110a and a second region 110b, the imaging element 10 can capture an image at a frame rate that is twice as high as the frame rate at which the pixels PX in the entire imaging region 110 are sequentially driven by independently driving the pixels PX1 in the first region 110a and the pixels PX2 in the second region 110b.

[0061] Here, the operation will be described taking the first region 110a as an example. Also, it is assumed that the gate drive circuit 712 is connected to the first gate wiring 132 via the first gate terminal 132P, and the reset gate drive circuit 714 is connected to the first reset gate wiring 144 via the first reset gate terminal 144P. Further, a readout circuit (not shown) is connected to the first data wiring 152 via the first data terminal 152P. The drain-source voltage is applied to the drain electrode of the second switching element 124 via the first reset terminal 164P and the first reset wiring 164, and the bias voltage is applied to the anode electrode of the photoelectric conversion element E1 via the first bias terminal 172P and the first bias wiring 172. Note that the readout circuit reads the charge accumulated in the source electrode 122S of the photoelectric conversion element E1 or the first switching element 122, and outputs a voltage value corresponding to the read charge to an image processing circuit (not shown).

[0062] For each row in which the pixels PX1 are arranged in the X direction, a reset operation, an exposure operation, and a readout operation are sequentially performed. In the reset operation, the second switching element 124 is turned on by a scanning signal from the reset gate drive circuit 714. On the other hand, the first switching element 122 is in the off state. When the second switching element 124 is turned on, the residual charge in the pixel PX1 is removed, and the pixels PX1 in the row are reset. In the exposure operation, the first switching element 122 is in the off state, and the off state of the first switching element 122 is maintained. As a result, the charge generated by the photoelectric conversion element E1 due to the visible light radiated from the scintillator SC is accumulated in the photoelectric conversion element E1 or the source electrode 122S of the first switching element 122. In the readout operation, the first switching element 122 is turned on by a scanning signal from the gate drive circuit 712. The off state of the second switching element 124 is maintained. As a result, the accumulated charge is sent to the readout circuit via the drain electrode 122D of the first switching element 122, the first data wiring 152, and the first data terminal 152P.

[0063] The pixels PX1 in the first region 110a are sequentially driven for each row by the above-described operations. The pixels PX2 in the second region 110b are also driven in the same manner as the pixels PX1 in the first region 110a, and image data representing the captured image is generated by the image processing circuit.

[0064] As described above, when the element substrate 100 is rotated 180° in plan view, the positions of the terminals connected to the wirings arranged in the first region 110a and the terminals connected to the wirings arranged in the second region 110b, which have the same function, are interchanged. Therefore, both the first region 110a and the second region 110b can be inspected with a single probe bar 900, and the inspection cost can be reduced.

[0065] <Embodiment 2> In Embodiment 1, the wirings connected to the pixels PX (PX1, PX2) and extending in the X direction are arranged in the order of the first gate wiring 132 and the first reset gate wiring 144 toward the +Y direction. Further, the wirings connected to the pixels PX (PX1, PX2) and extending in the Y direction are arranged in the order of the first data wiring 152, the first bias wiring 172, and the first reset wiring 164 toward the +X direction. The arrangement of the wirings connected to the pixels PX1 and PX2 is not limited to these.

[0066] The image sensor 10 of the present embodiment includes an element substrate 100 and a scintillator SC, similar to the image sensor 10 of Embodiment 1. The configuration of the scintillator SC of the present embodiment is the same as the configuration of the scintillator SC of Embodiment 1. The configuration of the element substrate 100 of the present embodiment is the same as the configuration of the element substrate 100 of Embodiment 1, except for the arrangement of the wirings and the configuration of the connection wiring 190. Here, the arrangement of the wirings and the connection wiring 190 of the element substrate 100 will be described.

[0067] First, with reference to FIGS. 11 and 12, the arrangement of the wirings (the first gate wiring 132, the first reset gate wiring 144, the first data wiring 152, the first reset wiring 164, the first bias wiring 172) connected to the pixel PX1 in the first region 110a of the imaging region 110 will be described. The first gate wiring 132 and the first reset gate wiring 144, which are connected to one pixel PX1 and extend in the X direction, are arranged in the order of the first gate wiring 132 and the first reset gate wiring 144 toward the +Y direction. The first data wiring 152, the first reset wiring 164, and the first bias wiring 172, which are connected to one pixel PX1 and extend in the Y direction, are arranged in the order of the first data wiring 152, the first bias wiring 172, and the first reset wiring 164 toward the +X direction.

[0068] Referring to FIGS. 11 and 13, the arrangement of wirings (second gate wiring 232, second reset gate wiring 244, second data wiring 252, second reset wiring 264, second bias wiring 272) connected to the pixel PX2 in the second region 110b of the imaging region 110 will be described. The second gate wiring 232 and the second reset gate wiring 244, which are connected to one pixel PX2 and extend in the X direction, are arranged in the order of the second reset gate wiring 244 and the second gate wiring 232 in the +Y direction. That is, the second gate wiring 232 and the second reset gate wiring 244, and the first gate wiring 132 and the first reset gate wiring 144 are arranged in reverse order.

[0069] The second data wiring 252, the second reset wiring 264, and the second bias wiring 272, which are connected to one pixel PX2 and extend in the Y direction, are arranged in the order of the second reset wiring 264, the second bias wiring 272, and the second data wiring 252 in the +X direction. That is, the first data wiring 152, the first reset wiring 164, the first bias wiring 172, and the second data wiring 252, the second reset wiring 264, and the second bias wiring 272 are arranged in reverse order.

[0070] As described above, in the pixels PX1 and PX2 of the present embodiment, the wirings having the same function are arranged in reverse order. Thereby, as shown in FIG. 11, the wiring pattern 192a of the connection wiring 190 that connects the wiring (that is, the wiring arranged in the first region 110a) connected to the pixel PX1 and the terminal, and the wiring pattern 192b of the connection wiring 190 that connects the wiring (that is, the wiring arranged in the second region 110b) connected to the pixel PX2 and the terminal can be made the same shape. When the wiring pattern 192a and the wiring pattern 192b are made the same shape, the wiring resistance and wiring capacitance of the connection wiring 190 that connects the wiring in the first region 110a and the terminal, and the wiring resistance and wiring capacitance of the connection wiring 190 that connects the wiring in the second region 110b and the terminal can be combined, and an image with higher uniformity can be captured.

[0071] As described above, in this embodiment, wirings having the same function are arranged in reverse order. Thereby, the wiring resistance and wiring capacitance of the connection wiring 190 can be matched, and the imaging device 10 can capture an image with higher uniformity. Also, similar to Embodiment 1, both the first region 110a and the second region 110b can be inspected with one probe bar 900, and the inspection cost can be reduced.

[0072] <Embodiment 3> In this embodiment, a mother board 400 for manufacturing the element substrate 100 will be described. The mother board 400 has an imaging region 110, a peripheral region 112, and an inspection terminal region 402 on the main surface. The configurations of the imaging region 110, the peripheral region 112, the wirings, and the terminals are the same as those of the imaging region 110, the peripheral region 112, the wirings, and the terminals of the element substrate 100 in Embodiment 1. Here, the inspection terminal region 402 will be described. Note that the element substrate 100 is manufactured by removing the inspection terminal region 402 from the mother board 400.

[0073] As shown in FIG. 14, the inspection terminal region 402 surrounds the peripheral region 112. Inspection terminals such as a first data inspection terminal 452, a first gate inspection terminal 432, and a first reset gate inspection terminal 444 are arranged in the inspection terminal region 402. In this embodiment, the first data inspection terminal 452, the first gate inspection terminal 432, the first reset gate inspection terminal 444, etc., which are connected to the wirings via the connection wirings 490 and the terminals arranged in the peripheral region 112, are collectively referred to as inspection terminals.

[0074] First, inspection terminals connected to the wiring arranged in the first region 110a will be described. Each of the first data inspection terminals 452 is connected to each of the first data terminals 152P via the connection wiring 490, and is connected to each of the first data wirings 152 via each of the first data terminals 152P. The first data inspection terminals 452 are arranged outside the first data terminals 152P in the inspection terminal region 402, and the first data inspection terminals 452 and the first data terminals 152P are arranged side by side along the Y direction. The first data inspection terminals 452 form a first data inspection terminal group 452U1 and a first data inspection terminal group 452U2 according to the first data terminal group 152PU1 and the first data terminal group 152PU2 of the first data terminals 152P.

[0075] The first reset inspection terminal 464 is connected to the first reset terminal 164P via the connection wiring 490, and is connected to all the first reset wirings 164 via the first reset terminal 164P. The first reset inspection terminal 464 is arranged outside the first reset terminal 164P in the inspection terminal region 402, and the first reset inspection terminal 464 and the first reset terminal 164P are arranged side by side along the Y direction. In this embodiment, two first reset inspection terminals 464 are provided in the inspection terminal region 402 according to the two first reset terminals 164P.

[0076] The first bias inspection terminal 472 is connected to the first bias terminal 172P via the connection wiring 490, and is connected to all the first bias wirings 172 via the first bias terminal 172P. The first bias inspection terminal 472 is arranged outside the first bias terminal 172P in the inspection terminal region 402, and the first bias inspection terminal 472 and the first bias terminal 172P are arranged side by side along the Y direction. In this embodiment, two first bias inspection terminals 472 are provided in the inspection terminal region 402 according to the two first bias terminals 172P.

[0077] In the peripheral region 112, the first data terminal 152P (the first data terminal groups 152PU1 and 152PU2), the first reset terminal 164P, and the first bias terminal 172P are arranged side by side along the X direction. Therefore, the first data inspection terminal 452 (the first data inspection terminal groups 452U1 and 452U2), the first reset inspection terminal 464, and the first bias inspection terminal 472 are also arranged side by side along the X direction in the inspection terminal region 402 outside the first data terminal 152P, the first reset terminal 164P, and the first bias terminal 172P.

[0078] The first reset gate inspection terminal 444 is connected to all the first reset gate terminals 144P via the connection wiring 490, and is connected to all the first reset gate wirings 144 via the first reset gate terminals 144P. That is, the first reset gate wiring 144 is commonly connected to the first reset gate inspection terminal 444. In this embodiment, two first reset gate inspection terminals 444 are provided in the inspection terminal region 402.

[0079] The first reset gate inspection terminal 444 is arranged side by side with the first data inspection terminal 452, the first reset inspection terminal 464, and the first bias inspection terminal 472. Specifically, the first data inspection terminal 452, the two first reset inspection terminals 464, the two first bias inspection terminals 472, and the two first reset gate inspection terminals 444 are arranged in the order of the first bias inspection terminal 472, the first data inspection terminal group 452U1, the first reset inspection terminal 464, the first reset gate inspection terminal 444, the first bias inspection terminal 472, the first data inspection terminal group 452U2, the first reset inspection terminal 464, and the first reset gate inspection terminal 444 in the +X direction.

[0080] Each of the first gate inspection terminals 432 is connected to each of the first gate terminals 132P via the connection wiring 490, and is connected to each of the first gate wirings 132 via each of the first gate terminals 132P. The first gate inspection terminals 432 are arranged outside the first gate terminals 132P in the inspection terminal region 402, and the first gate inspection terminals 432 and the first gate terminals 132P are arranged side by side along the X direction. The first gate inspection terminals 432 form a first gate inspection terminal group 432U according to the first gate terminal group 132PU of the first gate terminals 132P.

[0081] Inspection terminals connected to the wirings arranged in the second region 110b will be described. Each of the second data inspection terminals 552 is connected to each of the second data terminals 252P via the connection wiring 490, and is connected to each of the second data wirings 252 via each of the second data terminals 252P. The second data inspection terminals 552 are arranged outside the second data terminals 252P in the inspection terminal region 402, and the second data inspection terminals 552 and the second data terminals 252P are arranged side by side along the Y direction. The second data inspection terminals 552 form a second data inspection terminal group 552U1 and a second data inspection terminal group 552U2 according to the second data terminal group 252PU1 and the second data terminal group 252PU2 of the second data terminals 252P.

[0082] The second reset inspection terminal 564 is connected to the second reset terminal 264P via the connection wiring 490, and is connected to all the first reset wirings 164 via the second reset terminal 264P. The second reset inspection terminal 564 is arranged outside the second reset terminal 264P in the inspection terminal region 402, and the second reset inspection terminal 564 and the second reset terminal 264P are arranged side by side along the Y direction. In the present embodiment, two second reset inspection terminals 564 are provided in the inspection terminal region 402 according to the two second reset terminals 264P.

[0083] The second bias inspection terminal 572 is connected to the second bias terminal 272P via the connection wiring 490, and is connected to all the second bias wirings 272 via the second bias terminal 272P. The second bias inspection terminal 572 is disposed outside the second bias terminal 272P in the inspection terminal region 402, and the second bias inspection terminal 572 and the second bias terminal 272P are arranged side by side along the Y direction. In the present embodiment, two second bias inspection terminals 572 are provided in the inspection terminal region 402 corresponding to the two second bias terminals 272P.

[0084] In the peripheral region 112, the second data terminals 252P (the second data terminal groups 252PU1, 252PU2), the second reset terminal 264P, and the second bias terminal 272P are arranged side by side along the X direction. Therefore, the second data inspection terminals 552 (the second data inspection terminal groups 552U1, 552U2), the second reset inspection terminal 564, and the second bias inspection terminal 572 are also arranged side by side along the X direction in the inspection terminal region 402 outside the second data terminal 252P, the second reset terminal 264P, and the second bias terminal 272P.

[0085] The second reset gate inspection terminal 544 is connected to all the second reset gate terminals 244P via the connection wiring 490, and is connected to all the second reset gate wirings 244 via the second reset gate terminals 244P. That is, the second reset gate wiring 244 is commonly connected to the second reset gate inspection terminal 544. In the present embodiment, two second reset gate inspection terminals 544 are provided in the inspection terminal region 402.

[0086] The second reset gate inspection terminal 544 is arranged side by side with the second data inspection terminal 552, the second reset inspection terminal 564, and the second bias inspection terminal 572. Specifically, the second data inspection terminal 552, two second reset inspection terminals 564, two second bias inspection terminals 572, and two second reset gate inspection terminals 544 are arranged in the +X direction as the second reset gate inspection terminal 544, the second reset inspection terminal 564, the second data inspection terminal group 552U1, the second bias inspection terminal 572, the second reset gate inspection terminal 544, the second reset inspection terminal 564, the second data inspection terminal group 552U2, and the second bias inspection terminal 572 in this order.

[0087] Each of the second gate inspection terminals 532 is connected to each of the second gate terminals 232P via the connection wiring 490, and is connected to each of the second gate wirings 232 via each of the second gate terminals 232P. The second gate inspection terminals 532 are arranged outside the second gate terminals 232P in the inspection terminal region 402, and the second gate inspection terminals 532 and the second gate terminals 232P are arranged side by side along the X direction. The second gate inspection terminals 532 form the second gate inspection terminal group 532U according to the second gate terminal group 232PU of the second gate terminals 232P.

[0088] The inspection terminals are arranged as described above. As shown in FIG. 15, when the mother board 400 is rotated 180° in a plan view, the positions of the second gate inspection terminal group 532U and the first gate inspection terminal group 432U are interchanged. Also, the positions of the second data inspection terminal group 552U1 and the first data inspection terminal group 452U2, and the positions of the second data inspection terminal group 552U2 and the first data inspection terminal group 452U1 are interchanged. Furthermore, the positions of the second reset inspection terminal 564 and the first reset inspection terminal 464, the positions of the second bias inspection terminal 572 and the first bias inspection terminal 472, and the positions of the second reset gate inspection terminal 544 and the first reset gate inspection terminal 444 are interchanged. That is, similar to the element substrate 100 of Embodiment 1, the positions of the inspection terminals connected to the wirings arranged in the first region 110a and the inspection terminals connected to the wirings arranged in the second region 110b, which have the same functions, are interchanged.

[0089] Therefore, similar to the element substrate 100 (image pickup element 10), by rotating the mother substrate 400 by 180°, it is possible to inspect the imaging region 110 (the first region 110a and the second region 110b) with one probe bar having fewer probe pins. Further, since the first reset gate wiring 144 is commonly connected to the first reset gate inspection terminal 444 and the second reset gate wiring 244 is commonly connected to the second reset gate inspection terminal 544, it is possible to reduce the number of probe pins for inspecting the first reset gate wiring 144 or the second reset gate wiring 244. Thereby, the inspection cost of the mother substrate 400 can be reduced. Note that since the first reset gate wiring 144 is commonly connected to the first reset gate inspection terminal 444 and the second reset gate wiring 244 is commonly connected to the second reset gate inspection terminal 544, in the inspection of the mother substrate 400, the reset operations of the pixel PX1 and the pixel PX2 are performed collectively instead of for each row.

[0090] As described above, when the mother substrate 400 is rotated by 180° in plan view, the positions of the inspection terminals connected to the wirings arranged in the first region 110a and the inspection terminals connected to the wirings arranged in the second region 110b, which have the same function, are interchanged. Therefore, it is possible to inspect both the first region 110a and the second region 110b with one probe bar having fewer probe pins, and the inspection cost can be reduced.

[0091] <Modification> Although the embodiments have been described above, the present disclosure can be variously modified without departing from the gist thereof.

[0092] For example, the image pickup element 10 may not include the scintillator SC. In this case, the photoelectric conversion element E1 converts X-rays into charges.

[0093] In Embodiment 1 and Embodiment 2, the element substrate 100 has two first reset terminals 164P. The element substrate 100 only needs to have at least one first reset terminal 164P. Also, the element substrate 100 only needs to have at least one second reset terminal 264P. The element substrate 100 only needs to have at least one first bias terminal 172P. The element substrate 100 only needs to have at least one second bias terminal 272P.

[0094] In Embodiment 3, the mother substrate 400 has two first reset gate inspection terminals 444. The mother substrate 400 only needs to have at least one first reset gate inspection terminal 444. Also, the mother substrate 400 only needs to have at least one second reset gate inspection terminal 544.

[0095] In the element substrate 100 of Embodiment 1, as shown in FIG. 16, the first reset wiring 164 and the second reset wiring 264 may be connected. Thereby, even if either the first reset wiring 164 or the second reset wiring 264 is disconnected, the charge in the pixel PX can be removed.

[0096] Also, in the element substrate 100 of Embodiment 1, the first bias wiring 172 and the second bias wiring 272 may be connected. Thereby, even if either the first bias wiring 172 or the second bias wiring 272 is disconnected, a bias voltage can be supplied to the photoelectric conversion element E1.

[0097] In the element substrate 100 of Embodiment 2, as shown in FIG. 17, the first bias wiring 172 arranged between the first data wiring 152 and the first reset wiring 164 and the second bias wiring 272 arranged between the second reset wiring 264 and the second data wiring 252 may be connected. Thereby, even if either the first bias wiring 172 or the second bias wiring 272 is disconnected, a bias voltage can be supplied to the photoelectric conversion element E1.

[0098] The mother board 400 of Embodiment 3 includes a first gate inspection terminal 432 and a second gate inspection terminal 532. The mother board 400 may not include the first gate inspection terminal 432 and the second gate inspection terminal 532. In this case, instead of the first gate inspection terminal 432 and the second gate inspection terminal 532, the first gate terminal 132P and the second gate terminal 232P are used for inspection.

[0099] The mother board 400 of Embodiment 3 may have the imaging region 110 and the peripheral region 112 of Embodiment 3 instead of the imaging region 110 and the peripheral region 112 of Embodiment 1.

[0100] As described above, the preferred embodiments have been described. However, the present disclosure is not limited to such specific embodiments, and the present disclosure includes the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0101] 10 imaging element, 100 element substrate, 100a main surface, 110 imaging region, 110a first region, 110b second region, 112 peripheral region, 112a, 112b, 112c, 112d, 112e, 112f regions, 122 first switching element, 122G gate electrode, 122S source electrode, 122D drain electrode, 124 second switching element, 124G gate electrode, 124S source electrode, 124D drain electrode, 132 first gate wiring, 132P first gate terminal, 132PU first gate terminal group, 144 first reset gate wiring, 144P first reset gate terminal, 144PU first reset gate terminal group, 152 first data wiring, 152P first data terminal, 152PU1, 152PU2 first data terminal group, 164 first reset wiring, 164P first reset terminal, 172 first bias wiring, 172P first bias terminal, 190 connection wiring, 192a, 192b wiring patterns, 232 second gate wiring, 232P second gate terminal, 232PU second gate terminal group, 244 second reset gate wiring, 244P second reset gate terminal, 244PU second reset gate terminal group, 252 second data wiring, 252P second data terminal, 252PU1, 252PU2 second data terminal group, 264 second reset wiring, 264P second reset terminal, 272 second bias wiring, 272P second bias terminal, 400 mother substrate, 402 inspection terminal region, 432 first gate inspection terminal, 432U first gate inspection terminal group, 444 first reset gate inspection terminal, 452 first data inspection terminal, 452U1, 452U2 first data inspection terminal group, 464 first reset inspection terminal, 472 first bias inspection terminal, 490 connection wiring, 532 second gate inspection terminal, 532U second gate inspection terminal group, 544 second reset gate inspection terminal, 552 second data inspection terminal, 552U1, 552U2 second data inspection terminal group, 564 second reset inspection terminal, 572 second bias inspection terminal, 600 element substrate, 700 circuit board, 712 gate drive circuit, 714 reset gate drive circuit, 716 flexible wiring board, 900 probe bar, 910, 920, 930, 940 probe units, PX, PX1, PX2 pixels, E1 photoelectric conversion element, SC scintillator

Claims

1. An imaging region divided into a first region and a second region in a predetermined first direction, and a peripheral region surrounding the imaging region, A plurality of pixels having a first switching element, a second switching element, and a photoelectric conversion element connected to the source electrode of the first switching element and the source electrode of the second switching element, and arranged in the imaging region, A plurality of first gate wirings arranged in the first region, connected to the gate electrodes of the first switching elements of the pixels arranged in the first region, extending in a predetermined second direction perpendicular to the predetermined first direction, and connected to the respective ones of a plurality of first gate terminals arranged in the peripheral region, A plurality of first reset gate wirings arranged in the first region, connected to the gate electrodes of the second switching elements of the pixels arranged in the first region, extending in the predetermined second direction, and connected to the respective ones of a plurality of first reset gate terminals arranged in the peripheral region, A plurality of first data wirings arranged in the first region, connected to the drain electrodes of the first switching elements of the pixels arranged in the first region, extending in the predetermined first direction, and connected to the respective ones of a plurality of first data terminals arranged in the peripheral region, A plurality of first reset wirings arranged in the first region, connected to the drain electrodes of the second switching elements of the pixels arranged in the first region, extending in the predetermined first direction, and connected to a first reset terminal arranged in the peripheral region, A plurality of first bias wirings arranged in the first region, connected to the photoelectric conversion elements of the pixels arranged in the first region, extending in the predetermined first direction, and connected to a first bias terminal arranged in the peripheral region, A plurality of second gate wirings arranged in the second region, connected to the gate electrodes of the first switching elements of the pixels arranged in the second region, extending in the predetermined second direction, and connected to the respective ones of a plurality of second gate terminals arranged in the peripheral region, A plurality of second reset gate wirings arranged in the second region, connected to the gate electrodes of the second switching elements of the pixels arranged in the second region, extending in the predetermined second direction, and connected to the respective ones of a plurality of second reset gate terminals arranged in the peripheral region, Disposed in the second region, connected to the drain electrodes of the first switching elements of the pixels disposed in the second region, extending in the predetermined first direction, and connected to respective ones of a plurality of second data terminals disposed in the peripheral region, a plurality of second data wirings; Disposed in the second region, connected to the drain electrodes of the second switching elements of the pixels disposed in the second region, extending in the predetermined first direction, and connected to a second reset terminal disposed in the peripheral region, a plurality of second reset wirings; Disposed in the second region, connected to the photoelectric conversion elements of the pixels disposed in the second region, extending in the predetermined first direction, and connected to a second bias terminal disposed in the peripheral region, a plurality of second bias wirings; and The first gate terminal and the first reset gate terminal are disposed in the peripheral regions on opposite sides across the first region. The second gate terminal and the second reset gate terminal are disposed in the peripheral regions on opposite sides across the second region. The first gate terminal and the second reset gate terminal are disposed in the peripheral region on the same side with respect to the imaging region. The first reset gate terminal and the second gate terminal are disposed in the peripheral region on the same side with respect to the imaging region. When rotated 180° in a plan view, The positions of the first gate terminal and the second gate terminal are interchanged. The positions of the first reset gate terminal and the second reset gate terminal are interchanged. The positions of the first data terminal and the second data terminal are interchanged. The positions of the first reset terminal and the second reset terminal are interchanged. The positions of the first bias terminal and the second bias terminal are interchanged. An imaging device.

2. The first data terminal, the first reset terminal, and the first bias terminal are disposed in the peripheral region on the first region side among the peripheral regions on opposite sides across the first region and the second region. The second data terminal, the second reset terminal, and the second bias terminal are disposed in the peripheral region on the second region side among the peripheral regions on opposite sides across the first region and the second region. The imaging device according to claim 1.

3. The first reset wiring and the second reset wiring are connected. The imaging device according to claim 1.

4. wherein the first bias wiring and the second bias wiring are connected; The image sensor according to claim 1 or 3.

5. The arrangement order in the predetermined first direction of the first gate wiring and the first reset gate wiring connected to one of the pixels arranged in the first region, and the arrangement order in the predetermined first direction of the second gate wiring and the second reset gate wiring connected to one of the pixels arranged in the second region are opposite; The arrangement order in the predetermined second direction of the first data wiring, the first reset wiring, and the first bias wiring connected to one of the pixels arranged in the first region, and the arrangement order in the predetermined second direction of the second data wiring, the second reset wiring, and the second bias wiring connected to one of the pixels arranged in the second region are opposite; The image sensor according to claim 1.

6. The first bias wiring is located between the first data wiring and the first reset wiring; The second bias wiring is located between the second data wiring and the second reset wiring; The first bias wiring and the second bias wiring are connected; The image sensor according to claim 5.

7. An imaging region divided into a first region and a second region in a predetermined first direction, a peripheral region surrounding the imaging region, and an inspection terminal region surrounding the peripheral region; A plurality of pixels including a first switching element, a second switching element, and a photoelectric conversion element connected to the source electrodes of the first switching element and the second switching element, and arranged in the imaging region; A plurality of first gate wirings arranged in the first region, connected to the gate electrodes of the first switching elements of the pixels arranged in the first region, extending in a predetermined second direction perpendicular to the predetermined first direction, and connected to the respective ones of a plurality of first gate terminals arranged in the peripheral region; A plurality of first reset gate wirings arranged in the first region, connected to the gate electrodes of the second switching elements of the pixels arranged in the first region, extending in the predetermined second direction, and connected to the respective ones of a plurality of first reset gate terminals arranged in the peripheral region; A plurality of first data wirings that are disposed in the first region, are connected to the drain electrodes of the first switching elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to respective ones of a plurality of first data terminals disposed in the peripheral region. A plurality of first reset wirings that are disposed in the first region, are connected to the drain electrodes of the second switching elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to a first reset terminal disposed in the peripheral region. A plurality of first bias wirings that are disposed in the first region, are connected to the photoelectric conversion elements of the pixels disposed in the first region, extend in the predetermined first direction, and are connected to a first bias terminal disposed in the peripheral region. A plurality of second gate wirings that are disposed in the second region, are connected to the gate electrodes of the first switching elements of the pixels disposed in the second region, extend in the predetermined second direction, and are connected to respective ones of a plurality of second gate terminals disposed in the peripheral region. A plurality of second reset gate wirings that are disposed in the second region, are connected to the gate electrodes of the second switching elements of the pixels disposed in the second region, extend in the predetermined second direction, and are connected to respective ones of a plurality of second reset gate terminals disposed in the peripheral region. A plurality of second data wirings that are disposed in the second region, are connected to the drain electrodes of the first switching elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to respective ones of a plurality of second data terminals disposed in the peripheral region. A plurality of second reset wirings that are disposed in the second region, are connected to the drain electrodes of the second switching elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to a second reset terminal disposed in the peripheral region. A plurality of second bias wirings that are disposed in the second region, are connected to the photoelectric conversion elements of the pixels disposed in the second region, extend in the predetermined first direction, and are connected to a second bias terminal disposed in the peripheral region. A first reset gate inspection terminal that is connected to the plurality of first reset gate terminals and is disposed in the inspection terminal region. A plurality of first data inspection terminals that are connected to respective ones of the plurality of first data terminals and are disposed in the inspection terminal region. connected to the first reset terminal and a first reset test terminal disposed in the test terminal region; connected to the first bias terminal and a first bias test terminal disposed in the test terminal region; connected to the plurality of second reset gate terminals and a second reset gate test terminal disposed in the test terminal region; connected to each of the plurality of second data terminals and a plurality of second data test terminals disposed in the test terminal region; connected to the second reset terminal and a second reset test terminal disposed in the test terminal region; connected to the second bias terminal and a second bias test terminal disposed in the test terminal region; The first data terminal, the first reset terminal, and the first bias terminal are disposed in the peripheral region on the first region side among the peripheral regions on opposite sides across the first region and the second region; The second data terminal, the second reset terminal, and the second bias terminal are disposed in the peripheral region on the second region side among the peripheral regions on opposite sides across the first region and the second region; The first gate terminal and the first reset gate terminal are disposed in the peripheral regions on opposite sides across the first region; The second gate terminal and the second reset gate terminal are disposed in the peripheral regions on opposite sides across the second region; The first gate terminal and the second reset gate terminal are disposed in the peripheral region on the same side with respect to the imaging region, and the first reset gate terminal and the second gate terminal are disposed in the peripheral region on the same side with respect to the imaging region; Each of the first data test terminal, the first reset test terminal, and the first bias test terminal is disposed outside each of the first data terminal, the first reset terminal, and the first bias terminal; Each of the second data test terminal, the second reset test terminal, and the second bias test terminal is disposed outside each of the second data terminal, the second reset terminal, and the second bias terminal; The first reset gate test terminal is disposed side by side with the first data test terminal, the first reset test terminal, and the first bias test terminal; The second reset gate test terminal is disposed side by side with the second data test terminal, the second reset test terminal, and the second bias test terminal; when rotated 180° in a plan view; The positions of the first data inspection terminal and the second data inspection terminal are swapped, The positions of the first reset inspection terminal and the second reset inspection terminal are swapped, The positions of the first bias inspection terminal and the second bias inspection terminal are swapped, The positions of the first reset gate inspection terminal and the second reset gate inspection terminal are swapped, Mother board.

8. The first reset wiring and the second reset wiring are connected, The mother board according to claim 7.

9. The first bias wiring and the second bias wiring are connected, The mother board according to claim 7 or 8.

10. A plurality of first gate inspection terminals connected to each of the plurality of first gate terminals and arranged in the inspection terminal region, A plurality of second gate inspection terminals connected to each of the plurality of second gate terminals and arranged in the inspection terminal region, The first gate inspection terminal is arranged outside the first gate terminal, The second gate inspection terminal is arranged outside the second gate terminal, When rotated 180° in plan view, The positions of the first gate inspection terminal and the second gate inspection terminal are swapped, The mother board according to claim 7.

11. The arrangement order in the predetermined first direction of the first gate wiring and the first reset gate wiring connected to one of the pixels arranged in the first region, and the arrangement order in the predetermined first direction of the second gate wiring and the second reset gate wiring connected to one of the pixels arranged in the second region are reversed, The arrangement order in the second direction of the first data wiring, the first reset wiring, and the first bias wiring connected to one of the pixels arranged in the first region, and the arrangement order in the second direction of the second data wiring, the second reset wiring, and the second bias wiring connected to one of the pixels arranged in the second region are reversed, The mother board according to claim 7.

12. The first bias wiring and the second bias wiring are connected, The mother board according to claim 11.

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