Display apparatus

Abstract

To provide a display apparatus with improved aperture ratio and definition.SOLUTION: A display apparatus in an example includes a substrate including a plurality of subpixels, a first light-emitting element disposed in each of the subpixels, a first transistor disposed in each of the subpixels and driving the first light-emitting element, a second light-emitting element disposed between the adjacent subpixels among the plurality of subpixels, and a second transistor disposed in each of the subpixels and driving the second light-emitting element. The gap between the substrate and the second light-emitting element is larger than the gap between the first light-emitting element and the substrate.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] This specification relates to a display device with improved aperture ratio and resolution.

Background Art

[0002] In recent years, with the development of multimedia, the importance of display devices has been increasing. As display devices, various display devices such as liquid crystal display devices and organic electroluminescence display devices have been proposed.

[0003] A display device includes a plurality of pixels each including a plurality of sub-pixels, and a display element is provided for each sub-pixel to display an image. However, in a conventional display device, a structure for partitioning sub-pixels is required, but such a structure is an area where no image is displayed. Therefore, due to such a structure, the aperture ratio of the display device decreases, which becomes a factor hindering the realization of high resolution.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This specification aims to provide a display device with an improved aperture ratio and capable of high resolution.

Means for Solving the Problems

[0005] A display device according to an embodiment includes a substrate including a plurality of pixels each including a plurality of sub-pixels, a first transistor disposed for each sub-pixel, a second transistor disposed between the plurality of sub-pixels, a first light-emitting element disposed for each sub-pixel, and a second light-emitting element disposed between the plurality of sub-pixels, and a gap between the substrate and the second light-emitting element is larger than a gap between the first light-emitting element and the substrate.

[0006] A bank layer is disposed between sub-pixels, and the second light-emitting element is disposed on the bank layer.

[0007] The first light-emitting element includes a first electrode disposed in each sub-pixel, a first light-emitting layer disposed on the first electrode, and a second electrode disposed on the first light-emitting layer. The second light-emitting element includes a third electrode disposed on the bank layer, a second light-emitting layer disposed on the third electrode, and a fourth electrode disposed on the second light-emitting layer. The second electrode and the fourth electrode are integrally formed.

[0008] Between the bank layer and the second light-emitting element, a first pattern and a second pattern of an overhang structure are disposed, and the first light-emitting layer and the second light-emitting layer are disconnected due to the overhang structure.

[0009] The first transistor includes a first semiconductor layer disposed on the buffer layer, a gate insulating layer disposed on the first semiconductor layer, a first gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the first gate electrode, and a first source electrode and a first drain electrode disposed on the interlayer insulating layer. The second transistor includes a second semiconductor layer disposed on the buffer layer, a gate insulating layer disposed on the second semiconductor layer, a second gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the second gate electrode, and a second source electrode and a second drain electrode disposed on the interlayer insulating layer.

[0010] On the first transistor and the second transistor, a planarization layer is formed. The first drain electrode is electrically connected to the first electrode through a first contact hole formed in the planarization layer, and the second drain electrode is electrically connected to the first electrode through a second contact hole formed in the planarization layer, the bank layer, the first pattern, and the second pattern.

Advantages of the Invention

[0011] In the display device according to the present invention, by separately forming light-emitting elements between conventional sub-pixels and / or on a bank layer which is a structure outside the pixel, the actual image display area can be increased. Therefore, the aperture ratio of the display device is improved, and high resolution can be achieved.

[0012] In addition, in the display device according to the present invention, by forming the first pattern and the second pattern of an undercut structure or an overhang structure and simply laminating the light-emitting material, a patterned light-emitting layer can be formed in each sub-pixel, so that the manufacturing method can be simplified.

[0013] Furthermore, since the display device according to the present invention enables high efficiency by improving the aperture ratio, the power consumption can be reduced, and by optimizing the process with a simplified manufacturing method, the production energy can be reduced.

Brief Description of the Drawings

[0014]

Figure 1

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Figure 5

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Figure 8A

Figure 8B

Figure 8C

Figure 8D

Figure 8E

Figure 8F

Figure 8G

Figure 8H

Embodiments for Carrying Out the Invention

[0015] The advantages, features, and the methods for achieving them of the present invention will become clear by referring to the embodiments described in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be configured in various different forms. However, this embodiment is provided to make the disclosure of the present invention complete and to enable those with ordinary knowledge in the technical field to which the present invention pertains to fully understand the scope of the invention. The present invention is defined by the scope of the claims.

[0016] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary and the present invention is not limited thereto. Throughout the specification, the same reference numerals indicate the same components. Also, when explaining the present invention, if it is determined that a specific explanation of related known technologies obscures the gist of the present invention, the detailed explanation thereof will be omitted. When "comprises", "includes", "has", "holds", "becomes", etc. are described in this specification, other parts can be added unless both "only" are described. Also, when a component is described in the singular form, it can be interpreted in the plural form unless otherwise explicitly stated.

[0017] Also, when interpreting a component, even without an explicit description, it shall be considered to include an error range.

[0018] For example, when describing the positional relationship between two components using terms such as "above", "at the upper part", "at the lower part", "horizontally", etc., if it is not described as "directly" or "straight", one or more other components can also be located between the two components.

[0019] Also, in the description of the time relationship, for example, when describing the temporal precedence relationship using terms such as "after", "subsequent to", "next", "before", etc., if it is not described as "directly" or "immediately", non - continuous cases can be included.

[0020] In addition, in order to distinguish components, terms such as "first" and "second" are used, but the components are not limited to such terms. Therefore, the first component mentioned below can also be the second component within the technical idea of the present invention.

[0021] In describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used, but such terms are only used to distinguish components and do not limit the nature, order, sequence, number, etc. of the components. When a certain component is described as "connected", "coupled", or "joined" to another component, the two components can be directly connected, coupled, or joined, but it should be understood that another component may be interposed between the components, and each component may be "connected", "coupled", or "joined" through another component.

[0022] The "display device" in the present invention can include a display device in a narrow sense, such as a display module including a display panel and a driving unit for driving the display panel. Further, it can include electronic equipment displays such as notebook computers, televisions, computer monitors, or automotive displays and other forms of vehicles that are final products (complete product, final product) equipped with a display module, set electronic devices such as mobile electronic devices like smartphones and electronic pads, or set devices (set apparatus).

[0023] Therefore, the display device in the present invention can include the display device itself in a narrow sense, such as a display module, and application products or set devices that are final products equipped with the display module.

[0024] Hereinafter, the present invention will be described in detail with reference to the drawings.

[0025] FIG. 1 is a block diagram schematically showing a display device 100 according to the present invention, and FIG. 2 is a block diagram schematically showing a sub-pixel SP shown in FIG. 1.

[0026] As shown in FIG. 1, the display device 100 includes a video processing unit 102, a timing control unit 104, a gate driving unit 106, a data driving unit 107, a power supply unit 108, and a display panel 109.

[0027] The video processing unit 102 outputs a driving signal for driving any device together with video data from the outside. For example, the driving signal output from the video processing unit 102 can include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, etc.

[0028] The timing control unit 104 receives the supply of a drive signal and the like together with video data from the video processing unit 102. Based on the drive signal input from the video processing unit 102, the timing control unit 104 generates and outputs a gate timing control signal GDC for controlling the operation timing of the gate drive unit 106 and a data timing control signal DDC for controlling the operation timing of the data drive unit 107.

[0029] The gate drive unit 106 outputs a scan signal to the display panel 109 according to the gate timing control signal GDC from the timing control unit 104. The gate drive unit 106 outputs the scan signal through a plurality of gate lines GL1 to GLm. At this time, the gate drive unit 106 can be in the form of an IC (Integrated Circuit), but is not limited thereto. The gate drive unit 106 includes various gate drive circuits, and the gate drive circuit can be directly formed on the substrate of the display panel 109. In this case, the gate drive unit 106 may be a GIP (Gate-In-Panel).

[0030] The data drive unit 107 outputs a data voltage to the display panel 109 according to the data timing control signal DDC input from the timing control unit 104. The data drive unit 107 samples and latches the digital data signal DATA from the timing control unit 104 and converts it into an analog data voltage based on the gamma voltage. The data drive unit 107 outputs the data voltage through a plurality of data lines DL1 to DLn. At this time, the data drive unit 107 can be in the form of an IC, but is not limited thereto.

[0031] The power supply unit 108 outputs a high-potential voltage VDD, a low-potential voltage VSS, etc., and supplies them to the display panel 109. The high-potential voltage VDD is supplied to the display panel 109 through the first power line EVDD, and the low-potential voltage VSS is supplied to the display panel 109 through the second power line EVSS. At this time, the voltage output from the power supply unit 108 may also be output to the gate drive unit 106 and the data drive unit 107 and used for driving them.

[0032] The display panel 109 displays an image according to the data voltage and scan signal supplied from the gate driving unit 106 and the data driving unit 107, and the voltage supplied from the power supply unit 108.

[0033] The display panel 109 is composed of a plurality of sub-pixels SP, and an image is actually displayed. The sub-pixel SP may include a red (Red) sub-pixel, a green (Green) sub-pixel, and a blue (Blue) sub-pixel, or may include a white (White, W) sub-pixel, a red (Red, R) sub-pixel, a green (Green, G) sub-pixel, and a blue (Blue, B) sub-pixel. At this time, the sub-pixels SP of white W, red R, green G, and blue B may all have the same area or may have different areas from each other.

[0034] As shown in FIG. 2, one sub-pixel SP can be connected to a gate line GL1, a data line DL1, a first power line EVDD, and a second power line EVSS. The sub-pixel SP can include a plurality of thin film transistors and a storage capacitor depending on the configuration of the pixel circuit. For example, the sub-pixel SP can be 2 transistors and 1 capacitor 2T1C, but is not limited thereto, and can also be a sub-pixel adopting a configuration such as 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C.

[0035] FIG. 3 is a circuit diagram schematically showing the sub-pixel SP of the display device 100 according to the present invention.

[0036] As shown in FIG. 3, the display device according to the present invention includes a gate wiring GL, a data wiring DL, and a power wiring PL that intersect each other to partition the sub-pixel SP. In the sub-pixel SP, a switching transistor Ts, a driving transistor Td, a storage capacitor Cst, and an organic light emitting element D are arranged.

[0037] The switching transistor Ts is connected to the gate wiring GL and the data wiring DL, the driving transistor Td and the storage capacitor Cst are connected between the switching transistor Ts and the power supply wiring PL, and the organic light-emitting element D is connected to the driving transistor Td.

[0038] In the display device having such a structure, when the switching transistor Ts is turned on by the gate signal applied to the gate wiring GL, the data signal applied to the data wiring DL is applied via the switching transistor Ts to the gate electrode of the driving transistor Td and one electrode of the storage capacitor Cst.

[0039] The driving transistor Td is turned on by the data signal applied to the gate electrode. As a result, a current proportional to the data signal flows from the power supply wiring PL through the driving transistor Td to the organic light-emitting element D, and the organic light-emitting element D emits light with a luminance proportional to the current flowing through the driving transistor Td.

[0040] At this time, the storage capacitor Cst is charged with a voltage proportional to the data signal, so that the voltage of the gate electrode of the driving transistor Td is kept constant during one frame.

[0041] In FIG. 3, only two transistors Td, Ts and one capacitor Cst are shown, but the present invention is not limited thereto, and three or more transistors and two or more capacitors can be provided.

[0042] FIG. 4 is a plan view schematically showing the structure of the display device 100 according to the present invention.

[0043] As shown in FIG. 4, the display device 100 according to the present invention includes a display area AA where an image is actually displayed and a non-display area NA disposed outside the display area AA.

[0044] In the display area AA, a plurality of pixels P are arranged, and each pixel P includes a plurality of sub-pixels SP. At this time, the sub-pixel SP can include a sub-pixel of red R, a sub-pixel of green G, and a sub-pixel of blue B. Further, the sub-pixel SP can further include a sub-pixel of white W.

[0045] Although not shown in FIG. 4, in the display area AA, a plurality of gate lines and data lines are arranged, and the sub-pixel SP is arranged in the intersection area of the gate line and the data line. In each sub-pixel SP, a thin film transistor which is a switching element and a display element for actually reproducing an image are arranged.

[0046] The display element can include various display elements. For example, the display element can be an organic electroluminescence display element, a liquid crystal display element, a quantum dot display element, a micro LED display element, or a mini LED display element.

[0047] In the non-display area NA, a gate driving unit for applying all signals to the sub-pixel SP and a data driving unit can be arranged. The gate driving unit applies a scanning signal to the sub-pixel SP through the gate line, and the data driving unit applies a video signal to the sub-pixel SP through the data line.

[0048] FIG. 5 is a plan view showing the structure of the pixel P in the display device 100 according to the present invention.

[0049] As shown in FIG. 5, the pixel P of the display device 100 according to the present invention includes a first sub-pixel SP1 to a third sub-pixel SP3 and an auxiliary sub-pixel SPa. The first sub-pixel SP1 to the third sub-pixel SP3 are rectangular and can be arranged in the pixel P. In FIG. 5, the first sub-pixel SP1 to the third sub-pixel SP3 have the same area, but they may be formed to have different areas from each other.

[0050] Further, the first sub-pixel SP1 to the third sub-pixel SP3 can be formed in various shapes. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may be in the shape of a rhombus, pentagon, hexagon, or triangle, or may be circular or elliptical. Also, the first sub-pixel SP1 to the third sub-pixel SP3 can have different shapes from each other.

[0051] The auxiliary sub-pixel SPa can be formed along the outer edge of the first sub-pixel SP1 to the third sub-pixel SP3 and / or the sub-pixel SP. That is, the auxiliary sub-pixel SPa can be formed in a region where a structure partitioning the first sub-pixel SP1 to the third sub-pixel SP3 is arranged. Therefore, in the present invention, by forming the auxiliary sub-pixel SPa in a region where an image is not displayed in a conventional display device, the display region of the image can be increased, so that the aperture ratio of the display device 100 can be improved. Further, since an image is displayed in a non-display region of a conventional image, a desired image can be displayed even if the area of the pixel P is reduced, and a high-resolution display device 100 can be realized.

[0052] The first sub-pixel SP1 to the third sub-pixel SP3 can each be a sub-pixel of red R, a sub-pixel of green G, or a sub-pixel of blue B, but is not limited thereto. The auxiliary sub-pixel SPa can be any one of a sub-pixel of red R, a sub-pixel of green G, and a sub-pixel of blue B.

[0053] FIG. 6 is a plan view showing another structure of the pixel P in the display device 100 according to the present invention. In the display device 100 having this structure, the auxiliary sub-pixel SPa can include a plurality of auxiliary sub-pixels SPa1 and SPa2. In FIG. 6, the first auxiliary sub-pixel SPa1 is shown as an outer region of the pixel P, and the second auxiliary sub-pixel SPa2 is shown as a region between the first sub-pixel SP1 to the third sub-pixel SP3, but is not limited thereto. For example, the auxiliary sub-pixel SPa can also be composed of three or more auxiliary sub-pixels.

[0054] The first auxiliary sub-pixel SPa1 and the second auxiliary sub-pixel SPa2 can be auxiliary sub-pixels of different colors from each other. For example, the first auxiliary sub-pixel SPa1 and the second auxiliary sub-pixel SPa2 may be sub-pixels of different colors among the red R sub-pixel, the green G sub-pixel, and the blue B sub-pixel.

[0055] FIG. 7 is a cross-sectional view specifically showing the display device 100 according to an embodiment of the present invention. For convenience of explanation, only one sub-pixel SP and one auxiliary sub-pixel SPa are shown in FIG. 7.

[0056] As shown in FIG. 7, the substrate 140 includes a plurality of sub-pixels SP and auxiliary sub-pixels SPa. The substrate 140 may be made of a hard material such as glass, or may be made of a plastic-based material having flexibility.

[0057] When the substrate 140 is made of a plastic-based material, the substrate 140 can be formed of at least one or more of polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, and polycarbonate, but is not limited thereto.

[0058] For example, when the substrate 140 is made of polyimide, it can be composed of a plurality of polyimides, and an inorganic layer can be further disposed between the polyimides, but is not limited thereto.

[0059] A buffer layer 142 is formed on the substrate 140. The buffer layer 142 is formed over the entire substrate 140, and can play a role of improving the adhesion between the layer formed thereon and the substrate 140 and blocking an alkali component or the like flowing out of the substrate 140. Further, the buffer layer 142 can delay the diffusion of moisture or oxygen that has penetrated into the substrate 140.

[0060] The buffer layer 142 can be a single layer or a multilayer made of SiNx or SiOx. When the buffer layer 142 is a multilayer, SiNx and SiOx may be alternately formed. The buffer layer 142 can also be omitted based on the type and material of the substrate 140, the structure and type of the thin film transistor, etc.

[0061] A first thin film transistor T1 is arranged on the sub-pixel SP on the buffer layer 142, and a second thin film transistor T2 is arranged on the auxiliary sub-pixel SPa. For the convenience of explanation, among various thin film transistors, only the driving thin film transistor is shown in the figure, but other thin film transistors such as switching transistors can also be included. Also, although a thin film transistor with a top gate structure is shown, it is not limited thereto, and other structures such as a bottom gate structure can also be adopted.

[0062] The first thin film transistor T1 includes a first semiconductor layer 112 arranged on the buffer layer 142, a gate insulating layer 144 formed on the first semiconductor layer 112, a first gate electrode 113 arranged on the gate insulating layer 144, an interlayer insulating layer 146 formed on the first gate electrode 113, a first source electrode 115 and a first drain electrode 116 arranged on the interlayer insulating layer 146.

[0063] The second thin film transistor T2 includes a second semiconductor layer 162 arranged on the buffer layer 142, a gate insulating layer 144 formed on the second semiconductor layer 162, a second gate electrode 163 arranged on the gate insulating layer 144, an interlayer insulating layer 146 formed on the second gate electrode 163, a second source electrode 165 and a second drain electrode 166 arranged on the interlayer insulating layer 146.

[0064] The first semiconductor layer 112 and the second semiconductor layer 162 can each be made of a polycrystalline semiconductor. For example, the polycrystalline semiconductor may be made of low temperature poly silicon (LTPS) with high mobility, but is not limited thereto.

[0065] Further, the first semiconductor layer 112 and the second semiconductor layer 162 may be made of an oxide semiconductor. For example, it may be made of any one of IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IGO (Indium Gallium Oxide), but is not limited thereto.

[0066] The first semiconductor layer 112 and the second semiconductor layer 162 may each be made of a different material. For example, the first semiconductor layer 112 may be composed of an oxide semiconductor, and the second semiconductor layer 162 may be composed of a polycrystalline semiconductor. Conversely, the first semiconductor layer 112 may be composed of a polycrystalline semiconductor, and the second semiconductor layer 162 may be composed of an oxide semiconductor.

[0067] The first semiconductor layer 112 may include a first channel region 112a in its central region, and a first source region 112b and a first drain region 112c which are doped layers on both sides thereof. The second semiconductor layer 162 may include a second channel region 162a in its central region, and a second source region 162b and a second drain region 162c which are doped layers on both sides thereof.

[0068] The gate insulating layer 144 may be a single layer or a multilayer made of an inorganic material such as SiNx or SiOx, but is not limited thereto.

[0069] The interlayer insulating layer 146 may be a single layer or a multilayer made of an organic material such as photoacrylic or an inorganic material such as SiNx or SiOx. Further, the interlayer insulating layer 146 may be a multilayer composed of an organic layer and an inorganic layer, but is not limited thereto.

[0070] The first source electrode 115, the second source electrode 165, the first drain electrode 116, and the second drain electrode 166 can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but are not limited thereto. The first source electrode 115, the second source electrode 165, the first drain electrode 116, and the second drain electrode 166 are each connected to the first source region 112b and the second source region 162b, and the first drain region 112c and the second drain region 162c in the first semiconductor layer 112 and the second semiconductor layer 162 through contact holes formed in the gate insulating layer 144 and the interlayer insulating layer 146, respectively, and can be in contact therewith.

[0071] Although not shown in the figure, a bottom shield metal layer can be disposed on the substrate 140 below the first semiconductor layer 112 and the second semiconductor layer 162. The bottom shield metal layer is for minimizing the back channel effect caused by charges trapped in the substrate 140 and preventing afterimages and performance degradation of the transistor, and can be a single layer or a multilayer made of molybdenum (Mo), titanium (Ti), or an alloy thereof, but is not limited thereto.

[0072] A planarization layer 148 is formed on the substrate 140 on which the first thin film transistor T1 and the second thin film transistor T2 are disposed. The planarization layer 148 may be made of an organic layer such as photoacrylic, but is not limited thereto, and can also be a multilayer made of an inorganic layer and an organic layer.

[0073] A first light emitting element D1 is disposed on the sub-pixel SP on the planarization layer 148. The first light emitting element D1 is composed of a first electrode 132, a first light emitting layer 134, and a second electrode 136.

[0074] The first electrode 132 can be an anode. The first electrode 132 is disposed on the planarization layer 148 and is electrically connected to the first drain electrode 116 of the first thin-film transistor T1 through the first contact hole H1 formed in the planarization layer 148. The first electrode 132 can be composed of at least one or more of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof. Further, the first electrode 132 may be a transparent metal oxide layer such as ITO or IZO.

[0075] When the display device 100 is a top emission type, since the first electrode 132 serves as a reflective electrode for reflecting light, it can further contain an opaque conductive material. When the display device 100 is a bottom emission type, the first electrode 132 can use a transparent conductive material that transmits light, such as ITO or IZO.

[0076] On the planarization layer 148 in the auxiliary sub-pixel SPa, a bank layer BNK is formed. The bank layer BNK can be a partition wall that partitions the sub-pixels SP. The bank layer BNK can be composed of at least one or more of inorganic insulating materials such as SiNx and SiOx, or organic insulating materials such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin, or a photosensitive agent containing a black (or dark color) pigment, but is not limited thereto.

[0077] On the bank layer BNK, a first pattern 172 and a second pattern 174 are formed. The width of the first pattern 172 is formed smaller than that of the second pattern 174, and an undercut or overhang structure is formed at the boundary between the first pattern 172 and the second pattern 174, where a reverse step is formed.

[0078] The first pattern 172 can be composed of an inorganic insulating material such as SiNx or SiOx, and the second pattern 174 can be composed of amorphous silicon, but is not limited thereto.

[0079] The first light-emitting layer 134 is formed on the upper surface of the first electrode 132 that is exposed to the outside through the opening region between the bank layers BNK. Although it will be described in detail later, the first light-emitting layer 134 is formed simultaneously in a plurality of sub-pixels SP by the same process. However, due to the overhang structures of the first pattern 172 and the second pattern 174, the organic layer 134 between adjacent sub-pixels SP is disconnected.

[0080] In other words, although the light-emitting layer 134 is formed over the entire substrate 140, due to the overhang structures of the first pattern 172 and the second pattern 174, the first light-emitting layers 134 are disconnected from each other. Therefore, the first light-emitting layer 134 formed in each sub-pixel SP is disconnected from the first light-emitting layer of the adjacent sub-pixel SP.

[0081] For example, the first light-emitting layer 134 can be composed of an organic light-emitting layer. Alternatively, instead of the organic light-emitting layer, an inorganic light-emitting layer, for example, a nano-sized material layer, quantum dots, a micro LED light-emitting layer, a mini LED light-emitting layer can be used, but it is not limited thereto.

[0082] When the first light-emitting layer 134 is an organic light-emitting layer, the first light-emitting layer 134 is composed of a blue organic light-emitting layer and a yellow fluorescent layer, and white light is emitted from the first light-emitting layer 134. Also, the first light-emitting layer 134 can have a multi-stack structure. For example, when the first light-emitting layer 134 has a triple-stack structure, two charge generation layers can be interposed, and the first stack to the third stack can be arranged. The first stack to the third stack can be composed of an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, respectively. For example, the organic light-emitting layer of the first stack can emit red light, the organic light-emitting layer of the second stack can emit blue light, and the organic light-emitting layer of the third stack can emit green light.

[0083] On the upper part of the bank layer BNK in the auxiliary sub-pixel SPa, that is, on the second pattern 174, a second light-emitting element D2 is arranged. The second light-emitting element D2 is composed of a third electrode 137, a second light-emitting layer 138, and a fourth electrode 139. As shown in FIG. 7, the vertical gap (that is, the interval or distance in the direction perpendicular to the plane of the substrate) between the substrate 140 and the first light-emitting element D1 is smaller than the corresponding gap between the substrate 140 and the second light-emitting element D2.

[0084] The third electrode 137 can be an anode. The third electrode 137 is arranged on the second pattern 174 and is electrically connected to the second drain electrode 166 of the second thin-film transistor T2 through a second contact hole H2 formed in the first pattern 172, the second pattern 174, the bank layer BNK, and the planarization layer 148. The third electrode 137 can be composed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof. Also, the third electrode 137 may be a transparent metal oxide layer such as ITO or IZO.

[0085] The third electrode 137 may be composed of the same material as the first electrode of the first light-emitting element D1, or may be composed of a different material.

[0086] When the display device 100 is a top emission type, since the third electrode 137 serves as a reflective electrode that reflects light, it can further contain an opaque conductive material. When the display device 100 is a bottom emission type, the third electrode 137 can use a transparent conductive material that transmits light, such as ITO or IZO.

[0087] The second light-emitting layer 138 is formed on the second electrode 137. At this time, since the second light-emitting layer 138 is formed on the first pattern 172 and the second pattern 174 having an overhang structure, the second light-emitting layer 138 formed in the auxiliary sub-pixel SPa is disconnected from the first light-emitting layer 134 formed in the sub-pixel SP. Therefore, it is possible to block the flow of the side current between the first light-emitting layer 134 of the sub-pixel SP and the second light-emitting layer 138 of the auxiliary sub-pixel SPa.

[0088] Similar to the first light-emitting layer 134, the second light-emitting layer 138 can be composed of an organic light-emitting layer, a nano-sized material layer, quantum dots, a micro-LED light-emitting layer, or a mini-LED light-emitting layer. Further, the second light-emitting layer 138 can have a multi-stack structure.

[0089] That is, the second light-emitting layer 138 may be formed in the same structure using the same material as the first light-emitting layer 134, or may be formed in a different structure using a different material.

[0090] The fourth electrode 139 can be a cathode. The fourth electrode 138 is disposed on the second light-emitting layer 138 and can be a single layer or a multi-layer made of a metal or an alloy of a metal. Further, the fourth electrode 139 can use a transparent metal oxide such as ITO or IZO, but is not limited thereto.

[0091] The fourth electrode 139 can be formed integrally with the second electrode 136. That is, a metal or a metal oxide can be laminated over the entire substrate 140 to integrally form a common cathode in the sub-pixel SP and the auxiliary sub-pixel SPa.

[0092] A sealing layer 180 is formed on the sub-pixels SP and the auxiliary sub-pixels SPa, and the first light-emitting element D1 and the second light-emitting element D2 are sealed. When the first light-emitting element D1 and the second light-emitting element D2 are exposed to moisture or oxygen, pixel shrinkage may occur in which the light-emitting region shrinks, or problems such as black dots may occur in the light-emitting region. In addition, moisture and oxygen oxidize the electrodes made of metal. The sealing layer 180 blocks the penetration of moisture and oxygen from the outside and prevents problems in the first light-emitting element D1, the second light-emitting element D2, and all electrodes.

[0093] The sealing layer 180 can be composed of a first sealing layer 182, a second sealing layer 184, and a third sealing layer 186, but is not limited thereto, and can also be two layers or four or more layers.

[0094] The first sealing layer 182 and the third sealing layer 186 can be a single layer or multiple layers made of inorganic substances such as SiOx, SiNx, and SiON, and can further contain an organic substance between inorganic substances such as SiOx, SiNx, and SiON, but is not limited thereto. The second sealing layer 184 can be composed of an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxycarbide (SiOC), but is not limited thereto. The third sealing layer 186 can be composed of a thin-film metal (Face Seal Metal), but is not limited thereto.

[0095] Although not shown in the figure, a touch member can be arranged. The touch member is arranged in the display area and can sense touch input. The touch member can sense external touch information using a user's finger, a touch pen, or the like.

[0096] As described above, in the display device 100 according to the present invention, an auxiliary sub-pixel SPa is separately formed between the conventional sub-pixels SP and on the structure outside the pixel, that is, on the bank layer BNK, and the second light-emitting element D2 is formed on the auxiliary sub-pixel SPa, so that the actual image display area can be increased. Therefore, the aperture ratio of the display device 100 can be improved, and a high-resolution display device 100 can be realized.

[0097] Hereinafter, a method for manufacturing the display device 100 according to an embodiment of the present invention will be described in detail.

[0098] FIGS. 8A to 8H are diagrams showing a method for manufacturing the display device 100 according to an embodiment of the present invention. The figures show two sub-pixels SP1, SP2, and one auxiliary sub-pixel SPa2.

[0099] First, as shown in FIG. 8A, a buffer layer 142 is formed over the entire substrate 140 including a plurality of sub-pixels SP1, SP2, and the auxiliary sub-pixel SPa. The substrate 140 may be made of a hard material such as glass, or may be made of a plastic material such as polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate. The buffer layer 142 can be formed by laminating a single layer or multiple layers made of SiNx or SiOx.

[0100] Next, in each of the sub-pixels SP1, SP2, and the auxiliary sub-pixel SPa on the buffer layer 142, a polycrystalline semiconductor such as polysilicon, or an oxide semiconductor such as IGZO, IZO, IGTO, and IGO is laminated, and then etching is performed to form a first semiconductor layer 112 in each of the sub-pixels SP1, SP2, and a second semiconductor layer 162 in the auxiliary sub-pixel SPa. Further, impurities are doped on both side surfaces of the first semiconductor layer 112 and the second semiconductor layer 162 to form a first channel region 112a and a second channel region 162a, a first source region 112b and a second source region 162b, and a first drain region 112c and a second drain region 162c.

[0101] Thereafter, inorganic substances such as SiOx and SiNx are laminated to form the gate insulating layer 144. Then, metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) are laminated by sputtering, etched by a wet etching method, and a first gate electrode 113 is formed on each of the sub-pixels SP1 and SP2, and a second gate electrode 163 is formed on the auxiliary sub-pixel SPa. Thereafter, an organic substance such as photoacrylic or an inorganic substance such as SiNx or SiOx is laminated on the first gate electrode 113 and the second gate electrode 163 to form the interlayer insulating layer 146. Then, the interlayer insulating layer 146 above the first source region 112b and the first drain region 112c of the first semiconductor layer 112 is dry-etched, and the interlayer insulating layer 146 above the second source region 162b and the second drain region 162c of the second semiconductor layer 162 is dry-etched to form contact holes in each of them.

[0102] Subsequently, metals such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy are laminated by sputtering and etched, and a first source electrode 115 and a first drain electrode 116 that are ohmic contact with the first source region 112b and the first drain region 112c of the first semiconductor layer 112 through the contact holes are formed on each of the sub-pixels SP1 and SP2, respectively, and a second source electrode 165 and a second drain electrode 166 that are ohmic contact with the second source region 162b and the second drain region 162c of the second semiconductor layer 162 through the contact holes are formed on the auxiliary sub-pixel SPa.

[0103] Thereafter, as shown in FIG. 8B, an organic material such as photoacrylic is laminated on the first source electrode 115, the second source electrode 165, the first drain electrode 116, and the second drain electrode 166 to form a planarization layer 148. After that, dry etching is performed on the planarization layer 148 on the drain electrode 116 to form a first contact hole T1. Subsequently, a metal such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, or a metal oxide such as ITO or IZO is laminated by sputtering, and wet etching is performed to form a first electrode 132 on the upper surface of the planarization layer 148 in the sub-pixels SP1 and SP2. At this time, the first electrode 132 is electrically connected to the first drain electrode 116 of the first thin film transistor T1 through the first contact hole T1.

[0104] Next, an inorganic insulating material such as SiNx or SiOx, or an organic insulating material such as BCB, acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or a photosensitive agent containing a black (or dark color) pigment is laminated on the ends of the planarization layer 148 and the first electrode 132, and dry etching is performed to form a bank layer BNK.

[0105] At this time, the bank layer BNK is formed in a matrix shape across the entire substrate 140 and overlaps with the ends of the first electrode 132, so that the first electrode 132 is exposed to the outside through the opening region between the bank layers BNK.

[0106] Thereafter, as shown in FIG. 8C, a first insulating layer 172a and a second insulating layer 174a are continuously vapor-deposited across the entire substrate 140, and a photoresist is laminated thereon for patterning to form a photoresist pattern 190. At this time, the photoresist pattern 190 is removed in the first sub-pixel SP1 and is formed only on the upper parts of the second sub-pixel SP2 and the auxiliary sub-pixel SPa.

[0107] Next, as shown in FIG. 8D, using the photoresist pattern 190, the underlying first insulating layer 172a and second insulating layer 174a are etched to form a first insulating pattern 172b and a second insulating pattern 174b. The first insulating layer 172a can be formed by laminating inorganic substances such as SiNx or SiOx, and the second insulating layer 174a can be formed of amorphous silicon or the like, but is not limited thereto.

[0108] The second insulating layer 174a made of inorganic substances such as SiNx or SiOx is etched by dry etching, and the first insulating layer 172a made of amorphous silicon or the like is etched by wet etching. When performing wet etching, the first insulating layer 172a is isotropically etched, and a part of the first insulating layer 172a below the second insulating pattern 174b is also etched, and the first insulating pattern 172b is formed with a smaller width than the second insulating pattern 174b above it. As a result, the first insulating pattern 172b and the second insulating pattern 174b adjacent to the first sub-pixel SP1 have an undercut structure or an overhang structure.

[0109] Thereafter, a light-emitting substance, for example, an organic light-emitting substance, is laminated over the entire substrate 140, and a first light-emitting layer 134 is formed on the first electrode 132 of the first sub-pixel SP1 not blocked by the first insulating pattern 172b and the second insulating pattern 174b, and a light-emitting pattern 134a is formed on the first insulating pattern 172b and the second insulating pattern 174b. At this time, due to the undercut structure or overhang structure of the first insulating pattern 172b and the second insulating pattern 174b, the first light-emitting layer 134 and the light-emitting pattern 134a are in a disconnected state from each other.

[0110] Next, as shown in FIG. 8E, the light-emitting pattern 134a on the first insulating pattern 172b and the second insulating pattern 174b is removed.

[0111] Thereafter, the processes of FIGS. 8C to 8E are repeated, and as shown in FIG. 8F, a first light-emitting layer 134 is formed on the first electrode 132 of the second sub-pixel SP2.

[0112] When the pixel P of the display device includes three sub-pixels SP of R, G, and B, the processes of FIGS. 8C to 8E are repeated three times, and the first light-emitting layer 134 is formed on each of the R, G, and B sub-pixels SP. When the pixel P of the display device includes four sub-pixels SP, the processes of FIGS. 8C to 8E are repeated four times, and the first light-emitting layer 134 is formed on each of the sub-pixels SP.

[0113] Thereafter, as shown in FIG. 8G, a second contact hole T2 is formed in the planarization layer 148, the bank layer BNK, the first pattern 172, and the second pattern 174 above the second drain electrode 166 of the second thin-film transistor T2 disposed in the auxiliary sub-pixel SPa. Over the entire substrate 140, a metal, its alloy, or a metal oxide is laminated and etched to form a third electrode 137 electrically connected to the second drain electrode 166 on the second pattern 174 of the auxiliary sub-pixel SPa.

[0114] Next, a light-emitting material is laminated and patterned over the entire substrate 140 to form a second light-emitting layer 138 on the third electrode 137.

[0115] Thereafter, a metal or a metal oxide is laminated over the entire substrate 140, and a second electrode 136 is formed on the first light-emitting layer 134 of the sub-pixels SP1 and SP2, and a fourth electrode 139 is formed on the second light-emitting layer 138 of the auxiliary sub-pixel SPa.

[0116] Since the second electrode 136 and the fourth electrode 139 are formed on the first light-emitting layer 134 of the sub-pixels SP1 and SP2, on the second light-emitting layer 138 of the auxiliary sub-pixel SPa, and on the side surfaces of the bank layer BNK, the first pattern 172, and the second pattern 174, a continuous common cathode can be formed.

[0117] Next, as shown in FIG. 8H, an inorganic material is applied over the entire substrate 140 to form a first sealing layer 182, an organic material is applied over the first sealing layer 182 to form a second sealing layer 184, and then an inorganic material is applied over the second sealing layer 184 to form a third sealing layer 186, thereby completing the sealing layer 180 that seals the display device 100.

[0118] As described above, in the display device 100 according to the present invention, by forming the first pattern 172 and the second pattern 174 having an undercut structure or an overhang structure and simply laminating the light-emitting material, the first light-emitting layer 134 patterned for each sub-pixel can be formed, so that the manufacturing method can be simplified as compared with the prior art.

[0119] As described above, the embodiments of the present invention have been described in more detail with reference to the drawings. However, the present invention is not necessarily limited to these embodiments. The present invention can be variously modified within the scope not departing from the technical idea of the present invention. Therefore, the embodiments disclosed herein are not for limiting the technical idea of the present invention, but for explaining it, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the above-described embodiments should all be understood as exemplary and non-limiting.

Description of Reference Numerals

[0120] 112, 162... semiconductor layer 113, 163... gate electrode 115, 165... source electrode 116, 166... drain electrode 132... first electrode 134, 138... light-emitting layer 136... second electrode 137... third electrode 139... fourth electrode 140... substrate 142... buffer layer 144... gate insulating layer 146... interlayer insulating layer 148... planarization layer 172, 174... pattern 180... sealing layer Light-emitting elements D1, D2...

Claims

1. A substrate including a plurality of pixel regions each having a plurality of sub-pixel regions, a first light-emitting element disposed in each of the plurality of sub-pixel regions, a first transistor for driving the first light-emitting element, a second light-emitting element disposed between the adjacent sub-pixel regions of the plurality of sub-pixel regions, and a second transistor disposed between the plurality of sub-pixel regions for driving the second light-emitting element, a display device in which a gap between the substrate and the second light-emitting element is larger than a gap between the first light-emitting element and the substrate.

2. The display device according to claim 1, further including a bank layer disposed between the sub-pixel regions.

3. The display device according to claim 2, wherein the bank layer includes a plurality of opening regions formed therethrough, and the plurality of sub-pixel regions correspond to the plurality of opening regions.

4. The display device according to claim 3, wherein the first light-emitting element is disposed in each of the plurality of opening regions.

5. The display device according to any one of claims 2 to 4, wherein the second light-emitting element is disposed on the bank layer.

6. The first light-emitting element includes a first electrode disposed in each of the plurality of sub-pixel regions, a first light-emitting layer disposed on the first electrode, and a second electrode disposed on the first light-emitting layer.

7. The second light-emitting element includes a third electrode disposed on the bank layer, a second light-emitting layer disposed on the third electrode, and a fourth electrode disposed on the second light-emitting layer.

8. The display device according to claim 7, wherein the second electrode and the fourth electrode are integrally formed.

9. A first pattern and a second pattern are disposed between the bank layer and the second light-emitting element.

10. The display device according to claim 9, wherein the first pattern and the second pattern have an overhang structure that forms a step on the bank layer.

11. The display device according to claim 10, wherein the first light-emitting layer and the second light-emitting layer are not connected by the overhang structure.

12. The first transistor includes a first semiconductor layer disposed on the buffer layer, a gate insulating layer disposed on the first semiconductor layer, a first gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the first gate electrode, and a first source electrode and a first drain electrode disposed on the interlayer insulating layer. The second transistor includes a second semiconductor layer disposed on the buffer layer, the gate insulating layer disposed on the second semiconductor layer, a second gate electrode disposed on the gate insulating layer, the interlayer insulating layer disposed on the second gate electrode, and a second source electrode and a second drain electrode disposed on the interlayer insulating layer. The display device according to claim 9.

13. Further includes a planarization layer covering the first transistor and the second transistor. The first drain electrode is electrically connected to the first electrode through a first contact hole formed in the planarization layer. The display device according to claim 12.

14. The second drain electrode is electrically connected to the third electrode through a second contact hole formed in the planarization layer, the bank layer, the first pattern, and the second pattern. The display device according to claim 13.

15. A substrate including a plurality of pixel regions each having a plurality of sub-pixel regions and at least one or more auxiliary sub-pixel regions, A first light-emitting element disposed in each of the sub-pixel regions and constituting a sub-pixel, A second light-emitting element disposed in the auxiliary sub-pixel region and constituting an auxiliary sub-pixel, A first transistor for driving the first light-emitting element, A second transistor for driving the second light-emitting element, and A display device in which a gap between the substrate and the second light-emitting element is larger than a gap between the first light-emitting element and the substrate.

16. A first auxiliary sub-pixel disposed between the plurality of sub-pixel regions, and A second auxiliary sub-pixel formed outside the pixel. The display device according to claim 15.

17. Further includes a bank layer formed between the plurality of sub-pixels and at the outer edge of the pixel, The second light-emitting element is disposed on the bank layer. The display device according to claim 16.

18. The bank layer includes a plurality of opening regions formed through the bank layer, and the plurality of sub-pixel regions correspond to the plurality of opening regions. The display device according to claim 17.

19. The display device according to claim 18, wherein the first light-emitting element is disposed in each of the plurality of opening regions.

20. The display device according to claim 16, wherein the second light-emitting element disposed in the first auxiliary sub-pixel and the second auxiliary sub-pixel emits light of the same color.

21. The display device according to claim 16, wherein the second light-emitting element disposed in the first auxiliary sub-pixel and the second auxiliary sub-pixel emits light of different colors from each other.

Images