Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of a semiconductor device by reducing the operating voltage of a ferroelectric memory comprising a ferroelectric film.SOLUTION: An insulating film IF1 that is a paraelectric film, a ferroelectric film FEF that is a laminate comprising three or more ferroelectric layers FE1 to FE4 on the insulating film IF1, and a metal film MF and a gate electrode GE on the ferroelectric film FEF, are formed on a semiconductor board SB. Impurity particles GR are provided discretely between the ferroelectric layers in contact with each other, of the ferroelectric layers FE1 to FE4, to increase the crystallinity of the ferroelectric film FEF.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a ferroelectric memory cell and a method for manufacturing the same.

Background Art

[0002] In recent years, as a semiconductor memory device that operates at a low voltage, a ferroelectric memory cell using a ferroelectric film has been developed. The ferroelectric memory cell is a non-volatile memory cell that changes the write state and the erase state by controlling the direction of polarization of the ferroelectric. Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2019-201172) describes the structure and manufacturing method of a ferroelectric memory cell.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As the ferroelectric film, hafnium-based Hf 0.5 Zr 0.5 O2 (HZO) is widely known. However, in the structure of the existing HZO film, there is a problem that it is difficult to reduce the operating voltage of the ferroelectric memory cell.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] Among the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

[0007] A semiconductor device according to an embodiment is a ferroelectric memory cell including a paraelectric film provided in sequence on a semiconductor substrate and a ferroelectric film that is a laminate composed of three or more ferroelectric layers.

[0008] A method for manufacturing a semiconductor device according to an embodiment includes forming a paraelectric film, a stacked structure, and a metal film in sequence on a semiconductor substrate, and then performing a heat treatment. The stacked structure is formed by repeating at least three times a process of forming an amorphous layer and a process of discretely providing a plurality of impurity particles on the surface of the amorphous layer. In the process of performing the heat treatment, each of the amorphous layers is crystallized in a planar direction to form a ferroelectric stacked film.

Advantages of the Invention

[0009] According to one embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a partial or entire modification example, details, supplementary explanation, etc. of the other. Further, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, amount, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to the mentioned number, and it may be more or less than the mentioned number.

[0012] Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified and unless it is considered clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly not the case in principle, it includes those substantially approximating or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0013] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

[0014] Further, hereinafter, the direction along the main surface of the semiconductor substrate may be referred to as the planar direction, and the direction perpendicular to the main surface of the semiconductor substrate may be referred to as the thickness direction.

[0015] (Embodiment 1) <Summary of Embodiment> FIG. 1 shows a schematic cross-sectional view of the main components of the semiconductor device of this embodiment. FIG. 1 mainly shows the stacked structure between the semiconductor substrate and the gate electrode of the ferroelectric memory cell. As shown in FIG. 1, the semiconductor device of this embodiment has a semiconductor substrate SB. The semiconductor substrate SB includes a first main surface that is the upper surface and a second main surface that is the lower surface on the opposite side of the first main surface. On the first main surface of the semiconductor substrate SB, an insulating film IF1 that is a paraelectric film, a ferroelectric film FEF composed of a plurality of ferroelectric layers, a metal film MF, and a gate electrode GE are laminated in this order.

[0016] The ferroelectric film FEF is composed of ferroelectric layers FE1, FE2, FE3, and FE4 laminated in order from the semiconductor substrate SB side upward. That is, the ferroelectric film FEF includes a stacked layer composed of three or more ferroelectric layers laminated in order from the semiconductor substrate SB side. A plurality of impurity particles GR are discretely present between the ferroelectric layer FE1 and the ferroelectric layer FE2, between the ferroelectric layer FE2 and the ferroelectric layer FE3, and between the ferroelectric layer FE3 and the ferroelectric layer FE4.

[0017] Hereinafter, the fact that the ferroelectric film has three or more ferroelectric layers as described above enhances the crystallinity of the ferroelectric film of the ferroelectric memory cell, and thereby reduces the operating voltage of the ferroelectric memory cell will be described.

[0018] <Structure of Semiconductor Device> Figure 2 shows the specific structure of a ferroelectric memory cell, which is a semiconductor device according to the present embodiment. The ferroelectric memory cell shown in Figure 2 has a semiconductor substrate SB having a first main surface and a second main surface. The semiconductor substrate SB is made of, for example, p-type single crystal silicon (Si) having a specific resistance of about 1 to 10 Ωcm. In the semiconductor substrate SB, a p-type well region PW is formed that reaches a predetermined depth from the first main surface side toward the second main surface side. On the first main surface of the semiconductor substrate SB, a plurality of element isolation parts STI are formed that reach a predetermined depth toward the second main surface side. The element isolation part STI is configured by embedding an insulating film such as a silicon oxide film in a groove formed in the semiconductor substrate SB.

[0019] In the present embodiment, as a ferroelectric memory cell, a memory cell called an MFIS (Metal Ferroelectric Insulator Semiconductor) structure in which a ferroelectric film FEF is applied to a transistor structure is exemplified.

[0020] On the semiconductor substrate SB including the well region PW, an insulating film IF1 is formed as a dielectric film. The insulating film IF1 is, for example, a silicon oxide (SiO2) film or a silicon oxynitride (Si3NO4) film, and has a thickness of, for example, 2 nm or less. The insulating film IF1 is a film provided for the purpose of stabilizing the interface between the semiconductor substrate SB and the ferroelectric film FEF, or for the purpose of preventing electrons from entering the ferroelectric film FEF from the semiconductor substrate SB when a voltage is applied to the gate electrode GE during the operation of the ferroelectric memory cell.

[0021] On the insulating film IF1, a ferroelectric film FEF is formed. The ferroelectric film FEF has ferroelectric layers FE1, FE2, FE3, and FE4 laminated in order from the semiconductor substrate SB side, and a plurality of impurity particles GR existing between these ferroelectric layers.

[0022] Each of the ferroelectric layers FE1 to FE4 is made of a metal oxide film and is a high dielectric constant layer having a dielectric constant higher than that of, for example, a silicon nitride film. Also, the thickness of each of the ferroelectric layers FE1 to FE4 is, for example, 0.5 nm or more and 2 nm or less. The thickness of the ferroelectric film FEF is, for example, 6 nm or more and 20 nm or less.

[0023] In addition, each of the ferroelectric layers FE1 to FE4 is an insulating layer composed of a ferroelectric material, which is a material in which dielectric polarization occurs when an electric field is applied and the polarization does not become zero even when the electric field is removed. That is, polarization remains in the ferroelectric layers FE1 to FE4 (ferroelectric film FEF) even when no electric field is applied. A ferroelectric is a material in which electric dipoles are aligned even without an external electric field and the direction of the dipoles can be changed by an electric field.

[0024] And each of the ferroelectric layers FE1 to FE4 needs to be a cubic crystal. In other words, a film mainly composed of crystals other than cubic crystals is a paraelectric film. Therefore, in a ferroelectric memory cell, in order to increase the remnant polarization of the ferroelectric film FEF, improve the performance as a ferroelectric, and reduce the driving power of the ferroelectric memory cell, it is necessary to form the crystals constituting the ferroelectric layers FE1 to FE4 as cubic crystals as much as possible. That is, it is necessary to enhance the crystallinity of the ferroelectric layers FE1 to FE4.

[0025] Each of the ferroelectric layers FE1 to FE4 is an insulating film (HZO film) made of a material containing a metal oxide and a first element. This metal oxide is, for example, hafnium oxide (HfO) or gallium oxide (GaO). The first element is zirconium (Zr), silicon (Si), germanium (Ge), yttrium (Y), lanthanum (La), or ytterbium (Yb).

[0026] Between the ferroelectric layer FE1 and the ferroelectric layer FE2, a plurality of impurity particles GR are formed as part of the ferroelectric film FEF. As will be described later, the plurality of impurity particles GR function as crystal nuclei for growing the ferroelectric layers FE1 to FE4 from an amorphous state to a columnar crystal during the manufacturing process of the ferroelectric film FEF. Therefore, the plurality of impurity particles GR are separated from each other and are arranged discretely. In other words, the plurality of impurity particles GR are not arranged discontinuously in the direction along the first main surface of the semiconductor substrate SB, unlike the continuously formed films such as the ferroelectric layers FE1 to FE4. If each of the plurality of impurity particles GR is connected and formed as a film, the function as crystal nuclei of the plurality of impurity particles GR will be reduced.

[0027] The plurality of impurity particles GR contain a second element different from both oxygen and the first element. The second element is silicon (Si), aluminum (Al), carbon (C), nitrogen (N), hydrogen (H), or oxygen (O). Specifically, the plurality of impurity particles GR are any one of aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen, or oxygen, or a mixture or compound thereof. In the present embodiment, each of the plurality of impurity particles GR is composed of, for example, one atom, a compound, or an aggregate of 2 to 4 atoms. Here, mainly the case where the impurity particle GR is a grain of AlN (aluminum nitride) will be described.

[0028] Also, during the manufacturing process of the ferroelectric film FEF, the plurality of impurity particles GR may be combined with the substances contained in the ferroelectric layers FE1, FE2, FE3, or FE4 near the interface between the upper and lower ferroelectric layers. That is, finally, the plurality of impurity particles GR may be compounds in which aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen, or oxygen is combined with hafnium or the first element.

[0029] The areal density of the plurality of impurity particles GR is from 1×10 12 / cm 2 to 1×10 13 / cm2 is within the range. Also, the volume density of the plurality of impurity particles GR is 1×10 18 / cm 3 to 1×10 21 / cm 3 is within the range. The average distance between the plurality of impurity particles GR in plan view is 2.5 nm or more and 11 nm or less.

[0030] A metal film MF is formed on the ferroelectric film FEF. The metal film MF is a conductive film made of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. The thickness of the metal film MF is, for example, 2 nm to 10 nm. The metal film MF is a cap film provided to apply stress to the ferroelectric layers FE1 to FE4 and control the crystal orientation of each of the ferroelectric layers FE1 to FE4 during the manufacturing process of the ferroelectric film FEF. Therefore, after the formation of the ferroelectric film FEF, if each of the ferroelectric layers FE1 to FE4 can exist as a cubic crystal, the metal film MF may be removed. However, since the crystal orientation of each of the ferroelectric layers FE1 to FE4 may vary when the metal film MF is removed, it is more preferable to leave the metal film MF. Note that when the metal film MF is left, the metal film MF also functions as a part of the gate electrode GE described later.

[0031] A gate electrode GE is formed on the metal film MF. The gate electrode GE is a conductive film made of, for example, a polycrystalline silicon film into which n-type impurities are introduced. As the material constituting the gate electrode GE, instead of the polycrystalline silicon film, a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a laminated film obtained by appropriately laminating these may be used.

[0032] A sidewall spacer SW is formed on the side surface of the gate electrode GE. The sidewall spacer SW is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film.

[0033] In the well region PW under the sidewall spacer SW, an extension region EX, which is a low-concentration n-type impurity region, is formed. Further, in the well region PW at a position aligned with the sidewall spacer SW, a diffusion region D1, which is an n-type impurity region with a higher concentration than the extension region EX, is formed. The extension region EX and the diffusion region D1 are connected to each other and respectively constitute part of the source region or part of the drain region of the ferroelectric memory cell.

[0034] The ferroelectric memory cell includes at least an insulating film IF1, a ferroelectric film FEF, a gate electrode GE, and a pair of diffusion regions D1 that constitute part of the source region or part of the drain region.

[0035] On the gate electrode GE and the diffusion region D1, a silicide layer SI made of, for example, cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel platinum silicide (NiPtSi) is formed. The silicide layer SI is mainly formed to reduce the contact resistance with a plug PG described later.

[0036] An interlayer insulating film IL1 is formed on the ferroelectric memory cell. The interlayer insulating film IL1 is, for example, a silicon oxide film. A plurality of contact holes are formed in the interlayer insulating film IL1, and a plurality of plugs PG are formed in the plurality of contact holes. The plug PG is composed of, for example, a barrier metal film made of a titanium film, a titanium nitride film, or a laminated film thereof, and a conductive film mainly composed of tungsten. The plug PG is electrically connected to the diffusion region D1 via the silicide layer SI. Although not shown in the figure, there is also a plug PG in the interlayer insulating film IL1 that is electrically connected to the gate electrode GE.

[0037] Although illustration is omitted, a plurality of wirings are formed on the plug PG. For example, an interlayer insulating film is formed on the interlayer insulating film IL1, and a groove for wiring is formed in this interlayer insulating film. Then, a conductive film mainly composed of, for example, copper is embedded in the groove for wiring, thereby forming the first-layer wiring connected to the plug PG.

[0038] <Operation of ferroelectric memory cell> Next, an operation example of the ferroelectric memory cell will be described with reference to FIG. 3.

[0039] FIG. 3 is a table showing an example of the voltages applied to each part of the selected memory cell during "writing", "erasing", and "reading" among the ferroelectric memory cells. In the table of FIG. 3, the voltages applied to each part during each operation of "writing", "erasing", and "reading" are described. That is, in the table, the voltage Vd applied to the drain region (one diffusion region D1) of the ferroelectric memory cell shown in FIG. 2, the voltage Vg applied to the gate electrode GE, the voltage Vs applied to the source region (the other diffusion region D1), and the voltage Vb applied to the well region PW are described. Note that what is shown in the table of FIG. 3 is a preferred example of the voltage application conditions, and is not limited thereto, and can be variously changed as necessary.

[0040] Also, in the present embodiment, "writing" is defined as the state in which the polarization of the ferroelectric film FEF becomes upward and the threshold voltage of the ferroelectric memory cell becomes relatively high. And "erasing" is defined as the state in which the polarization of the ferroelectric film FEF becomes downward and the threshold voltage of the ferroelectric memory cell becomes relatively low.

[0041] The writing operation is performed by applying a negative voltage to the gate electrode GE. That is, for example, the voltages as shown in the "writing" column of FIG. 3 are applied to each part of the selected memory cell to be written. Thereby, the polarization of the ferroelectric film FEF becomes upward, the threshold voltage of the ferroelectric memory cell increases, and the ferroelectric film FEF becomes the written state.

[0042] In the erasure operation, it is performed by applying a positive voltage to the gate electrode GE. That is, for example, a voltage as shown in the "Erasure" column of FIG. 3 is applied to each part of the selected memory cell to be erased. As a result, the polarization of the ferroelectric film FEF becomes downward, the threshold voltage of the ferroelectric memory cell decreases, and the ferroelectric film FEF enters the erased state.

[0043] In the read operation, for example, a voltage as shown in the "Read" column of FIG. 3 is applied to each part of the selected memory cell to be read. By setting the voltage Vg applied to the gate electrode GE to a value between the threshold voltage of the ferroelectric film FEF in the writing state and the threshold voltage of the ferroelectric film FEF in the erased state, the writing state and the erased state can be discriminated.

[0044] <Manufacturing process of semiconductor device> Hereinafter, with reference to FIGS. 4 to 15, a method for manufacturing a semiconductor device according to the present embodiment will be described. Each of FIGS. 4 to 15 is a cross-sectional view showing a region where ferroelectric memory cells are formed.

[0045] FIG. 4 shows a process of forming the element isolation part STI and the well region PW.

[0046] First, for example, a semiconductor substrate SB made of single-crystalline silicon into which p-type impurities are introduced is prepared. Next, grooves are formed in the semiconductor substrate SB using photolithography and etching processes. Next, an insulating film such as a silicon oxide film is formed so as to fill the grooves, and then, by the CMP (Chemical Mechanical Polishing) method, the insulating film outside the grooves is removed, thereby forming the element isolation part STI made of the insulating film remaining in the grooves.

[0047] Next, p-type well regions PW are formed by introducing impurities into the semiconductor substrate SB using photolithography and ion implantation methods.

[0048] FIG. 5 shows a process of forming the insulating film IF1.

[0049] The semiconductor substrate SB is heat-treated in an atmosphere containing, for example, oxygen, to form an insulating film IF1 made of, for example, silicon oxide or silicon oxynitride on the semiconductor substrate SB. The thickness of the insulating film IF1 is, for example, 1 nm or less.

[0050] FIG. 6 shows the formation process of the amorphous layer AM1.

[0051] An amorphous layer (amorphous film) AM1 is formed on the insulating film IF1, for example, by the ALD (Atomic Layer Deposition) method. The thickness of the amorphous layer AM1 is, for example, from 0.5 nm to 2 nm. The amorphous layer AM1 is, for example, a film made of a material containing hafnium (Hf), oxygen (O), and zirconium (Zr) as the first element. Further, the first element may be any one of silicon (Si), germanium (Ge), yttrium (Y), lanthanum (La), or ytterbium (Yb) instead of zirconium.

[0052] FIG. 7 shows the formation process of a plurality of impurity particles GR.

[0053] Transfer the semiconductor wafer from the ALD apparatus used in the formation process of the amorphous layer AM1 in FIG. 6 to another apparatus, and perform the process of FIG. 7. In the present embodiment, a plurality of impurity particles GR are formed on the amorphous layer AM1 by a sputtering method. The plurality of impurity particles GR are separated from each other. In other words, the plurality of impurity particles GR are not formed as a continuously formed film like the amorphous layer AM1, but are formed discretely. That is, the plurality of impurity particles GR do not cover the entire amorphous layer AM1, but are scattered on the amorphous layer AM1. Therefore, a part of the amorphous layer AM1 is covered by the plurality of impurity particles GR, and the other part of the amorphous layer AM1 is exposed from the plurality of impurity particles GR. Also, a part of the plurality of impurity particles GR is deposited on the upper surface of the amorphous layer AM1, and there are also a plurality of impurity particles GR introduced near the upper surface in the amorphous layer AM1. For this reason, in the process of crystallizing the amorphous layer AM1 and the like described later, the plurality of impurity particles GR function as crystal nuclei.

[0054] Also, the plurality of impurity particles GR are any one of aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen or oxygen, or a mixture or compound thereof. In the present embodiment, the case where the second element is aluminum will be typically exemplified and described. Here, the impurity particles GR are made of aluminum nitride (AlN).

[0055] Also, the plurality of impurity particles GR may be formed by a CVD (Chemical Vapor Deposition) method instead of the sputtering method. However, as described above, it is preferable that the plurality of impurity particles GR are formed so as to be separated from each other. Therefore, the method of forming the plurality of impurity particles GR is preferably performed by the sputtering method. Also, the areal density of the plurality of impurity particles GR with respect to the upper surface of the amorphous layer AM1 is 1×10 12 / cm 2 to 1×10 13 / cm 2is within the range. As a result, the radius of the crystal grain size of the plurality of impurity particles GR can be precisely controlled, for example, within the range of 0.1 nm to 1 nm. Here, the plurality of impurity particles GR are, for example, 1×10 13 / cm 2 .

[0056] Also, in order to prevent the plurality of impurity particles GR from diffusing too much into the amorphous layer AM1, the sputtering method is preferably performed at a temperature in the range of 1 degree Celsius or more and 150 degrees Celsius or less.

[0057] Also, as described above, the second element constituting the plurality of impurity particles GR may be another element instead of aluminum. In such a case, the method for forming the plurality of impurity particles GR can also be performed using an ion implantation method instead of the sputtering method. When using the ion implantation method, the dose amount of the plurality of impurity particles GR is set to be in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 .

[0058] Figure 8 shows the formation process of the amorphous layer AM2.

[0059] An amorphous layer (amorphous film) AM2 is formed on the plurality of impurity particles GR and on the amorphous layer AM1, for example, by the ALD method. By this process, the plurality of impurity particles GR are covered by the amorphous layer AM2. The thickness of the amorphous layer AM2 is, for example, from 0.5 nm to 2 nm. The amorphous layer AM2 is made of the same material as the amorphous layer AM1 and is, for example, a film made of a material containing hafnium (Hf), oxygen (O), and zirconium (Zr) as the first element. Also, the first element may be any one of silicon (Si), germanium (Ge), yttrium (Y), lanthanum (La), or ytterbium (Yb) instead of zirconium.

[0060] Figure 9 shows the formation process of the amorphous layers AM3, AM4, and the impurity particles GR.

[0061] By repeating the process described with reference to FIGS. 7 and 8 twice, impurity particles GR, amorphous layer AM3, impurity particles GR, and amorphous layer AM4 are sequentially formed on the amorphous layer AM2. As a result, a laminated structure composed of amorphous layers AM1, AM2, AM3, and AM4 laminated in order is formed on the insulating film IF1. That is, the laminated structure is formed by repeating the amorphous layer forming step and the impurity particle forming step in order three or more times. Impurity particles GR are discretely arranged between the amorphous layer AM1 and the amorphous layer AM2, between the amorphous layer AM2 and the amorphous layer AM3, and between the amorphous layer AM3 and the amorphous layer AM4 in the direction along the first main surface of the semiconductor substrate SB. The film thickness of each of the amorphous layers AM1 to AM4 is, for example, 2 nm.

[0062] FIG. 10 shows the formation process of the metal film MF.

[0063] On the amorphous layer AM4, a metal film MF made of, for example, titanium nitride, tantalum nitride, or tungsten is formed using, for example, the CVD method or the sputtering method. The thickness of the metal film MF is, for example, from 2 nm to 10 nm. The metal film MF is mainly provided to apply stress to the amorphous layers AM1 to AM4.

[0064] FIG. 11 shows the formation process of the ferroelectric layer FE1, the ferroelectric layer FE2, the ferroelectric layer FE3, the ferroelectric layer FE4, and the ferroelectric film FEF.

[0065] The heat treatment (annealing treatment) is performed in a state where the metal film MF is formed on the amorphous layer AM4. As a result, the amorphous layer AM1 is crystallized to form the ferroelectric layer FE1 which is a cubic crystal, and the amorphous layer AM2 is crystallized to form the ferroelectric layer FE2 which is a cubic crystal. Further, by this heat treatment, the amorphous layer AM3 is crystallized to form the ferroelectric layer FE3 which is a cubic crystal, and the amorphous layer AM4 is crystallized to form the ferroelectric layer FE4 which is a cubic crystal. This heat treatment is performed at a temperature of 500 to 700 degrees Celsius by, for example, the RTA (Rapid Thermal Annealing) method. By this heat treatment, the laminated structure composed of a plurality of amorphous layers is crystallized to form the ferroelectric film FEF.

[0066] In the present embodiment, a plurality of impurity particles GR are formed as a plurality of grains between the amorphous layers laminated with each other. These plurality of grains function as crystal nuclei in the crystallization process. Among the plurality of grains which are the plurality of impurity particles GR, some bind to the substances contained in the amorphous layer AM1 and the amorphous layer AM2 to form a compound by the above heat treatment. That is, it is considered that the plurality of impurity particles GR after the above heat treatment are compounds in which aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen or oxygen is combined with hafnium or the first element. The mode (crystal growth) in which the amorphous layer is crystallized around the above crystal nuclei by heat treatment will be described later.

[0067] FIG. 12 shows the formation process of the conductive film FG.

[0068] On the metal film MF, a conductive film FG made of polycrystalline silicon into which, for example, an n-type impurity is introduced is formed by, for example, the CVD method. As described above, if the ferroelectric film FEF can be sufficiently maintained as a cubic crystal inside, the metal film MF may be removed before the formation of the conductive film FG.

[0069] FIG. 13 shows the formation process of the gate electrode GE.

[0070] The conductive film FG is patterned by a photolithography method and an etching process. Thereby, the gate electrode GE made of the conductive film FG is formed. Subsequently, by performing an etching process, the metal film MF, the ferroelectric film FEF, and the insulating film IF1 not covered by the gate electrode GE are removed. Here, since the case where the metal film MF under the gate electrode GE (conductive film FG) is left is exemplified, the metal film MF functions as a part of the gate electrode GE.

[0071] FIG. 14 shows the formation process of the extension region EX.

[0072] An extension region EX, which is an n-type impurity region, is formed in the well region PW at a position aligned with the gate electrode GE by a photolithography method and an ion implantation method. The extension region EX constitutes a part of the source region or the drain region of the ferroelectric memory cell.

[0073] FIG. 15 shows the formation process of the sidewall spacer SW, the diffusion region D1, and the silicide layer SI.

[0074] First, a silicon oxide film and a silicon nitride film are sequentially formed, for example, by CVD method so as to cover the gate electrode GE. Next, the silicon nitride film is processed by an anisotropic etching process. Thereafter, the silicon oxide film formed on the upper surface of the gate electrode GE and the like is removed. Thereby, a sidewall spacer SW made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the side surface of the gate electrode GE.

[0075] Next, a diffusion region D1, which is an n-type impurity region, is formed in the well region PW at a position aligned with the sidewall spacer SW by a photolithography method and an ion implantation method. The diffusion region D1 has a higher impurity concentration than the extension region EX, is connected to the extension region EX, and constitutes a part of the source region or the drain region of the ferroelectric memory cell.

[0076] Next, by using the salicide (Self Aligned Silicide) technology, a low-resistance silicide layer SI is formed on the upper surface of each of the diffusion region D1 and the gate electrode GE.

[0077] Specifically, the silicide layer SI can be formed as follows. First, a metal film for forming the silicide layer SI is formed on the semiconductor substrate SB so as to cover the diffusion region D1 and the gate electrode GE. This metal film is made of, for example, cobalt, nickel, or a nickel-platinum alloy. Next, the semiconductor substrate SB is subjected to a first heat treatment at about 300 to 400 degrees Celsius, and then a second heat treatment at about 600 to 700 degrees Celsius is performed to react the materials contained in the diffusion region D1 and the gate electrode GE with the metal film. As a result, a silicide layer SI made of cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel-platinum silicide (NiPtSi) is formed on the upper surface of each of the diffusion region D1 and the gate electrode GE. Thereafter, the unreacted metal film is removed.

[0078] Also, when a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a laminated film obtained by appropriately laminating these is employed as the material constituting the gate electrode GE, after the process of FIG. 15, the polycrystalline silicon film, which is the material of the gate electrode GE, can be replaced with the above metal film or the above laminated film by using a so-called gate-last process.

[0079] Thus, a ferroelectric memory cell having an MFIS structure is formed. That is, the ferroelectric memory cell includes at least an insulating film IF1, a ferroelectric film FEF, a gate electrode GE, and a pair of diffusion regions D1 that constitute a part of the source region or a part of the drain region.

[0080] Thereafter, through the following steps, the structure shown in FIG. 2 is obtained.

[0081] First, an interlayer insulating film IL1 made of, for example, silicon oxide is formed by, for example, CVD method so as to cover the ferroelectric memory cell. Next, a plurality of contact holes are formed in the interlayer insulating film IL1 using photolithography and etching processes. Next, a barrier metal film made of, for example, a titanium film, a titanium nitride film, or a laminated film thereof is formed in these plurality of contact holes, and a conductive film mainly composed of tungsten is formed on this barrier metal film. Next, for example, by CMP method, the barrier metal film and the conductive film outside the contact holes are removed, so that a plug PG is formed in the contact holes. The plug PG is electrically connected to the diffusion region D1 via the silicide layer SI. Although not shown, there is also a plug PG that is electrically connected to the gate electrode GE.

[0082] <Regarding crystal growth> Since the ferroelectric memory cell operates at a relatively low voltage, it has the characteristic of low power consumption. However, in a structure in which the ferroelectric film is composed of two ferroelectric layers, it has been difficult to form a ferroelectric memory cell with a lower operating voltage, for example, a ferroelectric memory cell that operates at 4V or less. The reason why it is difficult to form a ferroelectric memory cell with a low operating voltage is that the crystallization of the ferroelectric layer is performed by isotropic crystal growth (three-dimensional nucleation).

[0083] Fig. 29 shows the mode of crystal growth in the ferroelectric layer which is a comparative example. As shown in Fig. 29, in the comparative example, a ferroelectric film is formed by crystallizing only the two laminated amorphous layers AM1 and AM2. Here, the film thickness of each of the amorphous layers AM1 and AM2 is, for example, 3 nm. A plurality of impurity particles GR are arranged at intervals from each other between the amorphous layers AM1 and AM2. When such amorphous layers AM1 and AM2 are heat-treated, each of the amorphous layers AM1 and AM2 uses the impurity particle GR as a crystal nucleus CR3, and the crystal nucleus CR3 crystallizes three-dimensionally. That is, the crystal nucleus CR3 spreads spherically. Each crystal nucleus CR3 grows inside each of the amorphous layers AM1 and AM2 with the impurity particle GR between the amorphous layers AM1 and AM2 as the center.

[0084] However, in this case, when the crystal nuclei CR3 that are growing collide with each other, the crystal growth temporarily stops. Therefore, gaps that cannot be crystallized are generated between the crystals, and an amorphous state portion (non-crystallized region) remains in these gaps. As a result, the density of the crystals showing ferroelectricity in the ferroelectric film becomes low. That is, since the crystallinity of the ferroelectric film is poor, it is difficult to reduce the operating voltage in a ferroelectric memory cell including such a ferroelectric film.

[0085] On the other hand, in the crystallization step of the present embodiment, that is, in the heat treatment step described in Fig. 11, as shown in Figs. 16 and 17, crystal growth is performed in the plane direction, that is, two-dimensionally, with the impurity particle GR as the center in the amorphous layer, thereby suppressing the generation of the above gaps and improving the crystallinity of the ferroelectric film. Fig. 16 is a perspective view for explaining the mode of crystallization of the amorphous layer, and Fig. 17 is a cross-sectional view for explaining the mode of crystallization of the amorphous layer. In Fig. 17, the hatching of the amorphous layer is omitted for easy understanding of the figure.

[0086] Here, the crystal nucleus CR2 spreads in a disc shape centering on the impurity particle GR, and its thickness basically does not become larger than the respective film thicknesses of the amorphous layers AM1 to AM4. The crystal nucleus CR2 expands only in the planar direction (lateral direction) within each amorphous layer, and when it collides with other crystal nuclei CR2, crystal growth temporarily stops. For this reason, generation of the above-mentioned gaps can be suppressed as compared with the comparative example.

[0087] In this embodiment, although it is conceivable that there are crystals growing three-dimensionally, two-dimensional nucleation growth is dominant in the entire ferroelectric film. Here, in order for two-dimensional nucleation growth to be dominant in crystal growth, the surface energy of the horizontal plane of the crystal grains of each amorphous layer is made smaller than the surface energy of the vertical plane of the crystal grains of each amorphous layer, and the film thickness of each amorphous layer is controlled within a certain range (here, 2 nm or less). Thereby, epitaxial-like crystal growth can be expected. In order to make the surface energy of the horizontal plane of the crystal grains of each amorphous layer smaller than the surface energy of the vertical plane of the crystal grains of each amorphous layer, the arrangement of a plurality of discrete impurity particles GR may be controlled according to at least one of the following two conditions. That is, the areal density of the plurality of impurity particles GR is in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 Also, the volume density of the plurality of impurity particles GR is in the range of 1×10 18 / cm 3 to 1×10 21 / cm 3 Further, the average distance between the plurality of impurity particles GR in plan view is 2.5 nm or more and 11 nm or less. As in the comparative example of FIG. 29, since three-dimensional nucleation growth may be dominant when there are only two amorphous layers, in this embodiment, three or more amorphous layers are formed.

[0088] Next, with reference to FIG. 18, the range of the thickness of the amorphous layer in which two-dimensional nucleation growth is dominant will be described. In FIG. 18, the three-dimensional growing crystal nucleus CR3 of the comparative example is shown on the left side, and the two-dimensional growing crystal nucleus CR2 is shown on the right side. The boundaries of the amorphous layers AM1 and AM2 are indicated by broken lines. In the present embodiment in which the crystal nucleus CR2 grows two-dimensionally, amorphous layers AM3 and AM4 (not shown) are also provided above.

[0089] The "n - 1 layer" shown on the right side of FIG. 18 refers to the lower surface of the first amorphous layer AM1, the "n layer" refers to the lower surface of the second amorphous layer AM2, and the "n + 1 layer" refers to the upper surface of the second amorphous layer AM1 (or the lower surface of the third amorphous layer AM3). d is the thickness of each amorphous layer. σ1 is the surface energy in the n-layer amorphous layer (unit: J / m 2 ) and σ2 is the surface energy of each layer interface (unit: J / m 2 ). Here, if the driving force for crystallization (unit: J / m 2 ) is ΔG, the growth critical radius Rc(3D) of the three-dimensional growing crystal nucleus CR3 is represented by Rc(3D) = 2σ1 / ΔG > d. Also, the growth critical radius Rc(2D) of the two-dimensional growing crystal nucleus CR2 is represented by Rc(2D) = dσ1 / (dΔG - 2σ2).

[0090] The radius of the crystal and the driving energy of the crystal are represented as shown in the graph of Fig. 19. The horizontal axis of the graph in Fig. 19 is the radius of the crystal, and the vertical axis is the Gibbs free energy (driving energy) of the crystal. In Fig. 19, the graph at the time of formation of the three-dimensional nucleation nucleus (crystal nucleus CR3) is shown by a dashed line, and the graph at the time of formation of the two-dimensional nucleation nucleus (crystal nucleus CR2) is shown by a solid line. As shown in Fig. 19, the critical growth radius Rc(2D) of the two-dimensionally growing crystal nucleus CR2 is smaller than the critical growth radius Rc(3D) of the three-dimensionally growing crystal nucleus CR3. That is, when each of the crystal nuclei CR3 and CR2 starts to crystallize and gradually increases in radius, the crystallization of the crystal nucleus CR2 starts earlier while its radius is smaller. Therefore, when the crystallization is completed, the crystal nucleus CR2 becomes larger and dominant than the crystal nucleus CR3. σ2 represents wettability, and its value depends on the addition amount of the impurity particles GR and the surface treatment of the amorphous layer.

[0091] Table 20 shows the results of experiments conducted by the inventor to find a method for reducing the surface energy σ2. In this experiment, aluminum nitride is used as the impurity particles, but a mixture of silicon and aluminum or the like may be used instead. Here, aluminum nitride, which is an impurity particle, is discretely added to the upper surface of the amorphous layer, and the doping is in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 . Further, the volume density of the plurality of impurity particles is in the range of 1×10 18 / cm 3 to 1×10 21 / cm 3 , and the average distance between the plurality of impurity particles in plan view is 2.5 nm or more and 11 nm or less. In Examples 1 to 4, Comparative Example 1 and Comparative Example 2 shown in the table, the film thickness of the amorphous layer was set to the surface tension (2 nm or more) determined by the physical properties of the material from the lattice constant (0.5 nm or more) of the crystal material. However, in some examples or comparative examples, the experiments are carried out under conditions deviating from the upper and lower limit values of these ranges.

[0092] In this experiment, a crystal peak intensity of 600 or more is considered qualified (double circle), 400 or more and less than 600 is considered qualified (circle), and less than 400 is considered unqualified. As a result, Comparative Examples 1 and 2 are unqualified. In Comparative Example 1, the addition amount of aluminum nitride exceeds the upper limit value, and the interval between aluminum nitrides is smaller than the lower limit value, which is considered the reason for the unqualified. In Comparative Example 2, it is considered that the film thickness d exceeds the upper limit value, which is the reason for the unqualified. The low crystal peak intensity of Example 4 is considered to be due to the addition amount of aluminum nitride exceeding the upper limit value. Therefore, the areal density of a plurality of impurity particles is from 1×10 12 / cm 2 to 1×10 13 / cm 2 , and the volume density is from 1×10 18 / cm 3 to 1×10 21 / cm 3 . Also, it is desirable that the average distance between a plurality of impurity particles in plan view is 2.5 nm or more and 11 nm or less.

[0093] Fig. 21 shows the arrangement mode of impurity particles. In Fig. 21, which is a perspective view, the bottom surface nb of the n-layer ferroelectric layer and the bottom surface n1b of the (n + 1)-layer ferroelectric layer above it are shown as rectangular regions, respectively. In the plane thereof, the impurity particles GR are discretely arranged. Here, let the point (position) of a predetermined impurity particle GR on the bottom surface nb of the n-layer be a, and the points (positions) of two predetermined impurity particles GR on the bottom surface n1b of the (n + 1)-layer be b and c, respectively. Also, let the point (position) on the bottom surface n1b of the (n + 1)-layer directly above the position a in the thickness direction be o. The addition amount of the impurity particles GR is D. The distance between the impurity particles GR is R, and the thickness of the amorphous layer, that is, the distance between the bottom surface nb of the n-layer ferroelectric layer and the bottom surface n1b of the (n + 1)-layer ferroelectric layer is t.

[0094] At this time, t is the distance between point a and point o. Also, let the distance between point o and point b be x1, the distance between point o and point c be x2, the distance between point a and point b be la, and the distance between point a and point c be lb. At this time, x1 + x2 ≒ 2R, and R ≒ (Dπ)-1 / 2 It is represented by π being the ratio of a circle's circumference to its diameter. In the present embodiment, with x1 ≦ x2, a plurality of impurity particles GR are arranged so as to satisfy t ≦ 2R and t ≦ la ≦ lb. In FIG. 21, points b and c are displaced from directly above point a, but even if point b is located directly above point a, the said condition is satisfied. To satisfy this condition, in the present embodiment, the areal density of the plurality of impurity particles GR is in the range from 1×10 12 / cm 2 to 1×10 13 / cm 2 , and the volume density is in the range from 1×10 18 / cm 3 to 1×10 21 / cm 3 . Also, the average distance between the plurality of impurity particles in plan view is 2.5 nm or more and 11 nm or less. Also, the range of t is 0.5 nm or more and 2 nm or less.

[0095] <Effects of the Present Embodiment> FIG. 30 shows a cross-sectional view of the structure of the main part of a ferroelectric memory cell as a comparative example. As shown in FIG. 30, the ferroelectric film FEFa of the ferroelectric memory cell of the comparative example is a laminate, and the ferroelectric layers constituting this laminate are only the ferroelectric layers FE1 and FE2. A plurality of impurity particles GR are arranged between the ferroelectric layers FE1 and FE2. Inside the ferroelectric film FEFa, as described with reference to FIG. 29, crystals grow three-dimensionally around the impurity particles GR.

[0096] The writing characteristics of such a ferroelectric memory cell of the comparative example are shown in the graph of FIG. 31, and the erasing characteristics are shown in the graph of FIG. 32. Also, the writing characteristics of the main part of the ferroelectric memory cell of the present embodiment are shown in the graph of FIG. 22, and the erasing characteristics are shown in the graph of FIG. 23. The horizontal axis of each of FIGS. 22, 23, 31, and 32 is the time for applying a voltage to the ferroelectric memory cell, and the vertical axis is the threshold voltage of the ferroelectric memory cell. In FIGS. 22 and 31, the graphs when -4V is applied to the gate electrode are shown as black circular plots, the graphs when -3V is applied are shown as triangular circular plots, and the graphs when -2V is applied are shown as square circular plots. In FIGS. 23 and 32, the graphs when +4V is applied to the gate electrode are shown as black circular plots, the graphs when +3V is applied are shown as triangular circular plots, and the graphs when +2V is applied are shown as square circular plots.

[0097] From FIG. 31, in the writing operation of the ferroelectric memory cell of the comparative example, when -4V to -2V are respectively applied to the gate electrode, it can be seen that in any case, there is almost no difference in the threshold voltage, and the on / off switching of the current flow in the element cannot be achieved. Similarly, from FIG. 32, in the erasing operation of the ferroelectric memory cell of the comparative example, when +4V to +2V are respectively applied to the gate electrode, it can be seen that in any case, there is almost no difference in the threshold voltage, and the on / off switching of the current flow in the element cannot be achieved. Thus, the ferroelectric memory cell of the comparative example cannot be driven at a low voltage of 4V or less.

[0098] On the other hand, as shown in FIG. 22, when writing to the ferroelectric memory cell of the present embodiment, a voltage of -4V or -3V is applied to the gate electrode, so that the threshold voltage increases and writing is performed. Further, as shown in FIG. 23, when erasing the ferroelectric memory cell of the present embodiment, voltages of +4V to +2V are applied to the gate electrode, so that the threshold voltage decreases and erasing is performed. That is, in the present embodiment, the operating voltage of the ferroelectric memory cell can be reduced compared to the comparative example. Specifically, the memory operating voltage in the ferroelectric memory cell (semiconductor element) which is a memory element is reduced to 4V or less. This is the effect of improving the crystallinity of the ferroelectric film in the present embodiment.

[0099] By suppressing the memory operating voltage, it becomes unnecessary to modulate the power supply voltage for memory operation. Therefore, a semiconductor device including a circuit that performs a writing operation and an erasing operation in the ferroelectric memory cell can be realized without modulating the power supply voltage supplied to the ferroelectric memory cell.

[0100] FIG. 24 shows the results of X-ray diffraction in the ferroelectric film. The horizontal axis of the graph shown in FIG. 24 is the angle (the incident angle of the X-ray beam), and the vertical axis is the scattering intensity of the X-rays. As a result of irradiating the ferroelectric film of the present embodiment with an X-ray beam and measuring its scattering intensity, it can be seen that the cubic crystal (o(111)) is present predominantly compared to the monoclinic crystal (m(111)) and the like. The predominant presence of the cubic crystal enables an increase in the remnant polarization of the ferroelectric film, an improvement in the performance as a ferroelectric, and a reduction in the driving power of the ferroelectric memory cell in the ferroelectric film.

[0101] Fig. 25 shows a graph of the crystal peak intensity of the orthorhombic crystal (111). The horizontal axis in Fig. 25 is the addition amount (dose amount) of aluminum nitride, which is an impurity particle, and the vertical axis is the crystal peak intensity (physical intensity). The graph indicated by the white circular plots is the graph when only two ferroelectric layers are formed as in the comparative example shown in Fig. 30. The graph indicated by the black circular plots is the graph when four ferroelectric layers are formed as in this embodiment. It can be seen from Fig. 25 that when more than two ferroelectric layers are formed compared with the comparative example, the crystal peak intensity of the orthorhombic crystal of the ferroelectric film increases.

[0102] From the above, in this embodiment, the ferroelectricity of the ferroelectric film FEF (see Fig. 2) is improved, and a ferroelectric memory cell that can operate at a low voltage can be realized. That is, the performance of the semiconductor device can be improved.

[0103] (Embodiment 2) In Embodiment 1, the discrete arrangement of impurity particles and the provision of three or more ferroelectric layers (amorphous layers) were described. Embodiment 1 grows crystals two-dimensionally with a plurality of impurity particles as nuclei. On the other hand, even if three or more amorphous layers are provided and the surface (upper surface) of each amorphous layer is hydrophilized, the crystals can be grown two-dimensionally. Hereinafter, in this embodiment, the two-dimensional growth of crystals by hydrophilizing the surface of the amorphous layer without arranging a plurality of impurity particles will be described.

[0104] Fig. 26 is a flow showing the steps until an insulating film IF1, amorphous layers AM1, AM2, AM3, AM4, and a metal film MF are formed on a semiconductor substrate and then heat treatment is performed in the manufacturing method of the semiconductor device of this embodiment. The film formation steps of this series of steps are the same as the steps described using Figs. 5, 8, 9, 10, and 11, but the addition of impurity particles GR is not performed here. However, after each of the amorphous layers AM1, AM2, and AM3 is formed, the surface of each amorphous layer is hydrophilized.

[0105] That is, as shown in FIG. 26, formation of the insulating film IF1 (step S10), formation of the amorphous layer AM1 (step S11), hydrophilic treatment of the surface of the amorphous layer AM1 (step S12), and formation of the amorphous layer AM2 (step S13) are performed. Thereafter, hydrophilic treatment of the surface of the amorphous layer AM2 (step S14), formation of the amorphous layer AM3 (step S15), hydrophilic treatment of the surface of the amorphous layer AM3 (step S16), and formation of the amorphous layer AM4 (step S17) are performed. Thereafter, formation of the metal film MF (step S18) and crystallization by heat treatment (step S19) are performed. The film thicknesses of the insulating film IF1, the amorphous layers AM1 to AM4, and the metal film MF, and the temperature conditions of the heat treatment are the same as those in the first embodiment. Thereby, a laminated structure including the amorphous layers AM1 to AM4 is formed. Here, the laminated structure is formed by repeating the amorphous layer formation step and the hydrophilic treatment in order three or more times.

[0106] Thereafter, by performing the steps described with reference to FIGS. 12 and 13, the structure shown in FIG. 27 is obtained. As shown in FIG. 27, the ferroelectric film FEF includes four ferroelectric layers FE1 to FE4, and no impurity particles are formed between the overlapping ferroelectric layers. The surface (upper surface) of each of the ferroelectric layers FE1 to FE3 is hydrophilic-treated.

[0107] By the hydrophilic treatment in step S12, the wettability of the surface of the amorphous layer AM1 is enhanced. That is, the surface energy of the amorphous layer AM1 is decreased. Similarly, by the hydrophilic treatment in step S14, the surface energy of the amorphous layer AM2 is decreased, and by the hydrophilic treatment in step S16, the surface energy of the amorphous layer AM3 is decreased. The surface energy of the hydrophilic-treated amorphous layer is smaller than the surface energy of the amorphous layer before being hydrophilic-treated. In other words, it can be said that the contact angle of the hydrophilic-treated amorphous layer is smaller than the contact angle of the amorphous layer before being hydrophilic-treated. In this way, the interfaces between the amorphous layers overlapping in the thickness direction are hydrophilized, and the crystal growth in the plane direction of the crystal, that is, two-dimensional nucleation, in the crystallization step of step S19 is promoted. After obtaining the structure shown in FIG. 27, by performing the steps described with reference to FIGS. 14 and 15, the ferroelectric memory cell which is the semiconductor device of the present embodiment is formed.

[0108] Specifically, the hydrophilic treatment is a treatment performed on the surface of the amorphous layer, and is any one of O2 plasma treatment, O3 treatment, APM (Ammonia-hydrogen Peroxide Mixture) cleaning, HPM (Hydrochloric acid-hydrogen Peroxide Mixture) cleaning, water washing treatment, UV (Ultraviolet) treatment or air exposure, or a combination thereof. For example, the hydrophilic treatment can be performed by sequentially performing cleaning with a mixed solution of sulfuric acid and hydrogen peroxide water and running water cleaning with pure water on the semiconductor substrate on which the amorphous layer is formed. Further, the hydrophilic treatment can be performed by subjecting the semiconductor substrate on which the amorphous layer is formed to a hydrofluoric acid treatment and then performing running water cleaning with pure water to attach hydroxyl groups to the surface to be hydrophilized.

[0109] Also, the hydrophilic treatment can be performed, for example, by thermally oxidizing an amorphous layer containing silicon to form a silicon oxide film on the surface of the amorphous layer, or by reacting the amorphous layer with ammonia to form a silicon nitride film on the surface of the amorphous layer. Further, the hydrophilic treatment can be performed by immersing a semiconductor substrate on which an amorphous layer is formed in a solution of H2SO4:H2O2 = 1:4. Further, the hydrophilic treatment can be performed by cleaning a semiconductor substrate on which an amorphous layer is formed with nitric acid peroxide.

[0110] Also, the hydrophilic treatment can be performed by ashing the surface of a semiconductor substrate on which an amorphous layer is formed with oxygen plasma and then immersing it in water. Further, the hydrophilic treatment can be performed by subjecting a semiconductor substrate on which an amorphous layer is formed to ozone treatment with ultraviolet light. Further, the hydrophilic treatment can be performed by treating a semiconductor substrate on which an amorphous layer is formed with a surface treatment liquid selected from an organic solvent having a hydroxyl group and an aqueous solution having a pH of 1 to 10.

[0111] The method of hydrophilic treatment is not limited to this, and it may be performed by irradiating the amorphous layer with an energy beam or using a dry process such as RIE (Reactive Ion Etching).

[0112] In this embodiment, even without disposing impurity particles on the surface of the amorphous layer, by laminating three or more amorphous layers and performing hydrophilic treatment on the interfaces between the overlapping amorphous layers, two-dimensional crystals can be grown in each amorphous layer during subsequent heat treatment. As a result, the crystallinity of the ferroelectric film can be enhanced, and thus the performance of the semiconductor device can be improved.

[0113] (Embodiment 3) The above-described Embodiments 1 and 2 may be combined with each other. This embodiment performs both a step of discretely forming impurity particles on the upper surface of the amorphous layer and a step of performing hydrophilic treatment on the surface of the amorphous layer after forming the amorphous layer.

[0114] FIG. 28 is a flow chart showing the steps until an insulating film IF1, amorphous layers AM1, AM2, AM3, AM4, and a metal film MF are formed on a semiconductor substrate and then heat treatment is performed in the method of manufacturing a semiconductor device according to the present embodiment. In the film forming steps of this series of steps, in addition to the steps described with reference to FIGS. 5 to 11, after each of the amorphous layers AM1, AM2, and AM3 is formed, a hydrophilic treatment and a step of forming impurity particles are performed.

[0115] That is, as shown in FIG. 28, formation of the insulating film IF1 (step S20), formation of the amorphous layer AM1 (step S21), hydrophilic treatment of the surface of the amorphous layer AM1 (step S22), formation of impurity particles (step S23), and formation of the amorphous layer AM2 (step S24) are performed. Thereafter, hydrophilic treatment of the surface of the amorphous layer AM2 (step S25), formation of impurity particles (step S26), formation of the amorphous layer AM3 (step S27), hydrophilic treatment of the surface of the amorphous layer AM3 (step S28), formation of impurity particles (step S29), and formation of the amorphous layer AM4 (step S30) are performed. Thereafter, formation of the metal film MF (step S31) and crystallization by heat treatment (step S32) are performed. The film thicknesses of each of the insulating film IF1, the amorphous layers AM1 to AM4, and the metal film MF, and the temperature conditions of the heat treatment are the same as those in the first embodiment. Thereby, a laminated structure including the amorphous layers AM1 to AM4 is formed. Here, the laminated structure is formed by repeating the steps of forming the amorphous layer, the hydrophilic treatment, and the step of forming impurity particles in this order three or more times.

[0116] By each of the hydrophilic treatment in step S22 and the step of forming impurity particles in step S23, the wettability of the surface of the amorphous layer AM1 is enhanced. That is, the surface energy of the amorphous layer AM1 is decreased. Similarly, by each of the hydrophilic treatment in step S25 and the step of forming impurity particles in step S26, the surface energy of the amorphous layer AM2 is decreased, and by each of the hydrophilic treatment in step S28 and the step of forming impurity particles in step S29, the surface energy of the amorphous layer AM3 is decreased. In this way, the interfaces between the amorphous layers overlapping in the thickness direction are hydrophilized, and the two-dimensional nucleation of crystals in the crystallization step of step S29 is promoted with the impurity particles as nuclei. After the heat treatment in step S32, by performing the steps described with reference to FIGS. 12 to 15, the ferroelectric memory cell which is the semiconductor device of the present embodiment is formed.

[0117] In the present embodiment, three or more amorphous layers are stacked, impurity particles are arranged on the surface of the amorphous layer, and then the hydrophilic treatment of the interfaces between the overlapping amorphous layers is performed. Therefore, as compared with any of Embodiments 1 and 2, the two-dimensional growth of crystals in each amorphous layer in the subsequent heat treatment can be promoted. As a result, the crystallinity of the ferroelectric film can be enhanced, and thus the performance of the semiconductor device can be improved.

[0118] As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

[0119] For example, similar to Embodiment 1, also in Embodiments 2 and 3, controlling the film thickness of the amorphous layer is important for preferentially promoting the two-dimensional growth of crystals in the ferroelectric film.

[0120] In addition, a part of the content described in the embodiments is described below.

[0121] (Appendix 1) A paraelectric film formed on a semiconductor substrate, A stacked film formed on the paraelectric film, A semiconductor device including The stacked film is composed of a plurality of the ferroelectric layers stacked in three or more layers, A semiconductor device in which the memory operating voltage in the semiconductor device, which is a memory element having a plurality of the ferroelectric layers, is 4 V or less.

[0122] (Appendix 2) In the semiconductor device according to Appendix 1, A semiconductor device including a circuit that performs a write operation and an erase operation in the semiconductor element without modulating a power supply voltage.

Explanation of Reference Numerals

[0123] AM1, AM2, AM3, AM4 Amorphous layers CR2, CR3 Crystal nuclei D1 Diffusion region EX Extension region FE1, FE2, FE3, FE4 Ferroelectric layers FEF, FEFa Ferroelectric films GE Gate electrode GR Impurity particles IF1 Insulating film IL1 Interlayer insulating film MF Metal film PG Plug PW Well region SB Semiconductor substrate SI Silicide layer STI Element isolation part SW Sidewall spacer

Claims

1. A ferroelectric film formed on a semiconductor substrate, A stacked film formed on the ferroelectric film, Comprising, The stacked film is composed of a plurality of ferroelectric layers stacked in three or more layers, a semiconductor device.

2. In the semiconductor device according to Claim 1, On the surface of each of the plurality of ferroelectric layers, a plurality of impurity particles are discretely present, a semiconductor device.

3. In the semiconductor device according to Claim 1, The film thickness of each of the plurality of ferroelectric layers is 0.5 nm or more and 2 nm or less, a semiconductor device.

4. In the semiconductor device according to Claim 1, The film thickness of the stacked film is 6 nm or more and 20 nm or less, a semiconductor device.

5. In the semiconductor device according to Claim 1, Each of the plurality of ferroelectric layers is composed of a material containing a metal oxide and a first element, The metal oxide is hafnium oxide or gallium oxide, The first element is any one of zirconium, silicon, germanium, yttrium, lanthanum or ytterbium, a semiconductor device.

6. In the semiconductor device according to Claim 2, The ferroelectric film is a silicon oxide film or a silicon oxynitride film, a semiconductor device.

7. In the semiconductor device according to Claim 2, The plurality of impurity particles are composed of any one of aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen or oxygen, or a combination thereof, a semiconductor device.

8. In the semiconductor device according to Claim 2, The areal density of the plurality of impurity particles is 1×10 １２ / cm ２ or more and 1×10 １３ / cm ２ or less. A semiconductor device.

9. In the semiconductor device according to Claim 2, The volume density of the plurality of impurity particles is 1×10 １８ / cm ３ or more and 1×10 ２１ / cm ３ or less, semiconductor device.

10. In the semiconductor device according to Claim 2, The average distance between the plurality of impurity particles in plan view is 2.5 nm or more and 11 nm or less, a semiconductor device.

11. In the semiconductor device according to Claim 1, The surface of each of the plurality of ferroelectric layers is hydrophilized, a semiconductor device.

12. In the semiconductor device according to Claim 1, The surface energy of the hydrophilized ferroelectric layer is smaller than the surface energy of the ferroelectric layer before hydrophilization, a semiconductor device.

13. (a) A step of forming a ferroelectric film on a semiconductor substrate, (b) A step of forming a stacked structure on the ferroelectric film, (c) A step of forming a metal film on the stacked structure, (d) After the step (c), a step of performing heat treatment, Comprising, The step (b) is, Step (b1) of forming an amorphous layer composed of a material containing a metal oxide and a first element; Step (b2) of discretely providing a plurality of impurity particles on the surface of the amorphous layer after the step (b1); The step of forming the laminated structure by repeating at least three times the steps of forming the amorphous layer and the plurality of impurity particles in order; The step (d) is a method of manufacturing a semiconductor device in which each of the amorphous layers of the laminated structure is crystallized in a planar direction by the heat treatment to form a ferroelectric laminated film.

14. In the method of manufacturing a semiconductor device according to claim 13, The method of manufacturing a semiconductor device, wherein the film thickness of each of the amorphous layers of the laminated structure is 0.5 nm or more and 2 nm or less.

15. In the method of manufacturing a semiconductor device according to claim 13, The metal oxide is hafnium oxide or gallium oxide, The method of manufacturing a semiconductor device, wherein the first element is any one of zirconium, silicon, germanium, yttrium, lanthanum, or ytterbium.

16. In the method of manufacturing a semiconductor device according to claim 13, The areal density of the plurality of impurity particles stored in the step (b1) is 1×10 １２ / cm ２ or more and 1×10 １３ / cm ２ or less. A method of manufacturing a semiconductor device.

17. In the method of manufacturing a semiconductor device according to claim 13, The method of manufacturing a semiconductor device, wherein the average distance between the plurality of impurity particles in a plan view is 2.5 nm or more and 11 nm or less.

18. Step (a) of forming a paraelectric film on a semiconductor substrate; Step (b) of forming a laminated structure on the paraelectric film; Step (c) of forming a metal film on the laminated structure; Step (d) of performing a heat treatment after the step (c); Comprising: The step (b) is Step (b1) of forming an amorphous layer composed of a material containing a metal oxide and a first element; Step (b2) of performing a hydrophilic treatment on the surface of the amorphous layer after the step (b1); The step of forming the laminated structure by repeating at least three times the steps of laminating the amorphous layers in order; The step (d) is The method of manufacturing a semiconductor device in which each of the amorphous layers of the laminated structure is crystallized in a planar direction by the heat treatment to form a ferroelectric laminated film.

19. In the method of manufacturing a semiconductor device according to claim 18, The method of manufacturing a semiconductor device, wherein the surface energy of the amorphous layer hydrophilized in the step (b2) is smaller than the surface energy of the amorphous layer before being hydrophilized.

20. In the method of manufacturing a semiconductor device according to claim 18, A method of manufacturing a semiconductor device, wherein the contact angle of the amorphous layer hydrophilized in the step (b2) is smaller than the contact angle of the amorphous layer before being hydrophilized.

21. In the method of manufacturing a semiconductor device according to claim 18, The hydrophilic treatment performed in the step (b2) is one of O ２ plasma treatment, O ３ treatment, APM cleaning, HPM cleaning, water washing treatment, UV treatment, or air exposure, or a combination thereof, and a method for manufacturing a semiconductor device.

22. In the method of manufacturing a semiconductor device according to claim 18, A method of manufacturing a semiconductor device, wherein each film thickness of the amorphous layers of the stacked structure is 0.5 nm or more and 2 nm or less.

23. In the method of manufacturing a semiconductor device according to claim 18, The metal oxide is hafnium oxide or gallium oxide, A method of manufacturing a semiconductor device, wherein the first element is any one of zirconium, silicon, germanium, yttrium, lanthanum or ytterbium.

24. In the method of manufacturing a semiconductor device according to claim 18, The step (b) further includes: (b3) a step of discretely providing a plurality of impurity particles on the surface of the amorphous layer after the step (b2). A method of manufacturing a semiconductor device, which is a step of forming the stacked structure by sequentially forming the amorphous layer and the plurality of impurity particles.

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