Display device

Abstract

To provide a display device capable of controlling a viewing angle.SOLUTION: A display device comprises: a display panel including a display area in which a plurality of sub-pixels is arranged and a non-display area surrounding the display area; and a plurality of level shifts arranged in the display area and that transmits a mode signal so as to drive the plurality of sub-pixels in either a first mode or a second mode. Each of the plurality of sub-pixels includes: a first light-emitting element; a first optical member that refracts light from the first light-emitting element; a second light-emitting element; and a second optical member that refracts light from the second light-emitting element and has a different shape from the first optical member. As a result, a bezel area can be reduced by embedding the level shift for generating the mode signal in the display area.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, to a display device capable of controlling a viewing angle.

Background Art

[0002] As technology in modern society develops, display devices are widely used to provide information to users. Display devices include not only electro-optical panels that simply transmit visual information in one direction, but also various electronic devices that require higher technologies to confirm user input and provide information corresponding to the confirmed input.

[0003] For example, a display device can be included in a vehicle to provide various information to the driver and passengers of the vehicle. However, the display device in the vehicle needs to appropriately display content so as not to interfere with the operation of the vehicle. For example, the display device needs to limit the display of content that can reduce the driver's concentration during vehicle operation.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this specification is to provide a display device capable of generating a mode signal using a low-voltage signal without a separate high-voltage IC.

[0005] Another problem to be solved by this specification is to provide a display device capable of selectively controlling the viewing angle in both the row direction and the column direction for a plurality of regions.

[0006] Still another problem to be solved by this specification is to provide a display device with a minimized bezel.

[0007] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] The display device according to an embodiment of the present specification includes a display panel including a display area in which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, and a plurality of level shifters arranged in the display area and transmitting a mode signal so that the plurality of sub-pixels are driven in either the first mode or the second mode. Each of the plurality of sub-pixels includes a first light-emitting element, a first optical member that refracts light from the first light-emitting element, a second light-emitting element, and a second optical member that refracts light from the second light-emitting element and has a shape different from that of the first optical member. Therefore, the level shifter for generating the mode signal can be built in the display area to reduce the bezel area.

[0009] Specific matters of other embodiments are included in the detailed description and the drawings.

Effects of the Invention

[0010] According to the embodiment of the present specification, the mode signal can be generated by using a level shifter that uses the same control signal as the signal for driving the sub-pixel circuit without using a separate IC for generating the mode signal, and the manufacturing cost can be reduced.

[0011] According to the embodiment of the present specification, the level shifter for generating the mode signal can be built in the display area to reduce the bezel area.

[0012] According to the embodiment of the present specification, the level shifters are arranged in a plurality of regions, and the viewing angle can be selectively controlled in either the row direction or the column direction.

[0013] According to the embodiment of the present specification, since the level shifter shares the signal wiring with the sub-pixel circuit and can minimize the additional wiring for driving the level shifter, it is possible to prevent the wiring design from becoming complicated.

[0014] The effects according to this specification are not limited to the content exemplified above, and more diverse effects are included in this specification.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3a

Figure 3b

Figure 4a

Figure 4b

Figure 5

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Figure 7

Figure 8

Figure 9a

Figure 9b

Figure 9c

Figure 10

Figure 11

Figure 12a

Figure 12b

Figure 12c

Embodiments for Carrying Out the Invention

[0016] The advantages, features, and methods for achieving them of the present specification will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of the present specification becomes complete and that those having ordinary knowledge in the technical field to which the present specification pertains are fully informed of the scope of the specification.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, so the present specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining the present specification, if it is determined that a detailed description of related known technologies may muddy the gist of the present specification, the detailed description thereof is omitted. When terms such as "including", "having", "being made" as mentioned in the present specification are used, unless "only" is used, other parts can be added. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0018] When interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0019] When explaining the positional relationship, for example, when the positional relationship between two parts is described such as "above ~", "on the upper part of ~", "on the lower part of ~", "next to ~", etc., as long as "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0020] An element or layer being referred to as "on" another element or layer includes both the case where it is immediately above the other element and the case where another layer or another element is interposed in the middle.

[0021] Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical concept of this specification.

[0022] Throughout the specification, the same reference numerals refer to the same components.

[0023] The area and thickness of each configuration shown in the drawings are shown for the convenience of explanation, and this specification is not necessarily limited to the area and thickness of the shown configuration.

[0024] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various technical linkages and drives, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0025] Hereinafter, this specification will be described with reference to the drawings.

[0026] FIG. 1 is a block diagram of a display device according to an embodiment of this specification.

[0027] The display device 100 according to an embodiment of the present specification may apply an electroluminescent display device. The electroluminescent display device may utilize an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (QLED) display device, or an inorganic light emitting diode (ILED) display device.

[0028] Referring to FIG. 1, the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD, and a timing controller TC.

[0029] The display panel PN can generate an image provided to the user. For example, the display panel PN can generate and display an image provided to the user through pixels PX in which a plurality of sub-pixel circuits are arranged.

[0030] The data driving circuit DD, the gate driving circuit GD, and the timing controller TC can provide signals for the operation of each pixel PX through signal wirings. The signal wirings can include, for example, data wirings DL and gate wirings GL.

[0031] The data wirings DL are arranged in the column direction and can include a plurality of wirings connected to pixels PX arranged in one column direction, and the gate wirings GL are arranged in the row direction and can include a plurality of wirings connected to pixels PX arranged in one row direction.

[0032] In some cases, the display device 100 can further include a power supply unit. In such a case, signals for the operation of the pixels PX can be provided through a power supply wiring that connects the power supply unit and the display panel PN. According to an embodiment, the power supply unit can supply power to the data driving circuit DD and the gate driving circuit GD. The data driving circuit DD and the gate driving circuit GD can be driven based on the power supplied from the power supply unit.

[0033] As an example, the data driving circuit DD can apply a data signal to each pixel PX through the data wiring DL, the gate driving circuit GD can apply a gate signal to each pixel PX through the gate wiring GL, and the power supply unit can supply a power supply voltage to each pixel PX through the power supply voltage supply wiring.

[0034] The timing controller TC can control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller TC can re-align the digital video data input from the outside to match the resolution of the display panel PN and supply it to the data driving circuit DD.

[0035] The data driving circuit DD can convert the digital video data input from the timing controller TC based on a data control signal into an analog data voltage and supply it to a number of data wirings DL.

[0036] The gate driving circuit GD can generate a scan signal and a light emission signal (or a light emission control signal) based on a gate control signal. The gate driving circuit GD can include a scan driving unit and a light emission signal driving unit. The scan driving unit can generate a scan signal in a row sequential manner to drive at least one or more scan wirings connected for each row of each pixel and supply it to the scan wiring. The light emission signal driving unit can generate a light emission signal in a row sequential manner to drive at least one or more light emission signal wirings connected for each row of each pixel and supply it to the light emission signal wiring.

[0037] According to an embodiment, the gate driving circuit GD can be disposed on the display panel PN in a GIP (Gate-driver In Panel) manner. For example, the gate driving circuit GD can be divided into a plurality of parts and disposed on at least two sides of the display panel PN respectively.

[0038] The display panel PN can include a display area and a non-display area surrounding the display area.

[0039] The display area of the display panel PN can include a plurality of pixels PX arranged in a row direction and a column direction. The pixel PX can be disposed in an area where a number of data wirings and a number of gate wirings intersect.

[0040] One pixel PX can include a plurality of sub-pixels that emit different colors. For example, the pixel PX can implement blue, red, and green using 3 sub-pixels. However, it is not limited thereto, and in some cases, the pixel PX can further include a sub-pixel for further implementing a specific color (e.g., white).

[0041] The area for implementing blue in the pixel PX can be referred to as a blue sub-pixel, the area for implementing red can be referred to as a red sub-pixel, and the area for implementing green can be referred to as a green sub-pixel.

[0042] Each of the plurality of sub-pixels can include a first light-emitting element and a second light-emitting element, and can include a first lens that refracts light from the first light-emitting element in a specific direction and a second lens that refracts light from the second light-emitting element in a specific direction. Therefore, the first lens and the second lens can limit the viewing angle of each of the plurality of sub-pixels.

[0043] A detailed description of the first lens and the second lens will be described later with reference to FIGS. 4a and 4b.

[0044] The non-display area can be arranged along the periphery of the display area. Various components for driving a plurality of sub-pixels arranged in the pixel PX can be arranged in the non-display area. For example, at least a part of the gate driving circuit GD can be arranged in the non-display area. The non-display area can be referred to as a bezel area.

[0045] FIG. 2 is a circuit diagram of sub-pixels of a display device according to an embodiment of the present specification. The plurality of pixels PX can each include a plurality of sub-pixels SP indicating different colors from each other and sub-pixel circuits SPC corresponding to the plurality of sub-pixels SP respectively.

[0046] Referring to FIG. 2, each of the plurality of sub-pixels SP includes a plurality of light-emitting elements ED1, ED2, a driving transistor DT, first to eighth transistors T1 to T8, and a storage capacitor Cst.

[0047] The plurality of transistors DT, T1 to T8 can include at least one of oxide semiconductors such as amorphous silicon, polycrystalline silicon, and IGZO. The first electrode or the second electrode of the transistor can be a source electrode or a drain electrode. For example, the first electrode can be a source electrode and the second electrode can be a drain electrode. As another example, the first electrode can be a drain electrode and the second electrode can be a source electrode.

[0048] At least a part of the plurality of transistors included in the sub-pixel circuit SPC can be an n-type transistor or a p-type transistor. In the case of a p-type transistor, the low level voltage of each driving signal can mean a voltage for turning on the TFT, and the high level voltage of each driving signal can mean a voltage for turning off the transistor.

[0049] Here, the low-level voltage can correspond to a pre-specified voltage lower than the high-level voltage. For example, the low-level voltage can include voltages corresponding to the range of -8V to -12V. The high-level voltage can correspond to a pre-specified voltage higher than the low-level voltage. For example, the high-level voltage can include voltages corresponding to the range of 12V to 16V. By way of an example, the low-level voltage can be referred to as the first voltage, and the high-level voltage can be referred to as the second voltage. In such a case, the first voltage may be a value lower than the second voltage.

[0050] Hereinafter, the first electrode or the second electrode of the transistor described later may mean the source electrode or the drain electrode. However, the terms "first electrode" and "second electrode" are only terms for distinguishing each electrode and do not limit what each electrode corresponds to. Also, the first electrode may not refer to the same electrode for each electrode. For example, the first electrode of the first transistor T1 may mean the source electrode of the first transistor T1, and the first electrode of the eighth transistor T8 may mean the drain electrode of the eighth transistor T8.

[0051] The driving transistor DT can control the driving current applied to the plurality of light-emitting elements by the source-gate voltage Vsg. The driving transistor DT includes a source electrode connected to a high-level driving voltage wiring supplied with the high-level driving voltage VDD, a gate electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0052] The first transistor T1 can apply a data voltage Vdata from the data wiring DL to the first node N1. The first transistor T1 includes a source electrode connected to the data wiring, a drain electrode connected to the first node N1, and a gate electrode connected to a first scan signal wiring to which a first scan signal SCAN1 is applied. The first transistor T1 can be turned on or off by the first scan signal SCAN1. Therefore, the first transistor T1 can apply the data voltage Vdata from the data wiring DL to the first node N1 in response to the first scan signal SCAN1 at a turn-on level, which is a low level.

[0053] The second transistor T2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT. The second transistor T2 includes a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to a second scan signal wiring to which a second scan signal SCAN2 is applied. The second transistor T2 can be turned on or off by the second scan signal SCAN2. Therefore, the second transistor T2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT in response to the second scan signal SCAN2 at a turn-on level, which is a low level.

[0054] The third transistor T3 can apply a reference voltage Vref to the first node N1. The third transistor T3 includes a source electrode connected to a reference wiring that transmits the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to a light emission signal wiring. The third transistor T3 can be turned on or off by the light emission signal EM. Therefore, the third transistor T3 can transmit the reference voltage Vref to the first node N1 in response to the light emission signal EM at a turn-on level, which is a low level.

[0055] When the fourth transistor T4 is driven in the wide viewing angle mode which is the first mode, it can form a current path between the driving transistor DT and the first light emitting element ED1. The fourth transistor T4 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the first light emitting element ED1, and a gate electrode connected to the first mode control wiring to which the first mode signal MS1 is applied. The fourth transistor T4 can be turned on or off by the first mode signal MS1. Therefore, the fourth transistor T4 forms a current path between the fourth node N4 which is the source electrode of the fourth transistor T4 and the first light emitting element ED1 in response to the first mode signal MS1 which is at the turn-on level and is a low level. That is, the fourth transistor T4 forms a current path between the driving transistor DT and the first light emitting element ED1 in response to the first mode signal MS1 which is at a low level. Therefore, the fourth transistor T4 can also be referred to as the first light emission control transistor that controls the light emission of the first light emitting element ED1.

[0056] Here, the first mode signal MS1 is provided by the first level shifter LS1 which will be described later, and can control the driving (or light emission) of the first light emitting element ED1 where the first lens is disposed.

[0057] The fifth transistor T5 can apply the reference voltage Vref to the anode electrode of the first light emitting element ED1. The fifth transistor T5 includes a source electrode connected to the reference wiring that transmits the reference voltage Vref, a drain electrode connected to the anode electrode of the first light emitting element ED1, and a gate electrode connected to the second scan signal wiring to which the second scan signal SCAN2 is applied. The fifth transistor T5 can be turned on or off by the second scan signal SCAN2. Therefore, the fifth transistor T5 can apply the reference voltage Vref to the anode electrode of the first light emitting element ED1 in response to the second scan signal SCAN2 which is at the turn-on level and is a low level.

[0058] The sixth transistor T6 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2. The sixth transistor T6 includes a source electrode connected to a reference wiring for transmitting the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second scan signal wiring to which a second scan signal SCAN2 is applied. The sixth transistor T6 can be turned on or off by the second scan signal SCAN2. Therefore, the sixth transistor T6 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2 in response to the second scan signal SCAN2 at a turn-on level, which is a low level.

[0059] The seventh transistor T7 can form a current path between the driving transistor DT and the second light-emitting element ED2 when driven in a narrow viewing angle mode, which is the second mode. The seventh transistor T7 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second mode control wiring to which a second mode signal MS2 is applied. The seventh transistor T7 can be turned on or off by the second mode signal MS2. Therefore, the seventh transistor T7 forms a current path between the fourth node N4, which is the source electrode of the seventh transistor T7, and the second light-emitting element ED2 in response to the second mode signal MS2 at a turn-on level, which is a low level. That is, the seventh transistor T7 forms a current path between the driving transistor DT and the second light-emitting element ED2 in response to the low-level second mode signal MS2. Therefore, the seventh transistor T7 can also be referred to as a second light-emitting control transistor that controls the light emission of the second light-emitting element ED2.

[0060] Here, the second mode signal MS2 is provided by a second level shifter LS2, which will be described later, and can control the driving (or light emission) of the second light-emitting element ED2 where the second lens is disposed.

[0061] The eighth transistor T8 can apply the drive current of the drive transistor DT to the fourth node N4. The eighth transistor T8 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to a light emission signal wiring that transmits the light emission signal EM. The eighth transistor T8 can be turned on or off by the light emission signal EM. Therefore, the eighth transistor T8 can transmit the drive current to the fourth node N4 in response to the light emission signal EM at a low level which is the turn-on level.

[0062] The storage capacitor Cst includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the drive transistor DT, and the other electrode of the storage capacitor Cst is connected to the first transistor T1. The storage capacitor Cst can store a constant voltage and keep the voltage of the gate electrode of the drive transistor DT constant while the light emitting element emits light.

[0063] The first light emitting element ED1 can be connected to the fourth transistor T4 that is turned on or off by the first mode signal MS1. The second light emitting element ED2 can be connected to the seventh transistor T7 that is turned on or off by the second mode signal MS2.

[0064] In such a case, the first light emitting element ED1 or the second light emitting element ED2 can be connected to other components of the sub-pixel circuit SPC, for example, the drive transistor DT, depending on the mode. The mode can be specified by a user input or determined when a pre-specified condition is satisfied. For example, when a pre-specified first condition is satisfied, the first light emitting element ED1 can emit light based on the supply of the first mode signal MS1. When a pre-specified second condition is satisfied, the second light emitting element ED2 can emit light based on the supply of the second mode signal MS2. The first condition can include the pre-specified conditions for driving in the first mode. The second condition can include the pre-specified conditions for driving in the second mode.

[0065] When the first mode signal MS1 is input at a low value, the sub-pixel circuit can operate in the first mode. When the second mode signal MS2 is input at a low value, the sub-pixel circuit can operate in the second mode. At this time, the first mode may be a wide viewing angle mode, and the second mode may be a narrow viewing angle mode.

[0066] Specifically, the first light-emitting element ED1 emits light in the wide viewing angle mode which is the first mode. As will be described later, a semi-cylindrical first lens 161 is disposed on the first light-emitting element ED1, and the wide viewing angle mode can be realized. The first light-emitting element ED1 includes an anode electrode connected to the fourth transistor T4 and a cathode electrode connected to a low potential power supply wiring to which a low potential power supply VSS is applied. The first light-emitting element ED1 receives the supply of the drive current of the drive transistor DT through the fourth transistor T4 turned on in the wide viewing angle mode. Therefore, when driven in the wide viewing angle mode, the first light-emitting element ED1 can emit light by receiving the supply of the drive current.

[0067] The second light-emitting element ED2 emits light in the narrow viewing angle mode. A hemispherical second lens 162 is disposed on the second light-emitting element ED2, and the narrow viewing angle mode can be realized. The second light-emitting element ED2 includes an anode electrode connected to the seventh transistor T7 and a cathode electrode connected to the low potential power supply wiring. The second light-emitting element ED2 receives the supply of the drive current of the drive transistor DT through the seventh transistor T7 turned on in the narrow viewing angle mode. Therefore, when driven in the narrow viewing angle mode, the second light-emitting element ED2 can emit light by receiving the supply of the drive current.

[0068] FIGS. 3A and 3B are waveform diagrams for explaining the sub-pixel circuit of a display device according to an embodiment of the present specification. Specifically, FIG. 3A is a waveform diagram for explaining the realization of the wide viewing angle mode which is the first mode, and FIG. 3B is a waveform diagram for explaining the sub-pixel circuit for realizing the narrow viewing angle mode which is the second mode.

[0069] Referring to both FIGS. 2 to 3b, in the wide viewing angle mode, only the first light emitting element ED1 emits light, and in the narrow viewing angle mode, only the second light emitting element ED2 emits light. In the wide viewing angle mode, a second mode signal MS2 for controlling the light emission of the second light emitting element ED2 is output only at a high level which is a turn-off level so that only the first light emitting element ED1 emits light. In the narrow viewing angle mode, a first mode signal MS1 for controlling the light emission of the first light emitting element ED1 is output only at a high level which is a turn-off level so that only the second light emitting element ED2 emits light.

[0070] Specifically, referring to FIGS. 2 and 3a and considering the wide viewing angle mode, a low-level second scan signal SCAN2, a low-level first mode signal MS1, and a low-level light emission signal EM are output during an initial period Ti. The second scan signal SCAN2 at a low level can turn on the second transistor T2, the fifth transistor T5, and the sixth transistor T6. The first mode signal MS1 at a low level turns on the fourth transistor T4. The light emission signal EM at a low level can turn on the third transistor T3 and the eighth transistor T8.

[0071] Through the turned-on third transistor T3, the first node N1 can be initialized to the reference voltage Vref. Through the turned-on fifth transistor T5, the voltage of the anode electrode of the first light-emitting element ED1 is initialized to the reference voltage Vref, and through the turned-on sixth transistor T6, the voltage of the anode electrode of the second light-emitting element ED2 can be initialized to the reference voltage Vref. Then, through the turned-on second transistor T2, the driving transistor DT is diode-connected, and by shorting the gate electrode and the drain electrode of the driving transistor DT, the driving transistor DT operates like a diode. And the reference voltage Vref transmitted to the anode electrode side of the first light-emitting element ED1 through the turned-on fifth transistor T5 is transmitted to the third node N3 and the second node N2 through the turned-on fourth transistor T4 and eighth transistor T8, and the fourth node N4, the third node N3, and the second node N2 can also be initialized to the reference voltage Vref.

[0072] Next, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 are output during the sampling period Ts, and the first mode signal MS1 can be output at a high level. When a high-level light-emitting signal EM is output and the third transistor T3 is turned off, at the same time, the first transistor T1 is turned on by the low-level first scan signal SCAN1, and the data voltage Vdata can be transmitted to the first node N1. Then, the driving transistor DT is diode-connected by the turned-on second transistor T2, and the differential voltage between the high-potential power supply voltage and the threshold voltage can be sampled and supplied to the second node N2.

[0073] During the holding period Th, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can all be turned off. However, even if the first transistor T1 is turned off, the data voltage Vdata input during the previous sampling period Ts can be maintained by the storage capacitor Cst.

[0074] Finally, during the emission period Te, a low-level first mode signal MS1 and an emission signal EM are output, and a high-level second mode signal MS2 is output. The reference voltage Vref is applied to the first node N1 through the third transistor T3 turned on by the low-level emission signal EM, and the voltage of the first node N1 can become the differential voltage between the reference voltage Vref and the data voltage Vdata, and such voltage fluctuations can also be reflected in the second node N2. The gate-source voltage Vgs of the driving transistor DT can be set to the value (Vdata - Vref + Vth) obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata, thereby controlling the driving current.

[0075] Then, a driving current is supplied from the driving transistor DT to the first light-emitting element ED1 through the turned-on fourth transistor T4 and eighth transistor T8, enabling the first light-emitting element ED1 to emit light. However, since the second mode signal MS2 is output at a high level and the seventh transistor T7 is turned off, the driving current cannot be transmitted from the driving transistor DT to the second light-emitting element ED2. Therefore, in the wide viewing angle mode, the driving current is applied only to the first light-emitting element ED1, and only the first light-emitting element ED1 can emit light.

[0076] Referring to FIGS. 2 and 3b, when considering the narrow field of view mode, the sub-pixel circuit SPC can be driven in substantially the same manner as the wide field of view mode except that the first mode signal MS1 and the second mode signal MS2 are output in opposite directions. That is, the first mode signal MS1 is output only at a high level which is a turn-off level, and the second mode signal MS2 can be output at a low level which is a turn-on level during the emission period Te when the second light emitting element ED2 emits light.

[0077] Specifically, during the initial period Ti, the first scan signal SCAN1 is output at a high level, and the second scan signal SCAN2 is output at a low level. Then, the first mode signal MS1 is output at a high level, and the second mode signal MS2 and the emission signal EM are output at a low level. Therefore, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be turned on by the second scan signal SCAN2, the seventh transistor T7 can be turned on by the second mode signal MS2, and the third transistor T3 and the eighth transistor T8 can be turned on by the emission signal EM.

[0078] Through the third transistor T3 turned on by the emission signal EM, the first node N1 is initialized to the reference voltage Vref, and the anode electrodes of the first light emitting element ED1 and the second light emitting element ED2 can be initialized to the reference voltage Vref by the fifth transistor T5 and the sixth transistor T6 turned on by the second scan signal SCAN2, respectively. Then, the driving transistor DT is diode-connected through the turned-on second transistor T2 and operates like a diode. Finally, the reference voltage Vref transmitted to the anode electrode side of the second light emitting element ED2 through the turned-on sixth transistor T6 is transmitted to the fourth node N4, the third node N3, and the second node N2 through the turned-on seventh transistor T7, and the third node N3 and the second node N2 can also be initialized to the reference voltage Vref.

[0079] Next, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 are output during the sampling period Ts, and the second mode signal MS2 and the emission signal EM can be output from the low level to the high level. When the high-level emission signal EM is output, the third transistor T3 is turned off, and the first transistor T1 is turned on by the low-level first scan signal SCAN1, and the data voltage Vdata can be transmitted to the first node N1. Then, the driving transistor DT is diode-connected by the turned-on second transistor T2, and the differential voltage between the high-potential power supply voltage and the threshold voltage can be sampled and supplied to the second node N2.

[0080] Then, during the holding period Th, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can all be turned off. However, even if the first transistor T1 is turned off, the data voltage Vdata input during the previous sampling period Ts can be maintained by the storage capacitor Cst.

[0081] Finally, during the emission period Te, a low-level second mode signal MS2 and an emission signal EM are output, and a high-level first mode signal MS1 is output. The reference voltage Vref is applied to the first node N1 through the third transistor T3 turned on by the low-level emission signal EM, and the voltage of the first node N1 can become the differential voltage between the reference voltage Vref and the data voltage Vdata, and such voltage fluctuations can also be reflected in the second node N2. The gate-source voltage Vgs of the driving transistor DT is set to the value obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata (Vdata - Vref + Vth), and the driving current can be controlled.

[0082] Then, a drive current can be supplied from the drive transistor DT to the second light-emitting element ED2 through the turned-on seventh transistor T7 so that the second light-emitting element ED2 can emit light. However, since the first mode signal MS1 is output at a high level and the fourth transistor T4 is turned off, the drive current cannot be transmitted from the drive transistor DT to the first light-emitting element ED1. Therefore, in the narrow viewing angle mode, the drive current is applied only to the second light-emitting element ED2, and only the second light-emitting element ED2 can emit light.

[0083] Figures 4a and 4b are cross-sectional views of a display device according to an embodiment of the present specification. Specifically, Figure 4a shows a sub-pixel in which a first lens 161 is disposed, and Figure 4b shows a sub-pixel in which a second lens 162 is disposed.

[0084] Referring to Figures 4a and 4b, the display device 100 according to the embodiment of the present specification may include a substrate 110, a buffer film 111, a gate insulating film 112, an interlayer insulating film 113, a lower protective film 114, an overcoat layer 115, a first transistor T1, a second transistor T2, a first light-emitting element ED1, a second light-emitting element ED2, a first lens 161, a second lens 162, a lens protective film 170, and a sealing member 180.

[0085] The substrate 110 may include an insulating material. The substrate 110 may include a transparent material. For example, the substrate 110 may include glass or plastic.

[0086] A buffer film 111 may be disposed on the substrate 110. The buffer film 111 may include an insulating material. For example, the buffer film 111 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 111 may have a multilayer structure. For example, the buffer film 111 may have a laminated structure of a film made of silicon nitride (SiNx) and a film made of silicon oxide (SiOx).

[0087] The buffer film 111 can be positioned between the substrate 110 and the driving portions of each pixel PX. The buffer film 111 can prevent contamination of the substrate 110 in the process of forming the driving portions. For example, the upper surface of the substrate 110 facing the driving portions of each pixel PX can be covered by the buffer film 111. The driving portions of each pixel PX can be positioned on the buffer film 111.

[0088] A gate insulating film 112 can be disposed on the buffer film 111. The gate insulating film 112 can contain an insulating material. For example, the gate insulating film 112 can contain an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating film 112 can contain a material having a high dielectric constant. For example, the gate insulating film 112 can contain a High-K material such as hafnium oxide (HfO). The gate insulating film 112 can have a multilayer structure.

[0089] The gate insulating film 112 can extend between the semiconductor layers 121, 131 and the gate electrodes 122, 132 of the transistors Tr1, Tr2. For example, the gate electrodes of the driving transistor DT and the switching transistor ST can be insulated from the semiconductor layers of the driving transistor DT and the switching transistor ST by the gate insulating film 112. The gate insulating film 112 can cover the semiconductor layer of each pixel PX. The gate electrodes of the driving transistor DT and the switching transistor ST can be positioned on the gate insulating film 112.

[0090] An interlayer insulating film 113 can be disposed on the gate insulating film 112. The interlayer insulating film 113 can contain an insulating material. For example, the interlayer insulating film 113 can contain an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The interlayer insulating film 113 can extend between the gate electrode and the source electrode, and between the gate electrode and the drain electrode of each of the driving transistor DT and the switching transistor. For example, the source electrode and the drain electrode of each of the driving transistor DT and the switching transistor can be insulated from the gate electrode by the interlayer insulating film 113. The interlayer insulating film 113 can cover the gate electrodes of each of the driving transistor DT and the switching transistor. The source electrode and the drain electrode of each pixel PX can be located on the interlayer insulating film 113. The gate insulating film 112 and the interlayer insulating film 113 can expose the source region and the drain region of each semiconductor pattern located within each pixel PX.

[0091] An under protection film 114 can be disposed on the interlayer insulating film 113. The under protection film 114 can contain an insulating material. For example, the under protection film 114 can contain an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The under protection film 114 can prevent damage to the driving part due to external moisture and impact. The under protection film 114 can extend along the surfaces of the driving transistor DT and the switching transistor ST facing the substrate 110. The under protection film 114 can contact the interlayer insulating film 113 outside the driving part located within each pixel PX.

[0092] An overcoat layer 115 can be disposed on the under protection film 114. The overcoat layer 115 can contain an insulating material. The overcoat layer 115 can contain a material different from that of the under protection film 114. For example, the overcoat layer 115 can contain an organic insulating material. The overcoat layer 115 can remove the step caused by the driving part of each pixel PX. For example, the upper surface of the overcoat layer 115 facing the substrate 110 can be a flat surface.

[0093] On the substrate 110, the first transistor Tr1 and the second transistor Tr2 can be arranged. The first transistor Tr1 can be electrically connected between the drain electrode of the driving transistor DT and the first lower electrode 141 of the first light-emitting element ED1. The second transistor Tr2 can be electrically connected between the drain electrode of the driving transistor DT and the second lower electrode 151 of the second light-emitting element ED2.

[0094] The first transistor Tr1 can include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first transistor T1 can have the same structure as the switching transistor and the driving transistor DT. For example, the first semiconductor layer 121 can be located between the buffer film 111 and the gate insulating film 112, and the first gate electrode 122 can be located between the gate insulating film 112 and the interlayer insulating film 113. The first source electrode 123 and the first drain electrode 124 can be located between the interlayer insulating film 113 and the lower protective film 114. The first gate electrode 122 can overlap the channel region of the first semiconductor layer 121. The first source electrode 123 can be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 can be electrically connected to the drain region of the first semiconductor layer 121.

[0095] The second transistor T2 can include a second semiconductor layer 131, a second gate electrode 132, a second source electrode 133, and a second drain electrode 134. For example, the second semiconductor layer 131 can be located in the same layer as the first semiconductor layer 121, the second gate electrode 132 can be located in the same layer as the first gate electrode 122, and the second source electrode 133 and the second drain electrode 134 can be located in the same layer as the first source electrode 123 and the first drain electrode 124.

[0096] The first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX can be arranged on the overcoat layer 115 of the corresponding pixel PX.

[0097] The first light-emitting element ED1 can emit light showing a specific color. For example, the first light-emitting element ED1 can include a first lower electrode 141, a first light-emitting layer 142, and a first upper electrode 143 that are sequentially stacked on a substrate 110.

[0098] The first lower electrode 141 can include a conductive material. The first lower electrode 141 can include a material having a high reflectivity. For example, the first lower electrode 141 can include metals such as aluminum (Al) and silver (Ag). The first lower electrode 141 can have a multilayer structure. For example, the first lower electrode 141 can have a structure in which a reflective electrode made of a metal is positioned between transparent electrodes made of transparent conductive materials such as ITO and IZO. The first lower electrode 141 can be electrically connected to the first drain electrode 124 (or the first source electrode 123) of the first transistor T1 through a contact hole penetrating a lower protective film 114 and an overcoat layer 115.

[0099] The first light-emitting layer 142 can generate light having a luminance corresponding to the voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light-emitting layer 142 can include an emission material layer (EML) containing an emission material. The emission material can include an organic material, an inorganic material, or a hybrid material.

[0100] The first light-emitting layer 142 can have a multilayer structure. For example, the first light-emitting layer 142 can further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0101] The first upper electrode 143 can contain a conductive material. The first upper electrode 143 can contain a material different from that of the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than that of the first lower electrode 141. For example, the first upper electrode 143 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. As a result, in the display device according to the embodiment of this specification, the light generated by the first light-emitting layer 142 can be emitted through the first upper electrode 143.

[0102] The second light-emitting element ED2 can have the same structure as the first light-emitting element ED1. For example, the second light-emitting element ED2 can include a second lower electrode 151, a second light-emitting layer 152, and a second upper electrode 153 that are sequentially stacked on the substrate 110.

[0103] The second lower electrode 151 can correspond to the first lower electrode 141, the second light-emitting layer 152 can correspond to the first light-emitting layer 142, and the second upper electrode 153 can correspond to the first upper electrode 143. For example, the second lower electrode 151 can be formed with the same structure as the first lower electrode 141 for the second light-emitting element ED2, and this is the same for the second light-emitting layer 152 and the second upper electrode 153. For example, the first light-emitting element ED1 and the second light-emitting element ED2 can be formed to have the same structure. However, it is not limited thereto, and in some cases, at least some of the configurations of the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to be different.

[0104] In the embodiment, the second light-emitting layer 152 can be separated from the first light-emitting layer 142. As a result, in the display device according to the embodiment of this specification, light emission due to leakage current can be prevented.

[0105] According to the embodiment of this specification, in the display device, light can be generated only in one of the first light-emitting layer 142 and the second light-emitting layer 152 according to a user's selection or a preset condition.

[0106] The second lower electrode 151 of each pixel PX can be separated from the first lower electrode 141 of the corresponding pixel PX. For example, a bank insulating film 116 can be disposed between the first lower electrode 141 and the second lower electrode 151 of each pixel PX. The bank insulating film 116 can include an insulating material. For example, the bank insulating film 116 can include an organic insulating material. The bank insulating film 116 can include a material different from that of the overcoat layer 115.

[0107] The second lower electrode 151 of each pixel PX can be insulated from the first lower electrode 141 of the corresponding pixel PX by the bank insulating film 116. For example, the bank insulating film 116 can cover the edges of the first lower electrode 141 and the second lower electrode 151 located within each pixel PX. Thereby, in the display device, an image by the first lens region of each pixel PX where the first light-emitting element ED1 is located or an image by the second lens region of each pixel PX where the second light-emitting element ED2 is located can be provided to the user.

[0108] The first light-emitting layer 142 and the first upper electrode 143 of the first light-emitting element ED1 located within each pixel PX can be stacked on a partial region of the corresponding first lower electrode 141 exposed by the bank insulating film 116. The second light-emitting layer 152 and the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX can be stacked on a partial region of the corresponding second lower electrode 151 exposed by the bank insulating film 116. For example, the bank insulating film 116 can divide a first light-emitting region where light is emitted by the first light-emitting element ED1 and a second light-emitting region where light is emitted by the second light-emitting element ED2 within each pixel PX. The size of the second light-emitting region divided within each pixel PX may be smaller than the size of the first light-emitting region.

[0109] The second upper electrode 153 of each pixel PX can be electrically connected to the first upper electrode 143 of the corresponding pixel PX. For example, the voltage applied to the second upper electrode 153 of the second light-emitting element ED2 located in each pixel PX may be the same as the voltage applied to the first upper electrode 143 of the first light-emitting element ED1 located in the corresponding pixel PX. The second upper electrode 153 of each pixel PX can include the same material as the first upper electrode 143 of the corresponding pixel PX. For example, the second upper electrode 153 of each pixel PX can be formed simultaneously with the first upper electrode 143 of the corresponding pixel PX. The second upper electrode 153 of each pixel PX can extend on the bank insulating film 116 and directly contact the first upper electrode 143 of the corresponding pixel PX. The luminance of the first lens region and the luminance of the second lens region located in each pixel PX can be controlled by the driving current generated in the corresponding pixel PX.

[0110] A sealing member 180 can be positioned on the first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX. The sealing member 180 can prevent damage to the light-emitting elements ED1 and ED2 due to moisture and impact from the outside. The sealing member 180 can have a multilayer structure. For example, the sealing member 180 can include, but is not limited to, a first sealing layer 181, a second sealing layer 182, and a third sealing layer 183 laminated in sequence. The first sealing layer 181, the second sealing layer 182, and the third sealing layer 183 can include an insulating material. The second sealing layer 182 can include a material different from that of the first sealing layer 181 and the third sealing layer 183. For example, the first sealing layer 181 and the third sealing layer 183 are inorganic sealing layers including an inorganic insulating material, and the second sealing layer 182 can include an organic sealing layer including an organic insulating material. Thereby, damage to the light-emitting elements ED1 and ED2 of the display device due to moisture and impact from the outside can be more effectively prevented.

[0111] A first lens 161 and a second lens 162 can be positioned on the sealing member 180 of each pixel PX. On the other hand, the term "lens" used in this specification is used for convenience of explanation and can also be defined as the term "optical member" instead of "lens".

[0112] The first lens 161 can be disposed on the first light-emitting element ED1. The light generated by the first light-emitting element ED1 of each pixel PX can be emitted through the first lens 161 of the corresponding pixel PX. The first lens 161 can have a shape such that the light in at least one lateral direction does not need to be restricted. For example, the planar shape of the first lens 161 located within each pixel PX can have a bar shape extending in the first direction.

[0113] In such a case, the traveling direction of the light emitted in the first lens region of the pixel PX does not need to be restricted in the first direction. For example, the content (or image) provided through the first lens region of the pixel PX can be shared with the user and the people around adjacent to the first direction. When providing content through the first lens region, it can be called a wide-angle mode, which is a mode of providing content in a first viewing angle range wider than the second viewing angle range provided by the second lens region, and is the first mode.

[0114] The second lens 162 can be disposed on the second light-emitting element ED2. The light generated by the second light-emitting element ED2 of each pixel PX can be emitted through the second lens 162 of the corresponding pixel PX. The second lens 162 can restrict the traveling direction of the passing light in the first direction and / or the second direction. For example, the planar shape of the second lens 162 located within the pixel PX can have a circular shape. In such a case, the traveling direction of the light emitted in the second lens region of the pixel PX can be restricted in the first direction and the second direction. For example, the content provided by the second lens region of the pixel PX does not need to be shared with the people around the user. When providing content through the second lens region, it can be called a narrow-angle mode, which is a mode of providing content in a second viewing angle range narrower than the first viewing angle range provided by the first lens region, and is the second mode.

[0115] The first light-emitting region of each pixel PX may have a shape corresponding to the first lens 161 of the corresponding pixel PX. For example, the planar shape of the first light-emitting region of each pixel PX may have a bar shape extending in the first direction. The first lens 161 may have a size larger than that of the first light-emitting region of the corresponding pixel PX. Thereby, the efficiency of the light emitted from the first light-emitting region of the pixel PX can be improved.

[0116] The second light-emitting region of each pixel PX may have a shape corresponding to the second lens 162 of the corresponding pixel PX. For example, the planar shape of the second light-emitting region of each pixel PX may have a circular shape. The second lens 162 may have a size larger than that of the second light-emitting region of the corresponding pixel PX. Thereby, the efficiency of the light emitted from the second light-emitting region of the pixel PX can be improved.

[0117] In an embodiment, a lens protection film 170 may be located on the first lens 161 and the second lens 162 of the pixel PX. The lens protection film 170 may include an insulating material. For example, the lens protection film 170 may include an organic insulating material. The refractive index of the lens protection film 170 may be smaller than the refractive indices of the first lens 161 and the second lens 162 located within each pixel PX. Thereby, in the display device according to the embodiments of the present specification, the light passing through the first lens 161 and the second lens 162 of each pixel PX does not need to be reflected in the direction of the substrate 110 due to the refractive index difference with the lens protection film 170.

[0118] FIG. 5 is a plan view of a display device according to an embodiment of the present specification. In FIG. 5, for convenience of explanation, only the display panel PN, a plurality of flexible films COF, and a plurality of printed circuit boards PCB among various components of the display device 100 are shown.

[0119] Referring to FIG. 5, the display device 100 includes a plurality of flexible films COF, a plurality of printed circuit boards PCB, and a display panel PN.

[0120] A plurality of flexible film COFs can be arranged at one end of the display panel PN. The plurality of flexible film COFs are films on which various components are arranged on a ductile base film and supply signals to a plurality of pixels PX and a driving circuit, and can be electrically connected to the display panel PN. For example, the plurality of flexible film COFs can supply a power supply voltage, a data voltage Vdata, etc. to the plurality of pixels PX and the driving circuit.

[0121] On the other hand, a driving IC such as a data driver IC can be arranged on the plurality of flexible film COFs. The driving IC is a component that processes data for displaying an image and a driving signal for processing the same. The driving IC can be arranged in a method such as Chip On Glass (COG), Chip On Film (COF), Tape Carrier Package (TCP), etc. according to the mounting method. However, for the sake of convenience of explanation, it has been described that the driving IC is in the Chip On Film method mounted on the plurality of flexible film COFs, but it is not limited thereto. Also, the driving IC may be integrated with a timing controller and arranged in a single chip.

[0122] On the other hand, a plurality of mode control units for controlling driving in a wide viewing angle mode and a narrow viewing angle mode can be arranged in the driving IC. The mode control unit can provide signals for controlling the modes of the plurality of sub-pixels SP to the plurality of sub-pixels SP. The plurality of mode control units can provide a first mode selection signal for controlling the first mode through the first mode selection signal wiring MCSL1. Also, a second mode selection signal for controlling the second mode can be provided through the second mode selection signal wiring MCSL2. The mode control unit can be defined as a configuration included in the timing controller TC, and can also be defined as a configuration separate from the timing controller TC.

[0123] Each of the plurality of printed circuit boards (PCBs) is electrically connected to a plurality of flexible films (COFs). The plurality of PCBs are components that supply signals to the driving IC. A variety of components for supplying various signals such as driving signals and data signals to the driving IC can be arranged on the plurality of PCBs.

[0124] The display panel (PN) can include a display area (AA) and a non-display area (NA) surrounding the display area (AA). The display area (AA) of the display panel (PN) includes a plurality of regions (a) divided in the row direction. The plurality of regions (a) may be regions of pixels (PX) to which the same mode signal is applied. On the other hand, in FIG. 5, the display area (AA) is shown as being divided into 12 regions (a) extending in the column direction, but it is not limited thereto.

[0125] The display panel (PN) can include a first mode selection signal wiring (MCSL1) and a second mode selection signal wiring (MCSL2) extending side by side in the row or column direction in the plurality of regions (a). The first mode selection signal wiring (MCSL1) and the second mode selection signal wiring (MCSL2) are each connected to a mode control unit and can transmit a first mode selection signal and a second mode selection signal to the plurality of regions (a). The first mode selection signal transmitted by the first mode selection signal wiring (MCSL1) and the second mode selection signal transmitted by the second mode selection signal wiring (MCSL2) can each have their voltage changed by a level shift described later and be output as a first mode signal (MS1) and a second mode signal (MS2). Therefore, the first mode selection signal wiring (MCSL1) can also be referred to as a wide viewing angle mode selection signal wiring, and the second mode selection signal wiring (MCSL2) can also be referred to as a narrow viewing angle mode selection signal wiring. On the other hand, in FIG. 5, the plurality of first mode selection signal wirings (MCSL1) and the plurality of second mode selection signal wirings (MCSL2) are shown as extending in the column direction in the plurality of regions (a), but it is not limited thereto and can extend in the row direction.

[0126] FIG. 6 is a schematic enlarged plan view of the display area of a display device according to an embodiment of the present specification. In FIG. 6, a part of one of the plurality of regions (a) in FIG. 5, for example, a region corresponding to a total of 12 pixels (PX) is shown.

[0127] Referring to FIG. 6, a level shifter LS that provides a mode signal to a plurality of sub-pixels SP is disposed in the display area AA. The level shifter LS can provide a plurality of sub-pixels SP with mode signals MS1 and MS2 that control the driving mode of the display panel PN so that the plurality of sub-pixels SP are driven in either the first mode or the second mode. Specifically, the level shifter LS can change the output voltages of the first mode selection signal and the second mode selection signal. For example, the level shifter LS can change a low voltage output by the mode control unit, for example, a logic voltage of 1.8V or 3.3V, to a high voltage, for example, a value within the range of VGL(-9.0V) to VGH(15.0V). That is, the level shifter LS can change the output voltages of the first mode selection signal and the second mode selection signal provided by the mode control unit to provide a first mode signal or a second mode signal. For example, the level shifter LS includes a first level shifter LS1 that provides a first mode signal MS1 and a second level shifter LS2 that provides a second mode signal MS2. Therefore, since the first level shifter LS1 provides a first mode signal MS1 that controls the driving mode in the wide viewing angle mode, it is called a wide viewing angle mode level shifter, and the second level shifter LS2 can also be called a narrow viewing angle mode level shifter since it provides a second mode signal MS2 that controls the driving mode in the narrow viewing angle mode.

[0128] The first level shifter LS1 and the second level shifter LS2 can each be disposed one by one in each of the plurality of regions a. That is, the first level shifter LS1 and the second level shifter LS2 can each transmit a mode signal for each of the plurality of regions a. For example, the first level shifter LS1 and the second level shifter LS2 can each be configured with the same number as the plurality of regions a and can be disposed one by one in each of the plurality of regions a.

[0129] The plurality of regions a include pixels PX and non-pixel regions NPX. The pixel PX includes a plurality of sub-pixels SP. The non-pixel region NPX can be disposed between adjacent pixels PX. The non-pixel region NPX can refer to a region where no sub-pixel SP is disposed.

[0130] The first-level shift LS1 and the second-level shift LS2 are arranged between adjacent pixels PX. For example, when one region a includes 12 pixels PX, the first-level shift LS1 and the second-level shift LS2 can be arranged with 6 pixels PX in between. On the other hand, in FIG. 6, it is shown that 3 pixels PX are arranged in the same row and 2 pixels PX are arranged in the same column, but this is only an exemplary illustration and is not limited thereto.

[0131] On the other hand, the first-level shift LS1 and the second-level shift LS2 can be respectively arranged in the non-pixel region NPX between the pixels PX. However, it is not limited thereto. When one region a includes 3 or more pixels PX, the first-level shift LS1 and the second-level shift LS2 can be respectively arranged at two positions among the multiple adjacent pixels PX.

[0132] FIG. 7 is a circuit diagram of the first-level shift of the display device according to an embodiment of the present specification.

[0133] Referring to FIG. 7, the first-level shift LS1 includes the 11th transistor T11, the 12th transistor T12, the 13th transistor T13, the 14th transistor T14, the 15th transistor T15, the 16th transistor T16, the 17th transistor T17, the 11th capacitor C11, and the 12th capacitor C12.

[0134] On the other hand, as described above, since the first-level shift LS1 is arranged within the display area AA, it can share the signal wiring with a plurality of sub-pixel circuits SPC. That is, the first-level shift LS1 can share the first scan signal wiring, the second scan signal wiring, and the light emission signal wiring with the sub-pixel circuit SPC.

[0135] The 11th transistor T11 to the 17th transistor T17 may be p-type thin film transistors. In the case of p-type thin film transistors, the low level voltage of each drive signal may mean a voltage for turning on the TFT, and the high level voltage of each drive signal may mean a voltage for turning off the TFT.

[0136] The 11th transistor T11 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 11th node N11 which is the first electrode of the 11th capacitor C11. Therefore, the 11th transistor T11 is turned on or off by the first scan signal SCAN1, and can transmit the second mode selection signal MCS2 to the 11th node N11 which is the first electrode of the 11th capacitor C11.

[0137] The 12th transistor T12 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 12th node N12 which is the second electrode of the 11th capacitor C11. Therefore, the 12th transistor T12 is turned on or off by the first scan signal SCAN1, and can transmit the first mode selection signal MCS1 to the 12th node N12 which is the second electrode of the 11th capacitor C11.

[0138] The 13th transistor T13 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 13th node N13 which is the first electrode of the 12th capacitor C12. Therefore, the 13th transistor T13 is turned on or off by the second scan signal SCAN2, and can transmit the second mode selection signal MCS2 to the 13th node N13 which is the first electrode of the 12th capacitor C12.

[0139] The 14th transistor T14 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 14th node N14 which is the second electrode of the 12th capacitor C12. Therefore, the 14th transistor T14 is turned on or off by the first scan signal SCAN1, and can transmit the first mode selection signal MCS1 to the 14th node N14 which is the second electrode of the 12th capacitor C12.

[0140] The 15th transistor T15 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 15th node N15. Therefore, the 15th transistor T15 is turned on or off by the second scan signal SCAN2, and can transmit the first mode selection signal MCS1 to the 14th node N14 which is the second electrode of the 12th capacitor C12.

[0141] The 16th transistor T16 includes a gate electrode connected to the light emission signal wiring, a source electrode connected to the reference wiring that transmits the reference voltage Vref, and a drain electrode connected to the 15th node N15. Therefore, the 16th transistor T16 is turned on or off by the light emission signal EM, and can transmit the reference voltage Vref to the 14th node N14 which is the second electrode of the 12th capacitor C12.

[0142] The 17th transistor T17 includes a gate electrode connected to the light emission signal wiring, a source electrode connected to the 11th node N11 which is the first electrode of the 11th capacitor C11, and a drain electrode connected to a plurality of sub-pixels SP. Therefore, the 17th transistor T17 is turned on or off by the light emission signal EM, and can transmit the first mode signal MS1 to the plurality of sub-pixels SP.

[0143] The 11th capacitor C11 includes a first electrode connected to the 11th node N11 and a second electrode connected to the 12th node N12. The 12th capacitor C12 includes a first electrode connected to the 13th node N13 and a second electrode connected to the 14th node N14. On the other hand, the 11th capacitor C11 and the 12th capacitor C12 can be connected in series.

[0144] FIG. 8 is a waveform diagram for explaining the first level shift circuit of the display device according to an embodiment of the present specification. FIG. 9a is a circuit diagram of the first level shift of the display device according to an embodiment of the present invention during the first period in the wide viewing angle mode. FIG. 9b is a circuit diagram of the first level shift of the display device according to an embodiment of the present invention during the second period in the wide viewing angle mode. FIG. 9c is a circuit diagram of the first level shift of the display device according to an embodiment of the present invention during the third period in the wide viewing angle mode. Hereinafter, the voltage value corresponding to the first mode selection signal MCS1 may be referred to as "V1", which is the first voltage, and the voltage value corresponding to the second mode selection signal MCS2 may be referred to as "V2", which is the second voltage.

[0145] Referring to both FIGS. 8 and 9a, in the wide viewing angle mode, a low-level first scan signal SCAN1 and a low-level second mode selection signal MCS2 may be output during the first period TP1. Therefore, the 11th transistor T11, the 12th transistor T12, and the 14th transistor T14 can be turned on by the low-level first scan signal SCAN1.

[0146] The second voltage "V2" can be applied to the 11th node N11 by the turned-on 11th transistor T11. The first voltage "V1" can be applied to the 12th node N12 by the turned-on 12th transistor T12. The first voltage "V1" can be applied to the 14th node N14 by the turned-on 14th transistor T14.

[0147] Therefore, in the first period TP1, the voltage of the 11th node N11 may be "V2", and the voltages of the 12th node N12 and the 13th node N13 may be "V1". Also, the 11th capacitor C11 can store the voltage difference between both electrodes, that is, "V2 - V1", which is the voltage difference between the 11th node N11 and the 12th node N12.

[0148] Next, referring to both FIGS. 8 and 9b, in the second period TP2, a low-level second scan signal SCAN2 and a low-level second mode selection signal MCS2 may be output. Therefore, the 13th transistor T13 and the 15th transistor T15 can be turned on by the low-level second scan signal SCAN2.

[0149] The turned-on 13th transistor T13 can apply a second voltage "V2" to the 13th node N13. The turned-on 15th transistor T15 can apply a first voltage "V1" to the 15th node N15.

[0150] At this time, since the 12th node N12 and the 13th node N13 have the same voltage, the voltage of the 12th node N12 may be "V2". Also, since the voltage of the 11th node N11 is the value obtained by adding the voltage "V2 - V1" stored in the 11th capacitor C11 to the voltage "V2" of the 12th node N12, the voltage of the 11th node N11 may be "V2+(V2 - V1)". Also, since the voltages of the 14th node N14 and the 15th node N15 have the same voltage, the voltage of the 14th node N14 may be "V1". Also, the 12th capacitor C12 can store the voltage difference between both electrodes, that is, "V2 - V1", which is the voltage difference between the 13th node N13 and the 14th node N14.

[0151] Finally, referring to both FIGS. 8 and 9c, in the third period T3, a low-level light emission signal EM and a low-level first mode selection signal MCS1 may be output. Therefore, the 16th transistor T16 and the 17th transistor T17 can be turned on by the low-level light emission signal EM.

[0152] A reference voltage Vref can be applied to the 15th node N15 by the turned-on 16th transistor T16. A first mode signal MS1 can be output to a plurality of sub-pixels SP by the turned-on 17th transistor T17.

[0153] At this time, since the 14th node N14 and the 15th node N15 come to have the same voltage, the voltage of the 14th node N14 may be "Vref". Also, since the voltage of the 13th node N13 is the value obtained by adding "V2 - V1", which is the voltage stored in the 12th capacitor C12, to "Vref", which is the voltage of the 14th node N14, the voltage of the 13th node N13 may be "V2+(Vref - V1)". Also, since the voltages of the 12th node N12 and the 13th node N13 come to have the same voltage, the voltage of the 12th node N12 may be "V2+(Vref - V1)". Also, since the voltage of the 11th node N11 is the value obtained by adding "V2 - V1", which is the voltage stored in the 11th capacitor C11, to "V2+(Vref - V1)", which is the voltage of the 12th node N12, the voltage of the 11th node N11 may be "V2+(V2 - V1)+(Vref - V1)".

[0154] At this time, the first mode signal MS1 can be output through the 17th transistor T17 connected to the 11th node N11. That is, "V2+(V2 - V1)+(Vref - V1)", which is the voltage of the 11th node N11, may be the voltage value of the first mode signal MS1. Since the low-level first mode signal MS1 is a turn-on signal, at this time, "V2", which is the second voltage value, can be set to be smaller than "V1", which is the first voltage value.

[0155] FIG. 10 is a circuit diagram of a second level shifter of a display device according to an embodiment of the present specification.

[0156] Referring to FIG. 10, the second level shift LS2 includes a 21st transistor T21, a 22nd transistor T22, a 23rd transistor T23, a 24th transistor T24, a 25th transistor T25, a 26th transistor T26, a 27th transistor T27, a 21st capacitor C21, and a 22nd capacitor C22.

[0157] On the other hand, since the second level shift LS2 is disposed within the display area, it can share signal wirings with a plurality of sub-pixel circuits SPC. That is, the second level shift LS2 can share the first scan signal wiring, the second scan signal wiring, and the light emission signal wiring of the display panel with the sub-pixel circuits SPC.

[0158] The 21st transistor T21 to the 27th transistor T27 may be p-type thin film transistors. In the case of p-type thin film transistors, the low level voltage of each drive signal means the voltage for turning on the TFT, and the high level voltage of each drive signal may mean the voltage for turning off the TFT.

[0159] The 21st transistor T21 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to a 21st node N21 which is the first electrode of the 21st capacitor C21. Therefore, the 21st transistor T21 can be turned on or off by the first scan signal SCAN1, and transmit the first mode selection signal MCS1 to the 21st node N21 which is the first electrode of the 21st capacitor C21.

[0160] The 22nd transistor T22 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 22nd node N22 which is the second electrode of the 21st capacitor C21. Therefore, the 22nd transistor T22 is turned on or off by the first scan signal SCAN1, and can transmit the second mode selection signal MCS2 to the 22nd node N22 which is the second electrode of the 21st capacitor C21.

[0161] The 23rd transistor T23 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 23rd node N23 which is the first electrode of the 22nd capacitor C22. Therefore, the 23rd transistor T23 is turned on or off by the second scan signal SCAN2, and can transmit the first mode selection signal MCS1 to the 23rd node N23 which is the first electrode of the 22nd capacitor C22.

[0162] The 24th transistor T24 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 24th node N24 which is the second electrode of the 22nd capacitor C22. Therefore, the 24th transistor T24 is turned on or off by the first scan signal SCAN1, and can transmit the second mode selection signal MCS2 to the 24th node N24 which is the second electrode of the 22nd capacitor C22.

[0163] The 25th transistor T25 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 25th node N25. Therefore, the 25th transistor T25 is turned on or off by the second scan signal SCAN2, and can transmit the second mode selection signal MCS2 to the 24th node N24 which is the second electrode of the 22nd capacitor C22.

[0164] The 26th transistor T26 includes a gate electrode connected to the light emission signal wiring, a source electrode connected to a reference wiring that transmits a reference voltage Vref, and a drain electrode connected to the 25th node N25. Thus, the 26th transistor T26 is turned on or off by the light emission signal EM, and can transmit the reference voltage Vref to the 24th node N24 which is the second electrode of the 22nd capacitor C22.

[0165] The 27th transistor T27 includes a gate electrode connected to the light emission signal wiring, a source electrode connected to the 21st node N21, and a drain electrode connected to a plurality of sub-pixels SP. Thus, the 27th transistor T27 is turned on or off by the light emission signal EM, and can transmit the second mode signal MS2 to the plurality of sub-pixels SP.

[0166] The 21st capacitor C21 includes a first electrode connected to the 21st node N21 and a second electrode connected to the 22nd node N22. The 22nd capacitor C22 includes a first electrode connected to the 23rd node N23 and a second electrode connected to the 24th node N24. On the other hand, the 21st capacitor C21 and the 22nd capacitor C22 can be connected in series.

[0167] FIG. 11 is a waveform diagram for explaining a second level shift circuit of a display device according to an embodiment of the present specification. FIG. 12a is a circuit diagram of a second level shift of a display device according to an embodiment of the present invention during a first period in a narrow viewing angle mode. FIG. 12b is a circuit diagram of a second level shift of a display device according to an embodiment of the present invention during a second period in a narrow viewing angle mode. FIG. 12c is a circuit diagram of a second level shift of a display device according to an embodiment of the present invention during a third period in a narrow viewing angle mode. Hereinafter, the voltage value corresponding to the first mode selection signal MCS1 may be referred to as "V1", which is the first voltage, and the voltage value corresponding to the second mode selection signal MCS2 may be referred to as "V2", which is the second voltage.

[0168] Referring to FIGS. 11 and 12a, in the narrow field of view mode, a low-level first scan signal SCAN1 and a low-level first mode selection signal MCS1 can be output during the first period TP1. Therefore, the 21st transistor T21, the 22nd transistor T22, and the 24th transistor T24 can be turned on by the low-level first scan signal SCAN1.

[0169] The first voltage "V1" can be applied to the 21st node N21 by the turned-on 21st transistor T21. The second voltage "V2" can be applied to the 22nd node N22 by the turned-on 22nd transistor T22. The second voltage "V2" can be applied to the 24th node N24 by the turned-on 24th transistor T24.

[0170] Next, referring to FIGS. 11 and 12b, a low-level second scan signal SCAN2 and a low-level first mode selection signal MCS1 can be output during the second period TP2. Therefore, the 23rd transistor T23 and the 25th transistor T25 can be turned on by the low-level second scan signal SCAN2.

[0171] The first voltage "V1" can be applied to the 23rd node N23 by the turned-on 23rd transistor T23. The second voltage "V2" can be applied to the 25th node N25 by the turned-on 25th transistor T25.

[0172] At this time, since the 22nd node N22 and the 23rd node N23 come to have the same voltage, the voltage of the 22nd node N22 may be "V1". Also, since the voltage of the 21st node N21 is the value obtained by adding "V1 - V2", which is the voltage stored in the 21st capacitor C21, to "V1", which is the voltage of the 22nd node N22, the voltage of the 21st node N21 may be "V1+(V1 - V2)". Also, since the voltages of the 24th node N24 and the 25th node N25 come to have the same voltage, the voltage of the 24th node N24 may be "V2". Also, the 22nd capacitor C22 can store the voltage difference between both electrodes, that is, "V1 - V2", which is the voltage difference between the 23rd node N23 and the 24th node N24.

[0173] Finally, referring to FIGS. 11 and 12c, a low-level emission signal EM and a low-level second mode selection signal MCS2 can be output in the third period TP3. Therefore, the 26th transistor T26 and the 27th transistor T27 can be turned on by the low-level emission signal EM.

[0174] The reference voltage Vref can be applied to the 25th node N25 by the turned-on 26th transistor T26. The second mode signal MS2 can be output by the turned-on 27th transistor T27.

[0175] At this time, since the 24th node N24 and the 25th node N25 come to have the same voltage, the voltage of the 24th node N24 may be "Vref". Also, since the voltage of the 23rd node N23 is the value obtained by adding "V1 - V2", which is the voltage stored in the 22nd capacitor C22, to "Vref", which is the voltage of the 24th node N24, the voltage of the 23rd node N23 may be "V1+(Vref - V2)". Also, since the voltages of the 22nd node N22 and the 23rd node N23 come to have the same voltage, the voltage of the 22nd node N22 may be "V1+(Vref - V2)". Also, since the voltage of the 21st node N21 is the value obtained by adding "V1 - V2", which is the voltage stored in the 21st capacitor C21, to "V1+(Vref - V2)", which is the voltage of the 22nd node N22, the voltage of the 21st node N21 may be "V1+(V1 - V2)+(Vref - V2)".

[0176] At this time, the second mode signal MS2 can be output through the 27th transistor T27 connected to the 21st node N21. That is, "V1+(V1 - V2)+(Vref - V2)", which is the voltage of the 21st node N21, may be the voltage value of the second mode signal MS2. Since the low-level second mode signal MS2 is a turn-on signal, at this time, "V1", which is the first voltage value, can be set to be smaller than "V2", which is the second voltage value.

[0177] On the one hand, in order to implement various viewing angles, the display device can be driven by dividing it into a wide viewing angle mode or a narrow viewing angle mode for each region. Generally, a control signal is output by a mode control unit that controls the wide viewing angle mode or the narrow viewing angle mode driving, and can be changed to a desired voltage through a level shift and then transmitted to the display panel. This is because usually, the voltage output by the mode control unit is a relatively low voltage of about 1.8V or 3.3V, and the voltages of the control signals used for the display panel are high voltages of a VGH voltage of 10.0V or more and a VGL voltage of -9.0V or less. That is, since there is a difference between the voltage output by the mode control unit and the voltage used for the display panel, a separate level shift IC is required to change the low control voltage to a high control voltage. At this time, the use of a separate IC increases the manufacturing cost, or the bezel increases to secure space for arranging the level shift IC. Also, since the output channels of one level shift IC are limited, one or more level shift ICs may be required to implement various viewing angles. In this case, there is a problem that the routing of the wiring becomes complicated due to further wiring connections.

[0178] Therefore, in the display device 100 according to an embodiment of the present specification, the level shift LS is arranged in the display area AA. That is, since it is not necessary to arrange a separate level shift IC on the flexible film COF, the manufacturing cost can be reduced. Also, since it is not necessary to secure space in the non-display area NA to arrange wiring for connecting the separate IC and the display panel PN, the area of the non-display area NA can be minimized. That is, it is possible to implement a narrow bezel.

[0179] Also, in the display device 100 according to an embodiment of the present specification, the level shifter LS can share the first scan signal wiring, the second scan signal wiring, and the emission signal wiring arranged on the display panel PN with the sub-pixel circuit SPC. Therefore, an increase in the bezel due to additional wiring layout can be minimized, and the complication of the design due to additional wiring layout can be minimized. Further, the number of wirings added to drive the level shifter LS arranged within the display area AA and the level shifter LS is minimized, and the area that must be secured within the display area AA can also be minimized as the level shifter LS is arranged in the display area AA.

[0180] Also, in the display device 100 according to an embodiment of the present specification, the level shifter LS includes a first level shifter LS1 that transmits the first mode signal MS1 and a second level shifter LS2 that transmits the second mode signal MS2. At this time, the first level shifter LS1 and the second level shifter LS2 are arranged separately for each of the plurality of divided regions a of the display area AA. Therefore, in the display device 100 according to an embodiment of the present specification, the wide viewing angle mode and the narrow viewing angle mode can be independently controlled for each of the plurality of regions a. That is, in the display device 100 according to an embodiment of the present specification, the level shifter LS is arranged for each region of the sub-pixel SP, and the viewing angle can be freely and selectively limited for each of the plurality of regions. That is, in the display device 100 according to an embodiment of the present specification, only a specific region of the screen can be freely switched to either the wide viewing angle mode or the narrow viewing angle mode selectively, and the viewing angle can be selectively limited, and the regions driven in the wide viewing angle mode and the narrow viewing angle mode can be made variable.

[0181] The display device according to various embodiments of the present specification can be described as follows.

[0182] The display device according to an embodiment of the present specification includes a display panel including a display area in which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, and a plurality of level shifters arranged in the display area and transmitting a mode signal so that the plurality of sub-pixels are driven in either a first mode or a second mode. Each of the plurality of sub-pixels includes a first light-emitting element, a first optical member that refracts light from the first light-emitting element, a second light-emitting element, and a second optical member that refracts light from the second light-emitting element and has a shape different from that of the first optical member.

[0183] According to another feature of the present specification, the plurality of level shifters include a plurality of first level shifters that transmit a first mode signal and a plurality of second level shifters that transmit a second mode signal. The display area includes a plurality of areas divided in a row or column direction, and the plurality of first level shifters and the plurality of second level shifters can be arranged one by one for each of the plurality of areas.

[0184] According to still another feature of the present specification, the plurality of level shifters can transmit a mode signal for each of the plurality of areas.

[0185] According to still another feature of the present specification, the plurality of sub-pixels include a plurality of sub-pixel circuits, and the first level shifter and the second level shifter can share signal wirings with the plurality of sub-pixel circuits.

[0186] According to still other features of the present specification, the display panel includes a first scan signal wiring, a second scan signal wiring, and a light emission signal wiring. The plurality of sub-pixel circuits can include a driving transistor, a first transistor that applies a data voltage to a capacitor, a second transistor that diode-connects the gate electrode and the drain electrode of the driving transistor, a third transistor that applies a reference voltage to the capacitor, a fourth transistor that forms a current path between the driving transistor and the first light-emitting element, a fifth transistor that applies the reference voltage to the anode electrode of the first light-emitting element, a sixth transistor that applies the reference voltage to the anode electrode of the second light-emitting element, a seventh transistor that forms a current path between the driving transistor and the second light-emitting element, and an eighth transistor that connects the driving transistor to the fourth transistor and the seventh transistor.

[0187] According to still other features of the present specification, in the first mode, the fourth transistor can be turned on and the seventh transistor can be turned off. In the second mode, the fourth transistor can be turned off and the seventh transistor can be turned on.

[0188] According to still other features of the present specification, the first level shift circuit can include a first capacitor, a second capacitor connected in series with the first capacitor, a first transistor connected to the first scan signal wiring and transmitting a second mode selection signal to the first electrode of the first capacitor, a second transistor connected to the first scan signal wiring and transmitting a first mode selection signal to the second electrode of the first capacitor, a third transistor connected to the second scan signal wiring and transmitting a second mode selection signal to the first electrode of the second capacitor, a fourth transistor connected to the first scan signal wiring and transmitting a first mode selection signal to the second electrode of the second capacitor, a fifth transistor connected to the second scan signal wiring and transmitting a first mode selection signal to the second electrode of the second capacitor, a sixth transistor connected to the light emission signal wiring and transmitting a reference voltage to the second electrode of the second capacitor, and a seventh transistor connected to the light emission signal wiring and outputting a first mode signal.

[0189] According to yet another feature of the present specification, the first level shift circuit is driven by being divided into a first period, a second period, and a third period. During the first period, the first scan signal and the second mode selection signal are turn-on signals. During the second period, the second scan signal and the second mode selection signal are turn-on signals. During the third period, the light emission signal and the first mode selection signal may be turn-on signals.

[0190] According to yet another feature of the present specification, the second level shift circuit includes a first transistor connected to the first scan signal wiring and transmitting the first mode selection signal to the first electrode of the first capacitor, a second transistor connected to the first scan signal wiring and transmitting the second mode selection signal to the second electrode of the first capacitor, a third transistor connected to the second scan signal wiring and transmitting the first mode selection signal to the first electrode of the second capacitor, a fourth transistor connected to the first scan signal wiring and transmitting the second mode selection signal to the second electrode of the second capacitor, a fifth transistor connected to the second scan signal wiring and transmitting the second mode selection signal to the second electrode of the second capacitor, a sixth transistor connected to the light emission signal wiring and transmitting the reference voltage to the second electrode of the second capacitor, and a seventh transistor connected to the light emission signal wiring and outputting the second mode signal.

[0191] According to yet another feature of the present specification, the second level shift circuit is driven by being divided into a first period, a second period, and a third period. During the first period, the first scan signal and the first mode selection signal are turn-on signals. During the second period, the second scan signal and the first mode selection signal are turn-on signals. During the third period, the light emission signal and the second mode selection signal may be turn-on signals.

[0192] According to yet another feature of the present specification, it further includes a plurality of mode control units arranged in the non-display area, and the display panel A first mode selection signal wiring that extends in a row or column direction in a plurality of regions, is connected to a mode control unit, and transmits a first mode selection signal to a plurality of sub-pixels, and a second mode selection signal wiring that extends in a row or column direction in a plurality of regions, is connected to the mode control unit, and transmits a second mode selection signal to the plurality of sub-pixels may be further included.

[0193] According to another feature of this specification, the display panel includes a driving transistor and first to eighth transistors. Each of the plurality of sub-pixels is driven by being divided into an initial period, a sampling period, a holding period, and an emission period. During the initial period, the voltage of the gate electrode of the driving transistor is initialized. During the sampling period, the threshold voltage of the driving transistor is sampled, and the anode electrodes of the first light-emitting element and the second light-emitting element are each initialized. During the holding period, the first to eighth transistors are turned off. During the emission period, a driving current is applied to each of the first light-emitting element and the second light-emitting element, and each of the first light-emitting element and the second light-emitting element can emit light.

[0194] According to another feature of this specification, in the first mode, the first light-emitting element emits light, and the light from the first light-emitting element is output with a viewing angle limited with respect to the first direction and the second direction by the first optical member. In the second mode, the second light-emitting element emits light, and the light from the second light-emitting element can be output with a viewing angle limited only with respect to the first direction by the second optical member.

[0195] As described above, with reference to the accompanying drawings, the embodiments of this specification have been described in more detail. However, this specification is not necessarily limited to such embodiments, and various modifications can be made within the scope not deviating from the technical idea of this specification. Therefore, the embodiments disclosed in this specification are not for limiting the technical idea of this specification, but for explanation, and the scope of the technical idea of this specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive.

Claims

1. A display panel including a display area in which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, and a plurality of level shifters arranged in the display area and transmitting a mode signal so that the plurality of sub-pixels are driven in either a first mode or a second mode. Each of the plurality of sub-pixels includes a first light-emitting element, a first optical member that refracts light from the first light-emitting element, a second light-emitting element, and a second optical member that refracts light from the second light-emitting element and has a shape different from that of the first optical member. A display device.

2. The plurality of level shifters include a plurality of first level shifters that transmit a first mode signal, and a plurality of second level shifters that transmit a second mode signal, the display area includes a plurality of areas divided in a row or column direction, and the plurality of first level shifters and the plurality of second level shifters are respectively arranged one by one in each of the plurality of areas. The display device according to claim 1.

3. The plurality of level shifters transmit the mode signal to each of the plurality of areas. The display device according to claim 2.

4. The plurality of sub-pixels include a plurality of sub-pixel circuits, and the first level shifter and the second level shifter share a signal wiring with the plurality of sub-pixel circuits. The display device according to claim 2.

5. The display panel includes a first scan signal wiring, a second scan signal wiring, and a light-emitting signal wiring, and the plurality of sub-pixel circuits include a driving transistor, a first transistor that applies a data voltage to a capacitor, a second transistor that diode-connects a gate electrode and a drain electrode of the driving transistor, a third transistor that applies a reference voltage to the capacitor, a fourth transistor that forms a current path between the driving transistor and the first light-emitting element, a fifth transistor that applies the reference voltage to an anode electrode of the first light-emitting element, a sixth transistor that applies the reference voltage to an anode electrode of the second light-emitting element, a seventh transistor that forms a current path between the driving transistor and the second light-emitting element, and an eighth transistor that connects the driving transistor, the fourth transistor, and the seventh transistor. The display device according to claim 4.

6. In the first mode, the fourth transistor is turned on and the seventh transistor is turned off. The display device according to claim 5, wherein in the second mode, the fourth transistor is turned off and the seventh transistor is turned on.

7. The display panel includes a first scan signal wiring, a second scan signal wiring, and a light emission signal wiring. The first level shift circuit includes a first capacitor, a second capacitor connected in series with the first capacitor, a first transistor connected to the first scan signal wiring for transmitting a second mode selection signal to a first electrode of the first capacitor, a second transistor connected to the first scan signal wiring for transmitting a first mode selection signal to a second electrode of the first capacitor, a third transistor connected to the second scan signal wiring for transmitting the second mode selection signal to a first electrode of the second capacitor, a fourth transistor connected to the first scan signal wiring for transmitting the first mode selection signal to a second electrode of the second capacitor, a fifth transistor connected to the second scan signal wiring for transmitting the first mode selection signal to a second electrode of the second capacitor, a sixth transistor connected to the light emission signal wiring for transmitting a reference voltage to a second electrode of the second capacitor, and a seventh transistor connected to the light emission signal wiring for outputting the first mode signal. The display device according to claim 4.

8. The first level shift circuit is driven by being divided into a first period, a second period, and a third period. During the first period, the first scan signal and the second mode selection signal are turn-on signals. During the second period, the second scan signal and the second mode selection signal are turn-on signals. During the third period, the light emission signal and the first mode selection signal are turn-on signals. The display device according to claim 7.

9. The display panel includes a first scan signal wiring, a second scan signal wiring, and a light emission signal wiring. The second level shift circuit includes a first transistor connected to the first scan signal wiring for transmitting a first mode selection signal to a first electrode of a first capacitor, a second transistor connected to the first scan signal wiring for transmitting a second mode selection signal to a second electrode of the first capacitor, and a third transistor connected to the second scan signal wiring for transmitting the first mode selection signal to a first electrode of a second capacitor. A fourth transistor connected to the first scan signal wiring and transmitting the second mode selection signal to the second electrode of the second capacitor; A fifth transistor connected to the second scan signal wiring and transmitting the second mode selection signal to the second electrode of the second capacitor; A sixth transistor connected to the light emission signal wiring and transmitting a reference voltage to the second electrode of the second capacitor; The display device according to claim 4, further comprising a seventh transistor connected to the light emission signal wiring and outputting the second mode signal.

10. The second level shift circuit is driven by being divided into a first period, a second period, and a third period, During the first period, the first scan signal and the first mode selection signal are turn-on signals, During the second period, the second scan signal and the first mode selection signal are turn-on signals, The display device according to claim 9, wherein during the third period, the light emission signal and the second mode selection signal are turn-on signals.

11. The display device further includes a plurality of mode control units disposed in the non-display area, The display panel, A first mode selection signal wiring that extends in a row or column direction in the plurality of regions, is connected to the mode control unit, and transmits a first mode selection signal to the plurality of sub-pixels; and The display device according to claim 2, further comprising a second mode selection signal wiring that extends in a row or column direction in the plurality of regions, is connected to the mode control unit, and transmits a second mode selection signal to the plurality of sub-pixels.

12. The display panel includes a driving transistor and first to eighth transistors, Each of the plurality of sub-pixels is driven by being divided into an initial period, a sampling period, a holding period, and an emission period, During the initial period, the voltage of the gate electrode of the driving transistor is initialized, During the sampling period, the threshold voltage of the driving transistor is sampled, The anode electrode of the first light emitting element and the anode electrode of the second light emitting element are each initialized, During the holding period, the first to eighth transistors are turned off, During the emission period, the driving current is applied to each of the first light emitting element and the second light emitting element, and each of the first light emitting element and the second light emitting element emits light. The display device according to claim 1.

13. In the first mode, the first light-emitting element emits light, and the light from the first light-emitting element is output with the viewing angle restricted with respect to the first direction and the second direction by the first optical member. The display device according to claim 1, wherein in the second mode, the second light-emitting element emits light, and the light from the second light-emitting element is output with the viewing angle restricted only with respect to the first direction by the second optical member.

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