Semiconductor device

Abstract

To provide a fine transistor.SOLUTION: A semiconductor device includes a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, and a third conductor on the third insulator, and the third insulator is in contact with the side surface of the first insulator, the semiconductor has a first region where the semiconductor and the bottom surface of the first conductor overlap, a second region where the semiconductor and the bottom surface of the second conductor overlap, and a third region where the semiconductor and the bottom surface of the third conductor overlap, and the length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first and third regions.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to, for example, transistors and semiconductor devices, and manufacturing methods thereof. . Alternatively, the present invention relates to, for example, display devices, light-emitting devices, lighting devices, power storage devices, memory devices, imaging devices, processors, and electronic devices. Alternatively, it relates to manufacturing methods of display devices, liquid crystal display devices, light-emitting devices, memory devices, imaging devices, and electronic devices. Alternatively, it relates to driving methods of semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, memory devices, and electronic devices.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

[0003] Note that in this specification etc., the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may have a semiconductor device.

Background Art

[0004] In recent years, transistors using oxide semiconductors have attracted attention. Transistors using oxide semiconductors are known to have extremely small leakage current in the non-conducting state. For example, low-power CPUs etc. that apply the characteristic of low leakage current of transistors using oxide semiconductors have been disclosed (see Patent Document 1).

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0006] One of the objects is to provide a fine transistor. One of the objectives is to provide a transistor with high frequency characteristics. Another object of the present invention is to provide a transistor having favorable electrical characteristics. Another object of the present invention is to provide a transistor having stable electrical characteristics. Another object of the present invention is to provide a transistor with a small current when off. Another object of the present invention is to provide a novel transistor. Another object of the present invention is to provide a semiconductor device having a high operating speed. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a module including the semiconductor device. It is an object of the present invention to provide an electronic device having the semiconductor device or the module. do.

[0007] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0008] One aspect of the present invention includes a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, and a third conductor on the third insulator. The third insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap. The length between an upper surface of the semiconductor and a bottom surface of the third conductor is greater than the length between the first region and the third region. 1 insulator and a second insulator on the semiconductor, a third insulator on the second insulator, and a third conductor on the third insulator. The third insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap. The length between an upper surface of the semiconductor and a bottom surface of the third conductor is greater than the length between the first region and the third region. A semiconductor device having a third insulator on the insulator, a third conductor on the third insulator, the third insulator being in contact with a side surface of the first insulator, the semiconductor having a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap, and the length between an upper surface of the semiconductor and a bottom surface of the third conductor being greater than the length between the first region and the third region. 1 insulator, the semiconductor having a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap, and the length between an upper surface of the semiconductor and a bottom surface of the third conductor being greater than the length between the first region and the third region. A semiconductor having a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap. A semiconductor device having a third region where the semiconductor and a bottom surface of the third conductor overlap, and the length between an upper surface of the semiconductor and a bottom surface of the third conductor being greater than the length between the first region and the third region. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. .

[0009] One aspect of the present invention includes a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a third conductor on the third insulator, a fourth conductor on the first insulator and the third conductor. The third insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap. The length between an upper surface of the semiconductor and a bottom surface of the third conductor is greater than the length between the first region and the third region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. 1 insulator and a second insulator on the semiconductor, a third insulator on the second insulator, a third conductor on the third insulator, a fourth conductor on the first insulator and the third conductor. The third insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap. The length between an upper surface of the semiconductor and a bottom surface of the third conductor is greater than the length between the first region and the third region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. A semiconductor device having a third insulator on the insulator, a third conductor on the third insulator, a fourth conductor on the first insulator and the third conductor, the third insulator being in contact with a side surface of the first insulator, the semiconductor having a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap, the length between an upper surface of the semiconductor and a bottom surface of the third conductor being greater than the length between the first region and the third region, and the length between the first conductor or the second conductor and the fourth conductor being greater than the length between the first region and the second region. 1 insulator, the semiconductor having a first region where the semiconductor and a bottom surface of the first conductor overlap, a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap, the length between an upper surface of the semiconductor and a bottom surface of the third conductor being greater than the length between the first region and the third region, and the length between the first conductor or the second conductor and the fourth conductor being greater than the length between the first region and the second region. A semiconductor having a second region where the semiconductor and a bottom surface of the second conductor overlap, and a third region where the semiconductor and a bottom surface of the third conductor overlap. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. A semiconductor device having a third region where the semiconductor and a bottom surface of the third conductor overlap, the length between the first conductor or the second conductor and the fourth conductor being greater than the length between the first region and the second region. A semiconductor device having a third region where the semiconductor and a bottom surface of the third conductor overlap, the length between an upper surface of the semiconductor and a bottom surface of the third conductor being greater than the length between the first region and the third region, and the length between the first conductor or the second conductor and the fourth conductor being greater than the length between the first region and the second region. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region.

[0010] One aspect of the present invention includes a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. This is a semiconductor device. A first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. A fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. This is a semiconductor device. A semiconductor device having a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. This is a semiconductor device.

[0011] One aspect of the present invention includes a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. A first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. A third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. A third conductor on the fourth insulator, and a fourth conductor on the first insulator and the third conductor. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The semiconductor device further includes a fourth conductor on the first insulator and the third conductor. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. A semiconductor device having a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with a side surface of the first insulator. The semiconductor has a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The semiconductor device further includes a fourth conductor on the first insulator and the third conductor. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. The length between the upper surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The semiconductor device further includes a fourth conductor on the first insulator and the third conductor. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region. This is a semiconductor device.

[0012] ​In one aspect of the present invention, the length between the first conductor or the second conductor and the fourth conductor is not less than 1.5 times and not more than 2 times the length between the first region and the second region.

Advantages of the Invention

[0013] A fine transistor can be provided. Or, a transistor with a small parasitic capacitance can be provided. Or, a transistor with high frequency characteristics can be provided . Or, a transistor with good electrical characteristics can be provided. Or, a transistor with stable electrical characteristics can be provided. Or, a transistor with a small off-state current can be provided. Or, a novel transistor can be provided. Also, a semiconductor device having the transistor can be provided. Or, a semiconductor device with a high operating speed can be provided. Or, a novel semiconductor device can be provided . Or, a module having the semiconductor device can be provided. Or, an electronic device having the semiconductor device or the module can be provided.

[0014] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will naturally become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily make various changes to its form and details. It is not limited, and it is easy for those skilled in the art to make various changes to its form and details. It should be understood. Also, the present invention is not construed as being limited to the description of the embodiments shown below. When explaining the configuration of the invention with reference to the drawings, the same reference numerals are used in common among different drawings. When referring to similar elements, the hatch patterns are the same, and there may be cases where no reference numerals are particularly assigned. When explaining the configuration of the invention with reference to the drawings, the same reference numerals are used in common among different drawings. When referring to similar elements, the hatch patterns are the same, and there may be cases where no reference numerals are particularly assigned. When explaining the configuration of the invention with reference to the drawings, the same reference numerals are used in common among different drawings. When referring to similar elements, the hatch patterns are the same, and there may be cases where no reference numerals are particularly assigned.

[0017] In the drawings, the size, thickness of the film (layer), or region may be exaggerated for clarity. In the drawings, the size, thickness of the film (layer), or region may be exaggerated for clarity.

[0018] In this specification, for example, when defining the shape of an object by "diameter", "particle diameter", "size", "dimension", "width", etc., it may be read as the length of one side in the smallest cube that can accommodate the object, or the equivalent circular diameter in a cross-section of the object. The equivalent circular diameter in a cross-section of the object refers to the diameter of a perfect circle having the same area as the cross-section of the object. In this specification, for example, when defining the shape of an object by "diameter", "particle diameter", "size", "dimension", "width", etc., it may be read as the length of one side in the smallest cube that can accommodate the object, or the equivalent circular diameter in a cross-section of the object. The equivalent circular diameter in a cross-section of the object refers to the diameter of a perfect circle having the same area as the cross-section of the object. In this specification, for example, when defining the shape of an object by "diameter", "particle diameter", "size", "dimension", "width", etc., it may be read as the length of one side in the smallest cube that can accommodate the object, or the equivalent circular diameter in a cross-section of the object. The equivalent circular diameter in a cross-section of the object refers to the diameter of a perfect circle having the same area as the cross-section of the object. In this specification, for example, when defining the shape of an object by "diameter", "particle diameter", "size", "dimension", "width", etc., it may be read as the length of one side in the smallest cube that can accommodate the object, or the equivalent circular diameter in a cross-section of the object. The equivalent circular diameter in a cross-section of the object refers to the diameter of a perfect circle having the same area as the cross-section of the object.

[0019] In many cases, voltage indicates the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, it is possible to rephrase voltage as potential. In many cases, voltage indicates the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, it is possible to rephrase voltage as potential. In many cases, voltage indicates the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, it is possible to rephrase voltage as potential.

[0020] The ordinal numbers such as "first" and "second" are used for convenience and do not indicate the order of steps or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" for explanation. Also, the ordinal numbers described in this specification and the ordinal numbers used to specify an aspect of the present invention may not match. The ordinal numbers such as "first" and "second" are used for convenience and do not indicate the order of steps or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" for explanation. Also, the ordinal numbers described in this specification and the ordinal numbers used to specify an aspect of the present invention may not match. The ordinal numbers such as "first" and "second" are used for convenience and do not indicate the order of steps or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" for explanation. Also, the ordinal numbers described in this specification and the ordinal numbers used to specify an aspect of the present invention may not match. The ordinal numbers such as "first" and "second" are used for convenience and do not indicate the order of steps or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" for explanation. Also, the ordinal numbers described in this specification and the ordinal numbers used to specify an aspect of the present invention may not match.

[0021] The impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration Elements with less than 0.1 atomic % are impurities. The inclusion of impurities may, for example, form the DOS (Density of State) of a semiconductor, reduce the carrier mobility, or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, oxygen deficiency may be formed by the incorporation of impurities such as hydrogen. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen. The DOS (Density of State) of the semiconductor may be formed, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, oxygen deficiency may be formed by the incorporation of impurities such as hydrogen. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, oxygen deficiency may be formed by the incorporation of impurities such as hydrogen. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, oxygen deficiency may be formed by the incorporation of impurities such as hydrogen. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen.

[0022] The channel length refers to, for example, in the top view of a transistor, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. The channel length refers to, for example, in the top view of a transistor, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. The channel length refers to, for example, in the top view of a transistor, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. The channel width refers to, for example, in the semiconductor (or when the transistor is in the on state, the part where current flows in the semiconductor)

[0023] The channel width refers to, for example, in the semiconductor (or when the transistor is in the on state, the part where current flows in the semiconductor) the region where the portion through which current flows and the gate electrode overlap each other, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. Incidentally, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. That is, in one transistor, the channel width may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. In this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

[0024] Incidentally, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. the region where the portion through which current flows and the gate electrode overlap each other, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. That is, in one transistor, the channel width may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. In this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Incidentally, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. the region where the portion through which current flows and the gate electrode overlap each other, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. That is, in one transistor, the channel width may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0025] Incidentally, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. the region where the portion through which current flows and the gate electrode overlap each other, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. That is, in one transistor, the channel width may not be determined to be one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0026] Therefore, in this specification, in the top view of the transistor, the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap is defined as the apparent channel width, which may be referred to as the "surrounded channel width (SCW)". In this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Alternatively, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image or the like and analyzing the image. In addition, when calculating the field-effect mobility of the transistor or the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case where the effective channel width is used for calculation. In this specification, when it is described that A has a shape protruding more than B, it may indicate that in the top view or cross-sectional view, at least one end of A is outside at least one end of B. Therefore, when it is described that A has a shape protruding more than B, for example, in the top view, it can be read as having a shape where one end of A is outside one end of B. In this specification, "parallel" means that the angle between two straight lines is -10° or more and 10° or less.

[0027] When calculating the field-effect mobility of the transistor or the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case where the effective channel width is used for calculation.

[0028] In this specification, when it is described that A has a shape protruding more than B, it may indicate that in the top view or cross-sectional view, at least one end of A is outside at least one end of B. Therefore, when it is described that A has a shape protruding more than B, for example, in the top view, it can be read as having a shape where one end of A is outside one end of B.

[0029] In this specification, "parallel" means that the angle between two straight lines is -10° or more and 10° or less.​​​​​​ refers to the configured state. Therefore, it also includes the case where it is -5° or more and 5° or less. Also, "Vertical" refers to the state where two straight lines are arranged at an angle of 80° or more and 100° or less . Therefore, it also includes the case where it is 85° or more and 95° or less.

[0030] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system .

[0031] In addition, in the specification, when it is described as a semiconductor, it can be read as an oxide semiconductor . As the semiconductor, group 14 semiconductors such as silicon and germanium, silicon carbide, germa nium carbide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide, etc compound semiconductors, carbon nanotubes, graphene, and organic semiconductors can be used .

[0032] In addition, in this specification etc., a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen in its composition, and a silicon nitride oxide film refers to a film having a higher nitrogen content than oxygen in its composition.

[0033] Also, in this specification etc., in the figure or text described in one embodiment, when at least one specific example is described, deriving the upper concept of that specific example is , which can be easily understood by those skilled in the art. Therefore, in the figure or text described in one embodiment, when at least one specific example is described, the upper concept of that specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention . And it can be said that one aspect of that invention is clear.

[0034] In addition, in this specification and the like, at least the content described in the figures (even a part in the figures) is , which is disclosed as one aspect of the invention and can constitute one aspect of the invention . Therefore, for a certain content, if it is described in the figure, even if it is not described using text, that content is disclosed as one aspect of the invention and can constitute one aspect of the invention. Similarly, for a figure obtained by extracting a part of the figure, it is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And it can be said that one aspect of the invention is clear.

[0035] In addition, for content not defined in the text or drawings in the specification, one aspect of the invention that defines excluding that content can be constituted. Or, for a certain value, when a numerical range indicated by an upper limit value and a lower limit value, etc. is described, by arbitrarily narrowing that range , or by excluding a point within that range, one aspect of the invention excluding a part of that range can be defined. By these, for example, it can be defined that the prior art does not fall within the technical scope of one aspect of the present invention.

[0036] (Embodiment 1) <Transistor Structure 1> Hereinafter, the structure of a transistor included in a semiconductor device according to one aspect of the present invention will be described.

[0037] Figures 1(A), (B), and (C) are a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention. Figure 1(A) is a top view. Figure 1(B) is a dashed line A1 shown in Figure 1(A) -A2 corresponding cross-sectional view showing the cross-sectional shape in the channel length direction. FIG. 1(C) is a cross-sectional view corresponding to the dashed-dotted line A3 - A4 shown in FIG. 1 (A), showing the cross-sectional shape in the channel width direction . Note that in the top view of FIG. 1(A), some elements are omitted for clarity of the figure .

[0038] The transistor shown in FIG. 1 includes a conductor 413 and an insulator 401 on a substrate 400, an insulator 402 on the conductor 413 and the insulator 401, an insulator 406a on the insulator 402, a semiconductor 406b on the insulator 406a, conductors 416a and 416b having a region in contact with the upper surface of the semiconductor 406b, the upper surface of the insulator 402, the upper surface of the conductor 416a, and the upper surface of the conductor 416b, an insulator 410 in contact with the upper surfaces and having an opening, the side surface of the conductor 416a, the upper surface and the side surface of the semiconductor 406b, an insulator 406c, an insulator 412 in contact with the upper surface of the insulator 406c and the side surface of the opening of the insulator 410, and conductors 404a and 404b disposed on the semiconductor 406b via the insulator 412 and the insulator 406c . Note that the conductor 404b faces the side surface of the opening of the insulator 410 via the conductor 404a and the insulator 412. Also, on the transistor, there are a conductor 420 on the conductors 404a and 404b, and an insulator 408 on the insulator 412 and the conductor 420 . Also, as shown in FIGS. 56(A), 56(B), and 56(C), the conductor 413 and the insulator 401 are not essential components, and a configuration without the conductor 413 and the insulator 401 may be adopted . The insulator 406c has at least one element other than oxygen in the semiconductor 406b . . Also, as shown in FIGS. 56(A), 56(B), and 56(C), the conductor 413 and the insulator 401 are not essential components, and a configuration without the conductor 413 and the insulator 401 may be adopted .

[0039] The insulator 406c has at least one element other than oxygen in the semiconductor 406b This is preferable. By doing so, at the interface between the semiconductor 406b and the insulator 406c, generation of defects can be suppressed. Also, the crystallinity of the insulator 406c can be improved. .

[0040] The semiconductor 406b and the insulator 406c preferably have CAAC-OS described later. Also, the insulator 406a preferably has CAAC-OS.

[0041] In this transistor, the conductors 404a and 404b function as a first gate electrode. Also, at least one of the conductors 404a and 404b is preferably a conductor that is less permeable to oxygen. For example, by forming a conductor having a property of being less permeable to oxygen as the underlying conductor 404a, a decrease in conductivity due to oxidation of the conductor 404b can be prevented. Also, the insulator 412 functions as a first gate insulator.

[0042] Also, the conductor 413 functions as a second gate electrode. Also, the conductor 413 can have a laminated structure including a conductor having a function of being less permeable to oxygen. By making it a laminated structure including a conductor having a property of being less permeable to oxygen, a decrease in conductivity due to oxidation of the conductor 413 can be prevented. The insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by the potential applied to the conductor 413. Also, by electrically connecting the first gate electrode and the second gate electrode, the current (on-current) during conduction can be increased. Note that the functions of the first gate electrode and the second gate electrode may be interchanged.

[0043] In addition, the conductors 416a and 416b function as a source electrode or a drain electrode. Note that the conductivity of the conductor can be measured using the two-terminal method or the like.

[0044] The resistance of the semiconductor 406b can be controlled by the potential applied to the conductor 404. That is, the conduction / non-conduction between the conductor 416a and the conductor 416b can be controlled by the potential applied to the conductor 404.

[0045] As shown in FIG. 1(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed throughout the semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. In addition, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be decreased.

[0046] In the transistor according to the present embodiment, the region functioning as the gate electrode is self-aligned so as to fill the opening formed by the insulator 410 or the like. Therefore, it can also be called a TGSA s-channel FET (Trench Gate Self-Align s-channel FET).

[0047] ​​​​​​ Here, in FIG. 1(B), let the length between the upper surface of the semiconductor 406b in the region overlapping the conductor 404 and the bottom surface of the conductor 404 be t1. Also, in FIG. 1(B), in the semiconductor 406b, let the length between the region overlapping the bottom surface of the conductor 416a and the region overlapping the bottom surface of the conductor 404 be L1. Or, let the length between the region overlapping the bottom surface of the conductor 416b and the region overlapping the bottom surface of the conductor 404 be L1. In the transistor, in the semiconductor 406b, a region of length L1 is formed between the region where a channel is formed (the region where the conductor 404 and the semiconductor 406b overlap) and the source region or drain region (the region where the conductor 416a or the conductor 416b and the semiconductor 406b overlap). By having this region, the off-current of the transistor can be reduced. On the other hand, if this region is too large, the on-current of the transistor will be reduced. Also, by covering the region where the channel of the semiconductor 406b is formed with the insulator 406c, it is possible to block elements other than oxygen (such as hydrogen, silicon, etc.) that make up the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator 406c may be formed at least on the semiconductor 406b. So, by not providing the insulator 406c on the side surface of the conductor 404 via the insulator 412, or by making the region where the insulator 406c covers the side surface of the conductor 404 via the insulator 412 thinner than the region where the insulator 406c overlaps the bottom surface of the conductor 404 via the insulator 412, L1 can be made smaller. Therefore, t1 is, L (The description seems to be incomplete here. There should be more context or a full sentence following this for it to make complete sense.)

[0048] In the transistor, in the semiconductor 406b, the region where a channel is formed (the region where the conductor 40 4 and the semiconductor 406b overlap) and the source region or drain region (the region where the conductor 416 a or the conductor 416b and the semiconductor 406b overlap), a region of L1 is formed. By having this region, the off-current of the transistor can be reduced while if this region is too large, the on-current of the transistor will be reduced. Also, by covering the region where the channel of the semiconductor 406b is formed with the insulator 406c, it is possible to block elements other than oxygen (such as hydrogen, silicon, etc.) that make up the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator 406c may be formed at least on the semiconductor 406b.

[0049] Also, by covering the region where the channel of the semiconductor 406b is formed with the insulator 406c, it is possible to block elements other than oxygen (such as hydrogen, silicon, etc.) that make up the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator 406c may be formed at least on the semiconductor 406b. In the transistor, in the semiconductor 406b, the region where a channel is formed (the region where the conductor 404 and the semiconductor 406b overlap) and the source region or drain region (the region where the conductor 416a or the conductor 416b and the semiconductor 406b overlap), a region of L1 is formed. By having this region, the off-current of the transistor can be reduced while if this region is too large, the on-current of the transistor will be reduced. Also, by covering the region where the channel of the semiconductor 406b is formed with the insulator 406c, it is possible to block elements other than oxygen (such as hydrogen, silicon, etc.) that make up the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator 406c may be formed at least on the semiconductor 406b.

[0050] So, by not providing the insulator 406c on the side surface of the conductor 404 via the insulator 412, or by making the region where the insulator 406c covers the side surface of the conductor 404 via the insulator 412 thinner than the region where the insulator 406c overlaps the bottom surface of the conductor 404 via the insulator 412, L1 can be made smaller. Therefore, t1 is, L Here, in FIG. 1(B), let the length between the upper surface of the semiconductor 406b in the region overlapping the conductor 404 and the bottom surface of the conductor 404 be t1. Also, in FIG. 1(B), in the semiconductor 406b, let the length between the region overlapping the bottom surface of the conductor 416a and the region overlapping the bottom surface of the conductor 404 be L1. Or, let the length between the region overlapping the bottom surface of the conductor 416b and the region overlapping the bottom surface of the conductor 404 be L1. In the transistor, in the semiconductor 406b, a region of length L1 is formed between the region where a channel is formed (the region where the conductor 404 and the semiconductor 406b overlap) and the source region or drain region (the region where the conductor 416a or the conductor 416b and the semiconductor 406b overlap). By having this region, the off-current of the transistor can be reduced. On the other hand, if this region is too large, the on-current of the transistor will be reduced. Also, by covering the region where the channel of the semiconductor 406b is formed with the insulator 406c, it is possible to block elements other than oxygen (such as hydrogen, silicon, etc.) that make up the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator 406c may be formed at least on the semiconductor 406b. It is larger than 1, and L1 / t1 is less than 1.

[0051] Also, in FIG. 1(B), let the length between the conductor 416a or the conductor 416b and the conductor 420 be t2. Further, in FIG. 1(B), let the length between the conductor 416a and the conductor 416b be L2. Also, in FIG. 1(B), let the length between the conductor 416a or the conductor 416b and the conductor 420 be t2. Further, in FIG. 1(B), let the length between the conductor 416a and the conductor 416b be L2. Also, in FIG. 1(B), let the length between the conductor 416a and the conductor 416b be L2.

[0052] As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance in the vicinity of the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time required for charging the parasitic capacitance is necessary, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed for charging the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, t2 is preferably long enough that the parasitic capacitance can be ignored compared to the gate capacitance.

[0053] Also, as the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be a sufficient length, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 may be larger than L2, and preferably t2 / L2 is 1.5 or more and 2 or less. Also, as the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be a sufficient length, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 may be larger than L2, and preferably t2 / L2 is 1.5 or more and 2 or less. Also, as the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be a sufficient length, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 may be larger than L2, and preferably t2 / L2 is 1.5 or more and 2 or less. Also, as the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be a sufficient length, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 may be larger than L2, and preferably t2 / L2 is 1.5 or more and 2 or less. Also, as the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be a sufficient length, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 may be larger than L2, and preferably t2 / L2 is 1.5 or more and 2 or less.

[0054] As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia There are near substrates (such as yttria-stabilized zirconia substrates), resin substrates, etc. Also, as the semiconductor substrate, for example, single semiconductor substrates such as silicon and germanium, or silicon carbide , silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide compound semiconductor substrates made of, etc. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as SOI (Silicon On Insulator) substrates . As the conductor substrate, there are graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. . Or, there are substrates having a metal nitride, substrates having a metal oxide, etc. Further, there are substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, substrates in which a semiconductor or insulator is provided on a conductor substrate, etc. . Or, those with elements provided on these substrates may be used. As the elements provided on the substrate , there are capacitor elements, resistor elements, switch elements, light-emitting elements, memory elements, etc.

[0055] Also, as the substrate 400, a flexible substrate may be used. Note that as a method of providing a transistor on the flexible substrate, there is also a method in which a transistor is fabricated on a non-flexible substrate and then the transistor is peeled off and transferred to the substrate 400 which is a flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. Note that as the substrate 400 , a sheet, film, or foil knitted with fibers may be used. Also, the substrate 400 may have stretchability. Also, when the bending and pulling of the substrate 400 are stopped, it may have the property of returning to the original shape. Or, it may have the property of not returning to the original shape. Substrate 4 00 has a region with a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. When the substrate 400 is made thinner, the semiconductor device having transistors can be lightened. Also, by making the substrate 4 00 thinner, when using glass or the like, it may have stretchability, or when bending or tension is stopped, it may have the property of returning to its original shape. Therefore, impacts and the like applied to the semiconductor device on the substrate 400 due to dropping and the like can be mitigated. That is, a robust semiconductor device can be provided.

[0056] As the flexible substrate 400, for example, metal, alloy, resin, glass, or their fibers can be used. The flexible substrate 400 preferably has less deformation due to the environment as the linear expansion rate is lower. As the flexible substrate 400, for example, a material with a linear expansion rate of 1×10 / K or less, 5×10 -3 / K or less, or 1×1 -5 / K or less can be used. Examples of the resin include polyester, poly olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, -5 acrylic, etc. In particular, aramid is suitable as the flexible substrate 400 because of its low linear expansion rate.

[0057] In addition, by surrounding the transistor with an insulator having a function of blocking impurities such as hydrogen and oxygen and oxygen, the electrical characteristics of the transistor can be stabilized. For example, as the insulator 408, an insulator having a function of blocking impurities such as hydrogen and oxygen can be used. ​​​​​​

[0058] As an insulator having a function of blocking impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium , hafnium or tantalum may be used as a single layer or a laminate.

[0059] Also, for example, as the insulator 408, aluminum oxide, magnesium oxide, oxynitride silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, di zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. Note that the insulator 408 preferably has aluminum oxide. For example, when the insulator 408 is formed using a plasma containing oxygen, oxygen can be added to the insulator 410 that becomes the underlying layer of the insulator 408. Or oxygen can be added to the side surface of the insulator 412. The added oxygen becomes excess oxygen in the insulator 410 or the insulator 412. Since the insulator 408 has aluminum oxide, it is possible to suppress the mixing of impurities such as hydrogen into the semiconductor 406b. Also, for example, since the insulator 408 has aluminum oxide, it is possible to reduce the outward diffusion of the excess oxygen added to the insulator 410 and the insulator 412 described above.

[0060] As the insulator 402, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, a luminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , an insulator containing zirconium, lanthanum, neodymium, hafnium or tantalum may be used as a single layer or in a laminated form. For example, the insulator 402 preferably has silicon oxide or silicon oxynitride.

[0061] Note that the insulator 410 preferably has an insulator with a low relative permittivity. For example, the insulator 410 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine added silicon oxide, carbon added silicon oxide, carbon and nitrogen added silicon oxide, porous silicon oxide or resin. Or, the insulator 410 preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine added silicon oxide, carbon added silicon oxide, carbon and nitrogen added silicon oxide or porous silicon oxide and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining with resin, a thermally stable and low relative permittivity laminated structure can be obtained. Examples of the resin include, for example, polyester, polyolefin, polyamide (nylon, aramid, etc.) , polyimide, polycarbonate or acrylic.

[0062] As the insulator 412, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, al uminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum may be used as a single layer or in a laminated form. For example, the insulator 412 preferably has silicon oxide or silicon oxynitride.

[0063] Note that the insulator 412 preferably has an insulator with a high relative permittivity. For example, the insulator 412 preferably has gallium oxide, hafnium oxide, an oxide having aluminum and hafnium, a nitride oxide having aluminum and hafnium, an oxide having silicon and hafnium, or a nitride oxide having silicon and hafnium. Alternatively, the insulator 412 preferably has a laminated structure of silicon oxide or silicon oxynitride and an insulator with a high relative permittivity. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a high relative permittivity can be obtained by combining them with an insulator having a high relative permittivity. For example, by having aluminum oxide, gallium oxide, or hafnium oxide on the insulator 406c side, it is possible to suppress silicon contained in the silicon oxide or silicon oxynitride from mixing into the semiconductor 406b. Further, for example, by having silicon oxide or silicon oxynitride on the insulator 406c side, a trap center may be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. The trap center may be able to change the threshold voltage of the transistor in the positive direction by capturing electrons. As the conductors 416a and 416b, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver are used. or the like can be used.

[0064] , a conductor containing one or more of indium, tin, tantalum, and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may also be used. For the conductors 404, 413, and 420, for example, conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may also be used. It is preferable to use an oxide semiconductor for the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used in some cases. For the insulators 406a and 406c, it is preferable to use an oxide composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 406b. However, silicon .

[0065] For the conductors 404, 413, and 420, for example, conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may also be used. For the conductors 404, 413, and 420, for example, conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may also be used. It is preferable to use an oxide semiconductor for the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used in some cases. For the insulators 406a and 406c, it is preferable to use an oxide composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 406b. However, silicon For the conductors 404, 413, and 420, for example, conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or in a laminated form. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may also be used. It is preferable to use an oxide semiconductor for the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used in some cases. For the insulators 406a and 406c, it is preferable to use an oxide composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 406b. However, silicon .

[0066] It is preferable to use an oxide semiconductor for the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used in some cases. For the insulators 406a and 406c, it is preferable to use an oxide composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 406b. However, silicon It is preferable to use an oxide semiconductor for the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used in some cases. .

[0067] For the insulators 406a and 406c, it is preferable to use an oxide composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 406b. However, silicon For the insulators 406a and 406c, it is preferable to use an oxide composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 406b. However, silicon Including strained silicon), germanium, silicon germanium, silicon carbide, gallium Arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor, etc. May be used.

[0068] The semiconductor 406b is, for example, an oxide semiconductor. The semiconductor 406b, for example, indium When containing, the carrier mobility (electron mobility) becomes high. Further, the semiconductor 406b preferably contains an element M. The element M is preferably aluminum, gallium, yttrium or Tin or the like. Elements applicable to other elements M include boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , Neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, As the element M, there may be cases where a plurality of the foregoing elements are combined. The element M is, for example , An element having a high binding energy with oxygen. For example, an element having a binding energy with oxygen higher than that of indium Umm. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of an oxide semiconductor . Further, the semiconductor 406b preferably contains zinc . The oxide semiconductor may be more likely to crystallize when containing zinc.

[0069] However, the semiconductor 406b is not limited to an oxide semiconductor. The semiconductor 406b is, for example, Oxide semiconductors such as zinc tin oxide and gallium tin oxide, which do not contain indium and contain zinc, An oxide semiconductor containing gallium, an oxide semiconductor containing tin, etc. may be used.

[0070] The semiconductor 406b uses, for example, an oxide having a large energy gap. The semiconductor 406 The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

[0071] In addition, the insulator 406a and the insulator 406c are oxides composed of one or more elements other than oxygen that constitute the semiconductor 406b. Since the insulator 406a and the insulator 406c are composed of one or more elements other than oxygen that constitute the semiconductor 406b, defect levels are less likely to be formed at the interface between the insulator 406a and the semiconductor 406b and at the interface between the semiconductor 406b and the insulator 406c. The semiconductor 406b is composed of one or more elements other than oxygen that constitute the semiconductor 406b, or oxides composed of two or more elements. Therefore, since the insulator 406a and the insulator 406c are composed of one or more elements other than oxygen that constitute the semiconductor 406b, defect levels are less likely to be formed at the interface between the insulator 406a and the semiconductor 406b and at the interface between the semiconductor 406b and the insulator 406c. At the interface between the insulator 406a and the semiconductor 406b and at the interface between the semiconductor 406b and the insulator 406c, defect levels are less likely to be formed. At the interface between the insulator 406a and the semiconductor 406b and at the interface between the semiconductor 406b and the insulator 406c, defect levels are less likely to be formed.

[0072] The semiconductor 406b uses an oxide having a larger electron affinity than the insulator 406a and the insulator 406c. For example, as the semiconductor 406b, an oxide having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than the insulator 406a and the insulator 406c is used. The electron affinity is the energy difference between the vacuum level and the lower end of the conduction band. For example, as the semiconductor 406b, an oxide having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than the insulator 406a and the insulator 406c is used. eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than the insulator 406a and the insulator 406c is used. The electron affinity is the energy difference between the vacuum level and the lower end of the conduction band. The electron affinity is the energy difference between the vacuum level and the lower end of the conduction band.

[0073] Thus, in the transistor in which the insulator 406a and the insulator 406c are arranged above and below the semiconductor 406b, when a gate voltage is applied, a channel is formed in the semiconductor 406b having a larger electron affinity among the insulator 406a, the semiconductor 406b, and the insulator 406c. Thus, a so-called buried channel structure can be formed. Here, between the insulator 406a and the semiconductor 406b, there may be a mixed region between the insulator 406a and the semiconductor 406b. Also, between the semiconductor 406b and the insulator 406c, a mixed region between the semiconductor 406b and the insulator 406c may be present. A so-called buried channel structure can be formed in this way.

[0074] Here, between the insulator 406a and the semiconductor 406b, there may be a mixed region between the insulator 406a and the semiconductor 406b. Also, between the semiconductor 406b and the insulator 406c, a mixed region between the semiconductor 406b and the insulator 406c may be present. There may be a mixed region of the semiconductor 406b and the insulator 406c. In the mixed region, the defect level density is low. Therefore, in the stack of the insulator 406a, the semiconductor 406b, and the insulator 406c, the energy changes continuously near each interface (also referred to as a continuous junction). Note that it may not be possible to clearly distinguish the interfaces of the insulator 406a, the semiconductor 406b, and the insulator 406c. At this time, electrons mainly move in the semiconductor 406b rather than in the insulators 406a and 406c. The on-current of the transistor can be increased as the factors inhibiting the movement of electrons are reduced. The movement of electrons is inhibited, for example, even when the physical unevenness of the channel formation region is large. To increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper surface or the lower surface (the surface to be formed, here the upper surface of the insulator 406a) of the semiconductor 406b is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Also, the average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Further, the maximum height difference (also referred to as P-V) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and P-V are measured by a surface profilometer.

[0075]

[0076]

[0077] ​​​​​​​​​​​​​​​Using a scanning probe microscope system SPA-500 manufactured by Nanotechnology Co., Ltd., etc. Measurement can be performed.

[0078] The above three-layer structure is an example. For example, on or under the insulator 406a, or on or under the insulator 4 06c, a laminated structure having one or more of the insulators exemplified as the insulator 406a and the insulator 406c may be used. It does not matter.

[0079] For details of the oxide semiconductor that can be used for a semiconductor, it will be described in detail in other embodiments. It will be described in detail.

[0080] <Fabrication method of transistor 1> Hereinafter, the method for manufacturing the transistor of FIG. 1 according to the present invention will be described with reference to FIGS. 7 to 9. .

[0081] First, a substrate 400 is prepared.

[0082] Next, as shown in FIGS. 7(A) and 7(B), an insulator that becomes the insulator 401 is formed on the substrate 400, an opening is formed in the insulator 401, and a conductor that becomes the conductor 413 is formed on the insulator 401. The film formation of the conductor that becomes the conductor 413 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In addition, the conductor 413 may have a multilayer structure including a conductor having a property of being difficult to transmit oxygen (or having high oxidation resistance). Next, it is preferable to embed the conductor 413 in the opening of the insulator 401 using chemical mechanical polishing (CMP) or the like. As another method for forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. It is also good. ing: CMP) or the like.

[0083] In the photolithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next by performing an etching process through the resist mask, conductors, semiconductors, or insulators etc. can be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed may be used. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, a mask is not required. Note that for removing the resist mask, dry etching treatment such as ashing, or wet etching treatment, or wet etching treatment may be performed after dry etching treatment, or dry etching treatment may be performed after wet etching treatment.

[0084] As a dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high-frequency power source is applied to one of the parallel plate electrodes. Or it may have a configuration in which a plurality of different high-frequency power sources are applied to one of the parallel plate electrodes. Or it may have a configuration in which high-frequency power sources of the same frequency are applied to each of the parallel plate electrodes. Or it may have a configuration in which high-frequency power sources of the same frequency are applied to each of the parallel plate electrodes. ​​Alternatively, a high-frequency power source having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device is, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0085] Next, a high-density plasma treatment may be performed as shown by the arrows in FIG. 7(A) or (B). The high-density plasma treatment is preferably carried out in an oxygen atmosphere or a nitrogen atmosphere. is a gas atmosphere containing oxygen atoms, such as oxygen, ozone or nitrogen oxides (nitric oxide, Nitrogen dioxide, nitrous oxide, dinitrogen trioxide, dinitrogen tetroxide, dinitrogen pentoxide, etc.) atmosphere In addition, in an oxygen atmosphere, the inert gases such as nitrogen or rare gases (helium, argon, etc.) The active gas may be included. By performing high density plasma processing in such an oxygen atmosphere, Therefore, for example, carbon, hydrogen, etc. can be desorbed. By using plasma treatment, organic compounds such as hydrocarbons can be easily desorbed from the material to be treated. stomach.

[0086] The high density plasma treatment in a nitrogen atmosphere may be carried out in an atmosphere containing nitrogen and a rare gas, or in an atmosphere containing nitrogen, hydrogen and a rare gas, or in an atmosphere containing ammonia and a rare gas. The high-density plasma treatment can be performed by using the above-mentioned high-density plasma. The area to be nitrided can be formed very thinly on the surface side of the workpiece. Moreover, the nitrided region can suppress the diffusion of impurities.

[0087] In addition, the high-density plasma treatment may be performed in a nitrogen atmosphere after being performed in an oxygen atmosphere, and it may be processed in an oxygen atmosphere after being processed in a nitrogen atmosphere. Also, annealing treatment may be performed before and after each high-density plasma treatment. In order to increase the density of the plasma, it may be preferable to flow a sufficient amount of gas. If the amount of gas is insufficient, the inactivation rate may be higher than the generation rate of radicals. For example, it may be preferable to flow the gas at 100 sccm or more, 300 sccm or more, or 800 sccm or more.

[0088] The high-density plasma treatment may use, for example, microwaves generated using a high-frequency generator having a frequency of 0.3 GHz or more and 3.0 GHz or less, 0.7 GHz or more and 1.1 GHz or less, or 2.2 GHz or more and 2.8 GHz or less (typically 2.45 GHz). Also, the processing pressure is 10 Pa or more and 5000 Pa or less, preferably 200 Pa or more and 1500 Pa or less, more preferably 300 Pa or more and 1000 Pa or less, the substrate temperature is 100°C or more and 600°C or less (typically 400°C), and it can be performed using a mixed gas of oxygen and argon.

[0089] The high-density plasma is generated, for example, by using microwaves of 2.45 GHz, and it is preferably performed with an electron density of 1×10 11 / cm 3 or more and 1×10 13 / cm 3 or less, an electron temperature of 2 eV or less, or an ion energy of 5 eV or less. Such high-density plasma treatment has a small kinetic energy of radicals and less damage by plasma compared to conventional plasma treatment. Therefore, a film with few defects can be formed. The microwave ​​​​​​​​​​​​The distance from the generating antenna to the object to be processed is 5 mm or more and 120 mm or less, preferably 20 mm or more and 60 mm or less.

[0090] Alternatively, it may have a plasma power source for applying an RF (Radio Frequency) bias to the substrate side. The frequency of the RF bias may be, for example, 13.56 MHz or 27.1 2 MHz or the like. By using high-density plasma, higher-density oxygen ions can be generated, and by applying an RF bias to the substrate side, the oxygen ions generated by the high-density plasma can be efficiently guided to the object to be processed. Therefore, it is preferable to perform high-density plasma treatment while applying a substrate bias.

[0091] Also, after the high-density plasma treatment, annealing treatment may be continuously performed without exposure to the atmosphere. Also, the high-density plasma treatment may be continuously performed after the annealing treatment without exposure to the atmosphere. By continuously performing the high-density plasma treatment and the annealing treatment, it is possible to suppress the mixing of impurities during the treatment. Also, by performing annealing treatment after performing high-density plasma treatment in an oxygen atmosphere, unnecessary oxygen that was not used for compensating oxygen deficiency among the oxygen added to the object to be processed can be desorbed. Also, the above annealing treatment may be performed, for example, by lamp annealing or the like.

[0092] Also, the treatment time of the high-density plasma treatment is preferably 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less , 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0093] Also, the annealing treatment is 250°C or more and 800°C or less, 300°C or more and 700°C or less, or 4 The treatment time at 0°C or higher and 600°C or lower is preferably 30 seconds or longer and 120 minutes or shorter, 1 minute or longer and 90 minutes or shorter, 2 minutes or longer and 30 minutes or shorter, or 3 minutes or longer and 15 minutes or shorter.

[0094] Next, an insulator 402 is formed. The formation of the insulator 402 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, or a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an atomic layer deposition (ALD: Atomic Layer Deposition) method, etc. It can be done.

[0095] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, etc. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the source gas used. (MOCVD: Metal Organic CVD) method depending on the source gas used. (MOCVD: Metal Organic CVD) method depending on the source gas used. The plasma CVD method can obtain a high-quality film at a relatively low temperature. Also, the thermal CVD method is a film formation method capable of reducing plasma damage to the object to be processed because it does not use plasma.

[0096] For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. Yes. On the other hand, in the case of the thermal CVD method without using plasma, since damage caused by exposure to plasma as described above does not occur, the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since it is not exposed to plasma during film formation, a film with few defects is easily obtained.

[0097] Also, the ALD method is a film formation method capable of reducing plasma damage to the object to be processed. Also, in the ALD method, since plasma damage does not occur during film formation, a film with few defects is obtained.

[0098] The CVD method and the ALD method are different from film formation methods in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is hardly affected by the shape of the object to be processed and is a film formation method having good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a slow film formation rate, it may be preferably used in combination with other film formation methods such as the CVD method with a high film formation rate.

[0099] The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, by changing the flow rate ratio of the source gases while forming a film, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, a plurality of film formation chambers are used. ​​​​​Compared with the case of forming a film, the time required for film formation can be shortened by the time required for transfer and pressure adjustment. Therefore, the productivity of the semiconductor device may be improved.

[0100] Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be desorbed from the object to be treated.

[0101] Also, a process of adding oxygen to the insulator 402 may be performed. Examples of the process of adding oxygen include, for example, ion implantation method, plasma treatment method, etc. Note that the oxygen added to the insulator 402 becomes excess oxygen.

[0102] Next, as shown in FIGS. 7(C) and 7(D), an insulator that becomes the insulator 406a, a semiconductor that becomes the semiconductor 406b, and a resist mask 430 are formed.

[0103] First, an insulator that becomes the insulator 406a is formed on the insulator 402. The formation of the insulator that becomes the insulator 406a can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. In particular, it is preferable to form a film using a facing target type sputtering apparatus. In this specification, etc., the film formation method using a facing target type sputtering apparatus may also be called VDSP (vapor deposition SP).

[0104] By forming an insulator using a facing target type sputtering apparatus, plasma damage during film formation can be reduced. Therefore, oxygen deficiency in the film can be reduced. ​In addition, by using a facing target type sputtering apparatus, film formation in a high vacuum becomes possible. Thereby, the impurity concentration (for example, hydrogen, rare gas (such as argon ), water, etc.) in the formed insulator can be reduced.

[0105] Also, a sputtering apparatus having an inductively coupled antenna conductor plate may be used. Thereby a high deposition rate, a large area, and a highly uniform film can be formed.

[0106] Film formation is preferably performed using a gas containing oxygen, a rare gas, a gas containing nitrogen, etc. As the gas containing nitrogen, for example, nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. may be used.

[0107] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated.

[0108] Also, a process of adding oxygen to the insulator that becomes the insulator 406a may be performed. As the process of adding oxygen, there are an ion implantation method, a plasma treatment method, etc. Note that the oxygen added to the insulator that becomes the insulator 406a becomes excess oxygen.

[0109] Next, a semiconductor that becomes the semiconductor 406b is formed on the insulator that becomes the insulator 406a. The formation of the semiconductor can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In particular, it is preferred to form a film using a facing target type sputtering apparatus.

[0110] By depositing semiconductor films using a facing target sputtering device, This reduces plasma damage in the film, thereby reducing oxygen vacancies in the film. In addition, by using a facing target sputtering device, film formation in a high vacuum is possible. This allows the concentration of impurities (e.g. hydrogen, rare gas (argon, etc.)) in the deposited semiconductor to be ), water, etc.) can be reduced.

[0111] Also, a sputtering device having an inductively coupled antenna conductor plate may be used. This allows for a high film formation speed and the formation of a film with a large area and high uniformity.

[0112] The film is preferably formed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0113] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 450° C. or higher and 600° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. This can improve the crystallinity of a semiconductor and remove impurities such as hydrogen and water. Alternatively, the first heat treatment may be performed using a plasma treatment containing oxygen under reduced pressure. The plasma treatment including is preferably carried out using a device having a power source for generating high-density plasma using, for example, microwaves. Or, it may have a plasma power source for applying an RF (Radio Frequency) voltage to the substrate side. By using high-density plasma, oxygen radicals with a higher density can be generated, and by applying an RF voltage to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the semiconductor 406b. Or, after performing plasma treatment including an inert gas using this device, plasma treatment including oxygen may be performed to supplement the oxygen desorbed. Next, as shown in FIGS. 7(E) and 7(F), an insulator that becomes the insulator 406a and a semiconductor that becomes the semiconductor 406b are processed by a photolithography method using a resist mask 430 or the like to form a multilayer film having the insulator 406a and the semiconductor 406b. When forming the multilayer film, the insulator 402 may also be etched and some regions may become thinner. That is, the insulator 402 may have a shape having a convex portion in the region in contact with the multilayer film. Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated. Next, as shown in FIGS. 7(G) and 7(H), a conductor 416 and an insulator that becomes the insulator 410 are formed. First, the conductor 416 is formed. The film formation of the conductor 416 is carried out by a sputtering method, a CVD method,

[0114]

[0115]

[0116]

[0117] It can be carried out using the MBE method, PLD method, ALD method, etc.

[0118] Note that the conductor 416 is shaped to cover the multilayer film. When forming the conductor on the multilayer film, damage is caused to the side surface of the insulator 406a, the upper surface of the semiconductor 406b, and a part of the side surface of the semiconductor 406b, and in some cases, a region with reduced resistance is formed. Since a part of the insulator 406a and the semiconductor 406b has a region with reduced resistance, the contact resistance between the conductor 416 and the semiconductor 40 6b can be reduced.

[0119] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0120] Subsequently, it is processed by a photolithography method or the like to form the conductor 416a and the conductor 41 6b.

[0121] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0122] Next, an insulator that becomes the insulator 410 is formed. The formation of the insulator that becomes the insulator 410 can be carried out using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Or, the spin coating method, dipping method, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method, etc. can be used. printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method, etc. Alternatively, it can be carried out using a curtain coater method or the like.

[0123] The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have a flat upper surface immediately after film formation. Alternatively, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is referred to as a planarization process. Examples of the planarization process include chemical mechanical polishing and dry etching. However, the upper surface of the insulator that becomes the insulator 410 does not necessarily have to have flatness.

[0124] Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed. In addition, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0125] Next, a resist mask 431 is formed on the insulator that becomes the insulator 410 by a photolithography method or the like. Here, in order to improve the adhesion between the upper surface of the insulator that becomes the insulator 410 and the resist mask, for example, an organic coating film may be provided between the upper surface of the insulator that becomes the insulator 410 and the resist mask.

[0126] Next, as shown in FIGS. 8(A) and 8(B), openings are formed in the insulator 410 and the conductor 416. First, after forming the resist mask 431 on the insulator that becomes the insulator 410, the first processing is performed using a dry etching method or the like until reaching the upper surface of the conductor 416. The dry etching method can use the above-described dry etching apparatus, but a parallel plate type Use of an etching apparatus configured to connect high-frequency power supplies with different frequencies to respective electrodes is preferred.

[0127] Next, the conductor 416 may be secondarily processed using a dry etching method or the like to separate the conductor 416 into a conductor 416a and a conductor 416b. Note that the processing of the insulator 410 and the processing of the conductor 416 may be performed during a process by a common photolithography method. By making the processes by the photolithography method common, the number of processes can be reduced. Therefore, the productivity of a semiconductor device having transistors can be increased. At this time, the semiconductor 406b has an exposed region. A part of the exposed region of the semiconductor 406b may be removed by the above-described second processing. In addition, impurity elements such as residual components of the etching gas may adhere to the exposed semiconductor 406b. For example, when a chlorine-based gas is used as the etching gas, chlorine or the like may adhere. Also, when a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, or the like may adhere. For this reason, it is preferable to reduce the impurity elements adhering to the exposed surface of the semiconductor 406b. The reduction of the impurities may be performed, for example, by a cleaning process using dilute hydrofluoric acid or the like, a cleaning process using ozone or the like, or a cleaning process using ultraviolet rays or the like. Note that a plurality of cleaning processes may be combined. As a result, the exposed surface of the semiconductor 406b, in other words, the region where the channel is formed has a high resistance. Next, by performing the above-described high-density plasma process, carbon, hydrogen, or the like may be desorbed. By making the processes by the photolithography method common, the number of processes can be reduced. Therefore, the productivity of a semiconductor device having transistors can be increased.

[0128] At this time, the semiconductor 406b has an exposed region. A part of the exposed region of the semiconductor 406b may be removed by the above-described second processing. In addition, impurity elements such as residual components of the etching gas may adhere to the exposed semiconductor 406b. For example, when a chlorine-based gas is used as the etching gas, chlorine or the like may adhere. Also, when a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, or the like may adhere. For this reason, it is preferable to reduce the impurity elements adhering to the exposed surface of the semiconductor 406b. The reduction of the impurities may be performed, for example, by a cleaning process using dilute hydrofluoric acid or the like, a cleaning process using ozone or the like, or a cleaning process using ultraviolet rays or the like. Note that a plurality of cleaning processes may be combined. As a result, the exposed surface of the semiconductor 406b, in other words, the region where the channel is formed has a high resistance. In addition, impurity elements such as residual components of the etching gas may adhere to the exposed semiconductor 406b. For example, when a chlorine-based gas is used as the etching gas, chlorine or the like may adhere.

[0129] Next, by performing the above-described high-density plasma process, carbon, hydrogen, or the like may be desorbed. ​Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated. can also be desorbed.

[0130] Next, as shown in FIGS. 8(C) and 8(D), on at least the side surfaces of the insulator 410, the upper surface and side surfaces of the semiconductor 406b, the side surfaces of the insulator 406a, the upper surface of the insulator 402, and an insulator 406c is formed on the upper surface of the insulator 410. The formation of the insulator 406c can be performed using a sputtering method.

[0131] Here, the sputtering apparatus used for forming the insulator 406c will be described with reference to FIGS. 21 and 22 and FIG. 22.

[0132] FIG. 21 is a cross-sectional view showing a part of a sputtering apparatus 101. The sputtering apparatus 101 shown in FIG. 21 includes a member 190, a collimator 150 disposed on the member 190, a target holder 120, a backing plate 1 10 disposed on the target holder 120, a target 100 disposed on the backing plate 110, a magnet 130N and a magnet 130S disposed below the target 100 via the backing plate 110, a magnet unit 130 including the magnets 130N and 130S, and a magnet holder 132 for supporting the magnet unit 130. In the present specification, a combination of a plurality of magnets (magnets) is referred to as a magnet unit. The magnet unit can also be referred to as a cathode, a cathode magnet, a magnetic member, a magnetic component, or the like. Note that a substrate stage 170 disposed opposite to the target 100 and the substrate stage are also provided.

[0133] Note that a substrate stage 170 disposed opposite to the target 100 and the substrate stage The substrate 160 supported by 170 is also shown. Also, the magnetic field lines 180a and 180b formed by the magnet unit 130 are shown. are shown.

[0134] The target holder 120 and the backing plate 110 are fixed using screws (such as bolts) and are at the same electrical potential. Also, the target holder 120 has a function of supporting the target 100 via the backing plate 110. The target holder 120 has a function of supporting the target 100 via the backing plate 110. 110 has a function of supporting the target 100.

[0135] The backing plate 110 has a function of fixing the target 100.

[0136] The sputtering apparatus 101 may have a water channel inside or below the backing plate 110. Then, by flowing a fluid (such as air, nitrogen, rare gas, water, oil, etc.) through the water channel, it is possible to suppress abnormal discharge due to an increase in the temperature of the target 100 during sputtering, or damage to the sputtering apparatus 101 due to deformation of any member of the target 100. At this time, it is preferable to closely adhere the backing plate 110 and the target 100 via a bonding material because the cooling performance is enhanced. The sputtering apparatus 101 may have a water channel inside or below the backing plate 110. Then, by flowing a fluid (such as air, nitrogen, rare gas, water, oil, etc.) through the water channel, it is possible to suppress abnormal discharge due to an increase in the temperature of the target 100 during sputtering, or damage to the sputtering apparatus 101 due to deformation of any member of the target 100. The sputtering apparatus 101 may have a water channel inside or below the backing plate 110. Then, by flowing a fluid (such as air, nitrogen, rare gas, water, oil, etc.) through the water channel, it is possible to suppress abnormal discharge due to an increase in the temperature of the target 100 during sputtering, or damage to the sputtering apparatus 101 due to deformation of any member of the target 100. When discharging abnormal due to the temperature rise of the target 100 during sputtering, or damage to the sputtering apparatus 101 due to deformation of any member of the target 100 can be suppressed. At this time, it is preferable to closely adhere the backing plate 110 and the target 100 via a bonding material because the cooling performance is enhanced. When discharging abnormal due to the temperature rise of the target 100 during sputtering, or damage to the sputtering apparatus 101 due to deformation of any member of the target 100 can be suppressed. At this time, it is preferable to closely adhere the backing plate 110 and the target 100 via a bonding material because the cooling performance is enhanced. When discharging abnormal due to the temperature rise of the target 100 during sputtering, or damage to the sputtering apparatus 101 due to deformation of any member of the target 100 can be suppressed. At this time, it is preferable to closely adhere the backing plate 110 and the target 100 via a bonding material because the cooling performance is enhanced.

[0137] In addition, it is preferable to have a gasket between the target holder 120 and the backing plate 110 because it becomes difficult for impurities caused by the outside or the water channel, etc. to mix into the sputtering apparatus 101. In addition, it is preferable to have a gasket between the target holder 120 and the backing plate 110 because it becomes difficult for impurities caused by the outside or the water channel, etc. to mix into the sputtering apparatus 101. In addition, it is preferable to have a gasket between the target holder 120 and the backing plate 110 because it becomes difficult for impurities caused by the outside or the water channel, etc. to mix into the sputtering apparatus 101.

[0138] In the magnet unit 130, the magnet 130N and the magnet 130S are magnets arranged with different polarities facing the target 100 side. Here, the magnet 130N is arranged so that the side facing the target 100 becomes the N pole, and the magnet 130S is arranged so that the side facing the target 100 becomes the S pole. In the magnet unit 130, the magnet 130N and the magnet 130S are magnets arranged with different polarities facing the target 100 side. Here, the magnet 130N is arranged so that the side facing the target 100 becomes the N pole, and the magnet 130S is arranged so that the side facing the target 100 becomes the S pole. In the magnet unit 130, the magnet 130N and the magnet 130S are magnets arranged with different polarities facing the target 100 side. Here, the magnet 130N is arranged so that the side facing the target 100 becomes the N pole, and the magnet 130S is arranged so that the side facing the target 100 becomes the S pole. A case where the target 100 side is arranged to be the S pole will be described. However, the arrangement of the magnets and polarities in the magnet unit 130 is not limited to the arrangement shown in FIG. 21. The magnetic force line 180a is one of the magnetic force lines that form a horizontal magnetic field near the upper surface of the target 100. The vicinity of the upper surface of the target 100 is, for example, a region with a vertical distance of 0 mm or more and 10 mm or less, particularly 0 mm or more and 5 mm or less from the target 100. The magnetic force line 180b is one of the magnetic force lines that form a horizontal magnetic field at a vertical distance d from the upper surface of the magnet unit 130. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less.

[0139] The magnetic force line 180a is one of the magnetic force lines that form a horizontal magnetic field near the upper surface of the target 100. The vicinity of the upper surface of the target 100 is, for example, a region with a vertical distance of 0 mm or more and 10 mm or less, particularly 0 mm or more and 5 mm or less from the target 100. The magnetic force line 180b is one of the magnetic force lines that form a horizontal magnetic field at a vertical distance d from the upper surface of the magnet unit 130.

[0140] The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less. When forming a film, the potential V1 applied to the target holder 120 is, for example, lower than the potential V2 applied to the substrate stage 170.

[0141] The potential V2 applied to the substrate stage 170 is, for example, the ground potential. The potential V3 applied to the magnet holder 132 is, for example, the ground potential. The potentials V1, V2, and V3 are not limited to the above potentials. In addition, potentials do not have to be applied to all of the target holder 120, the substrate stage 170, and the magnet holder 132. For example, the substrate stage 170 may be electrically floating. For example, the substrate stage 170 may be electrically floating. In FIG. 21, an example is shown where the backing plate 110 and the target holder 120 are not electrically connected to the magnet unit 130 and the magnet holder 132.

[0142] In FIG. 21, an example is shown where the backing plate 110 and the target holder 120 are not electrically connected to the magnet unit 130 and the magnet holder 132. The backing plate 110 and the target holder 120 are not electrically connected to the magnet unit 130 and the magnet holder 132. However, it is not limited to this. For example, the backing plate 110 and the target holder 120, and the magnet unit 130 and the magnet holder 132, may be electrically connected and may be at the same electrical potential.

[0143] In the sputtering apparatus 101, a film-forming gas (for example, a rare gas such as argon, oxygen, nitrogen etc.) is flowed, the pressure is kept constant (for example, 0.05 Pa or more and 10 Pa or less, preferably 0.1 Pa or more and 0.8 Pa or less), and when a potential V1 is applied to the target holder 120, a plasma is formed in the magnetic field formed by the mag net unit 130. The potential of the plasma becomes a potential Vp higher than the potential V1. At this time, the cations in the plasma are accelerated toward the target 100 by the potential difference between the potential Vp and the potential V1. Then, when the cations collide with the target 100, sputtered particles are released. Among the released sp uttered particles, the sputtered particles that reach the substrate 160 are deposited as a film.

[0144] Generally, in a sputtering apparatus, at the bottom of a small opening with a large aspect ratio, it is difficult for sp uttered particles to reach. Also, sputtered particles flying in an oblique direction with respect to the substrate may deposit near the upper part of the opening, narrowing the frontage and preventing film formation within the opening.

[0145] On the other hand, by using the sputtering apparatus having the above configuration, among the released sputtered particles, the sputtered particles flying in an oblique direction with respect to the surface of the substrate 160 to be formed adhere to the collimator 150. That is, by installing the collimator 150, the collimator 150 installed between the target 100 and the substrate 160, and having a vertical component with respect to the substrate 160, passes through sputtered particles having a vertical component with respect to the substrate 160 that have passed through the collimator 150 installed between the target 100 and the substrate 160​​​​ Sputtered particles reach the substrate. Thus, they are deposited on a plane parallel to the substrate. On the other hand, sputtered particles do not deposit on a plane perpendicular to the substrate, or deposit less than on a plane parallel to the substrate. Therefore, by using the above sputtering apparatus, as shown in FIGS. 8(C) and 8(D), an insulator 406c can be formed except on a plane perpendicular to the substrate.

[0146] Note that the perpendicular distance between the target 100 and the collimator 150, or between the substrate 160 and the collimator 150 may be appropriately changed depending on the film quality to be formed. Therefore, as shown in FIG. 22, the collimator 150 may include a movable part 151 and a movable part 152. By having the movable part 151, the presence or absence of using the collimator 150 can be easily selected. Also, by having the movable part 152, the perpendicular distance between the collimator 150, the substrate 160, and the target 100 can be easily adjusted.

[0147] Also, the long-throw sputtering method can be used. The long-throw sputtering method is a method in which the perpendicular distance between the target 100 and the substrate 160 is increased to make the incident direction of sputtered particles on the substrate 160 closer to perpendicular. Therefore, even without using the collimator 150, the insulator 406c can be formed except on a plane perpendicular to the substrate. Note that the perpendicular distance between the substrate 160 and the target 100 may be 150 mm or more and 500 mm or less. Also, the collimator 150 may be combined with the long-throw sputtering method.

[0148] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. ​​​​​​​​​​​Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be desorbed from the object to be treated.

[0149] Next, as shown in FIGS. 8(E) and 8(F), an insulator that becomes the insulator 412, a conductor that becomes the conductor 404a, and a conductor that becomes the conductor 404b are formed.

[0150] First, an insulator that becomes the insulator 412 is formed on the insulator 410 and the insulator 406c. The formation of the insulator that becomes the insulator 412 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0151] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be desorbed from the object to be treated.

[0152] Next, the conductor that becomes the conductor 404a and the conductor that becomes the conductor 404b are formed. The formation of the conductor that becomes the conductor 404a and the conductor that becomes the conductor 404b can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductor that becomes the conductor 404a and the conductor that becomes the conductor 404b are formed so as to fill the opening formed by the insulator 410 or the like. Therefore, it is preferable to use a CVD method (particularly an MCVD method). Further, in order to improve the adhesion of the conductor formed by the MCVD method, it may be preferable to form a laminated film of the conductor formed by an ALD method or the like and the conductor formed by the CVD method. For example, a laminated film in which titanium nitride and tungsten are formed in this order may be used.

[0153] ​​​​​​​​​​​​ Subsequently, as shown in FIGS. 9(A) and 9(B), by CMP processing or the like, conductors 404a, 404b, insulator 412, and insulator 406c are removed until insulator 410 is exposed. At this time, insulator 410 can also be used as a stopper layer, and the thickness of insulator 410 may decrease. Therefore, in the completed transistor, conductors 404a and 404b are designed with a margin in the film thickness of insulator 410 so that their resistance is sufficiently low, and a plurality of transistors with little variation can be fabricated. Note that the CMP process may be performed only once or multiple times. When performing the CMP process in multiple steps, it is preferable to perform primary polishing with a high polishing rate and then finish polishing with a low polishing rate. By combining polishings with different polishing rates in this way, the flatness of the polished surface can be further improved. Next, a conductor to be conductor 420 is formed. Note that conductor 420 may have a stacked structure. The formation of the conductor to be conductor 420 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Subsequently, it is processed by photolithography or the like to form conductor 420. Next, as shown in FIGS. 9(C) and 9(D), insulator 408 is formed over insulator 410 and conductor 420. The formation of insulator 408 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Preferably, insulator 408

[0154] Note that the CMP process may be performed only once or multiple times. When performing the CMP process in multiple steps, it is preferable to perform primary polishing with a high polishing rate and then finish polishing with a low polishing rate. By combining polishings with different polishing rates in this way, the flatness of the polished surface can be further improved. Next, a conductor to be conductor 420 is formed. Note that conductor 420 may have a stacked structure. The formation of the conductor to be conductor 420 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Subsequently, it is processed by photolithography or the like to form conductor 420. Next, as shown in FIGS. 9(C) and 9(D), insulator 408 is formed over insulator 410 and conductor 420. The formation of insulator 408 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Preferably, insulator 408

[0155] Next, a conductor to be conductor 420 is formed. Note that conductor 420 may have a stacked structure. The formation of the conductor to be conductor 420 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Subsequently, it is processed by photolithography or the like to form conductor 420. Next, as shown in FIGS. 9(C) and 9(D), insulator 408 is formed over insulator 410 and conductor 420. The formation of insulator 408 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Preferably, insulator 408

[0156] Next, as shown in FIGS. 9(C) and 9(D), insulator 408 is formed over insulator 410 and conductor 420. The formation of insulator 408 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Preferably, insulator 408 By forming an aluminum oxide film using a plasma containing oxygen, oxygen in the plasma can be added as excess oxygen (exO) to the upper surface of the insulator 410. Also, oxygen diffuses through the insulator 410 to the insulator 408, so that excess oxygen can be added. Therefore, a mixed region rich in excess oxygen may be formed near the film interface between the insulator 408 and the insulator 410 at this time. Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be desorbed from the object to be processed. Also, a second heat treatment may be performed at any timing after the formation of the insulator 408. By performing the second heat treatment, excess oxygen contained in the insulator 410 and the mixed region 414 passes through the insulator 412, the insulator 402, the insulator 406c, and the insulator 406a and moves to the semiconductor 406b. Thus, since excess oxygen moves to the semiconductor 406b, defects (oxygen deficiencies) in the semiconductor 406b can be reduced. Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like.

[0157] Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be desorbed from the object to be processed. Incidentally, the second heat treatment may be performed at any timing after the formation of the insulator 408. By performing the second heat treatment, excess oxygen contained in the insulator 410 and the mixed region 414 passes through the insulator 412, the insulator 402, the insulator 406c, and the insulator 406a and moves to the semiconductor 406b. Thus, since excess oxygen moves to the semiconductor 406b, defects (oxygen deficiencies) in the semiconductor 406b can be reduced.

[0158] Also, a second heat treatment may be performed at any timing after the formation of the insulator 408. By performing the second heat treatment, excess oxygen contained in the insulator 410 and the mixed region 414 passes through the insulator 412, the insulator 402, the insulator 406c, and the insulator 406a and moves to the semiconductor 406b. Thus, since excess oxygen moves to the semiconductor 406b, defects (oxygen deficiencies) in the semiconductor 406b can be reduced. Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be desorbed from the object to be processed. Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed. Incidentally, the second heat treatment may be performed at any timing after the formation of the insulator 408. By performing the second heat treatment, excess oxygen contained in the insulator 410 and the mixed region 414 passes through the insulator 412, the insulator 402, the insulator 406c, and the insulator 406a and moves to the semiconductor 406b. Thus, since excess oxygen moves to the semiconductor 406b, defects (oxygen deficiencies) in the semiconductor 406b can be reduced.

[0159] Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like. Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like. Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like. Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like. Incidentally, the second heat treatment may be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, excess oxygen is not excessively released from the insulator 402 or the like. It is possible to suppress the output. Note that the second heat treatment may not be necessary if it can be combined with the heating during the film formation of each layer for equivalent heat treatment. When the film formation can be combined with heating during the film formation of each layer for equivalent heat treatment, it may not be necessary to perform it.

[0160] Also, although not particularly shown, openings reaching the conductors 416a and 416b may be formed in the insulators 408 and 410, and conductors functioning as wirings may be formed in the respective openings. Further, an opening reaching the conductor 404 may be formed in the insulator 408, and a conductor functioning as a wiring may be formed. As described above, the transistor shown in FIG. 1 can be manufactured. In addition, in this embodiment, one aspect of the present invention has been described. However, one aspect of the present invention is not limited to these. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0161] As described above, the transistor shown in FIG. 1 can be manufactured.

[0162] In this embodiment, one aspect of the present invention has been described. However, one aspect of the present invention is not limited to these. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which an oxide semiconductor is used as the semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like.

[0163] As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0164] (Embodiment 2) <Transistor Structure 2> Hereinafter, a transistor having a configuration different from that of FIG. 1 and a method for manufacturing the same will be described with reference to FIG. 2. FIG. 2 shows a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 2 (A) is a top view. FIG. 2(B) is a cross-sectional view corresponding to the dashed line A1 - A2 shown in FIG. 2(A). FIG. 2(C) is a cross-sectional view corresponding to the dashed line A3 - A4 shown in FIG. 2(A). In the top view of FIG. 2(A), some elements are omitted for clarity of the drawing.

[0165] In this transistor, in FIG. 2(B), the side surface of the insulator 410 has an angle θ greater than 0 degrees and less than 90 degrees with respect to the upper surface of the conductor 416a, and an insulator 4 06c is formed on the side surface of the insulator 410. The angle θ is 75 degrees or more and less than 90 degrees, preferably 80 degrees or more and less than 90 degrees, and more preferably 85 degrees or more and less than 90 degrees. The region where the insulator 406 c covers the side surface of the conductor 404 via the insulator 412 is provided with the insulator 406c thinner than the region where the insulator 406c overlaps with the bottom surface of the conductor 4 04. For other configurations, refer to the transistor shown in FIG. 1.

[0166] <Manufacturing Method of Transistor 2> First, the same steps as those up to FIG. 7 shown in Embodiment 1 are performed.

[0167] Next, the side surface of the insulator 410 is formed to have an angle θ greater than 0 degrees and less than 90 degrees with respect to the upper surface of the conductor 416a. Subsequently, using the film-forming apparatus described in Embodiment 1 the insulator 406c is formed. At this time, for example, the smaller the angle θ, the higher the probability that the sputtered particles are deposited, and the insulator 406c is formed thicker on the side surface of the insulator 410. Also, the larger the angle θ, the thinner the insulator 406c is formed on the side surface of the insulator 410. Therefore, the film thickness of the insulator 406c formed on the side surface of the insulator 410 can be adjusted by the angle θ. That is, L1, which is the width of the offset region to be formed, can be made smaller. t1 is larger than L1, and L1 / t1 is less than 1.

[0168] The subsequent steps may be performed in the same manner as the steps in the method 1 for manufacturing a transistor shown in Embodiment 1. That's all.

[0169] As described above, the transistor shown in FIG. 2 can be manufactured.

[0170] As described above, the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. That's all.

[0171] (Embodiment 3) <Transistor Structures 3 and 4> Hereinafter, a transistor having a configuration different from that in FIG. 1 and a method for manufacturing the same will be described with reference to FIGS. 3 and 4. FIGS. 3 and 4 show a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention. That's all. That's all.

[0172] The transistor shown in FIGS. 3 and 4 will be described. FIGS. 3(A) and 4(A) are top views. FIG. 3(B) is a cross-sectional view corresponding to the dashed line A1 - A2 shown in FIG. 3(A). FIG. 3(C) is a cross-sectional view corresponding to the dashed line A3 - A4 shown in FIG. 3(A). Note that, in the top view of FIG. 3(A), some elements are omitted for clarity of the drawing. That's all. That's all. In addition, FIG. 4(B) is a cross-sectional view corresponding to the dashed line A1 - A2 shown in FIG. 4(A). FIG.

[0173] That's all. 4(C) is a cross-sectional view corresponding to the dashed line A3 - A4 shown in Fig. 4(A). In the top view of Fig. 4 (A), some elements are omitted for clarity of the figure.

[0174] The transistors shown in Figs. 3 and 4 include an insulator 406c2 (insulator 406c in Fig. 4), an insulator 412, a conductor 404a, and a conductor 404b, which are also formed in a partial region on the upper surface of the insulator 410. For other configurations, refer to the transistors shown in Fig. 1 or Fig. 2.

[0175] In the transistors shown in Figs. 3 and 4, a part of the conductor 404a that functions as a gate electrode and the conductor 404b may also function as a wiring. That is, via the insulator 406c and the insulator 412, the conductor 404a and the conductor 4 04b formed on the insulator 410 correspond to the conductor 420 in the transistor structure 1. Therefore, in this structure , t2 is the vertical distance between the conductor 416a or the conductor 416b and the conductor 404 a on the insulator 410. In addition, since the insulator 406c2, the insulator 412, the conductor 404a , and the conductor 404b are formed simultaneously, between the upper surface of the insulator 410 and the conductor 404a formed on the insulator 410, the insulator 406c2 (insulator 406c in Fig. 4) and the insulator 412 are interposed. Therefore, t2 is the thickness of the insulator 410 plus the thickness of the insulator 406 c2 (insulator 406c in Fig. 4) and the insulator 412, so that it can have a sufficient distance and suppress the parasitic capacitance.

[0176] <Fabrication Methods 3 and 4 of Transistors> Hereinafter, the fabrication method of the transistor shown in Fig. 3 will be described.

[0177] First, perform the same steps up to FIG. 8 shown in Embodiment 1.

[0178] Next, using a photolithography method or the like, an insulator 406c, an insulator 412, a conductor 4 04a, and a conductor 404b are formed. With this configuration, a conductor corresponding to the conductor 420 in the transistor structure 1 can be formed simultaneously using the conductor 404a and the conductor 404b.

[0179] Next, an insulator 408 is formed.

[0180] As described above, the transistor shown in FIG. 3 can be manufactured.

[0181] Note that for the transistor shown in FIG. 4, an insulator 406c, an insulator 412, a conductor 404a, and a conductor 404b are formed into films using the same steps as those for the transistor shown in FIG. 2. After that using a photolithography method or the like, an insulator 406c, an insulator 412, a conductor 404a, and a conductor 404b having a desired shape are formed. With this configuration, a conductor corresponding to the conductor 420 in the transistor structure 1 can be formed simultaneously using the conductor 404a and the conductor 404b.

[0182] As described above, the transistor shown in FIG. 4 can be manufactured.

[0183] As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0184] (Embodiment 4) <Transistor Structures 5 and 6> Hereinafter, a transistor having a configuration different from that of FIG. 1 and a method for manufacturing the same will be described with reference to FIGS. 5 and 6. FIGS. 5 and 6 show a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention.

[0185] The transistor shown in FIGS. 5 and 6 will be described. Note that FIGS. 5(A) and 6(A) are top views. FIG. 5(B) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 5(A). FIG. 5(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 5(A). Note that in the top view of FIG. 5(A), some elements are omitted for clarity of the drawing.

[0186] Also, FIG. 6(B) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 6(A). FIG. 6(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 6(A). Note that in the top view of FIG. 6 (A), some elements are omitted for clarity of the drawing.

[0187] In the transistors shown in FIGS. 5 and 6, the conductors 416a and 416b are formed only on the semiconductor 4 06b. For other configurations, refer to the transistors shown in FIG. 1 or FIG. 2.

[0188] <Manufacturing Methods of Transistors 5 and 6> Hereinafter, the manufacturing method of the transistor shown in FIG. 5 will be described.

[0189] First, the same steps as those shown in FIGS. 7(A) and 7(B) of Embodiment 1 are performed.

[0190] Next, after forming the insulator 406a and the semiconductor 406b, the conductor 416 is formed. Subsequently, a resist is formed on the conductor 416 by a photolithography method or the like, and the resist Perform the first etching on the conductor 416 using the stopper as a mask. Next, remove the resist After removal, perform the second etching using the conductor 416 as a mask. The second etching is performed on the insulator 406a and the semiconductor 406b.

[0191] The subsequent steps are the same as the steps after FIGS. 7(G) and 7(H) in Embodiment 1. As described above, the transistor shown in FIG. 5 can be fabricated.

[0192] Note that the transistor shown in FIG. 6 also forms the insulator 406a , the semiconductor 406b, and the conductor 416 in the same manner as the transistor shown in FIG. 5. Thereafter, a transistor may be fabricated using the same steps as those of the transistor shown in FIG. 2.

[0193] As described above, the transistor shown in FIG. 6 can be fabricated.

[0194] As described above, the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. It can be used in combination.

[0195] (Embodiment 5) <Transistor Structure 7> Hereinafter, the structure of a transistor included in a semiconductor device according to an aspect of the present invention will be described. .

[0196] FIGS. 10(A), (B), and (C) are a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 10(A) is a top view. FIG. 10(B) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 10(A), and shows a cross-sectional shape in the channel length direction. FIG. 10(C ) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 10(A), and shows a cross-sectional shape in the channel width direction . . shows the cross-sectional shape. In the top view of FIG. 10(A), some elements are omitted for clarity of the drawing and shown as follows. omitted and shown.

[0197] The transistor shown in FIG. 10 includes a conductor 413 and an insulator 401 on a substrate 400, an insulator 402 on the conductor 413 and the insulator 401, an insulator 406a on the insulator 402, a semiconductor 406b on the insulator 406a, conductors 416a and 416b having regions in contact with the upper surface of the semiconductor 406b, the upper surface of the insulator 402, the upper surface of the conductor 416a, and an insulator 410 in contact with the upper surface of the conductor 416b and having an opening, an insulator 406c in contact with the side surface of the conductor 416a, the upper surface and the side surface of the semiconductor 406b, and an insulator 4 06d on the insulator 406c, an insulator 412 in contact with the upper surface of the insulator 406d and the side surface of the opening of the insulator 410, and conductors 404a and 404b arranged on the semiconductor 406b via the insulator 412, the insulator 406c, and the insulator 406d. Note that the conductor 404b faces the side surface of the opening of the insulator 410 via the insulator 412 and the conductor 404a. Also, on the transistor, there are a conductor 420 on the conductors 404a and 404b, and an insulator 408 on the insulator 412 and the conductor 420. Further, as shown in FIGS. 56(A), 56(B), and 56(C), the conductor 413 and the insulator 401 are not essential components, and a configuration without the conductor 413 and the insulator 401 may be employed. The insulator 406c and the insulator 406d preferably have at least one element other than oxygen included in the semiconductor 406b. Thereby, the semiconductor 406b and the insulator 406c and the insulator 406d are formed. The conductor 404 has conductors 404a and 404b. Note that the conductor 404b faces the side surface of the opening of the insulator 410 via the insulator 412 and the conductor 404a. Also, on the transistor, there are a conductor 420 on the conductors 404a and 404b, and an insulator 408 on the insulator 412 and the conductor 420. Further, as shown in FIGS. 56(A), 56(B), and 56(C), the conductor 413 and the insulator 401 are not essential components, and a configuration without the conductor 413 and the insulator 401 may be employed. The insulator 406c and the insulator 406d preferably have at least one element other than oxygen included in the semiconductor 406b. Thereby, the semiconductor 406b and the insulator 406c and the insulator 406d are formed. Note that the conductor 413 and the insulator 401 are not essential components, and a configuration without the conductor 413 and the insulator 401 may be employed. That is, it may be a configuration without the conductor 413 and the insulator 401.

[0198] The insulator 406c and the insulator 406d preferably have at least one element other than oxygen included in the semiconductor 406b. Thereby, the semiconductor 406b and the insulator 406c and the insulator 406d are formed. and at each interface between the insulator 406c and the insulator 406d, generation of defects can be suppressed. Also, the crystallinity of the insulator 406c and the insulator 406d can be improved .

[0199] The semiconductor 406b and the insulator 406c preferably have CAAC-OS, which will be described later. Furthermore, it is preferable that the insulator 406d also has CAAC-OS. Also, it is preferable that the insulator 4 06a also has CAAC-OS.

[0200] In this transistor, the conductors 404a and 404b function as a first gate electrode. Also, at least one of the conductors 404a and 404b is preferably a conductor that is less permeable to oxygen. For example, by forming a conductor that is less permeable to oxygen as the underlying conductor 404 a, it is possible to prevent a decrease in conductivity due to oxidation of the conductor 404b. Also, the insulator 412 functions as a first gate insulator.

[0201] Also, the conductor 413 functions as a second gate electrode. Also, the conductor 413 can have a laminated structure including a conductor having a property of being less permeable to oxygen. By having a laminated structure including a conductor having a property of being less permeable to oxygen, a decrease in conductivity due to oxidation of the conductor 413 can be prevented. The insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by the potential applied to the conductor 41 3. Also, by electrically connecting the first gate electrode and the second gate electrode, the current (on current) during conduction can be increased. Note that the functions of the first gate electrode and the second gate electrode can be interchanged. ​

[0202] Further, the conductor 416a and the conductor 416b function as a source electrode or a drain electrode. Note that the conductivity of the conductor can be measured using a two-terminal method or the like. The resistance of the semiconductor 406b can be controlled by the potential applied to the conductor 404.

[0203] That is, the conduction / non-conduction between the conductor 416a and the conductor 416b can be controlled by the potential applied to the conductor 404. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. That is, the conduction / non-conduction between the conductor 416a and the conductor 416b can be controlled by the potential applied to the conductor 404.

[0204] As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced. As shown in FIG. 10(B), the upper surface of the semiconductor 406b is in contact with the conductor 416a and the conductor 416b. Further, the semiconductor 406b can be electrically surrounded by the electric field of the conductor 404 having a function as a gate electrode. The structure of the transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called a surrounded channel (s-channel) structure. Therefore, a channel may be formed over the entire semiconductor 406b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased. Also, since the semiconductor 406b is surrounded by the electric field of the conductor 404, the current (off-current) during non-conduction can be reduced.

[0205] In the transistor according to the present embodiment, the region functioning as the gate electrode is self-aligningly formed so as to fill the opening formed by the insulator 410 or the like. Therefore, it is a TGSA s-channel FET (Trench Gate Sel In the transistor according to the present embodiment, the region functioning as the gate electrode is self-aligningly formed so as to fill the opening formed by the insulator 410 or the like. Therefore, it is a TGSA s-channel FET (Trench Gate Sel In the transistor according to the present embodiment, the region functioning as the gate electrode is self-aligningly formed so as to fill the opening formed by the insulator 410 or the like. Therefore, it is a TGSA s-channel FET (Trench Gate Sel It can also be called an "f - Align s - channel FET".

[0206] Here, in FIG. 10(B), let the length between the upper surface of the semiconductor 406b in the region overlapping with the conductor 404 and the bottom surface of the conductor 404 be t1. Also, in FIG. 10(B), in the semiconductor 40 6b, let the length between the region overlapping with the bottom surface of the conductor 416a and the region overlapping with the bottom surface of the conductor 404 be L1. Or, let the length between the region overlapping with the bottom surface of the conductor 416b and the region overlapping with the bottom surface of the conductor 4 04 be L1. In the transistor, in the semiconductor 406b, a region (the region where the conductor 40 4 and the semiconductor 406b overlap) where a channel is formed, and a source region or a drain region (the region where the conductor 416

[0207] a or the conductor 416b and the semiconductor 406b overlap), an L1 region is formed between them. By having this region, the off - current of the transistor can be reduced. On the other hand, if this region is too large, the on - current of the transistor will be reduced. Also, by covering the region where the channel of the semiconductor 406b is formed with the insulator 406c and the insulator 4 06d, it is possible to block elements other than oxygen (such as hydrogen, silicon, etc.) that constitute the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator 406c and the insulator 406d only need to be formed at least on the semiconductor 406b.

[0208] Therefore, the insulator 406c and the insulator 406d are not provided on the side surface of the conductor 404 via the insulator 412, or the insulator 406c and the insulator 406d do not pass through the insulator 412

[0209] That's fine.

[0209] So, the insulator 406c and the insulator 406d are not provided on the side surface of the conductor 404 via the insulator 412, or the insulator 406c and the insulator 406d do not pass through the insulator 412 The region covering the side surface of the conductor 404 through the insulator 406c and the insulator 406d is thinner than the overlapping region between the bottom surface of the conductor 404 and the insulator 412. By making the insulator 406c or the insulator 406d thinner, L1 can be reduced. Therefore, t1 is larger than L1, and L1 / t1 is less than 1. Also, in FIGS. 10(B) and 11(A), let the length between the conductor 416a or the conductor 416b and the conductor 420 be t2. Further, in FIG. 10(B), let the length between the conductor 416a and the conductor 416b be L2. As the transistor is miniaturized, the parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. Further, as the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be long enough, the resistance of the conductor 404a and the conductor 404b can be reduced.

[0210] In FIGS. 10(B) and 11(A), the length between the conductor 416a or the conductor 416b and the conductor 420 is t2. Also, in FIG. 10(B), the length between the conductor 416a and the conductor 416b is L2. As the transistor is miniaturized, the parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. In FIGS. 10(B) and 11(A), the length between the conductor 416a or the conductor 416b and the conductor 420 is t2. Also, in FIG. 10(B), the length between the conductor 416a and the conductor 416b is L2.

[0211] As the transistor is miniaturized, the parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance. As the transistor is miniaturized, the parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between the conductor 420 and the conductor 416a or the conductor 416b. When the parasitic capacitance in the vicinity of the region where the channel is formed is large, in transistor operation, time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and thus the responsiveness of the semiconductor device. Also, since unnecessary power is consumed to charge the parasitic capacitance, the power consumption increases in a circuit composed of a plurality of transistors. Therefore, it is preferable that t2 is long enough such that the parasitic capacitance can be ignored compared to the gate capacitance.

[0212] As the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be long enough, the resistance of the conductor 404a and the conductor 404b can be reduced. As the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be long enough, the resistance of the conductor 404a and the conductor 404b can be reduced. As the transistor is miniaturized, L2 becomes smaller, and it becomes difficult to apply a sufficient voltage to the conductor 404a and the conductor 404b. However, by designing t2 to be long enough, the resistance of the conductor 404a and the conductor 404b can be reduced. Therefore, t2 only needs to be larger than L2, preferably t2 / L2 is 1.5 or more. It is preferably 2 or less.

[0213] The transistors in the present embodiment shown in FIGS. 11(A) and 11(B) show an enlarged view of an opening provided in the insulator 41 0. The height of the upper surface of the insulator 406d may be approximately the same as the upper surfaces of the conductors 416a and 416b. Note that the upper surface of the insulator 406d refers to the surface closer to the conductor 404a in the region where the insulator 406d overlaps the bottom surfaces of the conductors 404a and 404b Ideally, as shown in FIG. 11(A), the upper surface of the insulator 406d is preferably at the same height as the upper surfaces of the conductors 416a and 416b.

[0214] Also, the height of the upper surface of the insulator 406c is preferably approximately the same as the interface between the semiconductor 406b and the conductors 416a and 416b. Note that the upper surface of the insulator 406c refers to the surface closer to the conductor 404a in the region where the insulator 406c overlaps the bottom surfaces of the conductors 404a and 404b. Ideally, the upper surface of the insulator 406c is preferably at the same height as the interface between the semiconductor 40 6b and the conductors 416a and 416b. However, the insulator 406c only needs to fill at least the over-etched portion of the semiconductor 406b. As shown in FIG. 11(B), the upper surface of the insulator 406c may be above the interface between the semiconductor 40 6b and the conductors 416a and 416b.

[0215] Also, in the transistor in the present embodiment, the insulator 406c is provided on the semiconductor 406b. Although a configuration is shown in which two layers of the insulator 406d are provided, the present invention is not limited to this, and a stacked structure of three or more layers may be used. As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.

[0216] Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. Further, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, those in which elements are provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element. For example, the insulator substrate includes a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. For the semiconductor substrate, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. For the semiconductor substrate, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. For the semiconductor substrate, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, etc. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, etc. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, etc. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0217] In addition, a flexible substrate may be used as the substrate 400. As a method of providing a transistor on the flexible substrate, there is also a method in which a transistor is fabricated on a non-flexible substrate and then the transistor is peeled off and transferred to the substrate 400 which is a flexible substrate. In that case, It is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that as the substrate 400, , a sheet, film, or foil with fibers woven therein may be used. Also, the substrate 400 may have stretchability. Further, when the substrate 400 stops being bent or pulled, it may have the property of returning to its original shape. Or, it may have the property of not returning to its original shape. The substrate 4 00 has a region with a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. Making the substrate 400 thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate 4 00 thinner, even when using glass or the like, it may have stretchability or the property of returning to its original shape when the bending or pulling stops. Therefore, impacts applied to the semiconductor device on the substrate 400 due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided.

[0218] As the substrate 400 that is a flexible substrate, for example, metal, alloy, resin, or glass, or their fibers or the like can be used. The substrate 400 that is a flexible substrate preferably has less deformation due to the environment as the linear expansion rate is lower. As the substrate 400 that is a flexible substrate, for example, the linear expansion rate is 1×10 / K or less, 5×10 -3 / K or less, or 1×1 -5 / K or less, and a material with such a property can be used. Examples of the resin include polyester, poly 0 -5 olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. In particular, aramid has a low linear expansion rate, so the substrate that is a flexible substrate 400 It is suitable as 400.

[0219] In addition, by surrounding the transistor with an insulator having a function of blocking impurities such as hydrogen and oxygen and oxygen, the electrical characteristics of the transistor can be stabilized. For example, as the insulator 408, an insulator having a function of blocking impurities such as hydrogen and oxygen may be used. That's fine.

[0220] Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include, for example, boron carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium , hafnium or tantalum-containing insulators may be used either singly or in layers.

[0221] Also, for example, as the insulator 408, aluminum oxide, magnesium oxide, oxynitride silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, oxide di lconium, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. Note that the insulator 408 preferably has aluminum oxide. For example, when the insulator 408 is formed using a plasma containing oxygen, oxygen can be added to the insulator 410 which becomes the base layer of the insulator 408. Alternatively, oxygen can be added to the side surface of the insulator 412. The added oxygen becomes excess oxygen in the insulator 410 or the insulator 412. Since the insulator 408 has aluminum oxide, it is possible to suppress the contamination of the semiconductor 406b with impurities such as hydrogen. Also, for example, when the insulator 408 is aluminum oxide It is also possible. The added oxygen becomes excess oxygen in the insulator 410 or the insulator 412. Since the insulator 408 has aluminum oxide, it is possible to suppress the contamination of the semiconductor 406b with impurities such as hydrogen. Also, for example, when the insulator 408 is aluminum oxide It is possible to suppress the mixing of impurities such as hydrogen into the semiconductor 406b. Also, for example, if the insulator 408 is aluminum oxide nium By having yttrium, outward diffusion of the excess oxygen added to the above-described insulators 410 and 412 can be reduced. Diffusion can be reduced.

[0222] As the insulator 402, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminated structure. For example, it is preferable that the insulator 402 has silicon oxide or silicon oxynitride. luminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminated structure. For example, as the insulator 402, it is preferable to have silicon oxide or silicon oxynitride.

[0223] Note that the insulator 410 preferably has an insulator with a low relative permittivity. For example, the insulator 410 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin. Or, the insulator 410 preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide with pores, and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low relative permittivity can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic. 410 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added silicon, silicon oxide with pores or resin. Or, the insulator 410 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added silicon or silicon oxide with pores, and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low relative permittivity can be obtained by combining them with resin. As the resin, for example, polyester, polyolefin, polyamide (nylon, aramid, etc.) , polyimide, polycarbonate or acrylic may be used.

[0224] ​​As the insulator 412, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminated form. For example, the insulator 412 preferably has silicon oxide or silicon nitride oxide.

[0225] Note that the insulator 412 preferably has an insulator with a high relative permittivity. For example, the insulator 412 preferably has gallium oxide, hafnium oxide, an oxide having aluminum and hafnium , a nitride oxide having aluminum and hafnium, an oxide having silicon and hafnium, or a nitride oxide having silicon and hafnium. Or, the insulator 412 preferably has a laminated structure of silicon oxide or silicon nitride oxide and an insulator with a high relative permittivity. Since silicon oxide and silicon nitride oxide are thermally stable, a laminated structure that is thermally stable and has a high relative permittivity can be obtained by combining them with an insulator having a high relative permittivity. For example, by having aluminum oxide, gallium oxide or hafnium oxide on the insulator 406c and the insulator 406d sides, it is possible to suppress silicon contained in silicon oxide or silicon nitride oxide from mixing into the semiconductor 406b. Also, for example, by having silicon oxide or silicon nitride oxide on the insulator 406c and the insulator 406d sides, a trap center may be formed at the interface between aluminum oxide, gallium oxide or hafnium oxide and silicon oxide or silicon nitride oxide. The trap center captures electrons and forms a trap... There may be cases where the threshold voltage of the transistor can be varied in the positive direction.

[0226] As the conductors 416a and 416b, for example, a conductor containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver , indium, tin, tantalum, and tungsten may be used either as a single layer or in a stacked layer. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may be used. .

[0227] As the conductors 404, 413, and 420, for example, a conductor containing one or more of boron, nitrogen, oxygen , fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel , copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver , indium, tin, tantalum, and tungsten may be used either as a single layer or in a stacked layer. For example, it may be an alloy film or a compound film, and conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin, and oxygen, or conductors containing titanium and nitrogen may be used. .

[0228] As the semiconductor 406b, it is preferable to use an oxide semiconductor. However, silicon (strained silicon-containing), germanium, silicon germanium, silicon carbide, gallium arsenide, It may be possible to use aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor, etc. There may be cases where it is acceptable.

[0229] As the insulator 406a, the insulator 406c, and the insulator 406d, it is preferable to use an oxide composed of one or more elements other than oxygen that constitute the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, carbon silicon, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor, etc. may be used in some cases. The semiconductor 406b is, for example, an oxide semiconductor containing indium. When the semiconductor 406b contains indium, for example, the carrier mobility (electron mobility) becomes high. Also, it is preferable for the semiconductor 406b to contain the element M. The element M is preferably aluminum, gallium,

[0230] yttrium, or tin, etc. Other elements applicable as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, as the element M, there may be cases where a plurality of the aforementioned elements may be combined. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element having a higher binding energy with oxygen than indium. Or, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Also, it is preferable for the semiconductor 406b to contain zinc. The oxide semiconductor may be more likely to crystallize when it contains zinc.

[0231] ​​​​​​​However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. The semiconductor 40 6b may be, for example, an oxide semiconductor that does not contain indium, such as zinc tin oxide or gallium tin oxide, and contains lead, or an oxide semiconductor containing gallium, or an oxide semiconductor containing tin. That's okay.

[0232] For the semiconductor 406b, for example, an oxide with a large energy gap is used. The energy gap of the semiconductor 406 b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0233] Also, the insulator 406a, the insulator 406c, and the insulator 406d are oxides composed of one or more elements other than oxygen that constitute the semiconductor 406b. Since the insulator 406a, the insulator 406c, and the insulator 406d are composed of one or more elements other than oxygen that constitute the semiconductor 406b, at the interface between the insulator 406a and the semiconductor 406b, the interface between the semiconductor 406b and the insulator 406c, and the interface between the insulator 406c and the insulator 406d, defect levels are less likely to be formed. One or more elements other than oxygen that constitute the semiconductor 406b, or two or more elements form the insulator 406a, the insulator 406c, and the insulator 406d. Therefore, at the interface between the insulator 406a and the semiconductor 406b, the interface between the semiconductor 406b and the insulator 406c, and the interface between the insulator 406c and the insulator 406d, defect levels are less likely to be formed. At the interface between the insulator 406a and the semiconductor 406b, the interface between the semiconductor 406b and the insulator 406c, and the interface between the insulator 406c and the insulator 406d, defect levels are less likely to be formed.

[0234] For the semiconductor 406b, an oxide with a greater electron affinity than the insulator 406a, the insulator 406c, and the insulator 406d is used. For example, as the semiconductor 406b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less greater than that of the insulator 406a, the insulator 406c, and the insulator 406d is used. Note that the electron affinity is the energy between the vacuum level and the lower end of the conduction band. For example, as the semiconductor 406b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less greater than that of the insulator 406a, the insulator 406c, and the insulator 406d is used. Note that the electron affinity is the energy between the vacuum level and the lower end of the conduction band. is the difference. Also, from the insulator 406d, the insulator 406c preferably has a larger electron affinity. Preferably.

[0235] Thus, in the transistor in which the insulator 406a, the insulator 406c, and the insulator 406d are arranged above and below the semiconductor 406b, when a gate voltage is applied, among the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, a channel is formed in the semiconductor 406b having a large electron affinity. In this way, a so-called buried channel structure can be formed. Here, between the insulator 406a and the semiconductor 406b, there may be a mixed region between the insulator 406a and the semiconductor 406b. Also, between the semiconductor 406b and the insulator 406c, there may be a mixed region between the semiconductor 406b and the insulator 406c. Also, between the insulator 406c and the insulator 406d, there may be a mixed region between the insulator 406c and the insulator 406d. The mixed region has a low defect level density. Therefore, in the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, energy changes continuously in the vicinity of each interface (also referred to as a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. At this time, electrons mainly move in the semiconductor 406b rather than in the insulator 406a, the insulator 406c, and the insulator 406d. As described above, a so-called buried channel structure can be formed. It can be done.

[0236] Here, between the insulator 406a and the semiconductor 406b, there may be a mixed region between the insulator 406a and the semiconductor 406b. Also, between the semiconductor 406b and the insulator 406c, there may be a mixed region between the semiconductor 406b and the insulator 406c. Also, between the insulator 406c and the insulator 406d, there may be a mixed region between the insulator 406c and the insulator 406d. The mixed region has a low defect level density. Therefore, in the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, energy changes continuously in the vicinity of each interface (also referred to as a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. Also, between the semiconductor 406b and the insulator 406c, there may be a mixed region between the semiconductor 406b and the insulator 406c. Also, between the insulator 406c and the insulator 406d, there may be a mixed region between the insulator 406c and the insulator 406d. The mixed region has a low defect level density. Therefore, in the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, energy changes continuously in the vicinity of each interface (also referred to as a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. There may be a mixed region between the semiconductor 406b and the insulator 406c. Also, between the insulator 406c and the insulator 406d, there may be a mixed region between the insulator 406c and the insulator 406d. The mixed region has a low defect level density. Therefore, in the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, energy changes continuously in the vicinity of each interface (also referred to as a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. There may be a mixed region between the insulator 406c and the insulator 406d. The mixed region has a low defect level density. Therefore, in the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, energy changes continuously in the vicinity of each interface (also referred to as a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. The mixed region has a low defect level density. Therefore, in the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, energy changes continuously in the vicinity of each interface (also referred to as a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. In the laminate of the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d, in the vicinity of each interface, energy changes continuously (also referred to as a continuous junction). (Also called a continuous junction). Note that the insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. The insulator 406a, the semiconductor 406b, the insulator 406c, and the insulator 406d may not be able to clearly distinguish each interface. There may be cases where it is not possible to clearly distinguish each interface.

[0237] At this time, electrons do not move mainly in the insulator 406a, the insulator 406c, and the insulator 406d, but mainly move in the semiconductor 406b. The on-current of the transistor increases as the factors that inhibit the movement of electrons are reduced.

[0238] The on-current of the transistor increases as the factors that inhibit the movement of electrons are reduced. This is possible. The movement of electrons is inhibited even when, for example, the physical irregularities of the channel formation region are large. This is inhibited.

[0239] In order to increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper surface or the lower surface (the surface to be formed, here the upper surface of the insulator 406a) of the semiconductor 406b is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Also, the average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0 .4 nm. Further, the maximum height difference (also referred to as P-V) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and P-V can be measured using a scanning probe microscope system SPA-500 manufactured by SII NanoTechnology Inc., etc. . The above-described four-layer structure is an example. For example, it may be a laminated structure having one or more of the insulators exemplified as the insulator 406a, the insulator 406c, and the insulator 406d above or below the insulator 406a, or above or below the insulator 4 06d. For details of the oxide semiconductor that can be used for the semiconductor, it will be described in detail in other embodiments.

[0240] The above four-layer structure is an example. For example, it may be a laminated structure having one or more of the insulators exemplified as the insulator 406a, the insulator 406c, and the insulator 406d above or below the insulator 406a, or above or below the insulator 4 06d.

[0241] Note that details of the oxide semiconductor that can be used for the semiconductor will be described in detail in other embodiments.

[0242] <Manufacturing method of transistor 7> Hereinafter, the method for manufacturing the transistor of FIG. 10 according to the present invention will be described with reference to FIGS. 18 to 20. Explain.

[0243] First, a substrate 400 is prepared.

[0244] Next, as shown in FIGS. 18(A) and 18(B), an insulator serving as the insulator 401 is formed on the substrate 400, an opening is formed in the insulator 401, and a conductor serving as the conductor 413 is formed on the insulator 401. The conductor serving as the conductor 413 can be formed by using a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. Further, the conductor 413 may have a multilayer structure including a conductor having a property of being difficult to permeate oxygen. Next, chemical mechanical polishing (CMP) or the like is used to fill the opening of the insulator 401 with the conductor 413. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. Insulator, form a conductor on the insulator 401 to become the conductor 413. The film formation of the conductor that becomes the conductor 413 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductor 413 may have a multilayer structure including a conductor having a property of being difficult to permeate oxygen. Next, chemical mechanical polishing (CMP) or the like is used to fill the opening of the insulator 401 with the conductor 413. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. The film formation of the conductor that becomes the conductor 413 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductor 413 may have a multilayer structure including a conductor having a property of being difficult to permeate oxygen. Next, chemical mechanical polishing (CMP) or the like is used to fill the opening of the insulator 401 with the conductor 413. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. BE method or PLD method, ALD method, etc. can be used. Further, the conductor 413 may have a multilayer structure including a conductor having a property of being difficult to permeate oxygen. Next, chemical mechanical polishing (CMP) or the like is used to fill the opening of the insulator 401 with the conductor 413. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. It is also possible to use chemical mechanical polishing (CMP) or the like to fill the opening of the insulator 401 with the conductor 413. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. hemical Mechanical Polishing: CMP) etc. It is advisable to embed the conductor 413 in the opening of the insulator 401. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. As another method of forming the conductor 413, a conductor may be formed and processed using a photolithography method or the like to form the conductor 413. It may be formed.

[0245] In the photolithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed. Also, as described above. The exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed. Also, as described above. Next, by performing an etching process through the resist mask, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed. Also, as described above. For example, by using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. It is sufficient to form a resist mask by exposing the resist. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed. Also, as described above. The resist mask may be formed by exposing the resist. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed. Also, as described above. A liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed, and a liquid immersion technique may be used. Also, as described above. Instead of light, an electron beam or an ion beam may be used. When using an electron beam or an ion beam, a mask is not required. For removing the resist mask, dry etching treatment such as ashing, wet etching treatment, or wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment can be performed. When using an electron beam or an ion beam, a mask is not required. For removing the resist mask, dry etching treatment such as ashing, wet etching treatment, or wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment can be performed. When using an electron beam or an ion beam, a mask is not required. For removing the resist mask, dry etching treatment such as ashing, wet etching treatment, or wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment can be performed. When using an electron beam or an ion beam, a mask is not required. For removing the resist mask, dry etching treatment such as ashing, wet etching treatment, or wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment can be performed. When using an electron beam or an ion beam, a mask is not required. For removing the resist mask, dry etching treatment such as ashing, wet etching treatment, or wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment can be performed.

[0246] As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like. As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high density plasma source can be used. The dry etching apparatus having a high density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Couple d Plasma) etching apparatus or the like.

[0247] Next, as shown by the arrows in FIG. 18(A) or (B), high density plasma treatment may be performed. The high density plasma treatment is preferably performed in an oxygen atmosphere or a nitrogen atmosphere. The oxygen atmosphere is a gas atmosphere having oxygen atoms, such as oxygen, ozone, or nitrogen oxide (nitric oxide). Next, as shown by the arrows in FIG. 18(A) or (B), high density plasma treatment may be performed. The high density plasma treatment is preferably performed in an oxygen atmosphere or a nitrogen atmosphere. The oxygen atmosphere is a gas atmosphere having oxygen atoms, such as oxygen, ozone, or nitrogen oxide (nitric oxide). Next, as shown by the arrows in FIG. 18(A) or (B), high density plasma treatment may be performed. The high density plasma treatment is preferably performed in an oxygen atmosphere or a nitrogen atmosphere. The oxygen atmosphere is a gas atmosphere having oxygen atoms, such as oxygen, ozone, or nitrogen oxide (nitric oxide). , an atmosphere such as nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, dinitrogen tetroxide, dinitrogen pentoxide, etc. It means that. Also, in an oxygen atmosphere, nitrogen or a noble gas (helium, argon, etc.) The inert gas may be included. By performing high-density plasma treatment in such an oxygen atmosphere , for example, carbon, hydrogen, etc. can be desorbed. Also, by performing high-density Plasma treatment, organic compounds such as hydrocarbons can also be desorbed from the object to be treated off.

[0248] As the high-density plasma treatment in a nitrogen atmosphere, for example, in an atmosphere containing nitrogen and a noble gas, or in an atmosphere containing nitrogen, hydrogen, and a noble gas, or in an atmosphere containing ammonia and a noble gas , the above high-density plasma treatment may be performed. Thereby, the surface of the object to be treated and its vicinity can be nitrided. The nitrided region can be formed extremely thinly on the surface side of the object to be treated . Also, the diffusion of impurities can be suppressed by the nitrided region formed in this way.

[0249] Also, the high-density plasma treatment may be performed in a nitrogen atmosphere after being performed in an oxygen atmosphere, or after being treated in a nitrogen atmosphere, it may be treated in an oxygen atmosphere. Also, annealing treatment may be performed before and after each high-density plasma treatment . In order to increase the density of the plasma, it may be preferable to flow a sufficient amount of gas. If the amount of gas is not sufficient, the inactivation rate may be higher than the generation rate of radicals . For example, it may be preferable to flow the gas at 100 sccm or more, 30 0 sccm or more, or 800 sccm or more. The high-density plasma treatment is, for example, at a frequency of 0.3 GHz or more and 3.0 GHz or less, 0.7 GH

[0250] ​Above z and below 1.1 GHz, or above 2.2 GHz and below 2.8 GHz (typically 2.4 5 GHz), microwaves generated using a high-frequency generator may be used. Also, the processing pressure is 10 Pa or more and 5000 Pa or less, preferably 200 Pa or more and 1500 Pa or less, and more preferably 300 Pa or more and 1000 Pa or less, and the substrate temperature is 100 °C or more and 600 °C or less ( typically 400 °C), and it can be carried out using a mixed gas of oxygen and argon.

[0251] High-density plasma is generated, for example, by using microwaves of 2.45 GHz, with an electron density of 1×10 11 / cm 3 or more and 1×10 13 / cm 3 or less, an electron temperature of 2 eV or less , or an ion energy of 5 eV or less is preferable. Such high-density plasma processing results in a small kinetic energy of radicals and less damage caused by the plasma compared to conventional plasma processing. Therefore, a film with fewer defects can be formed. The distance from the antenna that generates microwaves to the object to be processed is 5 mm or more and 120 mm or less, preferably 20 mm or more and 60 mm or less.

[0252] Alternatively, it may have a plasma power supply that applies an RF (Radio Frequency) bias to the substrate side. The frequency of the RF bias can be, for example, 13.56 MHz or 27.1 2 MHz, etc. By using high-density plasma, higher-density oxygen ions can be generated, and by applying an RF bias to the substrate side, the oxygen ions generated by the high-density plasma can be efficiently guided to the object to be processed. Therefore, it is preferable to perform high-density plasma processing while applying a substrate bias. ​​​

[0253] Also, after the high-density plasma treatment, an annealing treatment may be continuously performed without exposing to the atmosphere. Alternatively, the high-density plasma treatment may be continuously performed without exposing to the atmosphere after the annealing treatment. By continuously performing the high-density plasma treatment and the annealing treatment, it is possible to suppress the mixing of impurities during the treatment. Also, after performing the high-density plasma treatment in an oxygen atmosphere, by performing the annealing treatment, unnecessary oxygen that has not been used for compensating oxygen deficiency among the oxygen added to the object to be processed can be desorbed. Also, the annealing treatment may be performed, for example, by lamp annealing or the like.

[0254] Also, the treatment time of the high-density plasma treatment is preferably 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less,

[0255] 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less. Also, the annealing treatment is preferably performed at a temperature of 250°C or more and 800°C or less, 300°C or more and 700°C or less, or 4 00°C or more and 600°C or less, and the treatment time is preferably 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less,

[0256] 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less. Next, the insulator 402 is formed. The formation of the insulator 402 can be performed using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. ​​​​​​​

[0257] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, and the like. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the source gas used. nhanced CVD) method, a thermal CVD (TCVD: Thermal CV D) method, a photo CVD (Photo CVD) method that uses light, and the like. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD ( MOCVD: Metal Organic CVD) method depending on the source gas used. MOCVD: Metal Organic CVD) method depending on the source gas used.

[0258] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in semiconductor devices may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, since damage caused by being exposed to plasma as described above does not occur, the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since the film is not exposed to plasma during film formation, a film with few defects is easily obtained. On the other hand, in the case of the thermal CVD method that does not use plasma, since damage caused by being exposed to plasma as described above does not occur, the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since the film is not exposed to plasma during film formation, a film with few defects is easily obtained. easily obtained.

[0259] Also, the ALD method is a film-forming method capable of reducing plasma damage to the object to be processed. Also, since no plasma damage occurs during film formation in the ALD method, a film with few defects is obtained.

[0260] The CVD method and the ALD method are different from the film-forming method in which particles emitted from a target or the like are deposited. It is a film-forming method in which a film is formed by a reaction on the surface of an object to be processed. Therefore it is a film-forming method that is less affected by the shape of the object to be processed and has good step coverage. In particular the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio etc. However, since the ALD method has a slow film-forming rate it is sometimes preferable to use it in combination with other film-forming methods such as the CVD method with a high film-forming rate in some cases.

[0261] The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gases For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers the time required for film formation can be shortened by the time required for transfer and pressure adjustment. Therefore, the productivity of semiconductor devices may be increased

[0262] Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed

[0263] In addition, a treatment for adding oxygen to the insulator 402 may be performed. Examples of the treatment for adding oxygen include, for example, the ion implantation method, the plasma treatment method, etc. Note that the oxygen added to the insulator 402 becomes excess oxygen ​​​

[0264] Next, as shown in FIG. 18(C) and FIG. 18(D), the insulator 406a, the semiconductor A semiconductor that will become the body 406b and a resist mask 430 are formed.

[0265] First, an insulator that will become the insulator 406a is formed over the insulator 402. The insulator film is formed by sputtering, CVD, MBE, PLD, ALD, etc. In particular, the deposition can be performed using a facing target sputtering device. In this specification and the like, the term "facing target type sputtering apparatus" is used. The deposition method using this method is also called VDSP (vapor deposition SP). can.

[0266] By depositing an insulator using a facing target sputtering device, This reduces plasma damage in the film, thereby reducing oxygen vacancies in the film. In addition, by using a facing target sputtering device, film formation in a high vacuum is possible. This allows the concentration of impurities (e.g. hydrogen, rare gas (argon, etc.)) in the deposited insulator to be ), water, etc.) can be reduced.

[0267] Also, a sputtering device having an inductively coupled antenna conductor plate may be used. This allows for a high film formation speed and the formation of a film with a large area and high uniformity.

[0268] The film is preferably formed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0269] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated.

[0270] Also, a process of adding oxygen to the insulator that becomes the insulator 406a may be performed. As a process of adding oxygen, there are an ion implantation method, a plasma treatment method, etc. Note that the oxygen added to the insulator that becomes the insulator 406a becomes excess oxygen.

[0271] Next, a semiconductor that becomes the semiconductor 406b is formed on the insulator that becomes the insulator 406a. The formation of the semiconductor can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In particular, it is preferable to form a film using a facing target type sputtering apparatus.

[0272] By forming a semiconductor using a facing target type sputtering apparatus, plasma damage during film formation can be reduced. Therefore, oxygen vacancies in the film can be reduced. Also, by using a facing target type sputtering apparatus, film formation in a high vacuum becomes possible. Thereby, the impurity concentration (for example, hydrogen, noble gas (such as argon ), water, etc.) in the formed semiconductor can be reduced.

[0273] Also, a sputtering apparatus having an inductively coupled antenna conductor plate may be used. Thereby, a high film formation rate, a large area, and a highly uniform film can be formed.

[0274] It is preferable to perform film formation using a gas containing oxygen, a noble gas, a gas containing nitrogen, etc. Nitrogen ​Gases that contain nitrogen (N2), nitrous oxide (N2O), ammonia (NH3 ) etc. can be used.

[0275] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 450° C. or higher and 600° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. This can improve the crystallinity of a semiconductor and remove impurities such as hydrogen and water. Alternatively, the first heat treatment may be performed using a plasma treatment containing oxygen under reduced pressure. The plasma treatment includes, for example, a power source that generates high-density plasma using microwaves. It is preferable to use a device that can perform the same process as the above. y) A plasma power supply for applying a voltage may be provided. By using high density plasma, By applying RF voltage to the substrate, high density printing can be achieved. The oxygen radicals generated by the plasma can be efficiently guided into the semiconductor 406b. Alternatively, the apparatus can be used to supplement the oxygen released after plasma treatment containing an inert gas. In order to achieve this, a plasma treatment containing oxygen may be performed.

[0276] Next, as shown in FIG. 18(E) and FIG. 18(F), the insulator that will become the insulator 406a and A semiconductor to be a semiconductor 406b is formed by photolithography using a resist mask 430. It is processed by, etc., to form a multilayer film having an insulator 406a and a semiconductor 406b. When forming the multilayer film, the insulator 402 may also be etched and some regions may become thinner. That is, the insulator 402 may have a shape with convex portions in the regions in contact with the multilayer film. There is.

[0277] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated. There is.

[0278] Next, as shown in FIGS. 18(G) and 18(H), an insulator composed of a conductor 416 and an insulator 410 is formed. is formed.

[0279] First, the conductor 416 is formed. The film formation of the conductor 416 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0280] Note that the conductor 416 has a shape that covers the multilayer film. When forming the conductor on the multilayer film, damage is caused to a part of the side surface of the insulator 406a, the upper surface of the semiconductor 406b, and the side surface of the semiconductor 406b. By being given, a region with reduced resistance may be formed. Since a part of the insulator 406a and the semiconductor 406b has a region with reduced resistance, the contact resistance between the conductor 416 and the semiconductor 40 6b can be reduced. 6b, can be reduced. 6b and can be reduced.

[0281] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated. There is.

[0282] Subsequently, it is processed by a photolithography method or the like to form the conductor 416a and the conductor 41 6b.

[0283] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0284] Next, an insulator that becomes the insulator 410 is formed. The formation of the insulator that becomes the insulator 410 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Or, it can be performed using a spin coating method, a dip method, a droplet ejection method (such as an inkjet method), a printing method (such as screen printing, offset printing, etc.), a doctor knife method, a roll coater method, or a curtain coater method. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness.

[0285] The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness. The insulator that becomes the insulator 410 may be formed so that the upper surface has flatness. For example, the insulator that becomes the insulator 410 may have flatness on the upper surface immediately after film formation. Or, for example, the insulator that becomes the insulator 410 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a planarization process. Examples of the planarization process include a chemical mechanical polishing process and a dry etching process. However, the upper surface of the insulator that becomes the insulator 410 does not have to have flatness.

[0286] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. In addition, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0287] Next, a resist mask 431 is formed on the insulator that will become the insulator 410 by a photolithography method or the like. Here, in order to improve the adhesion between the upper surface of the insulator that will become the insulator 410 and the resist mask, for example, an organic coating film may be provided between the insulator that will become the insulator 410 and the resist mask.

[0288] Next, as shown in FIGS. 19(A) and 19(B), openings are formed in the insulator 410 and the conductor 416. First, the insulator that will become the insulator 410 is subjected to a first process using a dry etching method or the like until it reaches the upper surface of the conductor 416. As the dry etching method, the above-described dry etching apparatus can be used, but it is preferable to use a dry etching apparatus configured to connect high-frequency power supplies having different frequencies to each of the parallel plate electrodes.

[0289] Next, the conductor 416 is subjected to a second process using a dry etching method or the like to separate the conductor 416 into a conductor 416a and a conductor 416b. Note that the processing of the insulator 410 and the processing of the conductor 416 may be performed during a process using a common photolithography method. By sharing the process using the photolithography method, the number of processes can be reduced. Therefore, the productivity of the semiconductor device having the transistor can be increased.

[0290] At this time, the semiconductor 406b has an exposed region. ​​​​​​​​​​​​​A part may be removed by the above-described second processing. Also, impurities such as residual components of the etching gas may adhere to the exposed semiconductor 406b. For example, when a chlorine-based gas is used as the etching gas, chlorine or the like may adhere. Also, when a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, or the like may adhere. Therefore, it is preferable to reduce the impurity elements adhering to the exposed surface of the semiconductor 406b. The reduction of the impurities can be performed, for example, by a cleaning process using dilute hydrofluoric acid or the like, a cleaning process using ozone or the like, or a cleaning process using ultraviolet rays or the like. Note that a plurality of cleaning processes may be combined. As a result, the exposed surface of the semiconductor 406b, in other words, the region where the channel is formed becomes high resistance.

[0291] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, or the like may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0292] Next, as shown in FIGS. 19(C) and 19(D), an insulator 406c is formed on the upper surface and side surfaces of the semiconductor 406b, the side surface of the insulator 406a, the upper surface of the insulator 402, and the upper surface of the insulator 410, except at least the side surface of the insulator 410. Note that the insulator 406c is preferably formed so as to fill the groove formed in the semiconductor 406b. The film formation of the insulator 406c can be performed using a sputtering method.

[0293] Here, the sputtering apparatus used for the film formation of the insulator 406c and the insulator 406d will be described with reference to FIGS. 21 and 22. ​​​​​​​​​

[0294] FIG. 21 is a cross-sectional view showing a part of the sputtering apparatus 101. The sputtering ring apparatus 101 includes a member 190, a collimator 150 disposed on the member 190, a target holder 120, a backing plate 1 10 disposed on the target holder 120, a target 100 disposed on the backing plate 110, a magnet 130N and a magnet 130S disposed below the target 100 via the backing plate 110, a magnet unit 130 including the magnet 130N and the magnet 130S, and a magnet holder 132 that supports the magnet unit 130. In this specification, a combination of a plurality of magnets (magnets) is referred to as a magnet unit. The magnet unit can also be referred to as a cathode, a cathode magnet, a magnetic member, a magnetic component, etc.

[0295] Note that a substrate stage 170 disposed opposite to the target 100 and a substrate 160 supported by the substrate stage 170 are also shown. Also shown are magnetic field lines 180a and 180b formed by the magnet unit 130.

[0296] The target holder 120 and the backing plate 110 are fixed using screws (bolts, etc.) and are at the same potential. Also, the target holder 120 has a function of supporting the target 100 via the backing plate 110.

[0297] The backing plate 110 has a function of fixing the target 100.

[0298] The sputtering apparatus 101 has a water channel inside or below the backing plate 110, etc. ​​​​It may be provided. Then, fluid (such as air, nitrogen, noble gas, water, oil, etc.) is allowed to flow through the water channel. By doing so, it is possible to suppress abnormal discharges due to an increase in the temperature of the target 100 during sputtering, and damage to the sputtering apparatus 101 caused by deformation of any member of the target 100. At this time, it is preferable to bond the backing plate 110 and the target 100 via a bonding material because the cooling performance is enhanced.

[0299] In addition, it is preferable to have a gasket between the target holder 120 and the backing plate 110 because it becomes difficult for impurities resulting from the outside or a water channel, etc. to mix into the sputtering apparatus 101.

[0300] In the magnet unit 130, the magnet 130N and the magnet 130S are magnets arranged with different polarities facing the target 100 side. Here, the case where the magnet 130N is arranged such that the side facing the target 100 is the N - pole and the magnet 130S is arranged such that the side facing the target 100 is the S - pole will be described. However, the arrangement of the magnets and polarities in the magnet unit 130 is not limited to the arrangement in FIG. 21.

[0301] The magnetic field line 180a is one of the magnetic field lines that form a horizontal magnetic field near the upper surface of the target 100. The vicinity of the upper surface of the target 100 is, for example, a region where the vertical distance from the target 100 is 0 mm or more and 10 mm or less, particularly 0 mm or more and 5 mm or less.

[0302] The magnetic field line 180b is one of the magnetic field lines that form a horizontal magnetic field at a vertical distance d from the upper surface of the magnet unit 130. The vertical distance d is, for example, 0 mm or more and 20 mm or less or ​​​​​​​​​​​​ Between 5mm and 15mm.

[0303] During film formation, the potential V1 applied to the target holder 120 is, for example, The potential V2 applied to the substrate stage 170 is lower than the potential V3 applied to the substrate stage 170. The potential V2 is, for example, a ground potential. The potential V1, the potential V2, and the potential V3 are the above potentials. In addition, the target holder 120, the substrate stage 170, the magnet holder For example, if the substrate stage 170 is electrically It doesn't matter if it's floating on the target.

[0304] In addition, in FIG. 21, the backing plate 110, the target holder 120, and the magnet In this example, the magnet unit 130 and the magnet holder 132 are not electrically connected. For example, the backing plate 110 and the target holder 120 is electrically connected to the magnet unit 130 and the magnet holder 132. The potentials may be equipotential.

[0305] A deposition gas (for example, a rare gas such as argon, oxygen, nitrogen, etc.) is placed in the sputtering device 101. The pressure is kept constant (for example, 0.05 Pa or more and 10 Pa or less, preferably 0.1 When a potential V1 is applied to the target holder 120, Plasma is generated in the magnetic field generated by the net unit 130. The potential becomes Vp, which is higher than the potential V1. At this time, the positive ions in the plasma It is accelerated toward the target 100 by the potential difference between Vp and the potential V1. Then, the positive ions collide with the target 100 to release sputter particles. Among the released sputter particles, the sputter particles that reach the substrate 160 are deposited as a film.

[0306] Generally, in a sputtering apparatus, at the bottom of an opening with a large aspect ratio and a small size, it is difficult for sputter particles to reach. Also, sputter particles flying in an oblique direction with respect to the substrate may be deposited near the upper part of the opening, narrowing the frontage, and may not form a film inside the opening.

[0307] On the other hand, by using the sputtering apparatus having the above configuration, among the released sputter particles, the sputter particles flying in an oblique direction with respect to the surface to be formed of the substrate 160 adhere to the collimator 150. That is, by installing the collimator 150, the sputter particles having a vertical component with respect to the substrate 160, which have passed through the collimator 150 installed between the target 100 and the substrate 160 reach the substrate. Therefore, they are deposited on a plane parallel to the substrate. On the other hand, sputter particles do not deposit on a plane perpendicular to the substrate or deposit less than on a plane parallel to the substrate. Therefore, by using the above sputtering apparatus, as shown in FIGS. 19(C) and 19(D ), an insulator 406c can be formed on a plane parallel to the substrate, excluding the plane perpendicular to the substrate. ) .

[0308] Note that the vertical distance between the target 100 and the collimator 150, or between the substrate 160 and the collimator 150 may be appropriately changed depending on the film quality to be formed. Therefore, the collimator 150 may include a movable part 151 and a movable part 152 as shown in FIG. 22. The movable part 15 By having 1, the presence or absence of the use of the collimator 150 can be easily selected. Also , by having the movable part 152, the vertical distance between the collimator 150, the substrate 160, and the target 100 can be easily adjusted.

[0309] Also, the long-throw sputtering method can be used. The long-throw sputtering method is a method in which by increasing the vertical distance between the target 100 and the substrate 160, the incident direction of the sputtered particles on the substrate 160 can be made closer to perpendicular. Therefore, even without using the collimator 150, the insulator 406c can be formed on surfaces other than the surface perpendicular to the substrate. Note that the vertical distance between the substrate 160 and the target 100 may be set to 150 mm or more and 500 mm or less. Also, the collimator 150 may be combined with the long-throw sputtering method.

[0310] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be treated.

[0311] Next, as shown in FIGS. 19(E) and 19(F), an insulator 406d is formed. The insulator 406d can be formed by the same process as the insulator 406c.

[0312] Next, as shown in FIGS. 20(A) and 20(B), an insulator that becomes the insulator 412, a conductor that becomes the conductor 404a, and a conductor that becomes the conductor 404b are formed.

[0313] First, an insulator that becomes the insulator 412 is formed on the insulator 410 and the insulator 406d. The The film formation of the insulator that becomes the insulator 412 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0314] Next, by performing the high-density plasma treatment described above, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons etc. from the object to be processed can also be desorbed.

[0315] Next, conductors that become the conductor 404a and the conductor 404b are formed into a film. The conductors that become the conductor 404a, and the conductor 404b can be formed into a film using a sputtering method, a CVD method, an MBE method, or a PLD method, an ALD method, or the like. The conductors that become the conductor 404a and the conductor 40 4b are formed into a film so as to fill the openings formed by the insulator 410 or the like. Therefore, it is preferable to use a CVD method (especially an MCVD method). Also, in order to improve the adhesion of the conductor formed by the MCVD method, in some cases, it is preferable to form a laminated film of the conductor formed by an ALD method or the like and the conductor formed by the CVD method. For example, a laminated film in which titanium nitride and tungsten are formed in this order may be used.

[0316] Subsequently, as shown in FIGS. 20(C) and 20(D), by CMP processing or the like, until the insulator 4 10 is exposed, the conductor 404a, the conductor 404b, the insulator 412, the insulator 406c , and the insulator 406d are removed. At this time, the insulator 410 can also be used as a stopper layer, and the thickness of the insulator 410 may decrease. Therefore, in the completed transistor, the conductors 404a and 404b are made to have a sufficiently low resistance so that the insulator... By designing with a margin in the film thickness of the insulator 410, transistors with little variation can be fabricated. A plurality of them can be created.

[0317] Note that the CMP process may be performed only once or multiple times. When performing the CMP process in multiple steps, it is preferable to perform primary polishing with a high polishing rate first and then finish polishing with a low polishing rate. By combining polishings with different polishing rates in this way, the flatness of the polished surface can be further improved. After performing primary polishing with a high polishing rate, finish polishing with a low polishing rate is preferably performed. By combining polishings with different polishing rates in this way, the flatness of the polished surface can be further improved. After performing primary polishing with a high polishing rate, finish polishing with a low polishing rate is preferably performed.

[0318] Next, a conductor that becomes the conductor 420 is formed. Note that the conductor 420 may have a laminated structure. The formation of the conductor that becomes the conductor 420 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Subsequently, it is processed by a photolithography method or the like to form the conductor 420. Next, a conductor that becomes the conductor 420 is formed. Note that the conductor 420 may have a laminated structure. The formation of the conductor that becomes the conductor 420 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Subsequently, it is processed by a photolithography method or the like to form the conductor 420. Subsequently, it is processed by a photolithography method or the like to form the conductor 420.

[0319] Next, as shown in FIGS. 20(E) and 20(F), an insulator 408 is formed on the insulator 410 and on the conductor 420. The formation of the insulator 408 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Preferably, as the insulator 408, aluminum oxide is formed using plasma containing oxygen, so that oxygen in the plasma can be added as excess oxygen (exO) to the upper surface of the insulator 410. Also, oxygen can be added to the insulator 408 by diffusion of oxygen through the insulator 410. Therefore, at this time, a mixed region containing a large amount of excess oxygen may be formed in the vicinity of the film interface between the insulator 408 and the insulator 410. Next, as shown in FIGS. 20(E) and 20(F), an insulator 408 is formed on the insulator 410 and on the conductor 420. The formation of the insulator 408 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Preferably, as the insulator 408, aluminum oxide is formed using plasma containing oxygen, so that oxygen in the plasma can be added as excess oxygen (exO) to the upper surface of the insulator 410. Preferably, as the insulator 408, aluminum oxide is formed using plasma containing oxygen, so that oxygen in the plasma can be added as excess oxygen (exO) to the upper surface of the insulator 410. Also, oxygen can be added to the insulator 408 by diffusion of oxygen through the insulator 410. Also, oxygen can be added to the insulator 408 by diffusion of oxygen through the insulator 410. Therefore, at this time, a mixed region containing a large amount of excess oxygen may be formed in the vicinity of the film interface between the insulator 408 and the insulator 410. Therefore, at this time, a mixed region containing a large amount of excess oxygen may be formed in the vicinity of the film interface between the insulator 408 and the insulator 410.

[0320] Next, by performing the above-described high-density plasma treatment, carbon, hydrogen, etc. may be desorbed. Also, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be desorbed from the object to be processed.

[0321] Also, at any timing after the formation of the insulator 408, a second heat treatment may be performed. By performing the second heat treatment, the excess oxygen contained in the insulator 410 and the mixed region 414 passes through the insulator 412, the insulator 402, the insulator 406d, the insulator 406c, and the insulator 406a and moves to the semiconductor 406b. Thus, since the excess oxygen moves to the semiconductor 406b, defects (oxygen deficiencies) in the semiconductor 406b can be reduced. .

[0322] Note that the second heat treatment may be performed at a temperature at which the excess oxygen contained in the insulator 410 and the mixed region 414 diffuses to the semiconductor 406b. For example, reference may be made to the description of the first heat treatment. Alternatively, the second heat treatment preferably has a lower temperature than the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. Thereby, it is possible to suppress the excessive release of excess oxygen from the insulator 402 or the like. Note that the second heat treatment may not be performed if it can be combined with the heating during the film formation of each layer by performing an equivalent heat treatment.

[0323] Also, although not particularly shown, openings reaching the conductor 416a and the conductor 416b are formed in the insulator 408 and the insulator 410, and conductors that function as wirings are provided in the respective openings. It may be formed. Further, an opening reaching the conductor 404 may be formed in the insulator 408, and a conductor functioning as a wiring may be formed.

[0324] As described above, the transistor shown in FIG. 10 can be manufactured.

[0325] In addition, in this embodiment, one aspect of the present invention has been described. However, one aspect of the present invention is not limited to these. That is, in this embodiment and other embodiments, since various aspects of the invention are described, one aspect of the present invention is not limited to a specific aspect. For example , as one aspect of the present invention, an example in which an oxide semiconductor is used as a semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or situation, one aspect of the present invention may use silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like.

[0326] As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0327] (Embodiment 6) <Transistor Structure 8> Hereinafter, a transistor having a configuration different from that of FIG. 10 and a method for manufacturing the same will be described with reference to FIGS. 12 and 13. FIG. 12 shows a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention. FIG. 12(A) is a top view. FIG. 12(B) is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 12(A). FIG. 12(C) is a cross-sectional view corresponding to the dashed line A 3-A4 shown in FIG. 12(A). In the top view of FIG. 12(A), for clarity of the drawing ​ Some elements are omitted in the illustration. Further, FIG. 13 shows an enlarged view of the cross-sectional view shown in FIG. 12. That is.

[0328] In this transistor, in FIG. 12(B), the side surface of the insulator 410 has an angle θ greater than 0 degrees and less than 90 degrees with respect to the upper surface of the conductor 416a, and an insulator 406d is formed on the side surface of the insulator 410 via an insulator 406c. The angle θ is 75 degrees or more and less than 90 degrees, preferably 80 degrees or more and less than 90 degrees, and more preferably 85 degrees or more and less than 90 degrees. The regions where the insulators 406c and 406d cover the side surface of the conductor 404 via the insulator 412 are provided thinner than the regions where the insulators 406c and 406d overlap the bottom surface of the conductor 404. For other configurations, refer to the transistor shown in FIG. 10. The side surface of the insulator 410 has an angle θ greater than 0 degrees and less than 90 degrees with respect to the upper surface of the conductor 416a, and an insulator 406d is formed on the side surface of the insulator 410 via an insulator 406c. The angle θ is 75 degrees or more and less than 90 degrees, preferably 80 degrees or more and less than 90 degrees, and more preferably 85 degrees or more and less than 90 degrees. That is good. In addition, the insulators 406c and 406d cover the side surface of the conductor 404 via the insulator 412. The region where the insulators 406c and 406d cover the side surface of the conductor 404 via the insulator 412 is thinner than the region where the insulators 406c and 406d overlap the bottom surface of the conductor 404. For other configurations, refer to the transistor shown in FIG. 10. That is.

[0329] In addition, t1 is larger than L1, and L1 / t1 may be less than 1. Either one of the insulators 406c or 406d may form a thinner region covering the side surface of the insulator 410. That is good. In addition, either one of the insulators 406c or 406d may be formed in the region covering the side surface of the insulator 410, and the other may not be provided. That is good.

[0330] The transistors in the present embodiment shown in FIGS. 13(A) and (B) show an enlarged view of the opening provided in the insulator 410. The height of the upper surface of the insulator 406d may be approximately the same as the upper surfaces of the conductors 416a and 416b. The upper surface of the insulator 406d is in the region where the insulator 406d overlaps the bottom surfaces of the conductors 404a and 404b. The height of the upper surface of the insulator 406d may be approximately the same as the upper surfaces of the conductors 416a and 416b. In addition, the upper surface of the insulator 406d is in the region where the insulator 406d overlaps the bottom surfaces of the conductors 404a and 404b. That is good. , make it the surface close to the conductor 404a. Ideally, as shown in Fig. 13(A), the insulator 40 The upper surface of 6d is preferably at the same height as the upper surfaces of the conductor 416a and the conductor 416b .

[0331] Also, the height of the upper surface of the insulator 406c is preferably approximately the same as the height of the interface between the semiconductor 406b and the conductors 416a and 416b. Note that the upper surface of the insulator 406c refers to the surface close to the conductor 404a in the region where the insulator 406c overlaps the bottom surfaces of the conductors 404a and 404b. Ideally, the upper surface of the insulator 406c is preferably at the same height as the interface between the semiconductor 40 6b and the conductors 416a and 416b. However, the insulator 406c only needs to fill at least the over-etched portion of the semiconductor 406b. As shown in Fig. 13(B), the upper surface of the insulator 406c may be above the interface between the semiconductor 40 6b and the conductors 416a and 416b . . However, as long as the insulator 406c fills at least the over-etched portion of the semiconductor 406b, as shown in Fig. 13(B), the upper surface of the insulator 406c may be above the interface between the semiconductor 40 6b and the conductors 416a and 416b and it doesn't matter .

[0332] Also, in the transistor of this embodiment, a configuration in which two layers of the insulator 406c and the insulator 406d are provided on the semiconductor 406b is shown, but it is not limited to this, and a stacked structure of three or more layers may be used .

[0333] <Fabrication method of transistor 8> First, perform the steps in the same manner up to Fig. 18 shown in Embodiment 5

[0334] Next, form the side surface of the insulator 410 to have an angle θ greater than 0 degrees and less than 90 degrees with respect to the upper surface of the conductor 416a. Subsequently, use the film-forming apparatus described in Embodiment 5 Then, insulators 406c and 406d are formed. At this time, for example, the smaller the angle θ, the higher the probability that sputtering particles are deposited, and on the side surface of the insulator 410, the insulators 40 6c and 406d are formed thickly. Also, the larger the angle θ, the thinner the insulators 406c and 406d are formed on the side surface of the insulator 410. Therefore, the film thicknesses of the insulators 406c and 406d formed on the side surface of the insulator 41 0 can be adjusted by the angle θ. That is, L1, which is the width of the offset region to be formed, can be made smaller. t1 is larger than L1, and L1 / t1 is less than 1. The subsequent steps may be performed in the same manner as the steps in the method 1 for manufacturing a transistor shown in Embodiment 5. The transistor shown in FIG. 12 can be manufactured as described above. As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. (Embodiment 7)

[0335] <Transistor Structures 9 and 10> Hereinafter, a transistor having a configuration different from that in FIG. 10 and a method for manufacturing the same will be described with reference to FIGS. 14 and

[0336] 15. FIGS. 14 and 15 show a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention.

[0337] The transistor shown in FIGS. 14 and 15 will be described. Note that FIGS. 14(A) and 15 (A) are top views. FIG. 14(B) corresponds to the dashed line A1 - A2 shown in FIG. 14(A).

[0338] (Embodiment 7) <Transistor Structures 9 and 10> Hereinafter, a transistor having a configuration different from that in FIG. 10 and a method for manufacturing the same will be described with reference to FIGS. 14 and 15. FIGS. 14 and 15 show a top view and a cross-sectional view of a semiconductor device according to an aspect of the present invention. The transistor shown in FIGS. 14 and 15 will be described. Note that FIGS. 14(A) and 15

[0339] The transistor shown in FIGS. 14 and 15 will be described. Note that FIGS. 14(A) and 15 (A) are top views. FIG. 14(B) corresponds to the dashed line A1 - A2 shown in FIG. 14(A). It is a cross-sectional view. FIG. 14(C) corresponds to the dashed line A3 - A4 shown in FIG. 14(A). It is a cross-sectional view. In the top view of FIG. 14(A), some elements are omitted for clarity of the figure and shown in the figure.

[0340] Also, FIG. 15(B) is a cross-sectional view corresponding to the dashed line A1 - A2 shown in FIG. 15(A). FIG. 15(C) is a cross-sectional view corresponding to the dashed line A3 - A4 shown in FIG. 15(A). Note that in the top view of FIG. 15(A), some elements are omitted for clarity of the figure and shown in the figure.

[0341] The transistors shown in FIGS. 14 and 15 have an insulator 406c2 (insulator 406c in FIG. 4), an insulator 406d2 (insulator 406d in FIG. 4), an insulator 412, a conductor 404a, and a conductor 404b formed also in a partial region on the upper surface of the insulator 410. Other configurations refer to the transistors shown in FIG. 10 or FIG. 12.

[0342] In the transistors shown in FIGS. 14 and 15, a part of the conductor 404a that functions as a gate electrode and the conductor 404b may also have a function as a wiring. That is, via the insulator 406 c2 (insulator 406c in FIG. 4), the insulator 406d2 (insulator 406d in FIG. 4), and the insulator 412, the conductor 404a and the conductor 404 b formed on the insulator 410 correspond to the conductor 420 in the transistor structure 1. Therefore, in this structure , t2 is defined as the vertical distance between the conductor 416a or the conductor 416b and the conductor 404a on the insulator 410 . Note also that the insulator 406c2 (insulator 406c in FIG. 4), the insulator 406d2 (insulator 406d in FIG. 4), the insulator 412, the conductor 404a, and the conductor 4 Since 04b is formed simultaneously, between the upper surface of the insulator 410 and the conductor 404a formed on the insulator 410, the insulators 406c, 406d2 (insulator 406d in FIG. 4 ) and the insulator 412 ...

Claims

1. A semiconductor device having a first transistor and a second transistor, comprising: a substrate; a first insulator above the substrate; a channel formation region of the first transistor above the first insulator; a second insulator above the channel formation region of the first transistor; a first conductor above the second insulator; a third insulator above the first conductor and the second insulator; a layer including a channel formation region of the second transistor above the third insulator; a second conductor having a region overlapping with the layer including the channel formation region of the second transistor; a third conductor and a fourth conductor having regions in contact with an upper surface of the layer including the channel formation region of the second transistor; a fourth insulator above the third conductor and above the fourth conductor; a fifth conductor above the fourth insulator, wherein the channel formation region of the first transistor contains silicon, the first conductor functions as a gate electrode of the first transistor, the second conductor functions as a gate electrode of the second transistor, the channel formation region of the second transistor has an oxide semiconductor containing indium, the third conductor functions as one of a source electrode and a drain electrode of the second transistor, the fourth conductor functions as the other of the source electrode and the drain electrode of the second transistor, the fifth conductor functions as a first electrode of a capacitor, in a cross-sectional view in a channel length direction of the second transistor, the first conductor does not overlap with the second conductor, the third conductor is electrically connected to one of a source and a drain of the first transistor, the fourth conductor is electrically connected to the first conductor. A semiconductor device.

2. A semiconductor device having a first transistor and a second transistor, comprising: a substrate; a first insulator above the substrate; a channel formation region of the first transistor above the first insulator; a second insulator above the channel formation region of the first transistor; a first conductor above the second insulator; a third insulator above the first conductor and the second insulator; a layer including a channel formation region of the second transistor above the third insulator; a second conductor having a region overlapping with the layer including the channel formation region of the second transistor; A third conductor and a fourth conductor having a region in contact with the upper surface of a layer including the channel formation region of the second transistor; A fourth insulator above the third conductor and above the fourth conductor; A fifth conductor above the fourth insulator, and having: The channel formation region of the first transistor contains silicon; The first conductor functions as a gate electrode of the first transistor; The second conductor functions as a gate electrode of the second transistor; The channel formation region of the second transistor has an oxide semiconductor containing indium; The third conductor functions as one of the source electrode and the drain electrode of the second transistor; The fourth conductor functions as the other of the source electrode and the drain electrode of the second transistor; The fifth conductor functions as a first electrode of a capacitor; In a cross-sectional view in the channel length direction of the second transistor, the first conductor does not overlap with the second conductor; The third conductor is electrically connected to one of the source and the drain of the first transistor; The fourth conductor is located in the same layer as the second conductor and is electrically connected to the first conductor via a sixth conductor containing the same material as the second conductor. A semiconductor device.

3. In Claim 1 or Claim 2, The oxide semiconductor contains indium, gallium, and zinc. A semiconductor device.

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