Semiconductor device

Abstract

To provide a novel semiconductor device, low power consumption semiconductor device, or a semiconductor device capable of shrinking its area.SOLUTION: A semiconductor device includes: an internal circuit; an input / output terminal; a signal line; a power supply line; a resister; a first transistor; and a control signal generation circuit. The internal circuit is connected to the input / output terminal via the signal line. A first terminal of the first transistor is electrically connected to the power supply line. A second terminal of the first transistor is connected to a first terminal of the resister. A second terminal of the resister is electrically connected to the signal line. The control signal generation circuit is electrically connected to the gate of the first transistor, and the resister and the first transistor include an oxide semiconductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a circuit board, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. is related to an article, a method, or a manufacturing method. Or, one aspect of the present invention is related to a process, a machine, a manufacture, or a composition of matter. Or, one aspect of the present invention is related to a semiconductor device, a display device, a light emitting device, a power storage device, a storage device, an imaging device, a driving method thereof, or a manufacturing method thereof.

Background Art

[0003] In semiconductor devices such as integrated circuits (ICs) and display devices, a pull-up (or pull-down) resistor is used to prevent the input / output terminals of a circuit from becoming indefinite. For example, a technique of using a gate poly silicon as a pull-up (or pull-down) resistor of a CMOS inverter has been disclosed (see Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] For example, in a CMOS circuit, the resistance value of a pull-up (or pull-down) resistor is several kiloohms Values in the order of several megaohms, and in some cases, extremely large values, may be required. As shown in Patent Document 1 described above, when polysilicon is used as a resistor in a gate array semiconductor circuit device, there is a problem that the area occupied by the polysilicon increases, resulting in an increase in the cell size.

[0006] In addition, in an IC having a pull-up (or pull-down) resistor, a current of about several μA continuously flows while signals are being input and output to and from the input / output terminals, resulting in a problem of increased power consumption.

[0007] Also, as described above, an IC having a pull-up (or pull-down) resistor has a large power consumption. Therefore, in order to suppress this power consumption and make the IC have lower power consumption, a switch may be provided to cut off the pull-up (or pull-down) resistor after the IC starts stable operation. The switch can mainly be formed by a transistor. However, even when the transistor is turned off to cut off the switch, an off-leakage current flows, resulting in an increase in power consumption due to this.

[0008] Therefore, one aspect of the present invention aims to provide a novel semiconductor device, circuit board, or electronic device. Or, one aspect of the present invention aims to provide a configuration that can reduce the layout area or realize it. Or, one aspect of the present invention aims to provide a configuration that can prevent current from constantly flowing or realize it. Or, one aspect of the present invention aims to provide a configuration that can reduce power consumption or realize it. Or, one aspect of the present invention aims to prevent through-current from occurring ​​​​​​​​​​​ One of the problems is to shorten the time required or to provide a configuration that enables it.

[0009] Note that one aspect of the present invention does not necessarily have to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not preclude the existence of other problems. Other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problem

[0010] One aspect of the present invention includes an internal circuit, input / output terminals, signal lines, power supply lines, a resistance portion, a first transistor, and a control signal generation circuit. The internal circuit is electrically connected to the input / output terminals via the signal lines. The first terminal of the first transistor is electrically connected to the power supply lines, the second terminal of the first transistor is electrically connected to the first terminal of the resistance portion, and the second terminal of the resistance portion is electrically connected to the signal lines. The control signal generation circuit is electrically connected to the gate of the first transistor. The resistance portion and the first transistor are semiconductor devices having an oxide semiconductor.

[0011] One aspect of the present invention includes an internal circuit, input / output terminals, signal lines, power supply lines, a resistance portion, a first transistor, and a control signal generation circuit. The internal circuit is electrically connected to the input / output terminals via the signal lines. The first terminal of the first transistor is electrically connected to the second terminal of the resistance portion, the second terminal of the first transistor is electrically connected to the signal lines, and the ​​The first terminal is electrically connected to a power supply line, and the control signal generation circuit is electrically connected to the gate of the first transistor. The resistor portion and the first transistor are semiconductor devices having an oxide semiconductor.

[0012] One aspect of the present invention includes an internal circuit, input / output terminals, signal lines, a power supply line, a first transistor, and a control signal generation circuit. The internal circuit is electrically connected to the input / output terminals via the signal lines. The first terminal of the first transistor is electrically connected to the power supply line. The second terminal of the first transistor is electrically connected to the signal lines. The control signal generation circuit is electrically connected to the gate of the first transistor. The first transistor is a semiconductor device having an oxide semiconductor.

[0013] Another aspect of the present invention includes the semiconductor device described above and a second transistor. The control signal generation circuit is electrically connected to the first terminal of the second transistor. The second terminal of the second transistor is electrically connected to the gate of the first transistor. The second transistor is a semiconductor device having an oxide semiconductor.

[0014] Another aspect of the present invention includes the semiconductor device described above and a capacitor. The capacitor is electrically connected to the second terminal of the second transistor and the gate of the first transistor.

[0015] The control signal generation circuit and the gate of the second transistor may be electrically connected. Also, the gate of the second transistor may be connected to another wiring.

[0016] ​​​​​​​​​​​​Also, one aspect of the present invention is a circuit board having the semiconductor device described above and a printed circuit board. It is.

[0017] Also, one aspect of the present invention is an electronic device having the semiconductor device described above or the circuit board described above, a display unit, a microphone, a speaker, or an operation key.

[0018] In the present specification and the like, it is preferable that the resistance portion uses a layer having an oxide semiconductor as a resistance. Preferably.

Advantages of the Invention

[0019] One aspect of the present invention can provide a novel semiconductor device, circuit board, or electronic device. Or, one aspect of the present invention can provide a configuration that reduces the layout area or enables it. Or, one aspect of the present invention can provide a configuration that prevents a steady current from occurring or enables it. Or, one aspect of the present invention can provide a configuration that reduces power consumption or enables it. Or, one aspect of the present invention can provide a configuration that shortens the time during which a through current occurs or enables it. Or, one aspect of the present invention can provide a configuration that shortens the time during which a through current occurs or enables it. It is possible to provide a configuration that can be realized.

[0020] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings and claims, etc.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is as follows Not limited to the description in the embodiments, it can be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In the drawings, the size, thickness of the film (layer), or region may be exaggerated for clarity.

[0024] In this specification, the notations "film" and "layer" can be interchanged with each other.

[0025] Also, voltage often indicates the potential difference between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). Therefore, it is possible to rephrase voltage as potential. Generally, potential (voltage) is relative and is determined by the relative magnitude from the reference potential. Therefore, even when described as "ground potential," etc., the potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, an intermediate potential in a circuit may be the "ground potential." In that case, positive and negative potentials are defined based on that potential.

[0026] In this specification, etc., the high power supply potential VDD (hereinafter, also simply referred to as "VDD" or "H potential") indicates a power supply potential with a higher potential than the low power supply potential VSS (hereinafter, also simply referred to as "VSS" or "L potential"). Also, the low power supply potential VSS indicates a power supply potential with a lower potential than the high power supply potential VDD. Also, the ground potential is used as VDD or VSS. ​​​​​​​​​​​​It can also be done. For example, when VDD is at the ground potential, VSS is at a potential lower than the ground potential ; when VSS is at the ground potential, VDD is at a potential higher than the ground potential.

[0027] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described accordingly. Also, the ordinal numbers described in this specification etc. may not match the ordinal numbers used to specify an aspect of the present invention.

[0028] In addition, one aspect of the present invention includes, in addition to integrated circuits, all devices such as display devices, RF tags, and imaging devices within its scope. Also, display devices include liquid crystal display devices, light-emitting devices having light-emitting elements represented by organic light-emitting elements in each pixel, electronic paper, DMD (Digital M icromirror Device), PDP (Plasma Display Pa nel), FED (Field Emission Display), etc., and display devices having integrated circuits are included within its scope.

[0029] Note that when explaining the configuration of the invention using drawings, the same reference numerals may be commonly used between different drawings to indicate the same thing.

[0030] Also, in this specification etc., in the figures or text described in a certain embodiment, it is possible to extract a part of it to constitute an aspect of the invention. Therefore, when a figure or text describing a part is described, the content obtained by extracting a part of that figure or text is also disclosed as an aspect of the invention and constitutes an aspect of the invention. It is assumed to be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, one or more active elements (such as transistors), wirings, passive elements (such as capacitive elements), conductive layers , insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described in the drawings or text, and it is possible to extract a part of them to form one aspect of the invention. For example, it is assumed to be possible to extract M (M is an integer, M < N) circuit elements (such as transistors and capacitive elements) from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitive elements) to form one aspect of the invention. As another example, from the text "A has B, C, D, E or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E and F", or "A has B, C, D and E" can be formed. That is, it is possible to form one aspect of the invention. In addition, in this specification, etc., when at least one specific example is described in the drawings or text described in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of the specific example. Therefore, when at least one specific example is described in the drawings or text described in a certain embodiment, the upper concept of the specific example is also disclosed as one aspect of the invention and can form one aspect of the invention. And it can be said that one aspect of the invention is clear. Moreover, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is

[0031] In addition, in this specification, etc., when at least one specific example is described in the drawings or text described in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of the specific example. Therefore, when at least one specific example is described in the drawings or text described in a certain embodiment, the upper concept of the specific example is also disclosed as one aspect of the invention and can form one aspect of the invention. And it can be said that one aspect of the invention is clear. And, in this specification, etc., when at least one specific example is described in the drawings or text described in a certain embodiment, the upper concept of the specific example is also disclosed as one aspect of the invention and can form one aspect of the invention. And it can be said that one aspect of the invention is clear. In addition, in this specification, etc., when at least one specific example is described in the drawings or text described in a certain embodiment, the upper concept of the specific example is also disclosed as one aspect of the invention and can form one aspect of the invention. And it can be said that one aspect of the invention is clear. Moreover, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is

[0032] In addition, in this specification, etc., at least the content described in the drawings (even a part of the drawings) and is disclosed as one aspect of the invention, and it is possible to constitute one aspect of the invention That is, for a certain content, if it is described in the figure, even if it is not described in the text, that content is disclosed as one aspect of the invention and it is possible to constitute one aspect of the invention. Similarly, for a figure obtained by extracting a part of the figure, it is also disclosed as one aspect of the invention and it is possible to constitute one aspect of the invention. And it can be said that one aspect of that invention is clear.

[0033] Further, for content not defined in the text or drawings in the specification, it is possible to constitute one aspect of the invention that defines excluding that content. Or, for a certain value, when a numerical range indicated by an upper limit value and a lower limit value etc. is described, by arbitrarily narrowing that range or by excluding one point within that range, it is possible to define one aspect of the invention excluding a part of that range. By these, for example, it is possible to define that the prior art does not fall within the technical scope of one aspect of the present invention.

[0034] Further, in this specification etc., for all terminals of active elements (such as transistors), passive elements (such as capacitor elements etc.), even if the connection destination is not specified, a person skilled in the art may be able to constitute one aspect of the invention. That is, even if the connection destination is not specified, it can be said that one aspect of the invention is clear. And when the content with the connection destination specified is described in this specification etc., it may be possible to determine that one aspect of the invention without specifying the connection destination is described in this specification etc. In particular, when there are a plurality of candidates for the connection destination of the terminal, There is no need to limit the connection destination of the terminal to a specific location. Therefore, for some terminals of active elements (such as transistors), passive elements (such as capacitive elements), etc., it may be possible to constitute an aspect of the invention by specifying their connection destination. Furthermore, in this specification and the like, for a certain circuit, if at least the connection destination is specified, a person skilled in the art may be able to identify the invention. Or, for a certain circuit, if at least the function is specified, a person skilled in the art may be able to identify the invention. In other words, it can be said that if the function is specified, an aspect of the invention is clear. And, in some cases, it may be possible to determine that an aspect of the invention with the function specified is described in this specification and the like. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, it is disclosed as an aspect of the invention and can constitute an aspect of the invention. Or, for a certain circuit, even if the connection destination is not specified, if the function is specified, it is disclosed as an aspect of the invention and can constitute an aspect of the invention.

[0035] Also, in this specification and the like, when it is explicitly described that X and Y are connected, it is disclosed in this specification and the like that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text. Other connection relationships than those shown in the figure or the text are also regarded as those described in the figure or the text.

[0036]

[0037] ​​​​​​​​​​​​​Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0038] As an example of the case where X and Y are directly connected, an element (e.g., switch, transistor, capacitor, inductor, resistor, diode , display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y is not connected between X and Y, and X and Y are connected without an element (e.g., switch, transistor, capacitor , inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y. That is, it is the case where X and Y are connected without passing through an element (e.g., switch, transistor, capacitor , inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y.

[0039] As an example of the case where X and Y are electrically connected, one or more elements (e.g., switch, transistor, capacitor , inductor, resistor, diode, display element, light-emitting element, load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether to allow current to flow. Or, the switch has a function of selecting and switching the path through which current flows. Note that when X and Y are electrically connected, it includes the case where X and Y are directly connected. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether to allow current to flow. Or, the switch has a function of selecting and switching the path through which current flows. When X and Y are electrically connected, it includes the case where X and Y are directly connected. When X and Y are electrically connected, it includes the case where X and Y are directly connected. shall include the case where X and Y are directly connected.

[0040] As an example of the case where X and Y are functionally connected, a circuit (e.g., logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion circuit, etc.) that enables the functional connection between X and Y Conversion circuits (such as DA conversion circuits, AD conversion circuits, gamma correction circuits), potential level conversion circuits (power source circuits (such as boost circuits, buck circuits), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, etc., operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected by one or more between X and Y. As an example, even if there is another circuit between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When X and Y are functionally connected, it includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0041] When it is explicitly described that X and Y are electrically connected, the case where X and Y are electrically connected (that is, connected with another element or another circuit sandwiched between X and Y ), the case where X and Y are functionally connected (that is, functionally connected with another circuit sandwiched between X and Y ), and the case where X and Y are directly connected (that is, connected without another element or another circuit sandwiched between X and Y ) are disclosed in this specification and the like. That is, when it is explicitly described as being electrically connected, it is considered that the same content as when it is only explicitly described as being connected is disclosed in this specification and the like. ) When it is explicitly described as being electrically connected, it is considered that the same content as when it is only explicitly described as being connected is disclosed in this specification and the like.

[0042] For example, the source (or the first terminal, etc.) of a transistor is connected via Z1 (or ​is electrically connected to X without going through (), the drain of the transistor (or the second terminal, etc.) when the () is electrically connected to Y with or without going through Z2, or the transistor source of the () (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X, and the drain of the transistor (or the second terminal, etc.) is that of Z2 when directly connected to a part and another part of Z2 is directly connected to Y, it can be expressed as follows can be expressed as follows

[0043] For example, "X, Y, the source of the transistor (or the first terminal, etc.), and the drain (or the second terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are in the order of electrically connected." It can be expressed like this. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order." It can be expressed like this. Or, "X is electrically connected to Y through the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.), and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order." It can be expressed like this. By using an expression method similar to these examples to specify the connection order in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or By stipulating in this way about the connection order in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor It is possible to determine the technical scope by distinguishing (such as the second terminal, etc.).

[0044] Or, as another expression method, for example, "the source of the transistor (or the first terminal, etc. ) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path, and the second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) via the transistor, and the first connection path is the path via Z1, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path, and the third connection path is the path via Z2. " It can be expressed as. Or, "the source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least the first connection path, and the first connection path does not have the second connection path, and the second connection path has a connection path via the transistor, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least the third connection path, and the third connection path does not have the second connection path. " It can be expressed as. Or, "the source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least the first electrical path, and the first electrical path does not have the second electrical path, and the second electrical path is the electrical path from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.), and the transistor ​​​​​​​​​​​​​​The drain (or the second terminal, etc.) is electrically connected to Y through at least a third electrical path, and the third electrical path has no fourth electrical path and the fourth electrical path is an electrical path from the drain (or the second terminal, etc.) of the transistor to the source (or the first terminal, etc.) of the transistor. It can be expressed as By defining the connection paths in the circuit configuration using an expression method similar to these examples, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0045] Note that even if components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of a plurality of components For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of a plurality of components within its scope.

[0046] (Embodiment 1) In this embodiment, an example of a semiconductor device according to one aspect of the present invention will be described. The semiconductor device according to one aspect of the present invention includes an internal circuit, input / output terminals for inputting / outputting signals to / from the internal circuit, and and electrically connects the input / output terminals to the internal circuit through a plurality of wirings.

[0047] (Embodiment 1) In this embodiment, an example of a semiconductor device according to one aspect of the present invention will be described. The semiconductor device according to one aspect of the present invention has an internal circuit, input / output terminals for inputting / outputting signals to / from the internal circuit, In a circuit having, a pull-up ( or pull-down) resistor is provided to prevent the input / output terminals of the circuit from entering an indeterminate state.

[0048] <Configuration Example of Semiconductor Device> FIG. 1(A) is a circuit diagram of a semiconductor device 10 according to one aspect of the present invention. As shown in FIG. 1(A), the semiconductor device 10 includes a transistor 11, a resistor section 12, an input / output terminal 13, an internal circuit 1 4, a power supply line 15, a signal line 16, and a control signal generation circuit 17.

[0049] In the semiconductor device 10, the first terminal of the transistor 11 is connected to the power supply line 15, and the second terminal of the transistor 11 is connected to the first terminal of the resistor section 12. Also, the gate of the transistor 11 is connected to the control signal generation circuit 17. The second terminal of the resistor section 12 is connected to the signal line 16, and the input / output terminal 13 is connected to the internal circuit 14 via the signal line 16.

[0050] The input / output terminal 13 is a terminal for inputting a signal (high-level signal, low-level signal, or analog signal) to the internal circuit 14 or outputting a signal (high-level signal, low-level signal, or analog signal) from the internal circuit 14. The control signal generation circuit 17 is a circuit that sends a signal to the gate of the transistor 11 to control the on / off state of the transistor 11.

[0051] The power supply line 15 can be a high-potential power supply line VDD that provides a high-level (H) potential, or a low-potential (L) potential power supply line VSS (VSS < VDD). When the power supply line 15 is VDD, the resistor section 12 in the semiconductor device 10 is a pull-up resistor and ​​functions. When the power line 15 is VSS, the resistance part 12 in the semiconductor device 10 functions as a pull-down resistor.

[0052] Without a pull-up (or pull-down) resistor, when no external circuit or negative load device is connected to the input / output terminal 13, or when no signal is input / output to the input / output terminal 13, the input / output terminal 13 will be in an indeterminate state (a state that is neither H nor L. Or a state that is H or L or unknown).). When the input / output terminal 13 is in an indeterminate state, the internal circuit 14

[0053] may malfunction. Therefore, by providing a pull-up (or pull-down) resistor as shown in Fig. 1(A), the input / output terminal 13 can be fixed to H or L, thereby preventing malfunction of the internal circuit.

[0054] The transistor 11 is on when no signal (high-level signal, low-level signal or analog signal) is input / output to the input / output terminal 13. Therefore, when the power line 15 is V DD, when no signal is input to the input / output terminal 13, the input / output terminal will be held at a high level. Also, when the power line 15 is VSS, when no signal is input / output to the input / output terminal 13, the input / output terminal will be held at a low level.

[0055] The transistor 11 turns off after a signal (high-level signal, low-level signal or analog signal) is input to the input / output terminal 13 and the internal circuit 14 starts up normally. Thereby, the flow of current between the power line 15 and the signal line 16 can be stopped. Therefore, it is possible to prevent a current from being constantly consumed in the resistance portion 12 and reduce the power consumption of the semiconductor device 10.

[0056] The transistor 11 and the resistance portion 12 include an oxide semiconductor. The oxide semiconductor is a wide-gap semiconductor, and the effective mass of holes is also very large. Further, by reducing the impurities contained in the oxide semiconductor as much as possible and further reducing the oxygen deficiency, the carrier concentration of the oxide semiconductor can be decreased. By using such a highly purified intrinsic oxide semiconductor for a transistor, a transistor with a very small off-current can be formed. Thereby, by using the oxide semiconductor for the transistor 11, the power consumption of the semiconductor device 10 can be reduced. Also, when used for the resistance portion 12, since the oxide semiconductor as described above has a very high resistance, the area required to obtain the required resistance value becomes small. That is, by using the oxide semiconductor for the resistance portion 12, the layout area of the resistance portion 12 can be reduced.

[0057] Also, the transistor and the resistance portion using the oxide semiconductor can easily form a stacked structure. For example, they can be formed by stacking with a transistor using silicon or the like. Therefore, for example, like the semiconductor device 10 according to one aspect of the present invention, the transistor 11 and the resistance portion 12 are formed using the oxide semiconductor, and the internal circuit 14 is formed by a transistor using silicon or the like, so that the transistor 11 and the resistance portion 12 and the internal circuit 14 can be stacked and formed, and thus the layout area can be reduced. ​​​​​​​​​​​​​​​It can be made. Further, the transistor 11 and the resistance part 12 may be laminated and formed. It may be.

[0058] Further, the resistance part having an oxide semiconductor that functions as a resistance layer and a conductive layer in contact with the oxide semiconductor may have a non-linear resistance. The resistance part to be used may have a non-linear resistance.

[0059] FIG. 1(B) is a circuit diagram of a semiconductor device 20 according to an aspect of the present invention. The semiconductor device 20 has a configuration in which the connection of the transistor 11 and the resistance part 12 in the semiconductor device 10 shown in FIG. 1(A) is reversed. The semiconductor device 20 includes a transistor 21, a resistance part 22, an input / output terminal 23, an internal circuit 24, a power supply line 25, a signal line 26, and a control signal generation circuit 27. In the semiconductor device 20, the first terminal of the transistor 21 is connected to the second terminal of the resistance part 22, and the second terminal of the transistor 21 is connected to the signal line 26. Further, the gate of the transistor 21 is connected to the control signal generation circuit 27. The first terminal of the resistance part 22 is connected to the power supply line 25, and the input / output terminal 23 is connected to the internal circuit 24 via the signal line 26. In the semiconductor device 20, the first terminal of the transistor 21 is connected to the second terminal of the resistance part 22, and the second terminal of the transistor 21 is connected to the signal line 26. Also, the gate of the transistor 21 is connected to the control signal generation circuit 27. The first terminal of the resistance part 22 is connected to the power supply line 25, and the input / output terminal 23 is connected to the internal circuit 24 via the signal line 26. Output terminal 23 and an internal circuit 24, a power supply line 25, a signal line 26, and a control signal generation circuit 27. It has.

[0060] In the semiconductor device 20, the first terminal of the transistor 21 is connected to the second terminal of the resistance part 22, and the second terminal of the transistor 21 is connected to the signal line 26. Continued, the second terminal of the transistor 21 is connected to the signal line 26. Also, the transistor 21 gates are connected to the control signal generation circuit 27. The first terminal of the resistance part 22 is the power supply line 25 is connected, and the input / output terminal 23 is connected to the internal circuit 24 via the signal line 26.

[0061] FIG. 1(C) is a circuit diagram of a semiconductor device 30 according to an aspect of the present invention. The semiconductor device 30 includes a transistor 31, an input / output terminal 33, an internal circuit 34, a power supply line 35, a signal line 36, and a control signal generation circuit 37. In the semiconductor device 30, the transistor 31, the input / output terminal 33, the internal circuit 34, the power supply line 35, the signal line 36 And a control signal generation circuit 37.

[0062] The semiconductor device 30 has a configuration in which the resistance part 12 is absent in the semiconductor device 10 of FIG. 1(A). That is, the semiconductor device 30 in FIG. 1(C) has a configuration with only the transistor 31 between the power supply line 35 and the signal line 36. That is, in the semiconductor device 30 of FIG. 1(C), between the power supply line 35 and the signal line 36, there is only the configuration of the transistor 31.

[0063] In the semiconductor device 30, the first terminal of the transistor 31 is connected to the power supply line 35, and the second terminal of the transistor 31 is connected to the signal line 36. Also, the gate of the transistor 31 is connected to the control signal generation circuit 37. The input / output terminal 33 is connected to the internal circuit 34 via the signal line 36.

[0064] The semiconductor device 30 is configured such that there is no resistance portion between the power supply line 35 and the signal line 36. However, the channel resistance in the on-state of the transistor 31 can be used instead of the resistance portion, and it also functions as a pull-up (or pull-down) resistance. In particular, when an oxide semiconductor is used for the transistor 31, it is preferable because it is easy to form a high channel resistance and the off-current is very small.

[0065] FIG. 1(D) is a circuit diagram of a semiconductor device 40 according to an aspect of the present invention. The semiconductor device 40 includes a resistance portion 42, an input / output terminal 43, an internal circuit 44, a power supply line 45, and a signal line 46.

[0066] The semiconductor device 40 has a configuration in which the transistor 11 and the control signal generation circuit 17 are absent in the semiconductor device 10 of FIG. 1(A). That is, the semiconductor device 40 in FIG. 1(D) has a configuration with only the resistance portion 42 between the power supply line 4

[0067] In the semiconductor device 40, the first terminal of the resistance portion 42 is connected to the power supply line 45, and the second terminal of the resistance portion 42 is connected to the signal line 46. The input / output terminal 43 is connected to the internal circuit 44 via the signal line 46.

[0068] The semiconductor device 40 is configured such that there is no transistor between the power line 45 and the signal line 46. In this way, even if no transistor is formed between the power line 45 and the signal line 46, since there is the resistor portion 42, it is possible to suppress the signal line 46 from becoming an indeterminate state. However, in that case, while the semiconductor device 40 is operating, a current constantly flows, so the power consumption of the semiconductor device 40 increases, but since the area for forming the transistor becomes unnecessary, the layout can be made smaller.

[0069] Also, in the semiconductor device 10 shown in FIG. 1(A), a plurality of the transistors 11 and resistor portions 12 can be used respectively. For example, as in the semiconductor device 70 shown in FIG. 2(A), a configuration using two resistor portions 12 may be adopted. Note that a configuration using three or more resistor portions 12 may also be used. Further, as in the semiconductor device 80 shown in FIG. 2(B), a configuration using two transistors 11 may be adopted. Note that a configuration using three or more transistors 11 may also be used. Also, the transistors 11 and the resistor portions 12 do not need to be connected alternately, and a configuration in which the same ones are connected continuously may be adopted.

[0070] Also, as an example of the internal circuit 14 in the semiconductor device 10 shown in FIG. 1(A), a gate driver circuit can be used as shown in FIG. 3(A), and a clock generator or the like can be used as shown in FIG. 3(B). Moreover, not limited to these, various circuits can be used.

[0071] FIG. 4(A) is a circuit diagram of a semiconductor device 50 according to an aspect of the present invention. The semiconductor device 50 has, in the configuration of the semiconductor device 10 of FIG. 1(A), the gate of the transistor 11 and the generation of the control signal Between the circuit 17, there is a configuration in which a transistor is further provided.

[0072] The semiconductor device 50 includes a transistor 51, a resistor section 52, input / output terminals 53, an internal circuit 5 4, a power supply line 55, a signal line 56, a control signal generation circuit 57, and a transistor 58. It has.

[0073] In the semiconductor device 50, the first terminal of the transistor 51 is connected to the power supply line 55, and the second terminal of the transistor 51 is connected to the first terminal of the resistor section 52, and the second terminal of the resistor section 52 is connected to the signal line 56. Also, the gate of the transistor 51 is connected to the first terminal of the transistor 58, and the second terminal of the transistor 58 is connected to the control signal generation circuit 57. Also, the gate of the transistor 58 is connected to the control signal generation circuit 57. The input / output terminals 53 are connected to the internal circuit 54 via the signal line 56. Also, at the connection point between the gate of the transistor 51 and the first terminal of the transistor 58, a floating node (FN) is formed.

[0074] The transistor 58, like the transistor 51 and the resistor section 52, has an oxide semiconductor. A transistor having an oxide semiconductor has a very small off-current. Therefore, in the semiconductor device 50, by switching the on / off of the transistor 58, the voltage for operating the transistor 51 can be held at the FN. Therefore, the period for holding the on state or off state of the transistor 51 can stop the control signal generation circuit 57. With this configuration, the power consumption of the semiconductor device 50 can be reduced. With this configuration, the power consumption of the semiconductor device 50 can be reduced.

[0075] In the semiconductor device 50 shown in Fig. 4(A), the gate of the transistor 58 is connected to the control signal generation circuit 57. However, the gate of the transistor 58 may not be connected to the control signal generation circuit 57. That is, the gate of the transistor 58 can be configured to be connected to other wiring or circuits, etc.

[0076] Fig. 4(B) is a circuit diagram of a semiconductor device 60 according to an aspect of the present invention. The semiconductor device 60 has a configuration in which a capacitor element is further connected to a floating node formed at the connection point between the gate of the transistor 51 and the transistor 58 in the configuration of the semiconductor device 50 of Fig. 4(A).

[0077] The semiconductor device 60 includes a transistor 61, a resistor section 62, an input / output terminal 63, an internal circuit 6 4, a power supply line 65, a signal line 66, a control signal generation circuit 67, a transistor 68, and a capacitor element 69.

[0078] In the semiconductor device 60, the first terminal of the transistor 61 is connected to the power supply line 65, and the second terminal of the transistor 61 is connected to the first terminal of the resistor section 62, and the second terminal of the resistor section 62 is connected to the signal line 66. Also, the gate of the transistor 61 is connected to the first terminal of the transistor 68 and the capacitor element 69, and the second terminal of the transistor 68 is connected to the control signal generation circuit 67. Also, the gate of the transistor 68 is connected to the control signal generation circuit 67. The input / output terminal 63 is connected to the internal circuit 64 via the signal line 66. Also, a floating node (FN) is formed at the connection point among the gate of the transistor 61, the first terminal of the transistor 68, and the capacitor element 69.

[0079] Similar to the semiconductor device 50, the semiconductor device 60 switches the on / off state of the transistor 68 to hold the voltage for operating the transistor 61 at FN. Furthermore, since the capacitor element 69 is connected to FN in the semiconductor device 60, it is easier to hold the voltage at FN. Therefore, it becomes easier to hold the on-state or off-state of the transistor 61, and the control signal generation circuit 67 can be stopped, thus reducing the power consumption of the semiconductor device 60.

[0080] In the semiconductor device 60 shown in FIG. 4(B), the gate of the transistor 68 is shown connected to the control signal generation circuit 67. However, the gate of the transistor 68 may not be connected to the control signal generation circuit 67. That is, the gate of the transistor 68 can be configured to be connected to other wiring or circuits.

[0081] <Operation Example of Semiconductor Device> Next, the operation when the semiconductor device 10 shown in FIG. 1(A) is controlled based on the timing charts shown in FIGS. 5(A) and 5(B) will be described. However, the semiconductor device 10 shown in FIG. 1(A) can perform various other operations by appropriately controlling the potential of each wiring.

[0082] FIG. 5(A) is a timing chart explaining the case where the power supply line 15 of the semiconductor device 10 in FIG. 1(A) functions as the high-potential power supply line VDD. That is, the resistance section 12 functions as a pull-up resistor.

[0083] FIG. 5(A) shows the potential V15 of the power supply line 15, the potential V17 of the control signal generation circuit 17, and the input / output potential V13 of the terminal 13.

[0084] During the period T11 shown in FIG. 5(A), the potentials of the power supply line 15 and the control signal generation circuit 17 gradually increase and are boosted to the threshold voltage (Vth) of the transistor 11. Also, since the potential of the input / output terminal 13 is in a floating state with the transistor 11 being off, it becomes an indeterminate state.

[0085] During the period T12, the potentials of the power supply line 15 and the control signal generation circuit 17 further increase and are boosted to V DD(H). Thereafter, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at V DD(H). Also, since the transistor 11 is in the on state, the potential of the input / output terminal 13 becomes the same as that of the power supply line 15 (VDD).

[0086] During the period T13, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD(H). A low-level (L) signal (VSS) is input to the input / output terminal 13. That is, during the period T13, current flows through the transistor 11 and the resistor section 12, so the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T13 be short. During the period T14, the potential of the power supply line 15 is held at VDD. A low-level (L) signal (VSS) is input to the control signal generation circuit 17, and the transistor 11 is turned off.

[0087] The potential of the input / output terminal 13 is held at VSS(L). During the period T15, the potential of the power supply line 15 is held at VDD(H). The control signal generation circuit receives a low-level (L) signal (VSS), and the transistor 11 is turned off.

[0088] The potential of the input / output terminal 13 is held at VSS(L). A high-level signal (VDD) is input to 17, and the transistor 11 is turned on. The potential of the input / output terminal 13 is held at VSS(L). That is, during the period T15, the current flows through the transistor 11 and the resistor section 12, so the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T15 is short.

[0089] During the period T16, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD. The potential of the input / output terminal 13 becomes VDD(H) because the input of the low-level (L) signal stops.

[0090] FIG. 5(B) is a timing chart for explaining the case where the power supply line 15 of the semiconductor device 10 in FIG. 1(A) functions as a low-potential power supply line VSS. That is, the resistor section 12 functions as a pull-down resistor.

[0091] FIG. 5(B) shows the potential V15 of the power supply line 15, the potential V17 of the control signal generation circuit 17, and the input / output potential V13 of the terminal 13.

[0092] During the period T21 shown in FIG. 5(B), the power supply line 15 is held at VSS(L). The potential of the control signal generation circuit 17 gradually increases and is boosted to the threshold voltage (Vth) of the transistor 11. Also, the potential of the input / output terminal 13 is floating because the transistor 11 is off, resulting in an indeterminate state.

[0093] During the period T22, the power supply line 15 is held at VSS(L). The potential of the control signal generation circuit 17 further increases and is boosted to VDD(H). Thereafter, the potential of the control signal generation circuit 17 is held at VDD(H). Also, the potential of the input / output terminal 13 is such that the transistor 11 is off. ​​​​ It becomes the state of <UNK>, and has the same potential (VSS) as the power supply line 15.

[0094] During period T23, the power supply line 15 is held at VSS(L). The potential of the control signal generation circuit 17 is held at VDD. A high-level signal (VDD) is input to the input / output terminal 13 . That is, during period T23, current flows through the transistor 11 and the resistor section 12, so the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that period T23 is short.

[0095] During period T24, the power supply line 15 is held at VSS(L). A low-level (L) signal (VSS) is input to the control signal generation circuit 17, and the transistor 11 turns off. The potential of the input / output terminal 13 is held at VDD(H).

[0096] During period T25, the power supply line 15 is held at VSS(L). A high-level signal (VDD) is input to the control signal generation circuit 17, and the transistor 11 turns on. The potential of the input / output terminal 13 is held at VDD(H). That is, during period T25, current flows through the transistor 11 and the resistor section 12, so the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that period T25 is short.

[0097] During period T26, the potential of the power supply line 15 is held at VSS(L). The potential of the control signal generation circuit 17 is held at VDD. Since the input of the high-level (H) signal to the input / output terminal 13 stops, it becomes VSS(L).

[0098] As described above, the semiconductor device 10 shown in FIG. 1 can function as a semiconductor device having a pull-up (or pull-down ) resistor such as an IC.

[0099] In addition, in this embodiment, one aspect of the present invention has been described. Or, in other embodiments one aspect of the present invention is described. However, one aspect of the present invention is not limited to these. That is, in this embodiment and other embodiments, various aspects of the invention are described therefore, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention an example in the case where a pull-up (or pull-down) resistor is applied has been shown, but one aspect of the present invention is not limited to this. Depending on the case or the situation, one aspect of the present invention may be applied to other circuits. Or for example, depending on the case or the situation one aspect of the present invention may not apply a pull-up (or pull-down) resistor. For example as one aspect of the present invention, an example in the case where a transistor has an oxide semiconductor has been shown, but one aspect of the present invention is not limited to this. Depending on the case or the situation, in one aspect of the present invention, the transistor may have various semiconductor materials such as silicon, germanium, silicon germanium, carbon silicon, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride or an organic semiconductor. Or for example, depending on the case or the situation, in one aspect of the present invention, the transistor may not have an oxide semiconductor.

[0100] Note that this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, the content described in this embodiment (even some of the content) is the other content described in that embodiment (even some of the content), and / or the content described in one or more other embodiments For the described content (even part of the content), applications, combinations, replacements, etc. can be made. This can be done. Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the sentences described in the specification. Also, the figure (even part of it) described in a certain embodiment can be combined with another part of that figure, another figure (even part of it) described in that embodiment, and / or the figure (even part of it) described in one or more other embodiments to form even more figures. This is the same for the following embodiments.

[0101] (Embodiment 2) In this embodiment, a configuration example of the transistor 11 and the resistor 12 in the semiconductor device 10 shown in Embodiment 1 will be described.

[0102] <Configuration Example 1> FIG. 6 shows a circuit diagram, a top view, and a cross-sectional view of the transistor 100 and the resistor 200. Note that the transistor 100 can be used as the transistor 11 in FIG. 1(A). Also, the resistor 200 can be used as the resistor 12 in FIG. 1(A). Further, the transistor 100 and the resistor 200 in this embodiment will be described with a configuration having an oxide semiconductor.

[0103] FIG. 6(A) shows a circuit diagram in which the transistor 100 and the resistor 200 are connected. For the transistor 100 and the resistor 200 shown in FIG. 6(A), a top view showing an example of the configuration is shown in FIG. 6(B). FIG. 6(C) is taken along the dashed-dotted line A1 - A2 in FIG. 6(A). The cross-sectional view in [is shown in Fig. 6(D)], the cross-sectional view along the dashed-dotted line A3 - A4 is shown in Fig. 6(E), and the cross-sectional view along the dashed-dotted line A5 - A6 is shown. Here, the direction of the dashed-dotted line A1 - A2 may be referred to as the channel length direction, and the direction of the dashed-dotted line A3 - A4 may be referred to as the channel width direction. Thus, Fig. 6(C) shows the cross-sectional structure of the transistor 100 in the channel length direction, and Fig. 6(D) shows the cross-sectional structure of the transistor 100 in the channel width direction. Note that, in order to clarify the device structure, some components are omitted in Fig. 6(B).

[0104] The transistor 100 shown in Fig. 6 includes an insulating layer 112 on a substrate 110, an oxide semiconductor layer 120 on the insulating layer 112, a conductive layer 141 and a conductive layer 142 formed in partial contact with the oxide semiconductor layer 120, an insulating layer 113 on the oxide semiconductor layer 120, the conductive layer 141, and the conductive layer 142, a conductive layer 130 overlapping the oxide semiconductor layer 120 and on the insulating layer 113, and an insulating layer 115 on the conductive layer 130 and the insulating layer 113.

[0105] The resistor 200 shown in Fig. 6 includes an insulating layer 112 on a substrate 110, an oxide semiconductor layer 121 on the insulating layer 112, a conductive layer 142 and a conductive layer 143 formed in partial contact with the oxide semiconductor layer 121, an insulating layer 113 on the oxide semiconductor layer 121, the conductive layer 142, and the conductive layer 143, and an insulating layer 115 on the insulating layer 113.

[0106] In the transistor 100, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 120 can function as an active layer of the transistor 100. The conductive layers 141 and 142 can function as a source electrode and a drain electrode, respectively. It can be formed. The insulating layer 113 has a region that functions as a gate insulating layer. The conductive layer 130 can function as a gate electrode. The insulating layer 115 can function as an interlayer insulating layer .

[0107] Also, in the resistance portion 200, the oxide semiconductor layer 121 can function as a resistance layer .

[0108] <Configuration Example 2> FIG. 7 shows a circuit diagram, a top view, and a cross-sectional view of the transistor and the resistance portion 101. Note that the transistor and the resistance portion 101 can be used for the transistor 11 and the resistance portion 12 in FIG. 1(A). Also, the transistor and the resistance portion 10 1 in the formation of the present embodiment will be described with respect to a configuration having an oxide semiconductor.

[0109] The transistor and the resistance portion 101 shown in FIG. 7 have a configuration in which the transistor 100 and the resistance portion 200 in FIG. 6 are combined into one. In particular, by using a transistor and a resistance portion 101 having an oxide semiconductor, a structure in which the active layer of a transistor with a small off-current and a resistance layer with a high resistance value are directly connected can be formed. By adopting such a configuration combining a transistor and a resistance portion, the layout area can be reduced.

[0110] FIG. 7(A) shows a circuit diagram of the transistor and the resistance portion 101. For the transistor and the resistance portion 101 shown in FIG. 7(A), a top view showing an example of the configuration is shown in FIG. 7(B). FIG. 7(C) is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 7(A), FIG. 7(D ) is a cross-sectional view taken along the dashed-dotted line A3-A4, and FIG. 7(E) is a cross-sectional view taken along the dashed-dotted line A5-A6​​ shows a cross-sectional view. Note that, in order to clarify the device structure, in FIG. 7(B), some of the components are omitted.

[0111] The transistor and resistor portion 101 shown in FIG. 7 includes an insulating layer 112 on a substrate 110, an oxide semiconductor layer 122 on the insulating layer 112, a conductive layer 141 and a conductive layer 143 formed in partial contact with the oxide semiconductor layer 122, an insulating layer 114 on the oxide semiconductor layer 122, the conductive layer 141 and the conductive layer 143, a conductive layer 131 overlapping partially with the oxide semiconductor layer 122 and on the insulating layer 114, and an insulating layer 115 on the conductive layer

[0112] In the transistor and resistor portion 101, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 122, in the transistor and resistor portion 101, the region overlapping with the conductive layer 131 can function as an active layer of the transistor. The conductive layers 141 and 143 can function as a source electrode and a drain electrode, respectively. The insulating layer 114 has a region that can function as a gate insulating layer. The conductive layer 131 can function as a gate electrode. The insulating layer 115 can function as an interlayer insulating layer.

[0113] Also, in the transistor and resistor portion 101, the oxide semiconductor layer 122, the region between the conductive layer 131 and the conductive layer 143 can function as a resistance layer of the resistor portion.

[0114] <Configuration Example 3> FIG. 8 shows a circuit diagram, a top view, and a cross-sectional view of a transistor 400 and a resistor portion 401. Note that the transistor 400 and the resistor 401 can be used for the transistor 11 and the resistor 12 in FIG. 1(A). In addition, the transistor 400 and the resistor 401 in the formation of this embodiment will be described with respect to a configuration having an oxide semiconductor.

[0115] The transistor 400 shown in FIG. 8 is not a top-gate type transistor as shown in FIGS. 6 and 7, but a bottom-gate type transistor.

[0116] FIG. 8(A) shows a circuit diagram of the transistor 400 and the resistor 401. For the transistor 400 and the resistor 401 shown in FIG. 8(A), a top view showing an example of the configuration is shown in FIG. 8(B). FIG. 8(C) shows a cross-sectional view taken along the dashed line A1 - A2 in FIG. 8(A). Note that, in order to clarify the device structure, some components are omitted in FIG. 8(B).

[0117] The transistor 400 shown in FIG. 8 includes an insulating layer 112 on a substrate 110, a conductive layer 410 on the insulating layer 112, an insulating layer 412 on the conductive layer 410, an oxide semiconductor layer 414 on the insulating layer 412, a conductive layer 418 and a conductive layer 420 formed in partial contact with the oxide semiconductor layer 414, and an insulating layer 424 on the oxide semiconductor layer 414, the conductive layer 418, and the conductive layer 420.

[0118] The resistor 401 shown in FIG. 8 includes an insulating layer 112 on a substrate 110, an insulating layer 412 on the insulating layer 112, an oxide semiconductor layer 416 on the insulating layer 412, a conductive layer 420 and a conductive layer 422 formed in partial contact with the oxide semiconductor layer 416, and an insulating layer 424 on the oxide semiconductor layer 416, the conductive layer 420, and the conductive layer 422. ​​​​​​​​​​​​​

[0119] In transistor 400, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 414 can function as the active layer of transistor 400. The conductive layer 418 and the conductive layer 420 can function as a source electrode and a drain electrode, respectively. The insulating layer 412 has a region that functions as a gate insulating layer. The conductive layer 410 can function as a gate electrode. The insulating layer 424 can function as an interlayer insulating layer.

[0120] Also, in the resistor portion 401, the oxide semiconductor layer 416 can function as a resistance layer.

[0121] Also, the bottom-gate type transistor 400 shown in FIG. 8 has a channel-etch type structure. However, as shown in FIG. 9(A), it may be a channel-protection type transistor 402.

[0122] The transistor 402 shown in FIG. 9(A) includes an insulating layer 112 on the substrate 110, a conductive layer 410 on the insulating layer 112, an insulating layer 412 on the conductive layer 410, an oxide semiconductor layer 414 on the insulating layer 412, an insulating layer 428 on the oxide semiconductor layer 414, conductive layers 430 and 432 formed in partial contact with the oxide semiconductor layer 414 and the insulating layer 428, and an insulating layer 434 on the oxide semiconductor layer 414, the insulating layer 428, the conductive layers 430 and 432.

[0123] In transistor 402, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 414 can function as the active layer of transistor 400. The conductive layer 430 and the conductive layer 432 can function as a source electrode and a drain electrode. The insulating layer 412 has a region that functions as a gate insulating layer. The conductive layer 410 can function as a gate electrode. The insulating layer 434 can function as an interlayer insulating layer. The insulating layer 428 can function as a channel protection layer.

[0124] Also, the transistor 403 shown in FIG. 9(B) has a structure in which a conductive layer 4 11 is added to the transistor 400 of FIG. 8. In the transistor 403, the conductive layer 411 can function as a back gate electrode.

[0125] Also, in the resistor 401 shown in FIG. 8, it may have a structure with an additional conductive layer. A resistor 404 having an additional conductive layer 435 is shown in FIG. 9(C).

[0126] The resistor 404 shown in FIG. 9(C) includes an insulating layer 112 on the substrate 110, a conductive layer 435 on the insulating layer 112, an insulating layer 438 on the conductive layer 435, an oxide semiconductor layer 4 44 on the insulating layer 438, a conductive layer 440 and a conductive layer 44 2 that are formed in partial contact with the oxide semiconductor layer 444, and an insulating layer 446 on the oxide semiconductor layer 444, the conductive layer 440, and the conductive layer 442.

[0127] Also, in the resistor 404, the oxide semiconductor layer 444 can function as a resistance layer.

[0128] Also, the resistor 405 shown in FIG. 9(D) has a structure in which a conductive layer 448 is added to the resistor 404 of FIG. 9(C).

[0129] 9E shows a resistor section 406 having an insulating layer 450 in addition to the resistor section 401 shown in FIG. It is a structure.

[0130] When a film containing a large amount of hydrogen, such as a film containing silicon nitride, is used for the insulating layer 450, In this case, the resistance of the oxide semiconductor layer 416 can be reduced in some cases.

[0131] The structure and method described in this embodiment may be appropriately combined with the structure and method described in other embodiments. It is possible.

[0132] (Embodiment 3) In this embodiment, a transistor including an oxide semiconductor which can be used in one embodiment of the present invention will be described. A configuration example of an OS transistor (also referred to as an OS transistor) will be described in this embodiment. The OS transistor is, for example, the transistor 11 in FIG. 1A and the transistor 12 in FIG. This can be applied to the transistor 58, etc.

[0133] <Configuration example 1> FIG. 10 shows an example of the structure of an OS transistor. FIG. 10(A) shows the structure of an OS transistor. FIG. 10(B) is a cross-sectional view taken along line y1-y2, and FIG. FIG. 10(D) is a cross-sectional view taken along the line x3-x4. The direction of the 1-y2 line is called the channel length direction, and the direction of the x1-x2 line is called the channel width direction. FIG. 10B shows a cross-sectional structure of an OS transistor in the channel length direction. 10C and 10D show the structure of the OS transistor in the channel width direction. In order to clarify the device structure, FIG. 10(A) shows a cross-sectional structure. Some components are omitted.

[0134] The OS transistor 501 shown in FIG. 10 has a back gate. The OS transistor 50 1 is formed on an insulating surface. Here, it is formed on the insulating layer 511. The insulating layer 511 is formed on the surface of the substrate 510. The OS transistor 501 is covered with the insulating layer 514 and the insu lating layer 515. Note that the insulating layers 514 and 515 can also be regarded as components of the OS transistor 501 . The OS transistor 501 has the insulating layer 512, the insulating layer 5 13, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, the conductive layer 5 30, the conductive layer 531, the conductive layer 541, and the conductive layer 542. Here, the oxide semiconductor layer 5 21, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 are collectively referred to as the oxide semiconductor layer 5 20. Note that although a structure with a back gate is shown here, a structure without a back gate may also be used.

[0135] The insulating layer 513 has a region that functions as a gate insulating layer. The conductive layer 530 functions as a gate electrode ( the first gate electrode). The conductive layer 531 functions as a back gate electrode (the second gate electrode). The conductive layers 541 and 542 function as a source electrode or a drain electrode, respectively. Note that the conductive layer 531 may not be provided (the same applies hereinafter).

[0136] As shown in FIGS. 10(B) and (C), the oxide semiconductor layer 520 has a region in which the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 are laminated in this order. The insulating layer 5 13 covers this laminated portion. The conductive layer 531 overlaps the laminated portion of the oxide semiconductor layer via the insulating layer 513 . The conductive layers 541 and 542 are in contact with the oxide semiconductor layer 521 and the acid ​​It is provided on a stacked film composed of the oxide semiconductor layer 523, and these are in contact with the upper surface of this stacked film and the side surfaces in the channel length direction of the stacked film. Also, in the example of FIG. 10, the conductive layers 541 , 542 are also in contact with the insulating layer 512. The oxide semiconductor layer 523 is formed so as to cover the oxide semiconductor layer 52 1, the oxide semiconductor layer 522, and the conductive layer 541 and the conductive layer 542. The lower surface of the oxide semiconductor layer 523 is in contact with the upper surface of the oxide semiconductor layer 522.

[0137] In the oxide semiconductor layer 520, the conductive layer 530 is formed so as to surround the channel width direction of the stacked portion of the oxide semiconductor layers 521 to 52 3 via the insulating layer 513 (see FIG. 1 0(C)). Therefore, in addition to the gate electric field from the vertical direction, a gate electric field from the side direction is also applied to this stacked portion. In the OS transistor 501, the gate electric field refers to the electric field formed by the voltage applied to the conductive layer 531 (gate electrode layer). Therefore, due to the gate electric field, the entire stacked portion of the oxide semiconductor layers 521 to 523 can be electrically surrounded, so a channel may be formed in the entire (bulk) of the oxide semiconductor layer 522. Therefore, the OS transistor 501 can have high on-current characteristics.

[0138] In this specification, the structure of a transistor that can electrically surround a semiconductor by such a gate electric field is called "surrounded channel (s-channel)" structure. The OS transistor 501 has an s-channel structure. In the s-chan nel structure, a large current can flow between the source and drain of the transistor, and the drain current (on-current) in the conductive state can be increased. ​​​

[0139] By making the OS transistor 501 have an s-channel structure, it becomes easier to control the channel formation region by the gate electric field with respect to the side surface of the oxide semiconductor layer 522. The conductive layer 530 extends to below the oxide semiconductor layer 522 and faces the side surface of the oxide semiconductor layer 521. In this structure, the controllability is further excellent and preferable. As a result, the subthreshold threshold swing value (also referred to as the S value) of the OS transistor 501 can be made small, and the short-channel effect can be suppressed. Therefore, it is a structure suitable for miniaturization.

[0140] By making the OS transistor have a three-dimensional device structure like the OS transistor 501 shown in FIG. 10, the channel length can be made less than 100 nm. By miniaturizing the OS transistor, the circuit area can be reduced. The channel length of the OS transistor is preferably less than 65 nm, more preferably 30 nm or less or 20 nm or less.

[0141] A conductor that functions as the gate of the transistor is called the gate electrode, a conductor that functions as the source of the transistor is called the source electrode, a conductor that functions as the drain of the transistor is called the drain electrode, a region that functions as the source of the transistor is called the source region, and a region that functions as the drain of the transistor is called the drain region. In this specification, the gate electrode may be referred to as the gate, the drain electrode or the drain region may be referred to as the drain, and the source electrode or the source region may be referred to as the source.

[0142] The channel length is, for example, in the top view of the transistor, the semiconductor (or the transistor The region where the part of the current flowing in the semiconductor overlaps with the gate when it is in the on state, or the distance between the source and the drain in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. Refers to the distance between the source and the drain in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. In one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. In this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0143] The channel width refers to, for example, the region where the part of the current flowing in the semiconductor (or in the semiconductor when the transistor is in the on state) overlaps with the gate, or the length of the part where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. The channel width refers to, for example, the region where the part of the current flowing in the semiconductor (or in the semiconductor when the transistor is in the on state) overlaps with the gate, or the length of the part where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. Refers to the length of the part where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. In one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0144] Note that depending on the structure of the transistor, the effective channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, on the side surface of the semiconductor. The effective channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. In a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, on the side surface of the semiconductor. ​​There are cases where the ratio of the formed channel region may increase. In such cases, in the top view, the actual effective channel width where the channel is actually formed is larger than the apparent channel width shown.

[0145] In this specification, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image.

[0146] <Configuration Example 2> The OS transistor 502 shown in FIG. 11 is a modified example of the OS transistor 501. FIG. 1 1(A) is a top view of the OS transistor 502. FIG. 11(B) is a cross-sectional view along the line y1 - y2, FIG. 11(C) is a cross-sectional view along the line x1 - x2, and FIG. 11(D) is a cross-sectional view along the line x3 - x4. Note that, to clarify the device structure, in FIG. 11(A), some constituent elements are omitted.

[0147] The OS transistor 502 shown in FIG. 11 also has an s-channel structure, similar to the OS transistor 501. The shapes of the conductive layer 541 and the conductive layer 542 are different from those of the OS transistor 501. The conductive layer 541 and the conductive layer 542 of the OS transistor 502 are formed from a hard mask used to form a stacked film of the oxide semiconductor layer 521 and the oxide semiconductor layer 522. Therefore, the conductive layer 541 and the conductive layer 542 are the oxide semiconductor layer 521 and not in contact with the side surface of the oxide semiconductor layer 522 (FIG. 11(D)).

[0148] Through the following steps, the oxide semiconductor layers 521 and 522 and the conductive layers 541 and 542 can be fabricated. Form two oxide semiconductor films that constitute the oxide semiconductor layers 521 and 522. Form a single-layer or laminated conductive film on the oxide semiconductor film. Etch this conductive film to form a hard mask. Using this hard mask, etch the two oxide semiconductor films to form a laminated film of the oxide semiconductor layer 521 and the oxide semiconductor layer 522. Next, etch the hard mask to form the conductive layer 541 and the conductive layer 542.

[0149] <Configuration Examples 3 and 4> The OS transistor 503 shown in FIG. 12 is a modified example of the OS transistor 501, and the OS transistor 504 shown in FIG. 1 3 is a modified example of the OS transistor 502. In the OS transistor 503 and the OS transistor 504, the conductive layer 530 is used as a mask to etch the oxide semiconductor layer 523 and the insulating layer 513. Therefore, the ends of the oxide semiconductor layer 532 and the insulating layer 513 substantially coincide with the ends of the conductive layer 530.

[0150] <Configuration Examples 5 and 6> The OS transistor 505 shown in FIG. 14 is a modified example of the OS transistor 501, and the OS transistor 506 shown in FIG. 1 5 is a modified example of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each have a layer 551 between the oxide semiconductor layer 523 and the conductive layer 541, and a layer 552 between the oxide semiconductor layer 523 and the conductive layer 542.

[0151] ​​​​​​​Layers 551 and 552 can be formed of, for example, a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor layer. Layers 551 and 552 can be formed of an n-type oxide semiconductor layer, or can be formed of a conductor layer having a higher resistance than conductor layers 541 and 542. For example, as layers 551 and 552, a layer containing indium, tin, and oxygen, a layer containing indium and zinc, a layer containing indium, tungsten, and zinc, a layer containing tin and zinc, a layer containing zinc and gallium, a layer containing zinc and aluminum, a layer containing zinc and fluorine, a layer containing zinc and boron, a layer containing tin and antimony, a layer containing tin and fluorine, or a layer containing titanium and niobium may be used. These exemplified layers may contain one or more of hydrogen, carbon, nitrogen, silicon, germanium, or argon. Layers 551 and 552 may have a property of transmitting visible light. Or, layers 551 and 552 may have a property of not allowing visible light, ultraviolet rays, infrared rays, or X-rays to be transmitted by reflection or absorption. By having such a property, fluctuations in the electrical characteristics of the transistor due to stray light may be suppressed in some cases. Also, it is preferable to use layers 551 and 552 that do not form a Schottky barrier with oxide semiconductor layer 532. By doing so, the on characteristics of OS transistors 505 and 506 can be improved. Layers 551 and 552 are made into layers having a higher resistance than conductor 516a and conductor 516b.

[0152]

[0153]

[0154] is preferred. Further, the layers 551 and 552 preferably have a lower resistance than the channel resistance of the transistor. For example, if the resistivity of the layers 551 and 552 is set to 0.1 Ωcm or more and 100 Ωcm or less, 0.5 Ωcm or more and 50 Ωcm or less, or 1 Ωcm or more and 10 Ωcm or less, it is good. By setting the resistivity of the layers 551 and 552 within the above range, the electric field concentration at the boundary between the channel and the drain can be alleviated. Therefore, the variation in the electrical characteristics of the transistor can be reduced. Also, the punch-through current caused by the electric field generated from the drain can be reduced. Therefore, even in a transistor with a short channel length, the saturation characteristics can be improved. Note that if the circuit configuration is such that the source and the drain cannot be interchanged, it may be preferable to arrange only one of the layers 551 and 552 (for example, on the drain side).

[0155] <Configuration Example 7> In FIGS. 10 to 15, the conductive layer 530 functioning as the first gate electrode and the conductive layer 531 functioning as the second gate electrode may be connected. As an example, FIG. 16 shows a configuration in which the conductive layer 530 and the conductive layer 531 in FIG. 10 are connected.

[0156] As shown in FIG. 16(C), openings are provided in the insulating layer 512 and the insulating layer 513, and a conductive layer 560 is provided in the openings. And the conductive layer 530 is connected to the conductive layer 531 via the conductive layer 560. Thereby, the first gate electrode and the second gate electrode of the OS transistor 501 can be connected. Note that the configuration in which the first gate electrode and the second gate electrode are connected can also be applied to FIGS. 11 to 15 in the same manner.

[0157] Hereinafter, the components of the OS transistors 501 to 506 will be described.

[0158] <Oxide semiconductor layer> Typical semiconductor materials for the oxide semiconductor layers 521 to 523 are In-Ga oxide , In-Zn oxide, In-M-Zn oxide (M is Ga, Sn, Y, Zr, La, Ce , or Nd). Further, the oxide semiconductor layers 521 to 523 are not limited to oxide layers containing indium. The oxide semiconductor layers 521 to 523 can be formed of, for example, a Zn-Sn oxide layer, a Ga-Sn layer, a Zn-Mg oxide, or the like. Further, the oxide semiconductor layer 522 is preferably formed of an In-M-Zn oxide. Further, the oxide semiconductor layer 52 1 and the oxide semiconductor layer 523 can each be formed of a Ga oxide.

[0159] The case where the oxide semiconductor layers 521 to 523 are formed of an In-M-Zn oxide film formed by a sputtering method will be described. For the In-M used for the formation of the oxide semiconductor layer 522 -Zn oxide, the atomic ratio of the metal elements of the target for film formation is In:M:Zn = x1:y1 :z1, and for the targets used for the formation of the oxide semiconductor layer 521 and the oxide semiconductor layer 523, the atomic ratio of the metal elements of the target is In:M:Zn = x2:y2:z2.

[0160] For the formation of the oxide semiconductor layer 522, x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less. It is preferable to use a polycrystalline target of In-M-Z n oxide. By setting z1 / y1 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed. Instead of the atomic ratio of the metal elements of the target Examples include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Z n = 2:1:1.5, In:M:Zn = 2:1:2.3, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, etc. Note that CAA C-OS refers to an oxide semiconductor having a crystal part oriented along the c-axis, which will be described later. The CAAC-OS film preferably does not contain a spinel-type crystal structure in particular. Thereby, the electrical characteristics and reliability of the transistor using the CAAC-OS film can be improved.

[0161] The targets used for forming the oxide semiconductor layers 521 and 523 satisfy x2 / y2 < x1 / y 1, and z2 / y2 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, the CAAC-OS film is likely to be formed. Typical examples of the atomic ratio of the metal elements of the target are In:M:Zn = 1:3:2, In:M :Zn = 1:3:4, In:M:Zn = 1:3:6, In:M:Zn = 1:3:8, In :M:Zn = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn = 1:4:6, In:M:Zn = 1:4:7, In:M:Zn = 1:4:8, In:M:Zn = 1:5: 5, In:M:Zn = 1:5:6, In:M:Zn = 1:5:7, In:M:Zn = 1: 5:8, In:M:Zn = 1:6:8, etc.

[0162] The atomic ratio of the In-M-Zn oxide film includes a variation of plus or minus 40% of the above atomic ratio as an error. For example, the atomic ratio of the metal elements contained in the oxide semiconductor film formed using an oxide target of In:M:Zn = 4:2:4.1 is approximately In:M: Zn = 4:2:4.1. Zn = 4:2:3.

[0163] [Energy Band] Next, regarding the function and effects of the oxide semiconductor layer 520 composed of the stack of oxide semiconductor layers 521 to 523, it will be described using the energy band structure diagram shown in Fig. 17(B). Fig. 17(A) is an enlarged view of the channel region of the OS transistor 502 and is a partially enlarged view of Fig. 11(B). In Fig. 17(B), the energy band structure of the site (channel formation region of the OS transistor 502) indicated by the dotted line z1 - z2 in Fig. 17(A) is shown. Hereinafter, the OS transistor 502 will be taken as an example for explanation, but the same applies to the OS transistors 501, 503 to 506. Fig. 17(A) is an enlarged view of the channel region of the OS transistor 502 and is a partially enlarged view of Fig. 11(B). Fig. 17(B) shows the energy band structure of the site (channel formation region of the OS transistor 502) indicated by the dotted line z1 - z2 in Fig. 17(A). Hereinafter, the OS transistor 502 will be taken as an example for explanation, but the same applies to the OS transistors 501, 503 to 506. Fig. 17(A) is an enlarged view of the channel region of the OS transistor 502 and is a partially enlarged view of Fig. 11(B). Fig. 17(B) shows the energy band structure of the site (channel formation region of the OS transistor 502) indicated by the dotted line z1 - z2 in Fig. 17(A). Hereinafter, the OS transistor 502 will be taken as an example for explanation, but the same applies to the OS transistors 501, 503 to 506. In Fig. 17(B), Ec512, Ec521, Ec522, Ec523, Ec513 respectively indicate the energies of the lower ends of the conduction bands of the insulating layer 512, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, and the insulating layer 513. Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). In Fig. 17(B), Ec512, Ec521, Ec522, Ec523, Ec513 respectively indicate the energies of the lower ends of the conduction bands of the insulating layer 512, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, and the insulating layer 513.

[0164] In Fig. 17(B), Ec512, Ec521, Ec522, Ec523, Ec513 respectively indicate the energies of the lower ends of the conduction bands of the insulating layer 512, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, and the insulating layer 513. In Fig. 17(B), Ec512, Ec521, Ec522, Ec523, Ec513 respectively indicate the energies of the lower ends of the conduction bands of the insulating layer 512, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, and the insulating layer 513. In Fig. 17(B), Ec512, Ec521, Ec522, Ec523, Ec513 respectively indicate the energies of the lower ends of the conduction bands of the insulating layer 512, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, and the insulating layer 513.

[0165] Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe). Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (PHI VersaProbe).

[0166] Note that the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2 is approximately 3.5 eV, and the electron affinity is approximately 4 .5 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:4 is approximately 3.4 eV, and the electron affinity is approximately 4.5 eV. Further, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:6 is approximately 3.3 eV, and the electron affinity is approximately 4.5 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:2 is approximately 3.9 eV, and the electron affinity is approximately 4.3 eV. Additionally, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:8 is approximately 3.5 eV, and the electron affinity is approximately 4.4 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:10 is approximately 3.5 eV, and the electron affinity is approximately 4.5 eV. Moreover, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:1:1 is approximately 3.2 eV , and the electron affinity is approximately 4.7 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 is approximately 2.8 eV , and the electron affinity is approximately 5.0 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 is approximately 2.8 eV, and the electron affinity is approximately 5.0 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:1:1 is approximately 3.2 eV , and the electron affinity is approximately 4.7 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 is approximately 2.8 eV , and the electron affinity is approximately 5.0 eV. The energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 is approximately 2.8 eV, and the electron affinity is approximately 5.0 eV.

[0167] Since the insulating layers 512 and 513 are insulators, Ec513 and Ec512 are closer to the vacuum level (have a smaller electron affinity) than Ec52 1, Ec522, and Ec523.

[0168] Also, Ec521 is closer to the vacuum level than Ec522. Specifically, Ec521 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less closer to the vacuum level than Ec522 is preferable.

[0169] Also, Ec523 is closer to the vacuum level than Ec522. Specifically, Ec523 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less closer to the vacuum level than Ec522 is preferable.

[0170] Also, in the vicinity of the interface between the oxide semiconductor layer 521 and the oxide semiconductor layer 522, and in the vicinity of the interface between the oxide semiconductor layer 522 and the oxide semiconductor layer 523, a mixed region is formed, so the energy of the lower end of the conduction band changes continuously. That is, at these interfaces, there are no levels, almost none.

[0171] Therefore, in the stacked structure having the energy band structure, electrons mainly move through the oxide semiconductor layer 5 22. Therefore, even if there are levels at the interface between the oxide semiconductor layer 521 and the insulating layer 512, or at the interface between the oxide semiconductor layer 523 and the insulating layer 513, such levels hardly affect the movement of electrons. Also, between the oxide semiconductor layer 521 and the oxide semiconductor layer 523 The interface with the semiconductor layer 522 and the interface between the oxide semiconductor layer 523 and the oxide semiconductor layer 522 Since there are no or almost no energy levels in this region, electron movement in this region is inhibited either. Therefore, the OS transistor 502 having the stacked structure of the oxide semiconductor can have a high field-effect mobility.

[0172] As shown in Fig. 17(B), near the interface between the oxide semiconductor layer 521 and the insulating layer 512 and near the interface between the oxide semiconductor layer 523 and the insulating layer 513, trap energy levels Et502 caused by impurities and defects may be formed. However, due to the presence of the oxide semiconductor layer 521 and the oxide semiconductor layer 5 23, the oxide semiconductor layer 522 can be kept away from the trap energy levels thereby.

[0173] In the channel width direction, the upper surface and the side surface of the oxide semiconductor layer 522 are in contact with the oxide semiconductor layer 523, and the lower surface of the oxide semiconductor layer 522 is in contact with the oxide semiconductor layer 521 (see Fig. 11(C)). Thus, by covering the oxide semiconductor layer 522 with the oxide semiconductor layer 521 and the oxide semiconductor layer 523, the influence of the trap energy levels can be further reduced.

[0174] However, when the energy difference between Ec521 or Ec523 and Ec522 is small, electrons in the oxide semiconductor layer 522 may reach the trap energy levels beyond the energy difference thereby. When electrons are trapped in the trap energy levels, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction.

[0175] ​​Therefore, when the energy differences between Ec521 and Ec523 and Ec522 are each set to 0 .1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and the electrical characteristics of the transistor can be made good, which is preferable . .

[0176] Also, the band gaps of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 are preferably wider than the band gap of the oxide semiconductor layer 522. .

[0177] For the oxide semiconductor layer 521 and the oxide semiconductor layer 523, for example, a material containing (Ga, Y, Zr, La, Ce, or Nd) at an atomic ratio higher than that of the oxide semiconductor layer 522 can be used . Specifically, the atomic ratio is set to 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. Since the aforementioned elements strongly bond with oxygen, they have a function of suppressing the occurrence of oxygen vacancies in the oxide semiconductor. That is, it can be said that the oxide semiconductor layer 521 and the oxide semiconductor layer 523 are less likely to generate oxygen vacancies than the oxide semiconductor layer 522. . . . .

[0178] When the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 are In-M-Zn oxides containing at least indium, zinc, and M (M is Ga, Sn, Y, Zr, La, Ce, or Nd), when the oxide semiconductor layer 521 is In:M:Zn = x1:y1:z1 [atomic ratio], the oxide semiconductor layer 522 is In:M:Zn = x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 523 is In:M:Zn = x3:y3:z3 [atomic ratio], it is preferable that y1 / x1 and y3 / x3 are larger than y2 / x2. y1 . . . . . / x1 and y3 / x3 are 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than y2 / x2. At this time, in the oxide semiconductor layer 522, when y2 is equal to or more than x2, the electrical characteristics of the transistor can be stabilized. However, when y2 becomes 3 times or more of x2, the field-effect mobility of the transistor decreases. Therefore, it is preferable that y2 is less than 3 times of x2.

[0179] The In-M-Zn oxide film satisfying such conditions can be formed by using a target of In-M-Zn oxide that satisfies the atomic ratio of the above-described metal elements.

[0180] The atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 521 and the oxide semiconductor layer 523 is preferably such that In is less than 50 atomic% and M is higher than 50 atomic%, and more preferably In is less than 25 atomic% and M is higher than 75 atomic%. Also, the atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 522 is preferably such that In is higher than 25 atomic% and M is less than 75 atomic%, and more preferably In is higher than 34 atomic% and M is less than 66 atomic%.

[0181] Further, at least one of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 may not contain indium. For example, the oxide semiconductor layer 521 and / or the oxide semiconductor layer 523 can be formed of a gallium oxide film.

[0182] The thicknesses of the oxide semiconductor layer 521 and the oxide semiconductor layer The thickness of the oxide semiconductor layer 522 is preferably 3 nm or more and 50 nm or less. nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 100 nm or less. The oxide semiconductor layer 523 has a thickness greater than or equal to m and less than or equal to 50 nm. It is preferable that the thickness of the oxide semiconductor layer 523 be smaller than that of the oxide semiconductor layer 522 .

[0183] In order to give stable electrical characteristics to an OS transistor with an oxide semiconductor channel, The present invention relates to a method for reducing the impurity concentration in an oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is 1× 10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 Less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0184] In addition, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity levels can become traps and degrade the electrical characteristics of the transistor. Therefore, the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 It is preferable to reduce the impurity concentration in the layers and at their respective interfaces.

[0185] In order to make an oxide semiconductor intrinsic or substantially intrinsic, for example, , at a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, The concentration of [element] is 1×10 19 atoms / cm 3 less than, preferably 5×10 18 atoms / c m 3 less than, more preferably 1×10 18 atoms / cm 3 and is set to be less than. Also, the hydrogen concentration is, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, 2×10 atoms / cm 20 less than, preferably 5×10 3 atoms / cm 19 3 less than, more preferably 1×10 19 atoms / cm 3 less than, even more preferably 5×1 0 18 atoms / cm 3 and is set to be less than. Also, the nitrogen concentration is, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, 5×10 atoms / c 19 m less than, preferably 5×10 3 atoms / cm 18 less than, more preferably 1×10 3 1 atoms / cm 8 less than, even more preferably 5×10 3 atoms / cm 17 less than, and is set to be 3 less than. Thus,

[0186] Also, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, it may reduce the crystallinity of the oxide semiconductor. In order not to reduce the crystallinity of the oxide semiconductor, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the silicon concentration is 1×10 atoms / cm 19 less than, 3less than, preferably 5×10 18 atom s / cm 3 less than, more preferably 1×10 18 atoms / cm 3 having a portion less than is sufficient. Also, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the carbon concentration is 1×10 atoms / cm 19 less than, preferably 5 3 ×10 ×10 18 atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 having a portion less than is sufficient.

[0187] Also, the off-current of the transistor using the oxide semiconductor purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1V, 5V or 10V, the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm. or 10V, the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm. [Off-current] In this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state

[0188] [Off-current] In this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state refers to the state where, unless otherwise specified, for an n-channel transistor, the voltage Vgs between the gate and the source is lower than the threshold voltage Vth, and for a p-channel transistor, the voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage V th. source is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage V th.

[0189] The off-current of the transistor may depend on Vgs. Therefore, when it is said that the off-current of the transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of the transistor may refer to the off-current in the off-state at a predetermined Vgs, in the off-state at Vgs within a predetermined range, or in the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. When it is said that the off-current of the transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of the transistor may refer to the off-current in the off-state at a predetermined Vgs, in the off-state at Vgs within a predetermined range, or in the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. The off-current of the transistor may refer to the off-current in the off-state at a predetermined Vgs, in the off-state at Vgs within a predetermined range, or in the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. The off-current of the transistor may refer to the off-current in the off-state at a predetermined Vgs, in the off-state at Vgs within a predetermined range, or in the off-state at Vgs where a sufficiently reduced off-current is obtained, etc.

[0190] As an example, assume an n-channel transistor where the threshold voltage Vth is 0.5 V, the drain current at Vgs = 0.5 V is 1×10 A, the drain current at Vgs = 0.1 V is 1×10 -9 A, the drain current at Vgs = -0.5 V is 1×10 -13 A, and the drain current at Vgs = -0.8 V is 1×10 -19 A. Since the drain current of the transistor is 1×10 A or less at Vgs = -0.5 V, or in the range of Vgs from -0.5 V to -0.8 V, it may be said that the off-current of the transistor is 1×10 -22 A or less. Since there exists a Vgs for which the drain current of the transistor becomes 1×10 A or less, it may be said that the off-current of the transistor is 1×10 A or less. -19 A or less. A or less, it may be said that the off-current of the transistor is 1×10 -19 A or less. Since there exists a Vgs for which the drain current of the transistor becomes 1×10 -22 A or less, it may be said that the off-current of the transistor is 1×10 A or less. -22 A or less.

[0191] In this specification, the off-current of a transistor having a channel width W may be expressed by the current value flowing per channel width W. Also, it may be the current flowing per a predetermined channel width (for example, 1 μm). In this specification, the off-current of a transistor having a channel width W may be expressed by the current value flowing per channel width W. Also, it may be the current flowing per a predetermined channel width (for example, 1 μm). It may be represented by a current value. In the latter case, the unit of the off-current may be represented by a unit having the dimension of current / length (for example, A / μm).

[0192] The off-current of a transistor may depend on temperature. In this specification, the off-current represents, unless otherwise specified, the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, it may represent the off-current at a temperature at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or at a temperature at which a semiconductor device or the like including the transistor is used (for example, any one temperature from 5 °C to 35 °C). That the off-current of a transistor is I or less means that there exists a value of Vgs at which the off-current of the transistor at room temperature, 60 °C, 85 °C, 95 °C, 125 °C, the temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the temperature at which a semiconductor device or the like including the transistor is used (for example, any one temperature from 5 °C to 35 °C) is I or less.

[0193] The off-current of a transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-current represents, unless otherwise specified, the off-current at Vds = 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Or, it may represent the off-current at Vds at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or the off-current at Vds used in a semiconductor device or the like including the transistor. That the off-current of a transistor is I or less means that Vds is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2 ​​​​​​​​​​​​​​ .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, when the transistor is included The reliability of the semiconductor device including the Vds, or the Vds used in the semiconductor device or the like including the transistor, there may be a case where the value of Vg at which the off-current of the transistor becomes I or less exists. refers to the case where there is a value of Vg such that the off-current of the transistor is I or less.

[0194] In the description of the off-current above, the drain may be read as the source. That is, the off-current may also refer to the current flowing through the source when the transistor is in the off state.

[0195] In this specification, in the same meaning as the off-current, it may be described as the leakage current.

[0196] In this specification, the off-current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state.

[0197] [Crystal Structure of Oxide Semiconductor Film] Hereinafter, the structure of the oxide semiconductor film constituting the oxide semiconductor layer 520 will be described. In this specification, when the crystal is trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system.

[0198] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Non single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crys talline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film , a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0199] 〈CAAC-OS Film〉The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented along the c-axis. conductor film.

[0200] By using a transmission electron microscope (TEM), a composite analysis image of the bright-field image and diffraction pattern of the CAAC-OS film ( also referred to as a high-resolution TEM image) can be observed to confirm a plurality of crystal portions. On the other hand, the boundaries between distinct crystal portions, i.e., grain boundaries (also referred to as grain boundaries), cannot be confirmed even by high-resolution TEM images. Therefore, it can be said that the CAAC-OS film is less likely to have a decrease in electron mobility due to grain boundaries. When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal portion. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the film-forming surface) or the upper surface of the CAAC-OS film and is arranged parallel to the film-forming surface or the upper surface of the CAAC-OS film.

[0201] When observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal portion. However, no regularity is observed in the arrangement of metal atoms between different crystal portions. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the out-of-plane method analysis of a CAAC-OS film having InGaZnO4 crystals, a peak may appear at a diffraction angle (2θ) near 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystals.

[0202] When observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal portion. However, no regularity is observed in the arrangement of metal atoms between different crystal portions. However, no regularity is observed in the arrangement of metal atoms between different crystal portions.

[0203] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the out-of-plane method analysis of a CAAC-OS film having InGaZnO4 crystals, a peak may appear at a diffraction angle (2θ) near 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystals. In the out-of-plane method analysis of a CAAC-OS film having InGaZnO4 crystals, a peak may appear at a diffraction angle (2θ) near 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystals. This peak is attributed to the (009) plane of the InGaZnO4 crystals. Therefore, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0204] In the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak around 2θ = 31°, there is a case where a peak also appears around 2θ = 36°. The peak around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak around 2θ = 31° and does not show a peak around 2θ = 36°.

[0205] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, will disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film and reduce the crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and reduce the crystallinity. Note that the impurities contained in the oxide semiconductor film may be carrier traps or carrier generation sources.

[0206] The CAAC-OS film is an oxide semiconductor film with a low density of defect energy levels. For example, oxygen vacancies in the oxide semiconductor film can become carrier traps or carrier generation sources by capturing hydrogen.

[0207] ​​​​​​​​​A state in which the impurity concentration is low and the density of defect levels is low (with few oxygen deficiencies) is referred to as highly pure intrinsic or substantially highly pure intrinsic. An oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, so the carrier density can be reduced. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative ( also referred to as normally-on).) Also, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0208] An OS transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0209] 〈Microcrystalline Oxide Semiconductor Film〉A microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed in a high-resolution TEM image and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film often have a size of 1 nm or more and 100 nm or less, or 1 n m or more and 10 nm or less. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called nc-OS (nanocrystalline Oxide Se ​​​​​​is called an (miconductor) film. Also, the nc-OS film, for example, in a high-resolution TEM image there may be cases where grain boundaries cannot be clearly confirmed.

[0210] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film shows no regularity in the crystal orientation between different crystalline parts. Therefore, no orientation is observed in the whole film. Thus, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when performing structural analysis on the nc-OS film using an XRD device with an X-ray having a diameter larger than that of the crystalline part, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Also, for the nc-OS film, electron diffraction (also referred to as restricted-field electron diffraction) using an electron beam with a probe diameter larger than that of the crystalline part (for example, 50 nm or more) is performed, and a diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film when performing nano-beam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystalline part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film there may be cases where regions with high luminance are observed in a ring shape (drawing a circle). Also, when performing nano-beam electron diffraction on the nc-OS film, multiple spots may be observed within the ring-shaped region.

[0211] The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect energy levels than an amorphous oxide semiconductor film. However, the nc-OS film shows no regularity in the crystal orientation between different crystalline parts. Therefore, nc-O The S film has a higher density of defect levels compared to the CAAC-OS film.

[0212] 〈Amorphous Oxide Semiconductor Film〉 An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystalline part. An oxide semiconductor film having an amorphous state like quartz is an example.

[0213] In the high-resolution TEM image, no crystalline part can be confirmed in the amorphous oxide semiconductor film. When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane analysis by the method. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. When performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

[0214] The oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semiconductor) film.

[0215] In the high-resolution TEM image of the a-like OS film, voids (also referred to as voids) may be observed . Also, in the high-resolution TEM image, there are regions where a crystalline part can be clearly confirmed and regions where a crystalline part cannot be confirmed. The a-like OS film undergoes crystallization and growth of the crystalline part due to a very small amount of electron irradiation at the level of observation by TEM. may occur. On the other hand, in the case of a high-quality nc-OS film, crystallization due to electron irradiation to the extent observable by TEM is hardly seen.

[0216] Measurement of the crystal size of the a-like OS film and the nc-OS film can be carried out using a high-resolution TEM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit cell of the crystal of InGaZnO4 has three In-O layers and six Ga-Zn-O layers, and a total of nine layers are stacked in the c-axis direction in a layered structure. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, the value is determined to be 0.29 nm. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, where the distance between the lattice fringes is 0. At positions of 28 nm or more and 0.30 nm or less, each lattice fringe corresponds to the a-b plane of the crystal of InGaZn O4.

[0217] Oxide semiconductor films may have different film densities depending on the structure. For example, if the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing it with the film density of a single-crystal oxide semiconductor film having the same composition. For example, with respect to the film density of a single-crystal oxide semiconductor film, the film density of the a-like OS film is 78.6% or more and less than 92.3%. Also, for example, with respect to the film density of a single-crystal oxide semiconductor film, the film densities of the nc-OS film and the CAAC-OS film are 92.3% or more and less than 100%. Note that an oxide semiconductor film having a film density of less than 78% with respect to the film density of a single-crystal oxide semiconductor film is difficult to form itself.

[0218] The above will be described using specific examples. For example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the single-crystalline InGaZnO4 having a rhombohedral crystal structure has a film density of 6.357 g / cm 3 . Therefore, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1: 1 [atomic ratio], the film density of the a-like OS film is 5. 0 g / cm 3 or more and less than 5.9 g / cm 3 . Also, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1: 1:1 [atomic ratio], the film densities of the nc-OS film and the CA AC-OS film are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0219] Note that there may be cases where a single-crystalline oxide semiconductor film of the same composition does not exist. In such a case, by combining single-crystalline oxide semiconductor films with different compositions at an arbitrary ratio, the film density corresponding to a single-crystalline oxide semiconductor film of a desired composition can be calculated. The film density of a single-crystalline oxide semiconductor film of a desired composition may be calculated using a weighted average with respect to the ratio of combining single-crystalline oxide semiconductor films with different compositions. However, it is preferable to calculate the film density by combining as few types of single-crystalline oxide semiconductor films as possible. Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0220] Note that the substrate 510 is not limited to a mere support material, and other devices such as other transistors may be formed on it.

[0221] <Substrate> The substrate 510 is not limited to a mere support material, and other devices such as other transistors may be formed on it. ​It may be a substrate. In this case, one of the conductive layer 530, the conductive layer 541 and the conductive layer 542 of the OS transistor 501 may be electrically connected to the other devices described above.

[0222] <Underlying insulating layer> The insulating layer 511 serves to prevent the diffusion of impurities from the substrate 510. The insulating layer 512 preferably serves to supply oxygen to the oxide semiconductor layer 520. It can bear Therefore, the insulating layer 512 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, in TDS (Therma l Desorption Spectroscopy), when the surface temperature of the film is in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower the amount of oxygen molecules released is 1.0×10 [molecules / cm 18 3 or more. When the substrate 510 is a substrate on which other devices are formed, the insulating layer 511 is preferably planarized by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat .

[0223] The insulating layers 511 and 512 can be formed using insulating materials such as aluminum oxide, aluminum oxynitride, magnesium oxide , silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide , zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide , silicon nitride, silicon oxynitride, aluminum oxynitride, or a mixed material thereof. In this specification, oxynitride and ​​​is a material with a higher oxygen content than nitrogen, and a nitride oxide is a material with a higher nitrogen content than oxygen. The content is large.

[0224] <Gate electrode> The conductive layer 530 is made of a single substance, alloy, or compound mainly composed of these, which is made of a low-resistance material such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co) , ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt). It is preferably formed.

[0225] Also, the conductive layer 530 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film , a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film , a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, a single-layer structure of a Cu-Mn alloy film, a two-layer structure in which a Cu film is laminated on a Cu-Mn alloy film , a three-layer structure in which a Cu film is laminated on a Cu-Mn alloy film and a Cu-Mn alloy film is further laminated thereon. In particular, the Cu-Mn alloy film has a low electrical resistance and can form manganese oxide at the interface with an insulating film containing oxygen to prevent the diffusion of Cu. Therefore, it is preferable.

[0226] Also, the conductive layer 530 contains indium tin oxide and indium oxide containing tungsten oxide. substances, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide , indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide and other conductive materials having translucency can also be applied. Further, a laminated structure of the above-mentioned conductive material having translucency and the above metal element can also be adopted.

[0227] Here, when a certain transistor T has a pair of gates sandwiching a semiconductor film as in the case of OS transistors 501 to 506, a signal A may be applied to one gate and a fixed potential Vb may be applied to the other gate. When a certain transistor T has a pair of gates sandwiching a semiconductor film as in the case of OS transistors 501 to 506, a signal A may be applied to one gate and a fixed potential Vb may be applied to the other gate. When a certain transistor T has a pair of gates sandwiching a semiconductor film as in the case of OS transistors 501 to 506, a signal A may be applied to one gate and a fixed potential Vb may be applied to the other gate.

[0228] The signal A is, for example, a signal for controlling a conduction state or a non-conduction state. The signal A may be a digital signal taking two types of potentials, a potential V1 or a potential V2 (where V1 > V2). The signal A is, for example, a signal for controlling a conduction state or a non-conduction state. The signal A may be a digital signal taking two types of potentials, a potential V1 or a potential V2 (where V1 > V2). For example, the potential V1 may be set as a high power supply potential and the potential V2 may be set as a low power supply potential. The signal A may be an analog signal. For example, the potential V1 may be set as a high power supply potential and the potential V2 may be set as a low power supply potential. The signal A may be an analog signal.

[0229] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable because there is no need to separately provide a potential generation circuit for generating the fixed potential Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable because there is no need to separately provide a potential generation circuit for generating the fixed potential Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable because there is no need to separately provide a potential generation circuit for generating the fixed potential Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable because there is no need to separately provide a potential generation circuit for generating the fixed potential Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. When the fixed potential Vb is lowered, the threshold voltage VthA may be increased. As a result, the drain current when the gate-source voltage Vgs is 0V may be reduced, and the leakage current of the circuit having the transistor T may be reduced. When the fixed potential Vb is lowered, the threshold voltage VthA may be increased. As a result, the drain current when the gate-source voltage Vgs is 0V may be reduced, and the leakage current of the circuit having the transistor T may be reduced. For example, the fixed potential Vb may be set lower than the low power supply potential. Fixed In some cases, the threshold voltage VthA can be lowered by increasing the potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD can be improved, and the operating speed of the circuit having the transistor T can be improved in some cases. For example, the fixed potential Vb may be made higher than the low power supply potential.

[0230] Also, signal A may be applied to one gate of the transistor T, and signal B may be applied to the other gate. Signal B is, for example, a signal for controlling the conductive state or non-conductive state of the transistor T. Signal B may be a digital signal having two types of potentials, potential V3 or potential V4 (where V3 > V4). For example, potential V3 may be set as the high power supply potential, and potential V4 may be set as the low power supply potential. Signal B may be an analog signal.

[0231] When both signal A and signal B are digital signals, signal B may be a signal having the same digital value as signal A. In this case, the on-current of the transistor T can be improved, and the operating speed of the circuit having the transistor T can be improved in some cases. At this time, the potential V1 of signal A may be different from the potential V3 of signal B. Also, the potential V2 of signal A may be different from the potential V4 of signal B. For example, when the gate insulating film corresponding to the gate to which signal B is input is thicker than the gate insulating film corresponding to the gate to which signal A is input, the potential amplitude (V3 - V 4) of signal B may be made larger than the potential amplitude (V1 - V2) of signal A. By doing so, in some cases, the influence given by signal A and the influence given by signal B on the conductive state or non-conductive state of the transistor T can be made approximately the same.

[0232] When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the control of transistor T can be separately performed by signal A and signal B, and higher functions may be realized. For example, when transistor T is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, it may conduct only in this case, or when signal A is at potential V2 and signal B is at potential V4, it may be non-conductive only in this case. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having transistor T is operating and during the period when the circuit is not operating. Signal B may be a signal having different potentials according to the operation mode of the circuit. In this case, the potential of signal B may not be switched as frequently as that of signal A.

[0233] When both signal A and signal B are analog signals, signal B may be an analog signal having the same potential as signal A, an analog signal obtained by multiplying the potential of signal A by a constant, or an analog signal obtained by adding or subtracting a constant from the potential of signal A, etc. In this case, the on-current of transistor T may be increased, and the operating speed of the circuit having transistor T may be increased. Signal B may be an analog signal different from signal A. In this case, the control of transistor T can be separately performed by signal A and signal B, and higher functions may be realized. signal B, and higher functions may be realized.

[0234] Signal A may be a digital signal and signal B may be an analog signal. Signal A may be an analog signal, Signal B may be a digital signal.

[0235] Also, a fixed potential Va may be applied to one gate of the transistor T, and a fixed potential V b may be applied to the other gate. When fixed potentials are applied to both gates of the transistor T, the trans istor T may function as an element equivalent to a resistance element. For example, when the transistor T is an n-channel type, by increasing (decreasing ) the fixed potential Va or the fixed potential Vb, the effective resistance of the transistor may be decreased (increased). By increasing (decreasing) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by a transistor having only one gate may be obtained. There are cases.

[0236] <Gate insulating layer> The insulating layer 513 is formed of an insulating film having a single-layer structure or a laminated structure. The insulating layer 513 may contain one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film can be used. Also, the insulating layer 513 may be a laminate of the above materials. Further, the insulating layer 513 may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities. Also, the insulating layer 511 can be formed in the same manner as the insulating layer 513. The insulating layer 513 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride. In addition, the insulating layer 513 may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities. Also, the insulating layer 511 can be formed in the same manner as the insulating layer 513. The insulating layer 513 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

[0237] ​​​​Hafnium oxide has a higher relative permittivity than silicon oxide or silicon oxynitride. Therefore, compared with the case of using silicon oxide, the film thickness of the insulating layer 513 can be increased, so that the leakage current due to the tunneling current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative permittivity than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited thereto.

[0238] <Source electrode, drain electrode, back gate electrode> The conductive layer 541, the conductive layer 542, and the conductive layer 531 can be formed in the same manner as the conductive layer 530. The Cu-Mn alloy film has a low electrical resistance and can form manganese oxide at the interface with the oxide semiconductor layer 520 to prevent the diffusion of Cu. Therefore, it is preferably used for the conductive layer 541 and the conductive layer 542.

[0239] <Protective insulating layer> The insulating layer 514 preferably has a function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing such an insulating layer 514, the diffusion of oxygen from the oxide semiconductor layer 520 to the outside and the entry of hydrogen, water, etc. from the outside into the oxide semiconductor layer 520 can be prevented. As the insulating layer 514, for example, a nitride insulating film can be used. As the nitride insulating film, there are silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. Note that oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. ​​​​​ Instead of a nitride insulating film having a blocking effect of alkaline earth metals or the like, an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided. The oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided. The oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like Examples of the oxide insulating film having a blocking effect include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. gallium, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide nium, hafnium oxynitride, and the like.

[0240] The aluminum oxide film has a high blocking effect that does not allow the film to permeate both impurities such as hydrogen and moisture and oxygen, so it is preferable for application to the insulating layer 514. Therefore, the aluminum oxide film prevents the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide semiconductor layer 520 during and after the manufacturing process of the transistor, and prevents the release of oxygen, which is the main component material constituting the oxide semiconductor layer 520, from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. characteristics of the transistor, hydrogen, moisture, and other impurities that are factors causing fluctuations in the electrical characteristics of the transistor are prevented from mixing into the oxide semiconductor layer 520, and oxygen, which is the main component material constituting the oxide semiconductor layer 520, is prevented from being released from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. characteristics of the transistor, hydrogen, moisture, and other impurities that are factors causing fluctuations in the electrical characteristics of the transistor are prevented from mixing into the oxide semiconductor layer 520, and oxygen, which is the main component material constituting the oxide semiconductor layer 520, is prevented from being released from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. characteristics of the transistor, hydrogen, moisture, and other impurities that are factors causing fluctuations in the electrical characteristics of the transistor are prevented from mixing into the oxide semiconductor layer 520, and oxygen, which is the main component material constituting the oxide semiconductor layer 520, is prevented from being released from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. characteristics of the transistor, hydrogen, moisture, and other impurities that are factors causing fluctuations in the electrical characteristics of the transistor are prevented from mixing into the oxide semiconductor layer 520, and oxygen, which is the main component material constituting the oxide semiconductor layer 520, is prevented from being released from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. characteristics of the transistor, hydrogen, moisture, and other impurities that are factors causing fluctuations in the electrical characteristics of the transistor are prevented from mixing into the oxide semiconductor layer 520, and oxygen, which is the main component material constituting the oxide semiconductor layer 520, is prevented from being released from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor. characteristics of the transistor, hydrogen, moisture, and other impurities that are factors causing fluctuations in the electrical characteristics of the transistor are prevented from mixing into the oxide semiconductor layer 520, and oxygen, which is the main component material constituting the oxide semiconductor layer 520, is prevented from being released from the oxide semiconductor. It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor.

[0241] <Interlayer insulating layer> In addition, it is preferable that an insulating layer 515 is formed on the insulating layer 514. The insulating layer 515 can be formed of an insulating film having a single-layer structure or a laminated structure. The insulating film may include one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide lium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide neodymium, hafnium oxide, and tantalum oxide. can be used.

[0242] <Film formation method> As film formation methods for insulating films, conductive films, semiconductor films, etc. that make up semiconductor devices, sputtering methods, and plasma CVD methods are representative. Other methods, for example, those formed by thermal CVD are also possible. As thermal CVD methods, for example, MOCVD (Metal Organic Chemical Vapor Deposition) methods can be used. Also, ALD (Atomic Layer Deposition) methods may be used.

[0243] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. The thermal CVD method sets the inside of the chamber to atmospheric pressure or reduced pressure, sends the source gas and the oxidant into the chamber simultaneously, and reacts them near or on the substrate to deposit a film on the substrate. Also, the ALD method sets the inside of the chamber to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially introduced into the chamber, and film formation may be performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are supplied to the chamber in order, and an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the first source gas so that the plurality of types of source gases do not mix, and the second

[0244] source gas is introduced. When an inert gas is introduced simultaneously, the inert gas becomes a carrier gas, and an inert gas may also be introduced simultaneously when the second source gas is introduced. Also, instead of introducing an inert gas, after evacuating the first source gas by vacuum exhaust, the second source gas is introduced. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are supplied to the chamber in order, and an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the first source gas so that the plurality of types of source gases do not mix, and the second source gas is introduced. When an inert gas is introduced simultaneously, the inert gas becomes a carrier gas, and an inert gas may also be introduced simultaneously when the second source gas is introduced. Also, instead of introducing an inert gas, after evacuating the first source gas by vacuum exhaust, 2nd source gas is introduced. When introducing an inert gas simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when introducing the 2nd source gas. Also, instead of introducing an inert gas, after exhausting the first source gas by vacuum evacuation, the second source gas is introduced. When introducing an inert gas simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when introducing the second source gas. Also, instead of introducing an inert gas, after exhausting the first source gas by vacuum evacuation, the second source gas is introduced. Also, instead of introducing an inert gas, after exhausting the first source gas by vacuum evacuation, , the second source gas may be introduced. The first source gas adsorbs on the surface of the substrate to form a first monolayer subatomic layer, and reacts with the subsequently introduced second source gas to form a second monolayer subatomic layer on the first subatomic layer to form a thin film. By repeating this gas introduction sequence multiple times until the desired thickness is reached, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, making it suitable for fabricating fine FETs.

[0245] The conductive films and semiconductor films disclosed in the embodiments described so far can be formed by film-forming methods such as MOCVD and ALD. For example, when forming an InGaZnO X (X>0) film , trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is (CH3)3In. Also, the chemical formula of trimethylgallium is (CH3)3Ga. Also, the chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula (C2H5)3Ga) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0246] For example, when forming a tungsten film using a film-forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then a tungsten film is formed using WF6 gas and H2 gas. Note that SiH 4 gas may be used instead of B2H6 gas.

[0247] For example, when forming an oxide semiconductor film, such as InGaZnO X (X >0) film, using a film formation apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially introduced repeatedly to form an InO2 layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced repeatedly to form a GaO layer. Further, after that, Zn(CH3)2 gas and O3 gas are sequentially introduced repeatedly to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases may be mixed to form mixed compound layers such as InGaO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer etc. Note that instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar may be used, but it is more preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used as well. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also (CH3)2 gas may be used.

[0248] Also, in this embodiment, a top gate type transistor structure has been shown, but it is not limited to this . For example, a bottom gate type transistor or a planar type transistor etc can be applied.

[0249] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments .

[0250] (Embodiment 4) In this embodiment, an example of the cross-sectional structure of a semiconductor device according to one aspect of the present invention will be described.

[0251] <Configuration Example 1> ​FIG. 18 shows a cross-sectional view of transistor 301, transistor 302, and resistor section 303. Note that transistor 302 can be used as transistor 11 in FIG. 1(A), and resistor section 303 can be used as resistor section 12 in FIG. 1 (A). Also, transistor 301 connected to transistor 302 can be used as a transistor that constitutes internal circuit 14 in FIG. 1(A), etc. FIG. 18 illustrates a cross-sectional structure of a semiconductor device in a case where transistor 301 having a channel formation region is located in a first layer on a single-crystalline semiconductor substrate, and transistor 302 and resistor section 303 which are OS transistors are located in a second layer on the first layer. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc.

[0252] Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc. Transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single-crystalline. When forming transistor 301 using a thin film of silicon, the thin film may be made of amorphous silicon produced by a vapor growth method such as plasma CVD method or a sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by a treatment such as laser annealing, single-crystalline silicon obtained by implanting hydrogen ions or the like into a single-crystalline silicon wafer and peeling off the surface layer portion, etc.

[0253] As the semiconductor substrate 310 on which transistor 301 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, etc. can be used. FIG. 18 illustrates a case where a single-crystalline silicon substrate is used as the semiconductor substrate 310. As the semiconductor substrate 310 on which transistor 301 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, etc. can be used. FIG. 18 illustrates a case where a single-crystalline silicon substrate is used as the semiconductor substrate 310. As the semiconductor substrate 310 on which transistor 301 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, etc. can be used. FIG. 18 illustrates a case where a single-crystalline silicon substrate is used as the semiconductor substrate 310.

[0254] Also, transistor 301 is electrically isolated by an element isolation method. The element isolation method and Thus, methods such as the selective oxidation method (LOCOS method: Local Oxidation of Silicon on method), the trench isolation method (STI method: Shallow Trench Isolation on) can be used. FIG. 18 illustrates a case where transistor 30 1 is electrically isolated using the trench isolation method. Specifically, in FIG. 18, after forming a trench in semiconductor substrate 310 by etching or the like, an element isolation region 311 formed by embedding an insulator containing silicon oxide or the like in the trench illustrates a case where transistor 301 is elementarily separated.

[0255] Transistor 301 has impurity regions 312a and 312b. The impurity regions 312a and 312b function as the source or drain of transistor 301

[0256] An insulating film 321 is provided on transistor 301, and an opening is formed in insulating film 321 . And in the opening, a conductive layer 313a connected to impurity region 312a and a non-conductive layer 313a connected to impurity region 312a are formed. pure conductive layer 313b connected to impurity region 312b are formed. Further, conductive layer 313a is connected to conductive layer 322a formed on insulating film 321, and conductive layer 313b is connected to conductive layer 322b formed on insulating film 321.

[0257] An insulating film 323 is provided on conductive layers 322a and 322b, and an opening is formed in insulating film 323 . And in the opening, a conductive layer 324 connected to conductive layer 322a is formed. Further, conductive layer 324 is connected to conductive layer 3 formed on insulating film 323. 25 is connected. ​​​​

[0258] An insulating film 326 is provided over the conductive layer 325 .

[0259] The transistor 302, which is an OS transistor, is provided over the insulating film 326. The transistor 302 includes an oxide semiconductor layer 341 over an insulating film 326 and an oxide semiconductor The conductive layer 343a and the conductive layer 343b over the oxide semiconductor layer 341, the conductive layer 3 43a, an insulating film 344 on the conductive layer 343b, and an oxide semiconductor layer The conductive layer 343a and the conductive layer 345 have an area overlapping with the conductive layer 341. The electrode layer 343b functions as a source electrode or a drain electrode of the transistor 302. The insulating film 344 functions as a gate insulating film of the transistor 302, and the conductive layer 345 serves as a gate electrode of the transistor 302.

[0260] In addition, a resistor portion 303 is provided on the insulating film 326. 26, an oxide semiconductor layer 342, a conductive layer 343b and a conductive layer 343c on the oxide semiconductor layer 342, and 43c, the oxide semiconductor layer 342, the conductive layer 343b, and the insulating film 344 on the conductive layer 343c. Note that the oxide semiconductor layer 342 functions as a resistance layer in the resistance portion 303. do.

[0261] An insulating film 346 is provided on the insulating film 344 and the conductive layer 345. A conductive layer 352 and a conductive layer 353 are provided on the insulating layer 346. The conductive layer 325 is connected to the insulating film 326, the insulating film 344, and the conductive layer 325 through an opening provided in the insulating film 346. The conductive layer 3 is exposed through the openings provided in the insulating films 344, 346, and 351. It is connected to 43c. The conductive layer 353 is connected to the conductive layer 343a through the openings provided in the insulating film 344 and the insulating film 346.

[0262] In addition, in FIG. 18, a case where the transistor 302 has a single gate structure having one channel formation region corresponding to one conductive layer 345 is illustrated. However, the transistor 302 may have a multi-gate structure having a plurality of channel formation regions in the oxide semiconductor layer 341 by having a plurality of gate electrodes connected to each other. Further, a structure having a back gate may also be used.

[0263] As described above, by laminating the transistor 301, the transistor 302, and the resistor 303, the area of the semiconductor device can be reduced. Further, the transistor 302 and the resistor 303 may be formed by lamination.

[0264] The transistor 302 and the resistor 303 may be formed as the transistor and the resistor 101 shown in FIG. 7. Further, the transistor 302 may be formed as the transistor shown in FIGS. 10 to 16.

[0265] The configuration and method shown in this embodiment can be appropriately combined with the configuration and method shown in other embodiments.

[0266] (Embodiment 5) In this embodiment, an example of applying the semiconductor device described in the above embodiment to an electronic component and an example of applying the electronic component to an electronic device including the same will be described with reference to FIGS. 19 and 20.

[0267] In FIG. 19(A), an example of applying the semiconductor device described in the above embodiment to an electronic component will be described. Note that an electronic component is also referred to as a semiconductor package or an IC package. There are a plurality of standards and names for this electronic component depending on the terminal extraction direction and the shape of the terminal. Therefore, in this embodiment, an example thereof will be described. The circuit section composed of transistors as shown in the above embodiment is completed by assembling a plurality of components detachable from the printed circuit board through an assembly process (post-process ). The post-process can be completed by going through each process shown in FIG. 19(A). Specifically, after the element substrate obtained in the pre-process is completed (step S1), the back surface of the substrate is ground

[0268] (step S2). By thinning the substrate at this stage, warping of the substrate in the pre-process etc. is reduced to achieve miniaturization as a component.

[0269] A dicing process is performed to grind the back surface of the substrate and separate the substrate into a plurality of chips. Then, a die bonding process is performed to pick up the separated chips individually and mount and bond them on the lead frame (step S3). The adhesion between the chip and the lead frame in this die bonding process can be selected appropriately according to the product, such as adhesion with resin or adhesion with tape. Note that the die bonding process may be performed by mounting and bonding on an interposer.

[0270] Next, wire bonding is performed to electrically connect the leads of the lead frame and the electrodes on the chip with a thin metal wire (step S4). As the thin metal wire, a silver wire or a gold

[0271] Wires can be used. Also, wire bonding can use ball bonding or wedge bonding.

[0272] The wire-bonded chip is subjected to a molding process (step S5) of being encapsulated with an epoxy resin or the like. By performing the molding process, the inside of the electronic component is filled with resin, which can reduce damage to the built-in circuit parts and wires due to mechanical external forces, and can also reduce deterioration of characteristics due to moisture and dust.

[0273] Next, the leads of the lead frame are plated. Then, the leads are cut and formed (step S6). This plating process prevents the leads from rusting and enables more reliable soldering when later mounted on a printed circuit board.

[0274] Next, a printing process (marking) is performed on the surface of the package (step S7). Then, after the final inspection process (step S8), the electronic component is completed (step S9).

[0275] The electronic component described above can be configured to include the semiconductor device described in the above embodiment. Therefore, an electronic component with reduced power consumption can be realized.

[0276] In addition, a perspective schematic diagram of the completed electronic component is shown in FIG. 19(B). Also, the electronic component 1700 on the circuit board 1704 shown in FIG. 19(B) is shown in FIG. 19(C). In FIG. 19(B), as an example of an electronic component, a perspective schematic diagram of a QFP (Quad Flat Package) is shown. The electronic component 1700 shown in FIGS. 19(B) and 19(C) has leads 170 ​​​​​​​1 and a circuit section 1703. The electronic component 1700 shown in FIG. 19(B) is, for example, The electronic components 1700 are mounted on a printed circuit board 1702. Each of them is electrically connected on a printed circuit board 1702, and can be mounted inside an electronic device. The completed circuit board 1704 is installed inside an electronic device or the like.

[0277] The semiconductor device or electronic component according to one embodiment of the present invention is applicable to display devices, personal computers, etc. Computers, image playback devices equipped with recording media (typically DVD: Digital Vers It has a display that can play recording media such as a tablet disc and display the images. In addition, the semiconductor device according to one embodiment of the present invention can be used in a semiconductor device. Examples of electronic devices that can be used include mobile phones, handheld game consoles, personal digital assistants, and e-books. Terminals, cameras such as video cameras and digital still cameras, goggle-type displays (headsets, etc.) mounted displays), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, multifunction printers , automated teller machines (ATMs), vending machines, medical equipment, etc. Specific examples of electronic devices are shown in FIG.

[0278] FIG. 20A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The semiconductor device according to one embodiment of the present invention includes a portable game machine. The portable game machine shown in FIG. 20(A) can be used for various integrated circuits. It has a display unit 5003 and a display unit 5004, but the number of display units of the portable game machine is not limited to this. is not limited to this.

[0279] FIG. 20(B) is a portable information terminal, which has a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. A semiconductor device according to an aspect of the present invention can be used for various integrated circuits of the portable information terminal. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection unit 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection unit 5605. The video on the first display unit 5603 can be switched according to the angle between the first housing 5601 and the second housing 5602 at the connection unit 5605. It may also be configured as follows. Further, at least one of the first display unit 5603 and the second display unit 5604 may use a display device with a function as a position input device added thereto. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

[0280] FIG. 20(C) is a notebook personal computer, which has a housing 5401, a display unit 5402 a keyboard 5403, a pointing device 5404, etc. A semiconductor device according to an aspect of the present invention can be used for various integrated circuits of the notebook personal computer.

[0281] Figure 20(D) shows an electric refrigerator, which includes a housing 5301, a refrigerator door 5302, a freezer door 5303, etc. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of the electric refrigerator.

[0282] Figure 20(E) shows a video camera, which includes a first housing 5801, a second housing 5802, a display unit 58 03, operation keys 5804, a lens 5805, a connection part 5806, etc. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of the video camera. The operation keys 5 804 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection part 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection part 5806. A configuration may be adopted to switch the video on the display unit 5803 according to the angle between the first housing 5801 and the second housing 5802 at the connection part 5806.

[0283] Figure 20(F) shows an automobile, which includes a vehicle body 5101, wheels 5102, a dashboard 5103, lights 5104, etc. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of the automobile.

[0284] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments.

Description of Reference Numerals

[0285] 10 Semiconductor device 11 Transistor 12 Resistance part 13 Input / output terminal​ 14 Internal circuit 15 Power supply line 16 Signal line 17 Control signal generation circuit 20 Semiconductor device 21 Transistor 22 Resistance part 23 Input / output terminal 24 Internal circuit 25 Power supply line 26 Signal line 27 Control signal generation circuit 30 Semiconductor device 31 Transistor 33 Input / output terminal 34 Internal circuit 35 Power supply line 36 Signal line 37 Control signal generation circuit 40 Semiconductor device 42 Resistance part 43 Input / output terminal 44 Internal circuit 45 Power supply line 46 Signal line 50 Semiconductor device 51 Transistor 52 Resistance part 53 Input / output terminal 54 Internal circuit 55 Power supply line 56 Signal line 57 Control signal generation circuit 58 Transistor 60 Semiconductor device 61 Transistor 62 Resistance part 63 Input / output terminal 64 Internal circuit 65 Power supply line 66 Signal line 67 Control signal generation circuit 68 Transistor 69 Capacitor element 70 Semiconductor device 80 Semiconductor device 100 Transistor 101 Resistance part 110 Substrate 112 Insulating layer 113 Insulating layer 114 Insulating layer 115 Insulating layer 120 Oxide semiconductor layer 121 Oxide semiconductor layer 122 Oxide semiconductor layer 130 Conductive layer 131 Conductive layer 141 Conductive layer 142 Conductive layer 143 Conductive layer 200 Resistance part 301 Transistor 302 Transistor 303 Resistance part 310 Semiconductor substrate 311 Element isolation region 312a Impurity region 312b Impurity region 313a Conductive layer 313b Conductive layer 321 Insulating film 322a Conductive layer 322b Conductive layer 323 Insulating film 324 Conductive layer 325 Conductive layer 326 Insulating film 341 Oxide semiconductor layer 342 Oxide semiconductor layer 343a Conductive layer 343b Conductive layer 343c Conductive layer 344 Insulating film 345 Conductive layer 346 Insulating film 351 Insulating film 352 Conductive layer 353 Conductive layer 400 Transistor 401 Resistance part 402 Transistor 403 Transistor 404 Resistance part 405 Resistance part 406 Resistance part 410 Conductive layer 411 Conductive layer 412 Insulating layer 414 Oxide semiconductor layer 416 Oxide semiconductor layer 418 Conductive layer 420 Conductive layer 422 Conductive layer 424 Insulating layer 428 Insulating layer 430 Conductive layer 432 Conductive layer 434 Insulating layer 435 Conductive layer 438 Insulating layer 440 Conductive layer 442 Conductive layer 444 Oxide semiconductor layer 446 Insulating layer 448 Conductive layer 450 Insulating layer 501 OS transistor 502 OS transistor 503 OS transistor 504 OS transistor 505 OS transistor 506 OS transistor 510 Substrate 511 Insulating layer 512 Insulating layer 513 Insulating layer 514 Insulating layer 515 Insulating layer 516a Conductor 516b Conductor 520 Oxide semiconductor layer 521 Oxide semiconductor layer 522 Oxide semiconductor layer 523 Oxide semiconductor layer 530 Conductive layer 531 Conductive layer 532 Oxide semiconductor layer 541 Conductive layer 542 Conductive layer 551 Layer 552 Layer 560 Conductive layer 1700 Electronic component 1701 Lead 1702 Printed circuit board 1703 Circuit section 1704 Circuit board 5001 Housing 5002 Housing 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Vehicle body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Refrigerator door 5303 Freezer door 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing device 5601 Housing 5602 Housing 5603 Display section 5604 Display section 5605 Connection section 5606 Operation key 5801 Housing 5802 Housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection section

Claims

1. It has an oxide semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer, The first conductive layer has a region disposed above the oxide semiconductor layer, The second conductive layer has a region disposed above the oxide semiconductor layer, The oxide semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region between the first region and the second region, The insulating layer has a region in contact with the entire lower surface of the oxide semiconductor layer, The third conductive layer is disposed below the insulating layer so as to have a region overlapping with the first region, a region overlapping with the third region, and a region overlapping with the second region, The oxide semiconductor layer has a function as a resistor, The oxide semiconductor layer does not have a channel formation region of a transistor, a semiconductor device.

2. It has an oxide semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer, The first conductive layer has a region disposed above the oxide semiconductor layer, The second conductive layer has a region disposed above the oxide semiconductor layer, The oxide semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region between the first region and the second region, The insulating layer has a region in contact with the entire lower surface of the oxide semiconductor layer, The third conductive layer is disposed below the insulating layer so as to have a region overlapping with the first region, a region overlapping with the third region, and a region overlapping with the second region, The oxide semiconductor layer has a function as a non-linear resistor, The oxide semiconductor layer does not have a channel formation region of a transistor, a semiconductor device.

3. It has an oxide semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer, The first conductive layer has a region disposed above the oxide semiconductor layer, The second conductive layer has a region disposed above the oxide semiconductor layer, The oxide semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region between the first region and the second region, The insulating layer has a region in contact with the entire lower surface of the oxide semiconductor layer, The third conductive layer is disposed below the insulating layer so as to have a region overlapping with the first region, a region overlapping with the third region, and a region overlapping with the second region. The oxide semiconductor layer has a function as a resistor. The oxide semiconductor layer does not have a channel formation region of a transistor. The semiconductor device, wherein the third conductive layer does not have a region in contact with another conductive layer.

4. An oxide semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer has a region disposed above the oxide semiconductor layer. The second conductive layer has a region disposed above the oxide semiconductor layer. The oxide semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region between the first region and the second region. The insulating layer has a region in contact with the entire lower surface of the oxide semiconductor layer. The third conductive layer is disposed below the insulating layer so as to have a region overlapping with the first region, a region overlapping with the third region, and a region overlapping with the second region. The oxide semiconductor layer has a function as a non-linear resistor. The oxide semiconductor layer does not have a channel formation region of a transistor. The semiconductor device, wherein the third conductive layer does not have a region in contact with another conductive layer.

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