Semiconductor device

Abstract

To miniaturize a semiconductor device, and to reduce an area of a drive circuit of a semiconductor device having a memory cell.SOLUTION: A semiconductor device comprises: an element formation layer having at least a first semiconductor element; first wiring provided on the element formation layer; an interlayer film provided on the first wiring; and second wiring superposed with the first wiring via the interlayer film. The first wiring, the interlayer film, and the second wiring configure a second semiconductor element. The first wiring and the second wiring are supplied with the same potential.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using semiconductor elements.

Background Art

[0002] Semiconductor devices such as non-volatile memory devices capable of repeatedly writing and erasing data, such as EEPROMs and flash memories, are highly convenient and resistant to physical shocks. Therefore, they are mainly used in portable storage media such as USB memories and memory cards, and RF tags, which are media for wirelessly reading information, such as RFID (Radio frequency identification) media, and are widely available on the market. The above semiconductor device has a transistor that functions as a memory element in each memory cell. And the above transistor has an electrode called a floating gate between the gate electrode and the semiconductor film, which is an active layer. Data can be stored by accumulating charges in the floating gate. The following Patent Document 1 and Patent Document 2 describe a thin film transistor having a floating gate formed on a glass substrate. formed on a glass substrate.

[0003]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, when forming a circuit having a plurality of signal lines in a driver circuit of a semiconductor device, In order to reduce the area of ​​the driver circuit, the number of wiring layers is increased and signal lines are formed on each layer. However, simply increasing the number of wiring layers does not necessarily mean increasing the number of wiring masks. Increasing the number of sheets is not preferable because it increases costs.

[0006] In particular, a semiconductor device such as a memory device includes a memory cell and a drive circuit for driving the memory cell. The size of the semiconductor device is limited by the area of ​​the driver circuit. Even if the cell area is reduced, if the driving circuit area cannot be reduced, the semiconductor Therefore, it is not possible to reduce the area of ​​the driving circuit. This is important in miniaturizing semiconductor devices.

[0007] In view of the above, an object of one embodiment of the present invention is to miniaturize a semiconductor device.

[0008] Another embodiment of the present invention is to reduce the area of ​​a driver circuit of a semiconductor device having memory cells. One of the challenges we face is to: [Means for solving the problem]

[0009] One embodiment of the disclosed invention is a semiconductor device including an element formation layer having at least a first semiconductor element; A first wiring provided on the formation layer, an interlayer film provided on the first wiring, and a and a second wiring layer overlapping the first wiring layer. , constitute a second semiconductor element, and the first wiring and the second wiring are supplied with the same potential. The semiconductor device is an interconnect.

[0010] Another aspect of the disclosed invention is element formation having at least a first semiconductor element layer, a first wiring provided on the element formation layer, an interlayer film provided on the first wiring, and a layer having a second wiring overlapping the first wiring via the interlayer film, the first wiring, the interlayer film, and the second wiring constitute a second semiconductor element, and the first wiring and the second wiring are wirings to which signals of the same phase are supplied, which is a semiconductor device.

[0011] Another aspect of the disclosed invention is a semiconductor device including a memory cell and a drive circuit portion of the memory cell. The memory cell includes a first transistor including a first channel formation region, a first gate electrode, a first source electrode, and a first drain electrode, a second channel formation region, a second gate electrode, a second source electrode, and a second drain electrode, a second transistor including a capacitor element, and at least a part of the second transistor is provided to overlap the first transistor. The drive circuit portion includes a first wiring formed in the same process as the second source electrode or the second drain electrode, and a second wiring that overlaps the first wiring via an interlayer film and is formed in the same process as the second gate electrode, and has a semiconductor element including the second wiring. The first wiring and the second wiring are wirings to which the same potential is supplied, which is a semiconductor device.

[0012] Another aspect of the disclosed invention is a semiconductor device including a memory cell and a drive circuit portion of the memory cell. The memory cell includes a first transistor including a first channel formation region, a first gate electrode, a first source electrode, and a first drain electrode, a second channel formation region, a second gate electrode, a second source electrode, and a second drain electrode, a second transistor A semiconductor device having a transistor and a capacitor element, wherein at least a part of the second transistor overlaps with the first transistor, and the drive circuit section includes a first wiring formed in the same process as the second source electrode or the second drain electrode, and a second wiring that overlaps with the first wiring via an interlayer film and is formed in the same process as the second gate electrode. The first wiring and the second wiring are wirings to which signals of the same phase are supplied. In the semiconductor device, the semiconductor element may be a level shifter. Further, the thickness of the interlayer film is preferably 10 nm or more and 100 nm or less. In addition, in this specification and the like, the terms "above" and "below" do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating film", those including other components between the gate insulating film and the gate electrode are excluded. Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally define these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are employed or when the direction of current changes in the circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0013] In the semiconductor device, the semiconductor element may be a level shifter. Further, the thickness of the interlayer film is preferably 10 nm or more and 100 nm or less. In addition, in this specification and the like, the terms "above" and "below" do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating film", those including other components between the gate insulating film and the gate electrode are excluded.

[0014] Also, in this specification and the like, the terms "above" and "below" do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating film", those including other components between the gate insulating film and the gate electrode are excluded. For example, in the expression "gate electrode on the gate insulating film", those including other components between the gate insulating film and the gate electrode are excluded. For example, in the expression "gate electrode on the gate insulating film", those including other components between the gate insulating film and the gate electrode are excluded. For example, in the expression "gate electrode on the gate insulating film", those including other components between the gate insulating film and the gate electrode are excluded.

[0015] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally define these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. For example, an "electrode" may be used as a part of a "wiring", and vice versa. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0016] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are employed or when the direction of current changes in the circuit operation. In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are employed or when the direction of current changes in the circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0017] In addition, in this specification, "electrically connected" means "something that has some electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0018] In addition, in this specification, the term "same potential" includes "approximately the same potential." The technical idea is to form a thin insulating film between conductive layers (first wiring and The object of the present invention is to make each of the first wiring (first wiring and second wiring) function as a wiring and to suppress parasitic capacitance. Therefore, a first potential (for example, VDD) is supplied to the first wiring, and a second potential (for example, VDD) is supplied to the second wiring. In comparison with the case where a second potential (e.g. GND) is supplied from a power line different from the first potential, This includes "approximately the same potential" such as a potential that can sufficiently reduce the parasitic capacitance (to one percent or less). In addition, for example, the difference in the degree of potential deviation caused by wiring resistance etc. is fully tolerated. The "in-phase" potential includes the "approximately in-phase" potential. Effect of the Invention

[0019] By using one embodiment of the present invention, a miniaturized semiconductor device can be provided. .

[0020] In addition, by using one embodiment of the present invention, a memory cell having a reduced area for a driver circuit can be provided. It is possible to provide a semiconductor device having the above structure.

Brief Description of the Drawings

[0021]

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Mode for Carrying Out the Invention

[0022] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows Not limited to the description, those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

[0023] Note that the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for the sake of easy understanding. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

[0024] Note that ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0025] (Embodiment 1) In this embodiment, the basic configuration of a semiconductor device according to an aspect of the disclosed invention will be described with reference to the drawings.

[0026] FIG. 1 is a diagram showing the configuration of a semiconductor device according to an aspect of the present invention. FIG. 1(A) schematically shows the cross-sectional structure of the semiconductor device, and FIG. 1(B) schematically shows the circuit configuration.

[0027] FIG. 1(A) shows the structure of a semiconductor device in which a layer (hereinafter, element formation layer) 301 in which semiconductor elements such as transistors are formed, a first wiring 302, a first interlayer film 305, a second wiring 303, a second interlayer film 306, and a third wiring 304 are laminated on a substrate 300. The element formation layer 301 is a region in which semiconductor elements such as capacitor elements and resistor elements can be formed, not limited to transistors. In FIG. 1, the film thickness of the first interlayer film 305 is ​​​​​​​​​​It has a thin structure. The first wiring 302, the second wiring 303, and the third wiring 304 are each formed of a single-layer or laminated conductive layer. Also, the first interlayer film 305 and the second interlayer film 306 are each formed of a single-layer or laminated insulating layer. Moreover, FIG. 1(B) shows a diagram representing the circuit configuration of the circuit 100 and the arrangement relationship of the wirings. The circuit 100 has a wiring 303a arranged across the circuit 100, a wiring 302a branched from the wiring 303a, and a transistor 101, and has a region 102 where the wiring 303a and the wiring 302a are arranged overlapping each other. Also, an input signal is applied to the wiring 303a, and it is connected to the gate electrode of the transistor 101 via the wiring 302a conducted with the wiring 303a. Note that the wiring 303a is formed using the second wiring 303 in FIG. 1(A), and the wiring 302a is formed using the first wiring 302 in FIG. 1(A).

[0028] In general, a semiconductor device having a cross-sectional structure as shown in FIG. 1(A) has the following problems. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Moreover, FIG. 1(B) shows a diagram representing the circuit configuration of the circuit 100 and the arrangement relationship of the wirings. The circuit 100 has a wiring 303a arranged across the circuit 100, a wiring 302a branched from the wiring 303a, and a transistor 101, and has a region 102 where the wiring 303a and the wiring 302a are arranged overlapping each other. Also, an input signal is applied to the wiring 303a, and it is connected to the gate electrode of the transistor 101 via the wiring 302a conducted with the wiring 303a. Note that the wiring 303a is formed using the second wiring 303 in FIG. 1(A), and the wiring 302a is formed using the first wiring 302 in FIG. 1(A). Moreover, FIG. 1(B) shows a diagram representing the circuit configuration of the circuit 100 and the arrangement relationship of the wirings. The circuit 100 has a wiring 303a arranged across the circuit 100, a wiring 302a branched from the wiring 303a, and a transistor 101, and has a region 102 where the wiring 303a and the wiring 302a are arranged overlapping each other. Also, an input signal is applied to the wiring 303a, and it is connected to the gate electrode of the transistor 101 via the wiring 302a conducted with the wiring 303a. Note that the wiring 303a is formed using the second wiring 303 in FIG. 1(A), and the wiring 302a is formed using the first wiring 302 in FIG. 1(A). Moreover, FIG. 1(B) shows a diagram representing the circuit configuration of the circuit 100 and the arrangement relationship of the wirings. The circuit

[0029] 100 has a wiring 303a arranged across the circuit 100, a wiring 302a branched from the wiring 303a, and a transistor 101, and has a region 102 where the wiring 303a and the wiring 302a are arranged overlapping each other. Also, an input signal is applied to the wiring 303a, and it is connected to the gate electrode of the transistor 101 via the wiring 302a conducted with the wiring 303a. Note that the wiring 303a is formed using the second wiring 303 in FIG. 1(A), and the wiring 302a is formed using the first wiring 302 in FIG. 1(A). Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlapping each other. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 becomes large, and the circuit operation becomes slow or does not operate. To avoid this influence, a configuration in which only one of the first wiring 302 and the second wiring 303 is used is possible, but there is a problem that the circuit area becomes large because the number of available wirings is reduced by one.

[0030] On the other hand, if the configuration is as shown in FIG. 1(B), even though a large parasitic capacitance is formed in the region 102 where the wiring 303a and the wiring 302a overlap, the influence on the signal delay time can be suppressed. This is because since the wiring 303a and the wiring 302a are conducting, the two terminals where the parasitic capacitance is formed are substantially at the same potential, and almost no charging and discharging occur to these two terminals. As a result, a circuit can be configured using the region where the first wiring and the second wiring are overlapped and separated by a thin interlayer film (the first interlayer film 305 in FIG. 1(A)), and a smaller circuit area can be realized compared to the case where only one of the first wiring and the second wiring is used. As a result, a small semiconductor device can be realized. By using the circuit configuration and the wiring arrangement relationship shown in FIG. 1(B), regardless of how thin the first interlayer film 305 shown in FIG. 1(A) is, the region where the first wiring 302 and the second wiring 303 overlap can be used as a part of the circuit, which is effective for reducing the circuit area. On the other hand, in a semiconductor device, when the first interlayer film 305 is used as the dielectric of a capacitive element or the gate insulating film of a transistor, the thickness of the first interlayer film 305 is preferably 10 nm or more and 300 nm or less, more preferably 10 nm or more and 100 nm or less, and still more preferably 10 nm or more and 30 nm or less. In the configuration shown in FIG. 1(B), the film thickness of the wiring 302a may be thinner than the film thickness of the wiring 303a. In such a case, the sheet resistance of the wiring 302a

[0031]

[0032]

[0033] It becomes larger than the sheet resistance of the wiring 303a, and there is a concern that the wiring 302a may have a large wiring resistance. However, by using the wiring 303a for a long wiring arranged across the circuit 100, the wiring 302a can be used only for short wirings, so that the wiring resistance of the wiring 302a can be reduced. As a result, it becomes possible to suppress the influence on the circuit operation due to the wiring resistance. On the other hand, in the manufacturing process of the semiconductor device, by reducing the film thickness of the wiring 302a, the step generated by the wiring 302a arranged in the lower layer becomes smaller, and disconnection of the wiring 303a and short - circuit between the wiring 302a and the wiring 303a can be prevented, which is preferable. As an example, the film thickness of the wiring 302a is preferably 50 nm or more and 150 nm or less. By setting such a value, a large sheet resistance can be obtained within the range where the influence on the circuit operation due to the wiring resistance of the wiring 302a can be suppressed, and the influence of the step generated by the wiring 302a in the manufacturing process can be suppressed. Moreover, in FIG. 1(B), the case where the wiring 302a and the gate electrode of the transistor 101 are electrically connected within the circuit 100 is shown as a representative example, but the present embodiment is not limited to this. The wiring 302a may be connected to the gate electrodes of a plurality of transistors. Also, in addition to the case where the wiring 302a is connected to the gate electrode of the transistor, the wiring 302a may be connected to the source electrode or the drain electrode of the transistor, or may be connected to a semiconductor element such as a capacitor element or a resistor element. Furthermore, as another semiconductor device different from the example shown in FIG. 1(B), the circuit configuration and the wiring layout shown in FIG. 2

[0034] While, in the manufacturing process of the semiconductor device, by making the film thickness of the wiring 302a thinner, the step caused by the wiring 302a disposed in the lower layer becomes smaller, and disconnection of the wiring 303a and short - circuit between the wiring 302a and the wiring 303a can be prevented, which is preferable. As an example, the film thickness of the wiring 302a is preferably 50 nm or more and 150 nm or less. By setting such a value, a large sheet resistance can be obtained within the range where the influence on the circuit operation due to the wiring resistance of the wiring 302a can be suppressed, and the influence of the step caused by the wiring 302a in the manufacturing process can be suppressed. For example, the film thickness of the wiring 302a is preferably 50 nm or more and 150 nm or less. By setting such a value, a large sheet resistance can be obtained within the range where the influence on the circuit operation due to the wiring resistance of the wiring 302a can be suppressed, and the influence of the step caused by the wiring 302a in the manufacturing process can be suppressed.

[0035] Note that in FIG. 1(B), the case where the wiring 302a and the gate electrode of the transistor 101 are electrically connected within the circuit 100 is shown as a representative example, but the present embodiment is not limited to this. The wiring 302a may be connected to the gate electrodes of a plurality of transistors. Also, in addition to the case where the wiring 302a is connected to the gate electrode of the transistor, the wiring 302a may be connected to the source electrode or the drain electrode of the transistor, or may be connected to a semiconductor element such as a capacitor element or a resistor element.

[0036] ​ A semiconductor device having a positional relationship will be described. Note that the cross-sectional structure of the semiconductor device is the cross-sectional structure shown in FIG. 1(A ) is applied.

[0037] FIG. 2 shows a diagram representing the circuit configuration of the circuit 200 and the arrangement relationship of the wirings. The circuit 200 has a wiring 303b, a wiring 302b, and transistors 201 and 202, and has a region 203 where the wiring 303b and the wiring 302b are arranged overlapping each other. A signal input to the circuit 200 is applied to the wiring 303b and is electrically connected to the gate electrode of the transistor 201 . Also, a signal output from the circuit 200 is applied to the wiring 302b and is electrically connected to one of the source electrode or the drain electrode of the transistor 202 . Note that the wiring 303b is formed using the second wiring 303 in FIG. 1(A), and the wiring 302b is formed using the first wiring 302 in FIG. 1(A). wiring 302 in FIG. 1(A). wiring 302 in FIG. 1(A).

[0038] Also, signals having the same phase are applied to the wiring 303b and the wiring 302b. Here, the signals having the same phase mean signals having the same phase. In the case of a digital signal, it is assumed to represent a signal in which the High (high) and L ow (low) periods coincide with each other. Note that the degree of coincidence in a digital signal is preferably such that at least a part of the rise time or fall time of the signal overlaps . In the case where the rise time or fall time overlaps, as compared with the case where the rise time or fall time does not overlap, charging and discharging of the parasitic capacitance of each wiring is suppressed, and thus there is an effect of reducing the delay time of the signal . .

[0039] As described above, generally, a semiconductor device having a cross-sectional structure as shown in FIG. 1(A) is as follows has problems. Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, a large parasitic capacitance is formed in the region where the first wiring 302 and the second wiring 303 are arranged overlappingly. As a result, the delay time of the signals applied to the first wiring 302 and the second wiring 303 increases, causing the circuit operation to slow down or not operate at all. To avoid this effect, it is possible to use only one of the first wiring 302 and the second wiring 303, but this results in a problem of an increase in the circuit area because the number of available wirings is reduced by one.

[0040] On the other hand, with the configuration as shown in FIG. 2, although a large parasitic capacitance is formed in the region 203 where the wiring 303b and the wiring 302b are arranged overlappingly, the influence on the signal delay time can be suppressed. This is because the same-phase signals are applied to the wiring 303b and the wiring 302b, so the potential difference between the two terminals where the parasitic capacitance is formed is kept small, and the charging and discharging to the two terminals are suppressed.

[0041] As a result, it becomes possible to apply the region 203 where the wiring 302b and the wiring 303b separated by the thin interlayer film (the first interlayer film 305 in FIG. 1(A)) are arranged overlappingly as part of the circuit, and a smaller circuit area can be realized compared to the case where only one of the wiring 302b and the wiring 303b is used. As a result, it becomes possible to realize a small semiconductor device.

[0042] Note that, as shown in FIG. 1(A), the first interlayer film 305 has a thinner film thickness than the second interlayer film 306. The structure having [the following] is a structure that various semiconductor devices may have. For example, a configuration in which the first wiring 302 and the second wiring 303 are used as a part of a semiconductor element different from the semiconductor element formed in the element formation layer 301 can be given. Specifically, a case where the first wiring 302 and the second wiring 303 are used as electrodes of a capacitor element can be considered. Since the capacitance value of the capacitor element increases as the thickness of the dielectric film becomes thinner, the first interlayer film 305 is preferably thin. Also, when the first wiring 302 is used as a gate electrode of a transistor and the second wiring 303 is used as a source electrode or a drain electrode of the transistor, since the first interlayer film 305 is used as a gate insulating film, it may be formed thinly. In addition, the first wiring 3 02 may be used as a source electrode or a drain electrode, and the second wiring 303 may be used as a gate electrode. As the transistor, a transistor using amorphous silicon in the semiconductor active region, a transistor using an oxide semiconductor in the semiconductor active region, etc. can be given. Among others, the first wiring 302 and the second wiring 303 may be used as a part of a resistor element or a memory element. By using the circuit configuration and the wiring arrangement relationship shown in FIG. 2, even if the first interlayer film 305 shown in FIG. 1(A) has a thin film thickness, the region where the first wiring 302 and the second wiring 303 overlap can be used as a part of the circuit, which is effective for reducing the circuit area. On the other hand, in a semiconductor device, when the first interlayer film 305 is used as a dielectric of a capacitor element or a gate insulating film of a transistor, the first interlayer film 305 has a thickness of 10 nm or more and 300 nm or less, preferably 10 nm or more and 100 nm or less, more preferably 10 n

[0043] It is preferable that m is greater than or equal to 30 nm.

[0044] In FIG. 2, the wiring 303b and the gate electrode of the transistor 201 are electrically connected to each other in the circuit 200. The wiring 302b and the source electrode or drain electrode of the transistor 202 are electrically connected to each other. Although the case where one side is electrically connected to the other side has been shown as a representative example, this embodiment is not limited to this. The wiring 303b is connected to one of the source electrode or the drain electrode of the transistor. The wiring 302b may be connected to a gate electrode of a transistor. In addition, the wiring 302b and the wiring 303b are connected to gate electrodes or sources of a plurality of transistors. The gate electrode may be connected to a drain electrode, or may be connected to a capacitance means, a resistance means, a semiconductor means such as a diode, etc. It may be connected to a conductive element.

[0045] In this embodiment, the wiring 303b is formed using the second wiring 303 in FIG. The wiring 302b is formed using the first wiring 302 in FIG. The line 302b is formed using the second wiring 303 in FIG. 1(A), and the wiring 303b is formed using the second wiring 303 in FIG. ) may be used as the first wiring 302.

[0046] In FIG. 2, a signal to be input to the circuit 200 is supplied to the wiring 303b. However, the present embodiment is not limited to this. In FIG. 2, the wiring 302b may be provided with a Although the embodiment is configured to supply a signal, the present invention is not limited to this. One of the internal signals of the circuit 200 may be provided.

[0047] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combination.

[0048] (Embodiment 2) In this embodiment, an example in which the circuit configuration shown in Embodiment 1 is applied to a drive circuit of a semiconductor device will be described with reference to the drawings. In this embodiment, an example of applying it to a memory device will be shown as an example of a semiconductor device. First, the configuration and operation of the memory cell 502 included in the memory device will be described. The circuit diagram of the memory cell 502 is shown in FIG. 3. The memory cell 502 shown in FIG. 3 includes a first transistor 1201, a second transistor 1202, and a capacitor element 1203. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2, and one of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. An example of applying it to a memory device will be shown.

[0049] <Configuration and Operation of Memory Cell> First, the configuration and operation of the memory cell 502 included in the memory device will be described. The circuit diagram of the memory cell 502 is shown in FIG. 3. The memory cell 502 shown in FIG. 3 includes a first transistor 1201, a second transistor 1202, and a capacitor element 1203. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2, and one of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. The memory cell 502 shown in FIG. 3 includes a first transistor 1201, a second transistor 1202, and a capacitor element 1203. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2, and one of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. The memory cell 502 shown in FIG. 3 includes a first transistor 1201, a second transistor 1202, and a capacitor element 1203. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2, and one of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2, and one of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. One of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. One of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the first signal line S1. The other of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the gate electrode of the first transistor 1201 and one of the electrodes of the capacitor element 1203. The source electrode of the first transistor 1201 is electrically connected to the source line (SL), and the drain electrode of the first transistor 1201 is electrically connected to the bit line (BL). The other electrode of the capacitor element 1203 is electrically connected to the word line (WL). The other of the source electrode or drain electrode of the second transistor 1202 is electrically connected to the gate electrode of the first transistor 1201 and one of the electrodes of the capacitor element 1203. The source electrode of the first transistor 1201 is electrically connected to the source line (SL), and the drain electrode of the first transistor 1201 is electrically connected to the bit line (BL). The other electrode of the capacitor element 1203 is electrically connected to the word line (WL). The source electrode of the first transistor 1201 is electrically connected to the source line (SL), and the drain electrode of the first transistor 1201 is electrically connected to the bit line (BL). The other electrode of the capacitor element 1203 is electrically connected to the word line (WL). The source electrode of the first transistor 1201 is electrically connected to the source line (SL), and the drain electrode of the first transistor 1201 is electrically connected to the bit line (BL). The other electrode of the capacitor element 1203 is electrically connected to the word line (WL). The other electrode of the capacitor element 1203 is electrically connected to the word line (WL).

[0050] Here, as the second transistor 1202, a transistor using an oxide semiconductor is applied. Since the off-current of a transistor using an oxide semiconductor is extremely small, this transistor Since the off-current of a transistor using an oxide semiconductor is extremely small, this transistor By applying a dista to the memory cell, it becomes possible to hold information memorized over an extremely long period of time. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption of the semiconductor device including the memory cell can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time. Further, as the first transistor 120 1, a transistor using a semiconductor material other than an oxide semiconductor is applied. Note that as the semiconductor material used for the first transistor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide can be used, and it is preferable to use a single crystal semiconductor. The first transistor using such a semiconductor material can operate at a sufficiently high speed, so that it is possible to read the stored information at high speed. .

[0051] A schematic diagram showing a cross section of the memory cell 502 is shown in FIG. 4. As shown in FIG. 4, the memory cell 50 2 includes a first transistor 1301 and a second transistor 1302 provided so as to overlap at least a part of the first transistor 1301. The second transistor 13 02 is formed above the first transistor 1301, and one of the gate electrode of the first transistor 1301 and the source electrode or drain electrode of the second transistor 1302 is electrically connected. The first transistor 1301 in FIG. 4 corresponds to the first transistor 120 1 in FIG. 3, and the second transistor 1302 in FIG. 4 corresponds to the second transistor 1202 in FIG. 3. .

[0052] In the semiconductor device shown in FIG. 3, it is possible to hold the potential of the gate electrode of the first transistor 1201. By taking advantage of this feature, writing, holding, and reading of information can be performed as follows. That is.

[0053] First, writing and holding of information will be described. First, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 is turned on, and the second transistor 1 202 is turned on. As a result, the potential of the first signal line (S1) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. That is, a predetermined potential is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203 (writing). Here, charges that give two different potentials (hereinafter, the charge that gives a low potential is referred to as charge QL, and the charge that gives a high potential is referred to as charge QH) are applied through S1 either. Note that charges that give three or more different potentials may be applied to increase the storage capacity. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 is turned off, and the second transistor 1202 is turned off, so that the charge applied to the gate electrode of the first transistor

[0054] 1201 is held (holding). Since the off-current of the second transistor 1202 is extremely small, the potential of the gate electrode of the first transistor 1201 is held for a long time.

[0055] Next, reading of information will be described. When an appropriate potential (read potential) is applied to the word line (WL) while a predetermined potential (constant potential) is applied to the source line (SL), the first transistor 1201 Depending on the amount of charge held in the gate electrode of the transistor 1201, the bit line (BL) assumes different electric levels. Generally, when the first transistor 1201 is of the N-channel type, the apparent threshold voltage Vth -H when QH is applied to the gate electrode of the first transistor 1201 is lower than the apparent threshold voltage Vth-L when QL is applied to the gate electrode of the first transistor 1201. Here, the apparent threshold voltage refers to the voltage of the word line (WL) required to turn the first transistor 1201 "on".

[0056] Therefore, by setting the potential of the word line (WL) to a potential VO between Vth-H and Vth-L, the charge applied to the gate electrode of the first transistor 1201 can be discriminated. For example, in the case where QH was applied during writing, when the potential of the word line (WL) is V O, VO is higher than Vth-H, so the first transistor 1201 turns on. On the other hand, in the case where QL was applied during writing, when the potential of the word line (WL) is VO, VO is lower than Vth-L, so the first transistor 1201 remains off. Therefore, by discriminating the potential of the bit line (BL), the stored information can be read out.

[0057] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. Thus, when reading the information of a predetermined memory cell and not reading the information of other memory cells, for the word line (WL) of the memory cell that is not the target of reading, regardless of the state of the gate electrode, the first transistor 1201 is off. A potential that causes the memory cell to enter the ON state or the OFF state may be applied. Specifically, regardless of the state of the gate electrode, to turn on the first transistor 1201, a potential greater than Vth-L may be applied to the word line (WL), and to turn off the first transistor 1201 regardless of the state of the gate electrode, a potential smaller than Vth-H may be applied to the word line (WL). Regardless of the state of the gate electrode, to turn on the first transistor 1201, a potential greater than Vth-L may be applied to the word line (WL). Regardless of the state of the gate electrode, to turn off the first transistor 1201, a potential smaller than Vth-H may be applied to the word line (WL). Regardless of the state of the gate electrode, to turn off the first transistor 1201, a potential smaller than Vth-H may be applied to the word line (WL). That's all.

[0058] Whether to apply a potential that turns on the first transistor 1201 or a potential that turns off the first transistor 1201 to the word line (WL) of the memory cell that is not the target of reading can be appropriately determined according to the connection relationship of the memory cell 502 (for example, whether the memory cells are connected in series, in parallel, etc.). Whether to apply a potential that turns on the first transistor 1201 or a potential that turns off the first transistor 1201 to the word line (WL) of the memory cell that is not the target of reading can be appropriately determined according to the connection relationship of the memory cell 502 (for example, whether the memory cells are connected in series, in parallel, etc.). Whether to apply a potential that turns on the first transistor 1201 or a potential that turns off the first transistor 1201 to the word line (WL) of the memory cell that is not the target of reading can be appropriately determined according to the connection relationship of the memory cell 502 (for example, whether the memory cells are connected in series, in parallel, etc.). That's all.

[0059] Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns on, and the second transistor 1202 is turned on. As a result, the potential of the wiring of the first signal line (S1) (the potential related to the new information) is applied to the gate electrode of the first transistor 1201 and the capacitor element 1203. Thereafter, the potential of the second signal line (S2) is set to a potential at which the second transistor 1202 turns off, and the second transistor 1202 is turned off, so that the gate electrode of the first transistor 1201 is in a state where the charge related to the new information is held.

[0060] Thus, the semiconductor device according to the disclosed invention can be directly rewritten by writing information again. It is possible to rewrite information. Therefore, it is not necessary to extract charges from the floating gate using a high voltage required in a flash memory or the like, and it is possible to suppress a decrease in the operation speed caused by the erasing operation. That is, high-speed operation of the semiconductor device is realized. Also, in this case, there is no problem of deterioration of the gate insulating film (tunnel insulating film) pointed out in the conventional floating gate type transistor. That is, the problem of deterioration of the gate insulating film when injecting electrons into the floating gate, which has been a conventional problem, can be solved. This means that there is no theoretical limit on the number of write operations.

[0061] ​​​​​​​​​​​​​​​​​​ It is possible.

[0062] For example, when the off-current of the second transistor 1202 at room temperature (25 ° C) is 10 zA (1 zA (zeptoampere) is 1 × 10 -21 A) or less, and the capacitance value of the capacitor element 1203 is about 10 fF, data retention of at least 10 4 seconds or more is possible. Note that it goes without saying that the retention time varies depending on the transistor characteristics and capacitance value.

[0063] <Configuration of Semiconductor Device> FIG. 5 shows an example of a circuit diagram of a semiconductor device. The circuit shown in FIG. 5 is a circuit diagram of the above-described memory cell 502 and a drive circuit for driving the memory cell. The drive circuit shown in FIG. 5 includes a load decoder 5 00, a load driver 501, and a memory cell 502. The load driver 501 and the memory cells 502 are arranged in an array in a plurality.

[0064] The load driver 501 includes a NAND gate section 504, a first level shifter 505, a first buffer 506, a second NAND gate 507, a second level shifter 508, and a second buffer 509. The NAND gate section 504 includes a first NAND gate 503.

[0065] <Configuration and Operation of Drive Circuit Section> The operation of the drive circuit shown in FIG. 5 will be described. One of the plurality of load drivers 501 is selected by the load decoder 500. The output line of the load decoder 500 is electrically connected to one of the input portions of the first NAND gate 503 and one of the input portions of the second NAND gate 507. On the other hand, the other input portion of the first NAND gate 503 is a write enable and is connected to one of the input portions of the second NAND gate 507. It is electrically connected to the write enable signal line (WE), and is also electrically connected to the read enable signal line (RE) in addition to the input section of the second NAND gate 507. Therefore, in the write operation, that is, when WE is active, the output of the first NAND gate 503 becomes active, and in the read operation, that is, when RE is active, the output of the second NAND gate 507 becomes active. The output of the first NAND gate 503 is input to the first level shifter 505, and the output of the second NAND gate 507 is input to the second level shifter 508. On the other hand, a write voltage (VW) is applied to the power supply line of the first level shifter 505, and a read voltage (VR) is applied as the power supply line of the second level shifter 508. Therefore, when the output of the first NAND gate 503 is active, the output of the loader 500 is amplified to the write voltage by the first level shifter 505, and when the output of the second NAND gate 507 is active, it is amplified to the read voltage by the second level shifter 508. The output of the first level shifter 505 passes through the first buffer 506 and is input to the memory cell 502 as the second signal line (S2), and the output of the second level shifter 508 passes through the second buffer 509 and is input to the memory cell 502 as the word line (WL). The memory cell 502 is also connected to the bit line (BL) and the first signal line (S1). In the write operation, that is, when WE is active, the output of the first NAND gate 503 becomes active. In the read operation, that is, when RE is active, the output of the second NAND gate 507 becomes active. The output of the second NAND gate 507 becomes active.

[0066] The output of the first NAND gate 503 is input to the first level shifter 505, and the output of the second NAND gate 507 is input to the second level shifter 508. On the other hand, the output of the second NAND gate 507 is input to the second level shifter 508. A write voltage (VW) is applied to the power supply line of the first level shifter 505, and a read voltage (VR) is applied to the power supply line of the second level shifter 508. Therefore, when the output of the first NAND gate 503 is active, the output of the loader 500 is amplified to the write voltage by the first level shifter 505. When the output of the second NAND gate 507 is active, it is amplified to the read voltage by the second level shifter 508. The output of the first level shifter 505 passes through the first buffer 506 and is input to the memory cell 502 as the second signal line (S2). The output of the second NAND gate 507 is amplified to the read voltage by the second level shifter 508 when it is active. When the output of the second NAND gate 507 is active, it is amplified to the read voltage by the second level shifter 508. The output of the first level shifter 505 passes through the first buffer 506 and is input to the memory cell 502 as the second signal line (S2). The output of the first level shifter 505 passes through the first buffer 506 and is input to the memory cell 502 as the second signal line (S2). The output of the second level shifter 508 passes through the second buffer 509 and is input to the memory cell 502 as the word line (WL). The memory cell 502 is also connected to the bit line (BL) and the first signal line (S1). The memory cell 502 is also connected to the bit line (BL) and the first signal line (S1).

[0067] As shown in FIG. 3, the memory cell 502 includes a first transistor 1201 and a second transistor 1202 provided superimposed on the first transistor 1201. Here The memory cell 502 includes a first transistor 1201 and a second transistor 1202 provided superimposed on the first transistor 1201. , in FIG. 4, the layer 1300 including the first transistor 1301 corresponds to the element formation layer 301 in FIG. 1(A). Also, in the present embodiment, the wiring of the drive circuit portion fabricated in the same process as the source electrode or drain electrode of the second transistor 120 2 corresponds to the first wiring 302 in FIG. 1( A), the interlayer film fabricated in the same process as the gate insulating film of the second transistor 1202 corresponds to the first interlayer film 305 in FIG. 1(A), and the wiring of the drive circuit portion fabricated in the same process as the gate electrode of the second transistor 1202 corresponds to the second wiring 303 in FIG. 1 (A). In this case, by applying the configuration of Embodiment 1, in the drive circuit portion, the wiring fabricated in the same process as the source electrode or drain electrode of the second transistor 1202 included in the memory cell 502 and the wiring fabricated in the same process as the gate electrode of the transistor can both be used as part of the circuit, so that the area of the drive circuit portion can be reduced. More specifically, the circuit configuration described in Embodiment 1 is applied to the NAND gate portion 504, the first level shifter 505, and the second level shifter 508. Among these, the circuit configuration shown in FIG. 1(B) is applied to the NAND gate portion 504, and the circuit configuration shown in FIG. 2 is applied to the first level shifter 505 and the second level shifter 508, respectively. First, the application of the circuit configuration shown in FIG. 1(B) to the NAND gate portion 504 will be described with reference to the drawings. FIG. 6 is a circuit diagram of the NAND gate portion 504. The circuit shown in FIG. 6 includes N-type transistors 601, 602, P-type transistors 603, 604,

[0068]

[0069]

[0070] ​​​​​​​It has signal lines 605 and 606.

[0071] Signal line 605 is a common signal line that drives a plurality of NAND gates (NAND gates 503 and 507 in FIG. 5). Signal line 606 is electrically connected to signal line 605 and is electrically connected to the gate electrode of N-type transistor 601 and the gate electrode of P-type transistor 603.

[0072] In FIG. 6, signal line 606 is used as the first wiring 302 shown in FIG. 1, and signal line 605 is used as the second wiring 303 shown in FIG. 1. More specifically, signal line 606 is fabricated in the same process as the source electrode or drain electrode of the second transistor 1202 included in memory cell 502, and signal line 605 is fabricated in the same process as the gate electrode of the transistor. Therefore, since the gate insulating film of the second transistor 1202 included in memory cell 502 and the interlayer film between signal line 606 and signal line 605 are fabricated in the same process, it is possible to reduce the thickness of the interlayer film. The thickness of the interlayer film can be 10 nm or more and 300 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less.

[0073] In FIG. 6, signal lines 606 and 605 have a region 607 where they are arranged overlappingly. Although a large parasitic capacitance is formed in region 607 where signal line 605 and signal line 606 are arranged overlappingly, the influence on the signal delay time can be suppressed. This is because signal line 605 and signal line 606 are electrically conductive, so the two terminals where the parasitic capacitance is formed are substantially at the same potential, and almost no charging and discharging occur at the two terminals. ​​​​​​​​​

[0074] The signal line 605 is connected to a source electrode or a drain electrode of the second transistor 1202. The signal line 606 is fabricated in the same process as the gate electrode of the transistor. It is also possible to form wiring in the same process as the source electrode or drain electrode. A wiring film with a thickness of 100 nm to 150 nm, which is produced in the same process as the gate electrode. The reason for making the wiring thinner compared to the thickness is to prevent disconnection due to a step in the lower wiring (first wiring). This is preferable because it can be prevented.

[0075] FIG. 7 is a diagram showing a part of a cross section of the NAND gate unit 504. The cross section shown in FIG. The signal line 700 includes a NAND gate 702 and a signal line 704. The NAND gate 702 is a transistor. In FIG. 7, the transistors 703a and 703b are The first transistor 1201 included in the memory cell 502 is manufactured in the same process. 6. Also, the signal line 704 in FIG. 7 corresponds to the signal line 606 in FIG. 6. In FIG. 7, the signal line 700 corresponds to the signal line 605. 6. A region 705 where the signal line 704 overlaps with the signal line 705 corresponds to the region 607 in FIG.

[0076] In FIG. 7, signal line 700 is electrically connected to signal line 704, which is a NAN. The gate electrode of the transistor 703a in the D gate 702 and the gate The gate electrode is electrically connected to the gate electrode.

[0077] 8 is a top view of the NAND gate unit 504 shown in FIGS. The dashed line A-A' in FIG. 8 corresponds to the A-A' in the cross-sectional view shown in FIG.

[0078] The NAND gate 802 shown in FIG. 8 corresponds to the NAND gate 702 shown in FIG. 7, and the signal line 800 corresponds to the signal line 700 shown in FIG. 7, the signal line 804 corresponds to the signal line 704 shown in FIG. 7, and the overlapping region 805 between the signal line 800 and the signal line 804 corresponds to the region 705 shown in FIG. 7. The transistor 803a in the NAND gate 802 corresponds to the transistor 70 3a shown in FIG. 7, and the transistor 803b corresponds to the transistor 703b shown in FIG. 7. The transistor 703a that constitutes the NAND gate 702 corresponds to the N-type transistor 601 in FIG. 6, and the transistor 703b corresponds to the P-type transistor 603 in FIG. 6. The signal line 700 is

[0079] in the same wiring layer as the gate electrode of the second transistor 1302 in FIG. 4, and the signal line 704 is in the same wiring layer as the source electrode or the drain electrode of the second transistor 1302 in FIG. 4. Therefore, the film thickness of the signal line 700 is preferably 200 nm or more, and the film thickness of the signal line 704 is preferably 100 nm or more and 150 nm or less. The region 705 is a region where the signal line 700 and the signal line 704 are stacked via the interlayer film 706. The film thickness of the interlayer film 706 is 10 nm or more and 300 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. The interlayer film 706

[0080] is a film formed in the same process as the source electrode or the drain electrode of the second transistor 1302 in FIG. 4 and the film (i.e., the gate insulating film) that separates the gate electrode. The signal line 700 and the signal line 704 are only separated by the interlayer film 706 of the thin film as described above. The signal line 700 and the signal line 704 are only separated by the interlayer film 706 of the thin film as described above. is separated from the gate electrode by the source electrode or the drain electrode of the second transistor 1302 in FIG. 4 and the film (i.e., the gate insulating film). is a film formed in the same process as the source electrode or the drain electrode of the second transistor 1302 in FIG. 4 and the film (i.e., the gate insulating film) that separates the gate electrode.

[0081] The signal line 700 and the signal line 704 are only separated by the interlayer film 706 of the thin film as described above. However, by applying the circuit configuration shown in FIG. 6, since the same signal is input to the signal line 700 and the signal line 704, even if the film thickness of the interlayer insulating film between the two is thin, they will not affect each other's signals. Therefore, even when there is a region 705 where the signal line 700 and the signal line 704 overlap, the signal line 700 and the signal line 704 can function as wirings. Since the same signal is input, even if the film thickness of the interlayer insulating film between the two is thin, they will not affect each other's signals. Therefore, even when there is a region 705 where the signal line 700 and the signal line 704 overlap, the signal line 700 and the signal line 704 can function as wirings. However, by applying the circuit configuration shown in FIG. 6, since the same signal is input to the signal line 700 and the signal line 704, even if the film thickness of the interlayer insulating film between the two is thin, they will not affect each other's signals. Therefore, even when there is a region 705 where the signal line 700 and the signal line 704 overlap, the signal line 700 and the signal line 704 can function as wirings.

[0082] Subsequently, an example in which the circuit configuration shown in FIG. 2 is applied to the first level shifter 505 and the second level shifter 508 in the semiconductor device of FIG. 5 will be described with reference to FIG. 9. FIG. 9 is a circuit diagram of the first level shifter 505 and the second level shifter 508. Subsequently, an example in which the circuit configuration shown in FIG. 2 is applied to the first level shifter 505 and the second level shifter 508 in the semiconductor device of FIG. 5 will be described with reference to FIG. 9. FIG. 9 is a circuit diagram of the first level shifter 505 and the second level shifter 508. The level shifter shown in FIG. 9 includes N-type transistors 901, 902, and P-type transistors 903, 904, 905, 906.

[0083] The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply. The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply.

[0084] The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply. The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply. The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply. The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply. The level shifter shown in FIG. 9 has a power supply potential when the potentials of the input signal line and the inverted signal input line are high and a ground potential when they are low. Also, the potentials of the output signal line and the inverted signal output line are at a high potential power supply VDDH when high and at a ground potential when low. In the case of the first level shifter 505, VW is applied as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the high potential power supply.

[0085] In FIG. 9, one of the input signal line 910 or the output signal line 912 is used as the first wiring 302 shown in FIG. 1(A), and the other is used as the second wiring 303 shown in FIG. 1(A). More specifically, one of the input signal line 910 or the output signal line 912 is fabricated in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 502. In FIG. 9, one of the input signal line 910 or the output signal line 912 is used as the first wiring 302 shown in FIG. 1(A), and the other is used as the second wiring 303 shown in FIG. 1(A). More specifically, one of the input signal line 910 or the output signal line 912 is fabricated in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 502. In FIG. 9, one of the input signal line 910 or the output signal line 912 is used as the first wiring 302 shown in FIG. 1(A), and the other is used as the second wiring 303 shown in FIG. 1(A). More specifically, one of the input signal line 910 or the output signal line 912 is fabricated in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 502. In FIG. 9, one of the input signal line 910 or the output signal line 912 is used as the first wiring 302 shown in FIG. 1(A), and the other is used as the second wiring 303 shown in FIG. 1(A). More specifically, one of the input signal line 910 or the output signal line 912 is fabricated in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 502.​ The other party is manufactured in the same process as the gate electrode of the transistor.

[0086] Alternatively, in FIG. 9, one of the inversion signal input line 911 or the inversion signal output line 913 is used as the first wiring 302 shown in FIG. 1(A), and the other is used as the second wiring 303 shown in FIG. 1(A). More specifically, one of the inversion signal input line 911 or the inversion signal output line 913 is manufactured in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 502, and the other is manufactured in the same process as the gate electrode of the transistor. It shall be made.

[0087] As a result, the interlayer film between the input signal line 910 and the output signal line 912, or the interlayer film between the inversion signal input line 911 and the inversion signal output line 913, or both of them, are manufactured in the same process as the gate insulating film of the second transistor 1202 included in the memory cell 502. Therefore, it is possible to reduce the film thickness of the interlayer film. The film thickness of the interlayer film can be 10 nm or more and 300 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. 02

[0088] Note that the input signal line 910 is a wiring for inputting the input signal IN, and the inversion signal input line 911 is a wiring for inputting the inversion signal INB of the input signal. Also, the output signal line 912 is a wiring for outputting the output signal OUT, and the inversion signal output line 913 is a wiring for outputting the inversion signal OUTB of the output signal. B.

[0089] Note that the second transistor 1302 included in the memory cell 502 is a top gate type transistor. ​​​​​​​​When using a transistor, the first wiring 302 shown in Fig. 1(A) is made into a wiring fabricated in the same process as the source electrode or drain electrode of the second transistor 130 and the second wiring 303 is preferably made into a wiring fabricated in the same process as the gate electrode of the second transistor 1302 In the second transistor 1302, since the source electrode or drain electrode has a film thickness thinner than that of the gate electrode, it is possible to prevent the disconnection of the second wiring due to the step of the first wiring This is because. Note that the film thickness of the first wiring (source electrode or drain electrode of the second transistor 1302) is preferably 100 nm or more and 150 nm or less

[0090] Note that Fig. 9 shows a level shifter of the type that converts a high signal from a power supply potential to a high - potential power supply. Similarly, it is applicable to a level shifter of the type that converts a low signal from a ground potential to a low - potential power supply

[0091] Fig. 10 is a diagram showing a part of the cross - section of the level shifter shown in Fig. 9. The cross - section shown in Fig. 10 includes a transistor 1000, a wiring 1001, and a wiring 1002. In Fig. 10, the transistor 1000 is fabricated in the same process as the first transistor 1201 included in the memory cell 502 Also, the level shifter shown in Fig. 10 has a region 1003 which is a region where the wiring 1001 and the wiring 1002 overlap. The wiring 1001 is electrically connected to one of the source electrode or drain electrode of the transistor 1000. Also, although not shown, the wiring 1002 is electrically connected to the gate electrode of a transistor different from the transistor 1000

[0092] ​​​​​​​​​​​The transistor 1000 shown in FIG. 10 corresponds to the transistor in the inverter 900 of FIG. 9. The wiring 1001 corresponds to the inverted signal input line 911 in FIG. 9, and the wiring 1002 corresponds to the inverted signal output line 913 in FIG. 9. Alternatively, the wiring 1001 corresponds to the input signal line 910 in FIG. 9, and the wiring 1002 corresponds to the output signal line 912 in FIG. 9.

[0093] FIG. 11 is a form of the top view of the level shifter shown in FIGS. 9 and 10. The dashed line B-B' in FIG. 11 corresponds to B-B' of the cross-sectional view shown in FIG. 10.

[0094] The transistor 1100 shown in FIG. 11 corresponds to the transistor 1000 shown in FIG. 10, and the wiring 1101 corresponds to the wiring 1001 shown in FIG. 10, the wiring 1102 corresponds to the wiring 10 02 shown in FIG. 10, and the region 1103 where the wiring 1101 and the wiring 1102 overlap corresponds to the region 1003 shown in FIG. 10.

[0095] In FIG. 10, the wiring 1001 is the wiring fabricated in the same process as the gate electrode of the second transistor 1302 in FIG. 4, and the wiring 1002 is the wiring fabricated in the same process as the source electrode or the drain electrode of the second transistor 1302 in FIG. 4. Therefore, the film thickness of the wiring 10 01 is preferably 200 nm or more, and the film thickness of the wiring 1002 is preferably 100 nm or more and 150 nm or less. The region 1003 is a region where the wiring 1001 and the wiring 1002 are stacked via the interlayer film 1006. The film thickness of the interlayer film 1006 is 10 nm or more and 300 nm or less, preferably 1 0 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. The interlayer film

[0096] is arranged. The film thickness of the interlayer film 1006 is 10 nm or more and 300 nm or less, preferably 1 0 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. The interlayer film 1006 is a source electrode or drain electrode of the second transistor 1302 in FIG. This film is formed in the same process as the film that separates the gate electrodes (that is, the gate insulating film).

[0097] In the level shifter to which the circuit configuration of FIG. 2 is applied, the wiring 1001 and the wiring 1002 are as described above. Although they are only separated by a thin interlayer film, the wiring 1001 and the wiring 1002 have the same phase signal. Since the signal is input, the effect of parasitic capacitance can be suppressed even if the film thickness between the two layers is thin. Therefore, as shown in the area 1003, the wiring 1001 and the wiring 1002 overlap each other. Even if the wiring 1001 and the wiring 1002 have a region 1003, This can be used to make it function.

[0098] In addition, the first level shifter 505 and the second level shifter 506 in the semiconductor device of FIG. The example of applying the circuit configuration shown in FIG. 2 to 508 is not limited to the configurations shown in FIGS. For example, a level shifter having a configuration as shown in FIG. 12 and FIG. 13 may be used. FIG. 12 is a circuit diagram of the first level shifter 505 and the second level shifter 508. FIG. 13 is a diagram showing a part of a cross section of the level shifter shown in FIG.

[0099] The level shifter shown in FIG. 12 includes an inverter 1400, N-type transistors 1401 and 140 2, P-type transistors 1403, 1404, 1405, and 1406. Inverter 1 400 includes an N-type transistor 1407 and a P-type transistor 1408 .

[0100] The level shifter shown in Figure 12 has a power supply voltage when the potential of the input signal line and the inverted signal input line are high. becomes the ground potential when it is in the low state. Also, the potential of the output signal line and the inverted signal output line becomes the high potential power supply VDDH when it is high, and becomes the ground potential when it is low. That is, VW is used as the high potential power supply in the case of the first level shifter 505, and VR is applied as the high potential power supply in the case of the second level shifter 508. In FIG. 12, one of the input signal line 1410 or the output signal line 1412 is set as the first wiring 302 shown in FIG. 1(A), and the other is set as the second wiring 303 shown in FIG. 1(A). More specifically speaking, one of the input signal line 1410 or the output signal line 1412 is fabricated in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 5

[0101] 02, and the other is fabricated in the same process as the gate electrode of the transistor. Or, in FIG. 12, one of the inverted signal input line 1411 or the inverted signal output line 1413 is set as the first wiring 302 shown in FIG. 1(A), and the other is set as the second wiring 303 shown in FIG. 1(A). More specifically speaking, one of the inverted signal input line 1411 or the inverted signal output line 1413 is fabricated in the same process as the source electrode or the drain electrode of the second transistor 1202 included in the memory cell 502, and the other is fabricated in the same process as the gate electrode of the transistor.

[0102] As a result, the interlayer film between the input signal line 1410 and the output signal line 1412, or the interlayer film between the inverted signal input line 1411 and the inverted signal output line 1413, or both of them, is fabricated in the same process as the gate insulating film of the second transistor 1202 included in the memory cell 502.

[0103] ​​​​​​​​Therefore, it is possible to reduce the film thickness of the interlayer film. The film thickness of the interlayer film is 10 nm or more and 3 00 nm or less, preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 30 nm or less.

[0104] The input signal line 1410 is a wiring for inputting the input signal IN, and the inverted signal input line 14 11 is a wiring for inputting the inverted signal INB of the input signal. The output signal line 1412 is a wiring for outputting the output signal OUT, and the inverted signal output line 1413 is the inverted signal of the output signal OUTB.

[0105] When the second transistor 1302 included in the memory cell 502 is a top-gate transistor, the first wiring 302 shown in FIG. 1 is used as the wiring manufactured in the same process as the source electrode or drain electrode of the second transistor 1302, and the second wiring 303 is used as the wiring manufactured in the same process as the gate electrode of the second transistor 1302. It is preferable that the source electrode or drain electrode of the second transistor 1302 has a film thickness thinner than that of the gate electrode, so that disconnection of the second wiring due to a step in the first wiring can be prevented. The film thickness of the first wiring (source electrode or drain electrode of the second transistor 1302) is preferably 100 nm or more and 150 nm or less.

[0106] In FIG. 12, a level shifter of the type that converts a high signal from the power supply potential to the high potential power supply is shown, but the same applies to a level shifter of the type that converts a low signal from the ground potential to the low potential power supply.

[0107] ​​​FIG. 13 is a diagram showing a part of the cross-section of the level shifter shown in FIG. 12. The cross-section shown in FIG. 13 includes a transistor 1500, a wiring 1501, and a wiring 1502. In FIG. 13, the trans istor 1500 is fabricated by the same process as the second transistor 1202 included in the memory cell 502. Also, the level shifter shown in FIG. 13 has a region 1503 which is a region where the wiring 1501 and the wiring 1502 overlap. The wiring 1501 is electrically connected to one of the source electrode or the drain electrode of the transistor 1500. Also, although not shown, the wiring 1 502 is electrically connected to the gate electrode of a transistor different from the transistor 1500

[0108] The transistor 1500 shown in FIG. 13 corresponds to the N-type transistor 1407 in the inverter 1400 of FIG. 12, the wiring 1501 corresponds to the inverted signal input line 1411 of FIG. 12, and the wiring 1 502 corresponds to the inverted signal output line 1413 of FIG. 12. Alternatively, the wiring 1501 corresponds to the input signal line 1410 of FIG. 12, and the wiring 1502 corresponds to the output signal line 1412 of FIG. 12

[0109] In FIG. 13, the wiring 1501 is a wiring fabricated by the same process as the gate electrode of the second transistor 1302 in FIG. 4, and the wiring 1502 is a wiring fabricated by the same process as the source electrode or the drain electrode of the second transistor 1302 in FIG. 4. Therefore, the film thickness of the wiring 15 01 is preferably 200 nm or more, and the film thickness of the wiring 1502 is preferably 100 nm or more and 150 nm or less

[0110] In the region 1503, the wiring 1501 and the wiring 1502 are stacked via an interlayer film 1506 ​​​​​​​​​is the area to be formed. The film thickness of the interlayer film 1506 is 10 nm or more and 300 nm or less, preferably 1 0 nm or more and 100 nm or less, more preferably 10 nm or more and 30 nm or less. The interlayer film 1506 is a film formed in the same process as the source electrode or drain electrode of the second transistor 1302 in FIG. 4 and the film (i.e., the gate insulating film) that separates the gate electrode.

[0111] For the level shifter to which the circuit configuration of FIG. 2 is applied, although the wiring 1501 and the wiring 1502 are only separated by the interlayer film of the thin film as described above, since the in-phase signals are input to the wiring 1501 and the wiring 1502, even if the film thickness between the two is thin, the influence due to the parasitic capacitance can be suppressed. Therefore, even when there is an area 1503 where the wiring 1501 and the wiring 1502 overlap as shown in the area 1503, the wiring 1501 and the wiring 1502 can function as wirings.

[0112] Next, an example in which the configuration shown in FIG. 1(A) is applied to a circuit having a buffer that can also be used in the semiconductor device shown in FIG. 5 will be described with reference to FIG. 14. FIG. 14 is a diagram showing an aspect of a circuit having a common signal line input to a plurality of circuits included in a semiconductor device and a signal line branched from the signal line and used as a wiring in the circuit. The circuit 1601 shown in FIG. 14 includes a buffer 1602 and a circuit 1603, and the input electrode of the buffer 1602 is electrically connected to the signal line 1604. The signal line 1600 is a common signal line that drives a plurality of circuits including the circuit 1601 and is electrically connected to the signal line 1604. The signal line 1605 is electrically connected to the output terminal of the buffer 1602 and the input terminal of the circuit 1603.

[0113] The circuit 1601 shown in FIG. 14 has a buffer 1602 and a circuit 1603, and the input electrode of the buffer 1602 is electrically connected to the signal line 1604. The signal line 1600 is a common signal line that drives a plurality of circuits including the circuit 1601 and is electrically connected to the signal line 1604. The signal line 1605 is electrically connected to the output terminal of the buffer 1602 and the input terminal of the circuit 1603. ​​​​​​​​​

[0114] In FIG. 14, signal line 1604 is defined as the first wiring 302 shown in FIG. 1, and signal line 1600 is defined as the second wiring 303 shown in FIG. 1. More specifically, signal line 1604 is fabricated in the same process as the source or drain electrode of the second transistor 1202 included in the memory cell 502, and signal line 1600 is fabricated in the same process as the gate electrode of the transistor. Similarly, signal line 1605 can be defined as the first wiring 302 shown in FIG. 1.

[0115] As a result, since the gate insulating film of the second transistor 1202 included in the memory cell 502, the interlayer film between signal lines 1600 and 1604, and the interlayer film between signal lines 1600 and 1605 are fabricated in the same process, it is possible to reduce the film thickness of these interlayer films. The film thickness of the interlayer film can be 10 nm or more and 300 nm or less, preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 30 nm or less.

[0116] When the second transistor 1202 included in the memory cell 502 is a top-gate transistor, it is preferable that the first wiring 302 shown in FIG. 1 is a wiring fabricated in the same process as the source or drain electrode of the second transistor 1302, and the second wiring 303 is a wiring fabricated in the same process as the gate electrode of the second transistor 1302. In the second transistor 1302, since the source or drain electrode has a film thickness thinner than that of the gate electrode, it is possible to prevent disconnection of the second wiring due to the step formed by the first wiring. Note that the first wiring (the source electrode of the second transistor 1302 (or drain electrode) of the second transistor 1302)​ The film thickness of the (gate electrode or drain electrode) is preferably 100 nm or more and 150 nm or less.

[0117] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used. It can be used in appropriate combination.

[0118] (Embodiment 3) In this embodiment, the configuration of a semiconductor device according to one aspect of the disclosed invention and a method for manufacturing the same will be described with reference to FIGS. 15 to 20. Specifically, the configuration of a memory cell that can be mounted on a memory device and a method for manufacturing the same will be described. <Configuration of the semiconductor device in cross section and in plan view> FIG. 15 is an example of the configuration of a semiconductor device. FIG. 15(A) shows a cross section of the semiconductor device, and FIG. 15(B) shows a plan view of the semiconductor device. Here, FIG. 15(A) corresponds to the cross section at A1 - A2 and B1 - B2 in FIG. 15(B). The semiconductor device shown in FIGS. 15(A) and 15(B) has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Here, it is desirable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material, etc. may be used. A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor

[0119] FIG. 15 is an example of the configuration of a semiconductor device. In FIG. 15(A), a cross section of the semiconductor device is shown, and in FIG. 15(B), a plan view of the semiconductor device is shown. Here, FIG. 15(A) corresponds to the cross section at A1 - A2 and B1 - B2 in FIG. 15(B). The semiconductor device shown in FIGS. 15(A) and 15(B) has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Here, it is desirable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material, etc. may be used. A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor 15(B), respectively. Here, FIG. 15(A) corresponds to the cross section at A1 - A2 and B1 - B2 in FIG. 15(B). The semiconductor device shown in FIGS. 15(A) and 15(B) has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Here, it is desirable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material, etc. may be used. A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor (B) at A1 - A2 and B1 - B2. The semiconductor device shown in FIGS. 15(A) and 15 has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Here, it is desirable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material, etc. may be used. A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor while the first semiconductor material and the second semiconductor material are preferably different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material, etc. may be used. A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor as the first semiconductor material, a semiconductor material other than an oxide semiconductor can be used, and as the second semiconductor material, an oxide semiconductor can be used. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material, etc. may be used. A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor A transistor using such a semiconductor material is easy to operate at high speed. On the other hand, for the oxide semiconductor while ​The transistor used enables charge retention for a long time due to its characteristics. The semiconductor device shown in FIG. 15 can be used as a memory cell.

[0120] Note that the technical essence of the disclosed invention lies in using a semiconductor material, such as an oxide semiconductor, in transistor 162 that can sufficiently reduce the off-current to retain information. It is not necessary to limit the specific configuration of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, to what is shown here.

[0121] Transistor 160 in FIG. 15 has a channel formation region 134 provided in a semiconductor layer on a semiconductor substrate 400, an impurity region 132 (also referred to as a source region and a drain region) provided so as to sandwich the channel formation region 134, a gate insulating film 122a provided on the channel formation region 134, and a gate electrode 128a provided on the gate insulating film 122a so as to overlay the channel formation region 134. In the figure, there may be cases where a source electrode and a drain electrode are not explicitly shown, but for convenience, such a state may be referred to as a transistor including this case. Also, in this case, to explain the connection relationship of the transistor, the source electrode and the drain electrode may be expressed including the source region and the drain region. That is, in this specification, the description of the source electrode may include the source region. Also, the description of the drain electrode may include the drain region.

[0122] Further, a conductive layer 128b is connected to an impurity region 126 provided in the semiconductor layer on the semiconductor substrate 400. Here, the conductive layer 128b is the source electrode of transistor 160 or It also functions as a drain electrode. An insulating layer 1 is formed on the transistor 160 so as to cover the transistor 160. 36, insulating layer 138, and insulating layer 140 are provided. To achieve this, the transistor 160 has a structure without a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, A sidewall insulating layer is provided on the side surface of the electrode 128a, and an impurity having a region with a different impurity concentration is formed. A pure region 132 may also be provided.

[0123] The transistor 162 in FIG. 15 is an oxide semiconductor provided on the insulating layer 140 etc. The oxide semiconductor layer 144 and a source electrode (or a drain electrode) electrically connected to the oxide semiconductor layer 144. a drain electrode (or source electrode) 142a, and a drain electrode (or source electrode) 142b, and an oxide semiconductor a gate insulating film 146 covering the layer 144, the source electrode 142a and the drain electrode 142b; A gate electrode is provided on the gate insulating film 146 so as to overlap with the oxide semiconductor layer 144. 148a.

[0124] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is preferable that the oxygen supply is sufficient to make the oxygen highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 144 is, for example, 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3Assume the following. Note that the hydrogen concentration in the above-described oxide semiconductor layer 144 is secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectro scopy) measured. Thus, the hydrogen concentration is sufficiently reduced to high purity and, due to the supply of sufficient oxygen, the defect levels in the energy gap caused by oxygen deficiency are reduced. In the oxide semiconductor layer 144, the carrier concentration is 1×10 12 / cm 3 less than, desirably or 1×10 11 / cm 3 less than, more desirably 1.45×10 10 / cm 3 less than becomes. For example, the off-current (here, the value per unit channel width (1 μm)) at room temperature (25 °C) is 100 zA (1 zA (zeptoampere) is 1×10 A) or less, desirably -21 10 zA or less. Thus, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained.

[0125] Note that in the transistor 162 of FIG. 15, an island-shaped oxide semiconductor layer 144 is used to suppress the leakage current generated between elements due to miniaturization. However, a configuration in which the oxide semiconductor layer is not processed into an island shape may also be adopted. When the oxide semiconductor layer is not processed into an island shape, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented.

[0126] The capacitor element 164 in FIG. 15 is composed of a drain electrode 142b, a gate insulating film 146, and a conductive layer 148b. That is, the drain electrode 142b is the capacitor element 164 ​​​​​functions as one of the electrodes, and the conductive layer 148b functions as the other electrode of the capacitor element 164 will be achieved. By adopting such a configuration, sufficient capacitance can be ensured . Further, when the oxide semiconductor layer 144 and the gate insulating film 146 are laminated, the insulation between the drain electrode 142b and the conductive layer 148b can be sufficiently ensured. Furthermore, when capacitance is not required, the capacitor element 164 may not be provided

[0127] In this embodiment, the transistor 162 and the capacitor element 164 are provided such that at least a part of them overlaps with the transistor 160. By adopting such a planar layout , high integration can be achieved. For example, assuming that the minimum processing dimension is F, the area occupied by the memory cell is 15F 2 ~25F 2 is achievable

[0128] An insulating layer 150 is provided over the transistor 162 and the capacitor element 164. Then , wirings 154 are provided in openings formed in the gate insulating film 146 and the insulating layer 150 . The wiring 154 is a wiring that connects one memory cell to another memory cell . The wiring 154 is connected to the impurity region 126 via the source electrode 142a and the conductive layer 128b . As a result, compared with the case where the source region or the drain region in the transistor 160 and the source electrode 142a in the transistor 162 are respectively connected to different wirings , the number of wirings can be reduced, so that the integration degree of the semiconductor device can be improved

[0129] Further, by providing the conductive layer 128b, the connection between the impurity region 126 and the source electrode 142a​​ The subsequent position and the position where the source electrode 142a is connected to the wiring 154 are provided in an overlapping manner. By adopting such a planar layout, an increase in the element area due to the contact region can be suppressed. That is, the integration degree of the semiconductor device can be increased. That is, the integration degree of the semiconductor device can be increased.

[0130] In the semiconductor device shown in FIG. 15, the layer including the transistor 160 corresponds to the element formation layer 301 in FIG. 1(A). The semiconductor memory device shown in the present embodiment has the memory cell shown in FIG. 15 and a drive circuit portion (not shown) for driving the memory cell. The first wiring 302 in FIG. 1(A) corresponds to a wiring (a wiring of the same layer) fabricated in the same process as the source electrode 142a (drain electrode 142b) of the transistor 162 in the drive circuit portion. Also, the first interlayer film 305 in FIG. 1(A) corresponds to an insulating layer fabricated in the same process as the gate insulating film 146 of the transistor 162 in the drive circuit portion. It is also possible to use the first interlayer film 305 without patterning the gate insulating film 146. Further, the second wiring 303 in FIG. 1(A) corresponds to a wiring fabricated in the same process as the gate electrode 148a of the transistor 162 in the drive circuit portion. Also, the second interlayer film 306 in FIG. 1(A) corresponds to an insulating layer fabricated in the same process as the insulating layer 150 of the transistor 162. It is also possible to use the second interlayer film 306 without patterning the insulating layer 150. Further, the third wiring 304 in FIG. 1(A) corresponds to a wiring fabricated in the same process as the wiring 154 of the transistor 162 in the drive circuit portion.

[0131] ​​​​​​​​​​​<Method for fabricating an SOI substrate> Next, an example of a method for fabricating an SOI substrate used in the fabrication of the semiconductor device will be described with reference to FIG. 16 as follows.

[0132] First, a semiconductor substrate 400 is prepared as a base substrate (see FIG. 16(A)). As the semiconductor substrate 400, semiconductor substrates such as a single crystal silicon substrate and a single crystal germanium substrate can be used . Also, as the semiconductor substrate, a solar cell grade silicon (SOG-Si: Solar Grade Silicon) substrate or the like may be used. Further, a polycrystalline semiconductor substrate may be used. When using solar cell grade silicon or a polycrystalline semiconductor substrate, the manufacturing cost can be suppressed as compared with the case of using a single crystal silicon substrate or the like .

[0133] Note that instead of the semiconductor substrate 400, various glass substrates used in the electronics industry such as aluminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, a quartz substrate , a ceramic substrate, and a sapphire substrate can be mentioned. Further, a ceramic substrate having a coefficient of thermal expansion close to that of silicon and mainly composed of silicon nitride and aluminum oxide may be used .

[0134] The surface of the semiconductor substrate 400 is preferably cleaned in advance. Specifically, the semiconductor substrate 400 is preferably cleaned using a hydrochloric acid hydrogen peroxide water mixed solution (HPM), a sulfuric acid hydrogen peroxide water mixed solution (SPM), an ammonia hydrogen peroxide water mixed solution (APM), a dilute hydrofluoric acid (DHF), etc .

[0135] Next, a bond substrate is prepared. Here, a single crystal semiconductor substrate 410 is used as the bond substrate It exists (see Fig. 16(B)). Here, although a single-crystal substrate is used as the bonding substrate, it is not necessary to limit the crystallinity of the bonding substrate to single crystal.

[0136] As the single-crystal semiconductor substrate 410, for example, a single-crystal silicon substrate, a single-crystal germanium substrate, a single-crystal silicon germanium substrate, etc., a single-crystal semiconductor substrate composed of Group 14 elements can be used. Also, a compound semiconductor substrate such as gallium arsenide or indium phosphide can be used. As commercially available silicon substrates, circular ones with diameters of 5 inches (125 mm), 6 inches (150 mm), 8 inches (200 mm), 12 inches (300 mm), 1 6 inches (400 mm) are typical. Note that the shape of the single-crystal semiconductor substrate 4 10 is not limited to circular, and it may be processed into, for example, a rectangle or the like. Also, the single-crystal semiconductor substrate 410 can be manufactured using the CZ (Czochralski) method or the FZ (floating zone) method.

[0137] An oxide film 412 is formed on the surface of the single-crystal semiconductor substrate 410 (see Fig. 16(C)). Note that from the viewpoint of removing contaminants, before forming the oxide film 412, a hydrochloric acid-hydrogen peroxide water mixed solution (HPM ), a sulfuric acid-hydrogen peroxide water mixed solution (SPM), an ammonia-hydrogen peroxide water mixed solution (APM) , dilute hydrofluoric acid (DHF), FPM (a mixed solution of hydrofluoric acid, hydrogen peroxide water, and pure water), etc. are used to clean the surface of the single-crystal semiconductor substrate 410 preferably. It may also be cleaned by alternately discharging dilute hydrofluoric acid and ozone water.

[0138] The oxide film 412 is, for example, a single layer of a silicon oxide film, a silicon oxynitride film, etc., or a laminate It can be formed by causing. As a method for producing the oxide film 412, there are a thermal oxidation method, a CVD method, a sputtering method, and the like. When forming the oxide film 412 using the CVD method , in order to achieve good bonding, it is preferable to form a silicon oxide film using an organic silane such as tetraethoxysilane (abbreviation: TEOS; chemical formula Si(OC2H5)4).

[0139] In this embodiment, the oxide film 412 (here, SiO x film) is formed by performing a thermal oxidation treatment on the single-crystal semiconductor substrate 410. The thermal oxidation treatment is preferably performed by adding a halogen to an oxidizing atmosphere .

[0140] For example, by performing a thermal oxidation treatment on the single-crystal semiconductor substrate 410 in an oxidizing atmosphere to which chlorine (Cl) is added , an oxide film 412 that has been chlorine-oxidized can be formed. In this case, the oxide film 412 becomes a film containing chlorine atoms. By such chlorine oxidation, heavy metals that are exogenous impurities (for example, Fe, Cr, Ni, Mo, etc.) are collected to form metal chlorides , and these can be removed to the outside to reduce the contamination of the single-crystal semiconductor substrate 410.

[0141] Note that the halogen atom contained in the oxide film 412 is not limited to a chlorine atom. The oxide film 412 may contain a fluorine atom. As a method for fluorine-oxidizing the surface of the single-crystal semiconductor substrate 410 , there are a method of immersing it in an HF solution and then performing a thermal oxidation treatment in an oxidizing atmosphere, a method of adding NF3 to the oxidizing atmosphere and performing a thermal oxidation treatment, and the like.

[0142] Next, ions are accelerated by an electric field and irradiated onto the single-crystal semiconductor substrate 410, and by adding them, single-crystalline ​​A brittle region 414 with damaged crystal structure is formed at a predetermined depth of the single-crystal semiconductor substrate 410 (see Fig. 1 6(D)).

[0143] The depth of the region where the brittle region 414 is formed can be adjusted by the kinetic energy of the ions, the mass and charge of the ions, the incident angle of the ions, etc. Also, the brittle region 414 is formed in a region having approximately the same depth as the average penetration depth of the ions. Therefore, the thickness of the single-crystal semiconductor layer separated from the single-crystal semiconductor substrate 410 can be adjusted at the depth where the ions are added . For example, the average penetration depth may be adjusted so that the thickness of the single-crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably about 50 nm or more and 200 nm or less . . . .

[0144] The ion irradiation treatment can be performed using an ion doping apparatus or an ion implantation apparatus. As a typical example of an ion doping apparatus, there is a non-mass separation type apparatus that irradiates all ion species generated by plasma-exciting a process gas onto an object to be processed. In this apparatus, the ion species in the plasma are irradiated onto the object to be processed without mass separation. On the other hand, an ion implantation apparatus is a mass separation type apparatus. In an ion implantation apparatus, the ion species in the plasma are mass-separated, and an ion species of a specific mass is irradiated onto the object to be processed . . . . .

[0145] In the present embodiment, an example in which hydrogen is added to the single-crystal semiconductor substrate 410 using an ion doping apparatus will be described. As the source gas, a gas containing hydrogen is used. Regarding the ions to be irradiated, it is preferable to increase the ratio of H3 . Specifically, the ratio of H , H2 + , H3 + , H2 + , H3 + in the total amount of H3 +The ratio is made to be 50% or more (more preferably 80% or more). H3 + By increasing the ratio of + , the efficiency of ion irradiation can be improved.

[0146] Note that the ions to be added are not limited to hydrogen. Ions such as helium may be added. Also, the ions to be added are not limited to one type, and a plurality of types of ions may be added. For example, when simultaneously irradiating hydrogen and helium using an ion doping apparatus, the number of steps can be reduced as compared with the case of irradiating in different steps, and the surface roughness of the subsequent single crystal semiconductor layer can be suppressed.

[0147] Note that when forming the embrittled region 414 using an ion doping apparatus, heavy metals may also be added simultaneously, but by performing ion irradiation through the oxide film 412 containing halogen atoms, contamination of the single crystal semiconductor substrate 410 by these heavy metals can be prevented.

[0148] Next, the semiconductor substrate 400 and the single crystal semiconductor substrate 410 are opposed to each other and adhered through the oxide film 412. Thereby, the semiconductor substrate 400 and the single crystal semiconductor substrate 410 are bonded together (see Fig. 16(E)). Note that an oxide film or a nitride film may be formed on the surface of the semiconductor substrate 400 to be bonded to the single crystal semiconductor substrate 410.

[0149] At the time of bonding, at one location of the semiconductor substrate 400 or the single crystal semiconductor substrate 410, 0. 001 N / cm 2 or more and 100 N / cm 2 or less, for example, 1 N / cm 2 or more and 20 N / cm 2 ​​It is desirable to apply the following pressure. When pressure is applied to bring the bonding surfaces closer and into close contact, bonding occurs between the semiconductor substrate 400 and the oxide film 412 at the portion where they are in close contact, and spontaneous bonding spreads almost entirely starting from this portion. Van der Waals forces and hydrogen bonds act in this bonding, and it can be carried out at room temperature.

[0150] Before bonding the single-crystalline semiconductor substrate 410 and the semiconductor substrate 400, it is preferable to perform surface treatment on the surfaces related to the bonding. By performing surface treatment, the bonding strength at the interface between the single-crystalline semiconductor substrate 410 and the semiconductor substrate 400 can be improved.

[0151] As the surface treatment, wet treatment, dry treatment, or a combination of wet treatment and dry treatment can be used. Also, different wet treatments can be combined and used, or different dry treatments can be combined and used.

[0152] After bonding, heat treatment may be performed to increase the bonding strength. The temperature of this heat treatment should be a temperature at which separation in the embrittlement region 414 does not occur (for example, above room temperature and less than 400 °C). Also, while heating within this temperature range, the semiconductor substrate 400 and the oxide film 412 may be bonded. For the above heat treatment, heating furnaces such as diffusion furnaces and resistance heating furnaces, RTA (Rapid Thermal Anneal) devices, microwave heating devices, etc. can be used. Note that the above temperature conditions are merely examples and one aspect of the disclosed invention should not be construed as being limited thereto.

[0153] Next, by performing heat treatment, the single-crystalline semiconductor substrate 410 is separated in the embrittlement region, A single-crystalline semiconductor layer 416 is formed on a semiconductor substrate 400 via an oxide film 412 (see Fig. 16 (F)).

[0154] Note that the heat treatment temperature during the above separation is preferably as low as possible. This is because the lower the temperature during separation, the more the surface roughness of the single-crystalline semiconductor layer 416 can be suppressed. Specifically , for example, the heat treatment temperature during the above separation may be 300°C or higher and 600°C or lower, and it is more effective if it is 400°C or higher and 500°C or lower.

[0155] Note that after separating the single-crystalline semiconductor substrate 410, the single-crystalline semiconductor layer 416 may be heat-treated at a temperature of 50 0°C or higher to reduce the concentration of hydrogen remaining in the single-crystalline semiconductor layer 416 .

[0156] Next, by irradiating the surface of the single-crystalline semiconductor layer 416 with laser light, a single-crystalline semiconductor layer 418 with improved surface flatness and reduced defects is formed (see Fig. 16(G) ). Note that instead of the laser light irradiation treatment, heat treatment may be performed.

[0157] Note that in the present embodiment, the laser light irradiation treatment is performed immediately after the heat treatment related to the separation of the single-crystalline semiconductor layer 416, but one aspect of the present invention is not construed as being limited thereto. After performing an etching treatment after the heat treatment related to the separation of the single-crystalline semiconductor layer 416 to remove a region with many defects on the surface of the single-crystalline semiconductor layer 416, the laser light irradiation treatment may be performed, or after improving the surface flatness of the single-crystalline semiconductor layer 416, the laser light irradiation treatment may also be performed. Note that as the above etching treatment, either wet etching or dry etching may be used. After removing a region with many defects on the surface of the single-crystalline semiconductor layer 416, the laser light irradiation treatment may be performed, or after improving the surface flatness of the single-crystalline semiconductor layer 416, the laser light irradiation treatment may also be performed. Note that as the above etching treatment, either wet etching or dry etching These may be used. Also, in the present embodiment, after irradiating the laser light as described above, a thinning process for reducing the film thickness of the single-crystalline semiconductor layer 416 may be performed. For thinning the single-crystalline semiconductor layer 416, one or both of dry etching and wet etching may be used. After that, a thinning process for reducing the film thickness of the single-crystalline semiconductor layer 416 may be performed. For thinning the single-crystalline semiconductor layer 416, one or both of dry etching and wet etching may be used. These may be used.

[0158] Through the above processes, an SOI substrate having a single-crystalline semiconductor layer 418 with good characteristics can be obtained (see Fig. 16(G)). (See Fig. 16(G)).

[0159] <Method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device using the above SOI substrate will be described with reference to Figs. 17 to 20. Next, a method for manufacturing a semiconductor device using the above SOI substrate will be described with reference to Figs. 17 to 20.

[0160] <Method for manufacturing the lower transistor> First, the method for manufacturing the lower transistor 160 will be described with reference to Figs. 17 and 18. Figs. 17 and 18 are cross-sectional process diagrams corresponding to the lower transistor shown in Fig. 15(A), which are part of the SOI substrate manufactured by the method shown in Fig. 16. First, the method for manufacturing the lower transistor 160 will be described with reference to Figs. 17 and 18. Figs. 17 and 18 are cross-sectional process diagrams corresponding to the lower transistor shown in Fig. 15(A), which are part of the SOI substrate manufactured by the method shown in Fig. 16. First, the method for manufacturing the lower transistor 160 will be described with reference to Figs. 17 and 18. Figs. 17 and 18 are cross-sectional process diagrams corresponding to the lower transistor shown in Fig. 15(A), which are part of the SOI substrate manufactured by the method shown in Fig. 16.

[0161] First, the single-crystalline semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (see Fig. 17(A)). Before and after this process, impurity elements for imparting n-type conductivity or impurity elements for imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. When the semiconductor is silicon, for example, phosphorus, arsenic, etc. can be used as impurity elements for imparting n-type conductivity. Also, for example, boron, aluminum, gallium, etc. can be used as impurity elements for imparting p-type conductivity. First, the single-crystalline semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (see Fig. 17(A)). Before and after this process, impurity elements for imparting n-type conductivity or impurity elements for imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. When the semiconductor is silicon, for example, phosphorus, arsenic, etc. can be used as impurity elements for imparting n-type conductivity. Also, for example, boron, aluminum, gallium, etc. can be used as impurity elements for imparting p-type conductivity. First, the single-crystalline semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (see Fig. 17(A)). Before and after this process, impurity elements for imparting n-type conductivity or impurity elements for imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. When the semiconductor is silicon, for example, phosphorus, arsenic, etc. can be used as impurity elements for imparting n-type conductivity. Also, for example, boron, aluminum, gallium, etc. can be used as impurity elements for imparting p-type conductivity. First, the single-crystalline semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (see Fig. 17(A)). Before and after this process, impurity elements for imparting n-type conductivity or impurity elements for imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. When the semiconductor is silicon, for example, phosphorus, arsenic, etc. can be used as impurity elements for imparting n-type conductivity. Also, for example, boron, aluminum, gallium, etc. can be used as impurity elements for imparting p-type conductivity. First, the single-crystalline semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (see Fig. 17(A)). Before and after this process, impurity elements for imparting n-type conductivity or impurity elements for imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. When the semiconductor is silicon, for example, phosphorus, arsenic, etc. can be used as impurity elements for imparting n-type conductivity. Also, for example, boron, aluminum, gallium, etc. can be used as impurity elements for imparting p-type conductivity. First, the single-crystalline semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (see Fig. 17(A)). Before and after this process, impurity elements for imparting n-type conductivity or impurity elements for imparting p-type conductivity may be added to the semiconductor layer to control the threshold voltage of the transistor. When the semiconductor is silicon, for example, phosphorus, arsenic, etc. can be used as impurity elements for imparting n-type conductivity. Also, for example, boron, aluminum, gallium, etc. can be used as impurity elements for imparting p-type conductivity.

[0162] Next, an insulating layer 122 is formed so as to cover the semiconductor layer 120 (see FIG. 17(B)). The insulating layer 122 will later become a gate insulating film. The insulating layer 122 can be formed, for example, by heat treatment (such as thermal oxidation treatment or thermal nitridation treatment) on the surface of the semiconductor layer 120. Instead of heat treatment, high-density plasma treatment may be applied. The high-density plasma treatment can be performed using, for example, a mixed gas of any of rare gases such as He, Ar, Kr, Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Of course, the insulating layer may be formed using a CVD method, a sputtering method, or the like. The insulating layer 122 preferably has a single-layer structure or a stacked structure containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)) with nitrogen added, hafnium silicate (HfSixOy (x>0, y>0)) with nitrogen added, hafnium aluminate (HfAlxOy (x>0, y>0)) with nitrogen added, etc. Also, the thickness of the insulating layer 122 can be, for example, 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. In this embodiment, a single-layer insulating layer containing silicon oxide is formed using the plasma CVD method.

[0163] Next, a mask 124 is formed on the insulating layer 122, and an impurity element imparting single conductivity is added to the semiconductor layer 120 to form an impurity region 126 (see FIG. 17(C)). Here, after adding the impurity element, the mask 124 is removed.

[0164] Next, a mask is formed on the insulating layer 122, and the region where the insulating layer 122 By removing a part of the region, a gate insulating film 122a is formed (see FIG. 17(D)). The insulating layer 122 can be removed by etching such as wet etching or dry etching. An etching process can be used.

[0165] Next, a gate electrode (including wiring formed in the same layer) is formed on the gate insulating film 122a. A conductive layer for forming the gate electrode 128a and the conductive layer is formed by processing the conductive layer. A layer 128b is formed (see FIG. 17(E)).

[0166] The conductive layer used for the gate electrode 128a and the conductive layer 128b may be aluminum, copper, or It can be formed using a metal material such as titanium, tantalum, or tungsten. A semiconductor material such as crystalline silicon may be used to form the layer containing the conductive material. The method is not particularly limited, and various methods such as deposition, CVD, sputtering, and spin coating can be used. The conductive layer can be processed by etching using a resist mask. This can be done by

[0167] Next, the gate electrode 128a and the conductive layer 128b are used as a mask to form a non-transparent layer having one conductivity type. A pure element is added to the semiconductor layer to form a channel forming region 134, an impurity region 132, and an impurity region 133. A pure region 130 is formed (see FIG. 18(A)). For example, an n-type transistor is formed. To achieve this, impurity elements such as phosphorus (P) and arsenic (As) can be added to p-type transistors. To form a sta, impurity elements such as boron (B) and aluminum (Al) are added. The concentration of the added impurity element can be appropriately set. After adding pure elemental substances, a heat treatment for activation is performed. Here, the concentrations of the impurity regions are , and they increase in the order of impurity region 126, impurity region 132, and impurity region 130.

[0168] Next, an insulating layer 136, an insulating layer 138, and an insulating layer 140 are formed so as to cover the gate insulating film 122a, the gate electrode 128a, and the conductive layer 128b (see FIG. 18(B)).

[0169] The insulating layer 136, the insulating layer 138, and the insulating layer 140 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide. In particular, by using a material with a low dielectric constant (low-k) for the insulating layer 136, the insulating layer 138, and the insulating layer 140, it is possible to sufficiently reduce the capacitance caused by the overlap of various electrodes and wirings, which is preferable. Note that a porous insulating layer using these materials may be applied to the insulating layer 136, the insulating layer 138, and the insulating layer 140. In a porous insulating layer, since the dielectric constant is lower than that of a high-density insulating layer, it is possible to further reduce the capacitance caused by electrodes and wirings. Also, the insulating layer 136, the insulating layer 138, and the insulating layer 140 can be formed using an organic insulating material such as polyimide or acrylic. In this embodiment, , the case where silicon oxynitride is used for the insulating layer 136, silicon nitride oxide is used for the insulating layer 138, and silicon oxide is used for the insulating layer 140 will be described. Here, although a stacked structure of the insulating layer 136, the insulating layer 138, and the insulating layer 140 is adopted, one aspect of the disclosed invention is not limited to this. It may be a single layer or a two-layer structure, or a stacked structure of four or more layers. (low-k)

[0170] Next, the insulating layer 138 and the insulating layer 140 are planarized by performing CMP (Chemical Mechanical Polishing) treatment or etching treatment (see Fig. 18(C)) . Here, the CMP treatment is performed until a part of the insulating layer 138 is exposed. When silicon oxynitride is used for the insulating layer 138 and silicon oxide is used for the insulating layer 140, the insulating layer 138 functions as an etching stopper .

[0171] Next, the upper surfaces of the gate electrode 128a and the conductive layer 128b are exposed by performing CMP treatment or etching treatment on the insulating layer 138 and the insulating layer 140 (see Fig. 18(D)) . Here, the etching treatment is performed until a part of the gate electrode 128a and the conductive layer 128b are exposed. The etching treatment is preferably dry etching, but wet etching may also be used . In the step of exposing a part of the gate electrode 128a and the conductive layer 128b, in order to improve the characteristics of the transistor 162 formed later, the surfaces of the insulating layer 136, the insulating layer 138, and the insulating layer 140 are preferably made as flat as possible .

[0172] Through the above steps, the lower transistor 160 can be formed (see Fig. 18(D)) .

[0173] Note that before and after each of the above steps, there may further be steps of forming electrodes, wirings, semiconductor layers, insulating layers, etc . For example, as a wiring structure, a multilayer wiring structure formed by laminating an insulating layer and a conductive layer can be adopted to realize a highly integrated semiconductor device .

[0174] <Method for manufacturing upper transistor> ​​​​​Next, a method for manufacturing the upper transistor 162 will be described with reference to FIGS. 19 and 20. Description.

[0175] First, an oxide semiconductor layer is formed over the gate electrode 128a, the conductive layer 128b, the insulating layer 136, the insulating layer 138, the insulating layer 14 0, etc., and the oxide semiconductor layer is processed to form an oxide semiconductor layer 144 (see FIG. 19(A)). Before forming the oxide semiconductor layer, an insulating layer that functions as a base may be provided over the insulating layer 136, the insulating layer 138, and the insulating layer 140. The insulating layer can be formed using a CVD method such as a PVD method including a sputtering method or a plasma CVD method.

[0176] As the oxide semiconductor to be used, it is preferable to contain at least indium (In) or zinc (Zn). Particularly, it is preferable to contain In and Zn. Further, as a stabilizer for reducing variations in the electrical characteristics of the transistor using the oxide semiconductor, in addition to those, it is preferable to have gallium (Ga). Further, it is preferable to have tin (Sn ) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer.

[0177] Further, as other stabilizers, lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium It may have any one or more of lutetium (Lu).

[0178] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based acids oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxidation oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides 、In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, I n-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In -Lu-Zn-based oxides, quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, I n-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used.

[0179] Here, for example, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, metal elements other than In, Ga, and Zn may be included.

[0180] Also, as the oxide semiconductor, InMO3(ZnO)m (m > 0 and m is not an integer) The material represented by may also be used. Here, M represents one or more metal elements selected from Ga, Fe, Mn, and Co Also, as the oxide semiconductor, In3SnO5 (ZnO) n (n > 0 and n is an integer) The material represented by may also be used.

[0181] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) In-Ga-Zn-based oxides with an atomic ratio or oxides in the vicinity of its composition can be used. Alternatively, In:Sn:Zn = 1 :1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) In-Sn-Zn-based oxides with an atomic ratio or oxides in the vicinity of its composition may be used.

[0182] However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, etc. appropriate. For example, in In-Sn-Zn-based oxides, relatively high mobility can be obtained easily. However, even in In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk.

[0183] For example, in In-Sn-Zn-based oxides, relatively high mobility can be obtained easily. However, even in In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk.

[0184] In addition, for example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn = a:b:c (a + b + ​​The composition of the oxide where c = 1) is in the vicinity of the composition of the oxide with an atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, and c satisfy (a - A) 2 +(b - B) 2 + (c - C) 2 ≦ r 2 where r may be, for example, 0.05. The same applies to other oxides.

[0185] The oxide semiconductor may be single crystal or non - single crystal. In the latter case, it may be amorphous or polycrystalline. It may also have a structure including a crystalline part in the amorphous, or be non - amorphous.

[0186] Since an amorphous oxide semiconductor can relatively easily obtain a flat surface, interface scattering when manufacturing a transistor using this can be reduced, and relatively easily, a relatively high mobility can be obtained.

[0187] Also, in a crystalline oxide semiconductor, more bulk defects can be reduced, and if the flatness of the surface is enhanced, a mobility higher than that of an amorphous oxide semiconductor can be obtained. To enhance the flatness of the surface, it is preferable to form the oxide semiconductor on a flat surface , specifically, on a surface with an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less.

[0188] Note that Ra is the center - line average roughness defined in JIS B0601 extended three - dimensionally so that it can be applied to the surface, and can be expressed as "the average value of the absolute values of the deviations from the reference surface to the specified surface", and is defined by the following formula. "the average value of the absolute values of the deviations from the reference surface to the specified surface", and is defined by the following formula.

[0189] ​​ [Number]

[0190] Incidentally, in the above, S0 refers to the area of the measurement surface (a rectangular area surrounded by four points represented by coordinates (x1, y1), (x1, y2), (x2, y1 ), (x2, y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope).

[0191] In the present embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers along the c-axis or metal atoms and oxygen atoms are arranged in layers, and in which the directions of the a-axis or b-axis are different (rotated about the c-axis as the center) in the ab-plane will be described.

[0192] An oxide containing CAAC generally refers to a non-single crystal that has a triangular, hexagonal, equilateral triangular, or regular hexagonal atomic arrangement when viewed from a direction perpendicular to the ab-plane, and contains a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis direction.

[0193] CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, CAAC contains crystallized portions (crystalline portions), but in some cases, the boundaries between one crystalline portion and another crystalline portion cannot be clearly distinguished.

[0194] When oxygen is contained in CAAC, part of the oxygen may be substituted with nitrogen. Also, CAAC The c-axes of the individual crystal parts constituting it may be aligned in a constant direction (for example, a direction perpendicular to the substrate surface supporting CAAC, the surface of CAAC, etc.). Or, the normal lines of the ab planes of the individual crystal parts constituting CAAC may face a constant direction (for example, a direction perpendicular to the substrate surface supporting CAAC, the surface of CAAC, etc.).

[0195] Depending on its composition, etc., CAAC can be a conductor, a semiconductor, or an insulator. Also, depending on its composition, etc., it can be transparent or opaque to visible light.

[0196] As an example of such CAAC, a crystal that is formed in a film shape and has a triangular or hexagonal atomic arrangement when observed from a direction perpendicular to the film surface or the substrate surface supporting it, and a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) when its film cross-section is observed can be cited.

[0197] An example of the crystal structure included in CAAC will be described in detail with reference to FIGS. 24 to 26. Unless otherwise specified, in FIGS. 24 to 26, the upward direction is taken as the c-axis direction, and the plane perpendicular to the c-axis direction is taken as the ab plane. Note that when simply referring to the upper half and the lower half, it means the upper half and the lower half when divided by the ab plane.

[0198] FIG. 24(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter 4-coordinate O) adjacent to In. Here, a structure in which only the adjacent oxygen atoms are shown for one metal atom is called a small group. The structure of FIG. 24(A) has an octahedral structure, but is shown in a planar structure for simplicity. Note that in the upper half and the lower half of FIG. 24(A), respectively ​​​​​​​​​​​​​ There are four-coordinate O's, three of them. The small group shown in Fig. 24(A) has a charge of 0.

[0199] Fig. 24(B) shows a structure having one five-coordinate Ga, three three-coordinate oxygen atoms (hereinafter referred to as three-coordinate O) close to Ga, and two four-coordinate O's close to Ga. The three-coordinate O's are all present on the ab plane. There is one four-coordinate O each in the upper half and the lower half of Fig. 24(B). Also, since In also takes a five-coordinate form, it can have the structure shown in Fig. 24(B). The small group shown in Fig. 24(B) has a charge of 0. The upper half and the lower half of Fig. 24(B) each have one four-coordinate O. Also, since In also takes a five-coordinate form, it can have the structure shown in Fig. 24(B). The small group shown in Fig. 24(B) has a charge of 0. The small group shown in Fig. 24(B) has a charge of 0.

[0200] Fig. 24(C) shows a structure having one four-coordinate Zn and four four-coordinate O's close to Zn. There is one four-coordinate O in the upper half of Fig. 24(C) and three four-coordinate O's in the lower half. Or, there may be three four-coordinate O's in the upper half of Fig. 24(C) and one four-coordinate O in the lower half. The small group shown in Fig. 24(C) has a charge of 0. Fig. 24(C) shows a structure having one four-coordinate Zn and four four-coordinate O's close to Zn. There is one four-coordinate O in the upper half of Fig. 24(C) and three four-coordinate O's in the lower half. Or, there may be three four-coordinate O's in the upper half of Fig. 24(C) and one four-coordinate O in the lower half. The small group shown in Fig. 24(C) has a charge of 0. Fig. 24(C) shows a structure having one four-coordinate Zn and four four-coordinate O's close to Zn. There is one four-coordinate O in the upper half of Fig. 24(C) and three four-coordinate O's in the lower half. Or, there may be three four-coordinate O's in the upper half of Fig. 24(C) and one four-coordinate O in the lower half. The small group shown in Fig. 24(C) has a charge of 0. Fig. 24(C) shows a structure having one four-coordinate Zn and four four-coordinate O's close to Zn. There is one four-coordinate O in the upper half of Fig. 24(C) and three four-coordinate O's in the lower half. Or, there may be three four-coordinate O's in the upper half of Fig. 24(C) and one four-coordinate O in the lower half. The small group shown in Fig. 24(C) has a charge of 0.

[0201] Fig. 24(D) shows a structure having one six-coordinate Sn and six four-coordinate O's close to Sn. There are three four-coordinate O's in the upper half of Fig. 24(D) and three four-coordinate O's in the lower half. The small group shown in Fig. 24(D) has a charge of +1. Fig. 24(D) shows a structure having one six-coordinate Sn and six four-coordinate O's close to Sn. There are three four-coordinate O's in the upper half of Fig. 24(D) and three four-coordinate O's in the lower half. The small group shown in Fig. 24(D) has a charge of +1. Fig. 24(D) shows a structure having one six-coordinate Sn and six four-coordinate O's close to Sn. There are three four-coordinate O's in the upper half of Fig. 24(D) and three four-coordinate O's in the lower half. The small group shown in Fig. 24(D) has a charge of +1.

[0202] Fig. 24(E) shows a small group containing two Zn's. There is one four-coordinate O in the upper half of Fig. 24(E) and one four-coordinate O in the lower half. The small group shown in Fig. 24(E) has a charge of -1. Fig. 24(E) shows a small group containing two Zn's. There is one four-coordinate O in the upper half of Fig. 24(E) and one four-coordinate O in the lower half. The small group shown in Fig. 24(E) has a charge of -1. Fig. 24(E) shows a small group containing two Zn's. There is one four-coordinate O in the upper half of Fig. 24(E) and one four-coordinate O in the lower half. The small group shown in Fig. 24(E) has a charge of -1.

[0203] Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell). Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell).

[0204] Here, the rules for the combination of these small groups will be described. As shown in Fig. 24(A), The three O atoms in the upper half of the 6-coordinate In each have three adjacent In atoms in the downward direction, and the three O atoms in the lower half each have three adjacent In atoms in the upward direction. The single O atom in the upper half of the 5-coordinate Ga has one adjacent Ga atom in the downward direction, and the single O atom in the lower half has one adjacent Ga atom in the upward direction. The single O atom in the upper half of the 4-coordinate Zn has one adjacent Zn atom in the downward direction, and the three O atoms in the lower half each have three adjacent Zn atoms in the upward direction. Thus, the number of 4-coordinate O atoms in the upward direction of the metal atom is equal to the number of adjacent metal atoms in the downward direction of that O, and similarly, the number of 4-coordinate O atoms in the downward direction of the metal atom is equal to the number of adjacent metal atoms in the upward direction of that O. Since O is 4-coordinate, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, when the sum of the number of 4-coordinate O atoms in the upward direction of one metal atom and the number of 4-coordinate O atoms in the downward direction of another metal atom is 4, two types of small groups having metal atoms can combine with each other. For example, when a 6-coordinate metal atom (In or Sn) binds through the 4-coordinate O atoms in the lower half, since there are three 4-coordinate O atoms, it will bind to either a 5-coordinate metal atom (Ga or In), or a 4-coordinate metal atom (Zn). In), or a 4-coordinate metal atom (Zn). coordinate, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, when the sum of the number of 4-coordinate O atoms in the upward direction of one metal atom and the number of 4-coordinate O atoms in the downward direction of another metal atom is 4, two types of small groups having metal atoms can combine with each other. For example, when a 6-coordinate metal atom (In or Sn) binds through the 4-coordinate O atoms in the lower half, since there are three 4-coordinate O atoms, it will bind to either a 5-coordinate metal atom (Ga or In), or a 4-coordinate metal atom (Zn). In), or a 4-coordinate metal atom (Zn). O atoms in the lower half, since there are three 4-coordinate O atoms, it will bind to either a 5-coordinate metal atom (Ga or In), or a 4-coordinate metal atom (Zn).

[0205] Metal atoms having these coordination numbers are bonded through 4-coordinate O atoms in the c-axis direction. In addition, a plurality of small groups combine to form a medium group so that the total charge of the layer structure becomes 0.

[0206] Fig. 25(A) shows a model diagram of the medium group constituting the layer structure of the In-Sn-Zn-O system. Figure 25(B) shows a large group consisting of three medium groups. FIG. 25C shows the atomic arrangement when the layer structure of FIG. 25B is observed from the c-axis direction.

[0207] In FIG. 25(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 25(A), the upper and lower halves of In are Each has one 4-coordinate O, which is shown as 1 in a circle. In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0208] In FIG. 25(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. The In is bonded to the In in the upper and lower halves of the Z atom, which has three tetracoordinate O atoms in the upper half. n, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one 4-coordinated O in the upper half. It bonds to a small group of 4-coordinate O atoms in the lower half of this small group. The structure has three O atoms bonded to Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0209] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67. It can be considered as -0.5. For example, the charges of In (6 - coordinate or 5 - coordinate), Zn (4 - coordinate), and Sn (5 - coordinate or 6 - coordinate) are +3, +2, and +4 respectively. Therefore, the small group containing Sn has a charge of +1. Thus, in order to form a layer structure containing Sn, a charge of -1 is required to cancel out the charge +1. As a structure with a charge of -1, as shown in Fig. 24(E), a small group containing 2 Zn atoms can be cited. For example, if there is 1 small group containing Sn and 1 small group containing 2 Zn atoms, the charges can be canceled out, so that the total charge of the layer structure can be made 0. Specifically, by repeating the large group shown in Fig. 25(B), a crystal of the In - Sn - Zn - O system (In2SnZn3O8) can be obtained. Note that the obtained layer structure of the In - Sn - Zn - O system can be represented by the composition formula In2SnZn2O7(ZnO)m (m is 0 or a natural number). In addition to this, there are also quaternary metal oxides such as In - Sn - Ga - Zn - based oxides, ternary metal oxides such as In - Ga - Zn - based oxides (also denoted as IGZO), In - Al - Zn - based oxides, Sn - Ga - Zn - based oxides, Al - Ga - Zn - based oxides, Sn - Al - Zn - based oxides, In - Hf - Zn - based oxides, In - La - Zn - based oxides, In - Ce - Zn - based oxides, In - Pr - Zn - based oxides, In - Nd - Zn - based oxides, In - Sm - Zn - based oxides, In - Eu - Zn - based oxides, In - Gd - Zn - based oxides, In - Tb - Zn - based oxides, In - Dy - Zn - based oxides, In - Ho - Zn - based oxides, In - Er - Zn - based oxides.

[0210] m (m is 0 or a natural number.)

[0211] ​​​​​​​​​​​​​​​n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn -based oxides, and binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I n-Ga-based oxides are the same when used.

[0212] For example, Fig. 26(A) shows a model diagram of the middle group constituting the layer structure of the In-Ga-Zn-O system. is shown.

[0213] In Fig. 26(A), the middle group constituting the layer structure of the In-Ga-Zn-O system has, from top downward, three 4-coordinate O atoms each in the upper and lower halves and In atoms, one 4-coordinate O atom in the upper half and Zn atoms that are bonded to the In atoms, and through the three 4-coordinate O atoms in the lower half of the Zn atoms, one 4-coordinate O atom each in the upper and lower halves and Ga atoms that are bonded to the Zn atoms, and through the one 4-coordinate O atom in the lower half of the Ga atoms, In atoms with three 4-coordinate O atoms each in the upper and lower halves are bonded. This is the structure in which the middle group is configured. A plurality of these middle groups are combined to form a large group.

[0214] Fig. 26(B) shows a large group composed of three middle groups. Note that Fig. 26(C) shows the atomic arrangement when the layer structure of Fig. 26(B) is observed from the c-axis direction.

[0215] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3, respectively. Therefore, a small group containing any of In, Zn, and Ga has a charge of 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0.

[0216] In addition, the middle group that constitutes the In-Ga-Zn-O-based layer structure is not limited to the middle group shown in Fig. 26(A), and a large group combining middle groups with different arrangements of In, Ga, and Zn can also be used. The middle group is not limited to the middle group shown in Fig. 26(A), and a large group combining middle groups with different arrangements of In, Ga, and Zn can also be used. The middle group is not limited to the middle group shown in Fig. 26(A), and a large group combining middle groups with different arrangements of In, Ga, and Zn can also be used.

[0217] In addition, In-Sn-Zn-based oxides can be called ITZO, and the composition ratio of the target used is an atomic ratio of In:Sn:Zn of 1:2:2, 2:1:3, 1:1:1, or 20:45:35, etc., and an oxide target is used. 20:45:35, etc., and an oxide target is used.

[0218] In addition, when using an In-Zn-O-based material as the oxide semiconductor, the composition ratio of the target used is an atomic ratio of In:Zn = 50:1 to 1:2 (converted to a molar ratio, In2O3 :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (converted to a molar ratio, In2O3:ZnO = 10:1 to 1:2), more preferably In:Zn = 1 5:1 to 1.5:1 (converted to a molar ratio, In2O3:ZnO = 15:2 to 3:4). For example, when forming an In-Zn-O-based oxide semiconductor, the target used has an atomic ratio of In:Zn:O = X:Y:Z, and Z > 1.5X + Y. For example, when forming an In-Zn-O-based oxide semiconductor, the target used has an atomic ratio of

[0219] In addition, the thickness of the oxide semiconductor layer is desirably 3 nm or more and 30 nm or less. If the oxide semiconductor layer is made too thick (for example, the film thickness is 50 nm or more), the transistor may become a normally-on type. type.

[0220] The oxide semiconductor layer is preferably manufactured by a method that makes it difficult for impurities such as hydrogen, water, hydroxyl groups, or hydrides to mix in. For example, it can be manufactured using a sputtering method or the like. The oxide semiconductor layer is preferably manufactured by a method that makes it difficult for impurities such as hydrogen, water, hydroxyl groups, or hydrides to mix in. For example, it can be manufactured using a sputtering method or the like.

[0221] In this embodiment, the oxide semiconductor layer is formed by a sputtering method using an In-Ga-Zn-O-based oxide target.

[0222] As the In-Ga-Zn-O-based oxide target, for example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [molar ratio] can be used. Note that it is not necessary to limit the material and composition of the target as described above. For example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] can also be used.

[0223] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide target with a high filling rate, the formed oxide semiconductor layer can be made into a dense film.

[0224] The film formation atmosphere may be an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas and oxygen. Further, in order to prevent the incorporation of hydrogen, water, hydroxyl groups, hydrides, etc. into the oxide semiconductor layer, it is desirable to use an atmosphere of a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, hydrides, etc. are sufficiently removed.

[0225] For example, the oxide semiconductor layer can be formed as follows.

[0226] First, a substrate is held in a film formation chamber maintained in a reduced pressure state, and the substrate temperature is heated to exceed 200°C and be 500°C or less, preferably exceed 300°C and be 500°C or less, more preferably 350°C or more and 450°C or less.

[0227] Next, while removing the remaining moisture in the film formation chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. A high-purity gas having been removed from the target was introduced into the target chamber, and an oxide semiconductor layer was formed on the substrate using the target. In order to remove the residual moisture in the deposition chamber, a cryopump is used as an exhaust means. Adsorption type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. It is also preferable that the exhaust means is a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen, water, hydroxyl groups, or hydrogen. Impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed. Hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of impurities can be reduced.

[0228] When the substrate temperature during film formation is low (for example, 100°C or lower), the oxide semiconductor contains hydrogen atoms. It is preferable to heat the substrate to the above-mentioned temperatures, since there is a risk of contamination with substances that may be harmful to the substrate. By heating the substrate to the above-mentioned temperature to form the oxide semiconductor layer, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, the oxide semiconductor layer is formed in a state where the substrate is heated to the above-mentioned temperature. By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be eliminated. It is possible to sufficiently reduce the concentration of substances. It is also possible to reduce damage caused by sputtering. This can be done.

[0229] As an example of the deposition conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, Set the DC power supply to 0.5 kW, the substrate temperature to 400 °C, and the film-forming atmosphere to an oxygen (oxygen flow rate ratio 100%) atmosphere. Note that when using a pulsed DC power supply, it is preferable because the powdery substances (also referred to as particles or dust) generated during film formation can be reduced and the film thickness distribution becomes uniform.

[0230] Note that before forming the oxide semiconductor layer by sputtering, reverse sputtering is performed by introducing argon gas to generate plasma, and it is preferable to remove the powdery substances (also referred to as particles or dust) adhering to the surface to be formed of the oxide semiconductor layer. Reverse sputtering is a method in which a voltage is applied to the substrate to form plasma near the substrate and modify the surface on the substrate side. Note that instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0231] Processing of the oxide semiconductor layer can be performed by forming a mask with a desired shape on the oxide semiconductor layer and then etching the oxide semiconductor layer. The above-mentioned mask can be formed by using methods such as photolithography . Alternatively, a mask may be formed by using a method such as the inkjet method . Note that the etching of the oxide semiconductor layer may be either dry etching or wet etching. Of course, these may be used in combination.

[0232] Thereafter, the oxide semiconductor layer 144 may be subjected to a heat treatment (first heat treatment). By performing the heat treatment, substances containing hydrogen atoms contained in the oxide semiconductor layer 144 can be further removed. The temperature of the heat treatment is 250 °C or higher and 700 °C or lower, preferably 450 °C or higher and 600 °C or lower, or less than the distortion point of the substrate, in an inert gas atmosphere. Inert gas ​As the atmosphere, nitrogen or a noble gas (helium, neon, argon, etc.) as the main component is desirable to apply an atmosphere that does not contain water, hydrogen, etc. For example, heat The purity of nitrogen or noble gases such as helium, neon, and argon introduced into the treatment apparatus is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0233] The heat treatment can be performed, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, under a nitrogen atmosphere, at 450 °C for 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the atmosphere, so as to prevent the mixing of water and hydrogen.

[0234] By the way, since the above heat treatment has the effect of removing hydrogen, water, etc., the heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. The heat treatment can be performed, for example, at the timing such as before processing the oxide semiconductor layer into an island shape or after forming the gate insulating film. It is also possible to perform such dehydration treatment and dehydrogenation treatment not only once but also multiple times. It is also possible to perform such dehydration treatment and dehydrogenation treatment not only once but also multiple times. It is also possible to perform such dehydration treatment and dehydrogenation treatment not only once but also multiple times. It is also possible to perform such dehydration treatment and dehydrogenation treatment not only once but also multiple times.

[0235] Next, a conductive layer for forming a source electrode and a drain electrode (including wirings formed in the same layer) is formed on the oxide semiconductor layer 144 or the like, and the conductive layer is processed to form a source electrode 142a and a drain electrode 142b (see FIG. 19(B)). Next, a conductive layer for forming a source electrode and a drain electrode (including wirings formed in the same layer) is formed on the oxide semiconductor layer 144 or the like, and the conductive layer is processed to form a source electrode 142a and a drain electrode 142b (see FIG. 19(B)). Next, a conductive layer for forming a source electrode and a drain electrode (including wirings formed in the same layer) is formed on the oxide semiconductor layer 144 or the like, and the conductive layer is processed to form a source electrode 142a and a drain electrode 142b (see FIG. 19(B)).

[0236] The conductive layer can be formed using a PVD method or a CVD method. Also, as the material of the conductive layer, from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten Selected elements, alloys containing the above-described elements as components, etc. can be used. Manganese, ma gnesium, zirconium, beryllium, neodymium, scandium, or any combination of these may be used.

[0237] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Further, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, there is an advantage that it is easy to process into the source electrode 142a and the drain electrode 142b having a tapered shape. In addition, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, it is easy to process into the source electrode 142a and the drain electrode 142b having a tapered shape. There is an advantage.

[0238] Also, the conductive layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3 - ZnO), or those obtained by adding silicon or silicon oxide to these metal oxide materials can be used.

[0239] Etching of the conductive layer is preferably performed so that the ends of the source electrode 142a and the drain electrode 142b to be formed have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The source electrode 142a, the drain electrode 142 ​​​​​​​​​​​By etching the end of b into a tapered shape, the gate formed later The coverage of the insulating film 146 can be improved, and step discontinuity can be prevented.

[0240] The channel length (L) of the upper transistor is determined by the interval between the lower ends of the source electrode 142a and the drain electrode 1 42b. When performing exposure for mask formation used to form a transistor with a channel length (L) of less than 25 nm, it is desirable to use extreme ultraviolet rays with a wavelength of several nm to several tens of nm . Exposure using extreme ultraviolet rays has high resolution and a large depth of focus. Therefore, it is possible to set the channel length (L) of the transistor formed later to be 10 nm or more and 1000 nm (1 μm) or less, which can increase the operating speed of the circuit. Also, due to miniaturization, it is possible to reduce the power consumption of the semiconductor device.

[0241] Next, a gate insulating film 146 is formed so as to cover the source electrode 142a and the drain electrode 142b and be in contact with a part of the oxide semiconductor layer 144 (see Fig. 19(C)).

[0242] The gate insulating film 146 can be formed using a CVD method, a sputtering method, or the like. Also, the gate insulating film 146 includes silicon oxide, silicon nitride, silicon oxynitride, gallium oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfSixOy (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSixOyNz (x > 0, y > 0, z > 0)), hafnium aluminate with nitrogen added (HfAlxOyNz (x > 0, y > 0, z > 0)), and the like The gate insulating film 146 may have a single layer structure or may be formed of any of the above materials. The thickness of the laminate may be, but is not limited to, the thickness of the semiconductor device. When miniaturizing a device, it is desirable to make it thinner in order to ensure the operation of the transistor. For example, when silicon oxide is used, the thickness is set to 1 nm or more and 100 nm or less, preferably 10 nm or less. The thickness can be m or more and 50 nm or less.

[0243] As mentioned above, if the gate insulating film is made thin, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating film 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0 , y>0), nitrogen-doped hafnium silicate (HfSixOyNz(x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAlxOyNz( It is recommended to use high-k materials such as x>0, y>0, z>0. By using an igh-k material for the gate insulating film 146, the electrical characteristics are ensured while the gate It is possible to increase the film thickness to suppress leakage. and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, alumina oxide, Alternatively, it may have a laminated structure with a film containing any one of aluminum and the like.

[0244] In addition, the insulating layer in contact with the oxide semiconductor layer 144 (the gate insulating film 1 in this embodiment) 46) may be an insulating material containing a Group 13 element and oxygen. Many of them contain Group 13 elements, and insulating materials containing Group 13 elements are compatible with oxide semiconductors. By preferably using this for the insulating layer in contact with the oxide semiconductor layer, the state at the interface with the oxide semiconductor layer can be kept good.

[0245] The insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, and the like. Here, aluminum gallium oxide means that the content (atomic %) of aluminum is more than the content (atomic %) of gallium, and gallium aluminum oxide means that the content (atomic %) of gallium is equal to or more than the content (atomic %) of aluminum. For example, when forming a gate insulating film in contact with a gallium-containing oxide semiconductor layer, by using a material containing gallium oxide for the gate insulating film, the interface characteristics between the oxide semiconductor layer and the gate insulating film can be kept good. Also, by providing the oxide semiconductor layer in contact with an insulating layer containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced. In addition, when using an element of the same group as the component element of the oxide semiconductor for the insulating layer, the same effect can be obtained. For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Since aluminum oxide has the property of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer. Moreover, the insulating layer in contact with the oxide semiconductor layer 144 is subjected to heat treatment in an oxygen atmosphere or oxygen doping.

[0246] For example, when forming a gate insulating film in contact with a gallium-containing oxide semiconductor layer, by using a material containing gallium oxide for the gate insulating film, the interface characteristics between the oxide semiconductor layer and the gate insulating film can be kept good. Also, by providing the oxide semiconductor layer in contact with an insulating layer containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced. In addition, when using an element of the same group as the component element of the oxide semiconductor for the insulating layer, the same effect can be obtained. For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Since aluminum oxide has the property of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0247] Also, the insulating layer in contact with the oxide semiconductor layer 144 is subjected to heat treatment in an oxygen atmosphere or oxygen doping. It is preferable to make the insulating material have a state where oxygen is more than the stoichiometric composition ratio by means of plasma or the like. Oxygen doping means adding oxygen to the bulk. Note that the term "bulk" is used to clarify that oxygen is added not only to the thin film surface but also to the inside of the thin film. Also, oxygen doping includes oxygen plasma doping in which plasmaized oxygen is added to the bulk. In addition, oxygen doping may be performed using an ion implantation method or an ion doping method.

[0248] For example, when gallium oxide is used as the insulating layer in contact with the oxide semiconductor layer 144, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of gallium oxide can be made Ga2O (X = 3 + α, 0 < α < 1). Also, when aluminum oxide is used as the insulating layer in contact with the oxide semiconductor layer 144, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of aluminum oxide can be made Al2O x (X = 3 + α, 0 < α < 1). Or, when gallium aluminum oxide (aluminum gallium oxide) is used as the insulating layer in contact with the oxide semiconductor layer 144, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of gallium aluminum oxide (aluminum gallium oxide) can be made Ga Al X (0 < X < 2, 0 < α < 1). By performing oxygen doping treatment or the like, an insulating layer having a region where oxygen is more than the stoichiometric composition ratio can be formed. When such an insulating layer having such a region is in contact with the oxide semiconductor layer, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and dehydration and dehydrogenation treatment are performed. X 2-X 3+α (0 < X < 2, 0 < α < 1).

[0249] ​ Reduce oxygen deficiency defects in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and the insulating layer so that the oxide semiconductor layer can be made into an i-type or an oxide semiconductor that is infinitely close to the i-type.

[0250] Note that an insulating layer having a region with more oxygen than the stoichiometric composition ratio may be applied to the insulating layer formed as the underlying film of the oxide semiconductor layer 144 instead of the gate insulating film 146, and may be applied to both the gate insulating film 146 and the underlying insulating film. Instead of both the gate insulating film 146 and the underlying insulating film.

[0251] After the formation of the gate insulating film 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 0°C or higher and 350°C or lower. For example, heat treatment at 250°C for 1 hour in a nitrogen atmosphere may be performed. By performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced. Moreover, when the gate insulating film 146 contains oxygen, oxygen can be supplied to the dehydrated and dehydrogenated oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is infinitely close to the i-type can also be formed. By performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced. Moreover, when the gate insulating film 146 contains oxygen, oxygen can be supplied to the dehydrated and dehydrogenated oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is infinitely close to the i-type can also be formed. Moreover, when the gate insulating film 146 contains oxygen, oxygen can be supplied to the dehydrated and dehydrogenated oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is infinitely close to the i-type can also be formed. Moreover, when the gate insulating film 146 contains oxygen, oxygen can be supplied to the dehydrated and dehydrogenated oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is infinitely close to the i-type can also be formed. .

[0252] Note that in this embodiment, the second heat treatment is performed after the formation of the gate insulating film 146, but the timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may be combined with the second heat treatment, or the second heat treatment may be combined with the first heat treatment. Note that in this embodiment, the second heat treatment is performed after the formation of the gate insulating film 146, but the timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may be combined with the second heat treatment, or the second heat treatment may be combined with the first heat treatment. Moreover, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may be combined with the second heat treatment, or the second heat treatment may be combined with the first heat treatment. Moreover, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may be combined with the second heat treatment, or the second heat treatment may be combined with the first heat treatment. Moreover, the second heat treatment may be combined with the first heat treatment.

[0253] Next, a conductive layer for forming a gate electrode (including wiring formed in the same layer) is formed, and the conductive layer is processed to form a gate electrode 148a and a conductive layer 148b (see FIG. 19(D)). The gate electrode 148a and the conductive layer 148b can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material mainly composed of these. Note that the gate electrode 148a and the conductive layer 148b may have a single-layer structure or a laminated structure. Next, an insulating layer 150 is formed on the gate insulating film 146, the gate electrode 148a, and the conductive layer 148b (see FIG. 20(A)). The insulating layer 150 can be formed using a method such as PVD or CVD. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material with a low dielectric constant or a structure with a low dielectric constant (such as a porous structure) for the insulating layer 150. By reducing the dielectric constant of the insulating layer 150, the capacitance generated between wirings, electrodes, etc. can be reduced, and the operation speed can be increased. In this embodiment, the insulating layer 150 has a single-layer structure, but one aspect of the disclosed invention is not limited to this, and it may have a laminated structure of two or more layers.

[0254] The gate electrode 148a and the conductive layer 148b can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material mainly composed of these. Note that the gate electrode 148a and the conductive layer 148b may have a single-layer structure or a laminated structure. Next, an insulating layer 150 is formed on the gate insulating film 146, the gate electrode 148a, and the conductive layer 148b (see FIG. 20(A)). The insulating layer 150 can be formed using a method such as PVD or CVD. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, or aluminum oxide. Note that it is desirable to use a material with a low dielectric constant or a structure with a low dielectric constant (such as a porous structure) for the insulating layer 150. By reducing the dielectric constant of the insulating layer 150, the capacitance generated between wirings, electrodes, etc. can be reduced, and the operation speed can be increased. In this embodiment, the insulating layer 150 has a single-layer structure, but one aspect of the disclosed invention is not limited to this, and it may have a laminated structure of two or more layers. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150.

[0255] Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150.

[0256] Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. Next, an opening reaching the source electrode 142a is formed in the gate insulating film 146 and the insulating layer 150. Then, a wiring 154 in contact with the source electrode 142a is formed on the insulating layer 150. (See FIG. 20(B)). The formation of the opening is performed by selective etching using a mask or the like. This is done by

[0257] The wiring 154 is formed by forming a conductive layer using the PVD method or the CVD method and then patterning the conductive layer. As the material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as components can be used. A material containing any one of manganese, magnesium, zirconium, beryllium, neodymium, scandium, or a combination of a plurality of these may also be used. More specifically, for example, a titanium film is thinly formed (about 5 nm) in a region including the opening of the insulating layer 150 by the PVD method, and after forming the titanium film by the PVD method, a method of forming an aluminum film so as to fill the opening can be applied. Here, the titanium film formed by the PVD method reduces the oxide film (such as a natural oxide film) on the surface to be formed and has a function of reducing the contact resistance with the lower electrode or the like (here, the source electrode 142a). In addition, hillocks of the aluminum film can be prevented. Further, a barrier film made of titanium or titanium nitride may be formed, and then a copper film may be formed by a plating method. It is desirable to form the opening formed in the insulating layer 150 in a region overlapping with the conductive layer 128b. By forming the opening in such a region, an increase in the element area due to the contact region can be suppressed. Here, without using the conductive layer 128b, the connection between the impurity region 126 and the source electrode 142a and

[0258]

[0259]

[0260] ​ 、 the case of superimposing the connection between the source electrode 142a and the wiring 154 will be described. In this case, openings (referred to as lower contacts) are formed in the insulating layer 136, the insulating layer 138, and the insulating layer 140 formed on the impurity region 126. After forming the source electrode 142a on the lower contact, in the gate insulating film 146 and the insulating layer 150, an opening (referred to as an upper contact) is formed in the region that overlaps with the lower contact, and the wiring 154 will be formed. When forming the upper contact in the region that overlaps with the lower contact, there is a risk that the source electrode 142a formed on the lower contact may be disconnected due to etching. To avoid this, forming the lower contact and the upper contact so that they do not overlap causes a problem that the element area increases. As shown in this embodiment, by using the conductive layer 128b, the upper contact can be formed without disconnecting the source electrode 142a. As a result, since the lower contact and the upper contact can be provided so as to overlap, an increase in the element area due to the contact region can be suppressed. That is, the integration degree of the semiconductor device can be increased.

[0261] Next, an insulating layer 156 is formed so as to cover the wiring 154 (see FIG. 20(C)). Thus, the transistor 162 using the highly purified oxide semiconductor layer 144 and the capacitor element 164 are completed (see FIG. 20(C)).

[0262]

[0263] In the transistor 162, between the oxide semiconductor layer 144 and the source electrode 142a, the drain

[0264] An oxide conductive layer functioning as a source region and a drain region may be provided between the in-electrode 142b. It may be provided as a buffer layer. Transistors 162A and 162B with an oxide conductive layer provided in the transistor 162 of FIG. 15(A) are shown in FIGS. 22(A) and (B).

[0265] In the transistors 162A and 162B of FIGS. 22(A) and (B), oxide conductive layers 404a and 404b functioning as source regions and drain regions are formed between the oxide semiconductor layer 144 and the source electrode 142a and the drain electrode 142b. The transistors 162A and 162B of FIGS. 22(A) and (B) are examples in which the shapes of the oxide conductive layers 404a and 404b are different due to the manufacturing process.

[0266] In the transistor 162A of FIG. 22(A), a laminate of an oxide semiconductor film and an oxide conductive film is formed, and the laminate of the oxide semiconductor film and the oxide conductive film is shaped by the same photolithography process to form an island-shaped oxide semiconductor layer 144 and an oxide conductive film. After forming the source electrode 142a and the drain electrode 142b on the oxide semiconductor layer and the oxide conductive film, the island-shaped oxide conductive film is etched using the source electrode 142a and the drain electrode 142b as masks to form the oxide conductive layers 404a and 404b serving as source regions and drain regions.

[0267] In the transistor 162B of FIG. 22(B), an oxide conductive film is formed on the oxide semiconductor layer 144, a metal conductive film is formed thereon, and the oxide conductive film and the metal conductive film are processed by the same photolithography process to form the oxide conductive layers 404a and 404b serving as source regions and drain regions, the source electrode 142a, and the drain electrode 142b.

[0268] ​​​​​​​​​​​​​ Note that, during etching treatment for processing the shape of the oxide conductive layer, the oxide semiconductor layer may be excessively In order to prevent etching, the etching conditions (type, concentration, etc. of etching material) must be carefully considered. Adjust the schedule (time, etc.) as appropriate.

[0269] The oxide conductive layers 404a and 404b are formed by a sputtering method or a vacuum deposition method (electron beam deposition). The coating is then applied to the metal by a variety of methods, including vapor deposition, arc discharge ion plating, and spraying. The materials for the conductive layer are zinc oxide, a compound of silicon oxide and indium tin oxide, and oxide. Zinc aluminum nitride, zinc aluminum oxynitride, zinc gallium oxide, etc. can be applied. The above materials may also contain silicon oxide.

[0270] As a source region and a drain region, an oxide conductive layer is formed between the oxide semiconductor layer 144 and the source electrode 142a and the drain electrode 142b, The resistance can be reduced, and the transistors 162A and 162B can operate at high speed. Cut.

[0271] In addition, the oxide semiconductor layer 144, the oxide conductive layers 404a and 404b, the source electrode 142a, By configuring the drain electrode 142b, the withstand voltage of the transistors 162A and 162B is The pressure can be improved.

[0272] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17atoms / cm 3 The following is the case. Also, the carrier density of the oxide semiconductor layer 144 is lower than that of a general silicon wafer (1×10 14 / cm 3 or so) and is sufficiently small (for example, less than 1 ×10 12 / cm 3 , more preferably less than 1.45×10 10 / cm 3 ). And the off-current also becomes sufficiently small. For example, the off-current (here, the value per unit channel width (1 μm)) of the transistor 162 at room temperature (25°C) is 100 zA (1 zA( zeptoampere is 1×10 A) or less, desirably 10 zA or less. -21

[0273] By using the highly purified and intrinsic oxide semiconductor layer 144 in this way, it becomes easy to sufficiently reduce the off-current of the transistor. And by using such a transistor , a semiconductor device capable of retaining the stored content for an extremely long time can be obtained .

[0274] In addition, in the semiconductor device shown in this embodiment, it is also possible to share wiring, and a semiconductor device with a sufficiently high integration degree can be realized.

[0275] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments .

[0276] (Embodiment 4) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device , it will be described with reference to FIG. 21. In this embodiment, a computer, a mobile phone (mobile​​ (also referred to as a telephone or a mobile phone), a portable information terminal (including a portable game machine, an audio playback device, etc.), a camera such as a digital camera or a digital video camera, an electronic paper, a television device (also referred to as a television or a television receiver), etc. The application of the above semiconductor device to such electronic devices will be described.

[0277] FIG. 21(A) is a notebook personal computer, which is composed of a housing 707, a housing 708, a display unit 709, a keyboard 710, etc. At least one of the housing 707 and the housing 708 is provided with the semiconductor device shown in the previous embodiment. Therefore, a notebook personal computer with high-speed information writing and reading, long-term memory retention, and sufficiently reduced power consumption is realized.

[0278] FIG. 21(B) is a portable information terminal (PDA). The main body 711 is provided with a display unit 713, an external interface 715, operation buttons 714, etc. In addition, a stylus 712 for operating the portable information terminal is provided. The semiconductor device shown in the previous embodiment is provided in the main body 711. Therefore, a portable information terminal with high-speed information writing and reading, long-term memory retention, and sufficiently reduced power consumption is realized.

[0279] FIG. 21(C) is an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 72 3. The housing 721 and the housing 723 are respectively provided with a display unit 7 25 and a display unit 727. The housing 721 and the housing 723 are connected by a shaft portion 737 ​​​​​​is connected and can perform an opening / closing operation with the shaft portion 737 as an axis. Further, the housing 7 21 includes a power supply 731, operation keys 733, a speaker 735, and the like. The housing 721 At least one of the housing 723 is provided with the semiconductor device shown in the previous embodiment. Therefore, an electronic book is realized in which information writing and reading are fast, long-term memory retention is possible, and power consumption is sufficiently reduced.

[0280] FIG. 21(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 can be slid and overlapped from the state of being unfolded as shown in FIG. 21(D), enabling miniaturization suitable for carrying. Also, The housing 741 includes a display panel 742, a speaker 743, a microphone 744, operation keys 745, a pointing device 746, a camera lens 747, an external connection terminal 74 8, and the like. Also, the housing 740 includes a solar cell 749 for charging the mobile phone , an external memory slot 750, and the like. Also, the antenna is built in the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. Therefore, a mobile phone is realized in which information writing and reading are fast, long-term memory retention is possible, and power consumption is sufficiently reduced.

[0281] FIG. 21(E) shows a digital camera, which is composed of a main body 761, a display unit 767, an eyepiece 763, an operation switch 764, a display unit 765, a battery 766, and the like. Inside the main body 761, the semiconductor device shown in the previous embodiment is provided. Therefore, information writing ​​​High-speed writing and reading, long-term memory retention, and sufficient reduction in power consumption A digital camera with the above characteristics is realized.

[0282] FIG. 21(F) shows a television apparatus 770, which includes a housing 771, a display unit 773, a stand 775, etc. The operation of the television apparatus 770 can be performed by switches provided in the housing 771 or a remote control operation unit 780. The housing 771 and the remote control operation unit 780 are equipped with the semiconductor devices shown in the previous embodiments. Therefore, a television apparatus with high-speed writing and reading of information, long-term memory retention, and sufficient reduction in power consumption is realized. As described above, the electronic devices shown in this embodiment are equipped with the semiconductor devices according to the previous embodiments. For this reason, electronic devices with reduced power consumption are realized.

[0283] As described above, the electronic devices shown in this embodiment are equipped with the semiconductor devices according to the previous embodiments. For this reason, electronic devices with reduced power consumption are realized.

[0284] (Embodiment 5) In the above embodiment, one form of the oxide semiconductor layer that can be used for the semiconductor layer of the transistor 162 will be described with reference to FIG. 23.

[0285] The oxide semiconductor layer of this embodiment has a laminated structure having a second crystalline oxide semiconductor layer thicker than the first crystalline oxide semiconductor layer on the first crystalline oxide semiconductor layer.

[0286] An insulating layer 437 is formed on the insulating layer 401. In this embodiment, as the insulating layer 437, an oxide insulating layer with a film thickness of 50 nm or more and 600 nm or less is formed using the P CVD method or the sputtering method. For example, a silicon oxide film, a gallium oxide film, an aluminum oxide film, an acid One selected from a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film layer or a laminate thereof can be used.

[0287] Next, a first oxide semiconductor film having a thickness of 1 nm or more and 10 nm or less is formed on the insulating layer 437. The first oxide semiconductor film is formed by a sputtering method, and the substrate temperature during film formation by the sputtering method is set to 200°C or higher and 400°C or lower.

[0288] In this embodiment, an oxide semiconductor target (a target for an In-Ga-Zn-O-based oxide semiconductor (In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio])) is used, the distance between the substrate and the target is 170 mm, the substrate temperature is 250°C, the pressure is 0.4 Pa, direct current (DC) power supply is 0.5 kW, and a first oxide semiconductor film having a thickness of 5 nm is formed in an atmosphere of only oxygen, only argon, or argon and oxygen.

[0289] When an In-Zn-O-based material is used as the oxide semiconductor, the composition ratio of the target to be used is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (in terms of molar ratio, In2O3 :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (in terms of molar ratio converted to In2O3:ZnO = 10:1 to 1:2), more preferably In:Zn = 1 5:1 to 1.5:1 (in terms of molar ratio converted to In2O3:ZnO = 15:2 to 3:4). For example, when a target used for forming an In-Zn-O-based oxide semiconductor has an atomic ratio of In:Zn:O = X:Y:Z, then Z > 1.5X + Y.

[0290] In addition, an In-Sn-Zn-based oxide can be called ITZO, and the composition of the target to be used ​The ratio is In:Sn:Zn in an atomic ratio of 1:2:2, 2:1:3, 1:1:1, or an oxide target having a ratio such as 20:45:35 is used.

[0291] Next, the chamber atmosphere in which the substrate is placed is nitrogen or dry air, and a first heat treatment is performed. The temperature of the first heat treatment is 400°C or higher and 750°C or lower. By the first heat treatment a first crystalline oxide semiconductor layer 450a is formed (see Fig. 23(A)).

[0292] Although it depends on the substrate temperature during film formation and the temperature of the first heat treatment, by the first heat treatment, crystallization occurs from the film surface, crystal growth proceeds from the film surface toward the inside, and c-axis oriented crystals are obtained. By the first heat treatment, a large amount of zinc and oxygen gather on the film surface, and a graphene-type two-dimensional crystal composed of zinc and oxygen with a hexagonal upper plane is formed in one or more layers on the outermost surface, and this grows in the film thickness direction and overlaps and stacks. When the temperature of the heat treatment is increased, crystal growth proceeds from the surface to the inside and from the inside to the bottom. From the first heat treatment, oxygen in the insulating layer 437, which is an oxide insulating layer, diffuses to the interface between the first crystalline oxide semiconductor layer 450a or the vicinity thereof (plus or minus 5 nm from the interface)

[0293] to reduce the oxygen deficiency of the first crystalline oxide semiconductor layer. Therefore, the insulating layer 437 that can be used as the underlying insulating film should preferably have at least an amount of oxygen exceeding the stoichiometric composition ratio at any of the interface between the first crystalline oxide semiconductor layer 450a and the insulating layer 437 in the film (in the bulk).

[0294] Next, a second oxide semiconductor thicker than 10 nm is formed on the first crystalline oxide semiconductor layer 450a ​​​​A body film is formed. The second oxide semiconductor film is formed using a sputtering method, and during the film formation the substrate temperature is set to be 200°C or higher and 400°C or lower. By setting the substrate temperature during the film formation to be 200 °C or higher and 400°C or lower, the alignment of the precursors occurs in the oxide semiconductor layer formed in contact with the surface of the first crystalline oxide semiconductor layer, and so-called orderliness can be imparted to it. .

[0295] In this embodiment, a target for an oxide semiconductor (a target for an In-Ga-Zn-O-based oxide semiconductor (In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio]) is used, and the distance between the substrate and the target is 170 mm, the substrate temperature is 400°C, the pressure is 0.4 Pa, and a direct current (DC) power supply is 0.5 kW. A second oxide semiconductor film with a film thickness of 25 nm is formed in an atmosphere of only oxygen, only argon, or an argon and oxygen atmosphere.

[0296] Next, the chamber atmosphere in which the substrate is placed is set to a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen, and a second heat treatment is performed. The temperature of the second heat treatment is 400°C or higher and 750°C or lower. By the second heat treatment, a second crystalline oxide semiconductor layer 450b is formed (see FIG. 23(B)). The second heat treatment is performed in a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen to increase the density of the second crystalline oxide semiconductor layer and reduce the number of defects. By the second heat treatment, crystal growth proceeds in the film thickness direction, that is, from the bottom to the inside, with the first crystalline oxide semiconductor layer 450a as a nucleus, and a second crystalline oxide semiconductor layer 450b is formed.

[0297] Also, the steps from the formation of the insulating layer 437 to the second heat treatment are continuously performed without exposure to the atmosphere. It is preferable to perform. The steps from the formation of the insulating layer 437 to the second heat treatment are carried out in an atmosphere containing almost no hydrogen and moisture (such as an inert atmosphere, a reduced-pressure atmosphere, a dry air atmosphere, etc.). It is preferably controlled. For example, for moisture, a dry nitrogen atmosphere with a dew point of -40°C or lower, preferably a dew point of -50°C or lower is used.

[0298] Next, an oxide semiconductor laminate composed of the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b is processed to form an oxide semiconductor layer 45 formed of an island-shaped oxide semiconductor laminate (see Fig. 23(C)). In the figure, the interface between the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b is shown by a dotted line and is described as an oxide semiconductor laminate, but there is no distinct interface. It is illustrated only for the sake of easy understanding.

[0299] The processing of the oxide semiconductor laminate can be carried out by forming a mask with a desired shape on the oxide semiconductor laminate and then etching the oxide semiconductor laminate. The above-mentioned mask can be formed by using a method such as photolithography. Or, a mask may be formed by using a method such as the inkjet method.

[0300] Note that the etching of the oxide semiconductor laminate may be either dry etching or wet etching. Of course, these may be used in combination.

[0301] Also, one of the characteristics of the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer obtained by the above manufacturing method is that they have a c-axis orientation. However, the first crystal The first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer have a structure that is not a single crystal structure nor an amorphous structure, and have an oxide containing a crystal having a c-axis orientation (also referred to as C Axis Aligned Crystal; CAAC). Note that the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer partially have crystal grain boundaries. It is a structure that is not, and has an oxide containing a crystal having a c-axis orientation (also called C Axis Aligned Crystal; CAAC). In addition, the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer partially have crystal grain boundaries. layer and the second crystalline oxide semiconductor layer partially have crystal grain boundaries.

[0302] The oxide semiconductor to be used preferably contains at least indium (In) or zinc (Zn). In particular, it is preferably contained In and Zn. Further, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Further, it is preferable to have tin (Sn as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer. for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Further, it is preferable to have tin (Sn as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer. ) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer. as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer. is.

[0303] Further, as another stabilizer, it may have any one or more of lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu), which are lanthanoids.

[0304] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide which is a binary metal oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based Oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, and ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, and quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides can be used.

[0305] Here, for example, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be contained in addition to In, Ga, and Zn.

[0306] Moreover, it is not limited to a two-layer structure in which a second crystalline oxide semiconductor layer is formed on the first crystalline oxide semiconductor layer. After the formation of the second crystalline oxide semiconductor layer, the processes of film formation and heat treatment for forming a third crystalline oxide semiconductor layer can be repeatedly performed to form a stacked structure of three or more layers.

[0307] The oxide semiconductor layer 453 composed of the oxide semiconductor laminate formed by the above production method can be appropriately used for the transistor 162 applicable to the semiconductor device disclosed in this specification.

[0308] In addition, in the transistor in Embodiment 3 using the oxide semiconductor laminate of the present embodiment as the oxide semiconductor layer, no electric field is applied from one surface of the oxide semiconductor layer to the other surface, and the current does not flow in the thickness direction of the oxide semiconductor laminate (the direction flowing from one surface to the other surface, specifically the vertical direction in FIG. 15(A)). Since the current mainly flows through the interface of the oxide semiconductor laminate in the transistor structure, even when light irradiation is performed on the transistor or BT stress is applied, deterioration of the transistor characteristics is suppressed or reduced.

[0309] By using a laminate of a first crystalline oxide semiconductor layer and a second crystalline oxide semiconductor layer such as the oxide semiconductor layer 453 in a transistor, a transistor having stable electrical characteristics and high reliability can be realized.

[0310] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0311] (Embodiment 6) Not limited to oxide semiconductors, the field-effect mobility of an actually measured insulated-gate transistor is lower than the original mobility for various reasons. Defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film are factors that reduce the mobility, but using the Levinson model makes it possible to theoretically derive the field-effect mobility when it is assumed that there are no defects inside the semiconductor.

[0312] Let the intrinsic mobility of the semiconductor be μ0 and the measured field-effect mobility be μ. Assuming that there is some potential barrier (grain boundary, etc.) in the semiconductor, it can be expressed by the following equation. If it is assumed that there is a potential barrier (grain boundary, etc.) in the semiconductor, it can be expressed by the following equation.

[0313]

Equation

[0314] Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, assuming that the potential barrier is due to defects, in the Levinson model, it is expressed by the following equation.

[0315]

Equation

[0316] Here, e is the elementary charge, N is the average defect density per unit area in the channel, ε is the dielectric constant of the semiconductor, n is the number of carriers contained in the channel per unit area, C is the capacitance per unit area, V ox is the gate voltage, and t is the thickness of the channel. Note that for a semiconductor layer with a thickness of 30 nm or less, the thickness of the channel can be regarded as the same as the thickness of the semiconductor layer. In the linear region, the drain current I is given by the following equation. g For a semiconductor layer with a thickness of 30 nm or less, the thickness of the channel can be regarded as the same as the thickness of the semiconductor layer without any problem. In the linear region, the drain current I is given by the following equation. In the linear region, the drain current I d is given by the following equation.

[0317]

Equation

[0318] Here, L is the channel length and W is the channel width. Here, L = W = 10 μm. Also, V d is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides, It becomes as follows.

[0319]

Number

[0320] The right side of Equation 5 is a function of V g . As can be seen from this equation, the defect density N is obtained from the slope of the straight line of the graph obtained by plotting the measured values with the vertical axis as ln(Id / Vg) and the horizontal axis as 1 / Vg. That is, the defect density can be evaluated from the I -V d characteristics of the transistor. g As the oxide semiconductor, when the ratio of indium (In), tin (Sn), and zinc (Zn) is I n:Sn:Zn = 1:1:1, the defect density N is about 1×10 12 / cm 2 .

[0321] Based on the defect density etc. obtained in this way, μ0 = 120 cm 2 / Vs is derived from Equations 2 and 3. The mobility measured in the defective In-Sn-Zn based oxide is about 35 cm 2 / Vs. However, even if there are no defects inside the semiconductor, the transport characteristics of the transistor are affected by scattering at the interface between the channel and the gate insulating film. That is, the mobility μ1 at a location x away from the gate insulating film interface is expressed by the following equation. The mobility μ0 of the oxide semiconductor without defects at the interface between the semiconductor and the insulating film can be expected to be 120 cm 2 / Vs.

[0322] However, even if there are no defects inside the semiconductor, the transport characteristics of the transistor are affected by scattering at the interface between the channel and the gate insulating film. That is, the mobility μ1 at a location x away from the gate insulating film interface is expressed by the following equation.

[0323]

Number

[0324] Here, D is the electric field in the gate electrode direction, and B and G are constants. B and G can be obtained from actual measurement results. From the above measurement results, B = 4.75×10 cm / s, G = 7 10 nm (depth affected by interface scattering). As D increases (i.e., the gate voltage increases), the second term in Equation (6) increases, so it can be seen that the mobility μ1 decreases. The mobility μ2 of a transistor using an ideal oxide semiconductor without defects inside the semiconductor as the channel is shown in FIG. 27. For the calculation, the device simulation software Sentaurus Device manufactured by Synopsys was used, and the bandgap, electron affinity, relative permittivity, and thickness of the oxide semiconductor were set to 2.8 electron volts, 4.7 electron volts,

[0325] 15, and 15 nm, respectively. These values were obtained by measuring a thin film formed by the sputtering method. In addition, the work functions of the gate electrode, source electrode, and drain electrode were set to 5.5 electron volts, 4.6 electron volts, and 4.6 electron volts, respectively. The thickness of the gate insulating film was 100 nm, and the relative permittivity was 4.1. Both the channel length and channel width were 10 μm, and the drain voltage V was 0.1 V.

[0326] As shown in FIG. 27, a peak with a mobility of 100 cm / Vs or more appears at a gate voltage of 1 V or higher. However, as the gate voltage further increases, the interface scattering becomes larger and the mobility decreases. Note that in order to reduce interface scattering, the surface of the semiconductor layer needs to be flattened at the atomic level (At d ).

[0327] As shown in FIG. 27, a peak with a mobility of 100 cm 2 / Vs or more appears at a gate voltage of 1 V or higher. However, as the gate voltage further increases, the interface scattering becomes larger and the mobility decreases. Note that in order to reduce interface scattering, the surface of the semiconductor layer needs to be flattened at the atomic level (At omic-level surface flattening) and the interface ​(Omic Layer Flatness) is desirable.

[0328] The characteristics when a fine transistor is fabricated using an oxide semiconductor having such a mobility are calculated, and the results are shown in FIGS. 28 to 30. Note that the cross-sectional structure of the transistor used in the calculation is shown in FIG. 31. The transistor shown in FIG. 31 has semiconductor regions 2103a and 2103c that exhibit an n type conductivity in the oxide semiconductor layer. The resistivity of the semiconductor regions 2103a and 2103c is set to 2 × 10 + Ωcm. The transistor shown in FIG. 31(A) is formed on a base insulating film 2101 and an embedded insulator 2102 made of aluminum oxide formed so as to be embedded in the base insulating film 2101. The transistor has semiconductor regions 2103a and 2103c, a true semiconductor region 2103b that is sandwiched between them and serves as a channel formation region, and a gate electrode 2105. The width of the gate electrode 2105 is 33 nm. There is a gate insulating film 2104 between the gate electrode 2105 and the semiconductor region 2103b, and sidewall insulators 2106a and 2106b are provided on both side surfaces of the gate electrode 2105. -3 There is an insulator 2107 for preventing a short circuit between the gate electrode 2105 and other wirings on the upper part of the gate electrode 2105. The width of the sidewall insulator is 5 nm. Also, source electrodes 2108a and drain electrodes 2

[0329] 108b are provided in contact with the semiconductor regions 2103a and 2103c. Note that the channel width in this transistor is 40 nm. are formed. The transistor has semiconductor regions 2103a, 2103c, and a true semiconductor region 2103b that is sandwiched between them and serves as a channel formation region, and a gate electrode 2105. The width of the gate electrode 2105 is set to 33 nm. There is a gate insulating film 2104 between the gate electrode 2105 and the semiconductor region 2103b, and sidewall insulators 2106a and 2106b are provided on both side surfaces of the gate electrode 2105.

[0330] There is an insulator 2107 for preventing a short circuit between the gate electrode 2105 and other wirings on the upper part of the gate electrode 2105. The width of the sidewall insulator is 5 nm. Also, source electrodes 2108a and drain electrodes 2 108b are provided in contact with the semiconductor regions 2103a and 2103c. Note that the channel width in this transistor is 40 nm. There is an insulator 2107 for preventing a short circuit between the gate electrode 2105 and other wirings on the upper part of the gate electrode 2105. The width of the sidewall insulator is 5 nm. Also, source electrodes 2108a and drain electrodes 2 108b are provided in contact with the semiconductor regions 2103a and 2103c. Note that the channel width in this transistor is 40 nm.

[0331] The transistor shown in Fig. 31(B) has a base insulating film 2101 and is formed on an embedded insulator 2102 made of aluminum oxide. It has a semiconductor region 2103a, a semiconductor region 2103c, a true semiconductor region 2103b sandwiched between them, a gate electrode 2105 with a width of 33 nm, a gate insulating film 2104, sidewall insulators 2106a and 2106b, an insulator 2107, a source electrode 2108a, and a drain electrode 2108b, and is the same as the transistor shown in Fig. 31(A) in these aspects. The difference between the transistor shown in Fig. 31(A) and the transistor shown in Fig. 31(B) lies in the conductivity type of the semiconductor region under the sidewall insulators 2106a and 2106b. In the transistor shown in Fig. 31(A), the semiconductor regions under the sidewall insulators 2106a and 2106b are semiconductor regions 2103a and 2103c that exhibit an n conductivity type. However, in the transistor shown in Fig. 31(B), it is the true semiconductor region 2103b. That is, in the semiconductor layer shown in Fig. 31(B), a region is formed where the semiconductor region 2103a (semiconductor region 2103c) and the gate electrode 2105 do not overlap by only Loff. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b). The other parameters used in the calculation are as described above. For the calculation, Synopsys' device simulation software, Sentaurus Device, was used. Fig. 28 shows the drain current (Id, solid line) and mobility of the transistor with the structure shown in Fig. 31(A).

[0332] The difference between the transistor shown in Fig. 31(A) and the transistor shown in Fig. 31(B) lies in the conductivity type of the semiconductor region under the sidewall insulators 2106a and 2106b. In the transistor shown in Fig. 31(A), the semiconductor regions under the sidewall insulators 2106a and 2106b are semiconductor regions 2103a and 2103c that exhibit an n conductivity type. However, in the transistor shown in Fig. 31(B), it is the true semiconductor region 2103b. That is, in the semiconductor layer shown in Fig. 31(B), a region is formed where the semiconductor region 2103a (semiconductor region 2103c) and the gate electrode 2105 do not overlap by only Loff. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b). + In the transistor shown in Fig. 31(A), the semiconductor regions under the sidewall insulators 2106a and 2106b are semiconductor regions 2103a and 2103c that exhibit an n conductivity type. However, in the transistor shown in Fig. 31(B), it is the true semiconductor region 2103b. That is, in the semiconductor layer shown in Fig. 31(B), a region is formed where the semiconductor region 2103a (semiconductor region 2103c) and the gate electrode 2105 do not overlap by only Loff. This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b). This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b). This region is called an offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b). The offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b).

[0333] The other parameters used in the calculation are as described above. For the calculation, Synopsys' device simulation software, Sentaurus Device, was used. Fig. 28 shows the drain current (Id, solid line) and mobility of the transistor with the structure shown in Fig. 31(A). The drain current (Id, solid line) and mobility of the transistor with the structure shown in Fig. 31(A). (μ, dotted line) shows the dependence on the gate voltage (Vg, the potential difference between the gate electrode and the source electrode). Drain The drain current Id is measured with the drain voltage (the potential difference between the drain electrode and the source electrode) set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V.

[0334] Figure 28(A) shows the case where the thickness of the gate insulating film is 15nm, Figure 28(B) shows the case where it is 10n m, and Figure 28(C) shows the case where it is 5nm. As the gate insulating film becomes thinner, especially the drain current Id (off-current) in the off state decreases significantly. On the other hand, there is no significant change in the peak value of the mobility μ or the drain current Id (on-current) in the on state. Around a gate voltage of 1V, the drain current exceeds 10 μA, which is required for memory cells etc. This is shown.

[0335] Figure 29 shows the dependence of the drain current Id (solid line) and the mobility μ (dotted line) on the gate voltage Vg for a transistor with the structure shown in Figure 31(B) and an offset length Loff of 5n m. The drain current Id is measured with the drain voltage set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. Figure 29(A) shows the case where the thickness of the gate insulating film is 15nm, Figure 29(B) shows the case where it is 10nm, and Figure 29(C) shows the case where it is 5nm. Figure 29(B) shows the case where it is 10nm, and Figure 29(C) shows the case where it is 5nm. This is shown.

[0336] Also, Figure 30 shows the dependence of the drain current Id (solid line) and the mobility μ (dotted line) on the gate voltage for a transistor with the structure shown in Figure 31(B) and an offset length Loff of 15nm. The drain current Id is measured with the drain voltage set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. Figure 30(A) shows the case where the thickness of the gate insulating film is 15n is set to m, FIG. 30(B) is set to 10 nm, and FIG. 30(C) is set to 5 nm respectively.

[0337] In all cases, as the gate insulating film becomes thinner, the off-current significantly decreases, while there is no significant change in the peak value of the mobility μ or the on-current.

[0338] Note that the peak of the mobility μ is about 80 cm 2 / Vs in FIG. 28, but about 60 cm 2 / Vs in FIG. 29, and about 40 cm 2 / Vs in FIG. 30, and it decreases as the offset length Loff increases. Also, the off-current shows a similar tendency. On the other hand, the on-current also decreases as the offset length L off increases, but it is much gentler compared to the decrease in the off-current. Also, in all cases, around a gate voltage of 1 V, the drain current was shown to exceed 1 0 μA required for a memory cell or the like.

Example

[0339] A transistor having an oxide semiconductor containing In, Sn, and Zn as main components in the channel formation region can obtain good characteristics by heating the substrate during film formation of the oxide semiconductor, or by performing a heat treatment after forming the oxide semiconductor film. Note that the main component refers to an element contained in a composition ratio of 5 atomic% or more.

[0340] By intentionally heating the substrate after forming the oxide semiconductor film containing In, Sn, and Zn as main components it becomes possible to improve the field-effect mobility of the transistor. Also, it becomes possible to shift the threshold voltage of the transistor to positive and make it normally-off.

[0341] ​​​ For example, FIGS. 32(A) to (C) show the characteristics of a transistor using an oxide semiconductor film mainly composed of In, Sn, and Zn, with a channel length L of 3 μm and a channel width W of 10 μm, and a gate insulating film with a thickness of 100 nm. Note that V was set to 10 V. d

[0342] FIG. 32(A) shows the transistor characteristics when an oxide semiconductor film mainly composed of In, Sn, and Zn is formed by sputtering without intentionally heating the substrate. At this time, the field-effect mobility is 18.8 cm / Vsec. On the other hand, when the substrate is intentionally heated to form an oxide semiconductor film mainly composed of In, S n, and Zn, it becomes possible to improve the field-effect mobility. FIG. 32(B) shows the transistor characteristics when an oxide semiconductor film mainly composed of In, Sn, and Zn is formed by heating the substrate to 200°C, and the field-effect mobility is 32.2 2 cm / Vsec. The field-effect mobility can be further increased by performing heat treatment after forming an oxide semiconductor film mainly composed of In, Sn, and Zn. FIG. 32(C) shows the transistor characteristics when an oxide semiconductor film mainly composed of In, Sn, and Zn is sputter-deposited at 200°C and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm / V cm 2 / Vsec.

[0343] It is expected that intentionally heating the substrate will reduce the incorporation of moisture in the sputtering film formation process into the oxide semiconductor film. Also, by performing heat treatment after film formation, the acid can also be achieved. The substrate is heated to 200°C to form an oxide semiconductor film mainly composed of In, Sn, and Zn, and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm / V 2 / V sec.

[0344] Intentionally heating the substrate can be expected to reduce the incorporation of moisture in the sputtering film formation process into the oxide semiconductor film. Also, by performing heat treatment after film formation, the acid can be reduced. ​The hydrogen, hydroxyl group, or moisture can be released and removed from the oxide semiconductor film, and as described above the field-effect mobility can be improved. Such an improvement in the field-effect mobility is due to not only the removal of impurities by dehydration and dehydrogenation, but also the shortening of the interatomic distance due to densification, it is also presumed. In addition, crystallization can be achieved by removing impurities from the oxide semiconductor to increase its purity. The non-single crystal oxide semiconductor thus highly purified can ideally achieve a field-effect mobility exceeding 10 0 cm 2 / Vsec.

[0345] Oxygen ions can be implanted into an oxide semiconductor mainly composed of In, Sn, and Zn, and heat treatment can be used to release the hydrogen, hydroxyl group, or moisture contained in the oxide semiconductor, and the oxide semiconductor can be crystallized simultaneously with or after the heat treatment. A non-single crystal oxide semiconductor with good crystallinity can be obtained by such crystallization or recrystallization treatment.

[0346] The effects of intentionally heating the substrate during film formation and / or heat treatment after film formation contribute not only to the improvement of the field-effect mobility but also to the normal-off operation of the transistor. For a transistor with an oxide semiconductor film formed without intentionally heating the substrate as the channel formation region, the threshold voltage tends to shift negatively. However, in the case of using an oxide semiconductor film formed by intentionally heating the substrate, this negative shift of the threshold voltage is eliminated. That is, the threshold voltage moves in the direction of making the transistor normal-off, and such a tendency can also be confirmed from the comparison between Fig. 32(A) and Fig. 32(B).

[0347] Note that the threshold voltage can also be controlled by changing the ratios of In, Sn, and Zn, and it is possible to expect normal-off characteristics of the transistor by setting the composition ratio to In:Sn:Zn = 2:1:3. Also, a highly crystalline oxide semiconductor film can be obtained by setting the target composition ratio to In:Sn:Zn = 2:1:3. The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher,

[0348] more preferably 400°C or higher. By forming the film or performing heat treatment at a higher temperature, it becomes possible to achieve normal-off characteristics of the transistor. Also, by intentionally heating the substrate during film formation and / or performing heat treatment after film formation, the stability against gate bias stress can be enhanced. For example, under the conditions of applying 2 MV / cm, 150°C, for 1 hour, drifts of less than ±1.5 V, preferably less than 1.0 V, can be obtained respectively.

[0349] Actually, a BT test was conducted on the transistors of sample 1 that had not been heat-treated after forming the oxide semiconductor film and sample 2 that had been heat-treated at 650°C. First, the substrate temperature was set to 25°C, Vd was set to 10 V, and the Vg-Id characteristics of the transistor were measured. Here, V represents the drain voltage (the potential difference between the drain and the source). Next, the substrate

[0350] temperature was set to 150°C and Vd was set to 0.1 V. Next, 20 V was applied to Vg so that the electric field strength applied to the gate insulating film became 2 MV / cm, and it was held for 1 hour. Next, V was maintained.

[0351] First, the substrate temperature was set to 25°C, Vd was set to 10 V, and the Vg-Id characteristics of the transistor were measured. Note that V d represents the drain voltage (the potential difference between the drain and the source). Next, the substrate temperature was set to 150°C and Vd was set to 0.1 V. Next, 20 V was applied to Vg so that the electric field strength applied to the gate insulating film became 2 MV / cm, and it was held for 1 hour. Next, V was maintained. g was set to 0 V. Next, the substrate temperature was set to 25 °C, Vd was set to 10 V, and the Vg- Id measurement was performed. This is called the plus BT test.

[0352] Similarly, first, the substrate temperature was set to 25 °C, Vd was set to 10 V, and the Vg-Id characteristics of the transistor were measured. Next, the substrate temperature was set to 150 °C and Vd was set to 0.1 V. Next, −20 V was applied to Vg so that the electric field strength applied to the gate insulating film became −2 MV / cm, and it was held for 1 hour as it was. Next, Vg was set to 0 V. Next, the substrate temperature was set to 25 °C, Vd was set to 1 0 V, and the Vg-Id measurement of the transistor was performed. This is called the minus BT test.

[0353] The results of the plus BT test of Sample 1 are shown in Fig. 33(A), and the results of the minus BT test are shown in Fig. 33(B ). Also, the results of the plus BT test of Sample 2 are shown in Fig. 34(A), and the results of the minus BT test are shown in Fig. 34(B).

[0354] The variations in the threshold voltage due to the plus BT test and the minus BT test of Sample 1 were 1.80 V and −0.42 V, respectively. Also, the variations in the threshold voltage due to the plus BT test and the minus BT test of Sample 2 were 0.79 V and 0.76 V, respectively. It can be seen that both Sample 1 and Sample 2 have small variations in the threshold voltage before and after the BT test and high reliability.

[0355] The heat treatment can be performed in an oxygen atmosphere, but first, heat treatment may be performed under nitrogen or an inert gas, or under reduced pressure, and then heat treatment may be performed in an atmosphere containing oxygen. By performing dehydration and dehydrogenation first and then adding oxygen to the oxide semiconductor, the effect of the heat treatment can be further enhanced. It is also possible to accelerate oxygen ions in an electric field and inject them into the oxide semiconductor film when adding oxygen later. This method may be applicable.

[0356] Defects due to oxygen deficiency are likely to be generated in the oxide semiconductor and at the interface between the oxide semiconductor and the film in contact therewith. However, by making the oxide semiconductor contain an excessive amount of oxygen through such heat treatment, it becomes possible to compensate for the constantly generated oxygen deficiency with excessive oxygen. The excessive oxygen mainly exists in the interstitial sites of the lattice, and its oxygen concentration is 1×10 16 / cm 3 or more and 2×10 20 / cm 3 or less. If this is done, it can be included in the oxide semiconductor without causing distortion or the like in the crystal. This can be achieved.

[0357] Also, by making at least a part of the oxide semiconductor contain crystals through heat treatment, a more stable oxide semiconductor film can be obtained. For example, using a target with a composition ratio of In:Sn:Zn = 1 :1:1, an oxide semiconductor film formed by sputtering without intentionally heating the substrate shows a halo pattern in X-ray diffraction (XRD: X-Ray Diffraction). By heat-treating this formed oxide semiconductor film, it can be crystallized. The heat treatment temperature is arbitrary. For example, by performing heat treatment at 650°C, clear diffraction peaks can be observed by X-ray diffraction. Actually, XRD analysis of the In-Sn-Zn-O film was performed. For the XRD analysis, an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used and measured by the Out-of-Plane method.

[0358] AXS was used and measured by the Out-of-Plane method. This was measured.

[0359] As samples for XRD analysis, Sample A and Sample B were prepared. The preparation methods of Sample A and Sample B are described below. The preparation method of Sample B will be described.

[0360] An In-Sn-Zn-O film was formed with a thickness of 100 nm on a dehydrogenated quartz substrate. .

[0361] The In-Sn-Zn-O film was formed using a sputtering apparatus with a power of 100 W (DC) in an oxygen atmosphere. The target used was an In-Sn-Zn-O target with an atomic ratio of In:Sn:Zn = 1:1:1. The substrate heating temperature during film formation was 200 °C. The sample prepared in this way was designated as Sample A. DC) during film formation. The target used was an In-Sn-Zn-O target with an atomic ratio of In:Sn:Zn = 1:1:1. The substrate heating temperature during film formation was 200 °C. The sample prepared in this way was designated as Sample A. DC) during film formation. The target used was an In-Sn-Zn-O target with an atomic ratio of In:Sn:Zn = 1:1:1. The substrate heating temperature during film formation was 200 °C. The sample prepared in this way was designated as Sample A. The sample prepared in this way was designated as Sample A.

[0362] Next, heat treatment was performed on the sample prepared in the same manner as Sample A at a temperature of 650 °C. The heat treatment was carried out by first heating in a nitrogen atmosphere for 1 hour and then further heating in an oxygen atmosphere for 1 hour without lowering the temperature. The sample prepared in this way was designated as Sample B. Next, heat treatment was performed on the sample prepared in the same manner as Sample A at a temperature of 650 °C. The heat treatment was carried out by first heating in a nitrogen atmosphere for 1 hour and then further heating in an oxygen atmosphere for 1 hour without lowering the temperature. The sample prepared in this way was designated as Sample B. Next, heat treatment was performed on the sample prepared in the same manner as Sample A at a temperature of 650 °C. The heat treatment was carried out by first heating in a nitrogen atmosphere for 1 hour and then further heating in an oxygen atmosphere for 1 hour without lowering the temperature. The sample prepared in this way was designated as Sample B.

[0363] The XRD spectra of Sample A and Sample B are shown in Fig. 35. In Sample A, no peaks derived from crystals were observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg - 38 deg. The XRD spectra of Sample A and Sample B are shown in Fig. 35. In Sample A, no peaks derived from crystals were observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg - 38 deg. The XRD spectra of Sample A and Sample B are shown in Fig. 35. In Sample A, no peaks derived from crystals were observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg - 38 deg.

[0364] Thus, the characteristics of transistors can be improved by intentionally heating the oxide semiconductor during film formation and / or performing heat treatment after film formation. Thus, the characteristics of transistors can be improved by intentionally heating the oxide semiconductor during film formation and / or performing heat treatment after film formation. Thus, the characteristics of transistors can be improved by intentionally heating the oxide semiconductor during film formation and / or performing heat treatment after film formation.

[0365] This substrate heating and heat treatment can remove hydrogen and hydroxyl groups, which are harmful impurities to the oxide semiconductor, from the film. To prevent inclusion therein or to remove it from the film. That is, high purity can be achieved by removing hydrogen which becomes a donor impurity in the oxide semiconductor, thereby making the transistor normally-off, and by making the oxide semiconductor highly pure, the off-current can be made 1 aA / μm or less. Here, the unit of the off-current value indicates the current value per 1 μm of channel width. By removing hydrogen which becomes a donor impurity in the oxide semiconductor, high purity can be achieved, thereby making the transistor normally-off, and by making the oxide semiconductor highly pure, the off-current can be made 1 aA / μm or less. Here, the unit of the off-current value indicates the current value per 1 μm of channel width. By making the oxide semiconductor highly pure, the off-current can be made 1 aA / μm or less. Here, the unit of the off-current value indicates the current value per 1 μm of channel width.

[0366] Fig. 36 shows the relationship between the off-current of the transistor and the reciprocal of the substrate temperature (absolute temperature) during measurement. Here, for simplicity, the horizontal axis is the value obtained by multiplying the reciprocal of the substrate temperature during measurement by 1000 (1000 / T). Here, for simplicity, the horizontal axis is the value obtained by multiplying the reciprocal of the substrate temperature during measurement by 1000 (1000 / T). Here, for simplicity, the horizontal axis is the value obtained by multiplying the reciprocal of the substrate temperature during measurement by 1000 (1000 / T).

[0367] Specifically, as shown in Fig. 36, when the substrate temperature is 125 °C, it can be made 1 aA / μm (1 × 10 0 -18 A / μm) or less, when it is 85 °C, it can be made 100 zA / μm (1 × 10 -19 A / μm ) or less, and when it is room temperature (27 °C), it can be made 1 zA / μm (1 × 10 -21 A / μm) or less. Preferably, at 125 °C, it can be made 0.1 aA / μm (1 × 10 A / μm) or less, at 85 °C, it can be made 10 zA / μm (1 × 10 -19 A / μm) or less, and at room temperature, it can be made 0.1 zA / μm (1 × 10 A / μm) or less. -20 A / μm) or less, and at room temperature, it can be made 0.1 zA / μm (1 × 10 A / μm) or less. -22 A / μm) or less.

[0368] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during film formation, it is preferable to sufficiently suppress leakage from outside the film formation chamber and outgassing from the inner wall of the film formation chamber, and to make the sputtering gas highly pure. For example, the sputtering gas should have a dew point of -70 °C or lower so that no moisture is contained in the film. However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during film formation, it is preferable to sufficiently suppress leakage from outside the film formation chamber and outgassing from the inner wall of the film formation chamber, and to make the sputtering gas highly pure. For example, the sputtering gas should have a dew point of -70 °C or lower so that no moisture is contained in the film. It is preferable to use a gas that is within the range of 1000 to 2000 nm. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors that are mainly composed of In, Sn, and Zn can be heat-treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0369] In addition, the transistor using Sample B, which was subjected to heat treatment at 650° C. after the formation of the oxide semiconductor film The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0370] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov The thickness is 0 μm and dW is 0 μm. Vd is 10 V. The substrate temperature is -40°C. , -25°C, 25°C, 75°C, 125°C and 150°C. In this case, the overlapping width between the gate electrode and the pair of electrodes is called Lov, and The protrusion of the pair of electrodes is called dW.

[0371] FIG. 37 shows the Vg dependence of Id (solid line) and field effect mobility (dotted line). Fig. 8(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 38(B) shows the relationship between the substrate temperature and the field-effect mobility. The relationship is shown below.

[0372] From FIG. 38(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0373] Moreover, from FIG. 38(B), it can be seen that the higher the substrate temperature, the lower the field effect mobility. The range was 36 cm at -40°C to 150°C 2 / Vs to 32 cm 2 / Vs. Therefore, it can be seen that the fluctuations in electrical characteristics are small in the above temperature range.

[0374] For a transistor having an oxide semiconductor containing In, Sn, and Zn as main components in a channel formation region, while keeping the off-current at 1 aA / μm or less, the field-effect mobility is 30 c m 2 / Vsec or more, preferably 40 cm 2 / Vsec or more, more preferably 60 cm 2 / Vsec or more, and it is possible to satisfy the on-current value required for LSI. For example, in an FET with L / W = 33 nm / 40 nm, when the gate voltage is 2.7 V and the drain voltage is 1.0 V it is possible to flow an on-current of 12 μA or more. Also, sufficient electrical characteristics can be ensured even in the temperature range required for the operation of the transistor. With such characteristics, even if a transistor formed of an oxide semiconductor is mixed in an integrated circuit made of an Si semiconductor, it is possible to realize an integrated circuit having a new function without sacrificing the operating speed.

Example

[0375] In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film will be described with reference to FIG. 39.

[0376] FIG. 39 is a top view and a cross-sectional view of a transistor having a coplanar top-gate and top-contact structure. FIG. 39(A) shows the top view of the transistor. Also, FIG. 39( B) shows a cross-section A1-A2 corresponding to the dashed line A1-A2 in FIG. 39(A).

[0377] The transistor shown in FIG. 39(B) includes a substrate 3100, an underlying insulating film 3102 provided on the substrate 3100, a protective insulating film 3104 provided around the underlying insulating film 3102, a high-resistance region 3106a and a low-resistance region 3106b provided on the underlying insulating film 3102 and the protective insulating film 3104, an oxide semiconductor film 3106 having a gate insulating film 3108 provided on the oxide semiconductor film 3106, a gate electrode 3110 provided to overlap the oxide semiconductor film 310 6 with the gate insulating film 3108 interposed therebetween, sidewall insulating films 3112 provided in contact with side surfaces of the gate electrode 3110, a pair of electrodes 3114 provided in contact with at least the low-resistance region 3106b, an interlayer insulating film 3116 provided to cover at least the oxide semiconductor film 3106, the gate electrode 3110, and the pair of electrodes 3114, and a wiring 31 18 provided to be connected to at least one of the pair of electrodes 3114 through an opening provided in the interlayer insulating film 3116. Although not shown, a protective film may be provided to cover the interlayer insulating film 3116 and the wiring 3118. By providing the protective film, it is possible to reduce a minute leakage current caused by surface conduction of the interlayer insulating film 3116 and reduce the off-current of the transistor.

[0378]

Example

[0379] In this example, another example of a transistor using an In-Sn-Zn-O film different from the above is shown.

[0380] FIG. 40 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 40(A) is a top view of a transistor. Further, FIG. 40(B) is a cross-sectional view corresponding to the dashed line B1-B2 in FIG. 40(A).

[0381] The transistor shown in FIG. 40(B) includes a substrate 3600, a base insulating film 3602 provided on the substrate 3600, an oxide semiconductor film 3606 provided on the base insulating film 3602, a pair of electrodes 3614 in contact with the oxide semiconductor film 3606, a gate insulating film 3608 provided on the oxide semiconductor film 3606 and the pair of electrodes 3614, a gate electrode 3610 provided so as to overlap the oxide semiconductor film 3606 with the gate insulating film 3608 interposed therebetween, an interlayer insulating film 3616 provided so as to cover the gate insulating film 3608 and the gate electrode 3610, a wiring 3618 connected to the pair of electrodes 3614 through an opening provided in the interlayer insulating film 3616, and a protective film 3620 provided so as to cover the interlayer insulating film 3616 and the wiring 3618.

[0382] As the substrate 3600, a glass substrate is used. As the base insulating film 3602, a silicon oxide film is used. As the oxide semiconductor film 3606, an In-Sn-Zn-O film is used. As the pair of electrodes 3614, a tungsten film is used. As the gate insulating film 3608, a silicon oxide film is used. As the gate electrode 3610, a laminated structure of a tantalum nitride film and a tungsten film is used. As the interlayer insulating film 3616, a laminated structure of a silicon oxynitride film and a polyimide film is used. As the wiring 3618, a laminated structure in which a titanium film, an aluminum film, and a titanium film are formed in this order is used. As the protective film 3620, a polyimide film is used, respectively.

[0383] In the transistor having the structure shown in FIG. 40(A), between the gate electrode 3610 and the pair of electrodes ​​​​​​​​​​​​​​The width overlapping with the electrode 3614 is called Lov. Similarly, the overhang of the pair of electrodes 3614 with respect to the oxide semiconductor film 3606 is called dW. The overhang of the pair of electrodes 3614 is called dW.

Explanation of symbols

[0384] 100 Circuit 101 Transistor 102 Region 120 Semiconductor layer 122 Insulating layer 124 Mask 126 Impurity region 130 Impurity region 132 Impurity region 134 Channel formation region 136 Insulating layer 138 Insulating layer 140 Insulating layer 144 Oxide semiconductor layer 146 Gate insulating film 150 Insulating layer 154 Wiring 156 Insulating layer 160 Transistor 162 Transistor 162A Transistor 162B Transistor 164 Capacitor element 200 Circuit 201 Transistor 202 Transistor 203 Region 300 Substrate 301 Element formation layer 302 Wiring 303 Wiring 304 Wiring 305 Interlayer film 306 Interlayer film 400 Semiconductor substrate 401 Insulating layer 404a Oxide conductive layer 404b Oxide conductive layer 410 Single crystal semiconductor substrate 412 Oxide film 414 Brittle region 416 Single-crystalline semiconductor layer 418 Single-crystalline semiconductor layer 437 Insulating layer 450a First crystalline oxide semiconductor layer 450b Second crystalline oxide semiconductor layer 453 Oxide semiconductor layer 500 Loader decoder 501 Load driver 502 Memory cell 503 NAND gate 504 NAND gate section 505 Level shifter 506 Buffer 507 NAND gate 508 Level shifter 509 Buffer 601 N-type transistor 603 P-type transistor 605 Signal line 606 Signal line 607 Region 700 Signal line 702 NAND gate 704 Signal line 705 Region 706 Interlayer film 707 Housing 708 Housing 709 Display unit 710 Keyboard 711 Main body 712 Stylus 713 Display unit 714 Operation button 715 External interface 720 E-book 721 Housing 723 Housing 725 Display unit 727 Display unit 731 Power supply 733 Operation key 735 Speaker 737 Shaft portion 740 Housing 741 Housing 742 Display Panel 743 Speaker 744 Microphone 745 Operation Key 746 Pointing Device 747 Camera Lens 748 External Connection Terminal 749 Solar Cell 750 External Memory Slot 761 Main Body 763 Eyepiece 764 Operation Switch 765 Display Unit 766 Battery 767 Display Unit 770 Television Set 771 Housing 773 Display Unit 775 Stand 780 Remote Control Unit 800 Signal Line 802 NAND Gate 804 Signal Line 805 Region 900 Inverter 901 N-Type Transistor 903 P-Type Transistor 910 Input Signal Line 911 Inverted Signal Input Line 912 Output Signal Line 913 Inverted Signal Output Line 1000 Transistor 1001 Wiring 1002 Wiring 1003 Region 1006 Interlayer Film 1100 Transistor 1101 Wiring 1102 Wiring 1103 Region 1201 Transistor 1202 Transistor 1203 Capacitive Element 122a Gate Insulating Film 128a gate electrode 128b conductive layer 1300 layer 1301 transistor 1302 transistor 1400 inverter 1401 N-type transistor 1403 P-type transistor 1407 N-type transistor 1408 P-type transistor 1410 input signal line 1411 inverted signal input line 1412 output signal line 1413 inverted signal output line 142a source electrode 142b drain electrode 148a gate electrode 148b conductive layer 1500 transistor 1501 wiring 1502 wiring 1503 region 1506 interlayer film 1600 signal line 1601 circuit 1602 buffer 1603 circuit 1604 signal line 1605 signal line 302a wiring 302b wiring 303a wiring 303b wiring 703a transistor 703b transistor 803a transistor 803b transistor 2101 underlayer insulating film 2102 embedded insulator 2103a semiconductor region 2103b semiconductor region 2103c semiconductor region 2104 gate insulating film 2105 gate electrode 2106a Sidewall insulator 2106b Sidewall insulator 2107 Insulator 2108a Source electrode 2108b Drain electrode 3100 Substrate 3102 Underlying insulating film 3104 Protective insulating film 3106 Oxide semiconductor film 3106a High-resistance region 3106b Low-resistance region 3108 Gate insulating film 3110 Gate electrode 3112 Sidewall insulating film 3114 Pair of electrodes 3116 Interlayer insulating film 3118 Wiring 3600 Substrate 3602 Underlying insulating film 3604 Protective insulating film 3606 Oxide semiconductor film 3608 Gate insulating film 3610 Gate electrode 3614 Pair of electrodes 3616 Interlayer insulating film 3618 Wiring 3620 Protective film

Claims

【Claim 1】 An element formation layer having at least a first semiconductor element; A first wiring provided on the element formation layer; An interlayer film provided on the first wiring; A second wiring that overlaps the first wiring via the interlayer film, and having: The first wiring, the interlayer film, and the second wiring constitute a second semiconductor element; A semiconductor device in which the first wiring and the second wiring are wirings to which the same potential is supplied.

Images