Semiconductor device

Abstract

To provide a semiconductor device which can suppress outflow of a solder.SOLUTION: A semiconductor device A1 includes a substrate 10, a wiring part 20, a joint part 40, a semiconductor element 50, and a sealing resin 60. The substrate 10 has a substrate main surface 101 and a substrate rear face 102 facing opposite to each other. A wiring part 20 has a conductive layer formed on the substrate main surface 101. The joint part 40 has a first plated layer 41 formed on the upper surface of the wiring part, and a first solder layer 42 formed on the upper surface of the first plated layer 41. The semiconductor element 50 has an element main surface 501 facing the substrate main surface 101, an element electrode 55 formed on the element main surface 501, and a second solder layer 56 which is formed on the lower surface of the element electrode 55 and is joined to the first solder layer 42. The sealing resin 60 covers the semiconductor element 50. The joint part 40 is larger than the element electrode 55, when being viewed from a thickness direction vertical to the substrate main surface 101. The thickness of the first solder layer 42 is equal to or less than the thickness of the first plated layer 41.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, an electronic component including elements such as a resistor and a semiconductor chip includes a substrate on which the elements are mounted and a sealing resin that covers the elements. For example, Patent Document 1 discloses a semiconductor device including a wiring body having external connection terminals on one surface and a semiconductor chip mounted on the other surface, and a sealing resin formed on the other surface of the wiring body so as to seal the semiconductor chip.

[0003] In recent years, with the miniaturization of electronic devices, miniaturization of semiconductor devices applied to such electronic devices has been demanded. In response to such a demand, Patent Document 2 discloses an example of a miniaturized semiconductor device. The semiconductor device includes a semiconductor wafer, a flip-chip mounted semiconductor chip, and a sealing sheet containing a thermosetting synthetic resin. The semiconductor wafer serves as a substrate on which the semiconductor chip is mounted. The semiconductor chip is flip-chip mounted on wiring provided on the upper surface of the semiconductor wafer. The sealing sheet is laminated on the semiconductor wafer and covers the semiconductor chip. Since the semiconductor wafer has a relatively small thickness, the semiconductor device is miniaturized.

[0004] In the manufacture of the above-described semiconductor device, there is a concern that when the sealing sheet thermosets, the semiconductor device may warp due to the linear expansion coefficient of the sealing sheet being larger than that of the semiconductor wafer. Therefore, the sealing sheet of the semiconductor device disclosed in Patent Document 2 has a two-layer structure including an embedding resin layer having different minimum melt viscosities from each other and a hard layer laminated on the embedding resin layer. The embedding resin layer is in contact with the semiconductor wafer and covers the semiconductor chip. The hard layer is located on the side opposite to the semiconductor wafer with respect to the embedding resin layer in the thickness direction of the semiconductor device. The minimum melt viscosity of the hard layer is larger than that of the embedding resin layer. Thereby, it is possible to reduce the warpage of the semiconductor device. However, the semiconductor device disclosed in Patent Document 2 has a problem that miniaturization of the semiconductor device is hindered because the overall thickness of the sealing sheet becomes larger in order to reduce the warpage of the sealing sheet.

[0005] Furthermore, as an example of an electronic component, an electronic component module including a circuit board, a plurality of functional elements mounted on the upper surface of the circuit board, and a sealing resin for sealing the plurality of functional elements is known (see, for example, Patent Document 3).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

[0007] [Summary] Incidentally, the semiconductor chip is soldered to the conductive layer of the wiring body by a reflow process. Cu (copper) is used for the conductive layer. Therefore, the solder that has become liquid due to heating during the reflow process may flow out along the conductive layer. If the solder flows out in an unintended direction in this way, there is a risk of a short-circuit defect problem.

[0008] The semiconductor device according to the first aspect of the present disclosure includes a substrate having a substrate main surface and a substrate back surface facing opposite sides, a wiring portion having a conductive layer formed on the substrate main surface, a first plating layer formed on the upper surface of the wiring portion, a bonding portion having a first solder layer formed on the upper surface of the first plating layer, an element main surface facing the substrate main surface, an element electrode formed on the element main surface, and a semiconductor element having a second solder layer formed on the lower surface of the element electrode and joined to the first solder layer, and a sealing resin covering the semiconductor element. The bonding portion is larger than the element electrode when viewed from the thickness direction perpendicular to the substrate main surface, and the thickness of the solder layer is equal to or less than the thickness of the first plating layer.

Brief Description of the Drawings

[0009]

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[0010] [Detailed Description] Hereinafter, embodiments and modified examples will be described with reference to the drawings. The embodiments and modified examples shown below illustrate configurations and methods for embodying technical ideas, and do not limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below. Various modifications can be made to the following embodiments and modified examples. Also, the following embodiments and modified examples can be implemented in combination with each other as long as they do not technically conflict with each other.

[0011] (First Embodiment) Hereinafter, a semiconductor device A1 according to the first embodiment will be described with reference to FIGS. 1 to 5. As shown in FIGS. 1 and 2, the semiconductor device A1 includes a substrate 10, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring portion 20 includes a main surface wiring 21 and a through wiring 22.

[0012] FIG. 1 is a cross-sectional view of the semiconductor device A1 according to the first embodiment. FIG. 2 is a schematic plan view of the semiconductor device A1. For convenience of understanding, in FIG. 2, the semiconductor element 50 is shown by a two-dot chain line except for the sealing resin 60. FIG. 3 is a partially enlarged plan view of the semiconductor device A1, showing a part of the wiring portion 20. FIG. 4 is a partially enlarged cross-sectional view of the semiconductor device A1, showing a part of the wiring portion 20, the bonding portion 40, and the semiconductor element 50. FIG. 5 shows a part of the wiring portion 20, the bonding portion 40, and the semiconductor element 50, and shows the state before mounting.

[0013] The semiconductor device A1 shown in these figures is a device surface-mounted on a circuit board of various electronic devices. Here, for convenience of explanation, the thickness direction of the substrate 10 is referred to as the thickness direction Z. Also, the direction along one side of the semiconductor device A1 orthogonal to the thickness direction Z (the left-right direction in the plan view) is referred to as the first direction X. Further, the direction orthogonal to both the thickness direction Z and the first direction X of the substrate 10 (the up-down direction in the plan view) is referred to as the second direction Y.

[0014] As shown in FIG. 2, the semiconductor device A1 is rectangular in the thickness direction Z view. As shown in FIG. 2, the semiconductor element 50 is rectangular when viewed from the thickness direction Z. The semiconductor element 50 of the present embodiment is square when viewed from the thickness direction Z.

[0015] The semiconductor element 50 is an integrated circuit (IC) such as an LSI (Large Scale Integration), for example. Further, the semiconductor element 50 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the element main surface 501 is a surface on which the constituent members for the functions of the semiconductor element 50 are formed. Note that the semiconductor element 50 is not limited to one in which a plurality of constituent members are formed, and may be an element in which a single constituent member is formed, such as a chip capacitor or a chip inductor, or an element in which a constituent member is formed on a base material other than a semiconductor. In the present embodiment, the semiconductor element 50 is an LSI.

[0016] As shown in FIG. 2, the semiconductor device A1 has a plurality of external connection terminals 70. The external connection terminals 70 are located outside the periphery of the semiconductor element 50. The semiconductor device A1 is a semiconductor device in a package form called a Fan-Out type.

[0017] As shown in FIGS. 1 and 2, the semiconductor element 50 has an element main surface 501 and an element back surface 502 facing opposite sides in the thickness direction Z, and element side surfaces 503, 504, 505, 506 extending in the thickness direction Z. The element side surface 503 intersects the element main surface 501 and the element back surface 502. The element main surface 501 faces the substrate main surface 101 of the substrate 10. The element back surface 502 faces the same direction as the substrate main surface 101 of the substrate 10. The element side surfaces 503 and 504 face opposite sides in the first direction X. The element side surfaces 505 and 506 face opposite sides in the second direction Y.

[0018] The main surface 501 of the element is the surface on which the components for the functions of the semiconductor element 50 are formed. The semiconductor element 50 has element electrodes 55 for mounting on the side of the main surface 501. The element electrodes 55 are mounted on the substrate 10 by the first solder layer 42 of the joint portion 40 and the second solder layer 56 of the semiconductor element 50. That is, the semiconductor element 50 is mounted with the main surface 501 facing the substrate 10. Therefore, the main surface 501 can be said to be the element mounting surface for mounting the semiconductor element 50.

[0019] As shown in FIG. 4, the semiconductor element 50 includes an element substrate 51, electrode pads 52, an insulating film 53, a protective film 54, and element electrodes 55. The electrode pads 52 are made of, for example, Al (aluminum). The insulating film 53 covers the surface of the element substrate 51 and the peripheral portion of the electrode pads 52. The insulating film 53 is made of, for example, SiN. The protective film 54 covers the surface of the insulating film 53 and a part of the electrode pads 52, and a part of the surface of the electrode pads 52 is exposed as connection terminals. The protective film 54 is made of, for example, a polyimide resin.

[0020] The element electrodes 55 are connected to the connection terminals which are the exposed portions of the electrode pads 52. The element electrodes 55 include a metal layer 551, a conductive layer 552, and a barrier layer 553 as the second plating layer. The metal layer 551 is formed so as to cover the exposed portion of the electrode pads 52 and the end portions of the openings of the protective film 54 that expose the electrode pads 52. The metal layer 551 is made of, for example, titanium (Ti) / Cu and is formed as a seed layer for forming the conductive layer 32.

[0021] The conductive layer 552 is formed so as to cover the lower surface of the metal layer 551. The conductive layer 32 is made of, for example, CU, a Cu alloy. The barrier layer 553 is formed so as to cover the lower surface of the conductive layer 552. The barrier layer 553 is made of Ni, an alloy containing Ni, or a plurality of metal layers containing Ni. As the barrier layer 553, for example, Ni, Pd, Au, an alloy containing two or more of these metals, etc. can be used. A second solder layer 56 is formed on the lower surface 553d of the barrier layer 553. That is, the lower surface 553d of the barrier layer 553 is the lower surface of the element electrode 55.

[0022] As shown in FIG. 1, the substrate 10 mounts the semiconductor element 50 and is a support member serving as the foundation of the semiconductor device A1. As shown in FIG. 2, the shape of the substrate 10 viewed from the thickness direction Z is a rectangular shape in which the length of the side in the first direction X and the length of the side in the second direction Y are substantially equal. Note that the shape of the substrate 10 and the length of each side may be changed as appropriate.

[0023] The substrate 10 has a substrate main surface 101, a substrate back surface 102, and a plurality of substrate side surfaces 103. The substrate main surface 101 and the substrate back surface 102 face opposite sides in the thickness direction Z. The substrate main surface 101 is flat. The substrate back surface 102 is flat. Each substrate side surface 103 intersects the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 faces either the first direction X or the second direction Y. Each substrate side surface 103 is flat. In the first embodiment, each substrate side surface 103 intersects, and is orthogonal to, the substrate main surface 101 and the substrate back surface 102.

[0024] The substrate 10 is made of, for example, a material having electrical insulation properties. As this material, for example, a synthetic resin mainly composed of an epoxy resin or the like, ceramics, glass, or the like can be used. The substrate 10 has a plurality of through holes 105 penetrating the substrate 10 from the substrate main surface 101 to the substrate back surface 102 in the thickness direction Z. In the first embodiment, the substrate 10 has four through holes 105. Each through hole 105 is provided near each of the four corners of the substrate 10. The through hole 105 is, for example, rectangular when viewed from the thickness direction Z. Note that the shape of the through hole 105 may be circular or polygonal.

[0025] The wiring portion 20 includes a plurality of main surface wirings 21, a plurality of through wirings 22, and a plurality of columnar wirings 27. Each through-wiring 22 is disposed in each through-hole 105. Each through-wiring 22 has an upper surface 221, a lower surface 222, and a plurality of side surfaces 223. The upper surface 221 and the lower surface 222 face opposite sides in the thickness direction Z. Each side surface 223 intersects the upper surface 221 and the lower surface 222. In the first embodiment, the upper surface 221 of the through-wiring 22 is flush with the substrate main surface 101 of the substrate 10. Also, in the first embodiment, the lower surface 222 of the through-wiring 22 is flush with the back surface 102 of the substrate 10. This lower surface 222 is an exposed surface exposed from the back surface 102 of the substrate 10. Note that at least one of the upper surface 221 and the lower surface 222 of the through-wiring 22 may not be flush with the substrate main surface 101 and the back surface 102 of the substrate 10. Also, the side surface 223 of the through-wiring 22 is in contact with the inner wall surface 106 of the through-hole 105. The through-wiring 22 is made of a material having electrical conductivity. As the material of the through-wiring 22, for example, Cu, a Cu alloy, etc. can be used.

[0026] The main surface wiring 21 is formed on the substrate main surface 101 of the substrate 10. The main surface wiring 21 is made of a material having electrical conductivity and is electrically connected to the through-wiring 22. The main surface wiring 21 has an upper surface 211, a lower surface 212, and a side surface 213. The upper surface 211 of the main surface wiring 21 faces the same direction as the substrate main surface 101 of the substrate 10. The lower surface 212 of the main surface wiring 21 faces the same direction as the back surface 102 of the substrate 10 and faces the substrate main surface 101 of the substrate 10. The side surface 213 of the main surface wiring 21 faces the same direction as the substrate side surface 103 of the substrate 10. Also, the side surface 213 of the main surface wiring 21 intersects the upper surface 211 and the lower surface 212 of the main surface wiring 21.

[0027] The columnar wiring 27 extends in the thickness direction Z from the upper surface 211 of the main surface wiring 21. More specifically, the columnar wiring 27 extends from the upper surface 211 of the main surface wiring 21 in the thickness direction Z on the side opposite to the through-wiring 22. The shape of the columnar wiring 27 viewed from the thickness direction Z is, for example, rectangular. That is, the columnar wiring 27 of the present embodiment is a prism. Note that the shape of the columnar wiring 27 is not limited to this, and it may be a cylinder, a polygonal prism, etc.

[0028] The columnar wiring 27 has an upper surface 271, a lower surface 272, and a plurality of side surfaces 273. The upper surface 271 and the lower surface 272 face opposite sides in the thickness direction Z. Each side surface 273 is sandwiched between the upper surface 271 and the lower surface 272. In the present embodiment, the upper surface 271 of the columnar wiring 27 is, for example, flat. Note that the shape of the upper surface 271 can be arbitrarily changed. The lower surface 272 of the columnar wiring 27 is a surface that contacts the upper surface 211 of the main surface wiring 21. This lower surface 272 is, for example, flat. In the present embodiment, one of the plurality of side surfaces 273, the side surface 273a facing the first direction X, is an exposed side surface that is exposed from the resin side surface 603 of the sealing resin 60.

[0029] As shown in FIGS. 4 and 5, the main surface wiring 21 includes a metal layer 31 and a conductive layer 32. The metal layer 31 and the conductive layer 32 are laminated on the main surface 101 of the substrate 10 in this order. The metal layer 31 is composed of, for example, a Ti layer that contacts the main surface 101 of the substrate 10 and the upper surface 221 of the through wiring 22 shown in FIG. 1, and a Cu layer that contacts the Ti layer. The metal layer 31 is formed as a seed layer for forming the conductive layer 32. The metal layer 31 has an upper surface 311 and a lower surface 312 that face opposite sides in the thickness direction Z.

[0030] The conductive layer 32 is formed on the upper surface 311 of the metal layer 31. The conductive layer 32 is made of Cu or a Cu alloy. The conductive layer 32 has an upper surface 321 and a lower surface 322 that face opposite sides in the thickness direction Z. The thickness of the conductive layer 32 is, for example, 15 μm or more and 20 μm or less.

[0031] As shown in FIGS. 1, 2, and 4, the joint portion 40 is formed on the main surface wiring 21. The joint portion 40 is electrically connected to the wiring portion 20. The joint portion 40 joins the semiconductor element 50 to the wiring portion 20.

[0032] The joint portion 40 has a plating layer 41 as a first plating layer formed on the upper surface 321 of the conductive layer 32 of the main surface wiring 21, and a first solder layer 42 formed on the upper surface of the plating layer 41. The semiconductor element 50 has an element electrode 55 formed on the element main surface 501 and a second solder layer 56 formed on the lower surface of the element electrode 55. The joint portion 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed in the thickness direction Z. The first solder layer 42 and the second solder layer 56 are joined to each other by a reflow process in the step of mounting the semiconductor element 50 on the substrate 10, constituting an integral solder layer 45. That is, the semiconductor element 50 is connected to the main surface wiring 21 by the solder layer 45 and mounted on the substrate 10.

[0033] FIG. 5 shows the joint portion 40, the element electrode 55 of the semiconductor element 50, and the second solder layer 56 before the reflow process. The joint portion 40 includes a plating layer 41 and a first solder layer 42. The plating layer 41 and the first solder layer 42 are laminated in this order on the main surface wiring 21 of the wiring portion 20. The plating layer 41 is made of a conductive metal material. For example, the plating layer 41 is made of Ni (nickel). The first solder layer 42 is made of Sn (tin) or an alloy containing Sn. This alloy is, for example, an Sn-Ag (silver)-based alloy, an Sn-Sb (antimony)-based alloy, or the like.

[0034] As shown in FIGS. 3, 4, and 5, the plating layer 41 is formed on the upper surface 321 of the conductive layer 32 constituting the wiring portion 20. The plating layer 41 has an upper surface 411, a lower surface 412, and a side surface 413. The upper surface 411 faces the same direction as the upper surface 321 of the conductive layer 32. The lower surface 412 faces the upper surface 321 of the conductive layer 32. The lower surface 412 is in contact with the upper surface 321 of the conductive layer 32. The side surface 413 intersects the upper surface 411 and the lower surface 412. An oxide film may be formed on the side surface 413. The thickness T1 of the plating layer 41 is, for example, 3 μm or more and 5 μm or less.

[0035] As shown in FIG. 5, the first solder layer 42 has an upper surface 421, a lower surface 422, and side surfaces 423. The upper surface 421 and the lower surface 422 face opposite sides in the thickness direction Z. The side surfaces 423 intersect the upper surface 421 and the lower surface 422. The lower surface 422 of the first solder layer 42 is in contact with the upper surface 411 of the plating layer 41. When viewed from the thickness direction Z, the first solder layer 42 is formed to have the same size as the plating layer 41. The first solder layer 42 is formed with a thickness equal to or less than the thickness T1 of the plating layer 41. The thickness of the first solder layer 42 is preferably, for example, 1 μm or more and 5 μm or less. In the first solder layer 42, the aspect ratio in a cross section perpendicular to the substrate main surface 101 of the substrate 10, for example, a cross section along the first direction X, is preferably, for example, 40 or more and 80 or less. The aspect ratio of the first solder layer 42 is the ratio of the length and width of a rectangle including the first solder layer 42, and is the ratio (L1 / T2) of the length L1 of the first solder layer 42 in the first direction X to the thickness T2 of the first solder layer 42.

[0036] FIG. 4 shows the solder layer 45 after the reflow process. The solder layer 45 has an upper surface 451, a lower surface 452, and side surfaces 453. The upper surface 451 and the lower surface 452 face opposite sides in the thickness direction Z. The side surfaces 453 intersect the upper surface 451 and the lower surface 452. The upper surface 451 of the solder layer 45 is in contact with the lower surface of the element electrode 55, that is, the lower surface 553d of the barrier layer 553. The lower surface 452 of the solder layer 45 is in contact with the upper surface 411 of the plating layer 41. The solder layer 45 is formed in a substantially trapezoidal shape in a cross section perpendicular to the substrate main surface 101. More specifically, the side surfaces of the solder layer 45 extend from the outer peripheral end of the upper surface 411 of the plating layer 41 to the outer peripheral end of the element electrode 55, specifically, the outer peripheral end of the lower surface 553d of the barrier layer 553. Further, the side surfaces 453 of the solder layer 45 are inclined such that the widths in the first direction X and the second direction Y increase as they approach the substrate 10.

[0037] As shown in FIG. 1, the encapsulating resin 60 is in contact with the main surface 101 of the substrate 10 and is formed to cover the semiconductor element 50. More specifically, the encapsulating resin 60 covers the element main surface 501, the element back surface 502, and the element side surface 503 of the semiconductor element 50. Further, in the first embodiment, the encapsulating resin 60 covers the main surface wiring 21 and the joint portion 40.

[0038] The encapsulating resin 60 overlaps the substrate 10 when viewed from the thickness direction Z. The encapsulating resin 60 has a resin upper surface 601 facing the same direction as the main surface 101 of the substrate 10 and a resin side surface 603 facing the same direction as the side surface 103 of the substrate.

[0039] The encapsulating resin 60 has a first resin portion 60A which is the portion on the side of the substrate 10 in the thickness direction Z and a second resin portion 60B on the side of the resin upper surface 601. The first resin portion 60A has a first resin side surface 603a which constitutes a part of the resin side surface 603, and the second resin portion 60B has a second resin side surface 603b which constitutes a part of the resin side surface 603. When viewed from the thickness direction Z, the first resin portion 60A has the same size as the substrate 10. Also, when viewed from the thickness direction Z, the second resin portion 60B is formed larger than the first resin portion 60A. The second resin side surface 603b is located outside the first resin side surface 603a. Thus, the encapsulating resin 60 has a step 61 which is recessed inside the encapsulating resin 60 due to the difference in size between the first resin portion 60A and the second resin portion 60B. As shown in FIG. 2, the step 61 is provided over the entire circumferential direction of the encapsulating resin 60.

[0040] The encapsulating resin 60 is made of, for example, a resin having electrical insulation properties. As this resin, for example, a synthetic resin having an epoxy resin as the main component can be used. Also, the encapsulating resin 60 is colored, for example, black.

[0041] The external connection terminal 70 is formed to cover the wiring portion 20 exposed from the substrate 10 and the sealing resin 60. The external connection terminal 70 includes a first conductive film 71 covering the lower surface 222 of the through-wiring 22, the side surface 223 of the through-wiring 22, the side surface 213 of the main surface wiring 21, and the side surface 273a of the columnar wiring 27. The external connection terminal 70 having the first conductive film 71 and the second conductive film 72 serves as an external connection terminal of the semiconductor device A1. The external connection terminal 70 is composed of, for example, a plurality of metal layers laminated on each other. Examples of the metal layer include a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. Note that the material of the external connection terminal 70 is not limited, and for example, a Ni layer and an Au layer may be laminated, or it may be Sn.

[0042] In this semiconductor device A1, when mounted on a mounting substrate, solder for connecting the external connection terminal 70 to the connection pad of the mounting substrate is interposed between the first conductive film 71 and the connection pad and also adheres to the second conductive film 72. That is, the solder that has become in a liquid state by the reflow process climbs up the second conductive film 72 to form a solder fillet between the second conductive film 72 and the connection pad. Note that in the semiconductor device A1 in this way, the solder fillet is more easily formed. This solder fillet increases the bonding area of the solder and can further enhance the connection strength. Also, the soldering state of the semiconductor device A1 can be confirmed from the outside by the solder fillet.

[0043] FIG. 3 shows a part of the semiconductor element 50 and the main surface wiring 21 in the semiconductor device A1 of the present embodiment. In FIG. 3, the semiconductor element 50 and the element electrode 55 are indicated by a one-dot chain line. The main surface wiring 21 is connected to the element electrode 55 of the semiconductor element 50 and extends outward from the element electrode 55 of the semiconductor element 50.

[0044] The joint portion 40 composed of the plating layer 41 and the first solder layer 42 has end sides 40a and 40c extending in the first direction X and end sides 40b and 40d extending in the second direction Y. The element electrode 55 is formed in a rectangular shape when viewed from the thickness direction Z and has side surfaces 55a and 55c along the first direction X and side surfaces 55b and 55d along the second direction Y.

[0045] The distance L2a from the side surface 55a of the element electrode 55 to the end side 40a of the joint portion 40 is, for example, 4 μm or more and 10 μm or less. The distance L2b from the side surface 55b of the element electrode 55 to the end side 40b of the joint portion 40 is, for example, 4 μm or more and 10 μm or less. The distance L2c from the side surface 55c of the element electrode 55 to the end side 40c of the joint portion 40 is, for example, 4 μm or more and 10 μm or less. The distance L2d from the side surface 55d of the element electrode 55 to the end side 40d of the joint portion 40 is, for example, 4 μm or more and 10 μm or less.

[0046] In the main surface wiring 21, with respect to the inner end side 21a of the semiconductor element 50 and the side sides 21b and 21c that are on both sides of the end side 21a and intersect the end side 21a, each end side 40b to 40d of the joint portion 40, that is, the ends of the plating layer 41 and the first solder layer 42, are located inside the main surface wiring 21. The distance L3a between the end side 21a and the joint portion 40 is, for example, 0.5 μm or more and 1.0 μm or less. The distance L3b between the side side 21b and the joint portion 40 is, for example, 0.5 μm or more and 1.0 μm or less. Also, the distance L3c between the side side 21c and the joint portion 40 is, for example, 0.5 μm or more and 1.0 μm or less.

[0047] (Manufacturing process) Next, an example of the manufacturing process of the semiconductor device A1 described above will be explained. First, a support substrate is prepared. The support substrate is made of, for example, a single crystal material of Si. Note that, as the support substrate, a substrate made of a synthetic resin material such as an epoxy resin may be used. A terminal pillar that will become the through wiring 22 is formed on the upper surface of the support substrate. The terminal pillar is made of, for example, Cu or a Cu alloy. The terminal pillar is composed of, for example, a seed layer formed on the upper surface of the support substrate and a plating metal formed on the upper surface of the seed layer. Note that the terminal pillar may be formed of a columnar material of Cu.

[0048] Next, a base material that contacts the upper surface of the support substrate and covers the terminal pillars is formed. The base material is formed so as to cover the upper surface of the terminal pillars. As the material of this base material, the material constituting the substrate 10 shown in FIG. 1 can be used. In the present embodiment, as the material of the base material, a synthetic resin mainly composed of an epoxy resin or the like can be used.

[0049] Next, a part of the base material and the terminal pillars is ground to form a through-wiring 22 exposed on the upper surface of the base material and an upper surface 221 of the through-wiring 22. The base material becomes the substrate 10 shown in FIG. 1. In grinding the base material, the thickness of the base material is made the same as that of the substrate 10.

[0050] Next, a main surface wiring 21 is formed on the upper surface of the base material and the upper surface 221 of the through-wiring 22. The main surface wiring 21 includes a metal layer 31 and a conductive layer 32. First, the metal layer 31 is formed by, for example, a sputtering method. For example, the metal layer 31 including a Ti layer and a Cu layer forms a Ti layer on the upper surface of the base material and the upper surface 221 of the through-wiring 22, and forms a Cu layer in contact with the Ti layer. Next, a plating metal is deposited on the surface of the metal layer 31 by, for example, an electrolytic plating method using the metal layer 31 as a conductive path to form the conductive layer 32.

[0051] Next, a joint portion 40 is formed on the main surface wiring 21. The joint portion 40 includes a plating layer 41 and a first solder layer 42. First, the plating layer 41 is formed on the main surface wiring 21 by, for example, an electrolytic plating method. Next, the first solder layer 42 is formed on the plating layer 41 by, for example, an electrolytic plating method.

[0052] Also, a columnar wiring 27 is formed on the main surface wiring 21. The columnar wiring 27 includes, for example, a seed layer and a plating layer. The seed layer is composed of, for example, a first layer whose main component is Ti and a second layer whose main component is Cu. The plating layer has, for example, a main component of Cu. First, the seed layer is formed on the main surface wiring 21 by, for example, a sputtering method, and then the columnar wiring 27 is formed by forming a plating layer by, for example, an electrolytic plating method using the seed layer as a conductive path.

[0053] Next, the semiconductor element 50 is mounted. The mounting of the semiconductor element 50 is performed by flip chip bonding (FCB). For example, using a flip chip bonder, flux is pin-transferred and applied to the second solder layer 56 of the semiconductor element 50, and flip chip mounting is performed. As a result, the semiconductor element 50 is temporarily attached to the joint portion 40. Thereafter, after the first solder layer 42 of the joint portion 40 and the second solder layer 56 of the semiconductor element 50 are brought into a liquid phase state by reflow, the first solder layer 42 and the second solder layer 56 are solidified by cooling, thereby forming the solder layer 45. The semiconductor element 50 is mounted on the substrate 10 by this solder layer 45.

[0054] Next, a resin layer that covers the upper surface of the base material, the wiring portion 20, and the semiconductor element 50 is formed. The resin layer is a member that becomes the sealing resin 60 shown in FIG. 1. The resin layer is, for example, a synthetic resin mainly composed of an epoxy resin. For example, the resin layer is formed by transfer molding.

[0055] Next, the support substrate is removed, for example, by grinding. Note that a method of forming a release film between the support substrate and the base material in advance and removing the support substrate by a release method can also be used. Next, a groove portion is formed from the side of the base material to the middle of the resin layer by a dicing blade or the like, and the side surface 223 of the through-wiring 22, the side surface 213 of the main surface wiring 21, and the side surface 273a of the columnar wiring 27 are exposed in the groove portion.

[0056] Next, external connection terminals 70 are formed on the surfaces of the through-wiring 22, the main surface wiring 21, and the columnar wiring 27 that are exposed from the base material and the resin layer. The external connection terminals 70 are made of, for example, a plated metal. For example, the external connection terminals 70 are formed by electroless plating to deposit a plated metal, for example, Ni, Pd, and Au, in this order. Note that the structure and formation method of the external connection terminals 70 are not limited.

[0057] Next, a dicing tape is attached to the resin layer, and the base material and the resin layer are cut to divide them into individual pieces with one semiconductor element 50 as a unit. In the division, for example, a dicing blade is used to cut from the side of the base material to the dicing tape to cut the base material and the resin layer. The individual piece is a semiconductor device A1 including the substrate 10 and the sealing resin 60.

[0058] (Function) Next, the function of the semiconductor device A1 described above will be explained. The semiconductor device A1 has a joint portion 40 on the upper surface 211 of the main surface wiring 21. The joint portion 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The joint portion 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed in the thickness direction Z. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 by a reflow process to form a solder layer 45. In this reflow process, since the melted second solder layer 56 fuses with the first solder layer 42, it is difficult to flow out to the outside of the plating layer 41. Therefore, the outflow of the solder in the reflow process when mounting the semiconductor element 50 can be suppressed.

[0059] The joint portion 40 has a plating layer 41 on the upper surface of the main surface wiring 21 and a first solder layer 42 on the plating layer 41. The main surface wiring 21 is made of Cu or a Cu alloy, and the first solder layer 42 is made of SnAg. Since the plating layer 41 is a barrier metal, it prevents the alloying of Cu in the main surface wiring 21 with Sn in the first solder layer 42 and the second solder layer 56. Thereby, the generation of voids (cuckend voids) between SnAg and Cu can be suppressed.

[0060] The joint portion 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 to form a solder layer 45. The upper surface 411 of the plating layer 41 may have irregularities in the formation of the main surface wiring 21 and the plating layer 41. When the second solder layer 56 is directly joined to the plating layer 41, voids (holes) may be generated in the solder layer due to the roughness of the upper surface 211 of the main surface wiring 21 and the upper surface 411 of the plating layer 41. On the other hand, the first solder layer 42 formed on the plating layer 41 is melted in the reflow process before mounting the semiconductor element 50, thereby smoothing the rough surface. By this smoothing, the generation of voids when the first solder layer 42 and the second solder layer 56 are joined can be suppressed. The first solder layer 42 has a thickness T2 smaller than the size in the direction parallel to the upper surface 411 of the plating layer 41 on which the first solder layer 42 is formed. That is, since the aspect ratio of the first solder layer 42 is small, the solder flow in the reflow process before mounting the semiconductor element 50 can be suppressed.

[0061] As described above, according to the present embodiment, the following effects can be obtained. (1-1) The semiconductor device A1 has a joint portion 40 on the upper surface 211 of the main surface wiring 21. The joint portion 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The joint portion 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 by the reflow process to form a solder layer 45. In this reflow process, the melted second solder layer 56 fuses with the first solder layer 42, so it is difficult to flow out to the outside of the plating layer 41. Therefore, the outflow of solder in the reflow process when mounting the semiconductor element 50 can be suppressed.

[0062] (1-2) The thickness T2 of the first solder layer 42 is small with respect to the size in the direction parallel to the upper surface 411 of the plating layer 41 on which the first solder layer 42 is formed. That is, since the aspect ratio of the first solder layer 42 is small, the solder flow in the reflow process before mounting the semiconductor element 50 can be suppressed.

[0063] (1-4) The joint 40 has the plating layer 41 on the upper surface of the main surface wiring 21 and the first solder layer 42 on the plating layer 41. The main surface wiring 21 is made of Cu or a Cu alloy, and the first solder layer 42 is made of SnAg. Since the plating layer 41 is a barrier metal, alloying between the Cu of the main surface wiring 21 and the Sn of the first solder layer 42 and the second solder layer 56 can be prevented. Thereby, generation of voids (cavity voids) between SnAg and Cu can be suppressed.

[0064] (1-5) The joint 40 has the plating layer 41 and the first solder layer 42 on the plating layer 41. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 to form a solder layer 45. The upper surface 411 of the plating layer 41 may be uneven in the formation of the main surface wiring 21 and the plating layer 41. When the second solder layer 56 is directly joined to the plating layer 41, voids (holes) may be generated in the solder layer due to the roughness of the upper surface 211 of the main surface wiring 21 and the upper surface 411 of the plating layer 41. On the other hand, the first solder layer 42 formed on the plating layer 41 is melted in the reflow process before mounting the semiconductor element 50, thereby smoothing the rough surface. By this smoothing, generation of voids when the first solder layer 42 and the second solder layer 56 are joined can be suppressed.

[0065] (1-6) In the semiconductor device A1, when mounted on a mounting substrate, solder that connects the external connection terminal 70 to the connection pad of the mounting substrate is interposed between the first conductive film 71 and the connection pad and also adheres to the second conductive film 72. That is, the solder that has become in a liquid state by the reflow process climbs up the second conductive film 72 and forms a solder fillet between the second conductive film 72 and the connection pad. This solder fillet increases the bonding area of the solder and can enhance the connection strength. Also, the state of soldering of the semiconductor device A1 can be confirmed from the outside by the solder fillet.

[0066] (Second Embodiment) Hereinafter, based on FIGS. 6 to 8, the semiconductor device A2 of the second embodiment will be described. In this second embodiment, the same members as those in the first embodiment will be described using the same reference numerals.

[0067] As shown in FIGS. 6 and 7, the semiconductor device A2 includes a substrate 10, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring portion 20 includes a main surface wiring 21 and a through wiring 22.

[0068] FIG. 6 is a cross-sectional view of the semiconductor device A2 of the second embodiment. FIG. 7 is a schematic plan view of the semiconductor device A2. For convenience of understanding, in FIG. 7, the semiconductor element 50 is shown by a two-dot chain line except for the sealing resin 60. FIG. 8 is a partially enlarged plan view of the semiconductor device A2 and shows a part of the wiring portion 20.

[0069] The semiconductor device A2 shown in these figures is a device that is surface-mounted on the circuit board of various electronic devices. Here, for convenience of explanation, the thickness direction of the substrate 10 is referred to as the thickness direction Z. Also, the direction (the left-right direction in the plan view) along one side of the semiconductor device A2 orthogonal to the thickness direction Z is referred to as the first direction X. Also, the direction (the up-down direction in the plan view) orthogonal to both the thickness direction Z and the first direction X of the substrate 10 is referred to as the second direction Y.

[0070] As shown in FIG. 7, the semiconductor device A2 is rectangular in the thickness direction Z view. As shown in FIG. 7, the semiconductor element 50 is rectangular when viewed in the thickness direction Z. The semiconductor element 50 is rectangular and longer in the second direction Y than in the first direction X.

[0071] The semiconductor element 50 is an integrated circuit (IC) such as an LSI (Large Scale Integration), for example. Further, the semiconductor element 50 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the element main surface 501 is a surface on which components for the functions of the semiconductor element 50 are formed. Note that the semiconductor element 50 is not limited to one in which a plurality of components are formed, and may be an element in which a single component is formed, such as a chip capacitor or a chip inductor, or an element in which components are formed on a substrate other than a semiconductor. In the present embodiment, the semiconductor element 50 is an LSI.

[0072] As shown in FIGS. 6 and 7, the semiconductor device A2 has a plurality of external connection terminals 70. The external connection terminals 70 are located outside the periphery of the semiconductor element 50. The semiconductor device A2 is a semiconductor device in a package form called the Fan-Out type.

[0073] As shown in FIGS. 6 and 7, the semiconductor element 50 has an element main surface 501 and an element back surface 502 facing opposite sides in the thickness direction Z, and an element side surface 503 extending in the thickness direction Z. The element side surface 503 intersects the element main surface 501 and the element back surface 502. The element main surface 501 faces the substrate main surface 101 of the substrate 10. The element back surface 502 faces the same direction as the substrate main surface 101 of the substrate 10.

[0074] The main element surface 501 is the surface on which the components for the functions of the semiconductor element 50 are formed. The semiconductor element 50 has element electrodes 55 for mounting on the side of the main element surface 501. The element electrodes 55 are mounted on the substrate 10 by the first solder layer 42 of the joint portion 40 and the second solder layer 56 of the semiconductor element 50. That is, the semiconductor element 50 is mounted with the main element surface 501 facing the substrate 10. Therefore, the main element surface 501 can be said to be the element mounting surface for mounting the semiconductor element 50.

[0075] As shown in FIG. 6, the substrate 10 is a support member that mounts the semiconductor element 50 and serves as the basis of the semiconductor device A2. The shape of the substrate 10 viewed from the thickness direction Z is, as shown in FIG. 7, a rectangular shape in which the length of the side in the first direction X and the length of the side in the second direction Y are substantially equal. Note that the shape of the substrate 10 and the length of each side may be appropriately changed.

[0076] The substrate 10 has a substrate main surface 101, a substrate back surface 102, and a plurality of substrate side surfaces 103. The substrate main surface 101 and the substrate back surface 102 face opposite sides in the thickness direction Z. The substrate main surface 101 is flat. The substrate back surface 102 is flat. Each substrate side surface 103 is sandwiched between the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 faces either the first direction X or the second direction Y. Each substrate side surface 103 is flat. Each substrate side surface 103 intersects, and in this embodiment is orthogonal to, the substrate main surface 101 and the substrate back surface 102.

[0077] The substrate 10 is made of, for example, a material having electrical insulation properties. As this material, for example, a synthetic resin with an epoxy resin or the like as the main component, ceramics, glass, etc. can be used. The substrate 10 has a plurality of through holes 105 that penetrate the substrate 10 from the substrate main surface 101 to the substrate back surface 102 in the thickness direction Z. In this embodiment, the substrate 10 has four through holes 105. Each through hole 105 is provided near each of the four corners of the substrate 10. The through hole 105 is, for example, rectangular when viewed from the thickness direction Z. Note that the shape of the through hole 105 may be circular or polygonal.

[0078] The wiring portion 20 includes a plurality of main surface wirings 21 and a plurality of through wirings 22. Each through wiring 22 is disposed in each through hole 105. Each through wiring 22 has an upper surface 221, a lower surface 222, and a plurality of side surfaces 223. The upper surface 221 and the lower surface 222 face opposite sides in the thickness direction Z. Each side surface 223 is sandwiched between the upper surface 221 and the lower surface 222. In the present embodiment, the upper surface 221 of the through wiring 22 is flush with the substrate main surface 101 of the substrate 10. Also, in the present embodiment, the lower surface 222 of the through wiring 22 is flush with the back surface 102 of the substrate 10. This lower surface 222 is an exposed surface exposed from the back surface 102 of the substrate 10. Note that at least one of the upper surface 221 and the lower surface 222 of the through wiring 22 may not be flush with the substrate main surface 101 and the back surface 102 of the substrate 10. Also, the side surface 223 of the through wiring 22 is in contact with the inner wall surface 106 of the through hole 105. The through wiring 22 is made of a material having electrical conductivity. As the material of the through wiring 22, for example, Cu, a Cu alloy, etc. can be used.

[0079] The external connection terminal 70 is formed on the back surface 102 of the substrate 10. The external connection terminal 70 is formed so as to cover the lower surface 222 of the through wiring 22. Also, the external connection terminal 70 extends from the through wiring 22 along the back surface 102 of the substrate and is formed so as to cover the back surface 102 of the substrate around the through hole 105. The external connection terminal 70 is composed of, for example, a plurality of metal layers laminated on each other. Examples of the metal layer include a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. Note that the material of the external connection terminal 70 is not limited, but for example, a Ni layer and an Au layer may be laminated and configured, or it may be Sn.

[0080] The main surface wiring 21 is formed on the main surface 101 of the substrate 10. The main surface wiring 21 is made of a material having electrical conductivity and is electrically connected to the through wiring 22. The main surface wiring 21 has an upper surface 211, a lower surface 212, and a side surface 213. The upper surface 211 of the main surface wiring 21 faces the same direction as the main surface 101 of the substrate 10. The lower surface 212 of the main surface wiring 21 faces the same direction as the back surface 102 of the substrate 10 and faces the main surface 101 of the substrate 10. The side surface 213 of the main surface wiring 21 faces the same direction as the side surface 103 of the substrate 10. Also, the side surface 213 of the main surface wiring 21 intersects the upper surface 211 and the lower surface 212 of the main surface wiring 21.

[0081] As shown in FIG. 7, the main surface wiring 21 has individual first wiring portions 23 each connected to the element electrode 55 of the semiconductor element 50 and a planar second wiring portion 24 connected to a plurality of element electrodes 55.

[0082] The first wiring portion 23 and the second wiring portion 24 are formed so as to extend from the portion overlapping the element electrode 55 of the semiconductor element 50 to the portion overlapping the corresponding through wiring 22 when viewed from the thickness direction Z. That is, the first wiring portion 23 and the second wiring portion 24 extend from the semiconductor element 50 toward the outside of the semiconductor element 50.

[0083] As shown in FIGS. 6 and 7, the bonding portion 40 is formed on the main surface wiring 21. The bonding portion 40 is electrically connected to the wiring portion 20. The bonding portion 40 bonds the semiconductor element 50 to the wiring portion 20.

[0084] The joint portion 40 has a plating layer 41 as a first plating layer formed on the upper surface 321 of the conductive layer 32 of the main surface wiring 21, and a first solder layer 42 formed on the upper surface of the plating layer 41. The semiconductor element 50 has an element electrode 55 formed on the element main surface 501 and a second solder layer 56 formed on the lower surface of the element electrode 55. The joint portion 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 and the second solder layer 56 are joined to each other by a reflow process in the step of mounting the semiconductor element 50 on the substrate 10, constituting an integrated solder layer 45. That is, the semiconductor element 50 is connected to the main surface wiring 21 by the solder layer 45 and mounted on the substrate 10.

[0085] As shown in FIG. 8, the plating layer 41 is formed on the upper surface 321 of the conductive layer 32 constituting the wiring portion 20. The plating layer 41 has an upper surface 411, a lower surface 412, and a side surface 413. The upper surface 411 faces the same direction as the upper surface 321 of the conductive layer 32. The lower surface 412 faces the upper surface 321 of the conductive layer 32. The lower surface 412 is in contact with the upper surface 321 of the conductive layer 32. The side surface 413 intersects the upper surface 411 and the lower surface 412. An oxide film may be formed on the side surface 413. The thickness T1 of the plating layer 41 is, for example, 3 μm or more and 5 μm or less.

[0086] As shown in FIG. 6, the sealing resin 60 is in contact with the substrate main surface 101 of the substrate 10 and is formed so as to cover the semiconductor element 50. More specifically, the sealing resin 60 covers the element main surface 501, the element back surface 502, and the element side surface 503 of the semiconductor element 50. Further, in the present embodiment, the sealing resin 60 covers the main surface wiring 21 and the joint portion 40.

[0087] The sealing resin 60 overlaps the substrate 10 when viewed from the thickness direction Z. The sealing resin 60 has a resin upper surface 601 facing the same direction as the substrate main surface 101 of the substrate 10 and a resin side surface 603 facing the same direction as the substrate side surface 103.

[0088] The encapsulating resin 60 is made of, for example, a resin having electrical insulation properties. As this resin, for example, a synthetic resin with an epoxy resin as the main component can be used. Further, the encapsulating resin 60 is colored, for example, black.

[0089] FIG. 8 shows a part of the semiconductor element 50 and the main surface wiring 21 in the semiconductor device A2 of this embodiment. In FIG. 8, the semiconductor element 50 and the element electrode 55 are shown by dashed-dotted lines. The main surface wiring 21 is connected to the element electrode 55 of the semiconductor element 50 and extends outward from the element electrode 55 of the semiconductor element 50.

[0090] The joint portion 40 composed of the plating layer 41 and the first solder layer 42 has end sides 40a, 40c extending in the first direction X and end sides 40b, 40d extending in the second direction Y. The element electrode 55 is formed in a rectangular shape when viewed from the thickness direction Z and has side surfaces 55a, 55c along the first direction X and side surfaces 55b, 55d along the second direction Y.

[0091] The distance L2a from the side surface 55a of the element electrode 55 to the end side 40a of the joint portion 40 is, for example, 4 μm or more and 10 μm or less. The distance L2b from the side surface 55b of the element electrode 55 to the end side 40b of the joint portion 40 is, for example, 4 μm or more and 10 μm or less. The distance L2c from the side surface 55c of the element electrode 55 to the end side 40c of the joint portion 40 is, for example, 4 μm or more and 10 μm or less. The distance L2d from the side surface 55d of the element electrode 55 to the end side 40d of the joint portion 40 is, for example, 4 μm or more and 10 μm or less.

[0092] In the first wiring portion 23, with respect to the inner end side 23a of the semiconductor element 50 and the side sides 23b, 23c on both sides of the end side 23a and intersecting the end side 23a, each end side 40b to 40d of the joint portion 40, that is, the ends of the plating layer 41 and the first solder layer 42, are located inside the main surface wiring 21. The distance L3a between the end side 23a and the joint portion 40 is, for example, 0.5 μm or more and 1.0 μm or less. The distance L3b between the side side 23b and the joint portion 40 is, for example, 0.5 μm or more and 1.0 μm or less. Also, the distance L3c between the side side 23c and the joint portion 40 is, for example, 0.5 μm or more and 1.0 μm or less.

[0093] In the second wiring portion 24, a joint portion 40 is provided for each element electrode 55. That is, the plurality of joint portions 40 formed on the upper surface of one second wiring portion 24 are formed separately from each other. In the second wiring portion 24 provided with the plurality of joint portions 40, the positional relationship between each joint portion 40 and the element electrode 55 connected to each joint portion 40 is the same as the positional relationship in the first wiring portion 23 described above. Also, the positional relationship between the end side 24a and the side sides 24b, 24c of the second wiring portion 24 and the joint portion 40 is the same as the positional relationship in the first wiring portion 23 described above. In the present embodiment, a plurality of joint portions 40 are provided along the end side 24a of the second wiring portion 24, but the position where the joint portion 40 is provided can be appropriately changed according to the semiconductor element to be mounted.

[0094] (Manufacturing process) Next, an example of the manufacturing process of the semiconductor device A2 described above will be described. First, a support substrate is prepared. The support substrate is made of, for example, a single crystal material of Si. Note that, as the support substrate, a substrate made of a synthetic resin material such as an epoxy resin may be used. A terminal pillar that will become the through-wiring 22 is formed on the upper surface of the support substrate. The terminal pillar is made of, for example, Cu or a Cu alloy. The terminal pillar is made of, for example, a seed layer formed on the upper surface of the support substrate and a plating metal formed on the upper surface of the seed layer. Note that the terminal pillar may be formed of a columnar material of Cu.

[0095] Next, a base material that contacts the upper surface of the support substrate and covers the terminal pillar is formed. The base material is formed so as to cover the upper surface of the terminal pillar. As the material of this base material, the material constituting the substrate 10 shown in FIG. 6 can be used. In the present embodiment, as the material of the base material, a synthetic resin mainly composed of an epoxy resin or the like can be used.

[0096] Next, a part of the base material and the terminal pillar is ground to form the through-wiring 22 exposed on the upper surface of the base material and the upper surface 221 of the through-wiring 22. The base material becomes the substrate 10 shown in FIG. 6. In grinding the base material, the base material is made to have the same thickness as the substrate 10.

[0097] Next, the main surface wiring 21 is formed on the upper surface of the base material and the upper surface 221 of the through-wiring 22. The main surface wiring 21 includes a metal layer 31 and a conductive layer 32. First, for example, the metal layer 31 is formed by a sputtering method. For example, the metal layer 31 including a Ti layer and a Cu layer forms a Ti layer on the upper surface of the base material and the upper surface 221 of the through-wiring 22, and forms a Cu layer in contact with the Ti layer. Next, for example, by an electrolytic plating method using the metal layer 31 as a conductive path, a plating metal is deposited on the surface of the metal layer 31 to form the conductive layer 32.

[0098] Next, the joint portion 40 is formed on the main surface wiring 21. The joint portion 40 includes a plating layer 41 and a first solder layer 42. First, the plating layer 41 is formed on the main surface wiring 21, for example, by an electrolytic plating method. Next, the first solder layer 42 is formed on the plating layer 41, for example, by an electrolytic plating method.

[0099] Next, the semiconductor element 50 is mounted. The mounting of the semiconductor element 50 is performed by flip chip bonding (FCB). For example, using a flip chip bonder, flux is pin-transferred and applied to the second solder layer 56 of the semiconductor element 50, and flip chip mounting is performed. As a result, the semiconductor element 50 is temporarily attached to the joint portion 40. Then, after the first solder layer 42 of the joint portion 40 and the second solder layer 56 of the semiconductor element 50 are brought into a liquid phase state by reflow, the first solder layer 42 and the second solder layer 56 are solidified by cooling to form the solder layer 45. The semiconductor element 50 is mounted on the substrate 10 by this solder layer 45.

[0100] Next, a resin layer covering the upper surface of the base material, the wiring portion 20, and the semiconductor element 50 is formed. The resin layer is a member that becomes the sealing resin 60 shown in FIG. 6. The resin layer is a synthetic resin mainly made of, for example, an epoxy resin. For example, the resin layer is formed by transfer molding.

[0101] Next, the support substrate is removed, for example, by grinding. Note that a release film may be formed in advance between the support substrate and the base material, and a method of removing the support substrate by a release method may also be used. Next, an external connection terminal 70 is formed on the surface of the through-wiring 22 exposed from the base material (the lower surface 222 shown in FIG. 6). The external connection terminal 70 is made of, for example, a plating metal. For example, the external connection terminal 70 is formed by depositing a plating metal, such as Ni, Pd, and Au, in this order by electroless plating. Note that the structure and formation method of the external connection terminal 70 are not limited.

[0102] Next, a dicing tape is attached to the resin layer, and the base material and the resin layer are cut to divide them into individual pieces each having a semiconductor element 50 as one unit. In the division, for example, a dicing blade is used to cut from the side of the base material to the dicing tape to cut the base material and the resin layer. The individual piece is a semiconductor device A2 including the substrate 10 and the sealing resin 60.

[0103] (Operation) Next, the operation of the semiconductor device A2 described above will be described. The semiconductor device A2 has a joint portion 40 on the upper surface 211 of the main surface wiring 21. The joint portion 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The joint portion 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed in the thickness direction Z. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 by a reflow process to form a solder layer 45. In this reflow process, since the molten second solder layer 56 fuses with the first solder layer 42, it is difficult to flow out outside the plating layer 41. Therefore, it is possible to suppress the outflow of solder in the reflow process when mounting the semiconductor element 50.

[0104] As shown in FIG. 8, a plurality of joints 40 formed on the upper surface 211 of one main surface wiring 21 (second wiring portion 24) are formed apart from each other. Each joint 40 is connected to an element electrode 55 of the semiconductor element 50. And each joint 40 suppresses the outflow of solder respectively. For this reason, in a plurality of element electrodes 55 connected to one main surface wiring 21 (second wiring portion 24), since a solder layer 45 is formed between each element electrode 55 and the joint 40, the amount of solder is ensured for each element electrode 55. Thereby, the electrical connection between each element electrode 55 and one main surface wiring 21 (second wiring portion 24) can be ensured.

[0105] For example, when one joint 40 is provided for a plurality of element electrodes 55, solder may concentrate in the vicinity of a predetermined element electrode 55, and there is a risk that the solder may be insufficient in other element electrodes 55. When the solder is thus insufficient, there is a risk that the element electrode 55 may be unconnected to the main surface wiring 21. On the other hand, in the present embodiment, each element electrode 55 can be connected to one main surface wiring 21.

[0106] The joint 40 has a plating layer 41 on the upper surface of the main surface wiring 21 and a first solder layer 42 on the plating layer 41. The main surface wiring 21 is made of Cu or a Cu alloy, and the first solder layer 42 is made of SnAg. Since the plating layer 41 is a barrier metal, alloying between Cu of the main surface wiring 21, Sn of the first solder layer 42 and the second solder layer 56 is prevented. Thereby, generation of voids (carkendal voids) between SnAg and Cu can be suppressed.

[0107] The joint portion 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 to form a solder layer 45. The upper surface 411 of the plating layer 41 may have irregularities in the formation of the main surface wiring 21 and the plating layer 41. When the second solder layer 56 is directly joined to the plating layer 41, voids (holes) may be generated in the solder layer due to the roughness of the upper surface 211 of the main surface wiring 21 and the upper surface 411 of the plating layer 41. On the other hand, the first solder layer 42 formed on the plating layer 41 is melted in the reflow process before mounting the semiconductor element 50, thereby smoothing the rough surface. By this smoothing, the generation of voids when the first solder layer 42 and the second solder layer 56 are joined can be suppressed. The first solder layer 42 has a thickness T2 smaller than the size in the direction parallel to the upper surface 411 of the plating layer 41 on which the first solder layer 42 is formed. That is, since the aspect ratio of the first solder layer 42 is small, the solder flow in the reflow process before mounting the semiconductor element 50 can be suppressed.

[0108] As described above, according to the second embodiment, the following effects can be obtained. (2-1) The same effects as (1-1) to (1-5) of the first embodiment can be obtained.

[0109] (2-2) The plurality of joint portions 40 formed on the upper surface 211 of the second wiring portion 24 that becomes one main surface wiring 21 are formed apart from each other. Each joint portion 40 is connected to the element electrode 55 of the semiconductor element 50, respectively. And each joint portion 40 suppresses the outflow of solder, respectively. For this reason, in the plurality of element electrodes 55 connected to the second wiring portion 24 that becomes one main surface wiring 21, since the solder layer 45 is formed between each element electrode 55 and the joint portion 40, the amount of solder is ensured for each element electrode 55. Thereby, the electrical connection between each element electrode 55 and the second wiring portion 24 that becomes one main surface wiring 21 can be ensured.

[0110] (Modification example) Each of the above embodiments can be implemented with the following modifications. · The size of the joint portion 40 may be appropriately changed.

[0111] FIG. 9 shows the joint portion 40 of the modified example. For example, in the first wiring portion 23, it is preferable to increase the distance L2a between the element electrode 55 on the outer side of the semiconductor element 50 and the end side 40a of the joint portion 40 with respect to the distance L2c between the element electrode 55 inside the semiconductor element 50 and the end side 40c of the joint portion 40. In the case of the second wiring portion 24, it is preferable to increase the distance L2d from the element electrode 55 to the end of the joint portion 40 with respect to the distance L2c from the element electrode 55 inside the semiconductor element 50 to the end of the joint portion 40 on the element side surface 504 side of the semiconductor element 50. By doing so, the outflow of solder to the inside of the semiconductor element 50 can be further suppressed.

[0112] · The configuration of the semiconductor device may be appropriately changed. The semiconductor device A11 shown in FIG. 10 includes a substrate 10, a wiring portion 20, a joint portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring portion 20 includes a main surface wiring 21 formed on the main surface 101 of the substrate 10 and a through wiring 22 penetrating the substrate 10.

[0113] The through wiring 22 extends to the substrate side surface 103 of the substrate 10. That is, the side surface 223 of the through wiring 22 is flush with the substrate side surface 103 of the substrate 10. Also, the external connection terminal 70 extends to the substrate side surface 103 of the substrate 10. Therefore, the lower surface 222 of the through wiring 22 is exposed on the back surface 102 of the substrate 10, and the side surface 223 of the through wiring 22 is exposed on the substrate side surface 103 of the substrate 10. The external connection terminal 70 is formed so as to cover the lower surface 222 of the through wiring 22. Even in such a semiconductor device A11, the same effects as those of the above-described embodiment can be obtained.

[0114] The semiconductor device A12 shown in FIG. 11 includes a substrate 10, a wiring portion 20, a joint portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring portion 20 includes a main surface wiring 21 formed on the main surface 101 of the substrate 10 and a through wiring 22 penetrating the substrate 10.

[0115] The through-wiring 22 extends to the substrate side surface 103 of the substrate 10. That is, the side surface 223 of the through-wiring 22 is flush with the substrate side surface 103 of the substrate 10. Therefore, the lower surface 222 of the through-wiring 22 is exposed on the back surface 102 of the substrate 10, and the side surface 223 of the through-wiring 22 is exposed on the substrate side surface 103 of the substrate 10.

[0116] The external connection terminal 70 of this semiconductor device A12 is formed so as to cover the through-wiring 22 exposed from the substrate 10. The external connection terminal 70 has a first conductive film 71 that covers the lower surface 222 of the through-wiring 22 and a second conductive film 72 that covers the side surface 223 of the through-wiring 22. The external connection terminal 70 having the first conductive film 71 and the second conductive film 72 serves as the external connection terminal of the semiconductor device A12 in the same manner as the external connection terminal 70 of the above embodiment. The external connection terminal 70 is composed of, for example, a plurality of metal layers laminated on each other. Examples of the metal layer include a Ni layer, a Pd layer, and an Au layer. Note that the material of the external connection terminal 70 is not limited, but for example, a Ni layer and an Au layer may be laminated, or it may be Sn.

[0117] In this semiconductor device A12, when mounted on a mounting substrate, the solder connecting the external connection terminal 70 to the connection pad of the mounting substrate is interposed between the first conductive film 71 and the connection pad and also adheres to the second conductive film 72. That is, the solder in the liquid phase state by the reflow process climbs up the second conductive film 72 and forms a solder fillet between the second conductive film 72 and the connection pad. Although a solder fillet is also formed in the semiconductor device A11 shown in FIG. 10, in the semiconductor device A12 of this modification example, the solder fillet is more easily formed. This solder fillet increases the bonding area of the solder and can further enhance the connection strength. Also, the soldering state of the semiconductor device A12 can be confirmed from the outside by the solder fillet.

[0118] The semiconductor device A13 shown in FIG. 12 has a substrate 11, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The substrate 11 is in the form of a thin plate and has no through holes formed therein. The substrate 11 has a substrate front surface 111, a substrate back surface 112, and a plurality of substrate side surfaces 113. The substrate front surface 111 and the substrate back surface 112 face opposite sides in the thickness direction Z. The substrate front surface 111 and the substrate back surface 112 are flat. As the material of this substrate 11, for example, synthetic resins mainly composed of epoxy resins and the like, ceramics, glass, semiconductor materials such as Si, etc. can be used. In the case of a substrate 11 made of a semiconductor material such as Si, an insulating layer covering the substrate front surface 111 is provided. As the insulating layer, for example, an oxide film such as SiO2, a resin film such as polyimide, etc. is used.

[0119] The wiring portion 20 has a main surface wiring 21 and a through wiring 22. The main surface wiring 21 is formed on the substrate front surface 111 of the substrate 11. The upper surface 211 of the main surface wiring 21 faces the same direction as the substrate front surface 111 of the substrate 11. The lower surface 212 of the main surface wiring 21 faces the same direction as the substrate back surface 112 of the substrate 11 and faces the substrate front surface 111 of the substrate 11. The side surface 213 of the main surface wiring 21 faces the same direction as the substrate side surface 113 of the substrate 11.

[0120] The encapsulation resin 60 is in contact with the substrate front surface 111 of the substrate 11 and is formed so as to cover the semiconductor element 50. The encapsulation resin 60 has a plurality of through holes 605 that penetrate the encapsulation resin 60 in the thickness direction Z. The through holes 605 extend from the resin upper surface 601 of the encapsulation resin 60 to the upper surface 211 of the main surface wiring 21. The shape of the through holes 605 is, for example, rectangular when viewed from the thickness direction Z. Note that the shape of the through holes 605 may be circular or polygonal.

[0121] The through wiring 22 is disposed in each through hole 605. The through wiring 22 has an upper surface 221, a lower surface 222, and a plurality of side surfaces 223. The upper surface 221 of the through wiring 22 is flush with the resin upper surface 601 of the encapsulation resin 60. The upper surface 221 of the through wiring 22 is exposed from the encapsulation resin 60. The lower surface 222 of the through wiring 22 is in contact with the upper surface 211 of the main surface wiring 21. The side surfaces 223 of the through wiring 22 are in contact with the inner wall surface 606 of the through hole 605 of the encapsulation resin 60.

[0122] The external connection terminal 70 is formed on the resin upper surface 601 of the encapsulation resin 60. The external connection terminal 70 is formed so as to cover the upper surface 221 of the exposed through-wiring 22. The external connection terminal 70 serves as an external connection terminal of the semiconductor device A13.

[0123] This semiconductor device A13 is mounted on the mounting substrate with the external connection terminal 70 facing the mounting substrate, that is, with the element main surface 501 of the semiconductor element 50 facing the opposite direction to the mounting substrate. In this semiconductor device A13 as well, the same effects as those of the above-described embodiment can be obtained. Further, in this semiconductor device A13, since the thickness of the substrate 11 can be made thinner than that of the substrate 10 of the semiconductor device A2 of the embodiment, the semiconductor device A13 can be made thinner.

[0124] The semiconductor device A14 shown in FIG. 13 includes a substrate 12, a wiring portion 20, an external connection terminal 70, a semiconductor element 50, and an encapsulation resin 60. The wiring portion 20 includes a main surface wiring 21 and a columnar body 25 as a through-wiring.

[0125] FIG. 13 is a schematic cross-sectional view of the semiconductor device A14 of a modified example. The substrate 12 is rectangular when viewed in the thickness direction Z. The substrate 12 includes a base material 13 and an insulating layer 14.

[0126] The base material 13 has a main surface 131, a back surface 132, and a plurality of side surfaces 133. The main surface 131 and the back surface 132 face opposite sides in the thickness direction Z. The main surface 131 and the back surface 132 are flat. The base material 13 is made of, for example, a material having electrical insulating properties. As this material, for example, a single-crystalline intrinsic semiconductor material such as Si, or a synthetic resin having an epoxy resin or the like as a main component can be used. As the main surface 131 of the base material 13, for example, a (100) plane with a crystal orientation of (100) can be adopted.

[0127] The base material 13 is provided with a plurality of through holes 135. Each through hole 135 penetrates in the thickness direction Z from the main surface 131 to the back surface 132 of the base material 13. Each through hole 135 is, for example, rectangular when viewed from the thickness direction Z. Note that the shape of the through hole 135 may be circular or polygonal. The inner wall surface 136 of each through hole 135 intersects the back surface 132. In this semiconductor device A14, the inner wall surface 136 is orthogonal to the back surface 132. Note that the inner wall surface 136 may be inclined with respect to the back surface 132 at a predetermined angle. The inclination angle of the inner wall surface 136 is, for example, an angle determined by the configuration of the base material 13 made of a semiconductor material, such as the crystal orientation.

[0128] The insulating layer 14 is formed on the base material 13. The insulating layer 14 is formed so as to cover the main surface 131 of the base material 13 and the inner wall surface 136 of the through hole 135. The insulating layer 14 includes a first insulating layer 141 that covers the main surface 131 of the base material 13 and a second insulating layer 142 that covers the inner wall surface 136 of the through hole 135. The insulating layer 14 is a film having electrical insulation properties. The insulating layer 14 in this modified example is made of SiO2. This insulating layer 14 is formed, for example, by thermally oxidizing the base material 13. The thickness of the insulating layer 14 is, for example, 0.7 μm or more and 2.0 μm or less. Note that the material, thickness, and formation method of the insulating layer 14 are not limited. For example, the insulating layer 14 may include SiO2 and a resin layer. Further, the insulating layer 14 may be made of a resin layer.

[0129] As described above, the substrate 12 has the base material 13 and the insulating layer 14. The base material 13 is made of a single-crystalline intrinsic semiconductor material and has a through hole 135 that penetrates the base material 13 from the main surface 131 to the back surface 132. The insulating layer 14 is formed so as to cover the main surface 131 of the base material 13 and the inner wall surface 136 of the through hole 135 of the base material 13. Therefore, the upper surface of the insulating layer 14 (the first insulating layer 141) becomes the substrate main surface 121 of the substrate 12, and the back surface 132 of the base material 13 becomes the substrate back surface 122 of the substrate 12. Then, the substrate 12 has a through hole 125 covered with the insulating layer 14 (the second insulating layer 142).

[0130] Note that an insulating layer may be formed on the back surface 132 of the base material 13. The insulating layer is a film having electrical insulation properties. As the insulating layer formed on the back surface 132, the same one as the insulating layer 14 can be used.

[0131] The wiring portion 20 of the semiconductor device A14 includes a plurality of main surface wirings 26 and a plurality of columnar bodies 25. The main surface wiring 26 is a part of the wiring portion 20 formed on the side of the substrate main surface 121 of the substrate 12. The main surface wiring 26 has an upper surface 261, a lower surface 262, and side surfaces 263. The main surface wiring 26 in this modification example includes a metal layer and a conductive layer.

[0132] A joint portion 40 is formed on the main surface wiring 26. The joint portion 40 includes a plating layer 41 and a first solder layer 42. The second solder layer 56 of the semiconductor element 50 is connected to the first solder layer 42.

[0133] The plurality of columnar bodies 25 are formed so as to penetrate the substrate 12. Each columnar body 25 is formed so as to be filled in a portion surrounded by the insulating layer 14 inside the through hole 125.

[0134] Each columnar body 25 is exposed from the substrate main surface 121 and the substrate back surface 122 of the substrate 12, respectively. Each columnar body 25 has an upper surface 251, a back surface 252, and a plurality of side surfaces 253. The upper surface 251 and the back surface 252 face opposite sides in the thickness direction Z. The upper surface 251 is a curved surface that curves so as to be concave toward the inside of the columnar body 25, that is, toward the back surface 252 of the columnar body 25. The back surface 252 is a surface exposed from the substrate back surface 122. The back surface 252 of the columnar body 25 is flush with the substrate back surface 122. The side surface 253 is in contact with the second insulating layer 142 of the insulating layer 14.

[0135] Note that the shape of each columnar body 25 is not limited, and for example, it may be a cylindrical shape or the like. In the semiconductor device A14 of the modification example, the main surface wiring 26 and the columnar body 25 are integrally formed of the same material. Note that the main surface wiring 26 and the columnar body 25 may be separately formed of different materials from each other.

[0136] The encapsulating resin 60 is disposed on the side of the main surface 121 of the substrate 12 and is formed to cover the semiconductor element 50. The encapsulating resin 60 is in contact with the main surface 121 of the substrate 12 and is formed to cover the semiconductor element 50 and the wiring portion 20 (the main surface wiring 26 and the upper surface 152 of the columnar body 25). The encapsulating resin 60 overlaps with the substrate 12 when viewed from the thickness direction Z. The encapsulating resin 60 is rectangular when viewed from the thickness direction Z.

[0137] The encapsulating resin 60 has electrical insulation properties. The encapsulating resin 60 is made of a resin material colored, for example, black or the like. The resin material is, for example, a synthetic resin such as an epoxy resin. Note that the material and shape of the encapsulating resin 60 are not limited.

[0138] The external connection terminal 70 is formed on the back surface 122 of the substrate 12. The external connection terminal 70 is formed to cover the upper surface 251 of the columnar body 25. The external connection terminal 70 serves as an external connection terminal of the semiconductor device A14. The external connection terminal 70 is composed of, for example, a plurality of metal layers laminated on each other. The metal layers are, for example, a Ni layer, a Pd layer, and an Au layer. Note that the material of the external connection terminal 70 is not limited, but for example, a Ni layer and an Au layer may be laminated and formed, or it may be Sn.

[0139] In this semiconductor device A14, by using the base material 13 made of a single-crystalline semiconductor material, it is possible to suppress the outflow of solder in the reflow process when mounting the semiconductor element 50. 〔Third Embodiment〕 Based on FIGS. 14 to 20, a semiconductor device A10 according to the third embodiment of the present invention will be described. The semiconductor device A10 includes a sealing resin 710, a wiring 721, a plurality of connection wirings 722, a semiconductor element 730, and a plurality of terminals 741. The semiconductor device A10 is in the form of a resin package surface-mounted on a wiring board. Here, for convenience of understanding, FIG. 14 shows through the second layer 712 (details will be described later) of the sealing resin 710. Further, in FIG. 14, the line V-V is shown by a dashed line. FIG. 15 shows through the semiconductor element 730 with respect to FIG. 14 for convenience of understanding. The semiconductor element 730 shown through in FIG. 15 is indicated by an imaginary line (two-dot chain line).

[0140] In the description of the semiconductor device A10, for convenience, the thickness direction of the semiconductor device A10 is referred to as the "thickness direction z". The direction orthogonal to the thickness direction z is referred to as the "first direction x". The direction orthogonal to both the thickness direction z and the first direction x is referred to as the "second direction y". As shown in FIG. 14, the semiconductor device A10 is rectangular when viewed along the thickness direction z.

[0141] As shown in FIGS. 17 to 19, the sealing resin 710 includes a first layer 711 and a second layer 712. Both the first layer 711 and the second layer 712 are made of a material containing a synthetic resin. As an example of the synthetic resin, an epoxy resin can be mentioned. In order to make the difference between the linear expansion coefficient of the first layer 711 and the linear expansion coefficient of the second layer 712 as small as possible, the synthetic resins contained in the first layer 711 and the second layer 712 are preferably the same as each other. The first layer 711 has a first main surface 711A, a first back surface 711B, and side surfaces 711C. The first main surface 711A and the first back surface 711B face opposite sides in the thickness direction z. Among these, the first back surface 711B faces the wiring board when the semiconductor device A10 is mounted on the wiring board. The side surfaces 711C face a direction orthogonal to the thickness direction z and are connected to the first main surface 711A and the first back surface 711B. In the semiconductor device A10, the side surfaces 711C include a pair of regions facing the first direction x and being separated from each other, and a pair of regions facing the second direction y and being separated from each other. The second layer 712 is laminated on the first main surface 711A in the thickness direction z. The second layer 712 has a second main surface 712A and a second back surface 712B. The second main surface 712A and the second back surface 712B face opposite sides in the thickness direction z. Among these, the second back surface 712B is in contact with the first main surface 711A. When viewed along the thickness direction z, the periphery of the second layer 712 coincides with the periphery of the first layer 711. Further, the distance between the first main surface 711A and the first back surface 711B is smaller than the distance between the second main surface 712A and the second back surface 712B. That is, the thickness of the first layer 711 is smaller than the thickness of the second layer 712.

[0142] As shown in FIG. 20, a filler 788 is mixed into the first layer 711. The filler 788 is a fine powder. The filler 788 contains an inorganic compound. The inorganic compound is glass, ceramics, or the like. As an example of the ceramics, alumina (Al2O3) can be mentioned.

[0143] As shown in FIGS. 14, 15, 18, and 19, the wiring 721 is disposed in contact with the first main surface 711A of the first layer 711. The wiring 721 forms part of the conductive path between the semiconductor element 730 and the wiring substrate on which the semiconductor device A10 is mounted. The wiring 721 includes a plurality of regions. When viewed along the thickness direction z, each of the plurality of regions is strip-shaped. In the semiconductor device A10, the semiconductor device A10 includes eight regions. A part of the wiring 721 is covered by the second layer 712. When viewed along the thickness direction z, the wiring 721 is located inward of the periphery of the encapsulating resin 710 (the first layer 711 and the second layer 712). For this reason, the wiring 721 is not exposed from the encapsulating resin 710 to the outside of the semiconductor device A10.

[0144] As shown in FIG. 20, each of the plurality of regions of the wiring 721 has an underlayer 789 and a main body layer 790. The underlayer 789 is in contact with the first main surface 711A of the first layer 711 and one of the plurality of connection wirings 722. The underlayer 789 is composed of a barrier layer in contact with these and a seed layer laminated in the thickness direction z with respect to the barrier layer. The composition of the barrier layer contains titanium (Ti). The composition of the seed layer contains copper (Cu). The main body layer 790 is laminated in the thickness direction z with respect to the underlayer 789. The thickness of the main body layer 790 is larger than the thickness of the underlayer 789. For this reason, in each of the plurality of regions of the wiring 721, the main body layer 790 serves as the main conductive path. The composition of the main body layer 790 is the same as the composition of the seed layer of the underlayer 789. For this reason, the composition of the main body layer 790 contains copper.

[0145] As shown in FIGS. 14, 15, and 18, each of the plurality of connection wirings 722 is connected to one of the plurality of regions of the wiring 721. Each of the plurality of connection wirings 722 reaches the first back surface 711B of the first layer 711 from the wiring 721, and a part of it is covered by the first layer 711. The plurality of connection wirings 722, together with the wiring 721, form part of the conductive path between the semiconductor element 730 and the wiring substrate on which the semiconductor device A10 is mounted. The composition of each of the plurality of connection wirings 722 contains copper.

[0146] As shown in FIGS. 16, 18, and 19, each of the plurality of connection wirings 722 has a bottom surface 722A and an end surface 722B. The bottom surface 722A is exposed at the first back surface 711B of the first layer 711. The end surface 722B is connected to the bottom surface 722A and faces a direction orthogonal to the thickness direction z. In the semiconductor device A10, the end surface 722B faces the second direction y. As shown in FIG. 17, the end surface 722B is exposed in any region of the side surface 711C of the first layer 711. In the semiconductor device A10, the end surface 722B is exposed in any one of a pair of regions that are separated from each other in the second direction y on the side surface 711C. In each of the plurality of connection wirings 722, the surface facing the opposite side of the bottom surface 722A in the thickness direction z is flush with the first main surface 711A of the first layer 711 and is in contact with the second back surface 712B of the second layer 712.

[0147] As shown in FIGS. 18 and 19, the semiconductor element 730 is joined to the wiring 721 via a plurality of bonding layers 739. The plurality of bonding layers 739 have conductivity. Each of the plurality of bonding layers 739 is composed of a nickel (Ni) layer laminated in the thickness direction z with respect to the wiring 721 and an alloy layer laminated on the nickel layer and containing tin (Sn) in its composition. The semiconductor element 730 is a flip-chip type element. In the semiconductor device A10, the semiconductor element 730 is an LSI. The semiconductor element 730 is covered by the second layer 712.

[0148] As shown in FIGS. 18 to 20, the semiconductor element 730 has a bottom surface 730A and a plurality of pads 731. The bottom surface 730A faces the first main surface 711A of the first layer 711 and the wiring 721. The plurality of pads 731 are provided on the bottom surface 730A. In the semiconductor device A10, each of the plurality of pads 731 is electrically connected to a circuit (not shown) configured inside the semiconductor element 730. Each of the plurality of pads 731 is joined to the wiring 721 via any one of the plurality of bonding layers 739. Thereby, the semiconductor element 730 is electrically connected to the wiring 721.

[0149] As shown in FIGS. 16 and 18, the plurality of terminals 741 individually cover the bottom surface 722A of the plurality of connection wirings 722. The plurality of terminals 741 are exposed to the outside of the semiconductor device A10. By bonding each of the plurality of terminals 741 to a wiring board via solder, the semiconductor device A10 is mounted on the wiring board. In the semiconductor device A10, each of the plurality of terminals 741 includes a plurality of metal layers laminated in the thickness direction z with respect to the bottom surface 722A. The plurality of metal layers are laminated in the order of a nickel layer and a gold (Au) layer in order from the closest to the bottom surface 722A. For this reason, the composition of the plurality of metal layers includes nickel and gold. As another configuration example of the plurality of metal layers, those laminated in the order of a nickel layer, a palladium (Pd) layer, and a gold layer in order from the closest to the bottom surface 722A may be used.

[0150] <Modification of the Third Embodiment> Based on FIGS. 21 and 22, a semiconductor device A11 according to a modification of the third embodiment of the present invention will be described. Here, FIG. 21 penetrates the second layer 712 of the sealing resin 710 for convenience of understanding. Further, in FIG. 21, the line IX-IX is indicated by a dashed-dotted line.

[0151] In the semiconductor device A11, the configuration of the plurality of terminals 741 is different from that of the semiconductor device A10 described above. As shown in FIG. 22, each of the plurality of terminals 741 includes a solder ball. Each of the plurality of terminals 741 protrudes in the thickness direction z from the bottom surface 722A of any one of the plurality of connection wirings 722. As shown in FIGS. 21 and 22, each of the plurality of terminals 741 has a substantially spherical shape.

[0152] Next, based on FIGS. 23 to 36, an example of a manufacturing method of the semiconductor device A10 will be described. The cross-sectional positions of FIGS. 23 to 36 are the same as the cross-sectional position of FIG. 18. First, as shown in FIG. 23, an insulating film 781 is formed on one surface of the substrate 780 in the thickness direction z. The substrate 780 is a semiconductor wafer (silicon wafer). The insulating film 781 is an oxide film (SiO2) or a nitride film (Si3N4). In the case of the oxide film for the insulating film 781, it is formed by thermal oxidation. On the other hand, in the case of the nitride film, it is formed by plasma CVD (Chemical Vapor Deposition).

[0153] Next, as shown in FIG. 24, a release layer 782 covering the upper surface of the insulating film 781 is formed. The release layer 782 consists of a metal thin film in contact with the insulating film 781 and made of titanium, and a metal thin film laminated in the thickness direction z with respect to the metal thin film and made of copper. The release layer 782 is formed by depositing these metal thin films respectively by sputtering.

[0154] Next, as shown in FIG. 25, a plurality of columnar bodies 783 protruding in the thickness direction z from the upper surface of the release layer 782 are formed. The plurality of columnar bodies 783 are made of copper. The plurality of columnar bodies 783 are formed by electrolytic plating using the release layer 782 as an electrical conduction path after lithographic patterning is performed on the upper surface of the release layer 782. The height of each of the plurality of columnar bodies 783 is made to be 100 μm or more.

[0155] Next, as shown in FIG. 26, a first resin layer 784 in contact with the release layer 782 and covering the plurality of columnar bodies 783 is formed. The first resin layer 784 is made of a material containing a black epoxy resin and a filler made of an inorganic compound mixed in the epoxy resin. The first resin layer 784 is formed by compression molding. In this step, the thickness of the first resin layer 784 is made to be 150 μm or more and larger than the height of each of the plurality of columnar bodies 783.

[0156] Next, as shown in FIG. 27, a part of each of the first resin layer 784 and the plurality of columnar bodies 783 is removed by grinding. The part to be removed is the part on the side opposite to the side where the base material 780 is located in the thickness direction z. By going through this step, the height of each of the plurality of columnar bodies 783 becomes equal to the thickness of the first resin layer 784. Further, the upper surface of each of the plurality of columnar bodies 783 is exposed on the upper surface of the first resin layer 784.

[0157] Next, as shown in FIGS. 28 to 31, a wiring 721 in contact with the upper surface of the first resin layer 784 and the upper surface of each of the plurality of columnar bodies 783, and a plurality of bonding layers 739 on the upper surface of the wiring 721 are formed.

[0158] First, as shown in FIG. 28, an underlayer 789 covering the upper surface of the first resin layer 784 and the upper surface of each of the plurality of columnar bodies 783 is formed. The underlayer 789 is formed by forming a barrier layer covering these upper surfaces by sputtering and then forming a seed layer on the upper surface of the barrier layer by sputtering. The barrier layer is made of titanium with a thickness of 100 nm to 300 nm. The seed layer is made of copper with a thickness of 200 nm to 600 nm.

[0159] Next, as shown in FIG. 29, a plurality of main body layers 790 are formed on the upper surface of the underlayer 789. The plurality of main body layers 790 are formed by performing lithographic patterning on the upper surface of the underlayer 789 and then electrolytic plating using the underlayer 789 as an electrical conduction path.

[0160] Next, as shown in FIG. 30, a plurality of bonding layers 739 are formed on the upper surface of the plurality of main body layers 790. The plurality of bonding layers 739 are formed by performing lithographic patterning on the upper surface of the underlayer 789 and the upper surface of the plurality of main body layers 790, and then electrolytic plating using the underlayer 789 and the plurality of main body layers 790 as electrical conduction paths.

[0161] Next, as shown in FIG. 31, a part of the underlying layer 789 is removed. The part of the underlying layer 789 to be removed is the part where the plurality of main body layers 790 are not laminated. The underlying layer 789 is removed by wet etching using a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Through this process, the wiring 721 is formed.

[0162] Next, as shown in FIG. 32, the semiconductor element 730 is joined to the wiring 721 via a plurality of bonding layers 739. First, using a collet, a plurality of pads 731 of the semiconductor element 730 are temporarily attached individually to the plurality of bonding layers 739. Next, the plurality of bonding layers 739 are melted by reflow. Finally, the melted plurality of bonding layers 739 are solidified by cooling. Thereby, the joining of the semiconductor element 730 to the wiring 721 is completed.

[0163] Next, as shown in FIG. 33, a second resin layer 785 in contact with the first resin layer 784 is formed. The second resin layer 785 is made of a material containing a black epoxy resin. The second resin layer 785 is formed by compression molding. Through this process, a part of the wiring 721 and the semiconductor element 730 are covered with the second resin layer 785.

[0164] Next, as shown in FIG. 34, the base material 780, the insulating film 781, and the release layer 782 are removed. The base material 780 and the insulating film 781 are removed by grinding. The release layer 782 is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide. Through this process, a part of each of the plurality of columnar bodies 783 is exposed from the first resin layer 784.

[0165] Next, as shown in FIG. 35, a plurality of metal layers 786 are formed to individually cover a part of each of the plurality of columnar bodies 783 exposed from the first resin layer 784. Each of the plurality of metal layers 786 is formed by electroless plating a nickel layer in contact with any of the plurality of columnar bodies 783 and then electroless plating a gold layer on the nickel layer.

[0166] Finally, after attaching the tape 787 to the surface of the second resin layer 785 facing the thickness direction z, the plurality of columnar bodies 783, the first resin layer 784, the second resin layer 785, and the plurality of metal layers 786 are cut in a lattice pattern along the two directions of the first direction x and the second direction y to be divided into a plurality of individual pieces. For cutting, a dicing blade or the like is used. By going through this process, the first resin layer 784 and the second resin layer 785 that have become the individual pieces become the first layer 711 of the encapsulation resin 710 of the semiconductor device A10 and the second layer 712 of the encapsulation resin 710 of the semiconductor device A10. At the same time, the plurality of columnar bodies 783 that have become the individual pieces and the plurality of metal layers 786 that individually cover them become the plurality of connection wirings 722 of the semiconductor device A10 and the plurality of terminals 741 of the semiconductor device A10. By going through the above processes, the semiconductor device A10 is manufactured.

[0167] Next, the operation and effect of the semiconductor device A10 will be described. The semiconductor device A10 includes an encapsulation resin 710, a wiring 721, and a semiconductor element 730. The encapsulation resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered by the second layer 712. The semiconductor element 730 is joined to the wiring 721 and is covered by the second layer 712. Thereby, the difference between the coefficient of linear expansion of the first layer 711 on which the semiconductor element 730 is mounted and the coefficient of linear expansion of the second layer 712 that covers the semiconductor element 730 becomes smaller than when the first layer 711 is a semiconductor wafer. Furthermore, the thickness of the second layer 712 can be made as small as possible under the condition of covering the semiconductor element 730. Therefore, according to the semiconductor device A10, it is possible to reduce the warpage of the semiconductor device A10 while achieving miniaturization.

[0168] The distance between the first major surface 711A and the first back surface 711B of the first layer 711 is smaller than the distance between the second major surface 712A and the second back surface 712B of the second layer 712. That is, the thickness of the first layer 711 is smaller than the thickness of the second layer 712. Thereby, miniaturization of the semiconductor device A10 can be achieved.

[0169] A filler 788 containing an inorganic compound is mixed in the first layer 711. The filler 788 serves as a reinforcing material for the first layer 711. Thereby, even when the thickness of the first layer 711 is made as small as possible, the mechanical strength of the first layer 711 can be ensured.

[0170] The semiconductor device A10 further includes a plurality of connection wirings 722 connected to the wiring 721. Each of the plurality of connection wirings 722 reaches the first back surface 711B of the first layer 711 from the wiring 721, and a part of it is covered by the first layer 711. Each of the plurality of connection wirings 722 has a bottom surface 722A exposed at the first back surface 711B. Thereby, in the semiconductor device A10, when viewed along the thickness direction z, the conductive member connected to the wiring 721 does not protrude from the sealing resin 710, so that a configuration suitable for miniaturization of the semiconductor device A10 can be achieved. Further, when the first layer 711 is a semiconductor wafer, it is necessary to form a plurality of holes in the semiconductor wafer for arranging the plurality of connection wirings 722. The plurality of holes can be formed by deep reactive ion etching (RIE) or the like. However, formation of the plurality of holes requires time and cost. Therefore, according to the first layer 711 of the semiconductor device A10, since it is not necessary to form the plurality of holes, the time and cost required for manufacturing the semiconductor device A10 can be reduced.

[0171] The semiconductor device A10 further includes a plurality of terminals 741 that individually cover the bottom surfaces 722A of the plurality of connection wirings 722. Thereby, when the semiconductor device A10 is mounted on a wiring board, the solder adheres to the plurality of terminals 741. Therefore, the plurality of terminals 741 can reduce the thermal shock caused by the solder acting on the plurality of connection wirings 722.

[0172] Each of the plurality of terminals 741 includes a plurality of metal layers laminated in the thickness direction z. The composition of the plurality of metal layers includes nickel and gold. Thereby, the thermal shock caused by the solder acting on the plurality of connection wirings 722 can be more effectively reduced. Further, since the wettability of the solder is good, the mounting strength of the semiconductor device A10 to the wiring board can be improved.

[0173] When viewed along the thickness direction z, the wiring 721 is located inward of the periphery of the sealing resin 710. Thereby, the entire wiring 721 is covered with the sealing resin 710. Therefore, it is possible to suppress a decrease in the withstand voltage of the semiconductor device A10 due to the wiring 721.

[0174] 〔Fourth Embodiment〕 Based on FIGS. 37 to 39, a semiconductor device A20 according to the fourth embodiment of the present invention will be described. In these figures, the same or similar elements as those of the above-described semiconductor device A10 are denoted by the same reference numerals, and redundant descriptions are omitted. Here, FIG. 37 penetrates the second layer 712 of the sealing resin 710 for convenience of understanding. Further, in FIG. 37, the line XXVI-XXVI is shown by a one-dot chain line.

[0175] In the semiconductor device A20, the configuration of the plurality of terminals 741 is different from that of the semiconductor device A10 described above. As shown in FIG. 39, in the semiconductor device A20, each of the plurality of terminals 741 has a bottom portion 791 and a side portion 792. The bottom portion 791 covers the bottom surface 722A of any one of the plurality of connection wirings 722. The bottom portion 791 includes a plurality of metal layers laminated in the thickness direction z with respect to the bottom surface 722A. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10. The side portion 792 is connected to the bottom portion 791 of any one of the plurality of terminals 741. The side portion 792 extends in the thickness direction z from the bottom portion 791. The side portion 792 covers the end surface 722B of any one of the plurality of connection wirings 722. Thereby, as shown in FIG. 38, in the semiconductor device A20, the plurality of connection wirings 722 are configured not to be exposed to the outside of the semiconductor device A10. The side portion 792 includes a plurality of metal layers laminated in a direction orthogonal to the thickness direction z (the second direction y in the semiconductor device A20). The configuration of the metal layer is the same as the configuration of the plurality of metal layers included in the bottom portion 791.

[0176] Next, the operation and effect of the semiconductor device A20 will be described. The semiconductor device A20 includes a sealing resin 710, a wiring 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered by the second layer 712. The semiconductor element 730 is joined to the wiring 721 and covered by the second layer 712. Therefore, also with the semiconductor device A20, it is possible to reduce the warpage of the semiconductor device A20 while achieving miniaturization.

[0177] In the semiconductor device A20, each of the plurality of terminals 741 has a bottom portion 791 and a side portion 792 connected to the bottom portion 791. The bottom portion 791 covers the bottom surface 722A of any one of the plurality of connection wirings 722. The side portion 792 covers the end surface 722B of any one of the plurality of connection wirings 722. Thereby, when the semiconductor device A10 is mounted on the wiring board, at each of the plurality of terminals 741, solder adheres not only to the bottom portion 791 but also to the side portion 792. Therefore, at each of the plurality of terminals 741, the adhesion area of the solder becomes larger, so that the mounting strength of the semiconductor device A20 to the wiring board can be improved. Further, since the solder adhering to the side portion 792 can be easily visually recognized, the mounting state of the semiconductor device A20 to the wiring board can be confirmed by visual inspection of the appearance.

[0178] 〔Fifth Embodiment〕 Based on FIGS. 40 to 44, a semiconductor device A30 according to the fifth embodiment of the present invention will be described. In these figures, elements that are the same as or similar to the above-described semiconductor device A10 are denoted by the same reference numerals, and redundant descriptions are omitted. Here, FIG. 40 penetrates the second layer 712 of the encapsulating resin 710 for convenience of understanding. Further, in FIG. 40, the line XXIX-XXIX is indicated by a one-dot chain line.

[0179] The semiconductor device A30 is different from the configuration of the above-described semiconductor device A10 in that it includes a heat sink 750. As shown in FIGS. 40 to 43, the semiconductor device A30 includes a heat sink 750. When viewed along the thickness direction z, at least a part of the heat sink 750 overlaps the semiconductor element 730. The heat sink 750 has a base portion 751, a covering portion 752, and a bump portion 753. The base portion 751 is a portion embedded in the first layer 711 of the sealing resin 710 and is in contact with the second layer 712 of the sealing resin 710. The thickness of the base portion 751 is equal to the distance between the first main surface 711A of the first layer 711 and the first back surface 711B of the first layer 711, that is, the thickness of the first layer 711. The composition of the base portion 751 contains copper. The covering portion 752 includes a plurality of metal layers laminated in the thickness direction z with respect to the base portion 751 and is exposed at the first back surface 711B. Therefore, the covering portion 752 is exposed to the outside of the semiconductor device A30. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10.

[0180] As shown in FIGS. 42 and 43, the bump portion 753 is located on the side opposite to the covering portion 752 with respect to the base portion 751 in the thickness direction z. The bump portion 753 protrudes from the base portion 751 toward the lower surface 730A of the semiconductor element 730 in the thickness direction z. As shown in FIG. 44, the bump portion 753 has an underlayer 793 and a main body layer 794. The underlayer 793 is in contact with the base portion 751. The underlayer 793 is composed of a barrier layer in contact with the base portion 751 and a seed layer laminated in the thickness direction z with respect to the barrier layer. The composition of the barrier layer contains titanium. The composition of the seed layer contains copper. The thickness of the underlayer 793 is equal to the thickness of the underlayer 789 of the wiring 721. The main body layer 794 is laminated in the thickness direction z with respect to the underlayer 793. The composition of the main body layer 790 is the same as the composition of the seed layer of the underlayer 789. Therefore, the composition of the main body layer 790 contains copper. The thickness of the main body layer 794 is larger than the thickness of the underlayer 793 and is equal to the thickness of the main body layer 790 of the wiring 721. Therefore, the thickness of the bump portion 753 is equal to the thickness of the wiring 721.

[0181] As shown in FIGS. 42 and 43, any one of the plurality of pads 731 of the semiconductor element 730 is joined to the bump portion 753 via the joining layer 739. The pad 731 joined to the bump portion 753 is a so-called dummy pad that is not electrically connected to the circuit formed inside the semiconductor element 730. Alternatively, the pad 731 joined to the bump portion 753 is connected to the ground of the semiconductor element 730.

[0182] Next, the operation and effect of the semiconductor device A30 will be described. The semiconductor device A30 includes a sealing resin 710, wirings 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered by the second layer 712. The semiconductor element 730 is joined to the wiring 721 and covered by the second layer 712. Therefore, also in the semiconductor device A30, it is possible to reduce the warpage of the semiconductor device A30 while achieving miniaturization.

[0183] The semiconductor device A30 further includes a heat sink 750. The heat sink 750 has a base portion 751. The base portion 751 is embedded in the first layer 711 and in contact with the second back surface 712B of the second layer 712. When viewed along the thickness direction z, at least a part of the heat sink 750 overlaps the semiconductor element 730. Thereby, when the semiconductor device A30 is in use, the heat generated from the semiconductor element 730 can be efficiently radiated to the outside of the semiconductor device A30. The thickness of the base portion 751 is equal to the distance between the first main surface 711A and the first back surface 711B of the first layer 711. Thereby, in the manufacture of the semiconductor device A30, the formation method of the base portion 751 can be made the same as the formation method of the plurality of connection wirings 722 (see FIGS. 25 to 27).

[0184] The heat sink 750 has a covering portion 752. The covering portion 752 is laminated on the base portion 751 and exposed at the first back surface 711B of the first layer 711. The covering portion 752 includes a plurality of metal layers that constitute each of the plurality of terminals 741. Thereby, when mounting the semiconductor device A30 on the wiring board, the heat sink 750 can be joined to the wiring board by solder, so that the heat conducted from the semiconductor element 730 to the heat sink 750 can be more effectively transmitted to the wiring board. Further, in the manufacture of the semiconductor device A30, the formation method of the covering portion 752 can be made the same as the formation method of the plurality of terminals 741 (see FIG. 35).

[0185] The heat sink 750 has a bump portion 753. The bump portion 753 protrudes from the base portion 751 toward the lower surface 730A of the semiconductor element 730 in the thickness direction z. Any one of the plurality of pads 731 of the semiconductor element 730 is joined to the bump portion 753. Thereby, the heat generated from the semiconductor element 730 can be more effectively transmitted to the heat sink 750. At the same time, the heights of each of the plurality of bonding layers 739 that are individually positioned with respect to the plurality of pads 731 can all be made equal. Further, in the manufacture of the semiconductor device A30, the formation method of the bump portion 753 can be made the same as the formation method of the wiring 721 (see FIGS. 28, 29, and 31).

[0186] 〔Sixth Embodiment〕 Based on FIGS. 45 to 48, the semiconductor device A40 according to the sixth embodiment of the present invention will be described. In these figures, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant descriptions are omitted. Here, FIG. 46 is shown passing through the second layer 712 of the encapsulating resin 710 for convenience of understanding. In FIG. 45, the line XXXIV-XXXIV is indicated by a dashed line.

[0187] In the semiconductor device A40, instead of the plurality of connection wirings 722 and the plurality of terminals 741, it is provided with a plurality of first connection wirings 723, a plurality of second connection wirings 724, a plurality of first terminals 742, and a plurality of second terminals 743, which is different from the configuration of the semiconductor device A10 described above.

[0188] As shown in FIGS. 46 to 48, the semiconductor device A40 includes a plurality of first connection wirings 723. Each of the plurality of first connection wirings 723 is connected to one of a plurality of regions of the wiring 721. Each of the plurality of first connection wirings 723 reaches from the wiring 721 to the first back surface 711B of the first layer 711 and a part of it is covered by the first layer 711. The plurality of first connection wirings 723, together with the wiring 721, constitute a part of the conduction path between the semiconductor element 730 and the wiring board on which the semiconductor device A40 is mounted. The composition of each of the plurality of first connection wirings 723 contains copper.

[0189] As shown in FIG. 47, each of the plurality of first connection wirings 723 has a bottom surface 723A and an end surface 723B. The bottom surface 723A is exposed on the first back surface 711B of the first layer 711. The end surface 723B is connected to the bottom surface 723A and faces a direction orthogonal to the thickness direction z. In the semiconductor device A40, the end surface 723B faces the second direction y. As shown in FIGS. 46 and 47, the end surface 723B is exposed in one of the regions of the side surface 711C of the first layer 711. In the semiconductor device A40, the end surface 723B is exposed in one of a pair of regions of the side surface 711C that are separated from each other in the second direction y. In each of the plurality of first connection wirings 723, the surface facing the side opposite to the bottom surface 723A in the thickness direction z is flush with the first main surface 711A of the first layer 711 and is in contact with the second back surface 712B of the second layer 712.

[0190] As shown in FIGS. 45 to 48, the semiconductor device A40 includes a plurality of second connection wirings 724. Each of the plurality of second connection wirings 724 is connected to one of a plurality of regions of the wiring 721. Each of the plurality of second connection wirings 724 reaches from the wiring 721 to the second main surface 712A of the second layer 712 and a part of it is covered by the second layer 712. The plurality of second connection wirings 724, together with the wiring 721, constitute a part of the conduction path between the semiconductor element 730 and the wiring board on which the semiconductor device A40 is mounted. The composition of each of the plurality of second connection wirings 724 contains copper.

[0191] As shown in FIGS. 46 to 48, each of the plurality of second connection wirings 724 has a top surface 724A and a side surface 724B. The top surface 724A is exposed on the second main surface 712A of the second layer 712. The side surface 724B is connected to the top surface 724A and faces a direction orthogonal to the thickness direction z. The side surface 724B is covered with the second layer 712.

[0192] As shown in FIG. 47, when viewed along the thickness direction z, the shortest distance L2 from the center C of the semiconductor element 730 to any one of the plurality of second connection wirings 724 is smaller than the shortest distance L1 from the center C of the semiconductor element 730 to any one of the plurality of first connection wirings 723. Here, the center C of the semiconductor element 730 refers to the intersection of the diagonals of the semiconductor element 730 when viewed along the thickness direction z.

[0193] As shown in FIGS. 47 and 48, the semiconductor device A40 includes a plurality of first terminals 742. The plurality of first terminals 742 individually cover the bottom surfaces 723A of the plurality of first connection wirings 723. The plurality of first terminals 742 are exposed to the outside of the semiconductor device A40. By bonding each of the plurality of first terminals 742 to the wiring board via solder, the semiconductor device A40 is mounted on the wiring board. Each of the plurality of first terminals 742 includes a plurality of metal layers stacked in the thickness direction z with respect to the bottom surface 723A. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10.

[0194] As shown in FIGS. 45, 47, and 48, the semiconductor device A40 includes a plurality of second terminals 743. The plurality of second terminals 743 individually cover the top surfaces 724A of the plurality of second connection wirings 724. The plurality of second terminals 743 are exposed to the outside of the semiconductor device A40. By bonding each of the plurality of second terminals 743 to the wiring board via solder, the semiconductor device A40 is mounted on the wiring board. Each of the plurality of second terminals 743 includes a plurality of metal layers stacked in the thickness direction z with respect to the top surface 724A. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10.

[0195] Next, the operation and effect of the semiconductor device A40 will be described. The semiconductor device A40 includes a sealing resin 710, a wiring 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered by the second layer 712. The semiconductor element 730 is joined to the wiring 721 and is covered by the second layer 712. Therefore, also with the semiconductor device A40, it is possible to reduce the warpage of the semiconductor device A40 while achieving miniaturization.

[0196] The semiconductor device A40 includes a plurality of first connection wirings 723 and a plurality of second connection wirings 724 instead of a plurality of connection wirings 722. Each of the plurality of first connection wirings 723 reaches from the wiring 721 to the first back surface 711B of the first layer 711, and a part of it is covered by the first layer 711. Each of the plurality of first connection wirings 723 has a bottom surface 723A exposed at the first back surface 711B. Each of the plurality of second connection wirings 724 reaches from the wiring 721 to the second main surface 712A of the second layer 712, and a part of it is covered by the second layer 712. Each of the plurality of second connection wirings 724 has a top surface 724A exposed at the second main surface 712A. Thereby, when mounting the semiconductor device A40 on a wiring board, the semiconductor device A40 can be mounted with not only the first back surface 711B but also the second main surface 712A facing the wiring board. Therefore, since the semiconductor device A40 can be mounted on the wiring board regardless of the orientation of the semiconductor device A40, the efficiency of the mounting operation can be improved.

[0197] When viewed along the thickness direction z, the shortest distance L2 from the center C of the semiconductor element 730 to any one of the plurality of second connection wirings 724 is smaller than the shortest distance L1 from the center C of the semiconductor element 730 to any one of the plurality of first connection wirings 723. Thereby, a configuration can be adopted in which the side surfaces 724B of each of the plurality of second connection wirings 724 are covered by the second layer 712. Here, the thickness of the second layer 712 is larger than the thickness of the first layer 711. For this reason, since the height of each of the plurality of second connection wirings 724 is larger than the height of each of the plurality of first connection wirings 723, the volume of each of the plurality of second connection wirings 724 tends to be larger than the volume of each of the plurality of first connection wirings 723. Therefore, by adopting this configuration, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device A40 due to the plurality of second connection wirings 724.

[0198] Instead of the plurality of terminals 741, the semiconductor device A40 includes a plurality of first terminals 742 and a plurality of second terminals 743. The plurality of first terminals 742 individually cover the bottom surfaces 723A of the plurality of first connection wirings 723. The plurality of second terminals 743 individually cover the top surfaces 724A of the plurality of second connection wirings 724. Thereby, when the semiconductor device A40 is mounted on a wiring board, the solder adheres to either the plurality of first terminals 742 or the plurality of second terminals 743. Therefore, the plurality of first terminals 742 and the plurality of second terminals 743 can reduce the thermal shock caused by the solder acting on either the plurality of first connection wirings 723 or the plurality of second connection wirings 724.

[0199] The present invention is not limited to the semiconductor devices A10 to A40 described above. The specific configuration of each part of the present invention can be freely designed and changed in various ways. Hereinafter, embodiments of an electronic component and a method for manufacturing an electronic component will be described with reference to the drawings. Each of the embodiments shown below exemplifies a configuration and method for embodying a technical idea, and does not limit the material, shape, structure, arrangement, dimensions, etc. of each component to those described below. Various changes can be made to each of the following embodiments.

[0200] [Seventh Embodiment] (Configuration of Electronic Component) With reference to FIGS. 49 to 58, the configuration of the electronic component 801A according to the seventh embodiment of the present disclosure will be described. In FIGS. 49 and 51, for convenience, the solder SD for joining the second functional element 860 and the encapsulating resin 840 is omitted. In FIG. 53, for convenience, the second functional element 860 is shown by a two-dot chain line. In FIG. 55, for convenience, the second functional element 860 is shown as a side structure instead of a cross-sectional structure. In FIGS. 56 and 58, for convenience, the second functional element 860 and the solder SD are omitted. Also, the solder SD is dotted even in a side view to facilitate identification from other components.

[0201] As shown in FIGS. 49 to 52, the electronic component 801A includes a substrate 810 which is an example of an insulating member, internal electrodes 820, a first functional element 830, an encapsulating resin 840, external electrodes 850, and a second functional element 860. The electronic component 801A is a component surface-mounted on a wiring board (not shown) of various electronic devices. As shown in FIGS. 49 and 52, the first functional element 830 is disposed inside the encapsulating resin 840, and as shown in FIGS. 49 to 51, the second functional element 860 is disposed on the encapsulating resin 840 outside the encapsulating resin 840. The encapsulating resin 840 is laminated on the substrate 810. The second functional element 860 is laminated on the encapsulating resin 840. As shown in FIG. 52, in the electronic component 801A of the present embodiment, the external electrodes 850 are located outside the first functional element 830 by pulling out the internal electrodes 820 to the outside of the first functional element 830.

[0202] In the following description, for convenience, the thickness direction of the substrate 810 is referred to as the thickness direction z. Also, two directions orthogonal to each other among the directions orthogonal to the thickness direction z are referred to as the first direction x and the second direction y, respectively.

[0203] As shown in FIGS. 49 and 52, the substrate 810 mounts the first functional element 830 and is a support member serving as the basis for the electronic component 801A. As shown in FIG. 52, in the present embodiment, the shape of the substrate 810 viewed from the thickness direction z is a substantially square having a pair of sides along the first direction x and a pair of sides along the second direction y.

[0204] Note that the shape of the substrate 810 viewed from the thickness direction z is not limited to a square and can be arbitrarily changed. In one example, the shape of the substrate 810 viewed from the thickness direction z is a rectangular shape in which one of the first direction x and the second direction y is the long side and the other of the first direction x and the second direction y is the short side.

[0205] As shown in FIGS. 52 and 55, the substrate 810 has a substrate main surface 810s which is an example of an insulating main surface, a substrate back surface 810r which is an example of an insulating back surface, and a plurality (four in the present embodiment) of substrate side surfaces 811 to 814 which are examples of insulating side surfaces. As shown in FIG. 55, the substrate main surface 810s and the substrate back surface 810r face opposite sides in the thickness direction z. The substrate main surface 810s and the substrate back surface 810r are each flat. As shown in FIG. 52, the substrate side surfaces 811 to 814 are provided between the substrate main surface 810s and the substrate back surface 810r in the thickness direction z and face the first direction x or the second direction y. The substrate side surfaces 811 and 812 are surfaces facing opposite sides in the second direction y and extend along the first direction x when viewed from the thickness direction z. The substrate side surfaces 813 and 814 are surfaces facing opposite sides in the first direction x and extend along the second direction y when viewed from the thickness direction z.

[0206] In the following description, for convenience, the direction from the substrate back surface 810r to the substrate main surface 810s in the thickness direction z is referred to as "upward", and the direction from the substrate main surface 810s to the substrate back surface 810r is referred to as "downward". Therefore, it can be said that the substrate main surface 810s is the upper surface of the substrate 810, and the substrate back surface 810r is the lower surface of the substrate 810.

[0207] As shown in FIG. 52, the substrate 810 is made of, for example, a material having electrical insulation properties. As this material, for example, a synthetic resin mainly composed of an epoxy resin or the like, ceramics, glass, or the like can be used. In the present embodiment, the substrate 810 is made of a synthetic resin mainly composed of an epoxy resin. The substrate 810 has a plurality of recesses 815 that are recessed inward from each of the substrate side surfaces 811 to 814 so as to penetrate the substrate 810 in the thickness direction z. In the present embodiment, four recesses 815 are provided for each side of the substrate 810. The shape of each recess 815 viewed from the thickness direction z is a rectangular concave shape. The shape of each of the four recesses 815 arranged near the substrate side surface 811 and the four recesses 815 arranged near the substrate side surface 812 viewed from the thickness direction z is a rectangular concave shape in which the first direction x is the short side and the second direction y is the long side. The shape of each of the four recesses 815 arranged near the substrate side surface 813 and the four recesses 815 arranged near the substrate side surface 814 viewed from the thickness direction z is a rectangular concave shape in which the first direction x is the long side and the second direction y is the short side.

[0208] The four recesses 815 provided on the substrate side surface 811 are formed so as to be outside the first functional element 830 in the second direction y. The four recesses 815 provided on the substrate side surface 812 are formed so as to be outside the first functional element 830 in the second direction y. The four recesses 815 provided on the substrate side surface 813 are formed so as to be outside the first functional element 830 in the first direction x. The four recesses 815 provided on the substrate side surface 814 are formed so as to be outside the first functional element 830 in the first direction x. Thus, each recess 815 does not overlap with the first functional element 830 when viewed from the thickness direction z.

[0209] The substrate 810 has a through-hole 816 that penetrates the substrate 810 in the thickness direction z. The through-hole 816 is provided at the center of the substrate 810 in the first direction x and the second direction y. When viewed from the thickness direction z, the through-hole 816 overlaps with the first functional element 830. The shape of the through-hole 816 when viewed from the thickness direction z is rectangular. In the present embodiment, the shape of the through-hole 816 when viewed from the thickness direction z is a rectangular shape with the first direction x as the long side and the second direction y as the short side.

[0210] Note that the shape of each recess 815 when viewed from the thickness direction z can be arbitrarily changed. The shape of each recess 815 when viewed from the thickness direction z may be a concave shape that is square, arc-shaped, or the like, or may be a concave shape that is a polygon other than a quadrilateral. Also, the shape of the through-hole 816 when viewed from the thickness direction z can be arbitrarily changed. The shape of the through-hole 816 when viewed from the thickness direction z may be square, circular, elliptical, or the like, or may be a polygon other than a quadrilateral.

[0211] As shown in FIGS. 52, 54, and 55, the encapsulating resin 840 is provided so as to cover the entire substrate main surface 810s of the substrate 810. In other words, the encapsulating resin 840 overlaps with the entire substrate 810 when viewed from the thickness direction z. As shown in FIG. 55, the encapsulating resin 840 covers the internal electrode 820 and the first functional element 830.

[0212] As shown in FIGS. 49 to 53, the encapsulation resin 840 has a resin main surface 840s which is an example of an element mounting surface, a resin back surface 840r, and a plurality (four in this embodiment) of resin side surfaces 841 to 844. The resin main surface 840s and the resin back surface 840r face opposite sides in the thickness direction z. The resin main surface 840s and the resin back surface 840r are each flat. The resin main surface 840s faces the same direction as the substrate main surface 810s, and the resin back surface 840r faces the same direction as the substrate back surface 810r. The resin side surfaces 841 to 844 are provided between the resin main surface 840s and the resin back surface 840r in the thickness direction z and face the first direction x or the second direction y. The resin side surfaces 841 and 842 are surfaces facing opposite sides in the second direction y and extend along the first direction x when viewed from the thickness direction z. The resin side surface 841 faces the same direction as the substrate side surface 811 in the second direction y, and the resin side surface 842 faces the same direction as the substrate side surface 812 in the second direction y. The resin side surfaces 843 and 844 are surfaces facing opposite sides in the first direction x and extend along the second direction y when viewed from the thickness direction z. The resin side surface 843 faces the same direction as the substrate side surface 813 in the first direction x, and the resin side surface 844 faces the same direction as the substrate side surface 814 in the first direction x. In this embodiment, a part of the resin side surface 841 in the thickness direction z is flush with the substrate side surface 811, a part of the resin side surface 842 in the thickness direction z is flush with the substrate side surface 812, a part of the resin side surface 843 in the thickness direction z is flush with the substrate side surface 813, and a part of the resin side surface 844 in the thickness direction z is flush with the substrate side surface 814.

[0213] As shown in FIGS. 49 to 52, on each of the resin side surfaces 841 to 844 of the encapsulation resin 840, a step 845 that depresses inward from each of the resin side surfaces 841 to 844 is provided. Due to this step 845, the encapsulation resin 840 is partitioned into a first resin portion 846 and a second resin portion 847 in the thickness direction z. The first resin portion 846 is the portion from the step 845 to the resin main surface 840s, and the second resin portion 847 is the portion from the step 845 to the resin back surface 840r. As shown in FIGS. 49 to 52, the second resin portion 847 is a portion that depresses inward from the first resin portion 846.

[0214] The encapsulation resin 840 is made of, for example, a resin material having electrical insulation properties. As this resin material, for example, a synthetic resin mainly composed of an epoxy resin can be used. In the present embodiment, the material constituting the substrate 810 is the same as the material constituting the encapsulation resin 840. Further, the encapsulation resin 840 is colored, for example, black. The encapsulation resin 840 is formed on the substrate main surface 810s by mold molding so as to cover the substrate main surface 810s of the substrate 810. Therefore, the resin back surface 840r is in contact with the substrate main surface 810s. More specifically, the resin back surface 840r and the substrate main surface 810s are melted and adhered to each other. Thus, the resin back surface 840r and the substrate main surface 810s become the interface between the substrate 810 and the encapsulation resin 840.

[0215] As shown in FIGS. 51 and 53, on the resin main surface 840s, an upper surface wiring 870 and an insulating film 873 are provided. The upper surface wiring 870 is a wiring electrically connected to the second functional element 860 and constitutes a part of a conductive path that electrically connects the second functional element 860 and the internal electrode 820. The upper surface wiring 870 is made of, for example, Cu and is formed on the resin main surface 840s. The insulating film 873 is made of a material having electrical insulation properties and is made of, for example, a polyimide resin.

[0216] The upper surface wiring 870 has a first upper surface electrode 871 and a second upper surface electrode 872. The first upper surface electrode 871 and the second upper surface electrode 872 are arranged to be separated from each other in the first direction x. The first upper surface electrode 871 and the second upper surface electrode 872 each extend in the first direction x. The shapes of the first upper surface electrode 871 and the second upper surface electrode 872 viewed from the thickness direction z are rectangular with the first direction x as the long side direction and the second direction y as the short side direction.

[0217] The first upper surface electrode 871 and the second upper surface electrode 872 are exposed from the insulating film 873. In other words, the insulating film 873 covers the resin main surface 840s and the portions of the upper surface wiring 870 other than the first upper surface electrode 871 and the second upper surface electrode 872.

[0218] As shown in FIGS. 52 and 55, the internal electrode 820 has a plurality (16 in this embodiment) of main surface wirings 821, a plurality (16 in this embodiment) of through wirings 822, and a plurality (2 in this embodiment) of connection conductors 823. A plurality of through wirings 822 and a plurality of connection conductors 823 are electrically connected to the plurality of main surface wirings 821. Therefore, the plurality of main surface wirings 821, the plurality of through wirings 822, and the plurality of connection conductors 823 are electrically connected to each other. In the following description, for the sake of convenience, in order to distinguish between the two connection conductors 823, one connection conductor 823 is referred to as the first connection conductor 823A, and the other connection conductor 823 is referred to as the second connection conductor 823B.

[0219] Each through wiring 822 is a wiring that connects the external electrode 850 and the main surface wiring 821, and is disposed in each recess 815 and through hole 816. As shown in FIG. 52, the through wirings 822 disposed in each of the four recesses 815 provided on the substrate side surface 811 are formed so as to be outside the first functional element 830 in the second direction y. The through wirings 822 disposed in each of the four recesses 815 provided on the substrate side surface 812 are formed so as to be outside the first functional element 830 in the second direction y. The through wirings 822 disposed in each of the four recesses 815 provided on the substrate side surface 813 are formed so as to be outside the first functional element 830 in the first direction x. The through wirings 822 disposed in each of the four recesses 815 provided on the substrate side surface 814 are formed so as to be outside the first functional element 830 in the first direction x. Thus, each through wiring 822 does not overlap with the first functional element 830 when viewed from the thickness direction z.

[0220] Note that, with respect to each through wiring 822 disposed in the recess 815 of the substrate 810, the positional relationship between each through wiring 822 and the first functional element 830 when viewed from the thickness direction z can be arbitrarily changed. In one example, a part of each through wiring 822 may overlap with the first functional element 830 when viewed from the thickness direction z. In short, it is preferable that each through wiring 822 is configured to extend outside the first functional element 830 in a direction orthogonal to the thickness direction z.

[0221] In this embodiment, each through-wiring 822 is provided separately from the main surface wiring 821. The shape of each through-wiring 822 viewed from the thickness direction z is determined according to the shapes of the respective recesses 815 and through-holes 816 viewed from the thickness direction z. In this embodiment, the shape of each through-wiring 822 viewed from the thickness direction z is rectangular. Each through-wiring 822 is made of a material having electrical conductivity. As the material of each through-wiring 822, for example, Cu, a Cu alloy, or the like can be used. In this embodiment, each through-wiring 822 includes a plating layer.

[0222] As shown in FIG. 55, each through-wiring 822 has a main surface 822s, a back surface 822r, and a plurality (four in this embodiment) of side surfaces 822x. Each through-wiring 822 penetrates the substrate 810 in the thickness direction z.

[0223] The main surface 822s and the back surface 822r face opposite sides in the thickness direction z. The main surface 822s faces the same direction as the substrate main surface 810s and is flush with the substrate main surface 810s in this embodiment. The back surface 822r faces the same direction as the substrate back surface 810r and is flush with the substrate back surface 810r in this embodiment. Thus, the main surface 822s is exposed from the substrate main surface 810s, and the back surface 822r is exposed from the substrate back surface 810r.

[0224] Each side surface 822x is provided between the main surface 822s and the back surface 822r in the thickness direction z and faces the first direction x or the second direction y. One of the four side surfaces 822x of the through-wiring 822 disposed in each recess 815 forms an exposed side surface 822xa that is exposed from the substrate side surfaces 811 to 814 of the substrate 810. The four side surfaces 822x of the through-wiring 822 disposed in the through-hole 816 are each surrounded by the substrate 810. That is, the four side surfaces 822x of the through-wiring 822 disposed in the through-hole 816 are not exposed.

[0225] Each main surface wiring 821 is formed on the substrate main surface 810s of the substrate 810. It can also be said that each main surface wiring 821 is provided in the second resin portion 847 of the sealing resin 840. Each main surface wiring 821 is made of a material having electrical conductivity. As the material of each main surface wiring 821, for example, Cu, a Cu alloy, etc. can be used. In the present embodiment, each main surface wiring 821 includes a plating layer.

[0226] The plurality of main surface wirings 821 have a plurality of main surface wirings 821 extending in the first direction x and a plurality of main surface wirings 821 extending in the second direction y. The plurality of main surface wirings 821 extending in the first direction x are arranged spaced apart from each other in the second direction y, and the plurality of main surface wirings 821 extending in the second direction y are arranged spaced apart from each other in the first direction x. The thickness of each main surface wiring 821 (the dimension in the thickness direction z of each main surface wiring 821) is thinner than the thickness of each through wiring 822 (the dimension in the thickness direction z of each through wiring 822). In other words, the thickness of each through wiring 822 is thicker than the thickness of each main surface wiring 821.

[0227] Each main surface wiring 821 has a wiring main surface 821s, a wiring back surface 821r, and a wiring side surface 821x. The wiring main surface 821s faces the same direction as the substrate main surface 810s. The wiring back surface 821r faces the same direction as the substrate back surface 810r and faces the substrate main surface 810s. The wiring side surface 821x is provided between the wiring main surface 821s and the wiring back surface 821r in the thickness direction z and faces the same direction as the substrate side surfaces 811 to 814. The wiring side surface 821xa of the wiring side surface 821x that faces the same direction as the exposed side surface 822xa of the through wiring 822 is exposed from the resin side surfaces 841 to 844. The wiring side surface 821xa is flush with the exposed side surface 822xa.

[0228] As shown in FIG. 55, the main surface wiring 821 is arranged to cover the through wiring 822 from above. For this reason, the back surface 821r of the wiring is in contact with the main surface 822s of the through wiring 822. Thereby, the main surface wiring 821 and the through wiring 822 are electrically connected. Thus, the through wiring 822 extends from the back surface 821r of the wiring to the back surface 810r of the substrate in the thickness direction z, and it can be said that it is exposed from the back surface 810r of the substrate.

[0229] The main surface wiring 821 extending in the first direction x has an inner portion 821p that extends inward in the first direction x of the substrate 810 from the through wiring 822 disposed in the concave portion 815 of the substrate 810. The main surface wiring 821 extending in the second direction y has an inner portion 821p that extends inward in the second direction y of the substrate 810 from the through wiring 822 disposed in the concave portion 815. The tip portions of these inner portions 821p overlap the outer peripheral portion of the first functional element 830 when viewed from the thickness direction z.

[0230] The main surface wiring 821 has a main surface wiring 821 that conducts with the through wiring 822 disposed in the through hole 816 of the substrate 810. This main surface wiring 821 covers the main surface 822s of the through wiring 822. The dimension in the first direction x and the dimension in the second direction y of this main surface wiring 821 are the same as the dimension in the first direction x and the dimension in the second direction y of the through wiring 822.

[0231] As shown in FIG. 56, the main surface wiring 821 includes a metal layer 821a and a conductive layer 821b. The metal layer 821a and the conductive layer 821b are laminated on the main surface 810s of the substrate in this order.

[0232] The metal layer 821a is composed of, for example, a Ti (titanium) layer in contact with the main surface 810s of the substrate and the main surface 822s of the through wiring 822, and a Cu layer in contact with the Ti layer. The metal layer 821a is formed as a seed layer for forming the conductive layer 821b. The metal layer 821a has an upper surface 821as and a lower surface 821ar facing opposite sides in the thickness direction z. The lower surface 821ar constitutes the back surface 821r of the main surface wiring 821.

[0233] The conductive layer 821b is formed on the upper surface 821as of the metal layer 821a. The conductive layer 821b is made of Cu or a Cu alloy. The conductive layer 821b has an upper surface 821bs and a lower surface 821br facing opposite sides in the thickness direction z. In the present embodiment, the lower surface 821br of the conductive layer 821b is in contact with the upper surface 821as of the metal layer 821a. The upper surface 821bs of the conductive layer 821b is covered by the second resin portion 847 of the sealing resin 840. The upper surface 821bs of the conductive layer 821b constitutes the wiring main surface 821s of the main surface wiring 821.

[0234] As shown in FIG. 55, the first connection conductor 823A extends in the thickness direction z from the wiring main surface 821s of one of the plurality of main surface wirings 821 closer to the substrate side surface 811 in the first direction x. As shown in FIG. 52, the first connection conductor 823A is connected to the main surface wiring 821 closest to the substrate side surface 814 in the second direction y among the plurality of main surface wirings 821 closer to the substrate side surface 811 in the first direction x. As shown in FIG. 55, the second connection conductor 823B extends in the thickness direction z from the wiring main surface 821s of one of the plurality of main surface wirings 821 closer to the substrate side surface 812. As shown in FIG. 52, the second connection conductor 823B is connected to the main surface wiring 821 closest to the substrate side surface 813 in the second direction y among the plurality of main surface wirings 821 closer to the substrate side surface 812 in the first direction x.

[0235] Each of the connection conductors 823A and 823B is arranged closer to the through-wiring 822 than the first functional element 830 in the inner portion 821p of the main surface wiring 821. Each of the connection conductors 823A and 823B is arranged inside the through-wiring 822 when viewed from the thickness direction z. Specifically, as shown in FIG. 55, each of the connection conductors 823A and 823B is arranged in the portion between the through-wiring 822 and the first functional element 830 in the inner portion 821p of the main surface wiring 821 when viewed from the thickness direction z.

[0236] As shown in FIGS. 52 and 53, the shape of each connection conductor 823A, 823B viewed from the thickness direction z is rectangular. That is, each connection conductor 823A, 823B is a prism. Note that the shape of each connection conductor 823A, 823B is not limited to this, and for example, it may be a cylinder, a polygonal prism, or the like. Each connection conductor 823A, 823B is made of a material having electrical conductivity. As the material of each connection conductor 823A, 823B, for example, Cu, a Cu alloy, or the like can be used. In the present embodiment, each connection conductor 823A, 823B includes a plating layer.

[0237] As shown in FIG. 55, each connection conductor 823A, 823B has an upper surface 823s, a lower surface 823r, and a side surface 823x. The upper surface 823s of each connection conductor 823A, 823B faces the same direction as the main surface 810s of the substrate, and the lower surface 823r of each connection conductor 823A, 823B faces the same direction as the back surface 810r of the substrate. The side surface 823x of each connection conductor 823A, 823B is provided between the upper surface 823s and the lower surface 823r in the thickness direction z and faces the first direction x or the second direction y. The side surface 823x of each connection conductor 823A, 823B is entirely covered by the sealing resin 840.

[0238] The lower surface 823r of each connection conductor 823A, 823B is the surface that contacts the wiring main surface 821s of the main surface wiring 821. This lower surface 823r is flat. Each connection conductor 823A, 823B extends from the wiring main surface 821s to the resin main surface 840s in the thickness direction z. For this reason, the upper surface 823s of each connection conductor 823A, 823B is exposed from the resin main surface 840s. In the present embodiment, as shown in FIG. 58, the upper surface 823s of the first connection conductor 823A is formed to be recessed in a curved shape. Although not shown, the upper surface 823s of the second connection conductor 823B is also formed to be recessed in a curved shape in the same manner.

[0239] As shown in FIG. 53, the first connection conductor 823A is electrically connected to the first upper electrode 871 of the upper wiring 870. Specifically, the upper surface 823s of the first connection conductor 823A overlaps and is in contact with the first upper electrode 871 of the upper wiring 870 when viewed from the thickness direction z. The second connection conductor 823B is electrically connected to the second upper electrode 872 of the upper wiring 870. Specifically, the upper surface 823s of the second connection conductor 823B overlaps and is in contact with the second upper electrode 872 of the upper wiring 870 when viewed from the thickness direction z. Thus, the upper wiring 870 is electrically connected to the connection conductor 823.

[0240] As shown in FIG. 56, the first connection conductor 823A is composed of a seed layer 823a and a plating layer 823b laminated on each other. The seed layer 823a is composed of a first layer in contact with the upper surface 821bs (the wiring main surface 821s of the main surface wiring 821) of the conductive layer 821b and a second layer in contact with the first layer. The first layer has, for example, Ti as the main component, and the second layer has, for example, Cu as the main component. The thickness of the seed layer 823a (the dimension in the thickness direction z of the seed layer 823a) is about 200 nm or more and 8800 nm or less. The plating layer 823b has Cu as the main component.

[0241] The seed layer 823a has an upper surface 823as and a lower surface 823ar facing opposite sides in the thickness direction z. The upper surface 823as faces the same direction as the substrate main surface 810s, and the lower surface 823ar faces the same direction as the substrate back surface 810r. The lower surface 823ar of the seed layer 823a constitutes the lower surface 823r of the connection conductor 823.

[0242] The plating layer 823b has an upper surface 823bs and a lower surface 823br facing opposite sides in the thickness direction z. The upper surface 823bs faces the same direction as the main surface 810s of the substrate, and the lower surface 823br faces the same direction as the back surface 810r of the substrate. The lower surface 823br of the plating layer 823b is in contact with the upper surface 823as of the seed layer 823a. The upper surface 823bs of the plating layer 823b constitutes the upper surface 823s of the connection conductor 823. Note that the configuration of the second connection conductor 823B is the same as that of the first connection conductor 823A shown in FIG. 56.

[0243] As shown in FIGS. 49 and 52, the first functional element 830 is a flat chip component. The first functional element 830 includes a semiconductor element. In the present embodiment, the first functional element 830 is an integrated circuit (IC) such as a large scale integration (LSI). More specifically, the first functional element 830 is a switching power supply LSI. Note that the first functional element 830 may be a voltage control element such as a low drop out (LDO), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors.

[0244] As shown in FIGS. 49 and 55, the size of the first functional element 830 is smaller than the size of the second functional element 860. Specifically, the dimension of the first functional element 830 in the thickness direction z is smaller than the dimension of the second functional element 860 in the thickness direction z. The dimension of the first functional element 830 in the thickness direction z is 100 μm or more and 300 μm or less. When the first functional element 830 is an LSI, the dimension of the LSI in the thickness direction z is, for example, about 100 μm. The dimension of the first functional element 830 in the first direction x is smaller than the dimension of the second functional element 860 in the first direction x. The dimension of the first functional element 830 in the second direction y is smaller than the dimension of the second functional element 860 in the second direction y.

[0245] When viewed from the thickness direction z, the shape of the first functional element 830 is substantially square. As shown in FIG. 55, the first functional element 830 has an element front surface 830s and an element back surface 830r facing opposite sides in the thickness direction z. The element front surface 830s is the surface on which the constituent members for the function of the first functional element 830 are formed. The element front surface 830s faces the same direction as the substrate back surface 810r of the substrate 810. The element back surface 830r faces the same direction as the substrate front surface 810s of the substrate 810.

[0246] The first functional element 830 has an element substrate 831, a plurality of electrode pads 832, wirings 833, an insulating film 834A, and a protective film 834B. As shown in FIG. 57, the element substrate 831 is formed with recesses 831b in which the electrodes 831a of the element substrate 831 are exposed. A plurality of the electrodes 831a and the recesses 831b are provided respectively.

[0247] The insulating film 834A covers the surface of the element substrate 831 (element front surface 830s). The recesses 831b are formed by the insulating film 834A penetrating in the thickness direction z. In the present embodiment, the insulating film 834A is made of an electrically insulating material, for example, SiO2 (silicon oxide). The insulating film 834A covers a part of the electrode pads 832, and a part of the surface of the electrode pads 832 is exposed as a connection terminal. Note that the insulating film 834A may be formed of SiN (silicon nitride).

[0248] A plurality of wirings 833 are formed on the element front surface 830s so as to be individually connected to the respective electrodes 831a. Each wiring 833 is formed on the surface of the insulating film 834A. Each wiring 833 is also formed in the recesses 831b and thus connected to the respective electrodes 831a. Each wiring 833 is made of, for example, Cu.

[0249] The protective film 834B covers the surface of the insulating film 834A and also covers the surfaces of the respective wirings 833. Further, the protective film 834B covers the peripheral portions of the electrode pads 832. That is, each electrode pad 832 protrudes downward from the protective film 834B. The protective film 834B is made of an electrically insulating material, for example, a polyimide resin.

[0250] Each electrode pad 832 is a terminal for electrically connecting to the main surface wiring 821 and is connected to each wiring 833. Thus, each electrode 831a of the element substrate 831 is electrically connected to the main surface wiring 821 via each electrode pad 832 and each wiring 833.

[0251] Each electrode pad 832 is arranged at a position different from each recess 831b in the direction orthogonal to the thickness direction z (the plane direction of the element main surface 830s). Each electrode pad 832 has a conductive portion 832a and a barrier layer 832b laminated on each other in the thickness direction z. The conductive portion 832a is made of, for example, Cu. The barrier layer 832b is made of a Ni layer. The barrier layer 832b is laminated so as to cover the tip surface of the conductive portion 832a. A solder layer 835 is laminated on the end surface on the side opposite to the end surface on the conductive portion 832a side among both end surfaces in the thickness direction z of the barrier layer 832b. In each electrode pad 832, by providing the barrier layer 832b, penetration of the Cu-made conductive portion 832a into the solder layer 835 can be suppressed. Note that the barrier layer 832b may be composed of a Ni layer, a Pd (palladium) layer, and an Au (gold) layer laminated on each other. Also, the barrier layer 832b may be omitted.

[0252] As shown in FIG. 57, a barrier layer 881 is formed in a portion of the wiring main surface 821s of the main surface wiring 821 that faces the solder layer 835 in the thickness direction z. The barrier layer 881 is made of a Ni layer. By this barrier layer 881, the spreading of the solder layer 835 can be suppressed. Note that the barrier layer 881 may be composed of a Ni layer, a Pd layer, and an Au layer laminated on each other. In this way, the solder layer 835 and the barrier layer 881 constitute a joint portion 880 that joins the main surface wiring 821 and the electrode pad 832 of the first functional element 830.

[0253] As shown in FIG. 55, the first functional element 830 is connected to the main surface wiring 821 via the solder layer 835. The solder layer 835 is made of Su (tin) or an alloy containing Sn. This alloy is, for example, an Sn - Ag based alloy, an Sn - Sb (antimony) based alloy, or the like. In this way, by joining the electrode pad 832 to the main surface wiring 821 via the solder layer 835, the first functional element 830 is mounted on the main surface wiring 821.

[0254] As shown in FIGS. 50, 52, and 54, the external electrode 850 serves as an external connection terminal that connects to a wiring substrate in the electronic component 801A. The external electrode 850 is composed of, for example, a plurality of metal layers laminated on each other. Examples of the metal layer include a Ni layer, a Pd layer, and an Au layer.

[0255] The external electrodes 850 are provided according to the through-wiring 822. More specifically, as shown in FIG. 52, they are provided in proximity to the substrate side surface 811 and external electrodes 850 are provided for each of the four through-wirings 822 that are arranged spaced apart from each other in the first direction x. In this case, the four external electrodes 850 are arranged spaced apart from each other in the first direction x. External electrodes 850 are provided for each of the four through-wirings 822 that are provided in proximity to the substrate side surface 812 and are arranged spaced apart from each other in the first direction x. In this case, the four external electrodes 850 are arranged spaced apart from each other in the first direction x. External electrodes 850 are provided for each of the four through-wirings 822 that are provided in proximity to the substrate side surface 813 and are arranged spaced apart from each other in the second direction y. In this case, the four external electrodes 850 are arranged spaced apart from each other in the second direction y. External electrodes 850 are provided for each of the four through-wirings 822 that are provided in proximity to the substrate side surface 814 and are arranged spaced apart from each other in the second direction y. In this case, the four external electrodes 850 are arranged spaced apart from each other in the second direction y. An external electrode 850 is provided for the through-wiring 822 provided at the center of the substrate back surface 810r in the first direction x and the second direction y. Each external electrode 850 covers the back surface 822r of each through-wiring 822.

[0256] As shown in FIG. 55, the second functional element 860 is an element having a relatively large dimension in the thickness direction z, such as an element such as a resistor, a capacitor, an inductor, a diode, or the like. In the present embodiment, the second functional element 860 is an inductor used in a power supply circuit, a so-called power supply system inductor. In the illustrated example, the second functional element 860 has a configuration in which a winding metal alloy capable of handling a large current is sealed with a sealing resin. The second functional element 860 has a first electrode 861 and a second electrode 862. In the illustrated example, the second functional element 860 is a surface mount type package. The dimension of the second functional element 860 in the first direction x is about 6.6 mm, the dimension of the second functional element 860 in the second direction y is about 7.0 mm, and the dimension of the second functional element 860 in the thickness direction z is about 3.0 mm.

[0257] In addition, when an inductor is used for the second functional element 860, the configuration of the inductor is not limited to this. For example, a wound ferrite or multilayer ferrite inductor may be used. Further, the external shape of the inductor is not limited to the illustrated example, and may be a rectangular flat plate shape or a box shape that appears square when viewed from the thickness direction z.

[0258] As shown in FIGS. 51 and 55, the second functional element 860 is connected to the upper surface wiring 870. More specifically, the first electrode 861 of the second functional element 860 is joined to the first upper surface electrode 871 of the upper surface wiring 870 by solder SD, and the second electrode 862 of the second functional element 860 is joined to the second upper surface electrode 872 of the upper surface wiring 870 by solder SD. Thereby, the second functional element 860 is electrically connected to the first functional element 830. As shown in FIG. 55, the internal electrode 820 and the upper surface wiring 870 constitute a conductive path that electrically connects the first functional element 830 and the second functional element 860. Further, the second functional element 860 is electrically connected to the external electrode 850 via the upper surface wiring 870 and the internal electrode 820.

[0259] In the present embodiment, the electronic component 801A is a power module in which an inductor, which is the second functional element 860, is electrically connected to a switching power supply LSI, which is the first functional element 830. Therefore, the electronic component 801A is applied to a power circuit. In this way, since the switching power supply LSI and the inductor are modularized by the electronic component 801A, the size of the power circuit can be reduced.

[0260] (Method for manufacturing an electronic component) With reference to FIGS. 59 to 78, a method for manufacturing the electronic component 801A according to the seventh embodiment of the present disclosure will be described. In FIGS. 59 to 62, FIG. 64, FIG. 65, FIG. 67, and FIGS. 69 to 73, two adjacent broken lines indicate the range in which one electronic component 801A is formed. The definition of the directions shown in FIGS. 59 to 78 is the same as the definition of the directions shown in FIGS. 49 to 58.

[0261] As shown in FIG. 59, the manufacturing method of the electronic component 801A includes a step of preparing a support substrate 1600. The support substrate 1600 is made of, for example, a single-crystalline intrinsic semiconductor. The support substrate 1600 is made of, for example, a single-crystalline Si material. The support substrate 1600 has an upper surface 1601 and a lower surface 1602 facing opposite sides in the thickness direction z. Note that, as the support substrate 1600, a substrate made of a composite resin material such as an epoxy resin may be used.

[0262] The manufacturing method of the electronic component 801A includes a step of forming a terminal pillar 1622 on the upper surface 1601 of the support substrate 1600. The terminal pillar 1622 is made of, for example, Cu or a Cu alloy and is formed by electrolytic plating.

[0263] More specifically, the terminal pillar 1622 is formed through, for example, a step of forming a seed layer, a step of forming a mask on the seed layer by photolithography, and a step of forming the terminal pillar 1622 in contact with the seed layer. Specifically, for example, a seed layer is formed on the upper surface 1601 of the support substrate 1600 by a sputtering method. Next, the seed layer is covered with, for example, a photosensitive resist layer, and the resist layer is exposed and developed to form a mask having an opening. Next, plating metal is deposited on the surface of the seed layer exposed from the mask by an electrolytic plating method using the seed layer as a conductive path to form the terminal pillar 1622. After the formation of the terminal pillar 1622, the mask is removed. Note that the terminal pillar 1622 may be formed of a columnar material of Cu.

[0264] The manufacturing method of the electronic component 801A includes a step of forming a base material 1610 which is an example of an insulating layer. More specifically, as shown in FIG. 60, a base material 1610 is formed in contact with the upper surface 1601 of the support substrate 1600 and covering the terminal pillar 1622. The base material 1610 is formed so as to cover the upper surface of the terminal pillar 1622. As the material of this base material 1610, the material constituting the substrate 810 shown in FIG. 49 can be used. In this embodiment, as the material of the base material 1610, a synthetic resin mainly composed of an epoxy resin or the like is used. Thus, it can be said that the manufacturing method of the electronic component 801A includes an insulating layer forming step.

[0265] The manufacturing method of the electronic component 801A includes a step of grinding the base material 1610 and the terminal pillar 1622. More specifically, by grinding a part of the base material 1610 and the terminal pillar 1622, the terminal pillar 1622 is exposed on the upper surface 1611 of the base material 1610. In this step, the upper surface 1622s of the terminal pillar 1622 constitutes the main surface 822s of the through-wiring 822. Also in this step, the base material 1610 has an upper surface 1611 constituting an insulating main surface and a lower surface 1612 constituting an insulating back surface. The base material 1610 becomes the substrate 810 shown in FIG. 55. In the grinding of the base material 1610, the base material 1610 is made to have the same thickness as the substrate 810. The terminal pillar 1622 is made to have the same thickness as the through-wiring 822. As shown in FIG. 60, a part of the terminal pillar 1622 (the terminal pillar 1622 disposed between the dashed lines adjacent in the second direction y) forms the through-wiring 822. Thus, it can be said that the manufacturing method of the electronic component 801A includes a step of forming a plurality of through-wirings 822.

[0266] The manufacturing method of the electronic component 801A includes a step of forming a main surface wiring 1621. More specifically, as shown in FIG. 62, the main surface wiring 1621 is formed on the upper surface 1611 of the base material 1610 and the upper surface 1622s of the terminal pillar 1622 (the main surface 822s of the through wiring 822). As shown in FIG. 63, the main surface wiring 1621 includes a metal layer 1621a and a conductive layer 1621b. The main surface wiring 1621 is formed through a step of forming the metal layer 1621a, a step of forming a mask on the metal layer 1621a by photolithography, and a step of forming a conductive layer 1621b in contact with the metal layer 1621a.

[0267] More specifically, first, for example, the metal layer 1621a is formed by a sputtering method. For example, the metal layer 1621a including a Ti layer and a Cu layer is formed by forming a Ti layer on the upper surface 1611 of the base material 1610 and the main surface 822s of the through wiring 822, and then forming a Cu layer in contact with the Ti layer. Next, for example, the metal layer 1621a is covered with a photosensitive resist layer, and the resist layer is exposed and developed to form a mask having an opening. Next, for example, a plating metal is deposited on the surface of the metal layer 1621a exposed from the mask by an electrolytic plating method using the metal layer 1621a as a conductive path to form the conductive layer 1621b. Through these steps, the main surface wiring 1621 is formed. After the formation of the main surface wiring 1621, the mask is removed. Thus, it can be said that the manufacturing method of the electronic component 801A includes a main surface wiring forming step.

[0268] As shown in FIGS. 64 to 66, the manufacturing method of the electronic component 801A includes a step of forming a connection conductor 1623. More specifically, as shown in FIGS. 65 and 66, the connection conductor 1623 is formed on the upper surface 1621s of the main surface wiring 1621.

[0269] The connection conductor 1623 is formed through, for example, a step of forming a seed layer, a step of forming a mask on the seed layer by photolithography, and a step of forming a plating layer in contact with the seed layer.

[0270] Specifically, as shown in FIG. 64, for example, by a sputtering method, a seed layer 1623a is formed on the upper surface 1621s of the main surface wiring 1621 and the upper surface 1611 of the base material 1610. Next, for example, the seed layer 1623a is covered with a photosensitive resist layer, and the resist layer is exposed and developed to form a mask having an opening.

[0271] Next, as shown in FIG. 66, a plating metal is deposited on the surface of the seed layer 1623a exposed from the mask by an electrolytic plating method using the seed layer 1623a as a conductive path to form a plating layer 1623b. Thereby, a connection conductor 1623 composed of a laminate of the seed layer 1623a and the plating layer 1623b is formed. Then, after the formation of the connection conductor 1623, the mask is removed. Note that the connection conductor 1623 may be formed of a columnar material of Cu.

[0272] Next, as shown in FIG. 66, the unnecessary seed layer 1623a is removed. Specifically, the seed layer 1623a other than the portion covered by the plating layer 1623b in the seed layer 1623a is removed. The removal of the unnecessary seed layer 1623a is performed by wet etching using, for example, a mixed solution of H2SO4. Thus, it can be said that the manufacturing method of the electronic component 801A includes a conductor forming step.

[0273] As shown in FIGS. 67 and 68, the manufacturing method of the electronic component 801A includes a step of forming a joint portion 880. More specifically, as shown in FIG. 67, the joint portion 880 is formed on the upper surface 1621s of the main surface wiring 1621. As shown in FIG. 68, the joint portion 880 includes a barrier layer 881 and a solder layer 1682. First, the barrier layer 881 is formed on the upper surface 1621s of the main surface wiring 1621. The barrier layer 881 can be formed, for example, by an electrolytic plating method using the main surface wiring 1621 as a conductive path. Next, an alloy containing Sn as a plating metal is deposited on the upper surface 881s of the barrier layer 881 by an electrolytic plating method to form the solder layer 1682. Thereafter, the surface of the rough solder layer 1682 is smoothed by melting the solder layer 1682 by a reflow process. By this smoothing, the generation of voids when the solder layer 1682 is joined to the solder layer (not shown) of the first functional element 830 can be suppressed. Note that the solder layer 1682 shown in FIGS. 67 and 68 shows the state after the reflow process.

[0274] The manufacturing method of the electronic component 801A includes a step of mounting the first functional element 830. More specifically, as shown in FIG. 69, the first functional element 830 is mounted on the main surface wiring 1621. The mounting of the first functional element 830 is performed by flip chip bonding (FCB).

[0275] Specifically, first, for example, by an electrolytic plating method, an alloy containing Sn as a plating metal is deposited on the barrier layer 832b of the electrode pad 832 of the first functional element 830 to form a solder layer (not shown). This solder layer is made of the same material as the solder layer 1682 of the joint portion 880 (see FIG. 68). Regarding the solder layer of the first functional element 830, the surface is smoothed by a reflow process in the same manner as the solder layer 1682 described above.

[0276] Next, for example, after applying flux to the portion of the joint 880, the first functional element 830 is mounted on the joint 880 using, for example, a flip chip bonder. As a result, the first functional element 830 is temporarily attached to the joint 880. Thereafter, after bringing the solder layer 1682 of the joint 880 and the solder layer of the first functional element 830 into a liquid phase state by a reflow process, the first functional element 830 is connected to the joint 880 by solidifying the solder layer 1682 of the joint 880 and the solder layer of the first functional element 830 by cooling. For this reason, the solder layer 835 shown in FIG. 57 is composed of the solder layer 1682 of the joint 880 and the solder layer of the first functional element 830. Thus, it can be said that the manufacturing method of the electronic component 801A includes a first element mounting step.

[0277] The manufacturing method of the electronic component 801A includes a step of forming a resin layer 1640. More specifically, as shown in FIG. 70, the resin layer 1640 is formed so as to cover the upper surface 1611, the main surface wiring 1621, the connection conductor 1623, and the first functional element 830 of the base material 1610. The resin layer 1640 is a member that becomes the encapsulating resin 840 shown in FIG. 49. The resin layer 1640 is a synthetic resin mainly composed of, for example, an epoxy resin. For example, the resin layer 1640 is formed by transfer molding. Thus, it can be said that the manufacturing method of the electronic component 801A includes a resin layer forming step.

[0278] The manufacturing method of the electronic component 801A includes a step of cutting the resin layer 1640 and the connection conductor 1623 so as to reduce their thicknesses. More specifically, as shown in FIG. 71, for example, by the CMP (Chemical Mechanical Polishing) method using an abrasive (abrasive grains), the resin main surface 1640s of the resin layer 1640 is ground until the connection conductor 1623 is exposed from the resin layer 1640. In this step, the resin main surface 1640s of the resin layer 1640 and the upper surface of the connection conductor 1623 are ground until the dimension in the thickness direction z of the connection conductor 1623 becomes a predetermined dimension. Thereby, the connection conductor 823 is formed. FIG. 71 shows the state after grinding. As shown in FIG. 71, the upper surface 823s of the connection conductor 823 is exposed from the resin main surface 1640s of the resin layer 1640. In this step, the shape of the upper surface 823s of the connection conductor 823 is the same as the shape of the upper surface 823s of the connection conductor 823 shown in FIG. 58. Also, the shape of the resin main surface 1640s of the resin layer 1640 is the same as the shape of the resin main surface 40s of the sealing resin 840 shown in FIG. 58. That is, grinding marks are formed on the resin main surface 1640s by grinding. Therefore, the resin main surface 1640s corresponds to the cut surface in the resin layer 1640. Thus, it can be said that the manufacturing method of the electronic component 801A includes a resin layer cutting step.

[0279] The manufacturing method of the electronic component 801A includes a step of forming the top surface wiring 870 and the insulating film 873. More specifically, as shown in FIG. 72, the top surface wiring 870 is formed on the resin main surface 1640s of the resin layer 1640 and the top surface 823s of the connection conductor 823. This step can also be said to form the top surface wiring 870 on the cut surface of the resin layer 1640. The method of forming the top surface wiring 870 is, for example, the same as the method of forming the main surface wiring 1621. An insulating film 873 is formed on a portion of the resin main surface 1640s of the resin layer 1640 other than the first top surface electrode 871 and the second top surface electrode 872 of the top surface wiring 870. In the step of forming the insulating film 873, for example, a spin coater (rotary coating device) is used to apply the insulating film 873 to the resin main surface 1640s of the resin layer 1640. Note that a film-shaped photosensitive resin material may be attached. Then, patterning is performed by exposing and developing the photosensitive resin material. As a result, the first top surface electrode 871 and the second top surface electrode 872 of the top surface wiring 870 are exposed from the insulating film 873. Thus, it can be said that the manufacturing method of the electronic component 801A includes a top surface wiring forming step and an insulating film forming step.

[0280] The manufacturing method of the electronic component 801A includes a step of removing the support substrate 1600. In the present embodiment, as shown in FIG. 73, the support substrate 1600 is removed by grinding. Note that FIG. 73 is shown with the top and bottom reversed with respect to FIG. 72. As another method of this step, the base material 1610 may be made thicker than the substrate 810 shown in FIG. 55, and in the grinding step of the support substrate 1600, after grinding the support substrate 1600, the base material 1610 and the terminal pillar 1622 may be ground to make the thickness of the base material 1610 equal to the thickness of the substrate 810. Further, a method may be used in which a release film is formed in advance and the support substrate 1600 is removed by a release method.

[0281] The manufacturing method of the electronic component 801A includes a step of cutting the base material 1610 and half-cutting the resin layer 1640. More specifically, as shown in FIG. 74, first, a dicing tape DT is attached to the lower surface of the resin layer 1640. Next, the base material 1610 is cut and a part in the thickness direction z of the resin layer 1640 is cut (half-cut). When cutting the base material 1610 and half-cutting the resin layer 1640 like this, for example, a dicing blade is used to cut from the base material 1610 toward the dicing tape DT along the cutting line (dashed line) shown in FIG. 73. In this way, by half-cutting the resin layer 1640, as shown in FIG. 74, a separation groove 1645 is formed in the resin layer 1640. In this step, the substrate 810, each through-wiring 822, and each main surface wiring 821 are formed by cutting the base material 1610. Thus, it can be said that the manufacturing method of the electronic component 801A includes a cutting step. Also, it can be said that the manufacturing method of the electronic component 801A includes a first cutting step.

[0282] The manufacturing method of the electronic component 801A includes a step of forming the external electrode 850. More specifically, as shown in FIG. 75, the external electrode 850 is formed on the back surface 822r of each through-wiring 822 exposed from the base material 1610. The external electrode 850 is made of a plating metal. For example, the external electrode 850 is formed by depositing a plating metal, such as Ni, Pd, and Au, in this order by electroless plating.

[0283] The manufacturing method of the electronic component 801A includes a step of dividing into individual pieces with the first functional element 830 as one unit. More specifically, as shown in FIG. 76, a dicing blade narrower than the dicing blade that half-cuts the resin layer 1640 cuts into the resin layer 1640 from the separation groove 1645 of the resin layer 1640 to the dicing tape DT, and cuts the resin layer 1640. In this case, the resin layer 1640 is cut along the cutting line (broken line) shown in FIG. 73. Thereby, the sealing resin 840 having the step 845 is formed. The individual piece is an electronic component including the substrate 810, the sealing resin 840, and the first functional element 830. Thus, it can be said that the manufacturing method of the electronic component 801A includes a cutting step. Also, it can be said that the manufacturing method of the electronic component 801A includes a second cutting step.

[0284] The manufacturing method of the electronic component 801A includes a step of mounting the second functional element 860. More specifically, as shown in FIG. 77, solder SD is applied to each of the first upper surface electrode 871 and the second upper surface electrode 872 of the upper surface wiring 870. As a method for forming the solder SD, the solder SD may be formed by depositing an alloy containing Sn as a plating metal on the first upper surface electrode 871 and the second upper surface electrode 872.

[0285] Next, the second functional element 860 is mounted on the solder SD formed on the first upper surface electrode 871 and the second upper surface electrode 872. Thereby, the second functional element 860 is temporarily attached to the first upper surface electrode 871 and the second upper surface electrode 872. Then, after melting the solder SD by a reflow process, the solder SD is solidified by cooling. Thereby, the second functional element 860 is connected to the solder SD. Thus, it can be said that the manufacturing method of the electronic component 801A includes a second element mounting step. Through the above steps, the electronic component 801A can be manufactured.

[0286] (Operation) Next, the operation of this embodiment will be described. Each connection conductor 823 electrically connected to the main surface wiring 821 is electrically connected to an upper surface wiring 870 formed on a resin main surface 840s of a sealing resin 840. That is, the main surface wiring 821 and the upper surface wiring 870 are electrically connected via each connection conductor 823.

[0287] The first functional element 830 is disposed inside the sealing resin 840 so as to be electrically connected to the main surface wiring 821, and the second functional element 860 is disposed on the resin main surface 840s of the sealing resin 840 so as to be electrically connected to the upper surface wiring 870. In this way, the position of the first functional element 830 in the thickness direction z and the position of the second functional element 860 in the thickness direction z are different, and the first functional element 830 and the second functional element 860 are arranged so as to overlap when viewed from the thickness direction z. In this way, in the electronic component 801A of the present embodiment, the first functional element 830 and the second functional element 860 that are electrically connected to each other are not planar mounting (2D mounting) but three-dimensional mounting (3D mounting). As a result, compared with a configuration in which the first functional element 830 and the second functional element 860 are arranged on the same plane in a direction orthogonal to the thickness direction z, the arrangement space of the first functional element 830 and the second functional element 860 in the direction orthogonal to the thickness direction z can be reduced.

[0288] (Effect) According to the present embodiment, the following effects can be obtained. (1-1) The electronic component 801A includes a first functional element 830 arranged to be electrically connected to the main surface wiring 821 formed on the substrate 810, a sealing resin 840 that seals the main surface wiring 821 and the first functional element 830, a second functional element 860 mounted on the resin main surface 840s of the sealing resin 840, and a connection conductor 823 that electrically connects the main surface wiring 821 and the second functional element 860. The connection conductor 823 is exposed from the resin main surface 840s of the sealing resin 840. According to this configuration, since the first functional element 830 and the second functional element 860 are arranged so as to overlap when viewed from the thickness direction z, compared with a configuration in which the first functional element 830 and the second functional element 860 are arranged side by side on the same plane in the direction orthogonal to the thickness direction z, miniaturization of the electronic component 801A in the direction orthogonal to the thickness direction z can be achieved.

[0289] (1-2) The dimension of the second functional element 860 in the thickness direction z is larger than the dimension of the first functional element 830 in the thickness direction z. According to this configuration, even if the dimension of the second functional element 860 arranged outside the sealing resin 840 in the thickness direction z is large, it is not necessary to increase the dimension of the sealing resin 840 in the thickness direction z. In other words, since the dimension of the first functional element 830 sealed by the sealing resin 840 in the thickness direction z is small, the dimension of the sealing resin 840 in the thickness direction z can be reduced. Therefore, in the manufacturing process of the electronic component 801A, since the dimension of the resin layer 1640 in the thickness direction z can be reduced, warping of the base material 1610 caused by the influence of thermal shrinkage of the resin layer 1640 can be reduced.

[0290] (1-3) An upper surface wiring 870 is formed on the resin main surface 840s of the sealing resin 840. The upper surface wiring 870 is electrically connected to the connection conductor 823. According to this configuration, the upper surface wiring 870 can form wiring suitable for mounting the second functional element 860. Therefore, the second functional element 860 can be suitably mounted on the resin main surface 840s.

[0291] (1-4) The dimension of the second functional element 860 in the second direction y is larger than the dimension of the first functional element 830 in the second direction y. According to this configuration, a functional element larger than the first functional element 830 in the second direction y can be mounted on the resin main surface 840s. Therefore, the variety of the second functional elements 860 that can be mounted on the resin main surface 840s increases.

[0292] (1-5) Each main surface wiring 821 has an inner portion 821p that extends inward of the substrate main surface 810s more than each through wiring 822. The first functional element 830 is mounted on the inner portion 821p. According to this configuration, a plurality of through wirings 822 are arranged outward of the substrate main surface 810s more than the first functional element 830. Thereby, a space for changing the pitch in the arrangement direction of the plurality of through wirings 822 can be secured. Therefore, for example, the pitch in the arrangement direction of the plurality of through wirings 822 can be made larger than the pitch of the inner portions 821p in the arrangement direction of the plurality of main surface wirings 821.

[0293] (1-6) The connection conductor 823 is arranged between the first functional element 830 and the through wiring 822 in the direction in which the inner portion 821p of the main surface wiring 821 extends among the inner portions 821p. According to this configuration, the influence due to the deformation of the through wiring 822 is less likely to be transmitted to the connection conductor 823.

[0294] (1-7) The first connection conductor 823A and the second connection conductor 823B are dispersedly arranged on both sides of the first functional element 830 when viewed from the thickness direction z. According to this configuration, the distance between the first upper surface electrode 871 of the upper surface wiring 870 and the first connection conductor 823A, and the distance between the second upper surface electrode 872 of the upper surface wiring 870 and the second connection conductor 823B can be shortened respectively. Therefore, the length of the upper surface wiring 870 can be shortened.

[0295] (1-8) On each of the substrate side surfaces 811 to 814 of the substrate 810, the through-wiring 822 is exposed. According to this configuration, when the electronic component 801A is mounted on the wiring board by soldering, for example, the solder also contacts the surfaces of the through-wiring 822 exposed from the substrate side surfaces 811 to 814 to form a fillet. Thereby, when the electronic component 801A is mounted on the wiring board, the bonding state of the electronic component 801A by the solder can be visually recognized.

[0296] (1-9) On each of the resin side surfaces 841 to 844 of the sealing resin 840, the main surface wiring 821 is exposed. According to this configuration, when the electronic component 801A is mounted on the wiring board by soldering, for example, the solder also contacts the surfaces of the main surface wiring 821 exposed from the resin side surfaces 841 to 844 to form a fillet. Thereby, when the electronic component 801A is mounted on the wiring board, the bonding state of the electronic component 801A by the solder can be visually recognized.

[0297] (1-10) The main surface wiring 821, the through-wiring 822, and the connection conductor 823 are each formed by electrolytic plating. In other words, the internal electrode 820 is formed by electrolytic plating. Also, the external electrodes 850 are each formed by electroless plating. Therefore, the electronic component 801A is wired by plating and does not use a lead frame formed from a metal plate. Wiring by plating can be made thinner than in the case of adopting a lead frame structure. Therefore, the thinning of the electronic component 801A can be realized. In addition, when an LSI is used for the first functional element 830, as the LSI becomes more highly integrated, the number of terminals increases and it is necessary to miniaturize the internal electrodes and the like. However, when using a lead frame, since the metal plate is processed, there is a limit to miniaturization. On the other hand, since the internal electrode 820 of the electronic component 801A of the present embodiment is formed by plating, it can also cope with miniaturization. Therefore, an electronic component having more terminals can be manufactured.

[0298] [Eighth Embodiment] With reference to FIGS. 79 to 100, an electronic component 801B according to the eighth embodiment of the present disclosure will be described. The electronic component 801B of this embodiment mainly differs from the electronic component 801A of the seventh embodiment in that it includes an insulating member 890 instead of a substrate 810 and the configuration of the internal electrodes 820. In the following description, components common to those of the electronic component 801A of the seventh embodiment may be denoted by the same reference numerals, and the description thereof may be omitted.

[0299] (Configuration of the electronic component) As shown in FIG. 79, the insulating member 890 is made of a material having electrical insulation properties, for example, a polyimide resin or a phenol resin. The insulating member 890 is provided on the lower surface side (back surface side) of the electronic component 801B. In this embodiment, the insulating member 890 is disposed below the sealing resin 840 in the thickness direction z. Further, in this embodiment, the shape of the insulating member 890 as viewed from the thickness direction z is the same as the shape of the substrate 810 as viewed from the thickness direction z (see FIGS. 50 and 52). The insulating member 890 has an insulating front surface 890s and an insulating back surface 890r facing opposite sides in the thickness direction z, and four insulating side surfaces 890x provided between the insulating front surface 890s and the insulating back surface 890r in the thickness direction z. Each insulating side surface 890x faces the first direction x or the second direction y.

[0300] The insulating front surface 890s of the insulating member 890 faces the same direction as the element back surface 830r of the first functional element 830 in the thickness direction z and faces the element front surface 830s of the first functional element 830. The insulating back surface 890r of the insulating member 890 faces the same direction as the element front surface 830s of the first functional element 830 in the thickness direction z. A plurality of recesses 891 and through holes 892 are formed in the insulating member 890. In this embodiment, the arrangement pattern of the plurality of recesses 891 is the same as the arrangement pattern of the plurality of recesses 815 (see FIG. 52) of the seventh embodiment. That is, four recesses 891 are provided for each side of the insulating member 890. The shape of each recess 891 as viewed from the thickness direction z is a rectangular concave shape. The shape of each recess 891 as viewed from the thickness direction z is the same as the shape of the recess 815 as viewed from the thickness direction z in the seventh embodiment.

[0301] The through-hole 892 penetrates the substrate 810 in the thickness direction z. The through-hole 892 is provided at the center of the insulating member 890 in the first direction x and the second direction y. The shape of the through-hole 892 viewed from the thickness direction z is rectangular.

[0302] Note that the shape of each recess 891 viewed from the thickness direction z can be arbitrarily changed. The shape of each recess 891 viewed from the thickness direction z may be a concave shape that is square, arc-shaped, etc., or may be a concave shape that is a polygon other than a quadrilateral. Also, the shape of the through-hole 892 viewed from the thickness direction z can be arbitrarily changed. The shape of the through-hole 892 viewed from the thickness direction z may be square, circular, elliptical, etc., or may be a polygon other than a quadrilateral.

[0303] The internal electrode 820 has a plurality (16 in this embodiment) of wiring layers 824 and a plurality (2 in this embodiment) of connection conductors 823. The arrangement pattern of the wiring layers 824 is the same as the arrangement pattern of the main surface wiring 821 and the through-wiring 822 of the seventh embodiment (see FIG. 52). Similar to the seventh embodiment, in this embodiment, the two connection conductors 823 are the first connection conductor 823A and the second connection conductor 823B. The first connection conductor 823A is electrically connected to one of the plurality of wiring layers 824. The second connection conductor 823B is electrically connected to another one of the plurality of wiring layers 824. The arrangement pattern of each of the connection conductors 823A, 823B is the same as the arrangement pattern of each of the connection conductors 823A, 823B of the seventh embodiment.

[0304] As shown in FIG. 79, each wiring layer 824 has a wiring main surface 824s and a wiring back surface 824r facing opposite sides in the thickness direction z. The wiring main surface 824s faces the same direction as the insulating main surface 890s of the insulating member 890, and the wiring back surface 824r faces the same direction as the insulating back surface 890r of the insulating member 890. Each wiring layer 824 is made of a material having electrical conductivity. As the material of each wiring layer 824, for example, Cu, Cu alloy, etc. can be used. In this embodiment, each wiring layer 824 includes a plating layer.

[0305] Each wiring layer 824 includes a main surface wiring 825 and a through wiring 826. In the present embodiment, in each wiring layer 824, the main surface wiring 825 and the through wiring 826 are integrally formed. For this reason, the wiring main surface 824s constitutes the wiring main surface of the main surface wiring 825, and the wiring back surface 824r constitutes the back surface of the main surface wiring 825 and the back surface of the through wiring 826. Since the back surface of the through wiring 826 is exposed from the insulating member 890 in the thickness direction z, it can be said that the wiring back surface 824r constitutes the exposed back surface that is exposed from the insulating back surface 890r of the through wiring 826.

[0306] The main surface wiring 825 is formed on the insulating main surface 890s of the insulating member 890. The through wiring 826 is formed in each recess 891 and each through hole 892 of the insulating member 890. The shape of each through wiring 826 viewed from the thickness direction z is determined according to the shape of each recess 891 and each through hole 892 viewed from the thickness direction z. In the present embodiment, the shape of each through wiring 826 viewed from the thickness direction z is rectangular.

[0307] As shown in FIG. 80, each wiring layer 824 is composed of a seed layer 824a and a plating layer 824b laminated on each other. The seed layer 824a includes, for example, a first layer whose main component is Ti and a second layer whose main component is Cu. The thickness of the seed layer 824a is about 200 nm or more and 8800 nm or less. The main component of the plating layer 824b is Cu. The thickness of the plating layer 824b is about 20 μm or more and 50 μm or less. Note that the thickness of the seed layer 824a and the thickness of the plating layer 824b are not limited to those described above.

[0308] Each of the connection conductors 823A and 823B extends upward along the thickness direction z from the wiring main surface 824s of the wiring layer 824. More specifically, each of the connection conductors 823A and 823B extends upward along the thickness direction z from the upper surface 825s of the main surface wiring 825. The configuration of each of the connection conductors 823A and 823B is the same as that of each of the connection conductors 823A and 823B in the seventh embodiment. Also, the upper surfaces 823s of each of the connection conductors 823A and 823B are exposed from the resin main surface 840s of the sealing resin 840, similar to the seventh embodiment.

[0309] On the resin main surface 840s of the sealing resin 840, an upper surface wiring 870 and an insulating film 873 are formed, similar to the seventh embodiment. A second functional element 860 is connected to the upper surface wiring 870, similar to the seventh embodiment. The mounting position of the second functional element 860 with respect to the resin main surface 840s is the same as the mounting position of the second functional element 860 with respect to the resin main surface 840s in the seventh embodiment. Therefore, the positional relationship between the first functional element 830 and the second functional element 860 is also the same as the positional relationship between the first functional element 830 and the second functional element 860 in the seventh embodiment.

[0310] (Method for manufacturing an electronic component) With reference to FIGS. 81 to 100, a method for manufacturing an electronic component 801B according to the eighth embodiment of the present disclosure will be described. The definitions of the directions shown in these figures are the same as the definitions of the directions shown in FIGS. 49 to 58.

[0311] The method for manufacturing the electronic component 801B includes a step of preparing a support substrate 1700. More specifically, as shown in FIG. 81, a support substrate 1700 having an upper surface 1701 and a lower surface 1702 facing opposite sides in the thickness direction z is prepared. The support substrate 1700 is, for example, a glass substrate or a Si substrate. In the present embodiment, a glass substrate having translucency is used as the support substrate 1700. The thickness of the support substrate 1700 is about 0.5 μm.

[0312] The manufacturing method of the electronic component 801B includes a step of forming a temporary fixing material 1710 on the upper surface 1701 of the support substrate 1700. More specifically, as shown in FIG. 81, the temporary fixing material 1710 is formed so as to cover the entire upper surface 1701 of the support substrate 1700.

[0313] The manufacturing method of the electronic component 801B includes a step of forming a sputtered film 1720 on the temporary fixing material 1710. More specifically, as shown in FIG. 81, the sputtered film 1720 is formed so as to cover the entire surface of the temporary fixing material 1710. The sputtered film 1720 is a metal film whose main component is Ti.

[0314] The manufacturing method of the electronic component 801B includes a step of forming an insulating layer 1790 shown in FIG. 82. This insulating layer 1790 corresponds to the insulating member 890 (see FIG. 79) of the electronic component 801B. More specifically, the insulating layer 1790 is an insulating film made of a photosensitive resin material such as polyimide resin or phenol resin. The insulating layer 1790 has an insulating front surface 1790s and an insulating back surface 1790r facing opposite sides in the thickness direction z. In this step, for example, using a spin coater (rotary coating device), the insulating layer 1790 is applied onto the sputtered film 1720. Note that a film-shaped photosensitive resin material may be attached. Then, patterning is performed by exposing and developing the photosensitive resin material. Thereby, the insulating layer 1790 is formed. Thus, it can be said that the manufacturing method of the electronic component 801B includes an insulating layer forming step.

[0315] The manufacturing method of the electronic component 801B includes a step of forming a wiring layer 1724 shown in FIG. 83. More specifically, as shown in FIG. 84, first, a seed layer 1724a is formed. A part of the seed layer 1724a later corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the seed layer 824a of the wiring layer 824). The seed layer 1724a is formed by a sputtering method. The seed layer 1724a is formed over the entire surfaces of the insulating layer 1790 and the sputtered film 1720 exposed to the insulating layer 1790. The seed layer 1724a of the present embodiment is composed of a Ti layer and a Cu layer laminated on each other. In the step of forming the seed layer 1724a, after forming a Ti layer in contact with the sputtered film 1720 exposed to the insulating layer 1790 and the insulating layer 1790, a Cu layer in contact with the Ti layer is formed.

[0316] Next, as shown in FIG. 85, a plating layer 1724b is formed. FIG. 85 shows the plating layer 1724b formed on a part of the seed layer 1724a. Each wiring layer 1724 shown in FIG. 85 has a laminated structure of the seed layer 1724a and the plating layer 1724b.

[0317] As shown in FIG. 85, the plating layer 1724b corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the plating layer 824b of the wiring layer 824). The plating layer 824b is formed by photolithography patterning and electroplating. In the step of forming the plating layer 1724b, first, a resist layer (not shown) for forming the plating layer 1724b is formed by photolithography. In the formation of this resist layer, a photosensitive resist is applied so as to cover the entire surface of the seed layer 1724a, and patterning is performed by exposing and developing this photosensitive resist. By this patterning, a part of the seed layer 1724a (the part where the plating layer 1724b is to be formed) is exposed. Then, by electroplating using the seed layer 1724a as a conductive path, the plating layer 1724b is formed on the exposed seed layer 1724a. After that, by removing the resist layer, the plating layer 1724b shown in FIG. 85 is formed.

[0318] Next, as shown in FIG. 85, all unnecessary seed layers 1724a that are not covered by the plating layer 1724b are removed. The removal of this unnecessary seed layer 1724a is performed by wet etching. In this wet etching, for example, a mixed solution of H2SO4 and H2O2 (hydrogen peroxide) is used. By the step of removing the unnecessary seed layer 1724a, the insulating layer 1790 is exposed from the portion where the seed layer 1724a has been removed. Also, by removing the unnecessary seed layer 1724a, a wiring layer 1724 composed of the seed layer 1724a and the plating layer 1724b is formed. This wiring layer 1724 corresponds to the wiring layer 824 (see FIG. 61) of the internal electrode 820 of the electronic component 801B. Thus, it can be said that the manufacturing method of the electronic component 801B includes a first internal electrode forming step.

[0319] The manufacturing method of the electronic component 801B includes a step of forming a plurality (two in this embodiment) of connection conductors 1723 shown in FIG. 86. More specifically, as shown in FIG. 87, first, a seed layer 1723a is formed. A part of the seed layer 1723a later corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the seed layer 823a of the connection conductor 823). The formation of the seed layer 1723a is by sputtering. The seed layer 1723a is formed over the entire exposed portion of the wiring layer 1724 and the insulating layer 1790 with respect to the wiring layer 1724. In this embodiment, the seed layer 1723a is composed of a Ti layer and a Cu layer laminated on each other. In the step of forming the seed layer 1723a, a Ti layer in contact with the exposed portion of the wiring layer 1724 among the wiring layer 1724 and the insulating layer 1790 is formed, and then a Cu layer in contact with this Ti layer is formed.

[0320] Next, as shown in FIG. 88, a plating layer 1723b is formed. FIG. 88 shows the plating layer 1723b formed on a part of the seed layer 1723a. Each connection conductor 1723 shown in FIG. 88 has a laminated structure of the seed layer 1723a and the plating layer 1723b.

[0321] As shown in FIG. 88, the plating layer 1723b corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the plating layer 823b of the connection conductor 1723). The formation of the plating layer 1723b is by pattern formation using photolithography and electrolytic plating. In the process of forming the plating layer 1723b, first, a resist layer (not shown) for forming the plating layer 1723b is formed by photolithography. In the formation of this resist layer, a photosensitive resist is applied so as to cover the entire surface of the seed layer 1723a, and patterning is performed by exposing and developing this photosensitive resist. By this patterning, a part of the seed layer 1723a (the part where the plating layer 1723b is to be formed) is exposed. Then, by electrolytic plating using the seed layer 1723a as a conduction path, the plating layer 1723b is formed on the exposed seed layer 1723a.

[0322] The manufacturing method of the electronic component 801B includes a step of removing the unnecessary seed layer 1723a. More specifically, all the unnecessary seed layer 1723a that is not covered by the plating layer 1723b and the joint portion 880 is removed. The removal of this unnecessary seed layer 1723a is performed in the same manner as the removal of the unnecessary seed layer 1724a described above. That is, for example, it is performed by wet etching using a mixed solution of H2SO4 and H2O2. As a result, the wiring layer 1724, the insulating layer 1790, and the sputter film 1720 are exposed from the portion where the seed layer 1723a has been removed. Also, due to the removal of the unnecessary seed layer 1723a, a connection conductor 1723 composed of the seed layer 1723a and the plating layer 1723b is formed. The connection conductor 1723 corresponds to the connection conductor 823 (see FIG. 79) of the internal electrode 820 of the electronic component 801B. Thus, it can be said that the manufacturing method of the electronic component 801B includes a second internal electrode formation step.

[0323] The manufacturing method of the electronic component 801B includes a step of forming the joint portion 880 shown in FIG. 89. The step of forming the joint portion 880 in this embodiment is the same as the step of forming the joint portion 880 in the seventh embodiment.

[0324] The manufacturing method of the electronic component 801B includes a step of mounting the first functional element 830 shown in FIG. 90. The method of mounting the first functional element 830 in the present embodiment is the same as the method of mounting the first functional element 830 in the seventh embodiment. That is, it can be said that the manufacturing method of the electronic component 801B includes a first element mounting step.

[0325] As shown in FIG. 91, the manufacturing method of the electronic component 801B includes a step of forming a resin layer 1740 that covers the first functional element 830. This resin layer 1740 corresponds to the sealing resin 840 (see FIG. 79) of the electronic component 801B. As the method of forming the resin layer 1740 in the present embodiment, a resin layer 1740 that seals all the first functional elements 830 at once is formed. The resin layer 1740 is a synthetic resin mainly composed of, for example, an epoxy resin. For example, the resin layer 1740 is formed by transfer molding. Thus, it can be said that the manufacturing method of the electronic component 801B includes a resin layer forming step.

[0326] The manufacturing method of the electronic component 801B includes a step of cutting the resin layer 1740 and the connection conductor 1723 so as to reduce the thicknesses of the resin layer 1740 and the connection conductor 1723 shown in FIG. 92. The step of cutting the resin layer 1740 and the connection conductor 1723 so as to reduce their thicknesses in the present embodiment is the same as the step of cutting the resin layer 1640 and the connection conductor 1623 (both shown in FIG. 71) so as to reduce their thicknesses in the seventh embodiment. As a result, the connection conductor 823 is formed. The upper surface 823s of the connection conductor 823 is exposed from the resin main surface 1740s, which is the end surface of the resin layer 1740 on the side opposite to the support substrate 1700 in the thickness direction z. Thus, it can be said that the manufacturing method of the electronic component 801B includes a resin layer cutting step.

[0327] The manufacturing method of the electronic component 801B includes a step of forming the top surface wiring 870 and the insulating film 873 shown in FIG. 93. The step of forming the top surface wiring 870 and the insulating film 873 in the present embodiment is the same as the step of forming the top surface wiring 870 and the insulating film 873 in the seventh embodiment. That is, it can be said that the manufacturing method of the electronic component 801B includes a top surface wiring forming step and an insulating film forming step.

[0328] As shown in FIG. 94, the manufacturing method of the electronic component 801B includes a step of peeling the support substrate 1700 (see FIG. 93) from the sputter film 1720. In the step of peeling the support substrate 1700, first, a dicing tape DT is attached to the resin main surface 1740s (insulating film 873) of the resin layer 1740. Then, for example, a laser is irradiated from the lower surface 1702 (see FIG. 93) of the support substrate 1700. At this time, the laser light passes through the support substrate 1700 and is irradiated onto the temporary fixing material 1710 (see FIG. 93). As a result, the adhesion of the temporary fixing material 1710 is reduced, and the support substrate 1700 can be peeled from the sputter film 1720. After the support substrate 1700 is peeled from the sputter film 1720, if the temporary fixing material 1710 remains partially (for example, remains as a residue), the partially remaining temporary fixing material 1710 is removed by, for example, plasma. By the above processing, the support substrate 1700 and the temporary fixing material 1710 are removed.

[0329] Note that the method of peeling the support substrate 1700 is not limited to the method by laser irradiation. For example, air may be blown from a direction (the first direction x or the second direction y) orthogonal to the thickness direction z to peel the support substrate 1700 or the like from the sputter film 1720, or the temporary fixing material 1710 may be softened by heating and then the support substrate 1700 or the like may be peeled from the sputter film 1720. Here, in the case of peeling by laser irradiation, since the laser light needs to be transmitted, the support substrate 1700 needs to be a material having appropriate light transmittance. On the other hand, in the case of peeling by blowing air or peeling by heating, for example, an Si substrate or the like can be used as the support substrate 1700 instead of a glass substrate.

[0330] As shown in FIG. 95, the method for manufacturing the electronic component 801B includes a step of removing the sputter film 1720 (see FIG. 94). By removing this sputter film 1720, the insulating back surface 1790r of the insulating layer 1790 and the back surface 1724r of the wiring layer 1724 are exposed.

[0331] The method for manufacturing the electronic component 801B includes a step of cutting the insulating layer 1790 and the wiring layer 1724 and half-cutting the resin layer 1740. More specifically, as shown in FIG. 96, a dicing tape DT is attached to the lower surface of the resin layer 1740, and the insulating layer 1790 and the wiring layer 1724 are cut while cutting a part of the resin layer 1740 in the thickness direction z (half-cutting). When cutting the insulating layer 1790 and the wiring layer 1724 and half-cutting the resin layer 1740 in this way, for example, a dicing blade is used to cut from the insulating layer 1790 toward the dicing tape DT along the cutting line CL (dashed line) shown in FIG. 95. Note that in the cutting line CL shown in FIG. 95, the width in the short side direction is the thickness (width) of the dicing blade. In this way, by cutting the insulating layer 1790 and the wiring layer 1724, the wiring layer 824 and the insulating member 890 are formed. And by half-cutting the resin layer 1740, a separation groove 1745 is formed in the resin layer 1740. Thus, it can be said that the method for manufacturing the electronic component 801B includes a cutting step. Also, it can be said that the method for manufacturing the electronic component 801B includes a first cutting step.

[0332] As shown in FIG. 97, the method for manufacturing the electronic component 801B includes a step of forming the external electrode 850. The step of forming the external electrode 850 in the present embodiment is the same as the step of forming the external electrode 850 in the seventh embodiment.

[0333] The manufacturing method of the electronic component 801B includes a step of dividing into individual pieces with the first functional element 830 as one unit, as shown in FIG. 98. The step of dividing into individual pieces with the first functional element 830 as one unit in this embodiment is the same as the step of dividing into individual pieces with the first functional element 830 as one unit in the seventh embodiment. That is, it can be said that the manufacturing method of the electronic component 801B includes a cutting step. Also, it can be said that the manufacturing method of the electronic component 801B includes a second cutting step.

[0334] The manufacturing method of the electronic component 801B includes a step of mounting the second functional element 860, as shown in FIGS. 99 and 100. The step of mounting the second functional element 860 in this embodiment is the same as the step of mounting the second functional element 860 in the seventh embodiment. That is, as shown in FIG. 99, after forming solder SD on each of the first top electrode 871 and the second top electrode 872 of the top surface wiring 870, as shown in FIG. 100, the second functional element 860 is fixed to the solder SD. Thus, it can be said that the manufacturing method of the electronic component 801B includes a second functional element mounting step. Through the above steps, the electronic component 801B can be manufactured.

[0335] (Effect) According to this embodiment, in addition to the same effects as the seventh embodiment, the following effects can be obtained. (2-1) The main surface wiring 825 and the through wiring 826 are integrally formed as the wiring layer 824. According to this configuration, the step of forming the wiring layer 824 can be simplified as compared with the case where the main surface wiring 825 and the through wiring 826 are formed individually.

[0336] (2-2) The through wiring 826 and the main surface wiring 825 are formed with the same thickness. According to this configuration, the thickness of the insulating member 890 can be reduced as compared with the case where the through wiring 826 is formed by a terminal pillar.

[0337] [Embodiment 9] Referring to FIGS. 101 to 105, the electronic component 801C according to the ninth embodiment of the present disclosure will be described. Compared with the electronic component 801A of the seventh embodiment, the type and number of the second functional elements 860 and the number and arrangement pattern of the connection conductors 823 are mainly different. In the following description, components common to the electronic component 801A of the seventh embodiment may be denoted by the same reference numerals, and their descriptions may be omitted. Also, in FIG. 101, for convenience, the second functional element 860 is shown by a two-dot chain line.

[0338] As shown in FIG. 101, the electronic component 801C of the present embodiment constitutes an audio output device by the first functional element 830 and a plurality (four in the present embodiment) of second functional elements 860. The audio output device is a device for amplifying a weak audio signal and driving an electroacoustic conversion element 1000 (see FIG. 105) such as a speaker or headphones.

[0339] The plurality of second functional elements 860 are arranged at intervals from each other in the first direction x and the second direction y. In the present embodiment, two second functional elements 860 spaced apart from each other in the first direction x are arranged near the resin side surface 841 of the resin main surface 840s, and two second functional elements 860 spaced apart from each other in the first direction x are arranged near the resin side surface 842 of the resin main surface 840s.

[0340] As shown in FIG. 102, the upper surface wiring 900 formed on the resin main surface 840s has upper surface electrodes 901 for electrically connecting to the second functional element 860. In the present embodiment, four upper surface electrodes 901 are formed for each second functional element 860. These four upper surface electrodes 901 are arranged at intervals from each other in the first direction x and the second direction y. Thus, in the present embodiment, the upper surface wiring 900 has 16 upper surface electrodes 901.

[0341] As shown in FIGS. 102 and 103, 16 connection conductors 823 are provided to electrically connect the 16 upper surface electrodes 901 and the 16 main surface wirings 821 individually. In other words, a connection conductor 823 is connected to each main surface wiring 821.

[0342] As shown in FIG. 102, four connection conductors 823 overlap the upper surface electrodes 901 in the thickness direction z. That is, the connection conductors 823 are in contact with the upper surface electrodes 901. For this reason, the upper surface wiring 900 has 12 connection wirings 902 that individually connect 12 connection conductors 823 and 12 upper surface electrodes 901 that do not overlap each other in the thickness direction z. In this way, the first functional element 830 and the four second functional elements 860 are electrically connected to each other.

[0343] As shown in FIG. 104, connection wirings 902 are formed on the upper surfaces 823s of the connection conductors 823 that do not overlap the upper surface electrodes 901 in the thickness direction z. That is, the connection wirings 902 cover the upper surfaces 823s of the connection conductors 823. These connection wirings 902 are covered with an insulating film 873.

[0344] FIG. 105 shows a simplified circuit configuration of the electronic component 801C as an audio output device. In the present embodiment, each second functional element 860 is electrically connected to an electroacoustic conversion element 1000, and outputs an amplified audio signal to the electroacoustic conversion element 1000. Each second functional element 860 includes a full-bridge type output stage 863 that amplifies and outputs an audio signal, and an LC filter 864 that removes noise from the audio signal output from the output stage 863. In the present embodiment, since each second functional element 860 uses a BTL (Balanced Trans Less) method, it has an output stage 863 and two LC filters 864 connected to the output stage 863. By using this BLT method, an output coupling capacitor becomes unnecessary, and the output of the electroacoustic conversion element 1000 is doubled.

[0345] As shown in FIG. 105, each second functional element 860 is configured to be packaged by encapsulating an output stage 863 and two LC filters 864 with a sealing resin, and has four external electrodes 865. Of the four external electrodes 865, two external electrodes 865 constitute an input electrode electrically connected to the input side of one half-bridge circuit of the output stage 863 and an output electrode electrically connected to the output side of one of the two LC filters 864. The remaining two external electrodes 865 constitute an input electrode electrically connected to the input side of another half-bridge circuit of the output stage 863 and an output electrode electrically connected to the output side of the other LC filter 864 of the two LC filters 864.

[0346] The output stage 863 has a configuration in which a pair of transistors connected in series are connected in parallel. An example of the transistor is an N-type MOSFET. In the output stage 863, two arms in which the source electrode of the upper-arm MOSFET and the drain electrode of the lower-arm MOSFET are connected are connected in parallel.

[0347] Each LC filter 864 has a configuration in which an inductor 864a and a capacitor 864b are connected in series. The first end of the inductor 864a is connected to a node between the source electrode of the upper-arm MOSFET and the drain electrode of the lower-arm MOSFET. The second end of the inductor 864a is connected to the first end of the capacitor 864b. The second end of the capacitor 864b is grounded. Also, the second end of the inductor 864a and the first end of the capacitor 864b are connected to the electroacoustic conversion element 1000 via the external electrode 865.

[0348] The first functional element 830 is a control circuit element that controls each second functional element 860 and is configured by, for example, an LSI. The first functional element 830 controls the on / off switching of each MOSFET in the output stage 863 of each second functional element 860. The first functional element 830 includes an upper arm drive circuit that controls the switching of the MOSFET in the upper arm, a lower arm drive circuit that controls the switching of the MOSFET in the lower arm, and a signal generation circuit that outputs a PWM signal for controlling each MOSFET with respect to the upper arm drive circuit and the lower arm drive circuit. Thus, it can be said that the electronic component 801C of the present embodiment is an audio output device including a class D amplifier circuit.

[0349] The operation of the present embodiment will be described. Since the second functional element 860 is not encapsulated by the encapsulating resin 840 like the first functional element 830, in other words, since the second functional element 860 is mounted on the resin main surface 840s which is outside the encapsulating resin 840, the number of second functional elements 860 mounted on the resin main surface 840s can be easily changed. Therefore, the number of second functional elements 860 mounted on the resin main surface 840s can be adjusted according to the number of electroacoustic conversion elements 1000 electrically connected to the electronic component 801C.

[0350] According to the present embodiment, in addition to the effects of the seventh embodiment, the following effects can be obtained. (3-1) The second functional element 860 has a transistor as the output stage 863. According to this configuration, since the second functional element 860 is provided outside the encapsulating resin 840, the heat generated by driving the transistor is likely to be dissipated to the outside of the electronic component 801C. Therefore, the heat of the transistor is less likely to interfere with the heat generated by driving the first functional element 830, and the occurrence of heat concentration due to the transistor and the first functional element 830 can be suppressed.

[0351] In addition, since the output stage 863 is included in the second functional element 860 and wiring for a transistor through which a large current flows is provided within the second functional element 860, the current supplied from the first functional element 830 to the output stage 863 of the second functional element 860 is reduced. Therefore, it is possible to reduce the EMI noise in the internal electrode 820 that connects the first functional element 830 and the second functional element 860.

[0352] [Modification Example] Each of the above embodiments is an exemplification of a form that an electronic component and a method for manufacturing an electronic component according to the present disclosure can take, and is not intended to limit that form. The electronic component and the method for manufacturing an electronic component according to the present disclosure can take a form different from the forms exemplified in the above embodiments. One example is a form in which a part of the configuration of each of the above embodiments is replaced, changed, or omitted, or a form in which a new configuration is added to each of the above embodiments. The following modification examples can be combined with each other as long as no technical contradiction occurs. For the sake of convenience of explanation, in the following modification examples, the seventh embodiment is basically used for explanation, but it can also be applied to other embodiments as long as no technical contradiction occurs.

[0353] · In the seventh and ninth embodiments, the configuration of the main surface wiring 821 can be arbitrarily changed. In one example, the main surface wiring 821 may have a laminated structure of a seed layer 824a and a plating layer 824b like the wiring layer 824 of the eighth embodiment. Note that the wiring layer 824 of the eighth embodiment may have a laminated structure of a metal layer 821a and a conductive layer 821b like the main surface wiring 821 of the seventh embodiment.

[0354] · In the seventh and ninth embodiments, the main surface wiring 821 and the through wiring 822 may be integrally formed like the main surface wiring 825 and the through wiring 826 of the eighth embodiment. · In the eighth embodiment, the main surface wiring 825 and the through wiring 826 may be separately formed like the main surface wiring 821 and the through wiring 822 of the seventh embodiment.

[0355] · In the seventh and ninth embodiments, the width dimension of the main surface wiring 821 (the dimension in the direction orthogonal to the direction in which the main surface wiring 821 extends as viewed from the thickness direction z) and the width dimension of the through wiring 822 (the dimension in the direction orthogonal to the direction in which the through wiring 822 extends as viewed from the thickness direction z) can each be arbitrarily changed. In one example, the width dimension of the main surface wiring 821 may be larger than the width dimension of the through wiring 822. Also, the width dimension of the main surface wiring 821 may be smaller than the width dimension of the through wiring 822.

[0356] · In the ninth embodiment, the electronic component 801C may include the insulating member 890 of the electronic component 801B instead of the substrate 810. In this case, a wiring layer 824 is used instead of the main surface wiring 821 and the through wiring 822.

[0357] · In the ninth embodiment, the configuration of the first functional element 830 and the configuration of the second functional element 860 can each be arbitrarily changed. In one example, as shown in FIG. 106, the first functional element 830 may have the output stage 863 of each second functional element 860 of the ninth embodiment. The first functional element 830 has a control circuit 836 that controls the output stage 863 of each second functional element 860. The control circuit 836 is composed of, for example, an LSI. Since the first functional element 830 has the output stage 863, the output stage 863 is omitted from each second functional element 860. Each second functional element 860 has an LC filter 864.

[0358] Here, since the electronic component 801C conducts the first functional element 830 and the second functional element 860 through the internal electrode 820 and the upper surface wiring 870, compared with the configuration in which the second functional element 860 is arranged separated from the encapsulating resin 840 of the electronic component 801C, the conductive path between the first functional element 830 and the second functional element 860 becomes shorter. Therefore, as shown in FIG. 106, since the first functional element 830 has the output stage 863, even if a large current flows from the output stage 863 of the first functional element 830 to the second functional element 860, the conductive path between the first functional element 830 and the second functional element 860 is short, so an increase in EMI noise can be suppressed.

[0359] · In each embodiment, the shapes of the electronic components 801A, 801B, and 801C may be appropriately changed. In one example, the electronic component 801A has a configuration in which the step 845 is omitted from the encapsulating resin 840. That is, the encapsulating resin 840 is not partitioned into a first resin portion 846 and a second resin portion 847. In such a manufacturing method of the electronic component 801A, instead of the steps of cutting the base material 1610 and half-cutting the resin layer 1640, a singulation step is performed. That is, after the singulation step, a step of forming the external electrodes 850 is performed. Note that the step 845 may be omitted from the electronic component 801B of the eighth embodiment and the electronic component 801C of the ninth embodiment.

[0360] · In the seventh and ninth embodiments, when viewed from the thickness direction z, the shape of the back surface 822r of the through-wiring 822 exposed from the substrate 810 can be arbitrarily changed. The shape of the back surface 822r of the through-wirings 822 arranged at intervals in the first direction x when viewed from the thickness direction z may be a rectangular shape in which the second direction y is the long side and the first direction x is the short side. The shape of the back surface 822r of the through-wirings 822 arranged at intervals in the second direction y when viewed from the thickness direction z may be a rectangular shape in which the first direction x is the long side and the second direction y is the short side. Note that the shape of the back surface 822r of the through-wiring 822 when viewed from the thickness direction z is not limited to a rectangular shape, and may be a circular shape, an elliptical shape, or the like.

[0361] · In the eighth embodiment, when viewed from the thickness direction z, the shape of the back surface 826r of the through-wiring 826 exposed from the insulating member 890 can be arbitrarily changed. The shape of the back surface 826r of the through-wirings 826 arranged at intervals in the first direction x when viewed from the thickness direction z may be a rectangular shape in which the second direction y is the long side and the first direction x is the short side. The shape of the back surface 826r of the through-wirings 826 arranged at intervals in the second direction y when viewed from the thickness direction z may be a rectangular shape in which the first direction x is the long side and the second direction y is the short side. Note that the shape of the back surface 826r of the through-wiring 826 when viewed from the thickness direction z is not limited to a rectangular shape, and may be a circular shape, an elliptical shape, or the like.

[0362] · In each embodiment, the shape of the through holes 816 and 892 as viewed from the thickness direction z and the shape of the through wirings 822 and 826 arranged in the through holes 816 and 892 (the shape of the external electrodes 850 as viewed from the thickness direction z) can each be arbitrarily changed. In one example, as shown in FIG. 107, the shape of the through hole 816 as viewed from the thickness direction z and the shape of the through wiring 822 arranged in the through hole 816 (the shape of the external electrode 850 as viewed from the thickness direction z) are each square. In the illustrated example, the dimension in the second direction y of the through hole 816 and the dimension in the second direction y of the through wiring 822 arranged in the through hole 816 (the dimension in the second direction y of the external electrode 850) are larger than the dimension in the second direction y of the through hole 816 and the dimension in the second direction y of the through wiring 822 arranged in the through hole 816 (the dimension in the second direction y of the external electrode 850) in the seventh embodiment. According to this configuration, heat dissipation from the first functional element 830 to the outside of the electronic component 801A becomes easier.

[0363] · In each embodiment, the through wirings 822 and 826 arranged in the through holes 816 and 892 may not be electrically connected to the electrode pads 832 of the first functional element 830 via the main surface wiring 821. In this case, the external electrodes 850 covering the through wirings 822 and 826 arranged in the through holes 816 and 892 may be omitted.

[0364] · In each embodiment, the through holes 816 and 892 and the through wirings 822 and 826 arranged in the through holes 816 and 892 may be omitted. Along with this, the external electrodes 850 covering the through wirings 822 and 826 arranged in the through holes 816 and 892 are also omitted.

[0365] · In each embodiment, the internal electrodes 820 are formed by electrolytic plating, but it is not limited thereto. For example, the main surface wiring 821 of the internal electrode 820 may be formed by a lead frame, and the connection conductor 823 may be formed by a metal post. In this case, the connection conductor 823 may be joined to the wiring main surface 821s of the main surface wiring 821 by a conductive bonding material, or may be joined to the main surface wiring 821 by welding such as ultrasonic welding.

[0366] ·In each embodiment, the external electrode 850 covered the back surfaces 822r and 826r of the through-wiring 822 and 826, but it is not limited thereto. For example, in the seventh and ninth embodiments, the external electrode 850 may be configured to also cover the exposed side surface 822xa that is exposed from the substrate side surfaces 811 to 814 of the substrate 810 among the side surfaces 822x of the through-wiring 822. Further, the external electrode 850 may be configured to also cover the wiring side surface 821xa that is exposed from the resin side surfaces 841 to 844 of the sealing resin 840 among the main surface wiring 821. Also, in the eighth embodiment, the external electrode 850 may be configured to also cover the side surface that is exposed from the insulating side surface 890x of the insulating member 890 among the side surfaces of the through-wiring 826. Further, the external electrode 850 may be configured to also cover the side surface that is exposed from the resin side surfaces 841 to 844 of the sealing resin 840 among the main surface wiring 825.

[0367] ·In the seventh and ninth embodiments, the arrangement position of the connection conductor 823 with respect to the main surface wiring 821 can be arbitrarily changed. In one example, the connection conductor 823 is arranged at a portion of the main surface wiring 821 that overlaps with the through-wiring 822 in the thickness direction z.

[0368] ·In the eighth embodiment, the arrangement position of the connection conductor 823 with respect to the wiring layer 824 can be arbitrarily changed. In one example, the first connection conductor 823A is connected to the through-wiring 826 among the wiring layer 824. The second connection conductor 823B is connected to the through-wiring 826 among the wiring layer 824.

[0369] ·In the seventh and eighth embodiments, the arrangement relationship between the first connection conductor 823A and the second connection conductor 823B and the first functional element 830 can be arbitrarily changed. In one example, the first connection conductor 823A and the second connection conductor 823B may be arranged closer to one side in the second direction y with respect to the first functional element 830, respectively. Also, the first connection conductor 823A and the second connection conductor 823B may be arranged dispersedly with respect to the first functional element 830 in the first direction x. Also, the first connection conductor 823A and the second connection conductor 823B may be arranged closer to one side in the first direction x with respect to the first functional element 830, respectively.

[0370] · In each embodiment, the dimensions of the connection conductor 823 in the first direction x and the second direction y can be arbitrarily changed. In one example, in the seventh embodiment, the dimension of the first connection conductor 823A in the first direction x is larger than the dimension of the main surface wiring 821 extending in the second direction y in the first direction x. Also, the dimension of the second connection conductor 823B in the first direction x is larger than the dimension of the main surface wiring 821 extending in the second direction y in the first direction x.

[0371] · In each embodiment, the numbers of the main surface wiring 821, the through wiring 822, and the connection conductor 823 can be arbitrarily changed. The main surface wiring 821, the through wiring 822, and the connection conductor 823 may be in any numbers as long as the first functional element 830 and the second functional element 860 can be electrically connected. For this reason, for example, the main surface wiring 821, the through wiring 822, and the connection conductor 823 may each be one.

[0372] · In each embodiment, the configuration of the terminals of the first functional element 830 can be arbitrarily changed. In one example, as shown in FIG. 108, a configuration may be adopted in which the wiring 833 is omitted and the electrode pad 832 is provided in the recess 831b of the element substrate 831. In this case, the electrode pad 832 is directly connected to the electrode 831a.

[0373] · In each embodiment, the main surface wiring 821 and the first functional element 830 are electrically connected by flip chip bonding, but it is not limited thereto. For example, the main surface wiring 821 and the first functional element 830 may be electrically connected by a wire formed by wire bonding.

[0374] ·In each embodiment, the main surface wiring 821 extended along the first direction x or the second direction y, but it is not limited thereto. For example, as shown in FIG. 109, in the electronic component 801A, the pitch of the through wirings 822 (external electrodes 850) arranged in the first direction x is larger than the pitch of the electrode pads 832 arranged in the first direction x, and the pitch of the through wirings 822 (external electrodes 850) arranged in the second direction y is larger than the pitch of the electrode pads 832 arranged in the second direction y. In this case, as shown in FIG. 110, when viewed from the thickness direction z, the first connection conductor 823A and the second connection conductor 823B do not overlap with the first upper surface electrode 871 and the second upper surface electrode 872 of the upper surface wiring 870. Therefore, in the illustrated example, the upper surface wiring 870 includes a connection wiring 874 that connects the first upper surface electrode 871 and the first connection conductor 823A, and a connection wiring 874 that connects the second upper surface electrode 872 and the second connection conductor 823B. In the illustrated example, the first upper surface electrode 871 and the connection wiring 874 are integrally formed, and the second upper surface electrode 872 and the connection wiring 875 are integrally formed. The connection wiring 874 is provided so as to cover the upper surface 823s of the first connection conductor 823A. The connection wiring 875 is provided so as to cover the upper surface 823s of the second connection conductor 823B. Note that the electronic component 801B of the eighth embodiment can be similarly modified.

[0375] ·In each embodiment, the main surface wiring 821 may not have an inner portion 821p. In this case, the connection conductor 823 is connected to a portion of the main surface wiring 821 that overlaps the through wiring 822 in the thickness direction z.

[0376] ·In each embodiment, the upper surface wiring 870 and the second functional element 860 are electrically connected by the solder SD, but it is not limited thereto. For example, the upper surface wiring 870 and the second functional element 860 may be electrically connected by a wire formed by wire bonding.

[0377] ·In each embodiment, the top surface wirings 870 and 900 may be omitted from the electronic components 801A to 801C. In this case, the connection conductor 823 and the second functional element 860 are directly electrically connected. In one example, the top surface 823s of the first connection conductor 823A exposed from the resin main surface 840s and the first electrode 861 of the second functional element 860 are connected by solder SD, and the top surface 823s of the second connection conductor 823B exposed from the resin main surface 840s and the second electrode 862 of the second functional element 860 are connected by solder SD.

[0378] ·In each embodiment, the insulating film 873 may be omitted from the electronic components 801A to 801C. · In each embodiment, the relationship between the first functional element 830 and the second functional element 860 can be arbitrarily changed. In one example, the second functional element 860 may be a driving element, and the first functional element 830 may be a control element that controls the driving of the second functional element 860. Also, the second functional element 860 may be an optical element, and the first functional element 830 may be a control element that controls the light emission mode of the second functional element 860. For example, a light-emitting diode may be used as the optical element. In this case, the first functional element 830 as the control element controls the supply of power to the optical element (the second functional element 860). In one example, as shown in FIG. 111, the second functional element 860 includes a substrate 910 having a substrate front surface 910s and a substrate back surface 910r facing opposite sides in the thickness direction z, a light-emitting diode 920 mounted on the substrate front surface 910s, and a light-transmissive encapsulating resin 930 that encapsulates the light-emitting diode 920. The substrate 910 is formed in a rectangular flat plate shape in which the second direction y is the long side direction and the first direction x is the short side direction. At both ends of the substrate 910 in the second direction y, a first electrode 911 and a second electrode 912 are provided. The first electrode 911 constitutes an anode electrode, and the second electrode 912 constitutes a cathode electrode. The first electrode 911 is connected to the first upper surface electrode 871, and the second electrode 912 is connected to the second upper surface electrode 872. Thereby, the light-emitting diode 920 and the LSI as the first functional element 830 are electrically connected. Also, a VCSEL (Vertical Cavity Surface Emitting LASER) may be used as the optical element.

[0379] · In each embodiment, the electronic components 801A, 801B, 801C may include a plurality of first functional elements 830. In this case, the types (LSIs, ICs, etc.) of the plurality of first functional elements 830 may be different from each other.

[0380] · In the seventh and eighth embodiments, the size of the second functional element 860 can be arbitrarily changed. In one example, the size of the second functional element 860 may be smaller than the size of the first functional element 830. Also, in the seventh and eighth embodiments, a plurality of second functional elements 860 may be mounted on the resin front surface 840s.

[0381] · In each embodiment, the second functional element may be omitted from the electronic components 801A, 801B, and 801C. That is, the electronic components 801A, 801B, and 801C include a substrate 810 (insulating member 890), main surface wirings 821 (825), a first functional element 830 that is electrically connected to the main surface wirings 821 (825) and is disposed on the side opposite to the substrate 810 (insulating member 890) with respect to the main surface wirings 821 (825) in the thickness direction z, a connection conductor 823 that is electrically connected to the main surface wirings 821 (825) and extends toward the side opposite to the substrate 810 (insulating member 890) in the thickness direction z, a through wiring 822 (826) that is electrically connected to the main surface wirings 821 (825) and extends toward the side opposite to the first functional element 830 in the thickness direction z, and a sealing resin 840 that seals the main surface wirings 821 (825), the first functional element 830, and the connection conductor 823. In this case, the connection conductor 823 is exposed from the resin main surface 840s of the sealing resin 840 so as to be electrically connectable to the second functional element 860. Further, the electronic components 801A, 801B, and 801C may include an upper surface wiring 870 on the resin main surface 840s of the sealing resin 840.

[0382] In one example, as shown in FIG. 112, the electronic component 801A does not include the second functional element 860. An upper surface wiring 870 is formed on the resin main surface 840s of the sealing resin 840. According to this configuration, the type of the second functional element 860 can be appropriately changed according to the circuit to which the electronic component 801A is applied. Further, after the electronic component 801A is mounted on a wiring board (not shown), an appropriate type of the second functional element 860 can be mounted on the upper surface wiring 870 according to the circuit of the wiring board. Note that the electronic components 801B and 801C can be changed in the same manner.

[0383] The manufacturing method of the electronic components 801A and 801C without such a second functional element 860 is the same as the manufacturing method of the electronic component 801A in the seventh embodiment from the step of forming the terminal pillar 1622 on the upper surface 1601 of the support substrate 1600 in FIG. 59 to the step of dividing the first functional element 830 in FIG. 76 into individual pieces with one unit. That is, the manufacturing method of the electronic components 801A and 801C without the second functional element 860 includes a step of forming a plurality of through wirings 822, an insulating layer forming step of forming an insulating layer (base material 1610), a main surface wiring forming step of forming the main surface wiring 1621, a conductor forming step of forming the connection conductor 1623, a first element mounting step of mounting the first functional element 830, a resin layer forming step of forming the resin layer 1640, and a cutting step of cutting the resin layer 1640 and the like.

[0384] Also, the manufacturing method of the electronic component 801B without the second functional element 860 is the same as the manufacturing method of the electronic component 801B in the eighth embodiment from the step of preparing the support substrate 1700 in FIG. 81 to the step of dividing the first functional element 830 in FIG. 98 into individual pieces with one unit. That is, the manufacturing method of the electronic component 801B without the second functional element 860 includes an insulating layer forming step of forming the insulating layer 1790, a first internal electrode forming step of forming a wiring layer 1724 composed of a main surface wiring and a through wiring, a second internal electrode forming step of forming the connection conductor 1723, a first element mounting step of mounting the first functional element 830, a resin layer forming step of forming the resin layer 1740, and a cutting step of cutting the resin layer 1740 and the like.

[0385] (Supplementary Note) The technical ideas understood from the above embodiments and the above modification examples are described below. (Supplementary Note 1-1) A substrate having a substrate main surface and a substrate back surface facing opposite sides to each other, A wiring portion having a conductive layer formed on the substrate main surface, A joint portion having a first plating layer formed on the upper surface of the wiring portion and a first solder layer formed on the upper surface of the first plating layer, A semiconductor device having an element main surface facing the main surface of the substrate, an element electrode formed on the element main surface, and a second solder layer formed on the lower surface of the element electrode and joined to the first solder layer. A sealing resin covering the semiconductor device. Comprising: The joint portion is larger than the element electrode when viewed from the thickness direction perpendicular to the main surface of the substrate. Semiconductor device.

[0386] (Supplementary Note 1-2) The semiconductor device according to Supplementary Note 1-1, wherein the aspect ratio of the first solder layer in a cross section perpendicular to the main surface of the substrate is 40 or more and 80 or less.

[0387] (Supplementary Note 1-3) The semiconductor device according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the distance from the element electrode to the end of the joint portion is 4 μm or more and 10 μm or less.

[0388] (Supplementary Note 1-4) The semiconductor device according to any one of Supplementary Notes 1-1 to 1-3, wherein the distance between the end of the conductive layer and the end of the joint portion is 1 μm or less.

[0389] (Supplementary Note 1-5) The element electrode and the second solder layer are respectively arranged at both ends of the mounting surface along a first direction parallel to the mounting surface. The wiring portion is formed to extend outward from the semiconductor device. The semiconductor device according to any one of Supplementary Notes 1-1 to 1-4.

[0390] (Supplementary Note 1-6) The semiconductor device according to Supplementary Note 1-5, wherein the distance from the element electrode to the end of the joint portion has a larger second distance in the direction toward the outside of the semiconductor device than a first distance in the direction toward the inside of the semiconductor device.

[0391] (Supplementary Note 1-7) The semiconductor device according to any one of Appendices 1-1 to 1-6, wherein the thickness of the solder layer is equal to or less than the thickness of the first plating layer.

[0392] (Appendix 1-8) The semiconductor device according to any one of Appendices 1-1 to 1-7, wherein the thickness of the first solder layer is 1 μm or more and 5 μm or less, and the thickness of the first plating layer is 3 μm or more and 5 μm or less.

[0393] (Appendix 1-9) The semiconductor device according to any one of Appendices 1-1 to 1-8, wherein the thickness of the conductive layer is 15 μm or more and 20 μm or less.

[0394] (Appendix 1-10) The semiconductor device according to any one of Appendices 1-1 to 1-9, wherein the thickness of the solder layer composed of the first solder layer and the second solder layer is 10 μm or more and 15 μm or less.

[0395] (Appendix 1-11) The semiconductor device according to any one of Appendices 1-1 to 1-10, wherein the conductive layer is made of Cu and the first plating layer is made of Ni.

[0396] (Appendix 1-12) The semiconductor device according to any one of Appendices 1-1 to 1-11, wherein the element electrode has a second plating layer, and the second solder layer is formed on the lower surface of the second plating layer.

[0397] (Appendix 1-13) The semiconductor device according to Appendix 1-12, wherein the second plating layer is made of Ni. (Appendix 1-14) The semiconductor device according to any one of Appendices 1-1 to 1-13, further comprising a metal layer formed on the lower surface of the conductive layer.

[0398] (Appendix 1-15) The semiconductor device according to Appendix 1-14, wherein the metal layer contains Ti. (Appendix 1-16) The substrate is made of resin, The wiring portion includes a main surface wiring including the conductive layer, and a through wiring that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the substrate in the thickness direction The semiconductor device according to any one of Appendices 1-1 to 1-15 having the above.

[0399] (Appendix 1-17) The semiconductor device according to Appendix 1-16, having an external connection terminal that covers the through wiring exposed on the back surface of the substrate.

[0400] (Appendix 1-18) The semiconductor device according to Appendix 1-17, wherein the main surface wiring and the through wiring are exposed on the side surface of the substrate.

[0401] (Appendix 1-19) The semiconductor device according to Appendix 1-18, wherein the external connection terminal covers the main surface wiring and the through wiring exposed on the side surface of the substrate.

[0402] (Appendix 1-20) The wiring portion has a columnar wiring provided on the side opposite to the through wiring with respect to the main surface wiring, The columnar wiring extends in the thickness direction and has a side surface exposed from the resin side surface The semiconductor device according to Appendix 1-16.

[0403] (Appendix 1-21) The sealing resin has a first resin portion on the side of the substrate and a second resin portion on the side of the upper surface of the resin. When viewed from the thickness direction, the second resin portion is larger than the first resin portion. The semiconductor device according to Appendix 1-20.

[0404] (Appendix 1-22) The semiconductor device according to Appendix 1-20 or Appendix 1-21, having an external connection terminal that covers the wiring portion exposed from the substrate and the sealing resin.

[0405] (Appendix 1-23) The substrate is made of resin, The wiring portion includes a main surface wiring including the conductive layer, and a through-wiring that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the encapsulating resin in the thickness direction. The semiconductor device according to any one of Appendices 1-1 to 1-15 having the above.

[0406] (Appendix 1-24) The semiconductor device according to Appendix 1-23, having an external connection terminal that covers the through-wiring exposed on the upper surface of the encapsulating resin.

[0407] (Appendix 1-25) The substrate is made of a semiconductor material, The wiring portion includes a main surface wiring including the conductive layer, and a through-wiring that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the substrate in the thickness direction. The semiconductor device according to any one of Appendices 1-1 to 1-15 having the above.

[0408] (Appendix 1-26) The semiconductor device according to Appendix 1-25, comprising a first insulating layer interposed between the substrate main surface and the conductive layer, and a second insulating layer interposed between the inner wall of the through-hole in which the through-wiring is disposed and the through-wiring.

[0409] (Appendix 1-27) The through-wiring has an upper surface facing the side of the conductive layer, and the upper surface is concave toward the inside of the through-wiring. The semiconductor device according to Appendix 1-25 or Appendix 1-26.

[0410] (Appendix 1-28) The semiconductor device according to any one of Appendices 1-23 to 1-27, having an external connection terminal that covers the through-wiring exposed on the back surface of the substrate.

[0411] (Appendix 2-1) A first layer having a first main surface and a first back surface facing opposite sides in the thickness direction, a second back surface in contact with the first main surface, and a second layer having a second main surface facing the opposite side of the second back surface in the thickness direction, and a sealing resin including the second layer; A wiring in contact with the first main surface and partially covered by the second layer; A semiconductor device having a lower surface facing the first main surface and a plurality of pads provided on the lower surface, wherein at least one of the plurality of pads is joined to the wiring and covered by the second layer.

[0412] (Appendix 2-2) The semiconductor device according to Appendix 2-1, wherein the distance between the first main surface and the first back surface is smaller than the distance between the second main surface and the second back surface.

[0413] (Appendix 2-3) The semiconductor device according to Appendix 2-2, wherein a filler containing an inorganic compound is mixed in the first layer.

[0414] (Appendix 2-4) The semiconductor device further includes a plurality of connection wirings connected to the wiring, Each of the plurality of connection wirings reaches the first back surface from the wiring and a part thereof is covered by the first layer, The semiconductor device according to Appendix 2-2 or Appendix 2-3, wherein each of the plurality of connection wirings has a bottom surface exposed at the first back surface.

[0415] (Appendix 2-5) The semiconductor device further includes a plurality of terminals, The semiconductor device according to Appendix 2-4, wherein the plurality of terminals individually cover the bottom surfaces of the plurality of connection wirings.

[0416] (Appendix 2-6) The semiconductor device according to Appendix 2-5, wherein each of the plurality of terminals includes a plurality of metal layers laminated in the thickness direction.

[0417] (Appendix 2-7) The semiconductor device according to Supplementary Note 2-6, wherein the composition of the plurality of metal layers includes nickel and gold.

[0418] (Supplementary Note 2-8) The semiconductor device according to Supplementary Note 2-5, wherein each of the plurality of terminals includes a solder ball. (Supplementary Note 2-9) The first layer is oriented in a direction orthogonal to the thickness direction and has side surfaces connecting to the first main surface and the first back surface. The semiconductor device according to Supplementary Note 2-6 or Supplementary Note 2-7, wherein each of the plurality of connection wirings has an end surface exposed on the side surface.

[0419] (Supplementary Note 2-10) Each of the plurality of terminals has a bottom portion and side portions connected to the bottom portion. The bottom portion covers the bottom surface of any one of the plurality of connection wirings. The semiconductor device according to Supplementary Note 2-9, wherein the side portions cover the end surfaces of any one of the plurality of connection wirings.

[0420] (Supplementary Note 2-11) Further comprising a heat sink. The heat sink is embedded in the first layer and includes a portion in contact with the second back surface. The semiconductor device according to Supplementary Note 2-6, wherein at least a part of the heat sink overlaps the semiconductor element when viewed along the thickness direction.

[0421] (Supplementary Note 2-12) The heat sink has a base portion embedded in the first layer and a covering portion laminated on the base portion and exposed on the first back surface. The thickness of the base portion is equal to the distance between the first main surface and the first back surface. The semiconductor device according to Supplementary Note 2-11, wherein the covering portion includes the plurality of metal layers.

[0422] (Supplementary Note 2-13) The heat sink has a bump portion protruding from the base portion toward the lower surface in the thickness direction. The semiconductor device according to appended note 12, wherein any one of the plurality of pads is joined to the bump portion.

[0423] (Appended note 2-14) The semiconductor device further includes a plurality of first connection wirings connected to the wiring and a plurality of second connection wirings. Each of the plurality of first connection wirings reaches the first back surface from the wiring and a part thereof is covered by the first layer. Each of the plurality of first connection wirings has a bottom surface exposed on the first back surface. Each of the plurality of second connection wirings reaches the second main surface from the wiring and a part thereof is covered by the second layer. The semiconductor device according to appended note 2-2 or appended note 2-3, wherein each of the plurality of second connection wirings has a top surface exposed on the second main surface.

[0424] (Appended note 2-15) The semiconductor device according to appended note 2-14, wherein, when viewed along the thickness direction, the shortest distance from the center of the semiconductor element to any one of the plurality of second connection wirings is smaller than the shortest distance from the center of the semiconductor element to any one of the plurality of first connection wirings.

[0425] (Appended note 2-16) The semiconductor device further includes a plurality of first terminals and a plurality of second terminals. The plurality of first terminals individually cover the bottom surfaces of the plurality of first connection wirings. The semiconductor device according to appended note 2-14 or appended note 2-15, wherein the plurality of second terminals individually cover the top surfaces of the plurality of second connection wirings.

[0426] (Appended note 2-17) The semiconductor device according to any one of appended notes 2-2 to 2-16, wherein, when viewed along the thickness direction, the wiring is located inward of the periphery of the sealing resin.

[0427] (Appended note 3-1) An electrically insulating insulating member having an insulating main surface and an insulating back surface facing opposite sides in the thickness direction. A main surface wiring having a wiring main surface formed on the insulating main surface and facing the same direction as the insulating main surface, and a wiring back surface facing the insulating main surface, A first functional element that is electrically connected to the main surface wiring and is disposed on the side opposite to the insulating member with respect to the main surface wiring in the thickness direction, A sealing resin that covers the main surface wiring and the first functional element and has an element mounting surface facing the same direction as the insulating main surface, A connection conductor that is electrically connected to the main surface wiring, extends from the wiring main surface to the element mounting surface in the thickness direction, and is exposed from the element mounting surface, A through wiring that is electrically connected to the main surface wiring, extends from the wiring back surface to the insulating back surface in the thickness direction, and is exposed from the insulating back surface, A second functional element mounted on the element mounting surface and electrically connected to the connection conductor, Comprising An electronic component.

[0428] (Appendix 3-2) The dimension of the second functional element in the thickness direction is larger than the dimension of the first functional element in the thickness direction The electronic component according to Appendix 3-1.

[0429] (Appendix 3-3) Comprising a top surface wiring formed on the element mounting surface and electrically connected to the connection conductor, The second functional element is electrically connected to the connection conductor via the top surface wiring The electronic component according to Appendix 3-1 or Appendix 3-2.

[0430] (Appendix 3-4) The top surface wiring has a top surface electrode that is electrically connected to the second functional element, The electronic component has an insulating film that covers the element mounting surface and the portion of the top surface wiring other than the top surface electrode The electronic component according to Appendix 3-3.

[0431] (Appendix 3-5) The connection conductor is arranged so as to overlap with the first functional element when viewed from a direction orthogonal to the thickness direction. The dimension of the second functional element in the direction orthogonal to the thickness direction is larger than the dimension of the first functional element in the direction orthogonal to the thickness direction. The electronic component according to any one of Appendices 3-1 to 3-4.

[0432] (Appendix 3-6) The main surface wiring has an inner portion that extends inward of the insulating main surface rather than the through wiring in the planar direction of the insulating main surface. The first functional element is mounted on the inner portion. The electronic component according to any one of Appendices 3-1 to 3-5.

[0433] (Appendix 3-7) The connection conductor is connected to a portion between the first functional element and the through wiring in the direction in which the inner portion extends among the inner portions. The electronic component according to Appendix 3-6.

[0434] (Appendix 3-8) A plurality of connection conductors are provided. The plurality of connection conductors are dispersedly arranged on both sides of the first functional element when viewed from the thickness direction. The electronic component according to Appendix 3-7.

[0435] (Appendix 3-9) The encapsulating resin has a resin side surface facing a direction intersecting the thickness direction, and a step that is recessed inward from the resin side surface, and is partitioned into a first resin portion that is a portion of the encapsulating resin on the element mounting surface side of the step and a second resin portion that is a portion of the encapsulating resin on the insulating member side of the step in the thickness direction. The electronic component according to any one of Appendices 3-1 to 3-8.

[0436] (Appendix 3-10) The through-wiring is exposed from the side surface of the insulating member. The electronic component according to any one of Appendices 3-1 to 3-9.

[0437] (Appendix 3-11) The encapsulating resin has a resin side surface facing a direction intersecting the thickness direction, The main surface wiring is exposed from the resin side surface. The electronic component according to Appendix 3-10.

[0438] (Appendix 3-12) A plurality of the second functional elements are provided, A plurality of the main surface wirings are provided, A plurality of the connection conductors are provided, The first functional element is individually electrically connected to the plurality of second functional elements via the plurality of main surface wirings and the plurality of connection conductors. The electronic component according to any one of Appendices 3-1 to 3-11.

[0439] (Appendix 3-13) A plurality of the second functional elements are provided, Each of the plurality of second functional elements has a plurality of electrodes, On the element mounting surface, an upper surface wiring having a plurality of upper surface electrodes individually connected to the plurality of connection conductors is formed, The plurality of electrodes are individually connected to the plurality of upper surface electrodes. The electronic component according to Appendix 3-12.

[0440] (Appendix 3-14) The first functional element includes a semiconductor element. The electronic component according to any one of Appendices 3-1 to 3-13.

[0441] (Appendix 3-15) The first functional element is a control element, The second functional element is a drive element driven by the control element. The electronic component according to any one of Supplementary Notes 3-1 to 3-14.

[0442] (Supplementary Note 3-16) The first functional element is an LSI. The electronic component according to Supplementary Note 3-14 or 3-15.

[0443] (Supplementary Note 3-17) The first functional element is a switching power supply LSI, The second functional element is an inductor. The electronic component according to Supplementary Note 3-14.

[0444] (Supplementary Note 3-18) The second functional element is an optical element. The electronic component according to Supplementary Note 3-15 or 3-16.

[0445] (Supplementary Note 3-19) The second functional element has a bridge-type output stage and an LC filter for removing noise from the output signal of the output stage, The first functional element has an LSI for controlling the output stage. The electronic component according to any one of Supplementary Notes 3-12 to 3-16.

[0446] (Supplementary Note 3-20) The first functional element has a bridge-type output stage and an LSI for controlling the output stage, The second functional element has an LC filter for removing noise from the output signal of the output stage. The electronic component according to any one of Supplementary Notes 3-12 to 3-14.

[0447] (Supplementary Note 3-21) An electrically insulating insulating member having an insulating front main surface and an insulating back main surface facing opposite sides in the thickness direction, A main surface wiring formed on the insulating front main surface and having a wiring front main surface facing the same direction as the insulating front main surface and a wiring back main surface facing the insulating front main surface, It is electrically connected to the main surface wiring, extends from the wiring back surface to the insulating back surface in the thickness direction, and is a through wiring exposed from the insulating back surface, It is electrically connected to the main surface wiring, and is a first functional element arranged on the side opposite to the insulating member with respect to the main surface wiring in the thickness direction, A sealing resin that covers the main surface wiring and the first functional element and has an element mounting surface facing the same direction as the insulating main surface, It ...

Claims

1. A substrate having a front main surface and a back main surface facing each other, A wiring portion having a conductive layer formed on the front main surface of the substrate, A joint portion having a first plating layer formed on the upper surface of the wiring portion and a first solder layer formed on the upper surface of the first plating layer, A semiconductor element having an element main surface facing the front main surface of the substrate, an element electrode formed on the element main surface, and a second solder layer formed on the lower surface of the element electrode and joined to the first solder layer, A sealing resin covering the semiconductor element, Comprising, When viewed from the thickness direction perpendicular to the front main surface of the substrate, the joint portion is larger than the element electrode, The thickness of the first solder layer is less than or equal to the thickness of the first plating layer, Semiconductor device.

2. The thickness of the first solder layer is 1 μm or more and 5 μm or less, and the thickness of the first plating layer is 3 μm or more and 5 μm or less, The semiconductor device according to claim 1.

3. The thickness of the conductive layer is 15 μm or more and 20 μm or less, The semiconductor device according to claim 1 or 2.

4. The thickness of the solder layer composed of the first solder layer and the second solder layer is 10 μm or more and 15 μm or less, The semiconductor device according to any one of claims 1 to 3.

5. The conductive layer is made of Cu, and the first plating layer is made of Ni, The semiconductor device according to any one of claims 1 to 4.

6. The element electrode has a second plating layer, and the second solder layer is formed on the lower surface of the second plating layer, The semiconductor device according to any one of claims 1 to 5.

7. The second plating layer is made of Ni, The semiconductor device according to claim 6.

8. Comprising a metal layer formed on the lower surface of the conductive layer, The semiconductor device according to any one of claims 1 to 7.

9. The metal layer contains Ti, The semiconductor device according to claim 8.

10. The substrate is composed of resin, The wiring portion has a main surface wiring including the conductive layer, and a through wiring that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the substrate in the thickness direction, The semiconductor device according to any one of claims 1 to 9.

11. Having an external connection terminal covering the through wiring exposed on the back main surface of the substrate, The semiconductor device according to claim 10.

12. The main surface wiring and the through wiring are exposed on the side surface of the substrate, The semiconductor device according to claim 11.

13. The external connection terminal covers the main surface wiring and the through wiring that are exposed on the side surface of the substrate. The semiconductor device according to claim 12.

14. The wiring portion has columnar wiring provided on the side opposite to the through wiring with respect to the main surface wiring. The columnar wiring extends in the thickness direction and has a side surface that is exposed from a resin side surface which is a plane parallel to the side surface of the substrate. The semiconductor device according to claim 10.

15. The encapsulating resin has a first resin portion on the side of the substrate and a second resin portion on the side of the upper surface of the resin. When viewed from the thickness direction, the second resin portion is larger than the first resin portion. The semiconductor device according to claim 14.

16. Having an external connection terminal that covers the wiring portion exposed from the substrate and the encapsulating resin. The semiconductor device according to claim 14 or claim 15.

17. The substrate is made of resin. The wiring portion has a main surface wiring including the conductive layer and a through wiring that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the encapsulating resin in the thickness direction. The semiconductor device according to any one of claims 1 to 9.

18. Having an external connection terminal that covers the through wiring exposed on the upper surface of the encapsulating resin. The semiconductor device according to claim 17.

19. The substrate is made of a semiconductor material. The wiring portion has a main surface wiring including the conductive layer and a through wiring that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the substrate in the thickness direction. The semiconductor device according to any one of claims 1 to 9.

20. The semiconductor device according to claim 19, wherein the substrate includes a first insulating layer interposed between the main surface of the substrate and the conductive layer, and a second insulating layer interposed between the inner wall of the through hole in which the through wiring is disposed and the through wiring.

21. The through wiring has an upper surface facing the side of the conductive layer, and the upper surface is concave toward the inside of the through wiring. The semiconductor device according to claim 19 or claim 20.

22. The semiconductor device according to any one of claims 19 to 21, having an external connection terminal that covers the through wiring exposed on the back surface of the substrate.

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