Semiconductor device

Abstract

To provide a novel semiconductor device that can write and read multilevel data.SOLUTION: A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control a conduction state between the bit line and the power supply line. The first and second transistors preferably include an oxide semiconductor in a semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manu facture, or a composition of matter. Further, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and driving methods thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

[0002] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A display device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

Background Art

[0003] A semiconductor device that enables data retention by combining a transistor using silicon (Si) for a semiconductor layer and a transistor using an oxide semiconductor (OS) for a semiconductor layer has attracted attention (see Patent Document 1).

[0004] In recent years, with the increase in the amount of data to be handled, semiconductor devices having a large storage capacity have been demanded. Among such semiconductor devices, the semiconductor device described in Patent Document 1 mentioned above discloses a configuration for storing multi-valued data and reading out the data. Note that in this specification, unless otherwise specified, multi-valued data refers to data of j bits (j is a natural number of 2 or more).

Prior Art Documents

Patent Documents

[0005] ​​​​​​​​

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] For example, in the semiconductor device described in Patent Document 1, multi-valued data is written using one transistor. However, as the number of bits of the multi-valued data increases, the difference between the potentials corresponding to each data becomes smaller, making it difficult to determine the potential when reading the data, and there is a possibility of reading an incorrect value. As the number of bits of the multi-valued data increases, the difference between the potentials corresponding to each data becomes smaller, making it difficult to determine the potential when reading the data, and there is a possibility of reading an incorrect value. As the number of bits of the multi-valued data increases, the difference between the potentials corresponding to each data becomes smaller, making it difficult to determine the potential when reading the data, and there is a possibility of reading an incorrect value. As the number of bits of the multi-valued data increases, the difference between the potentials corresponding to each data becomes smaller, making it difficult to determine the potential when reading the data, and there is a possibility of reading an incorrect value.

[0007] One aspect of the present invention is to provide a semiconductor device capable of writing and reading multi-valued data, or to provide a driving method for a semiconductor device capable of writing and reading multi-valued data. Another aspect of the present invention is to provide a novel semiconductor device. One aspect of the present invention is to provide a semiconductor device capable of writing and reading multi-valued data, or to provide a driving method for a semiconductor device capable of writing and reading multi-valued data. Another aspect of the present invention is to provide a novel semiconductor device. One aspect of the present invention is to provide a semiconductor device capable of writing and reading multi-valued data, or to provide a driving method for a semiconductor device capable of writing and reading multi-valued data. Another aspect of the present invention is to provide a novel semiconductor device. One aspect of the present invention is to provide a semiconductor device capable of writing and reading multi-valued data, or to provide a driving method for a semiconductor device capable of writing and reading multi-valued data. Another aspect of the present invention is to provide a novel semiconductor device.

[0008] The description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all of these problems. Also, problems other than those listed will naturally become apparent from the description in the specification, drawings, claims, etc., and these problems can also be problems of one form of the present invention. The description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all of these problems. Also, problems other than those listed will naturally become apparent from the description in the specification, drawings, claims, etc., and these problems can also be problems of one form of the present invention. The description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all of these problems. Also, problems other than those listed will naturally become apparent from the description in the specification, drawings, claims, etc., and these problems can also be problems of one form of the present invention. The description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all of these problems. Also, problems other than those listed will naturally become apparent from the description in the specification, drawings, claims, etc., and these problems can also be problems of one form of the present invention.

Means for Solving the Problems

[0009] One aspect of the present invention is a semiconductor device having bit lines, power supply lines, first and second word lines, first to fourth transistors, first and second capacitor elements, and first and second holding nodes. The first holding node is supplied with first data through the first transistor. One aspect of the present invention is a semiconductor device having bit lines, power supply lines, first and second word lines, first to fourth transistors, first and second capacitor elements, and first and second holding nodes. The first holding node is supplied with first data through the first transistor. One aspect of the present invention is a semiconductor device having bit lines, power supply lines, first and second word lines, first to fourth transistors, first and second capacitor elements, and first and second holding nodes. The first holding node is supplied with first data through the first transistor. is obtained. The second holding node is supplied with second data via a second transistor. The gate of the third transistor is electrically connected to the first holding node. One of the source and drain of the third transistor is electrically connected to the bit line. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor. The other of the source and drain of the fourth transistor is electrically connected to the power supply line. The gate of the fourth transistor is electrically connected to the second holding node. The first terminal of the first capacitor element is electrically connected to the first holding node. The second terminal of the first capacitor element is electrically connected to the first word line. The first terminal of the second capacitor element is electrically connected to the second holding node. The second terminal of the second capacitor element is electrically connected to the second word line. The first and second data consist of binary or multi-valued data. The first and second transistors have an oxide semiconductor in the semiconductor layer. In the above aspect, the third and fourth transistors are p-channel type transistors. In the above aspect, the third and fourth transistors are n-channel type transistors. One aspect of the present invention is an electronic device including the semiconductor device described in the above aspect, a display device, a microphone, a speaker, an operation key, or a housing. In this specification and the like, a transistor is an element having at least three terminals including a gate (gate terminal or gate electrode), a drain, and a source. And the drain

[0010]

[0011]

[0012]

[0013] ​​​​​​a drain (drain terminal, drain region, or drain electrode) and a source (source terminal, source region, or source electrode), having a channel region therebetween, and allowing current to flow through the drain, the channel region, and the source.

[0014] Here, since the source and the drain can change depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, instead of calling the part that functions as the source and the part that functions as the drain the source or the drain, one of the source and the drain may be referred to as the first electrode, and the other of the source and the drain may be referred to as the second electrode.

[0015] It should be noted that the ordinal numbers "first", "second", and "third" used in this specification are added to avoid confusion of components and are not intended to be numerically limiting.

[0016] In this specification, "A and B are connected" means that, in addition to A and B being directly connected, it includes those that are electrically connected. Here, "A and B are electrically connected" means that when there is an object having some electrical action between A and B, it enables the transfer of electrical signals between A and B.

[0017] For example, when the source (or the first terminal, etc.) of the transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 is directly connected to X, ​​​​​​​​Continuing, the drain of the transistor (or the second terminal, etc.) is directly connected to a part of Z2 If another part of Z2 is directly connected to Y, it can be expressed as follows as follows.

[0018] For example, it can be expressed as "X, Y, the source of the transistor (or the first terminal, etc.), and the drain of the transistor (or the second terminal, etc.) are electrically connected to each other, and they are electrically connected in the order of X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y." Or, it can be expressed as "The source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y through the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.), and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order." Using the same expression methods as these examples, by stipulating the connection order in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). That is, they are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0019] In this specification, terms indicating arrangements such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation. In this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state. The off state, unless otherwise specified, for an n-channel transistor means that the potential difference (V ) between the gate and the source is lower than the threshold voltage (Vth), and for a p-channel transistor, it means that V is higher than Vth. For example,

[0020] the off-current of an n-channel transistor may refer to the drain current when V is lower than Vth. The off-current of a transistor may depend on V . Therefore, when it is stated that the off-current of a transistor is 10 GS A or less, it may mean that there exists a value of V for which the off-current of the transistor is 10 GS A or less. Also, the off-current of a transistor may depend on the potential difference (V GS ) between the drain and the source. In this specification, unless otherwise stated, the off-current may represent the off-current at V with an absolute value of 0 GS .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 2V, 16V, or 20V. Alternatively, the off-current of the transistor -21 may refer to the drain current when V is lower than Vth. The off-current of a transistor may depend on V -21 . Therefore, when it is stated that the off-current of a transistor is 10 GS A or less, it may mean that there exists a value of V

[0021] for which the off-current of the transistor is 10 DS A or less. Also, the off-current of a transistor may depend on the potential difference (V ) between the drain and the source. In this specification, unless otherwise specified, the off-current may represent the off-current at V DS with an absolute value of 0 .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 2V, 16V, or 20V. Alternatively, the off-current of the transistor V used in the reliability required for semiconductor devices including studs DS , or the V used in semiconductor devices including the transistor DS represents the off-current in some cases.

Advantages of the Invention

[0022] According to one aspect of the present invention, it becomes possible to provide a semiconductor device capable of writing and reading multi-valued data, or to provide a driving method for a semiconductor device capable of writing and reading multi-valued data. Further, according to one aspect of the present invention, it becomes possible to provide a novel semiconductor device. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

[0023] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments have many different It can be implemented in the described manner, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention is not to be construed as limited to the description of the following embodiments.

[0026] Also, in the drawings, there are cases where the size, layer thickness, or area is exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values shown in the drawings. For example, it can include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations. Also, in the embodiments described below, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and the repeated description thereof is omitted.

[0027] (Embodiment 1) In this embodiment, the circuit configuration and operation of the memory cell included in the semiconductor device according to one aspect of the present invention

[0028] 〈〈Example of Memory Cell Configuration〉〉 FIG. 1 is a circuit diagram of a memory cell 100 according to one aspect of the present invention.

[0029] In the memory cell 100 shown in FIG. 1, there are a transistor 101, a transistor 102, a transistor 103, a capacitor element 104, a transistor 105, a capacitor element 106, a node FN1, and a node FN2. Also, the memory cell 100 includes bit lines BL , a power supply line SL, a word line WLC1, a word line WLOS1, a word line WLC2, and a word line It is electrically connected to WLOS2.

[0030] The gate of transistor 101 is electrically connected to word line WLOS1, and one of the source and drain of transistor 101 is electrically connected to bit line BL, and the other of the source and drain of transistor 101 is electrically connected to node FN1, and the second gate of transistor 101 is electrically connected to the wiring to which signal BG1 is applied.

[0031] The gate of transistor 102 is electrically connected to node FN1, and one of the source and drain of transistor 102 is electrically connected to bit line BL, and the other of the source and drain of transistor 10 2 is electrically connected to one of the source and drain of transistor 103.

[0032] The gate of transistor 103 is electrically connected to node FN2, and the other of the source and drain of transistor 103 is electrically connected to power supply line SL.

[0033] One terminal of capacitor element 104 is electrically connected to word line WLC1, and the other terminal of capacitor element 104 is electrically connected to node FN1.

[0034] The gate of transistor 105 is electrically connected to word line WLOS2, and one of the source and drain of transistor 105 is electrically connected to bit line BL, and the other of the source and drain of transistor 105 is electrically connected to node FN2, and the second gate of transistor 105 is electrically connected to the wiring to which signal BG2 is applied.

[0035] ​One terminal of the capacitance element 106 is electrically connected to the word line WLC2, and the capacitance element 106 's other terminal is electrically connected to the node FN2.

[0036] The node FN1 has a function of holding binary or multi-valued data. That is, the node FN1 has a function of holding M-bit (2 M values, M is a natural number of 1 or more) data. Specifically, if it is 2-bit data, it is 4-value (2 2 ) data, and is a signal having any one of four levels of voltage.

[0037] Similarly, the node FN2 has a function of holding binary or multi-valued data. That is , the node FN2 has a function of holding N-bit (2 N values, N is a natural number of 1 or more) data.

[0038] The above M-bit data and N-bit data are given to the bit line. Also, the above M-bit data is given from the bit line to the node FN1 via the transistor 101 . Also, the above N-bit data is given from the bit line to the node F N2 via the transistor 105.

[0039] In this specification, when the potential of the node FN1 or the node FN2 becomes a potential corresponding to the voltage of the bit line BL, it is said that data is written into the memory cell. Also, when the potential of the bit line BL becomes a potential corresponding to the potential of the node FN1 or the node FN2, it is said that data is read from the memory cell.

[0040] Write signals are given to the word lines WLOS1 and WLOS2.

[0041] ​​​​​ The write signal is a signal that turns on transistor 101 or transistor 105 to apply the potential of bit line BL to node FN1 or FN2.

[0042] Read signals are applied to word lines WLC1 and WLC2.

[0043] The read signal is a signal applied to one terminal of capacitor element 104 or one terminal of capacitor element 106 in order to selectively read data from the memory cell.

[0044] Transistors 101 and 105 are described as n-channel transistors. Also, transistors 102 and 103 are described as p-channel transistors.

[0045] Transistors 101 and 105 function as switches that control data writing by switching between the conductive state and the non-conductive state. Also, they have a function of holding the potential based on the written data by maintaining the non-conductive state.

[0046] Note that transistors 101 and 105 are preferably transistors with low current (off-current) flowing between the source and the drain in the non-conductive state. Here, low off-current means that at room temperature, with a voltage of 10V between the source and the drain, the normalized off-current per channel width of 1μm is 10×10 A or less. -21 Examples of transistors with such low off-current include transistors having an oxide semiconductor in the semiconductor layer.

[0047] In the configuration of the memory cell 100 shown in FIG. 1, the potential based on the written data is held by maintaining the non-conducting state. Therefore, a transistor with a low off-current is preferably used as a switch for suppressing potential fluctuations accompanied by the movement of charges at the nodes FN1 and FN2. Transistors 102 and 103 have a function of flowing a current between the bit line BL and the power supply line SL according to the potentials of the nodes FN1 and FN2. For this reason, it is particularly preferable to use a transistor with a low off-current as a switch for suppressing potential fluctuations accompanied by the movement of charges at the nodes FN1 and FN2. Particularly preferred.

[0048] Transistors 102 and 103 have a function of flowing a current between the bit line BL and the power supply line SL according to the potentials of the nodes FN1 and FN2. It should be noted that it is preferable to use transistors with little variation in threshold voltage for transistors 102 and 103. Here, a transistor with little variation in threshold voltage means a transistor in which, when transistors are fabricated in the same process, the allowable difference in threshold voltage can be formed within 100 mV. Specifically, a transistor in which the channel is formed of single crystal silicon can be mentioned.

[0049] It should be noted that it is preferable to use transistors with little variation in threshold voltage for transistors 102 and 103. Here, a transistor with little variation in threshold voltage means a transistor in which, when transistors are fabricated in the same process, the allowable difference in threshold voltage can be formed within 100 mV. Specifically, a transistor in which the channel is formed of single crystal silicon can be mentioned. Here, a transistor with little variation in threshold voltage means a transistor in which, when transistors are fabricated in the same process, the allowable difference in threshold voltage can be formed within 100 mV. Specifically, a transistor in which the channel is formed of single crystal silicon can be mentioned. Specifically, a transistor in which the channel is formed of single crystal silicon can be mentioned. Here, a transistor with little variation in threshold voltage means a transistor in which, when transistors are fabricated in the same process, the allowable difference in threshold voltage can be formed within 100 mV.

[0050] It should be noted that the second gates of transistors 101 and 105 have a function of controlling the threshold voltages of transistors 101 and 105, or a function of improving the on-currents of transistors 101 and 105, but may be omitted depending on the case. It should be noted that the second gates of transistors 101 and 105 have a function of controlling the threshold voltages of transistors 101 and 105, or a function of improving the on-currents of transistors 101 and 105, but may be omitted depending on the case. It should be noted that the second gates of transistors 101 and 105 have a function of controlling the threshold voltages of transistors 101 and 105, or a function of improving the on-currents of transistors 101 and 105, but may be omitted depending on the case.

[0051] 〈〈Timing Chart〉〉 Next, an example of the operation of the memory cell 100 will be described using the timing charts of FIGS. 2 and 3. Next, an example of the operation of the memory cell 100 will be described using the timing charts of FIGS. 2 and 3.

[0052] The timing charts shown in FIGS. 2 and 3 are for the bit line BL, power supply line SL, word line WLOS1, word line WLC1, node FN1, word line WLOS2, word line WLC2, node FN2, and word line WLOS3 of the memory cell 100. L, word line WLOS1, word line WLC1, node FN1, word line WLOS2, word line WLC2, node FN2, and word line WLOS3 of the memory cell 100. The potential changes of the drain line WLC2 and the node FN2 are shown. Figure 2 shows the timing chart when writing data to the memory cell 100, and Figure 3 shows the timing chart when reading the data written to the memory cell 100 in Figure 2. When writing data to the memory cell 100, the timing chart is shown in Figure 2. When reading the data written to the memory cell 100 in Figure 2, the timing chart is shown in Figure 3. Figure 2 shows the timing chart when writing data to the memory cell 100, and Figure 3 shows the timing chart when reading the data written to the memory cell 100 in Figure 2.

[0053] In Figures 2 and 3, the power supply line SL, the word lines WLOS1, and WLOS2 are given the high power supply potential and the potential V is applied, and the low power supply potential and the potential V H1 is applied. Note that the potential V GND can also be the ground potential GND. Also, the potential V GND is sometimes referred to as the H-level potential, and the potential V H1 is sometimes referred to as the L-level potential. Furthermore, the word lines WLOS1 and WLOS2 may be given a potential lower than the potential GN D V V GND -V L1 is applied. The potential -V L1 is preferably a negative potential ( -V L1 <0V).

[0054] H2 In Figures 2 and 3, the word lines WLC1 and WLC2 are given the high power supply potential and the potential V is applied, and the low power supply potential and the potential V GND is applied. Note that the potential V GND can also be the ground potential GND. Also, the potential V H2 is sometimes referred to as the H-level potential, and the potential V GND is sometimes referred to as the L-level potential In some cases, the word lines WLC1 and WLC2 may be given a potential lower than the potential V GND V -V L2 is applied. The potential -V L2 is preferably a negative potential (-V L2 <0V) and is preferably negative (-V

[0055] Write Operation The write operation of the memory cell 100 will be described with reference to the timing chart of FIG. cormorant.

[0056] FIG. 2 is composed of four periods p0 to p3. Period p0 is the initial period, period p1 is the normal period, and period p1 is the period for writing data to node FN1, period p2 is the period for writing data to node FN2, The period p3 represents the period during which the written data is retained. Times T0 to T8 are added to explain the timing of the operations.

[0057] First, during the period p0, the bit line BL is V GND The power supply line SL is initialized to V GND The word line WLOS1 is given a potential of L level, and the word line WLC1 is given a potential of H level. A potential of the L level is applied to the word line WLOS1, a potential of the L level is applied to the word line WLC 2 is given a high level potential.

[0058] Next, at time T0, the potential of the word line WLOS1 changes from L level to H level, The potential of the word line WLC1 changes from H level to L level. At this time, the transistor 101 is turned on, the connection between the bit line BL and the node FN1 is made conductive, and the node F N1 is the potential V GND is initialized to .

[0059] Next, at time T1, a potential V1 is applied to the bit line BL, and the bit line BL is electrically connected to the The potential V1 is also written to a node FN1 located at the node FN2.

[0060] In the timing charts of Figures 2 and 3, the hatched areas indicate A potential within the range where the pattern is given is applied, that is, it indicates that multi-valued data is given. For example, when writing 4-bit data to node FN1, the potential V1 can take 2 = 16 values of potential. 4

[0061] Next, at time T2, the potential of word line WLOS1 is set to the L level, and after turning off transistor 101, at time T3, the potential of bit line BL is initialized to V GND . At this time, node FN1 becomes electrically floating and holds potential V1.

[0062] Next, at time T4, the potential of word line WLC1 is set to the H level, and the potential of node FN1 is increased to V1 + V by capacitive coupling. By keeping the potential of node FN1 high, H2 p-channel transistor 102 remains off, and the leakage current flowing between bit line BL and power supply line SL can be prevented. At the same time, the potential of word line WLOS2 is changed from the L level to the H level, and the potential of word line WLC2 is changed from the H level to the L level. At this time, transistor 105 turns on and node FN2 is initialized. For node FN1 to transmit the potential applied to word line WLC1 through capacitive element 104,

[0063] it is preferable that the capacitance of capacitive element 104 is sufficiently larger than the gate capacitance of transistor 101 and the capacitance of capacitive element 104 is sufficiently larger than the gate capacitance of transistor 102. In this embodiment, for simplicity of explanation, the potential applied to word line WLC1 is directly transmitted to node FN1 (for example, when potential V is applied to word line WLC1, node FN1 receives it as it is). H2 is applied to word line WLC1, node ​​​​The potential of the word line FN1 rises from the potential V1 to the potential V1 + V H2 as described above, but depending on the magnitude relationship of the capacitance of the capacitor element 104, the gate capacitance of the transistor 101, and the gate capacitance of the transistor 102 the potential applied to the word line WLC1 may not be directly transmitted to the node FN1 in some cases.

[0064] Next, at time T5, a potential V2 is applied to the bit line BL, and the potential V2 is written into the node FN2. Note that the potential V2 is given multi-valued data. For example, when writing 4-bit data into the node FN2 the potential V2 can take 2 4 = 16 values. This is possible.

[0065] Next, at time T6, the potential of the word line WLOS2 is changed from the H level to the L level to turn off the transistor 105, and at time T7, the potential of the bit line BL is initialized to V GND . At this time, since the node FN2 is in an electrically floating state, it holds the potential V2.

[0066] Next, at time T8, the potential of the word line WLC2 is changed from the L level to the H level, and the potential of the node FN2 is raised to V2 + V by capacitive coupling. By keeping the potential of the node FN2 high H2 the p-channel transistor 103 is maintained in the off state, preventing leakage current from flowing from the bit line BL to the power supply line SL.

[0067] Note that in order to transmit the potential of the word line WLC2 to the node FN2 via the capacitor element 106 the capacitance of the capacitor element 106 should be sufficiently larger than the gate capacitance of the transistor 105, and the capacitance of the capacitor element 106 should be sufficiently larger than the gate capacitance of the transistor 103, which is preferable That is, in this embodiment, for simplicity of explanation, the potential applied to the word line WLC2 is directly transmitted to the node FN2 (for example, when a potential V is applied to the word line WLC2, the potential of the node FN2 rises from potential V2 to potential V2 + V). However, depending on the magnitude relationship among the capacitance of the capacitor element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 103, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. That is, in this embodiment, for simplicity of explanation, the potential applied to the word line WLC2 is directly transmitted to the node FN2 (for example, when a potential V is applied to the word line WLC2, the potential of the node FN2 rises from potential V2 to potential V2 + V). However, depending on the magnitude relationship among the capacitance of the capacitor element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 103, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. H2 is applied, the potential of the node FN2 rises from potential V2 to potential V2 + V). However, depending on the magnitude relationship among the capacitance of the capacitor element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 103, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. is applied, the potential of the node FN2 rises from potential V2 to potential V2 + V). However, depending on the magnitude relationship among the capacitance of the capacitor element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 103, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. H2 is applied, the potential of the node FN2 rises from potential V2 to potential V2 + V). However, depending on the magnitude relationship among the capacitance of the capacitor element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 103, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. Among the capacitances of the capacitor element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 103, depending on their magnitude relationship, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. depending on their magnitude relationship, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2.

[0068] In the period p3 after the time T8 has elapsed, the data written to the nodes FN1 and FN2 are each retained. In the period p3 after the time T8 has elapsed, the data written to the nodes FN1 and FN2 are each retained.

[0069] As described above, by the writing operation explained with the timing chart of FIG. 2, multi-valued data can be written to the nodes FN1 and FN2. As described above, by the writing operation explained with the timing chart of FIG. 2, multi-valued data can be written to the nodes FN1 and FN2.

[0070] In addition, in the period p1, the potential V applied to the word line WLOS1 is preferably higher than the potential obtained by adding the threshold voltage of the transistor 101 to the potential V1. For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. H1 is preferably higher than the potential obtained by adding the threshold voltage of the transistor 101 to the potential V1. For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. is preferably higher than the potential obtained by adding the threshold voltage of the transistor 101 to the potential V1. For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. H For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. For example, when the potential V1 is 3V and the threshold voltage of the transistor 101 is 1V, the potential V is preferably 4V (3V + 1V) or higher. This is because when writing a potential of 3V from the bit line BL to the node FN1, if the potential of the word line WLOS1 is less than 4V, before the potential of the node FN1 reaches 3V, the potential difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. GS difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1. difference (V) between the gate and source of the transistor 101 becomes less than or equal to the threshold voltage, the transistor 101 turns off, and a potential of 3V cannot be written to the node FN1.

[0071] Similarly, in period p2, the potential V applied to the word line WLOS2 H1 is higher than the potential obtained by adding the threshold voltage of the transistor 105 to the potential V2. It is preferably a potential higher than the potential obtained by adding the threshold voltage of the transistor 105 to the potential V2.

[0072] Note that V in this specification GS refers to the potential difference between the gate and the source when the source is used as a reference. For example, when a potential of 1 V is applied to the source and 3 V is applied to the gate, V is 2 V. For example, when a potential of 3 V is applied to the source and 1 V is applied to the gate, G S V V GS is -2 V.

[0073] <Reading operation> The operation of reading the data written in the memory cell 100 will be described along the timing chart of FIG. 3. The operation of reading the data written in the memory cell 100 will be described.

[0074] FIG. 3 is composed of four periods from period p3 to p6. Period p3 is a period for continuously holding the data from period p3 of FIG. 2, period p4 is a period for reading the data of node FN1, period p 5 is a period for reading the data of node FN2, and period p6 is a period for holding the data, respectively. represented. Also, times T9 to T13 shown in FIG. 3 are for explaining the timing of the operation. shown. attached for the purpose of explaining the timing of the operation.

[0075] First, at time T9, the bit line BL is charged (precharged) to the potential V BL .

[0076] Next, at time T10, the bit line BL is electrically floated. That is, the bit line BL becomes a state in which the potential fluctuates due to charging or discharging of charges. This state is the bit line This is achieved by turning off the switch that applies a potential to BL.

[0077] Also, at time T10, the potential of word line WLC1 drops from the H level to the L level, and due to the capacitive coupling, the potential of node FN1 also drops from potential V1 + V H2 to potential V1. When the potential of node FN1 drops, the absolute value of V of p-channel transistor 102 becomes large GS and transistor 102 turns on. At the same time, the potential of word line WLC2 drops from the H level to potential -V , and due to capacitive coupling, the potential of node FN2 also drops from potential V2 + V L2 2 to potential V2 - V H L2 to potential V2 - V. When the potential of node FN2 drops, the absolute value of V of p-channel transistor 103 becomes large and transistor 103 turns on. GS When both transistor 102 and transistor 103 turn on, the bit line BL and the power supply line SL are in a conductive state, a current flows, the bit line BL discharges its charge, and the potential of the bit line BL drops. When the potential of the bit line BL drops due to discharge, the absolute value of V

[0078] of transistor 102 and the absolute value of V GS of transistor 103 both drop. When the absolute value of V of either one of the transistors GS becomes equal to the threshold voltage of that transistor, the discharge is completed and the potential of the bit line BL converges to a certain potential. During period p4, since a lower potential is applied to node FN2 than to node FN1 GS , transistor 103 has a larger absolute value of V than transistor 102, and transistor 103 turns on earlier than transistor 102. Therefore, the potential of the bit line BL drops more significantly in the initial stage. GS ​The absolute value is large. That is, the channel resistance of transistor 103 is lower and the on-current is larger than that of transistor 102 Therefore, the discharge of bit line BL starts and the V of transistor 102 GS reaches the threshold voltage earlier, and transistor 102 turns off earlier.

[0079] When transistor 102 turns off, bit line BL converges to a certain potential (potential V1´). This potential V1´ can be obtained as a value obtained by subtracting the threshold voltage of transistor 102 from the potential of node FN1. That is, the potential V1´ of bit line BL can be obtained in a form reflecting the level of the potential of node FN1. By using this potential difference for data determination, the multi-valued data written to node FN1 can be read out. That is, the potential V1´ of bit line BL can be obtained in a form reflecting the level of the potential of node FN1. By using this potential difference for data determination, the multi-valued data written to node FN1 can be read out. By using this potential difference for data determination, the multi-valued data written to node FN1 can be read out.

[0080] At time T10, the potential of word line WLOS2 is changed from the L level to -V L1 to prevent transistor 105 from turning on due to the potential change of bit line BL or node FN2. At time T10, the potential of word line WLOS2 is changed from the L level to -V to prevent transistor 105 from turning on due to the potential change of bit line BL or node FN2.

[0081] Next, at time T11, the potential of bit line BL is restored to the potential V BL again, and precharge is performed. At the same time, the potentials of all word lines, nodes FN1, and FN2 are returned to the state of period p 3, and transistors 102 and 103 are turned off. Next, at time T11, the potential of bit line BL is restored to the potential V again, and precharge is performed. At the same time, the potentials of all word lines, nodes FN1, and FN2 are returned to the state of period p

[0082] 3, and transistors 102 and 103 are turned off.

[0083] Next, at time T12, bit line BL is electrically floated. This state is realized by turning off the switch that applies a potential to bit line BL.Also, at time T12, the potential of word line WLC1 changes from the H level to the potential -V L2 and the potential of word line WLC2 changes from the H level to the L level. At this time, due to capacitive coupling , the potential of node FN1 decreases from the potential V1 + V to the potential V1 - V H2 , and the potential of node FN2 decreases from the potential V2 + V L2 to the potential V2. As a result, transistors 10 2 and 103 turn on, and a conductive state is established between bit line BL and power supply line SL, and bit line B H2 L discharges the charge, and the potential of bit line BL decreases. In period p5, since node FN1 is given a lower potential than node FN2, the absolute value of V

[0084] is larger for transistor 102 than for transistor 103. That is , the channel resistance of transistor 102 is lower and the on-current is GS larger than that of transistor 103. Therefore, when the discharge of bit line BL starts, V of transistor 103 reaches the threshold voltage earlier, and transistor 103 turns off first. GS When transistor 103 turns off, bit line BL converges to a certain potential (potential V2'). This potential V2' is obtained as a value obtained by subtracting the threshold voltage of transistor 103 from the potential of node FN2 generally. That is, the potential V2' of bit line BL can be obtained in a form that reflects the height

[0085] of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out.

[0086] Note that at time T12, the potential of word line WLOS1 is changed from the L level to -V

[0086] L1 L1Change it to This prevents transistor 1 05 from turning on due to the potential change in bit line BL or node FN2.

[0087] Next, at time T13, the bit line BL is initialized to V GND All word lines and nodes FN1 and FN2 are returned to the state of period p3, transistors 102 and 103 are turned off and the potentials of nodes FN1 and FN2 are held.

[0088] As described above, by the read operation explained in the timing chart of FIG. 3, the multi-valued data written in nodes FN1 and FN2 can be read out.

[0089] For example, consider the case of writing 8-bit data, that is, 256 (= 2 8 ) values of potential, into one node. In that case, if the width of the potential of one value is 0.17V, the width of the potential applied to the node for holding the data is 0.17V × 256 = 43.52V. That is, to store 8-bit data in one node, it is necessary to apply a power supply potential of approximately 45V to the memory cell However, this power supply potential is not a realistic value because it causes the breakdown of the transistor. On the other hand, when writing 8-bit data to the memory cell 100 shown in this embodiment, the 8 bit data can be divided into two, 4-bit data and 4-bit data, and one can be stored in node

[0090] FN1 and the other in node FN2. Therefore, one node undertakes the potential of 16 (= 2 ) values . If the width of the potential of one value is 0.17V, one 4 value When the width of the potential of one value is 0.17V, one The width of the potential applied to one node is 0.17 V × 16 = 2.72 V. This is a realistic value for driving a memory cell.

[0091] As described above, by using the memory cell 100 according to one aspect of the present invention, it is possible to provide a semiconductor device that stores 8-bit data.

[0092] Also, the number of bits of data that the memory cell 100 can store is not limited to 8 bits, and it can store data of various bit numbers. For example, when M-bit (2 values) data is stored in node FN1 and N-bit (2 values) data is stored in node FN2, the memory cell 100 can store M + N-bit (2 values) data. M N M+N

[0093] The memory cell 100 in FIG. 1 may be provided with a common signal BG to the second gates of transistors 101 and 105 as shown in the circuit diagram of FIG. 21(A).

[0094] The memory cell 100 in FIG. 1 may be configured with the circuit diagram shown in FIG. 22(A). The circuit diagram shown in FIG. 22(A) is different from the circuit diagram in FIG. 1 in that it has two bit lines BL1 and BL2 and transistors 101 and 105 are connected to a common word line WLOS. Also, a common signal may be provided to the second gates of transistor 101 and transistor 105 shown in FIG. 22(A) in the same manner as in FIG. 21(A). Also, in some cases, these second gates may be omitted.

[0095] The memory cell 100 in FIG. 1 may be configured with the circuit diagram shown in FIG. 23(A). The circuit diagram shown in FIG. 23(A) ​​​​​​​​​​​​​The circuit diagram shown in is different from the circuit diagram shown in FIG. 1 in that it has transistor 107, capacitor element 108, transistor 109, node F , N3, word line WLOS3, and word line WLC3. Also, a common signal may be applied to the second gates of transistor 101, transistor 105 and transistor 107 shown in FIG. 23(A), similar to FIG. 21(A). Also, in some cases, these second gates may be omitted.

[0096] Note that the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0097] (Embodiment 2) In this embodiment, the circuit configuration and operation of the memory cell included in the semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 4 to 6.

[0098] <Example of Memory Cell Configuration> FIG. 4 is a circuit diagram of a memory cell 110 which is one aspect of the present invention.

[0099] In the memory cell 110 shown in FIG. 4, there are transistor 101, transistor 112, transistor 113, capacitor element 104, transistor 105, capacitor element 106, node FN1, and node FN2. The memory cell 110 is also electrically connected to bit line BL , power supply line SL, word line WLC1, word line WLOS1, word line WLC2, and word line WLOS2.

[0100] The memory cell 110 replaces transistors 102 and 10 3 of the memory cell 100 shown in Embodiment 1 with transistors 112 and 113 which are n-channel type transistors. There are. Hereinafter, the transistors 101, 112, 113, and 105 will be described as n-channel transistors. The description will be given.

[0101] The transistors 112 and 113 have a function of flowing a current between the bit line BL and the power supply line SL according to the potentials of the nodes FN1 and FN2. The description will be given.

[0102] Note that it is preferable to use transistors with a small variation in threshold voltage for the transistors 112 and 113. Here, a transistor with a small variation in threshold voltage means a transistor in which the allowable difference in threshold voltage is within 100 mV when the transistors are manufactured in the same process. Specifically, a transistor in which the channel is formed of single-crystalline silicon can be mentioned. The description will be given. The description will be given. The description will be given.

[0103] For details regarding other components of the memory cell 110, refer to the description of the memory cell 100. The description will be given.

[0104] <Timing Chart> Next, an example of the operation of the memory cell 110 will be described using the timing charts of FIGS. 5 and 6. The description will be given.

[0105] The timing charts shown in FIGS. 5 and 6 show the potential changes of the bit line BL, the power supply line SL, the word line WLOS1, the word line WLC1, the node FN1, the word line WLOS2, the word line WLC2, and the node FN2 of the memory cell 110. FIG. 5 represents a timing chart when writing data to the memory cell 110, and FIG. 6 represents a timing chart when reading the data written to the memory cell 110 in FIG. 5. The description will be given. The description will be given. The description will be given. The description will be given.

[0106] In FIGS. 5 and 6, the power line SL is supplied with a potential V as a high power potential H0 and a potential V as a low power potential. Note that the potential V GND may also be the ground potential GND. GND Also, the potential V may be referred to as the H-level potential, and the potential V H0 may be referred to as the L-level potential GND in some cases .

[0107] In FIGS. 5 and 6, the word lines WLOS1 and WLOS2 are supplied with a potential V as a high power potential and a potential V as a low power potential. Note that the potential V H1 may also be the ground potential GND. Also, the potential V GND may be referred to as the H-level potential, and the potential V G ND may be referred to as the L-level potential in some cases. Further, the word lines WLOS1 and WLOS2 H1 may be supplied with a potential -V lower than the potential V GND . The potential -V is preferably a negative GND potential (-V L1 < 0V). L1 The negative potential (-V L1 < 0V)

[0108] In FIGS. 5 and 6, the word lines WLC1 and WLC2 are supplied with a potential V as a high power potential and a potential V as a low power potential. Note that the potential V H2 may also be the ground potential GND. Also, the potential V GND may be referred to as the H-level potential, and the potential V GND may be referred to as the L-level potential in some cases. Further, the word lines WLC1 and WLC2 are supplied with a potential H2 -V lower than the potential V GND and L level potential in some cases. Further, the word lines WLC1 and WLC2 are supplied with a potential GND -V lower than the potential V L2may also be provided. Potential - V L2 is a negative potential (- V L2 <0 V) and is preferably so.

[0109] 〈〈Writing operation〉〉 An example of the writing operation of the memory cell 110 will be described along the timing chart of FIG. 5. will be described.

[0110] FIG. 5 is composed of four periods from period p0 to p3. Period p0 is the initial period, period p1 is the period for writing data to node FN1, period p2 is the period for writing data to node FN2, and period p3 is the period for holding the written data, respectively. Also, the times T0 to T8 shown in FIG. 5 are attached for explaining the timing of the operation. respectively. Also, the times T0 to T8 shown in FIG. 5 are attached for explaining the timing of the operation. respectively. Also, the times T0 to T8 shown in FIG. 5 are attached for explaining the timing of the operation. respectively. Also, the times T0 to T8 shown in FIG. 5 are attached for explaining the timing of the operation.

[0111] First, in period p0, the bit line BL and the power supply line SL are initialized to potential V GND and the word line WLOS1 is given potential - V and the word line WLC1 is given potential - V L1 and the word line WLOS2 is given potential - V L2 and the word line WLC2 is given potential - V and the word line WLOS2 is given potential - V L1 and the word line WLC2 is given potential - V L2 and is given.

[0112] Next, at time T0, a high - level potential is given to the word line WLOS1, and a low - level potential is given to the word line W LC1. At this time, the transistor 101 turns on, and the bit line BL and the node FN1 become conductive, and the node FN1 is initialized to potential V and the node FN1 becomes conductive, and the node FN1 is initialized to potential V GND and is initialized.

[0113] Next, at time T1, potential V1 is given to the bit line BL, and the bit line BL and the conductive state A potential V1 is written to the node FN1 therein.

[0114] Note that in the timing charts of FIGS. 5 and 6, the hatched portions indicate that the potential in the hatched range is applied, that is, multi-valued data is applied. For example, when 4-bit data is written to the node FN1, the potential V1 can take 2 = 16 values of potential. Also, at time T1, in order to keep the transistor 112 off, an H-level potential is applied to the power supply line SL. At this time, the potential V 4 applied to the power supply line SL is preferably higher than the potential V1 applied to the bit

[0115] line BL and the node FN1. By satisfying the above conditions, V of the transistor 112 can be kept at 0V. H0 Next, at time T2, an L-level potential is applied to the word line WLOS1, and the transistor 101 turns off. H0 Next, at time T3, the bit line BL and the power supply line SL are initialized to the potential V At this time, the node FN1 becomes electrically floating and holds the potential V1. GS Next, at time T4, an H-level potential is applied to the word line WLOS2, and an L-level potential is applied to the word line W

[0116] LC2. At this time, the transistor 105 turns on, the bit line BL and the node FN2 become conductive, and the node FN2 is initialized to the potential V

[0117] GND

[0118] GND

[0118]

[0119] At time T4, the word line WLC1 is applied with a potential of -V L2 Given that node FN1 has Potential V1-V L2 When the potential of the node FN1 is kept low, an n-channel The transistor 112 remains off, preventing leakage current flowing between the bit line BL and the power supply line SL. At this time, in order to prevent the transistor 101 from being turned on, the potential - V L1 is applied to word line WLOS1.

[0120] Note that the potential of the word line WLC1 is transmitted to the node FN1 through the capacitor 104. The capacitance of the capacitor 104 is sufficiently larger than the gate capacitance of the transistor 101, and It is preferable that the capacitance of the capacitor 104 is sufficiently larger than the gate capacitance of the transistor 112. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC1 is The potential of the word line WLC1 is directly transmitted to the node FN1 (for example, the potential of the word line WLC1 is V GND From Place-V L2 When the potential of the node FN1 changes from the potential V1 to the potential V1-V L2 Change to The capacitance of the capacitor 104, the gate capacitance of the transistor 101, and the Depending on the magnitude relationship with the gate capacitance of the transistor 112, There are cases where the potential is not transmitted directly to the node FN1.

[0121] Next, at time T5, the bit line BL is supplied with the potential V2, and the node FN2 is supplied with the potential V2. The potential V2 can have multiple values. For example, 4-bit data When is written to node FN2, the potential V2 is 2 4It can take a potential of 16 values. It is possible.

[0122] Also, at time T5, in order to maintain the off state of transistor 113, a high-level potential is applied to the power supply line SL. At this time, the potential V H0 applied to the power supply line SL is preferably higher than the potential V2 applied to the bit line BL and the node FN1. The potential V H0 satisfying the above conditions causes the V GS of transistor 113 to be maintained at 0V.

[0123] Next, at time T6, a low-level potential is applied to the word line WLOS2, and the transistor 105 turns off.

[0124] Next, at time T7, the bit line BL and the power supply line SL are initialized to the potential V GND . At this time, since the node FN2 is in an electrically floating state, it holds the potential V2.

[0125] Next, at time T8, a potential of -V L2 is applied to the word line WLC2, and a potential of V2 - V L2 is applied to the node FN2. When the potential of the node FN2 is kept low, the n-channel transistor 113 maintains the off state and cuts off the leakage current flowing between the bit line BL and the power supply line SL. Also, a potential of -V L1 is applied to the word line WLOS2 to prevent the transistor 1 05 from turning on.

[0126] Note that since the potential of the word line WLC2 is transmitted to the node FN2 via the capacitor element 106 , the capacitance of the capacitor element 106 is sufficiently larger than the gate capacitance of the transistor 105, and The capacitance of the capacitance element 106 is preferably sufficiently larger than the gate capacitance of the transistor 113. In the present embodiment, for simplicity of explanation, it is described that the potential applied to the word line WLC2 is directly transmitted to the node FN2 (for example, when the potential of the word line WLC2 changes from the potential V to the potential -V GND the potential of the node FN2 changes from the potential V2 to the potential V2 - V ), but depending on the magnitude relationship between the capacitance of the capacitance element 106, the gate capacitance of the transistor 105, and L2 the gate capacitance of the transistor 113, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. L2 ), but depending on the magnitude relationship between the capacitance of the capacitance element 106, the gate capacitance of the transistor 105, and the gate capacitance of the transistor 113, the potential applied to the word line WLC2 may not be directly transmitted to the node FN2. In the period p3 after the time T8 has elapsed, the data written to the nodes FN1 and FN2 are respectively retained. In the period p3 after the time T8 has elapsed, the data written to the nodes FN1 and FN2 are respectively retained.

[0127] In the period p3 after the time T8 has elapsed, the data written to the nodes FN1 and FN2 are respectively retained. In the period p3 after the time T8 has elapsed, the data written to the nodes FN1 and FN2 are respectively retained.

[0128] As described above, by the writing operation explained in the timing chart of FIG. 5, multi - valued data can be written to the nodes FN1 and node FN2.

[0129] H1 The potential V applied to the word line WLOS1 in the period p1 is preferably higher than the potential obtained by adding the threshold voltage of the transistor 101 to the potential V1. The potential V applied to the word line WLOS1 in the period p1 is preferably higher than the potential obtained by adding the threshold voltage of the transistor 101 to the potential V1.

[0130] Similarly, in the period p2, the potential V applied to the word line WLOS2 H1 is preferably higher than the potential obtained by adding the threshold voltage of the transistor 105 to the potential V2. is preferably higher than the potential obtained by adding the threshold voltage of the transistor 105 to the potential V2.

[0131] 〈〈Read operation〉〉 Read the data written to the memory cell 110 along the timing chart of FIG. 6. The operation will be described.

[0132] Figure 6 is composed of four periods from period p3 to p6. Period p3 is the period for continuously holding the data from period p3 in Figure 5. Period p4 is the period for reading the data of node FN1. Period p 5 is the period for reading the data of node FN2. Period p6 is the period for holding the data respectively represented. Also, the times T9 to T15 shown in Figure 6 are attached for explaining the timing of the operation .

[0133] First, at time T9, a potential of L level is applied to word line WLOS1, and a potential of L level is applied to word line W LC1. Due to capacitive coupling, the potential of node FN1 is pulled up from potential V1 - V L2 to potential V1. When the potential of node FN1 is pulled up, the V of the n-channel type transistor 112 becomes large, and the transistor 112 turns on. GS

[0134] Also, at time T9, a potential of L level is applied to word line WLOS2, and a potential of H level is applied to word line WLC 2. Due to capacitive coupling, the potential of node FN2 is pulled up from potential V2 - V L 2 to potential V2 + V H2 . When the potential of node FN2 is pulled up, the V of the n-channel type transistor 113 becomes large, and the transistor 113 turns on GS .

[0135] Next, at time T10, the bit line BL becomes electrically floating. That is, the bit line BL becomes a state where its potential fluctuates due to charging or discharging of charges. This state can be realized by turning off the switch for applying a potential to the bit line BL.

[0136] Also, at time T10, an H-level potential is applied to the power supply line SL. When an H-level potential is applied to the power supply line SL, a potential difference is generated between the bit line BL and the power supply line SL, and current flows from the power supply line SL to the bit line BL. The bit line BL is charged, and the potential of the bit line BL rises .

[0137] When the potential of the bit line BL rises due to charging, the V of transistor 112 GS and the V of transistor 113 both decrease. When the V of either one of the transistors GS becomes equal to the threshold voltage of that GS transistor, the charging is completed, and the potential of the bit line BL converges to a certain potential. In period p4, since a higher potential is applied to node FN2 than to node FN1, the V of transistor 113 is larger than the V of transistor 112 . That is, transistor 113 has a lower channel resistance and a larger on-current than transistor 112. Therefore, when the charging of the bit line BL starts, the V of transistor 112 GS reaches the threshold voltage first, and transistor 112 turns off first. . That is, transistor 113 has a lower channel resistance and a larger on-current than transistor 112. Therefore, when the charging of the bit line BL starts, the V of transistor 112 GS reaches the threshold voltage first, and transistor 112 turns off first. When transistor 112 turns off, the bit line BL converges to a certain potential (potential V1´). This potential V1´ can be obtained as a value obtained by subtracting the threshold voltage of transistor 112 from the potential of node FN1. That is, the potential V1´ of the bit line BL is obtained in a form that reflects the level of the potential of node FN1. By using this potential difference for data determination, multi-valued data written to node FN

[0138] 1 can be read out. This potential V1´ can be obtained as a value obtained by subtracting the threshold voltage of transistor 112 from the potential of node FN1. That is, the potential V1´ of the bit line BL is obtained in a form that reflects the level of the potential of node FN1. By using this potential difference for data determination, multi-valued data written to node FN 1 can be read out. 1 can be read out. By using this potential difference for data determination, multi-valued data written to node FN 1 can be read out.

[0139]

[0139] Next, at time T11, the bit line BL and the power supply line SL are initialized to the potential V GND . .

[0140] Next, at time T12, a high-level potential is applied to the word line WLC1, and due to capacitive coupling, the potential of the node FN1 is pulled up from the potential V1 to the potential V1+V H2 . Also simultaneously, a low-level potential is applied to the word line WLC2, and the potential of the node FN2 is pulled down from the potential V2+V H2 to the potential V2. Transistors 112 and 113 both turn on. .

[0141] Next, at time T13, the bit line BL becomes electrically floating.

[0142] Also simultaneously, at time T13, a high-level potential is applied to the power supply line SL. When the potential of the power supply line SL becomes high level, a potential difference is generated between the bit line BL and the power supply line SL, and current flows from the power supply line SL to the bit line BL. The bit line BL is charged and the potential of the bit line BL rises. .

[0143] When the potential of the bit line BL rises due to charging, the V GS of transistor 112 and the V of transistor 113 both decrease. When the V GS of either one of the transistors becomes equal to the threshold voltage of that GS transistor, the charging is completed and the potential of the bit line BL converges to a certain potential. During period p5, since a higher potential is applied to the node FN1 than to the node FN2, the V of transistor 112 is larger than that of transistor 113. Thus, GS ​​​​Moreover, the channel resistance of transistor 112 is lower and the on-current is larger than those of transistor 113. Therefore, when the charging of bit line BL starts, the V of transistor 113 reaches the threshold voltage first, and transistor 113 turns off first. When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out. GS When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out.

[0144] When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out. When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out. When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out. When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out. When transistor 113 turns off, bit line BL converges to a certain potential (potential V2´). This potential V2´ is obtained as a value obtained by subtracting the threshold voltage of transistor 113 from the potential of node FN2. That is, the potential V2´ of bit line BL can be obtained in a form that reflects the level of the potential of node FN2. By using this potential difference for data determination, multi-valued data written to node FN2 can be read out.

[0145] Next, at time T14, bit line BL and power supply line SL are initialized to potential V. GND Next, at time T14, bit line BL and power supply line SL are initialized to potential V. Next, at time T14, bit line BL and power supply line SL are initialized to potential V.

[0146] Next, at time T15, the same potential as period p3 is applied to all the wirings and nodes in FIG. 6, and the potentials of nodes FN1 and FN2 are held. Next, at time T15, the same potential as period p3 is applied to all the wirings and nodes in FIG. 6, and the potentials of nodes FN1 and FN2 are held.

[0147] As described above, by the read operation explained in the timing chart of FIG. 6, multi-valued data written to nodes FN1 and FN2 can be read out. As described above, by the read operation explained in the timing chart of FIG. 6, multi-valued data written to nodes FN1 and FN2 can be read out.

[0148] For example, consider the case of writing 8-bit data, that is, 256 (=2 8 ) values of potential to one node. In that case, if the width of the potential of one value is 0.17V, the width of the potential applied to the node holding the data is 0.17V × 256 = 43.52V. That is, For example, consider the case of writing 8-bit data, that is, 256 (=2 ) values of potential to one node. In that case, if the width of the potential of one value is 0.17V, the width of the potential applied to the node holding the data is 0.17V × 256 = 43.52V. That is, To store 8-bit data in one node, a power supply potential of approximately 45V needs to be applied to the memory cell However, this power supply potential is not a realistic value because it causes transistor breakdown.

[0149] On the other hand, when writing 8-bit data to the memory cell 110 shown in this embodiment, the 8 bit data is divided into two 4-bit data, and one can be stored in node FN1 and the other in node FN2. Therefore, one node bears the potential of 16(=2 4 ) values If the width of the potential of one value is 0.17V, the width of the potential applied to one node is 0.17V×16 = 2.72V. This is a realistic value for driving the memory cell.

[0150] As described above, by using the memory cell 110 which is one aspect of the present invention, it becomes possible to provide a semiconductor device that stores 8-bit data. Also, the number of bits of data that the memory cell 110 can store is not limited to 8 bits, and it can store data of various bit numbers. For example, when storing M-bit (2 value) data in node FN1 and N-bit (2 value) data in node FN 2, the memory cell 110 can store M + N-bit (2 M value) data. 2, the memory cell 110 can store M + N-bit (2 N value) data. M+N value) data.

[0151] The memory cell 110 in FIG. 4 may be given a common signal BG to the second gates of transistors 101 and 105 as shown in the circuit diagram of FIG. 21(B).

[0152] The memory cell 110 in FIG. 4 may be configured with the circuit diagram shown in FIG. 22(B). FIG. 22(B) The circuit diagram shown has two bit lines BL1 and BL2, and the point where the transistor 1 01 and the transistor 105 are connected to the common word line WLOS is different from the circuit diagram in FIG. 4. Also, a common signal may be applied to the second gates of the transistor 101 and the transistor 105 shown in FIG. 22(B) in the same manner as in FIG. 21(B). Also, in some cases, these second gates may be omitted.

[0153] The memory cell 110 in FIG. 4 may be configured with the circuit diagram shown in FIG. 23(B). FIG. 23(B) The circuit diagram shown has the transistor 107, the capacitor element 108, the transistor 114, the node F N3, the word line WLOS3, and the word line WLC3, and is different from the circuit diagram shown in FIG. 4 . Also, a common signal may be applied to the second gates of the transistor 101, the transistor 105 and the second gate of the transistor 107 shown in FIG. 23(B) in the same manner as in FIG. 21(B). Also, in some cases, these second gates may be omitted.

[0154] Note that in this embodiment, one aspect of the present invention has been described. Or, in other embodiments one aspect of the present invention is described. However, one aspect of the present invention is not limited to these. For example, as one aspect of the present invention, an example when applied to a memory cell is shown, but one aspect of the present invention is not limited to this. In some cases, or depending on the situation, one aspect of the present invention may not be applied to the memory cell. For example, one aspect of the present invention may be applied to a circuit having another function .

[0155] ​Note that the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments. They can be used in appropriate combination with those shown in other embodiments.

[0156] (Embodiment 3) In this embodiment, an example of a semiconductor device capable of performing the driving method described in Embodiment 1 will be described with reference to the drawings. An example of a semiconductor device capable of performing the driving method described in Embodiment 1 will be described with reference to the drawings.

[0157] <Configuration Example of Semiconductor Device> FIG. 7 is a block diagram showing a configuration example of a semiconductor device having the memory cell 100 described in Embodiment 1. It is a block diagram.

[0158] The semiconductor device 500 shown in FIG. 7 includes a memory cell array 501 in which a plurality of the memory cells 100 described in FIG. 4 are provided, a row selection driver 502, a column selection driver 503, and an A / D converter 504. Note that the semiconductor device 500 has memory cells 100 provided in an m-row (m is a natural number of 2 or more) by n-column (n is a natural number of 2 or more) matrix. Further, in FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. The semiconductor device 500 shown in FIG. 7 includes a memory cell array 501 in which a plurality of the memory cells 100 described in FIG. 4 are provided, a row selection driver 502, a column selection driver 503, and an A / D converter 504. Note that the semiconductor device 500 has memory cells 100 provided in an m-row (m is a natural number of 2 or more) by n-column (n is a natural number of 2 or more) matrix. Further, in FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. The semiconductor device 500 shown in FIG. 7 includes a memory cell array 501 in which a plurality of the memory cells 100 described in FIG. 4 are provided, a row selection driver 502, a column selection driver 503, and an A / D converter 504. Note that the semiconductor device 500 has memory cells 100 provided in an m-row (m is a natural number of 2 or more) by n-column (n is a natural number of 2 or more) matrix. Further, in FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. The semiconductor device 500 shown in FIG. 7 includes a memory cell array 501 in which a plurality of the memory cells 100 described in FIG. 4 are provided, a row selection driver 502, a column selection driver 503, and an A / D converter 504. Note that the semiconductor device 500 has memory cells 100 provided in an m-row (m is a natural number of 2 or more) by n-column (n is a natural number of 2 or more) matrix. Further, in FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown. In FIG. 7, word lines WLOS1[m-1], word line WLC1[m-1], word line WLOS2[m-1], and word line WLC2[m-1] are shown as word lines connected to the memory cells 100 in the (m-1)-th row, word lines WLOS1[m], word line WLC1[m], word line WLOS2[m], and word line WLC2[m] are shown as word lines connected to the memory cells 100 in the m-th row, bit line BL[n-1] and bit line BL[n] connected to the memory cells 100 in the (n-1)-th column and n-th column are shown, and power supply lines SL connected to the memory cells 100 in the (n-1)-th column and n-th column are shown.

[0159] The memory cell array 501 shown in FIG. 7 has the memory cells 100 described in FIG. 4 arranged in a matrix The description of each component of the memory cell 100 is the same as that in FIG. 4 and the description is omitted by referring to the description in FIG. 4

[0160] In the memory cell array 501 shown in FIG. 7, adjacent memory cells share the power supply line SL By adopting this configuration, the area occupied by the power supply line SL can be reduced Therefore, in a semiconductor device adopting this configuration, the storage capacity per unit area can be improved

[0161] The row selection driver 502 is a circuit having a function of selectively turning on the transistors 101 and 105 in each row of the memory cell 100, and a function of selectively changing the potentials of the nodes FN1 and FN2 in each row of the memory cell 100 By providing the row selection driver 502, the semiconductor device 500 can selectively perform writing and reading of data to the memory cell 100 for each row

[0162] The column selection driver 503 is a circuit having a function of selectively writing data to the nodes FN1 and FN2 in each column of the memory cell 100, a function of initializing the potential of the bit line BL, and a function of electrically floating the bit line BL Specifically, it is a circuit that supplies a potential corresponding to multi-valued data and the potential V to the bit line BL via a switch GND By providing the column selection driver 503, the semiconductor device 500 can selectively perform writing and reading of data to the memory cell 100 for each column

[0163] ​​​​​​​ The A / D converter 504 is a circuit having a function of converting the potential of the bit line BL, which is an analog value, into a digital value and outputting it externally. Specifically, it is a circuit having a flash type A / D converter. By providing the A / D converter 504, the semiconductor device 500 can output externally the potential of the bit line BL corresponding to the data read from the memory cell 100.

[0164] Although the A / D converter 504 is described as a flash type A / D converter, a successive approximation type, a multi-slope type, or a delta-sigma type A / D converter may be used.

[0165] FIG. 8 shows the memory cell 100 in FIG. 7 replaced with the memory cell 110 described in Embodiment 2. For details, refer to the description of FIG. 7.

[0166] The semiconductor device 500 shown in FIGS. 7 and 8 may be configured by the block diagram shown in FIG. 24. The block diagram shown in FIG. 24 shows the case where the second gates of the transistors connected to the same word line are connected to a common wiring. The second gate of the transistor connected to the word line WLOS1[m-1] is connected to the wiring to which the signal BG1[m-1] is applied. The second gate of the transistor connected to the word line WLOS2[m-1] is connected to the wiring to which the signal BG2[m-1] is applied. The second gate of the transistor connected to the word line WLOS1[m] is connected to the wiring to which the signal BG1[m] is applied. The second gate of the transistor connected to the word line WLOS2[m] is connected to the wiring to which the signal BG2[m] is applied. The signal BG1[m-1] and the signal BG2[m-1] are It may be a common signal or different signals. Similarly, signal BG1[m] and signal BG2 m] may be a common signal or different signals.

[0167] The semiconductor device 500 shown in FIGS. 7 and 8 may be configured by the block diagram shown in FIG. 25. FIG The block diagram shown in FIG. 25 is such that all the second gates included in the memory cell array 501 are connected to a common wiring and a common signal BG is applied.

[0168] <Configuration Example of Row Selection Driver> FIG. 9 is a block diagram showing a configuration example of the row selection driver 502 described with reference to FIGS. 7 and 8.

[0169] The row selection driver 502 shown in FIG. 9 includes a decoder 517 and a read / write control circuit 518. The read / write control circuit 518 is connected to word lines WLOS1, WLC1, W LOS2, WLC2 and is provided for each row.

[0170] The decoder 517 is a circuit having a function of outputting a signal for selecting a row where word lines are provided. Specifically, an address signal Address is input, and it is a circuit that selects one of the read / write control circuits 518 according to the address signal A ddress. By providing the decoder 517, the row selection driver 502 can select an arbitrary row and perform data writing or reading.

[0171] The read / write control circuit 518 is a circuit having a function of outputting a write word signal for a row having a word line selected by the decoder 517 and a function of selectively outputting a read word signal . Specifically, the read / write control circuit 518 is a write control signal ​ Write_CONT and the read control signal Read_CONT are input, and according to these signals it is a circuit that selectively outputs a write signal or a read signal. By providing the read / write control circuit 518, the row selection driver 502 can select and output a write word signal or a read word signal in the row selected by the decoder 517.

[0172] <Example configuration of column selection driver> FIG. 10 is a block diagram showing an example configuration of the column selection driver 503 described in FIGS. 7 and 8. It is as follows.

[0173] The column selection driver 503 shown in FIG. 10 includes a decoder 521, a latch circuit 522, a D / A converter 523, a switch circuit 524, and a transistor 526. Each of the aforementioned circuits and the transistor are provided for each column. Also, the switch circuit 524 and the transistor 526 of each column are connected to the bit line BL.

[0174] The decoder 521 is a circuit having a function of selecting a column in which the bit line BL is provided and distributing and outputting the input data. Specifically, it is a circuit to which an address signal Address and data Data are input, and according to the address signal Address, the data Data is output to the latch circuit 522 of any column. By providing the decoder 521, the column selection driver 503 can select any column and perform data writing. It should be noted that the data Data input to the decoder 521 is k-bit digital data.

[0175] The k-bit digital data is binary data represented by '1' or '0' for each bit. The k-bit digital data is a signal represented by binary data of '1' or '0' for each bit. Specifically, for 2-bit digital data, the codes are '00', '01', and '1 The data is represented by '0' and '11'.

[0176] The latch circuit 522 is a circuit that has a function of temporarily storing input data. Specifically, when a latch signal W_LAT is input, the stored data Data is A flip-flop circuit outputs to the D / A converter 523 according to the latch signal W_LAT. By providing the latch circuit 522, the column selection driver 503 can Data can be written.

[0177] The D / A converter 523 converts the input digital data (Data) into an analog data (Data). Data V data Specifically, the D / A converter 523 is a circuit that has the function of converting If the number of bits of the data Data is 3 bits, then the potentials V0 to V7 are set to eight levels. The D / A converter 524 converts the digital signal into one of the three digital values and outputs it to the switch circuit 524. 23, the column selection driver 503 selects data to be written to the memory cell 110 as follows: The potential can correspond to multi-value data.

[0178] The data V output from the D / A converter 523 data are expressed in different voltage values. In the case of 2-bit data, it is 0.5V, 1.0V, 1.5V, and 2.0V. The data is expressed as one of four voltage values.

[0179] The switch circuit 524 receives the input data V data to the bit line BL, and It is a circuit having a function of electrically floating the bit line BL. Specifically, it includes an analog switch and an inverter, and under the control of a switch control signal Write_SW, data V data is applied to the bit line BL, and then the analog switch is turned off to make it electrically floating. By providing the switch circuit 524, the column selection driver 503 can hold the bit line BL in an electrically floating state after applying data V data to the bit line BL.

[0180] The transistor 526 is a circuit having a function of applying a potential V GND for initialization to the bit line BL and a function of electrically floating the bit line BL. Specifically, under the control of an initialization control signal Init_EN, the potential V is applied to the bit line BL, and then it is a switch that makes the GND bit line BL electrically floating. By providing the transistor 526, the column selection driver 503 can hold the bit line BL in an electrically floating state after applying the potential V to the bit line BL. GND

[0181] <Example Configuration of A / D Converter> FIG. 11 is a block diagram showing an example configuration of the A / D converter 504 described in FIG. 8.

[0182] The A / D converter 504 shown in FIG. 11 includes a comparator 531, an encoder 532, a latch circuit 533, and a buffer 534. Each of the aforementioned circuits and transistors is provided for each column. Also, the buffer 534 of each column outputs data Dout.

[0183] ​​​​​​The comparator 531 compares the potential of the bit line BL with the reference voltages Vref0 to Vref6. The potential of the bit line BL is compared to the high potential, and the potential of the bit line BL is determined to be one of the potentials corresponding to the multi-value data. Specifically, the circuit is provided with a plurality of comparators 531, Each comparator 531 receives the potential of the bit line BL and different reference voltages Vref0 to Vref6 is applied, and it is determined whether the potential of the bit line BL is between any of the potentials. By providing the comparator 531, the A / D converter 504 It is possible to determine whether the potential of BL corresponds to any one of the multi-value data.

[0184] As an example, the reference voltages Vref0 to Vref6 shown in FIG. This is the potential given when the data is one bit, i.e., eight values.

[0185] The encoder 532 judges the potential of the bit line BL output from the comparator 531. It is a circuit that has the function of generating a multi-bit digital signal based on a signal. , and encoding is performed based on the H level or L level signals output from the multiple comparators 531. The A / D converter 532 is a circuit that generates a digital signal. The converter 504 converts the data read from the memory cell 110 into digital value data. It is possible.

[0186] The latch circuit 533 is a circuit having a function of temporarily storing input digital value data. Specifically, a latch signal LAT is input, and the stored data is latched by the latch signal LAT. The latch circuit 53 is a flip-flop circuit that outputs to the buffer 534 according to the LAT. By including 3, the A / D converter 504 can output data at any timing. The latch circuit 533 can be omitted.

[0187] The buffer 534 is a circuit having a function of amplifying the data output from the latch circuit 533 and outputting it as an output signal Dout. Specifically, it is a circuit having an even number of inverter circuits. By including the buffer 534, the A / D converter 504 can reduce noise with respect to the digital signal. The buffer 534 can be omitted.

[0188] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0189] (Embodiment 4) In the present embodiment, an example of a semiconductor device capable of realizing the circuits of the memory cell 100 and the memory cell 110 will be described with reference to FIG. 12.

[0190] <Configuration Example of Semiconductor Device> The semiconductor device shown in FIG. 12 includes a substrate 2000, a transistor 101, a transistor 122, a transistor 123, a transistor 105, a capacitor element 104, a capacitor element 106, an insulating film 2001, an insulating film 2002, an insulating film 2003, an insulating film 2004, an insulating film 2005, an insulating film 2006, an insulating film 2007, an insulating film 2008, a plug 2101, a plug 2102, a plug 2103, a plug 2104, a plug 2105, a plug 2106, a plug 2107, a plug 2108, a wiring 2301, a wiring 2302, a wiring 2501, a wiring 2502, a conductive film 2701, and a conductive film 2702. It is.

[0191] In addition, when realizing the memory cell 100 in FIG. 12, in the following description, the transistor 122 is replaced with the transistor 102, and the transistor 123 is replaced with the transistor 103 That's all. Similarly, when realizing the memory cell 110 in FIG. 12, in the following description, the transistor 122 is replaced with the transistor 112, and the transistor 123 is replaced with the transistor 11 3.

[0192] The transistors 122 and 123 have a gate electrode 2205, a gate insulating film 2204, sidewall insulating layer 2206, an impurity region 2203 that functions as a source region or a drain region, an impurity region 2202 that functions as an LDD (Lightly Doped Drain) region or an extension region, and a channel formation region 2201. have.

[0193] The capacitor element 104 has a first electrode 2401, a second electrode 2402, and an insulating film 2403. have.

[0194] The capacitor element 106 has a first electrode 2601, a second electrode 2602, and an insulating film 2603. have.

[0195] The conductive film 2701 is composed of a conductive film formed through a process of processing the same conductive film as the source electrode or drain electrode of the transistor 101 and a semiconductor layer formed through a process of processing the same semiconductor layer as the semiconductor layer of the transistor 101. are composed of.

[0196] The conductive film 2702 is composed of a conductive film formed through a process of processing the same conductive film as the source electrode or drain electrode of the transistor 105 and a semiconductor layer formed through a process of processing the same semiconductor layer as the semiconductor layer of the transistor 105. It is composed of a semiconductor layer formed through a process of processing a layer.

[0197] In FIG. 12, when there are a plurality of plugs in the same layer, only one representative plug is assigned a symbol, and the others use this symbol in combination. Similarly, when there are a plurality of wirings in the same layer, only one representative wiring is assigned a symbol, and the others use this symbol in combination. Similarly, when there are a plurality of conductive films in the same layer, only one representative conductive film is assigned a symbol, and the others use this symbol in combination. .

[0198] FIG. 12 shows terminals respectively connected to a bit line BL, a power supply line SL, a word line WLOS1, a word line WLOS 2, a word line WLC1, and a word line WLC2.

[0199] In the semiconductor device shown in FIG. 12, transistors 122 and 123 are provided on a substrate 2000, a capacitor element 104 is provided on the transistors 122 and 123, a transistor 101 is provided on the capacitor element 104, a transistor 105 is provided on the transistor 101, and a capacitor element 106 is provided on the transistor 105. Note that the vertical relationship of these elements is not limited to this. For example, the capacitor element 106 may be provided on the transistor 101, and the transistor 105 may be provided on the capacitor element 106.

[0200] As the substrate 2000, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon on Insulator) substrate, etc. can be used. It can be formed using a semiconductor substrate. ​​​​​​​​The obtained transistor is easy to operate at high speed. When a p-type single crystal silicon substrate is used as the substrate 2000, an impurity element for imparting an n-type is added to a part of the substrate 2000 to form an n type well, and a p-type transistor can be formed in the region where the n-type well is formed. As the impurity element for imparting an n-type, phosphorus (P), arsenic (As), etc. can be used. As the impurity element for imparting a p-type, boron (B), etc. can be used.

[0201] Further, the substrate 2000 may be a substrate having a semiconductor film provided on an insulating substrate or a metal substrate. Examples of the metal substrate include a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, etc. Examples of the insulating substrate include, for example, a glass substrate, a quartz substrate, a plastic substrate, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate include synthetic resins having flexibility such as polyethylene terephthalate (PET), poly ethylene naphthalate (PEN), polyethersulfone (PES), or acrylic. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Examples of the base film include polyester, polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, or papers.

[0202] Note that a semiconductor element is formed using a certain substrate, and then the semiconductor element is transferred to another substrate. This is also possible. As an example of the substrate on which the semiconductor element is inverted, in addition to the substrates described above, there are paper substrates, ceramic substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), leather substrates, or rubber substrates, etc. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture durable devices, impart heat resistance, reduce weight, or make the device thinner.

[0203] It is preferable to use a first semiconductor material for the channels of transistors 122 and 123. Also, it is preferable to use a second semiconductor material for the channels of transistors 101 and 105. The first semiconductor material and the second semiconductor material are preferably materials having different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.), and the second semiconductor material can be an oxide semiconductor. Transistors using single-crystalline silicon or the like as the semiconductor material are easy to operate at high speed. On the other hand, transistors using an oxide semiconductor have a small off-current.

[0204] Details of transistors 101 and 105 will be described in Embodiment 4.

[0205] As transistors 122 and 123, transistors having silicide (salicide), A transistor without the sidewall insulating layer 2206 may be used. Silicide (salicide) In the structure having it, the source region and the drain region can have lower resistance, and the semiconductor device can operate at high speed. Also, since it can operate at a low voltage, the power consumption of the semiconductor device can be reduced is possible.

[0206] The transistors 122 and 123 may be either an n-channel type transistor or a p-channel type transistor, and an appropriate transistor may be used depending on the circuit. Also the impurity concentration of the impurity region 2203 is higher than that of the impurity region 2202. Using the gate electrode 2 205 and the sidewall insulating layer 2206 as masks, the impurity region 2203 and the impurity region 2202 can be formed self-alignedly.

[0207] When a silicon-based semiconductor material is used for the transistors 122 and 123, the insulating film 2001 and the insulating film 2002 preferably contain hydrogen. By providing an insulating film containing hydrogen on the transistors 122 and 123 and performing heat treatment, the dangling bonds in the semiconductor film are terminated by the hydrogen in these insulating films, and the reliability of the transistors 122 and 123 can be improved is possible.

[0208] As the insulating films 2001 and 2002, for example, silicon oxide, silicon oxynitride, nitrogen oxide silicon, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide aluminum, aluminum nitride, etc. may be used, and they may be provided in a laminated or single-layer form.

[0209] When an oxide semiconductor is used for the transistors 101 and 105, the above-described insulating films 2001 and 2 Since the hydrogen in 002 is one of the factors that generate carriers in the oxide semiconductor, it may be a factor that reduces the reliability of the transistors 101 and 105. Therefore, it is particularly effective to provide insulating films 2003 and 2006 having a function of preventing the diffusion of hydrogen between the transistors 101 and 105 and the transistors 122 and 123. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time. It may be a factor that reduces the reliability of the transistors 101 and 105. Therefore, it is particularly effective to provide insulating films 2003 and 2006 having a function of preventing the diffusion of hydrogen between the transistors 101 and 105 and the transistors 122 and 123. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time. It is particularly effective to provide insulating films 2003 and 2006 having a function of preventing the diffusion of hydrogen between the transistors 101 and 105 and the transistors 122 and 123. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time. It is particularly effective to provide insulating films 2003 and 2006 having a function of preventing the diffusion of hydrogen between the transistors 101 and 105 and the transistors 122 and 123. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time. By confining hydrogen in the lower layer with the insulating films 2003 and 2006, the reliability of the transistors 122 and 123 is improved, and in addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistors 101 and 105 can be improved at the same time.

[0210] As the insulating films 2003 and 2006, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used. In particular, the aluminum oxide film is preferable because it has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen. As the insulating films 2003 and 2006, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used. In particular, the aluminum oxide film is preferable because it has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen. As the insulating films 2003 and 2006, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used. In particular, the aluminum oxide film is preferable because it has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen. As the insulating films 2003 and 2006, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used. In particular, the aluminum oxide film is preferable because it has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen. As the insulating films 2003 and 2006, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used. In particular, the aluminum oxide film is preferable because it has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen.

[0211] The insulating films 2004 and 2007 are preferably made of a material in which water and hydrogen do not easily diffuse, similar to the insulating films 2003 and 2006. In particular, it is preferable to use a material that does not easily permeate oxygen. By covering the oxide semiconductor film with an insulating film that does not easily permeate oxygen, the release of oxygen from the oxide semiconductor film beyond the insulating film can be suppressed. The insulating films 2004 and 2007 are preferably made of a material in which water and hydrogen do not easily diffuse, similar to the insulating films 2003 and 2006. In particular, it is preferable to use a material that does not easily permeate oxygen. By covering the oxide semiconductor film with an insulating film that does not easily permeate oxygen, the release of oxygen from the oxide semiconductor film beyond the insulating film can be suppressed. The insulating films 2004 and 2007 are preferably made of a material in which water and hydrogen do not easily diffuse, similar to the insulating films 2003 and 2006. In particular, it is preferable to use a material that does not easily permeate oxygen. By covering the oxide semiconductor film with an insulating film that does not easily permeate oxygen, the release of oxygen from the oxide semiconductor film beyond the insulating film can be suppressed. The insulating films 2004 and 2007 are preferably made of a material in which water and hydrogen do not easily diffuse, similar to the insulating films 2003 and 2006. In particular, it is preferable to use a material that does not easily permeate oxygen. By covering the oxide semiconductor film with an insulating film that does not easily permeate oxygen, the release of oxygen from the oxide semiconductor film beyond the insulating film can be suppressed.

[0212] In addition, the insulating films 2004 and 2007, which do not easily permeate water and hydrogen, can suppress the mixing of water and hydrogen, which are impurities for the oxide semiconductor from the outside, and the transistors 101 and 10 In addition, the insulating films 2004 and 2007, which do not easily permeate water and hydrogen, can suppress the mixing of water and hydrogen, which are impurities for the oxide semiconductor from the outside, and the transistors 101 and 10 Variations in the electrical characteristics of 5 can be suppressed, and a highly reliable transistor can be realized.

[0213] The insulating film 2005 has a function of protecting the transistor 101, and the insulating film 2008 has a function of protecting the transistor 105. The insulating films 2005 and 2008 may be insulating films containing one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Further, the insulating films 2005 and 2008 may be a laminate of the above materials. Note that the insulating films 2005 and 2008 may not be provided in some cases.

[0214] The wiring 2301 functions as the second gate electrode of the transistor 101. The wiring 23 01 may be supplied with a certain potential, or the same potential or the same signal as the first gate electrode of the transistor 101 may be supplied. The wiring 2302 functions as the second gate electrode of the transistor 105. The wiring 2302 may be supplied with a certain potential, or the same potential or the same signal as the first gate electrode of the transistor 105 may be supplied. Note that the wirings 2301 and 2302 may be omitted in some cases.

[0215] The plugs 2101 to 2108 are made of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum ( Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt A single body, alloy, or compound mainly composed of these made of a low-resistance material of cobalt (Co). It is preferably a single layer or a laminate of a conductive film containing a compound. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that achieves both heat resistance and conductivity. Also, it is preferably formed of a low-resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. Aluminum It is preferably formed of a low-resistance conductive material such as copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. When using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. It is preferably formed of a low-resistance conductive material such as copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable.

[0216] Wiring 2301, 2302, 2501, 2502, the first electrode 2401 of the capacitor element 104, the second electrode 2402 of the capacitor element 104, the first electrode 2601 of the capacitor element 106, and the second electrode 2602 of the capacitor element 106 are preferably a single layer or a laminate of a conductive film containing a single body, alloy, or compound mainly composed of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), or a low-resistance material thereof. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that achieves both heat resistance and conductivity. Also, it is preferably formed of a low-resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. Molybdenum (Mo) Gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), or a low-resistance material thereof. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that achieves both heat resistance and conductivity. Also, it is preferably formed of a low-resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. A single body, alloy, or compound mainly composed of these made of a low-resistance material of cobalt (Co). It is preferably a single layer or a laminate of a conductive film containing a compound. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that achieves both heat resistance and conductivity. Also, it is preferably formed of a low-resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. Aluminum It is preferably formed of a low-resistance conductive material such as copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. When using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable. It is preferably formed of a low-resistance conductive material such as copper. Furthermore, when using a Cu-Mn alloy, manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu, which is preferable.

[0217] The insulating film 2403 of the capacitor element 104 and the insulating film 2603 of the capacitor element 106 have a high dielectric constant. It is preferable to use an insulating film. For example, these insulating films may include an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Further, the insulating films 2403 and 2603 may be a laminate of the above materials. Additionally, these insulating films may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities. Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. It is possible to use an insulating film containing one or more of these. In addition, the insulating films 2403 and 2603 may be a laminate of the above materials. Moreover, these insulating films may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities.

[0218] In FIG. 12, the regions without symbols and hatching patterns represent regions composed of insulators. These regions may use an insulator containing one or more selected from aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Also, organic resins such as polyimide resin, polyamide resin, acrylic resin, siloxane resin, epoxy resin, and phenol resin can be used for these regions. Aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. It is possible to use an insulator containing one or more selected from these. In addition, polyimide resin, polyamide resin, acrylic resin, siloxane resin, epoxy resin, phenol resin, etc. can be used for these regions. Acrylic resin, siloxane resin, epoxy resin, phenol resin, etc.

[0219] Note that the transistors 122 and 123 can be not only planar transistors but also transistors of various types. For example, they can be transistors such as FIN (fin) type, TRI-GATE (trigate) type, etc. FIN (fin) type, TRI-GATE (trigate) type, etc. By configuring the memory cell 110 shown in FIG. 4 as the configuration shown in FIG. 12, per memory cell

[0220] By configuring the memory cell 110 shown in FIG. 4 as the configuration shown in FIG. 12, per memory cell​​ The occupied area can be reduced. In addition, since the memory cell 110 can store multi-valued data, by adopting the configuration shown in FIG. 12, a semiconductor device capable of storing a high-density amount of information in a small area can be provided.

[0221] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with those shown in other embodiments.

[0222] (Embodiment 5) <Example of the configuration of an oxide semiconductor transistor> In the present embodiment, an example of a transistor (hereinafter referred to as an OS (Oxide Semiconductor) transistor) using an oxide semiconductor layer for the channel, which is applicable to the transistors 101 and 105 shown in FIG. 12, will be described with reference to FIGS. 13 to 18.

[0223] FIGS. 13(A) to 13(C) are a top view and a cross-sectional view of the OS transistor. FIG. 13(A) is a top view, the cross-section in the direction of the dashed-dotted line A1 - A2 shown in FIG. 13(A) corresponds to FIG. 13(B), and the cross-section in the direction of the dashed-dotted line B1 - B2 shown in FIG. 13(A) corresponds to FIG. 13(C). Note that in FIGS. 13(A) to 13(C), some elements are enlarged, reduced, or omitted for clarity of the drawing. Also, the direction of the dashed-dotted line A1 - A2 may be referred to as the channel length direction, and the direction of the dashed-dotted line B1 - B2 may be referred to as the channel width direction.

[0224] Note that the channel length is, for example, in the top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or in the region where the channel is formed, the distance between the source (source region or source electrode) and the drain ​ Refers to the distance to the in (drain region or drain electrode). Note that in one transistor The channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor May not be determined by one value. Therefore, in this specification, the channel length is defined as any one value, the maximum value, the minimum value, or The average value in the region where the channel is formed.

[0225] The channel width refers to, for example, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is on) overlaps with the gate electrode, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor The channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor May not be determined by one value. Therefore, in this specification, the channel width is defined as any one value, the maximum value, the minimum value, or The average value in the region where the channel is formed.

[0226] Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, In a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the top surface of the semiconductor to the ratio of the channel region formed on the side surface of the semiconductor ​ It may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

[0227] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0228] Therefore, in this specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap, may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". In this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image.

[0229] When calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, it may take a different value from the case of calculating using the effective channel width.

[0230] The OS transistor includes an insulating film 652 on the insulating film 651, a stack formed in the order of a first oxide semiconductor 661 and a second oxide semiconductor 662 on the insulating film 652, a source electrode 671 and a drain electrode 672 that are electrically connected to a part of the stack, a third oxide semiconductor 663 that covers a part of the stack, a part of the source electrode 671, and a part of the drain electrode 672, a gate insulating film 653 and a gate electrode 673 that overlap a part of the stack, a part of the source electrode 671, a part of the drain electrode 672, and a part of the third oxide semiconductor 663, and an insulating film 654 on the source electrode 671, the drain electrode 672, and the gate electrode 673, and an insulating film 655 on the insulating film 654. Here, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 663 are collectively referred to as an oxide semiconductor 660. Note that at least a part (or all) of the source electrode 671 (and / or the drain electrode 672) is provided on at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of any semiconductor layer of the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 672) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 672) is

[0231]

[0232] ​​​​​​​​​​​​​​​It is in contact with at least a part (or all) of a semiconductor layer such as an oxide semiconductor 661).

[0233] Or, at least a part ( or all) of the source electrode 671 (and / or the drain electrode 672) is the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) and is electrically connected to at least a part (or all ) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 672) is electrically connected to a part (or all) of a semiconductor layer such as the second oxide semiconductor 662 (and / or also the first oxide semiconductor 661).

[0234] Or, at least a part ( or all) of the source electrode 671 (and / or the drain electrode 672) is the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) and is disposed in proximity to at least a part (or all ) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 672) is disposed in proximity to a part (or all) of a semiconductor layer such as the second oxide semiconductor 662 (and / or also the first oxide semiconductor 661).

[0235] Or, at least a part ( or all) of the source electrode 671 (and / or the drain electrode 672) is the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) and is disposed in proximity to at least a part (or all ​​) is disposed on the lateral side thereof. Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 6 72) is disposed on the lateral side of at least a part (or all) of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). .

[0236] Or, at least a part ( or all) of the source electrode 671 (and / or the drain electrode 672) is the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) and is disposed obliquely above at least a part (or all ) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 672) is disposed obliquely above at least a part (or all) of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). .

[0237] Or, at least a part ( or all) of the source electrode 671 (and / or the drain electrode 672) is the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) and is disposed above at least a part (or all ) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). Or, at least a part (or all) of the source electrode 671 (and / or the drain electrode 6 72) is disposed above at least a part (or all) of a semiconductor layer such as the second oxide semiconductor 662 (and / or the first oxide semiconductor 661). .

[0238] Note that the functions of the "source" and "drain" of the transistor are realized by transistors with different polarities In the case of adoption or when the direction of current changes in circuit operation, etc., it can be switched. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

[0239] The transistor according to one aspect of the present invention has a top gate structure with a channel length of 10 nm or more and 1000 nm or less, preferably a channel length of 20 nm or more and 500 nm or less, more preferably a channel length of 30 nm or more and 300 nm or less.

[0240] Hereinafter, the components included in the semiconductor device of this embodiment will be described in detail.

[0241] 〈Underlying insulating film〉 The insulating films 651 and 652 serve to prevent the diffusion of impurities from below the insulating film 651, and can also serve to supply oxygen to the oxide semiconductor 660. Therefore, the insulating films 651 and 652 are preferably insulating films containing oxygen, and more preferably insulating films containing more oxygen than the stoichiometric composition. For example, in TDS (Thermal Desorption Spectroscopy) analysis, the amount of oxygen released, converted into oxygen atoms, is 1.0×10 atoms / cm 19 3 or more. In addition, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 10 0°C or more and 500°C or less. Further, as shown in FIG. 12, when other devices are formed under the insulating film 651, the insulating films 651 and 652 are preferably planarized by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat. ​​​​​

[0242] The insulating films 651 and 652 are made of aluminum oxide, magnesium oxide, silicon oxide , silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide and other oxides insulating films, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride any nitride insulating film, or a mixed material thereof can be used for formation.

[0243] 〈Oxide semiconductor〉 The oxide semiconductor 660 typically includes In-Ga oxide, In-Zn oxide, In-M- Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf). In particular, it is preferable to use In-M-Zn oxide as the oxide semiconductor 660.

[0244] However, the oxide semiconductor 660 is not limited to oxides containing indium. The oxide semiconductor 660 may be, for example, ZnO, Zn-Sn oxide, Ga oxide, or Ga-Sn oxide .

[0245] When the oxide semiconductor 660 is an In-M-Zn oxide fabricated by a sputtering method, the atomic ratio of the metal elements of the target used to form the In -M-Zn oxide preferably satisfies In≧M , Zn≧M. As such atomic ratios of the metal elements of the target , In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3 :1:2 are preferable. Note that the atomic ratios of the formed oxide semiconductor 660 each have an error which is plus or minus the atomic ratio of the metal elements contained in the above sputtering target It includes a 40% variation.

[0246] Next, regarding the functions and effects of the oxide semiconductor 660 formed by laminating the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 663, it will be described using the energy band structure diagram shown in FIG. 14(B). FIG. 14(A) is an enlarged view of the channel portion of the OS transistor shown in FIG. 13(B), and FIG. 14(B) shows the energy band structure of the portion indicated by the chain line C1 - C2 in FIG. 14(A). That is, FIG. 14(B) shows the energy band structure of the channel formation region of the OS transistor. 14(B) shows the energy band structure of the channel formation region of the OS transistor. B), and FIG. 14(B) shows the energy band structure of the portion indicated by the chain line C1 - C2 in FIG. 14(A). That is, FIG. 14(B) shows the energy band structure of the channel formation region of the OS transistor. In FIG. 14(B), Ec652, Ec661, Ec662, Ec663, and Ec653 respectively represent the energies of the lower ends of the conduction bands of the insulating film 652, the first oxide semiconductor 661, the second oxide semiconductor 662, the third oxide semiconductor 663, and the gate insulating film 653. Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as the "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as the ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (ULVA C PHI VersaProbe).

[0247] In FIG. 14(B), Ec652, Ec661, Ec662, Ec663, and Ec653 respectively represent the energies of the lower ends of the conduction bands of the insulating film 652, the first oxide semiconductor 661, the second oxide semiconductor 662, the third oxide semiconductor 663, and the gate insulating film 653. In FIG. 14(B), Ec652, Ec661, Ec662, Ec663, and Ec653 respectively represent the energies of the lower ends of the conduction bands of the insulating film 652, the first oxide semiconductor 661, the second oxide semiconductor 662, the third oxide semiconductor 663, and the gate insulating film 653. Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as the "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as the ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (ULVA

[0248] Here, the difference between the energy of the vacuum level and the lower end of the conduction band (also referred to as the "electron affinity") is the value obtained by subtracting the energy gap from the difference between the energy of the vacuum level and the upper end of the valence band (also referred to as the ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (ULVA C PHI VersaProbe). C PHI VersaProbe). HORIBA JOBIN YVON UT - 300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (ULVA C PHI VersaProbe). iolet Photoelectron Spectroscopy) apparatus (ULVA C PHI VersaProbe).

[0249] Note that the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2 is approximately 3.5 eV, and the electron affinity is approximately 4 .5 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:4 is approximately 3.4 eV, and the electron affinity is approximately 4.5 eV. Further, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:6 is approximately 3.3 eV, and the electron affinity is approximately 4.5 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:2 is approximately 3.9 eV, and the electron affinity is approximately 4.3 eV. Additionally, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:8 is approximately 3.5 eV, and the electron affinity is approximately 4.4 eV. Further, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:10 is approximately 3.5 eV, and the electron affinity is approximately 4.5 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:1:1 is approximately 3.2 eV , and the electron affinity is approximately 4.7 eV. Additionally, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 is approximately 2.8 eV , and the electron affinity is approximately 5.0 eV. Further, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:6:10 is approximately 3.5 eV, and the electron affinity is approximately 4.5 eV. Also, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:1:1 is approximately 3.2 eV and the electron affinity is approximately 4.7 eV. Additionally, the energy gap of the In-Ga-Zn oxide formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 is approximately 2.8 eV and the electron affinity is approximately 5.0 eV.

[0250] Since the insulating film 652 and the gate insulating film 653 are insulators, Ec653 and Ec652 are closer to the vacuum level (have a smaller electron affinity) than Ec661, Ec662, and Ec663. .

[0251] Also, Ec661 is closer to the vacuum level than Ec662. Specifically, Ec661 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more higher than Ec662, and is closer to the vacuum level by 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. This is preferably the case.

[0252] Also, Ec663 is closer to the vacuum level than Ec662. Specifically, Ec663 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more higher than Ec662, and is closer to the vacuum level by 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. This is preferably the case.

[0253] Also, in the vicinity of the interface between the first oxide semiconductor 661 and the second oxide semiconductor 662, and in the vicinity of the interface between the second oxide semiconductor 662 and the third oxide semiconductor 663, a mixed region is formed, so the energy at the lower end of the conduction band changes continuously. That is, at these interfaces, there are no or almost no levels.

[0254] Therefore, in the stacked structure having such an energy band structure, electrons mainly move through the second oxide semiconductor 662. Therefore, even if there are levels at the interface between the first oxide semiconductor 661 and the insulating film 652 or at the interface between the third oxide semiconductor 663 and the gate insulating film 653, these levels have little effect on the movement of electrons. Also, the first oxide ​The interface between the first oxide semiconductor 661 and the second oxide semiconductor 662, and the third oxide semiconductor 663 Since there are few or no energy levels at the interface between the third oxide semiconductor 663 and the second oxide semiconductor 662, electron movement in this region is not inhibited. Therefore, an OS transistor having the stacked structure of the above oxide semiconductors can achieve high field-effect mobility.

[0255] As shown in FIG. 6, although trap levels Et600 due to impurities or defects may be formed near the interface between the first oxide semiconductor 661 and the insulating film 652 and near the interface between the third oxide semiconductor 663 and the gate insulating film 653, the presence of the first oxide semiconductor 661 and the third oxide semiconductor 663 can keep the second oxide semiconductor 662 away from the trap levels.

[0256] In particular, in the OS transistor exemplified in this embodiment, in the channel width direction, the upper surface and the side surface of the second oxide semiconductor 662 are in contact with the third oxide semiconductor 663, and the lower surface of the second oxide semiconductor 662 is in contact with the first oxide semiconductor 661 (see FIG. 13(C)). By configuring to cover the second oxide semiconductor 662 with the first oxide semiconductor 661 and the third oxide semiconductor 663 in this way, the influence of the trap levels can be further reduced.

[0257] However, when the energy difference between Ec661 or Ec663 and Ec662 is small, electrons in the second oxide semiconductor 662 may reach the trap levels across the energy difference. When electrons are trapped at the trap levels, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. ​​​​​​​​​​​​​

[0258] Therefore, when the energy differences between Ec661 and Ec663 and Ec662 are each 0 .1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and the electrical characteristics of the transistor can be made good, which is preferable . .

[0259] Also, the band gaps of the first oxide semiconductor 661 and the third oxide semiconductor 663 are preferably wider than the band gap of the second oxide semiconductor 662 .

[0260] For the first oxide semiconductor 661 and the third oxide semiconductor 663, materials containing, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at an atomic number ratio higher than that of the second oxide semiconductor 662 can be used. Specifically, the atomic number ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since the aforementioned elements strongly bond with oxygen, they have a function of suppressing the occurrence of oxygen deficiency in the oxide semiconductor. That is, it can be said that the first oxide semiconductor 661 and the third oxide semiconductor 663 are less likely to have oxygen deficiency than the second oxide semiconductor 66 2 . Also, when the third oxide semiconductor 663 contains In, In may diffuse into the gate insulating film 653 and cause gate leakage. Therefore, it is preferable to use a material that does not contain In for the third oxide semiconductor 663. For example, gallium oxide is preferable .

[0261] In addition, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 66 3

[0262] Note that the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 66 ​When 3 is an In-M-Zn oxide containing at least indium, zinc, and a metal such as M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), the first oxide semiconductor 661 has an atomic ratio of In:M:Zn = x1:y1:z1, the second oxide semiconductor 662 has an atomic ratio of In:M:Zn = x2:y2:z2, and the third oxide semiconductor 663 has an atomic ratio of In:M:Zn = x3:y3:z3, it is preferable that y1 / x1 and y3 / x3 are greater than y2 / x2. y1 / x1 and y3 / x3 are preferably 1.5 times or more, more preferably 2 times or more, and even more preferably 3 times or more than y2 / x2. At this time, in the second oxide semiconductor 662, when y2 is equal to or greater than x2, the electrical characteristics of the transistor can be stabilized. However, when y2 exceeds 3 times x2, the field-effect mobility of the transistor decreases, so it is preferable that y2 is less than 3 times x2. When excluding Zn and O from the first oxide semiconductor 661 and the third oxide semiconductor 663, the atomic ratio of In and M is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 75 atomic% or more for M. Also, when excluding Zn and O from the second oxide semiconductor 662, the atomic ratio of In and M is preferably 25 atomic% or more for In and less than 75 atomic% for M, more preferably 34 atomic% or more for In and less than 66 atomic% for M. The thicknesses of the first oxide semiconductor 661 and the third oxide semiconductor 663 are 3 nm or more and 100 nm or less. For example, when considering the ratio y1 / x1 and y3 / x3, it is preferred that they are larger than y2 / x2. Specifically, y1 / x1 and y3 / x3 are preferably 1.5 times or more, more preferably 2 times or more, and even more preferably 3 times or more than y2 / x2. Regarding the second oxide semiconductor 662, when y2 is greater than or equal to x2, it can stabilize the electrical properties of the transistor. But when y2 exceeds 3 times x2, the field-effect mobility of the transistor will decrease. So, it is preferred that y2 is less than 3 times x2. In the case of the first and third oxide semiconductors 661 and 663, excluding Zn and O, the atomic ratio of In and M is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 75 atomic% or more for M. For the second oxide semiconductor 662, excluding Zn and O, the atomic ratio of In and M is preferably 25 atomic% or more for In and less than 75 atomic% for M, more preferably 34 atomic% or more for In and less than 66 atomic% for M. The thicknesses of the first oxide semiconductor 661 and the third oxide semiconductor 663 are in the range of 3 nm to 100 nm. That is, when considering the relationship between these ratios, it helps to achieve better transistor performance.

[0263] When excluding Zn and O from the first oxide semiconductor 661 and the third oxide semiconductor 663, the atomic ratio of In and M is preferably such that In is less than 50 atomic% and M is 50 atomic% or more, more preferably In is less than 25 atomic% and M is 75 atomic% or more. For the second oxide semiconductor 662, excluding Zn and O, the atomic ratio of In and M is preferably such that In is 25 atomic% or more and M is less than 75 atomic%, more preferably In is 34 atomic% or more and M is less than 66 atomic%. The thicknesses of the first oxide semiconductor 661 and the third oxide semiconductor 663 are preferably from 3 nm to 100 nm. When considering the composition ratios of In and M in the second oxide semiconductor 662 (excluding Zn and O), it is related to the electrical characteristics of the transistor. In the first and third oxide semiconductors 661 and 663, the atomic ratio of In and M (excluding Zn and O) affects the performance of the semiconductor. The thickness range of the first and third oxide semiconductors 661 and 663 is important for device performance.

[0264] The thicknesses of the first oxide semiconductor 661 and the third oxide semiconductor 663 are 3 nm or more and 100 nm or less.It is set to be 50 nm or less, preferably 3 nm or more and 50 nm or less. Further, the thickness of the second oxide semiconductor 662 is 200 nm or less, preferably 100 nm or less, more preferably 3 nm or more and 50 nm or less. Further, the second oxide semiconductor 662 is preferably thicker than the first oxide semiconductor 661 and the third oxide semiconductor 663.

[0265] In order to impart stable electrical characteristics to a transistor having an oxide semiconductor as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor and make the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor is less than 1× 10 10 17 / cm 3 , preferably less than 1×10 15 / cm 3 , and more preferably less than 1×10 10 13 / cm 3 .

[0266] In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon also contributes to the formation of impurity levels in the oxide semiconductor. The impurity levels become traps and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the layers of the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 663 and at their respective interfaces.

[0267] In order to make the oxide semiconductor intrinsic or substantially intrinsic, SIMS (Secondary ​​​​​In Ion Mass Spectrometry analysis, for example, at a certain depth of an oxide semiconductor or in a certain region of the oxide semiconductor, the silicon concentration is less than 1×1 0 0 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 1 18 atoms / cm 3 . Also, the hydrogen concentration is, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, 2×10 2 20 atoms / cm 3 or less, preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 1 19 atoms / cm 3 , and even more preferably less than 5×10 18 atom s / cm 3 . Also, the nitrogen concentration is, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, 5×10 5 19 atoms / cm 3 or less, preferably less than 5×10 5 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 , and even more preferably less than 5×10 17 atoms / cm 3 .

[0268] Also, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor may be reduced. In order not to reduce the crystallinity of the oxide semiconductor, ​For example, in a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the silicon concentration is 1×10 19 atoms / cm 3 less than, preferably 5×10 18 atom s / cm 3 less than, more preferably 1×10 18 atoms / cm 3 and having a portion less than this is sufficient. Also, for example, in a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the carbon concentration is 1×10 atoms / cm 19 less than, preferably 5 3 ×10 atoms / cm 18 less than, more preferably 1×10 3 atoms / cm 18 less than, and having a portion less than this is sufficient.

[0269] Also, the off-current of the transistor using the oxide semiconductor purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1V, 5V, or 10V, it is possible to reduce the off-current normalized by the channel width of the transistor to several yA / μm to several zA / μm.

[0270] In the OS transistor illustrated in this embodiment, since the gate electrode 673 is formed so as to enclose the oxide semiconductor 660 in the channel width direction in an airtight manner, in addition to the gate electric field from the vertical direction with respect to the oxide semiconductor 660, a gate electric field from the side surface direction is applied (see Fig. 13(C)). That is, the gate electric field is applied to the entire oxide semiconductor, and the current flows through the entire second oxide semiconductor 662 that becomes the channel, and further ​ The current can be increased.

[0271] 〈Gate electrode〉 The gate electrode 673 can be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt ( Co), ruthenium (Ru), an alloy containing the above-described metal elements as components, or an alloy formed by combining the above-described metal elements, etc. Further, the gate electrode 673 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and further a titanium film is formed thereon, a single-layer structure of a Cu-Mn alloy film, a two-layer structure in which a Cu film is laminated on a Cu-Mn alloy film, a three-layer structure in which a Cu film is laminated on a Cu-Mn alloy film and further a Cu-Mn alloy film is laminated thereon, etc. In particular, the Cu-Mn alloy film has a low electrical resistance and can form manganese oxide at the interface with an insulating film containing an oxygen element to prevent the diffusion of Cu, so it is preferable. Further, the gate electrode 673 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide

[0272] Compounds, indium tin oxide containing titanium oxide, indium zinc oxide, and conductive materials with light transmissibility such as indium tin oxide added with silicon oxide can also be applied. Also, a laminated structure of the above-mentioned conductive material with light transmissibility and the above-mentioned metal element can also be formed.

[0273] 〈Gate Insulating Film〉 For the gate insulating film 653, an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. Also, the gate insulating film 653 may be a laminate of the above materials. Note that the gate insulating film 653 may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities.

[0274] Also, an example of the laminated structure of the gate insulating film 653 will be described. The gate insulating film 653 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

[0275] Hafnium oxide has a higher relative dielectric constant than silicon oxide or silicon oxynitride. Therefore, since the physical film thickness can be increased with respect to the equivalent oxide thickness, even when the equivalent oxide thickness is 10 nm or less or 5 nm or less, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized.

[0276] 〈Source Electrode and Drain Electrode〉 The source electrode 671 and the drain electrode 672 can be made of the same material as the gate electrode 673. In particular, the Cu-Mn alloy film is preferable because it has low electrical resistance and can form manganese oxide at the interface with the oxide semiconductor 660 to prevent the diffusion of Cu.

[0277] 〈Protective Insulating Film〉 The insulating film 654 has a function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 654, it is possible to prevent the diffusion of oxygen from the oxide semiconductor 660 to the outside and the entry of hydrogen, water, etc. from the outside into the oxide semiconductor 660. As the insulating film 654, for example, a nitride insulating film can be used. As the nitride insulating film, there are silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. Note that instead of the nitride insulating film having a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc., an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided. As the oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc., there are aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc.

[0278] The aluminum oxide film is preferable for application to the insulating film 654 because it has a high blocking effect that does not allow the film to permeate both impurities such as hydrogen and moisture and oxygen. Therefore, the aluminum oxide film prevents the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide semiconductor 660 during and after the manufacturing process of the transistor. Preventing the release from an oxide semiconductor of oxygen, which is the main component material constituting the semiconductor 660, insulating film 6 It is suitable for use as a protective film having an effect of preventing unnecessary release of oxygen from 52 In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor .

[0279] 〈Crystal Structure of Oxide Semiconductor〉 Next, the crystal structure of an oxide semiconductor applicable to an OS transistor will be described

[0280] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less Therefore, the case of -5° or more and 5° or less is also included. Also, "verti cal" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Accor dingly, the case of 85° or more and 95° or less is also included

[0281] In this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system .

[0282] Oxide semiconductor films are roughly classified into non-single crystal oxide semiconductor films and single crystal oxide semiconductor films. Non single crystal oxide semiconductor films refer to CAAC-OS (C Axis Aligned Crys talline Oxide Semiconductor) films, polycrystalline oxide semiconductor films , microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, and the like

[0283] First, the CAAC-OS film will be described

[0284] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction

[0285] By using a transmission electron microscope (TEM), a composite analysis image of the bright-field image and diffraction pattern of the CAAC-OS film ( also referred to as a high-resolution TEM image) can be observed, and multiple crystal parts can be confirmed. On the other hand, clear boundaries between crystal parts, i.e., grain boundaries ( also referred to as grain boundaries), cannot be confirmed from high-resolution TEM images. Therefore, it can be said that the CAAC-OS film is less likely to have a decrease in electron mobility due to grain boundaries. When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction approximately parallel to the sample surface,

[0286] it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. On the other hand, when observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction approximately perpendicular to the sample surface,

[0287] it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0288] Fig. 15(a) is a high-resolution TEM image of the cross-section of the CAAC-OS film. Also, Fig. 15(b ) is a high-resolution TEM image of the cross-section obtained by further magnifying Fig. 15(a), and the atomic arrangement is highlighted for easy understanding. Fig. 15(c) shows a region (diameter approximately 4n

[0289] enclosed by a circle) between A-O-A' in Fig. 15(a). ​It is the local Fourier transform image of (m). From FIG. 15(c), the c-axis orientation can be confirmed in each region. Also, between A-O and O-A', since the directions of the c-axis are different, it is suggested that they are different greyscales. Also, between A-O, it can be seen that the angle of the c-axis changes continuously little by little, such as 14.3°, 16.6 °, 26.4°. Similarly, between O-A', it can be seen that the angle of the c-axis changes continuously little by little as -18.3°, -17.6°, -15.9°.

[0290] In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also called nano-beam electron diffraction) using an electron beam of, for example, 1 nm or more and 30 nm or less is performed on the upper surface of the CAAC-OS film, spots are observed . (See FIG. 16(A).)

[0291] From the high-resolution TEM image of the cross-section and the high-resolution TEM image of the plane, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0292] In addition, most of the crystal parts contained in the CAAC-OS film are sized to fit within a cube with a side length of less than 100 nm. Therefore, the crystal parts contained in the CAAC-OS film also include cases where they are sized to fit within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystal parts contained in the CAAC-OS film are connected, a single large crystal region may be formed. For example, in the high-resolution TEM image of the plane, crystal regions of 2500 nm 2 or more 5 μm 2 or more 2 or 1000 μm 2 or more may be observed.

[0293] ​​​ When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the out-of-plane method analysis of the CAAC-OS film having crystals of InGaZnO4, peaks may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the out-of-plane method analysis of the CAAC-OS film having crystals of InGaZnO4, peaks may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0294] On the other hand, in the in-plane method analysis in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, peaks may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. On the other hand, in the in-plane method analysis in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, peaks may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. On the other hand, in the in-plane method analysis in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, peaks may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. For a single crystal oxide semiconductor film of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. For a single crystal oxide semiconductor film of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. For a single crystal oxide semiconductor film of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, even when φ scan is performed with 2θ fixed near 56°, no distinct peaks appear.

[0295] From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the high-resolution TEM observation of the cross-section described above is a plane parallel to the ab plane of the crystal.

[0296] Note that the crystal part is formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. formed when it is formed. As described above, the c-axis of the crystal is also parallel to the normal vector of the surface to be formed of the CAAC-OS film or is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the surface to be formed of the CAAC-OS film or the normal vector of the upper surface.

[0297] In addition, in the CAAC-OS film, the distribution of the c-axis oriented crystal parts does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film the proportion of the c-axis oriented crystal parts in the region near the upper surface may be higher than that in the region near the surface to be formed. Also, in the CAAC-OS film to which impurities are added, the region where the impurities are added is altered, and regions with different proportions of c-axis oriented crystal parts may be formed partially.

[0298] In addition, in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak near 2θ of 31°, a peak may also appear near 2θ of 36° In this case, the peak near 2θ of 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. It is preferable that the CAAC-OS film shows a peak near 2θ of 31° and does not show a peak near 2θ of 36°.

[0299] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurities are elements other than the main components of the oxide semiconductor film such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film are oxidized ​​​By depriving the physical semiconductor film of oxygen, the atomic arrangement of the oxide semiconductor film is disrupted, resulting in a decrease in crystallinity. This becomes a factor. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius). Therefore, when contained inside the oxide semiconductor film, they become a factor in disrupting the atomic arrangement of the oxide semiconductor film and decreasing its crystallinity. Note that impurities contained in the oxide semiconductor film may serve as carrier traps or carrier generation sources.

[0300] Also, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or may become carrier generation sources by capturing hydrogen.

[0301] A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be reduced. Therefore, a transistor using such an oxide semiconductor film has electrical characteristics (also called normally-on) in which the threshold voltage becomes negative less often. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0302] In addition, for a transistor using a CAAC-OS film, the electrical characteristics show little variation due to irradiation with visible light or ultraviolet light.

[0303] Next, the microcrystalline oxide semiconductor film will be described.

[0304] The microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed in a high-resolution TEM image and a region where clear crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc- OS (nanocrystalline Oxide Semiconductor) film. Further, the nc-OS film may not clearly show grain boundaries in a high-resolution TEM image, for example. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film does not show regularity in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film in some cases. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, for the nc-OS film, a probe diameter ( nc- -OS(nanocrystalline Oxide Semiconductor) film. Also, the nc-OS film may not clearly show grain boundaries in a high-resolution TEM image, for example. be confirmed in some cases.

[0305] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film does not show regularity in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film in some cases. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, for the nc-OS film, a probe diameter ( between different crystal parts. Therefore, no orientation is seen in the entire film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film in some cases. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, for the nc-OS film, a probe diameter ( larger than that of the crystal part is used for the nc-OS film for structural analysis using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, for the nc-OS film, a probe diameter ( is used for the nc-OS film for structural analysis using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, for the nc-OS film, a probe diameter ( showing a crystal plane is not detected. Also, for the nc-OS film, a probe diameter ( Perform electron diffraction (also referred to as limited field of view electron diffraction) using an electron beam of, for example, 50 nm or more. A diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film, when performing nano-beam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystalline part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film, there are cases where regions with high luminance are observed in a circular (ring-shaped) manner. Also, when performing nano-beam electron diffraction on the nc -OS film, there are cases where a plurality of spots are observed within the ring-shaped region (see Fig. 16(B)).

[0306] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However, the nc-OS film does not show regularity in the crystal orientation between different crystalline parts. Therefore, the nc-O S film has a higher density of defect levels than the CAAC-OS film.

[0307] Next, the amorphous oxide semiconductor film will be described.

[0308] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystalline part. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0309] In the high-resolution TEM image, no crystalline part can be confirmed for the amorphous oxide semiconductor film.

[0310] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the analysis by the out-of-p lane method. Also, for the amorphous oxide semiconductor film, When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0311] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Ox The resulting film is called an ide semiconductor membrane.

[0312] The amorphous-like OS membrane appears as voids in high-resolution TEM images. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The phos-like OS film is formed by irradiating a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of good quality, However, crystallization due to minute amounts of electron irradiation, such as that observed by TEM, is hardly observed.

[0313] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. For example, the crystal of InGaZnO4 It has a layered structure, with two Ga-Zn-O layers between In-O layers. InGaZnO4 The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is , which is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value), and its value is determined to be 0.29 nm from crystal structure analysis. Therefore, focusing on the lattice fringes in the high-resolution TEM image , in the region where the interval between the lattice fringes is between 0.28 nm and 0.30 nm, each of the lattice fringes was regarded as corresponding to the a-b plane of the InGaZnO4 crystal. The maximum length in the observed region was taken as the size of the crystal part of the amorphous-like OS film and the nc-OS film. Note that the size of the crystal part is selectively evaluated for those with a size of 0.8 nm or more.

[0314] Figure 17 is an example of investigating the change in the average size of the crystal parts (from 20 to 40 locations) of the amorphous-like OS film and the nc -OS film by a high-resolution TEM image. From Figure 17, it can be seen that the crystal part of the amorphous-like OS film grows larger according to the cumulative electron irradiation dose. Specifically, at the initial stage of observation by TEM, the crystal part with a size of about 1. 8 e - / nm 2 grows to a size of about 2.6 nm when the cumulative irradiation dose reaches 4.2×10 . On the other hand, for a high-quality nc-OS film , from the start of electron irradiation until the cumulative electron irradiation dose reaches 4.2×10 8 e - / nm 2 , it can be seen that there is no change in the size of the crystal part regardless of the cumulative electron irradiation dose. Also, by linearly approximating the change in the size of the crystal parts of the amorphous-like OS film and the nc-OS film shown in Figure 17 and extrapolating to a cumulative electron irradiation dose of 0 e

[0315] - / nm 2 up to, the junction It can be seen that the average size of the crystalline portion takes a positive value. Therefore, it can be seen that the crystalline portions of the amorphous-like OS film and the nc-OS film have existed since before observation by TEM.

[0316] Note that the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0317] When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nano-beam electron diffraction.

[0318] FIG. 16(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, a sample chamber 14 below the optical system 12, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, a camera 18 installed in the observation chamber 20, and a film chamber 22 below the observation chamber 20. The camera 18 is installed facing the inside of the observation chamber 20. Note that the film chamber 22 may not be provided.

[0319] Further, FIG. 16(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 16(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 10 are irradiated onto a substance 28 disposed in the sample chamber 14 through the optical system 12. The electrons that have passed through the substance 28 enter a fluorescent plate 32 installed inside the observation chamber 20 through the optical system 16. In the fluorescent plate 32, a transmission electron diffraction pattern can be measured by a pattern corresponding to the intensity of the incident electrons appearing.

[0320] The camera 18 is installed facing the fluorescent plate 32 and can photograph the pattern appearing on the fluorescent plate 32. The angle formed by the straight line passing through the center of the lens of the camera 18 and the center of the fluorescent plate 32 and the upper surface of the fluorescent plate 32 is, for example, 15° or more and 80° or less, 30° or more and 7 5° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance , it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 18 may be installed in the film chamber 22. For example, the camera 18 may be installed in the film chamber 22 so as to face the incident direction of the electrons 24. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back surface of the fluorescent plate 3 2. In the sample chamber 14, a holder for fixing the substance 28 as the sample is installed. The holder has a structure that allows electrons passing through the substance 28 to pass through. The holder may, for example, have a function of moving the substance

[0321] 28 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may, for example, move within a range such as 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less. It is sufficient to have an accuracy within these ranges. These ranges may be set to an optimal range according to the structure of the substance 28.

[0322] Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

[0323] For example, as shown in Fig. 16(D), the irradiation position of the electrons 24, which are nano-beams in the substance By changing (scanning), it is possible to confirm how the structure of the substance changes. At this time, if the substance 28 is a CAAC-OS film, a diffraction pattern as shown in Fig. 16(A) is observed. Or, if the substance 28 is an nc-OS film, a diffraction pattern as shown in Fig. 16(B) is observed.

[0324] Incidentally, even if the substance 28 is a CAAC-OS film, a diffraction pattern similar to that of an nc-OS film or the like may be partially observed. Therefore, the quality of the CAAC-OS film may be represented by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also referred to as the CAAC conversion rate). For example, in the case of a high-quality CAAC-OS film, the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Note that the ratio of the area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate.

[0325] As an example, for the upper surface of each sample having a CAAC-OS film immediately after film formation (denoted as as-sputtered) or after heat treatment at 450 °C in an oxygen-containing atmosphere, a transmission electron diffraction pattern was obtained while scanning. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the CAAC conversion rate was derived by converting the observed diffraction pattern into a still image every 0.5 seconds. A nano-beam electron beam with a probe diameter of 1 nm was used as the electron beam. The same measurement was performed on 6 samples. And the average value of the 6 samples was used for the calculation of the CAAC conversion rate.

[0326] ​​​​​​​The CAAC conversion rates for each sample are shown in Fig. 18(A). The CA AC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (the non-CAAC conversion rate was 24.3%). Also, the CAAC conversion rate of the CAAC-OS film after heat treatment at 450 °C was 85.3% (the non-CAAC conversion rate was 14.7%). It can be seen that the CAAC conversion rate after heat treatment at 450 °C is higher than that immediately after film formation. That is, it can be seen that by heat treatment at a high temperature (for example, 400 °C or higher), the non-CAAC conversion rate becomes low (the CAAC conversion rate becomes high). Also, it can be seen that a CAAC-OS film having a high CAAC conversion rate can be obtained even in heat treatment below 500 °C. (Here, most of the diffraction patterns different from those of the CAAC-OS film were the same as the diffraction pattern of the nc-OS film. Also, in the measurement region, the amorphous oxide semiconductor film could not be confirmed. Therefore, it is suggested that by heat treatment, the region having the same structure as the nc-OS film is rearranged under the influence of the structure of the adjacent region and is CAACified.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.)

[0327] (When such a measurement method is used, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.) (When such a measurement method is used, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.)

[0328] (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.) (Figs. 18(B) and 18(C) are high-resolution TEM images of the plane of the CAAC-OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 18(B) and Fig. 18(C), it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.)

[0329] (When such a measurement method is used, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.) (When such a measurement method is used, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.)

[0330] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments.

[0331] (Embodiment 6) A semiconductor device according to an aspect of the present invention can be used in a display device, a personal computer, or an image playback device equipped with a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying the image thereof). In addition, electronic devices that can use the semiconductor device according to an aspect of the present invention include mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays ), navigation systems, audio playback devices (such as car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 19.

[0332] FIG. 19(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908 , etc. Note that the portable game machine shown in FIG. 19(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this.

[0333] FIG. 19(B) is a portable data terminal, which has a first housing 911, a second housing 912, a first display unit 9 13, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 913​​​​ is provided on the first housing 911, and the second display unit 914 is provided on the second housing 912. The first housing 911 and the second housing 912 are connected by a connecting portion 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The video on the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 at the connecting portion 915. Also, a display device with a function as a position input device may be used for at least one of the first display unit 913 and the second display unit 914. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel portion of the display device.

[0334] FIG. 19(C) is a notebook personal computer, which has a housing 921, a display unit 922, a keyboard 923, a pointing device 924, etc.

[0335] FIG. 19(D) is an electric refrigerator-freezer, which has a housing 931, a refrigerator door 932, a freezer door 933, etc.

[0336] FIG. 19(E) is a video camera, which has a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connecting portion 946, etc. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. ​​​​​Furthermore, the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connecting portion 946.

[0337] FIG. 19(F) shows an ordinary motor vehicle, which has a vehicle body 951, wheels 952, a dashboard 953, a radio 954, etc.

[0338] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0339] (Embodiment 7) In this embodiment, a usage example of an RF tag according to an aspect of the present invention will be described with reference to FIG. 20. Although the applications of RF tags are extensive, for example, banknotes, coins, securities, bearer bonds, certificates (such as driver's licenses and residence certificates, see FIG. 20(A)), recording media (DVDs, video tapes, etc., see FIG. 20(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 20(C)), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used. The applications of RF tags are extensive. For example, they can be used for banknotes, coins, securities, bearer bonds, certificates (such as driver's licenses and residence certificates, see FIG. 20(A)), recording media (DVDs, video tapes, etc., see FIG. 20(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 20(C)), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article. bonds, certificates (such as driver's licenses and residence certificates, see FIG. 20(A)), recording media (DVDs, video tapes, etc., see FIG. 20(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 20(C)), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used. bonds, certificates (such as driver's licenses and residence certificates, see FIG. 20(A)), recording media (DVDs, video tapes, etc., see FIG. 20(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 20(C)), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used. ), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used. ), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used. ), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used. ), vehicles (bicycles, etc., see FIG. 20(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other articles, or tags (see FIGS. 20(E) and 20(F)) attached to each article can be provided and used.

[0340] An RF tag 4000 according to an aspect of the present invention is fixed to an article by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each article. An RF tag according to an aspect of the present invention is fixed to an article by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each article. An RF tag according to an aspect of the present invention is fixed to an article by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each article. An RF tag according to an aspect of the present invention​​​​ The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to various items, such as items of clothing, recording media, personal belongings, food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0341] As described above, the RF tag according to one aspect of the present invention is used for each of the applications described in this embodiment. This reduces the power required for operations, including writing and reading information, thereby extending the maximum communication distance. It is also possible to store information for an extremely long period of time even if the power is cut off. Since the data can be retained for a long time, it can be used for applications where the frequency of writing and reading is low. Cut.

[0342] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0343] BG1 signal BG2 signal BL bit line BL1 bit line BL2 bit line FN1 node FN2 Node FN3 Node p0 Period p1 period p2 period p3 period p4 period p5 period p6 period T0 time T1 time T2 time T3 time T4 time T5 time T6 time T7 time T8 time T9 time T10 time T11 time T12 time T13 time T14 time T15 time WLC1 word line WLC2 word line WLC3 word line WLOS1 word line WLOS2 word line WLOS3 word line 10 electron gun chamber 12 optical system 14 sample chamber 16 optical system 18 camera 20 observation chamber 22 film chamber 24 electron 28 substance 32 fluorescent plate 100 memory cell 101 transistor 102 transistor 103 transistor 104 capacitor element 105 transistor 106 capacitor element 107 transistor 108 capacitor element 109 transistor 110 memory cell 112 transistor 113 Transistor 114 Transistor 122 Transistor 123 Transistor 500 Semiconductor device 501 Memory cell array 502 Row selection driver 503 Column selection driver 504 A / D converter 517 Decoder 518 Control circuit 521 Decoder 522 Latch circuit 523 D / A converter 524 Switch circuit 526 Transistor 531 Comparator 532 Encoder 533 Latch circuit 534 Buffer 651 Insulating film 652 Insulating film 653 Gate insulating film 654 Insulating film 655 Insulating film 660 Oxide semiconductor 661 Oxide semiconductor 662 Oxide semiconductor 663 Oxide semiconductor 671 Source electrode 672 Drain electrode 673 Gate electrode 901 Housing 902 Housing 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display unit 914 Display unit 915 Connection part 916 Operation keys 921 Housing 922 Display unit 923 Keyboard 924 Pointing device 931 Housing 932 Refrigerator door 933 Freezer door 941 Housing 942 Housing 943 Display unit 944 Operation keys 945 Lens 946 Connection part 951 Vehicle body 952 Wheels 953 Dashboard 954 Light 2000 Substrate 2001 Insulating film 2002 Insulating film 2003 Insulating film 2004 Insulating film 2005 Insulating film 2006 Insulating film 2007 Insulating film 2008 Insulating film 2101 Plug 2102 Plug 2103 Plug 2104 Plug 2105 Plug 2106 Plug 2107 Plug 2108 Plug 2201 Channel formation region 2202 Impurity region 2203 Impurity region 2204 Gate insulating film 2205 Gate electrode 2206 Sidewall insulating layer 2301 Wiring 2302 Wiring 2401 Electrode 2402 Electrode 2403 Insulating film 2501 Wiring 2502 Wiring 2601 Electrode 2602 Electrode 2603 Insulating Film 2701 Conductive Film 2702 Conductive Film 4000 RF Tag

Claims

1. A semiconductor device comprising first to third transistors, a capacitance element, and a power supply line, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the capacitance element; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the third transistor is electrically connected to the power supply line, a semiconductor film including a channel formation region of the second transistor and a channel formation region of the third transistor; a first conductive film having a region located above the semiconductor film and functioning as one electrode of the capacitor; a first insulating film having a region located above the first conductive film and containing nitrogen and silicon; a second conductive film having a region overlapping with the first conductive film with the first insulating film interposed therebetween and functioning as the other electrode of the capacitor; a second insulating film having a region located above the second conductive film and containing oxygen and silicon; an oxide semiconductor film having a region located above the second insulating film and including a channel formation region of the third transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having the same material as the fourth conductive film; a third insulating film having a region located above the third conductive film, a region located above the fourth conductive film, and a region located above the fifth conductive film; a sixth conductive film having a region located above the third insulating film and functioning as the power supply line; the sixth conductive film is electrically connected to the semiconductor film via the fifth conductive film, the semiconductor film comprises silicon; the oxide semiconductor film contains In, Ga, and Zn, the first transistor and the second transistor are arranged such that a channel length direction of the first transistor and a channel length direction of the second transistor are aligned along a first direction; Semiconductor device.

2. A semiconductor device comprising first to third transistors, a capacitance element, and a power supply line, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the capacitance element; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the third transistor is electrically connected to the power supply line, a semiconductor film including a channel formation region of the second transistor and a channel formation region of the third transistor; a first conductive film having a region located above the semiconductor film and functioning as one electrode of the capacitor; a first insulating film having a region located above the first conductive film and containing nitrogen and silicon; a second conductive film having a region overlapping with the first conductive film with the first insulating film interposed therebetween and functioning as the other electrode of the capacitor; a second insulating film having a region located above the second conductive film and containing oxygen and silicon; an oxide semiconductor film having a region located above the second insulating film and including a channel formation region of the third transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having the same material as the fourth conductive film; a third insulating film having a region in contact with an upper surface of the fourth conductive film and a region in contact with an upper surface of the fifth conductive film; a sixth conductive film having a region located above the third insulating film and functioning as the power supply line; the sixth conductive film is electrically connected to the semiconductor film via the fifth conductive film, the semiconductor film comprises silicon; the oxide semiconductor film contains In, Ga, and Zn, the first transistor and the second transistor are arranged such that a channel length direction of the first transistor and a channel length direction of the second transistor are aligned along a first direction; Semiconductor device.

3. A semiconductor device comprising first to third transistors, a capacitance element, and a power supply line, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the capacitance element; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the third transistor is electrically connected to the power supply line, a semiconductor film including a channel formation region of the second transistor and a channel formation region of the third transistor; a first conductive film having a region located above the semiconductor film and functioning as one electrode of the capacitor; a first insulating film having a region located above the first conductive film and containing nitrogen and silicon; a second conductive film having a region overlapping with the first conductive film with the first insulating film interposed therebetween and functioning as the other electrode of the capacitor; a second insulating film having a region located above the second conductive film and containing oxygen and silicon; an oxide semiconductor film having a region located above the second insulating film and including a channel formation region of the third transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as a gate electrode of the first transistor; a fourth conductive film having a region located above the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having the same material as the fourth conductive film; a third insulating film having a region in contact with an upper surface of the fourth conductive film and a region in contact with an upper surface of the fifth conductive film; a sixth conductive film having a region located above the third insulating film and functioning as the power supply line; the sixth conductive film is electrically connected to the semiconductor film via the fifth conductive film, the semiconductor film comprises silicon; the oxide semiconductor film contains In, Ga, and Zn, the first transistor and the second transistor are arranged such that a channel length direction of the first transistor and a channel length direction of the second transistor are aligned along a first direction; the first conductive film does not have a region overlapping with a channel formation region of the third transistor when viewed cross-sectionally in the first direction; Semiconductor device.

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