Semiconductor device

Abstract

To reduce a time span between sequence processes to be executed.SOLUTION: A semiconductor device 100 includes: an HLC 1 which stores in advance the operation sequences of multiple peripherals, and which control a sequence process without utilizing software; an APB 3 that sets, to the HLC 1, a signal which affects the sequence process; an AND circuit 5 that outputs a logical product of a completion interruption which is output by the HLC 1 from an output terminal when the sequence process completes by a repetition permission which is a signal output by the APB 3 and which sets whether or not to repeatedly execute the sequence process in accordance with the operation sequences; and an OR circuit 4 that outputs, to the HLC 1, a logical sum of the output by the AND circuit 5 with an activation command which is a signal output by the APB 3 and which instructs the HLC 1 in an inactive state not executing the sequence process to start the sequence process. The APB 3 outputs, to the HLC 1, the activation command with the setting for the repetition permission being maintained as effective.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a microcomputer that includes a CPU (Central Processing Unit) and a PWM timer that enables generation of a PWM (Pulse Width Modulation) pulse, and that enables time-series changes in the duty value of the PWM pulse without the intervention of the CPU. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-282828 A Summary of the Invention [Problem to be solved by the invention]

[0004] When control is performed by a CPU using software, the processing speed is slower than when the desired function is realized by hardware, and the load on the CPU is increased.

[0005] Therefore, there exists an HLC (Hardware Linkage Controller) sequencer that realizes peripheral linkage operations, such as starting up a subsequent peripheral without relying on software processing by the CPU, by connecting the completion notification output by a previous peripheral device, i.e., a peripheral, upon completion of its operation, to the start-up terminal of the subsequent peripheral.

[0006] The HLC sequencer is a sequencer that realizes coordinated operations such as the completion and startup of multiple peripheral operations by hardware, and executes a target function by sequentially starting multiple peripherals according to a predetermined operation sequence.

[0007] In a conventional HLC sequencer, when activated by a CPU, sequence processing is started to sequentially activate peripherals according to a predetermined operation sequence. When the operation of the peripheral registered at the end of the operation sequence is completed, an interrupt is output to the CPU to end the sequence processing. In order to execute the peripheral sequence processing again according to the predetermined operation sequence, it is necessary for the CPU to restart the HLC sequencer by using the interrupt from the HLC sequencer as a trigger. Therefore, after the first sequence processing is completed, the HLC sequencer cannot start the second sequence processing until the time required for the CPU to restart the HLC sequencer has elapsed, and a delay occurs between the sequence processings.

Means for Solving the Problem

[0008] The semiconductor device according to the present disclosure stores in advance the operation sequences of a plurality of peripherals, and includes a control unit that controls each of the peripherals without using software, a setting unit that sets a signal that affects the control of the peripherals to the control unit, a completion interrupt that the control unit outputs from an output terminal when the operation of each of the peripherals is completed according to the operation sequence, and a logical product circuit that outputs a logical product of repetition permissions for setting whether to repeatedly execute the operation of each of the peripherals according to the operation sequence, and a logical sum circuit that outputs to the control unit a logical sum of the output of the logical product circuit and a signal output by the setting unit, which is a start command for instructing the control unit in a stopped state where the control of the peripherals is not being performed to start the control of the peripherals. The setting unit outputs the start command to the control unit while keeping the setting of the repetition permission valid.

[0009] Thereby, it is possible to provide a semiconductor device capable of shortening the interval between sequence processings to be executed as compared with the case where a start command from the CPU is required every time the sequence processing is repeated.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

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Figure 9

Embodiments for Carrying Out the Invention

[0011] Hereinafter, this embodiment will be described with reference to the drawings. Note that the same components and the same processes are given the same reference numerals throughout all the drawings, and duplicate explanations are omitted. The dimensional ratios in the drawings are exaggerated for the convenience of explanation and may be different from the actual ratios.

[0012] FIG. 1 is a diagram showing a configuration example of a semiconductor device 100 according to this embodiment. As shown in FIG. 1, the semiconductor device 100 includes an HLC (Hardware Linkage Controller) 1, an APB (Advanced Peripheral Bus) 3, an OR circuit 4, and an AND circuit 5.

[0013] HLC1 is a control device that realizes the coordinated operation of a plurality of peripherals (not shown) using hardware without relying on software processing by a CPU (Central Processing Unit), and is an example of a control unit. A peripheral refers to a peripheral device connected to HLC1, and executes a predetermined process such as data transfer. There is no restriction on the content of the process executed by the peripheral according to the present embodiment, and any process may be performed.

[0014] HLC1 stores in advance the operation order of the connected plurality of peripherals, and controls to sequentially operate each peripheral by starting the peripherals according to the registered operation order. Specifically, for example, when the operation order is defined in the order of peripheral A, peripheral B, and peripheral C, HLC1 first starts peripheral A. When each peripheral finishes a predetermined process, it outputs a completion notification to HLC1. When HLC1 receives the completion notification from peripheral A, it refers to the operation order and starts the next peripheral, that is, peripheral B. When HLC1 receives the completion notification from peripheral B, it refers to the operation order and starts peripheral C this time. When HLC1 receives the completion notification from peripheral C, since there is no peripheral defined to be started next to peripheral C in the operation order, the start of the peripherals according to the operation order is terminated, and a completion interrupt is output from the output terminal (not shown) to the CPU through bus 10. The completion interrupt is represented by a pulse that changes from, for example, "0" to "1".

[0015] Hereinafter, the processing executed by each peripheral is referred to as "peripheral processing". Also, a table storing the operation order of the peripherals is called "sequence table 20". As shown in FIG. 1, the sequence table 20 is composed of, for example, an order column representing the operation order and a device name column indicating the peripheral to be executed in the specified operation order. The "#N" (index N is a positive integer) in the order column of the sequence table 20 represents the operation order of the peripheral. For example, the peripheral specified in the device name column associated with "#1" in the order column is the first peripheral to be executed, and the peripheral specified in the device name column associated with "#2" is the next peripheral to be executed. That is, the index N is a number representing the operation order of the peripheral.

[0016] "Peri-*" in the device name column represents the name of the peripheral, and the English letter "*" is an identifier for identifying the peripheral. For example, "Peri-A" represents peripheral A, and "Peri-B" represents peripheral B.

[0017] For convenience of explanation, each row in the sequence table 20 may be referred to as a "stage". Using the notation of "stage", the sequence table 20 in FIG. 1 is composed of 6 stages with operation orders from "#1" to "#6".

[0018] Also, in the sequence table 20, the peripheral defined in the operation order immediately before the peripheral of interest is referred to as the "preceding peripheral", and the peripheral defined in the operation order immediately after is referred to as the "succeeding peripheral". Further, in the sequence table 20, the peripheral that is executed first in the operation order is referred to as the "first-stage peripheral", and the peripheral that is executed last is referred to as the "final-stage peripheral". Specifically, in the sequence table 20 in FIG. 1, when focusing on the peripheral C associated with "#3" in the order column, the preceding peripheral is the peripheral B associated with "#2" in the order column, and the succeeding peripheral is the peripheral A associated with "#4" in the order column. Also, the first-stage peripheral is the peripheral A associated with "#1" in the order column, and the final-stage peripheral is the peripheral B associated with "#6" in the order column.

[0019] Note that a series of control units in which the HLC1 executes from the operation of the first-stage peripheral to the operation of the final-stage peripheral according to the operation order defined in the sequence table 20 is referred to as "sequence processing".

[0020] As described above, the HLC1 includes a sequencer 2 that realizes associated operations such as the completion and activation of the operations of a plurality of peripherals by hardware. The sequence table 20 is included in the sequencer 2.

[0021] APB3 is an example of a setting unit that sets signals that affect the control of peripherals with respect to the HLC1. APB3 sets, for example, each signal of a start command, repetition permission, forced stop command, and stop state selection output from the CPU with respect to the HLC1.

[0022] The start command is an instruction to start sequence processing for the HLC1 in a stopped state where it is not controlling the peripherals, specifically, the HLC1 that is not performing sequence processing. For example, the instruction is given by a pulse that changes from "0" to "1". The start command is input to one of the input terminals of the OR circuit 4 through the bus 7.

[0023] The repeat enable is an instruction to instruct the HLC1 to repeatedly execute sequence processing according to the operation sequence defined in the sequence table 20 without outputting the start command every time the CPU executes sequence processing, provided that the start command is issued once initially. APB3 keeps the setting of repeat enable valid while causing the HLC1 to repeatedly execute sequence processing. Specifically, APB3 holds the value of repeat enable at "1" while causing the HLC1 to repeatedly execute sequence processing. Hereinafter, the state where the value of repeat enable is "1" is referred to as "enabled". The state where the value of repeat enable is "0" is referred to as "disabled". The repeat enable is input to one of the input terminals of the AND circuit 5 through the bus 6.

[0024] The forced stop command is an instruction to stop the sequence processing being executed in the HLC1, and for example, the instruction is given by a pulse that changes from "0" to "1". The forced stop command is input to the HLC1 through the bus 8.

[0025] The stop state selection is a signal for selecting the method of stopping the sequence processing in the HLC1 when APB3 inputs a forced stop command to the HLC1, and the selection content is specified by the level of "0" or "1". The stop state selection is input to the HLC1 through the bus 9.

[0026] As an example, if the value of the stop state selection when receiving the forced stop command is "0", the HLC1 stops the sequence processing at the time of receiving the forced stop command even before the operation of the peripheral at the final stage in the sequence processing is completed. That is, the HLC1 stops the sequence processing halfway without outputting a completion interrupt to the CPU.

[0027] On the other hand, if the value of the stop state selection when receiving a forced stop command is "1", even if HLC1 receives a forced stop command, it continues the sequence process until it completes the operation of the final-stage peripheral in the sequence process and outputs a completion interrupt to the CPU. HLC1 stops the ongoing sequence process with the completion of the operation of the final-stage peripheral and outputs a completion interrupt to the CPU.

[0028] The value "0" in the stop state selection is an example of the first value, and the value "1" in the stop state selection is an example of the second value. Hereinafter, the state where the value of the stop state selection is "0" is represented as the "forced stop mode", and the state where the value of the stop state selection is "1" is represented as the "continue stop mode".

[0029] The completion interrupt output by HLC1 is input to the other input terminal of AND circuit 5 through bus 11 connected to bus 10. AND circuit 5, which is an example of a logical product circuit, inputs the logical product of the repetition permission and the completion interrupt to the other input terminal of OR circuit 4.

[0030] OR circuit 4, which is an example of a logical sum circuit, outputs the logical sum of the start command and the logical product of the repetition permission and the completion interrupt to HLC1 through bus 12. The output of OR circuit 4 is input to HLC1 as a start command.

[0031] Next, the control process of semiconductor device 100 shown in FIG. 1 will be described in detail. FIG. 2 is a flowchart showing an example of the flow of the control process when APB3 outputs a start command with the repetition permission enabled.

[0032] In step S10, HLC1 executes a sequence process that controls the operations of each peripheral from the first-stage peripheral to the final-stage peripheral according to the operation order defined in sequence table 20.

[0033] In step S20, HLC1 determines whether the control has been completed up to the final-stage peripheral. If the control has not been completed up to the final-stage peripheral, the process proceeds to step S10, and HLC1 continues the sequence processing according to the operation sequence defined in the sequence table 20. On the other hand, if the control has been completed up to the final-stage peripheral, the process proceeds to step S30.

[0034] Since the sequence processing is completed, in step S30, HLC1 outputs a completion interrupt to the CPU through the bus 10.

[0035] In step S40, the semiconductor device 100 determines whether the continuation condition of the sequence processing is satisfied. Specifically, if the repeat permission is enabled, the completion interrupt output in the process of step S30 is input to the input terminal of the AND circuit 5, so that the output of the AND circuit 5 changes from "0" to "1" according to the pulse width of the completion interrupt. Therefore, the output of the OR circuit 4 becomes "1" according to the output of the AND circuit 5, and a start command is input to HLC1, and the continuation condition of the sequence processing is satisfied.

[0036] Therefore, the process proceeds to step S10, and HLC1 performs control to re-execute the sequence processing from the initial-stage peripheral according to the operation sequence defined in the sequence table 20. That is, HLC1 continues the sequence processing until the repeat permission is disabled.

[0037] On the other hand, if it is determined in the determination process of step S30 that the continuation condition of the sequence processing is not satisfied, that is, if the repeat permission is disabled, the control process shown in FIG. 2 is terminated.

[0038] Thus, according to the semiconductor device 100 according to this embodiment, even if a start command is not received from the CPU every time sequence processing is executed, the sequence processing can be repeatedly executed using a completion interrupt. Therefore, when the sequence processing ends and the next sequence processing starts, the semiconductor device 100 does not need to wait for a start command from the CPU. That is, the semiconductor device 100 can shorten the time required to continuously execute a predetermined number of sequence processings compared to the case of receiving a start command from the CPU every time sequence processing is executed.

[0039] Also, according to the semiconductor device 100 according to this embodiment, if the repeat permission is disabled, the number of executions of the sequence processing can be set to one. That is, the semiconductor device 100 can switch between a single operation and a continuous operation of the sequence processing by controlling the repeat permission.

[0040] Next, the operation of the semiconductor device 100 when a forced stop command is received will be described. FIG. 3 is a flowchart showing an example of the flow of control processing when a forced stop command is received during the execution of sequence processing in the semiconductor device 100 shown in FIG. 1.

[0041] The control processing shown in FIG. 3 differs from the control processing shown in FIG. 2 in that steps S12 and steps S50 to S70 are added, and the other processing is the same. Therefore, hereinafter, the processing of steps S12 and steps S50 to S70 will be mainly described.

[0042] After starting the sequence processing by a start command, HLC1 proceeds to step S12.

[0043] In step S12, HLC1 determines whether a forced stop command has been received through bus 8. If a forced stop command has not been received, the process proceeds to step S20, and the subsequent processing described with reference to FIG. 2 is executed.

[0044] On the other hand, if it is determined in the determination process of step S12 that a forced stop command has been received, the process proceeds to step S50.

[0045] In step S50, HLC1 determines whether the stop state selection is in the forced stop mode. If the stop state selection is in the forced stop mode, the control process shown in FIG. 3 is terminated. That is, the semiconductor device 100 stops the sequence process at the time when the forced stop command is received even before the operation of the final peripheral in the sequence process is completed.

[0046] If it is determined in the determination process of step S50 that the stop state selection is not in the forced stop mode, that is, if it is determined that the stop state selection is in the continuous stop mode, the process proceeds to step S60.

[0047] In step S60, HLC1 continues to control the sequence process until the operation of the final peripheral in the operation procedure defined in the sequence table 20 is completed.

[0048] With the completion of the operation of the final peripheral, in step S70, HLC1 outputs a completion interrupt to the CPU through the bus 10 and terminates the control process shown in FIG. 3.

[0049] Thus, according to the semiconductor device 100 according to the present embodiment, the stop method of the sequence process when a forced stop command is received can be controlled by the stop state selection. Therefore, the semiconductor device 100 can provide a plurality of options for the stop operation in the sequence process to the device using the semiconductor device 100. The device using the semiconductor device 100 may set a stop state selection according to the specifications.

[0050] <Modification Example 1 of Semiconductor Device 100> Next, the CPU measures the number of completion interrupts from the semiconductor device 100. When the number of repetitions of the sequence process reaches the preset stop specified number, even if a forced stop command is not output to the semiconductor device 100, the semiconductor device 100 that autonomously stops after repeatedly executing the sequence process up to the stop specified number will be described. That the number of repetitions of the sequence process "reaches" the stop specified number means that the number of repetitions of the sequence process becomes the same value as the stop specified number.

[0051] Note that the semiconductor device 100 can stop the sequence process by a forced stop command, but can also stop the sequence process by disabling the repeat permission. In Modification Example 1, an example in which the semiconductor device 100 receives a forced stop command when stopping the sequence process will be described. However, the semiconductor device 100 may stop the sequence process by receiving the repeat permission set to disabled.

[0052] FIG. 4 is a diagram showing a configuration example of the semiconductor device 100 in Modification Example 1. In the configuration example of the semiconductor device 100 shown in FIG. 4, a counter 15 is added to the configuration example shown in FIG. 1.

[0053] The counter 15 is connected in series to the bus 11 and measures the number of output times of the completion interrupt from when the HLC1 receives the start command and starts the sequence process until it receives the forced stop command and stops the sequence process, that is, the number of repetitions of the sequence process.

[0054] The counter 15 is connected to the APB3 through the bus 13, and the stop specified number is set for the counter 15 from the APB3. The stop specified number is a value that specifies the number of repetitions of the sequence process in the semiconductor device 100. When the number of repetitions of the sequence process reaches the stop specified number, the counter 15 outputs a process completion command to the HLC1 through the bus 14 and resets the number of repetitions of the sequence process to "0".

[0055] Upon receiving the processing completion command, the HLC1 completes the operation of the final-stage peripheral in the ongoing sequence processing, outputs a completion interrupt to the CPU, and then halts the sequence processing. That is, the HLC1 performs the same operation as the stop control of the sequence processing when a forced stop command is received in a state where the stop state selection is set to the continuous stop mode.

[0056] If it is not necessary to stop the sequence processing a specified number of times, the specified number of stops may be set to a predetermined value (e.g., "0" or a negative value) in advance to invalidate the specified number of stops.

[0057] Next, the control processing of the semiconductor device 100 shown in FIG. 4 will be described in detail. First, the operation of the counter 15 will be described.

[0058] FIG. 5 is a flowchart showing an example of the flow of the measurement process of the number of completion interrupts in the counter 15 when the sequence processing is started in the semiconductor device 100. The measurement process of the number of completion interrupts is started, for example, when a specified number of stops to stop the sequence processing by APB3 is set in the counter 15. Note that the count value of the counter 15 is initialized to "0" before the setting of the specified number of stops, and it is assumed that the repetition permission is enabled. The counter 15 may initialize the count value to "0" by setting the specified number of stops.

[0059] First, in step S100, the counter 15 determines whether it has received a completion interrupt from the HLC1 through the bus 11. If it has not received a completion interrupt, it proceeds to step S100 to continue monitoring for a completion interrupt. If it has received a completion interrupt, it proceeds to step S110.

[0060] In step S110, the counter 15 increments the count value by "1" to perform a count-up of the count value.

[0061] In step S120, counter 15 determines whether the count value has reached the specified stop count. If the count value has not reached the specified stop count, the process proceeds to step S100 to continue monitoring the completion interrupt. On the other hand, if the count value has reached the specified stop count, the process proceeds to step S130.

[0062] Since the count value has reached the specified stop count, in step S130, counter 15 outputs a process completion command to HLC1 through bus 14.

[0063] In step S140, counter 15 initializes the count value to "0" and ends the measurement process of the number of completion interrupts shown in FIG. 5.

[0064] When the number of repeated executions of the sequence process in HLC1 reaches the specified stop count by the measurement process of the number of completion interrupts shown in FIG. 5, counter 15 outputs a process completion command to HLC1 and notifies that the number of repeated executions of the sequence process has reached the specified stop count.

[0065] FIG. 6 is a flowchart showing an example of the flow of control processing when a start command is output with APB3 enabled for repeated permission.

[0066] The difference between the control processing shown in FIG. 6 and the control processing shown in FIG. 3 is that step S14 is added, and the other processes are the same. Therefore, hereinafter, the processing of step S14 will be mainly described.

[0067] If a forced stop command has not been received during the execution of the sequence process, step S14 is executed.

[0068] In step S14, HLC1 determines whether it has received a process completion command through bus 14. If it has not received the process completion command, the process proceeds to step S20 and executes the subsequent processing described with reference to FIG. 2.

[0069] On the other hand, if it is determined in the determination process of step S14 that a process completion command has been received, the process proceeds to step S60. Therefore, when HLC1 receives a process completion command, it performs the same operation as the stop control of the sequence process when a forced stop command is received in a state where the stop state selection is set to the continuous stop mode.

[0070] As described above, according to Modification 1 of the semiconductor device 100 according to the present embodiment, the semiconductor device 100 can control the number of repetitions of the sequence process only by hardware using the counter 15 and the completion interrupt without receiving a forced stop command from, for example, the CPU.

[0071] Note that when the semiconductor device 100 receives a process completion command, the sequence process may be stopped at the time when the process completion command is received even before the operation of the final-stage peripheral in the sequence process is completed. In this case, HLC1 performs the same operation as the stop control of the sequence process when a forced stop command is received in a state where the stop state selection is set to the forced stop mode.

[0072] <Modification 2 of Semiconductor Device 100> So far, the semiconductor device 100 that performs the sequence process has been described. However, since the semiconductor device 100 shown above performs the sequence process according to the operation order defined in the sequence table 20, the same sequence process will be repeated. However, in some cases, it may be desired to change the content of the sequence process during the repeated execution of the sequence process. Hereinafter, a semiconductor device 100 that can update the content of the sequence process during the execution of the sequence process will be described.

[0073] FIG. 7 is a diagram showing a configuration example of the semiconductor device 100 in Modification 2. In the configuration example of the semiconductor device 100 shown in FIG. 7, a reload control unit 18 and a buffer 19 are added to the configuration example shown in FIG. 4.

[0074] Buffer 19 is a storage unit provided in sequencer 2, and temporarily stores the operation sequence in the updated sequence process, that is, the combination of the name and order of the peripherals. Therefore, buffer 19 has the same number of storage areas as sequence table 20.

[0075] Reload control unit 18 is provided in sequencer 2, and updates the operation sequence of the peripherals set in sequence table 20 to the operation sequence of the peripherals stored in buffer 19.

[0076] In addition, a bus 16 connected to APB3 and a bus 17 connected to HLC1 are added to counter 15 of semiconductor device 100 shown in FIG. 7.

[0077] Counter 15 receives the specified number of updates from APB3 through bus 16. The specified number of updates is a value that specifies the timing of updating the operation sequence of sequence table 20 according to the number of repetitions of the sequence process. For example, when the sequence process according to the existing operation sequence preset in sequence table 20 is repeated 3 times, and from the 4th sequence process onwards, it is desired to execute the sequence process according to the new operation sequence, the specified number of updates is set to "3".

[0078] When the number of repetitions of the sequence process reaches the specified number of updates, counter 15 outputs a reload command to HLC1 through bus 17. The reload command is a command that requests HLC1 to update the operation sequence of the peripherals defined in sequence table 20 to the operation sequence of the peripherals stored in buffer 19.

[0079] Reload control unit 18 of HLC1 that has received the reload command updates the operation sequence of the peripherals defined in sequence table 20 to the operation sequence of the peripherals stored in buffer 19.

[0080] In FIG. 7, a bus 16 is provided to set the number of update designations. However, it may be shared with a bus 13 for setting the number of stop designations. Also, in FIG. 7, a bus 17 is provided to output a reload instruction. However, it may be shared with a bus 14 for outputting a process completion instruction.

[0081] Next, the control process of the semiconductor device 100 shown in FIG. 7 will be described in detail. First, the operation of the counter 15 will be described.

[0082] FIG. 8 is a flowchart showing an example of the flow of the measurement process of the number of completion interrupts in the counter 15 when the sequence process is started in the semiconductor device 100. The measurement process of the number of completion interrupts starts, for example, when the number of update designations is set in the counter 15 by APB3. Note that the count value of the counter 15 is initialized to "0" before the number of update designations is set, and the repetition permission is assumed to be enabled.

[0083] First, in step S200, the counter 15 determines whether it has received a completion interrupt from the HLC1 through the bus 11. If it has not received a completion interrupt, it returns to step S200 to continue monitoring for the completion interrupt. If it has received a completion interrupt, it proceeds to step S210.

[0084] In step S210, the counter 15 increments the count value by "1" to perform a count-up of the count value.

[0085] In step S220, the counter 15 determines whether the count value has reached the number of update designations. If the count value has not reached the number of update designations, it returns to step S200 to continue monitoring for the completion interrupt. On the other hand, if the count value has reached the number of update designations, it proceeds to step S230.

[0086] Since the count value has reached the number of update designations, in step S230, the counter 15 outputs a reload instruction to the HLC1 through the bus 17.

[0087] When the number of times of repeated execution of the sequence process in HLC1 reaches the update specified number by the measurement process of the completion interrupt number shown in FIG. 8, the counter 15 outputs a reload command to HLC1 and notifies that the number of times of repeated execution of the sequence process has reached the update specified number.

[0088] FIG. 9 is a flowchart showing an example of the flow of control processing when a start command is output with APB3 enabled for repeated permission.

[0089] Note that it is assumed that the operation order in the updated sequence process is preset in the buffer 19. The setting of the operation order in the updated sequence process to the buffer 19 can be performed in any state during the execution of the sequence process and during the stop of the sequence process.

[0090] The difference between the control process shown in FIG. 9 and the control process shown in FIG. 6 is that steps S32 and S34 are added, and the other processes are the same. Therefore, hereinafter, the processes of steps S32 and S34 will be mainly described.

[0091] When HLC1 has not received either a forced stop command or a process completion command and the control has been completed up to the last peripheral in the sequence table 20, HLC1 outputs a completion interrupt and executes step S32.

[0092] In step S32, HLC1 determines whether it has received a reload command through the bus 17. If it has received a reload command, it proceeds to step S34.

[0093] In step S34, the reload control unit 18 updates the operation order of the peripherals defined in the sequence table 20 to the operation order of the peripherals stored in the buffer 19. Thereby, the operation order in the sequence table 20 is rewritten.

[0094] If repeat permission is enabled, the determination process in step S40 causes a transition to step S10, so HLC1 continues the sequence process according to the updated operation order.

[0095] In this case, for example, if a stop specified number greater than the update specified number is set, HLC1 executes the sequence process according to the operation order before the update until it receives a reload instruction, and after receiving the reload instruction and until the number of repetitions of the sequence process reaches the stop specified number, it executes the sequence process according to the updated operation order.

[0096] Thus, according to modification example 2 of the semiconductor device 100 according to the present embodiment, even while the semiconductor device 100 is repeatedly executing the sequence process, at the timing when the operation of the final-stage peripheral in the sequence process ends, the operation order in the sequence table 20 can be updated. That is, the semiconductor device 100 can update the operation order in the sequence table 20 in accordance with the output of the completion interrupt signal.

[0097] Therefore, the semiconductor device 100 can handle complex processes such as updating the content of the sequence table 20 during the sequence process without using a CPU.

[0098] Note that the semiconductor device 100 described above is not limited to the sequencer using HLC1, and is applicable to all sequencers realized by hardware.

[0099] As described above, one form of the semiconductor device 100 has been described using the embodiment, but the disclosed form of the semiconductor device 100 is an example and is not limited to the scope described in the embodiment. Various changes or improvements can be made to the embodiment without departing from the gist of the present disclosure, and the forms with such changes or improvements are also included in the technical scope of the disclosure.

[0100] For example, the internal processing order in each flowchart of the control process shown in FIGS. 2, 3, 6, and 9, and the measurement process of the number of completion interrupts shown in FIGS. 5 and 8 may be changed without departing from the gist of the present disclosure.

[0101] The following is an appendix according to this embodiment.

[0102] (Appendix 1) A control unit that stores in advance the operation order of a plurality of peripherals and controls each of the peripherals without using software; A setting unit that sets a signal that affects the control of the peripheral to the control unit; A completion interrupt output from the output terminal by the control unit when the operation of each of the peripherals is completed according to the operation order, and a signal output by the setting unit, and an AND circuit that outputs a logical product of repetition permission for setting whether to repeatedly execute the operation of each of the peripherals according to the operation order; An OR circuit that outputs to the control unit a logical sum of the output of the AND circuit and a signal output by the setting unit, the signal being a start command that instructs the control unit in a stopped state where the peripheral is not being controlled to start controlling the peripheral; comprising The setting unit outputs the start command to the control unit while keeping the setting of the repetition permission valid. A semiconductor device.

[0103] (Appendix 2) The setting unit sets a forced stop command for stopping the control of the peripheral and a stop state selection for selecting a stop method of the control of the peripheral to the control unit. When the value of the stop state selection when the control unit receives the forced stop command is the first value, even before the operation of the last peripheral defined in the operation sequence is completed, the control of the peripheral is stopped at the time when the forced stop command is received. When the value of the stop state selection when the forced stop command is received is the second value, even if the forced stop command is received, the control of the peripheral is continued until the operation of the last peripheral defined in the operation sequence is completed and the completion interrupt is output, and the control of the peripheral is stopped together with the output of the completion interrupt. The semiconductor device according to Supplementary Note 1.

[0104] (Supplementary Note 3) A counter is provided, which is connected between the input terminal and the output terminal of the logical product circuit, and measures the number of times the completion interrupt is output from when the control unit receives the start command and starts controlling the peripheral until the control unit receives the forced stop command and stops controlling the peripheral. When the number of times the completion interrupt is output reaches the stop designation number preset by the setting unit, the counter outputs a process completion command for stopping the control of the peripheral to the control unit. Even if the control unit receives the process completion command, the control of the peripheral is continued until the operation of the last peripheral defined in the operation sequence is completed and the completion interrupt is output, and the control of the peripheral is stopped together with the output of the completion interrupt. The semiconductor device according to Supplementary Note 2.

[0105] (Supplementary Note 4) The control unit includes a buffer for storing another operation sequence of the peripheral different from the operation sequence, and a reload control unit for updating the operation sequence. When the number of times the completion interrupt is output reaches the update designation number preset by the setting unit, the counter outputs a reload command for requesting an update of the operation sequence to the control unit. Upon receiving the reload command, the control unit updates the operation sequence to the other operation sequence stored in the buffer in accordance with the output of the completion interrupt signal, and continues to control the peripheral according to the updated operation sequence. The semiconductor device according to Supplementary Note 3.

[0106] (Supplementary Note 5) The control unit is a control device that realizes the linked operation of the peripherals without relying on software processing. The semiconductor device according to any one of Supplementary Notes 1 to 4.

Explanation of Reference Numerals

[0107] 1 HLC 2 Sequencer 3 APB 4 OR circuit 5 AND circuit 6 to 14, 16, 17 Buses 15 Counter 18 Reload control unit 19 Buffer 20 Sequence table 100 Semiconductor device

Claims

1. A control unit that stores in advance the operation order of a plurality of peripherals and controls each of the peripherals without using software; A setting unit that sets a signal affecting the control of the peripheral to the control unit; An AND circuit that outputs an end interrupt output from the output terminal by the control unit when the operation of each peripheral is completed according to the operation order, and a logical product of a repetition permission that sets whether to repeatedly execute the operation of each peripheral according to the operation order; An OR circuit that outputs a logical sum of the output of the AND circuit and a signal output by the setting unit, which is a start command that instructs the control unit in a stopped state where the peripheral is not being controlled to start controlling the peripheral, to the control unit; Comprising; The setting unit outputs the start command to the control unit while keeping the setting of the repetition permission valid Semiconductor device.

2. The setting unit sets a forced stop command for stopping the control of the peripheral and a stop state selection for selecting a method of stopping the control of the peripheral to the control unit, When the value of the stop state selection when the control unit receives the forced stop command is the first value, the control unit stops the control of the peripheral even before the operation of the last peripheral defined in the operation order is completed when the forced stop command is received. If the value of the stop state selection when the forced stop command is received is the second value, even if the forced stop command is received, the control of the peripheral is continued until the operation of the last peripheral defined in the operation order is completed and the end interrupt is output, and the control of the peripheral is stopped together with the output of the end interrupt The semiconductor device according to claim 1.

3. Connected between the input terminal and the output terminal of the AND circuit, and including a counter that measures the number of times the end interrupt is output from when the control unit receives the start command and starts controlling the peripheral to when the control unit receives the forced stop command and stops controlling the peripheral, When the number of times the end interrupt is output reaches a stop specified number preset by the setting unit, the counter outputs a process completion command for stopping the control of the peripheral to the control unit Even if the control unit has received the processing completion command, the control of the peripheral is continued until the operation of the last peripheral specified in the operation sequence is completed and the completion interrupt is output, and the control of the peripheral is stopped together with the output of the completion interrupt. The semiconductor device according to claim 2.

4. The control unit includes a buffer that stores another operation sequence of the peripheral different from the operation sequence, and a reload control unit that updates the operation sequence. When the number of output times of the completion interrupt reaches the update specified number set in advance by the setting unit, the counter outputs a reload command for requesting an update of the operation sequence to the control unit. The control unit that has received the reload command updates the operation sequence to the other operation sequence stored in the buffer in accordance with the output of the completion interrupt signal, and continues to control the peripheral according to the updated operation sequence. The semiconductor device according to claim 3.

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