Semiconductor package

Abstract

To provide a semiconductor package having a stacked bridge die.SOLUTION: A semiconductor package includes: a first semiconductor chip having a semiconductor substrate and an upper bonding pad disposed on an upper surface of the semiconductor substrate; and a bridge die disposed on the first semiconductor chip, including a bridge substrate and a lower pad disposed on a lower surface of the bridge substrate to be in contact with the upper bonding pad, and at least partially protruding to the outside the first semiconductor chip. The bridge die and the first semiconductor chip have different structures.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor package.

Background Art

[0002] In response to the development of the electronics industry and user requirements, electronic devices have become smaller and lighter, and semiconductor packages used in electronic devices are required to be smaller, lighter, and have high performance and large capacity. In order to achieve miniaturization, weight reduction, high performance, and large capacity, research and development on semiconductor chips including through silicon vias (TSVs) and semiconductor packages in which the semiconductor chips are stacked have been continuously carried out. Since the interconnection between a plurality of semiconductor chips cannot be guaranteed by a printed circuit board, it can be connected by a separate interposer.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the technical problems to be solved by the present invention is to provide a semiconductor package having stacked semiconductor chips with improved structural reliability.

Means for Solving the Problems

[0004] To achieve the above technical problems, an embodiment of the present invention can provide a semiconductor package including a semiconductor substrate, a first semiconductor chip having upper bonding pads disposed on an upper surface of the semiconductor substrate, and a bridge die disposed on the first semiconductor chip, including a bridge substrate and lower pads disposed on a lower surface of the bridge substrate and in contact with the upper bonding pads, with at least a part protruding outside the first semiconductor chip, wherein the bridge die and the first semiconductor chip include different structures from each other.

[0005] To achieve the above technical problem, an embodiment of the present invention includes an insulating layer and a wiring layer disposed within the insulating layer, a redistribution structure including an upper contact pad disposed on the upper surface of the insulating layer and a lower contact pad disposed on the lower surface of the insulating layer, a first semiconductor chip disposed on the redistribution structure, having a semiconductor substrate and an upper bonding pad disposed on the upper surface of the semiconductor substrate, at least one second semiconductor chip disposed on the redistribution structure and around the first semiconductor chip, a bridge die disposed on the first semiconductor chip, including a bridge substrate and a lower pad disposed on the lower surface of the bridge substrate and contacting the upper bonding pad, with at least a part protruding outside the first semiconductor chip, and a vertical conductive structure connecting the lower pad of the bridge die exposed outside the first semiconductor chip and the upper contact pad of the redistribution structure. A semiconductor package can be provided.

Advantages of the Invention

[0006] According to the above-described embodiment, by forming some functional blocks of the logic chip as separate chips on the logic chip and attaching them as a bridge die (e.g., a semiconductor bridge), the area of the logic chip on the package can be reduced. In particular, by separating and vertically arranging a memory controller directly connected to a plurality of memory chips and a cache memory that occupies a large area into separate bridge dies, the size of the cache memory can be further expanded. In particular, by realizing bridge dies of various numbers on the upper part of the logic chip, bridge dies of an optimal number and an optimal shape can be realized according to the number of memory chips.

[0007] The various and beneficial advantages and effects of the present invention are not limited to the above-described content and can be more easily understood during the process of describing specific embodiments of the present invention.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0010] FIG. 1 is a diagram showing a semiconductor package according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view showing an embodiment along the line I-I' of FIG. 1, FIG. 3 is a plan view showing the semiconductor package of FIG. 1 cut along the line II-II' of FIG. 2, and FIG. 4 is a cross-sectional view showing an enlarged "A" region of FIG. 2.

[0011] Referring to FIGS. 1 to 4, the semiconductor package 300 can include a package substrate 311, an interposer 100, and a plurality of semiconductor chips 210, 220, 250. In one example, the semiconductor package 300 can further include a logic chip or a processor chip 210 disposed adjacent to the memory semiconductor chip 220 on the interposer 100 and at least one bridge die 250 disposed on the processor chip 210.

[0012] In one embodiment, the package substrate 311 can include an upper pad 324 disposed on the upper surface of the body, a lower pad 322 disposed on the lower surface of the body, and a redistribution circuit 330 that electrically connects the upper pad 324 and the lower pad 322. In one example, the package substrate 311 may be a support substrate on which the interposer 100, the processor chip 210, the bridge die 250, and the memory semiconductor chip 220 are mounted, and may be a semiconductor package substrate including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring substrate, or the like.

[0013] In one embodiment, the body of the package substrate 311 can contain different substances depending on the type of substrate. For example, when the package substrate 311 is a printed circuit board, it may be in a form where a wiring layer is further laminated on the copper foil laminate or one or both sides of the copper foil laminate of the body. In one example, solder resist layers may be formed on the lower and upper surfaces of the package substrate 311, respectively. The upper and lower pads 324, 322 and the redistribution circuit 330 can form an electrical path connecting the upper and lower surfaces of the package substrate 311. The upper and lower pads 324, 322, and the redistribution circuit 330 can contain a metallic substance. The pads 324, 322 and the redistribution circuit 330 can contain a metallic substance, for example, at least one metal or an alloy containing two or more metals among copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). In one example, the redistribution circuit 330 can include a multi-layer redistribution layer and vias connecting them. External connection terminals 380 connected to the lower pads 322 may be arranged on the lower surface of the package substrate 311. In one example, the external connection terminals 380 can contain tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or an alloy thereof.

[0014] In one embodiment, the interposer 100 can include a substrate 110, a lower protective layer 120, lower pads 130, bumps 140, through electrodes 150, and a wiring structure 170. In one example, a plurality of semiconductor chips 210, 220, 250 may be stacked on a package substrate 311 via the interposer 100. In one example, the interposer 100 can electrically connect a plurality of semiconductor chips 210, 220, 250. In one example, the substrate 110 may be formed of any one of silicon, an organic material, plastic, and a glass substrate. When the substrate 110 is a silicon substrate, the interposer 100 can be called a silicon interposer 100. In the interposer 100, when the substrate 110 is an organic substrate, the interposer 100 can be called a panel interposer 100. In one example, a lower protective layer 120 is disposed on the lower surface of the substrate 110, and the lower pads 130 can be disposed under the lower protective layer 120. The lower pads 130 can be connected to the through electrodes 150. The plurality of semiconductor chips 210, 220, 250 and the package substrate 311 can be electrically connected via the bumps 140 disposed under the lower pads 130.

[0015] In one embodiment, the wiring structure 170 is disposed on the upper surface of the substrate 110 and can include an insulating layer 171 and a single-layer or multi-layer wiring layer 172. When the wiring structure 170 has a multi-layer wiring structure, the wirings in different layers can be connected to each other by vertical contacts.

[0016] In one embodiment, the through electrode 150 can extend from the upper surface to the lower surface of the substrate 110 and penetrate the substrate 110. The through electrode 150 may extend into the wiring structure 170 and be electrically connected to the wiring of the wiring structure 170. In one example, when the substrate 110 is silicon, the through electrode 150 can be referred to as a TSV (Through Silicon Via). In one example, the interposer 100 may include only a wiring layer inside and may not include the through electrode 150.

[0017] In one embodiment, the interposer 100 can be used for the purpose of converting or transmitting an input electrical signal between the package substrate 311 and the plurality of semiconductor chips 210, 220, 250. That is, the interposer 100 may not include elements such as active elements and passive elements.

[0018] In one embodiment, the wiring structure 170 may be disposed below the through electrode 150. For example, the positional relationship between the wiring structure 170 and the through electrode 150 can be relative.

[0019] In one embodiment, the bumps 140 are disposed on the lower surface of the interposer 100 and can be electrically connected to the wiring of the wiring structure 170. The interposer 100 can be stacked on the package substrate 311 via the bumps 140. The bumps 140 can be connected to the wiring layer 172 of the wiring structure 170 via the through electrodes 150 and the lower pads 130. In one example, some of the lower pads 130 among the lower pads 130 used for power and ground are integrated and connected to the bumps 140 together, so that the number of the lower pads 130 can be more than the number of the bumps 140.

[0020] In one embodiment, the interposer 100 can include upper pads 160 on the wiring structure 170.

[0021] Referring to FIGS. 3 and 1, the upper pads 160 on the wiring structure 170 of the interposer 100 can include a first upper pad 160a disposed below the semiconductor chips 210, 220 and a second upper pad 160b connected to the bridge die 250.

[0022] The upper pad 160 disposed on the upper surface of the interposer 100 can be allocated and disposed in each region 210A, 220A, 250A according to a plurality of semiconductor chips 210, 220 disposed on the upper surface of the interposer 100. Specifically, a first upper pad 160a attached to the connection bump 216 of the first semiconductor chip 210 can be disposed within a processor chip region 210A where the first semiconductor chip 210, which is a processor, is disposed. The first upper pad 160a can also be disposed within a memory structure region 220A where the second semiconductor chip 220, which is a memory structure, is disposed. The first upper pads 160a disposed within each structure region 210A, 220A can include an area having the same or a similar range of sizes, and can have a circular or rectangular planar shape.

[0023] On the other hand, a region that protrudes from above the first semiconductor chip 210 to the outside of the first semiconductor chip 210 where the bridge die 250 is disposed can be defined as a bridge die region 250A, and the bridge die region 250A can be disposed at a continuous position without overlapping the processor chip region 210A.

[0024] A plurality of second upper pads 160b can be disposed within the bridge die region 250A. Vertical bumps 240 for contacting the lower pads 253b of the bridge die 250 that overlap in the z direction can be disposed on the second upper pads 160b.

[0025] The second upper pad 160b can have a larger width W2 and a larger area than the first upper pad 160a. When the first upper pad 160a has a first width W1, the second upper pad 160b can have a second width W2 that is larger than the first width W1. Also, the second upper pad 160b can have the same shape as the first upper pad 160a, for example, a circular shape, but can have a rectangular shape according to the embodiment. When having a circular or rectangular shape, its area can have a value larger than the area of the first upper pad 160a.

[0026] Between the second upper pads 160b disposed within the bridge die region 250A, they can be disposed separately from adjacent second upper pads 160b so as to satisfy a minimum separation distance. The above minimum separation distance can satisfy 100 to 100 μm and can have a value larger than the separation distance between the first upper pads 160a.

[0027] The semiconductor package 300 according to this embodiment can include first and second semiconductor chips 210 and 220 mounted on the interposer 100, and a bridge die 250. The first semiconductor chip 210 is disposed so as to partially overlap the bridge die 250, and complex signal lines in the PHY region can be interconnected by the bridge die 250. In a planar view of the semiconductor package 300 (see FIGS. 1 and 3), by shaping and disposing a part of the functional blocks in the first semiconductor chip 210 as separate chipletz (chiplets) in the bridge die 250, the area occupied by the first semiconductor chip 210 is reduced within the package 300, so that the area occupied by the memory chip 220 can be secured. Also, a part of the functional blocks included in the first semiconductor chip 210, for example, semiconductor structures such as cache memory and functional blocks directly connected to the second semiconductor chip 220 such as a memory controller can be implemented in the bridge die 250 as separate chip structures. By forming the functional blocks of the first semiconductor chip 210 as separate chip structures and disposing them overlapping the first semiconductor chip 210, the area of the first semiconductor chip 210 is reduced, enabling the implementation of more memory chips.

[0028] The second semiconductor chip 220 adopted in this embodiment can include a high bandwidth memory chip. The second semiconductor chip 220 can include a plurality (for example, four) of memory chips stacked on each other and connected to each other. The plurality of memory chips can each include a semiconductor substrate having an active surface and an inactive surface facing each other, and a through electrode, an upper pad, and a lower pad penetrating the semiconductor substrate. The upper pad of one memory chip can be connected to the lower pad of an adjacent memory chip. The lower pad of the lowermost memory chip can be connected to the redistribution pattern by a connection bump.

[0029] In a System in Package that integrates a large number of individual semiconductor chips into one package, the number of memory chips constituting the second semiconductor chip 220 can vary according to the use of the semiconductor package 300. That is, the number of memory chips constituting the second semiconductor chip 220 is not limited to the number shown in the drawings. The memory chips constituting the second semiconductor chip 220 can be adhered and stacked with each other via an adhesive member (not shown). The adhesive member may be a non-conductive film.

[0030] In one embodiment, an adhesive material layer can surround the space between the memory chip and the redistribution pattern, the space between a plurality of memory chips, and the sides of a plurality of memory chips. In one example, the adhesive material layer can include an Epoxy material. For example, the adhesive material layer may be an NCF (Non-Conductive Film), but the embodiment is not limited to such a material.

[0031] In one embodiment, the mold layer is arranged to cover a plurality of memory chips and the adhesive material layer, and can protect the plurality of memory chips and the adhesive material layer from the external environment. In one example, the mold layer can include an insulating material including a resin material such as an epoxy molding compound (EMC).

[0032] In some embodiments, the second semiconductor chip 220 can include a volatile memory chip and / or a non-volatile memory chip. The volatile memory chip may be, for example, a DRAM (dynamic random access memory), SRAM (static RAM), TRAM (thyristor RAM), ZRAM (zero capacitor RAM), or TTRAM (Twin Transistor RAM). Also, the non-volatile memory chip may be, for example, a flash memory, MRAM (magnetic RAM), STT-MRAM (spin-transfer torque MRAM), FRAM (ferroelectric RAM), PRAM (phase change RAM), RRAM (resistive RAM), nanotube RRAM, polymer RAM, or insulator resistance change memory. The second semiconductor chip 220 can include a substrate at the bottom and lower bonding pads 224 under the substrate. The lower bonding pads 224 can be connected to the first upper pads 160a by connection bumps 225, and the lower bonding pads 224 and the connection bumps 225 can be protected by a separate underfill 232.

[0033] In one embodiment, the first semiconductor chip 210 can be, as a processor chip, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, a chipset, an audio codec, a video codec, an application processor, a system on chip (SoC), or an application-specific integrated circuit (ASIC), etc. According to the types of elements included inside the first semiconductor chip 210, the semiconductor package 300 can be classified into a semiconductor package for a server or a semiconductor package for a mobile device, etc.

[0034] The first semiconductor chip 210 can include a semiconductor substrate 211 having an active surface and an inactive surface facing each other, and lower bonding pads 215 on the lower surface of the semiconductor substrate 211. The lower bonding pads 215 can be connected to the first upper pads 160a by connection bumps 216. The lower bonding pads 215 can include a surface treatment layer P formed to serve as pads. The surface treatment layer P is not particularly limited as long as it is known in the art, and can be formed, for example, by electrolytic gold plating, electroless gold plating, OSP, electroless tin plating, electroless silver plating, electroless nickel plating / replacement gold plating, DIG plating, HASL, etc., but is not limited thereto. The first semiconductor chip 210 in the present embodiment can further include a dielectric layer 212 disposed on the upper surface of the semiconductor substrate 211 and upper bonding pads 213 formed on the dielectric layer 212. The upper bonding pads 213 can be in contact with the lower bonding pads 253 disposed on the lower surface of the bridge die 250.

[0035] An underfill 231, 232 surrounding the connection bumps 216, 225 can be formed between the first and second semiconductor chips 210, 220 and the redistribution structure 170, respectively. The underfills 231, 232 can stably fix the first and second semiconductor chips 210, 220 on the interposer 100. For example, the underfills 231, 232 may be curable resins such as epoxy.

[0036] Referring to FIGS. 1 and 3, in the semiconductor package 300 according to the present embodiment, a first semiconductor chip 210 is disposed in a central region on the upper surface of the interposer 100, and a second semiconductor chip 220 can be disposed while surrounding the first semiconductor chip 210. The number of the second semiconductor chips 220 can be variously set. In FIGS. 1 to 4, four second semiconductor chips 220 can be disposed on the left and right sides of the first semiconductor chip 210, two on each side, with the first semiconductor chip 210 as the center.

[0037] The two second semiconductor chips 220 disposed on one side of the first semiconductor chip 210 can be arranged side by side in the y direction and arranged to have a first separation distance I1 from the first semiconductor chip 210.

[0038] At least one bridge die 250 can be disposed on the first semiconductor chip 210. As described above, the bridge die 250 is formed by separating a part of the functional blocks of the first semiconductor chip 210 into a separate chip structure, and can include a memory controller and a cache memory in FIGS. 1 to 4.

[0039] The memory controller may be a functional block that is connected to each of the second semiconductor chips 220, transmits and receives signals, and can read and write data stored in the second semiconductor chips 220. Therefore, the memory controller can be arranged one by one for each second semiconductor chip 220. A plurality of cache memories can be applied in the processor, and the cache memory is a buffer memory between the fast first semiconductor chip 210 and the second semiconductor chip 220 which is a slow-speed memory semiconductor chip, and can be defined as a general-purpose memory for compensating for the speed difference for storing the data of the second semiconductor chip 220 and utilizing it for the operation of the first semiconductor chip 210. Such a cache memory requires a larger memory storage capacity as the function of the processor improves, and it can be defined that the larger the cache memory, the better the performance of the package. The cache memory can be classified into L1, L2, and L3. The L1 cache memory can generally be built into the first semiconductor chip 210 and can be the memory first used for data use and reference. The L2 cache memory performs a function similar to that of the L1 cache memory. However, when the L1 cache memory is first utilized and the desired data does not exist in the L1 cache memory, the processor can search the L2 cache memory. The L2 cache memory is slower than the L1 cache memory but can have a speed faster than that of general memory (RAM).

[0040] The L3 cache memory performs functions similar to those of the L1 and L2 cache memories and can function as a memory for finding data not covered by the L2 cache memory. Therefore, when searching for data in the first semiconductor chip 210, access can be made in the order of the L1-L2-L3 cache memories, and it can be recognized that the larger the capacity of the L3 cache memory, the better the performance of the semiconductor package. Therefore, an increase in the capacity of the L3 cache memory is continuously required, which may lead to an increase in the size of the first semiconductor chip 210. An increase in the size of the first semiconductor chip 210 on the semiconductor package 300 having a predetermined area, that is, on the interposer 100, reduces the number of the second semiconductor chips 220, which may lead to an increase in the vertical stacking of the second semiconductor chips 220 and the like, which may lead to an increase in the process burden and an increase in the overall height of the package.

[0041] In an embodiment of the present invention, among some functional blocks of the first semiconductor chip 210, a memory controller and an L3 cache memory that are most closely related to the second semiconductor chip 220 are formed as separate chip structures, and such a chip structure can be arranged as a bridge die 250 on the first semiconductor chip 250.

[0042] At least one bridge die 250 can be arranged on the first semiconductor chip 210, and as shown in FIGS. 1 to 4, the bridge die 250 can be arranged in a 1:1 correspondence with each of the second semiconductor chips 220. Therefore, when four second semiconductor chips 220 are arranged around one first semiconductor chip 210, four bridge dies 250 can be arranged on the first semiconductor chip 210.

[0043] Each bridge die 250 can have the same area and the same shape, and can protrude from above the first semiconductor chip 210 toward the corresponding second semiconductor chip 220. Specifically, the bridge die 250 can include a first region 250a located on the first semiconductor chip 210 and a second region 250b protruding outside the first semiconductor chip 210 in the x-y plane. The area of the first region 250a may be larger than that of the second region 250b, but is not limited thereto.

[0044] When a plurality of bridge dies 250 are arranged on the first semiconductor chip 210, the plurality of bridge dies 250 are not arranged in the central region of the first semiconductor chip 210, and can be arranged limitedly in each corner region. A large amount of heat is generated in the central region of the first semiconductor chip 210 and the device layer is not arranged, and a heat dissipation chip or a heat dissipation layer may be arranged, but is not limited thereto. The plurality of bridge dies 250 are spaced apart from each other on the first semiconductor chip 210, and the second region 250b can be arranged so as to overlap the separation space between the first semiconductor chip 210 and the second semiconductor chip 220. At this time, the second region 250b does not overlap with the second semiconductor chip 220 in the z direction and can satisfy a separation distance I2 that separates them from each other. Each bridge die 250 can be arranged so that the first region 250a abuts on the upper surface of the first semiconductor chip 210. Each bridge die 250 will be described with reference to FIGS. 1 and 4.

[0045] The bridge die 250 can be arranged such that the first region 250a is attached to the first semiconductor chip 210 and the second region 250b protrudes outside the first semiconductor chip 210 and overlaps the separation space. The bridge die 250 may be provided as a bridge structure for interconnecting the first semiconductor chip 210 and the second semiconductor chip 220.

[0046] Referring to Fig. 4, the bridge die 250 employed in this embodiment includes a semiconductor block 251, a dielectric layer 252 disposed on the lower surface of the semiconductor block 251, and a wiring layer 254 formed on the dielectric layer 252. In this specification, the bridge die 250 is referred to as a "semiconductor bridge". The wiring layer 254 can include a lower contact pad 253 disposed on the lower surface of the bridge die 250. The semiconductor block 251 may be, for example, a silicon (Si) block. The wiring layer 254 can include a conductor pattern and vias connecting the same. The conductor pattern and vias can be formed as fine structures using semiconductor processes. The conductor pattern of the wiring layer 254 can have a small width. For example, the width and pitch of the conductor pattern may each be 1 μm or less.

[0047] The lower contact pad 253 can include a first lower contact pad 253a disposed in the first region 250a and a second lower contact pad 253b disposed in the second region 250b.

[0048] The first lower contact pad 253a can be in contact with the upper bonding pad 213 of the first semiconductor chip 210 to make a physical / electrical connection, and the second lower contact pad 253b can be connected to the vertical bump 240 for connecting to the second upper pad 160b of the interposer 100.

[0049] The second lower contact pad 253b can face the second upper pad 160b of the interposer 100 in the z direction and can be electrically / physically connected by the vertical bump 240.

[0050] The second lower contact pad 253b can have a width W4 greater than the width W3 of the first lower contact pad 253a and can have a larger area. The shapes of the second lower contact pad 253b and the first lower contact pad 253a may be different from each other. The first lower contact pad 253a can have a circular or angular shape like the first upper pad 160a of the interposer 100, and the lower surfaces of the first lower contact pad 253a and the second lower contact pad 253b can be located at the same level.

[0051] The bridge die 250 and the first semiconductor chip 210 can be connected by hybrid bonding, which is a connection process between semiconductor chips. Specifically, the first lower contact pad 253a of the bridge die 250 can be directly bonded to the upper bonding pad 213 of the first semiconductor chip 210 to form an intermetallic bond DB1. Such an intermetallic bond DB1 can join the bridge die 250 and the first semiconductor chip 210 to each other and ensure electrical connection. A lower bonding insulating layer is formed on the lower surface of the bridge die 250 employed in this embodiment, and the lower bonding insulating layer can have a substantially flat upper surface with the first lower contact pad 253a. The upper contact insulating layer 212 of the first semiconductor chip 210 and the lower bonding insulating layer of the bridge die 250 can be directly bonded to form a dielectric bond DB2.

[0052] The vertical bumps 240 adopted in this embodiment are conductive posts, and may be provided as a path for vertically connecting the interposer 100 and the bridge die 250. The conductive posts 240 may be formed by plating processes a plurality of times (for example, once) to form a desired height, but on the contrary, may be integral posts formed in a single layer. The vertical bumps 240 may be realized by an alloy containing a conductive material such as copper, but are not limited thereto. The vertical bumps 240 can connect the upper and lower parts to each other on the contact pads 160b and 253b having an area larger than that of the other pads 160a and 253a. Also, the vertical bumps 240 may be spaced apart so as to satisfy a predetermined separation distance from adjacent vertical bumps 240. The predetermined separation distance can satisfy 200 to 400 μm, preferably 250 to 350 μm. At this time, the predetermined width W5 of the vertical bumps 240 is smaller than the contact pads 160b and 253b of the lower and upper parts respectively, and can satisfy 150 to 250 μm.

[0053] The molding part 270 can seal the upper surfaces of the first and second semiconductor chips 210 and 220 and the bridge die 250, and can serve to protect the first and second semiconductor chips 210 and 220 and the bridge die 250 from the external environment. In the molding part 270, an appropriate amount of molding resin can be injected onto the upper surface of the interposer 100 by an injection process, and the outer shape of the semiconductor package 300 can be formed by a curing process. In some embodiments, the molding resin can include an epoxy-group molding resin or a polyimide-group molding resin. The molding part 270 can serve to protect the first and second semiconductor chips 210 and 220 from external influences such as impact. In some embodiments, the molding part 270 may be formed to surround the upper surfaces of the first and second semiconductor chips 210 and 220. In other embodiments, the molding part 270 may be formed to expose the upper surfaces of the first and second semiconductor chips 210 and 220 to the outside.

[0054] In the present embodiment, the semiconductor package 300 adopted may further include a heat dissipation member 390. The heat dissipation member 390 may be, for example, a heat slug or a heat sink. The heat dissipation member 390 may be in contact with the upper surface of the package substrate 310 and provided so as to surround the semiconductor package 300. The heat dissipation member 390 may be configured to be in direct contact with the upper surfaces of the first and second semiconductor chips 210 and 220, but is not limited thereto.

[0055] In some embodiments, a thermal interface material layer (TIM) may be disposed between the heat dissipation member 390 and the upper surfaces of the first and second semiconductor chips 210 and 220. In some embodiments, the heat dissipation member 390 may have an electromagnetic wave (EMI) shielding layer formed thereon, and such an electromagnetic wave shielding layer may be electrically connected to the ground layer of the package substrate 311.

[0056] FIGS. 5 and 6 are enlarged cross-sectional views showing semiconductor packages according to other embodiments of the present invention. FIGS. 5 and 6 are enlarged cross-sectional views of the "A" region of FIG. 2 enlarged as shown in FIG. 4.

[0057] Referring to FIG. 5, the semiconductor package 300a according to the present embodiment can be understood to be similar to the semiconductor package 300 described with reference to FIGS. 1 to 4, except that a first semiconductor chip 210 having a different structure is adopted. For the description of the components of the present embodiment, reference can be made to the description of the same or similar components of the semiconductor package 300 shown in FIGS. 1 to 4, unless otherwise stated.

[0058] The semiconductor package 300a of FIG. 5 can include a through - electrode 217 for connecting the upper bonding pad 213 and the lower wiring layer 232 to each other, with the first semiconductor chip 210 penetrating the semiconductor substrate 211. The through - electrode 217 can extend from the upper surface to the lower surface of the semiconductor substrate 211 and penetrate the semiconductor substrate 211. The through - electrode 217 can extend inside the wiring structure 230 and be electrically connected to the wiring layer 232 through the wiring pad 233 of the wiring structure 230. In one example, when the semiconductor substrate 211 is silicon, the through - electrode 217 can be referred to as a TSV (Through Silicon Via).

[0059] Referring to FIG. 6, the semiconductor package 300b according to this embodiment can be understood to be similar to the semiconductor package 300 described with reference to FIGS. 1 - 4, except that the first semiconductor chip 210 and the bridge die 250 of other structures are adopted. For the description of the components of this embodiment, unless otherwise stated, reference can be made to the description of the same or similar components of the semiconductor package 300 shown in FIGS. 1 - 4.

[0060] The semiconductor package 300b of FIG. 6 can include a through - electrode 217 for connecting the upper bonding pad 213 and the lower wiring layer 232 to each other, with the first semiconductor chip 210 penetrating the semiconductor substrate 211, and the bridge die 250 can also include a through - electrode 255 penetrating the semiconductor block 251. The through - electrode 217 of the first semiconductor chip 210 can be the same as that described in FIG. 5. The bridge die 250 can further include redistribution structures 252, 254 below the semiconductor block 251, and can include a redistribution insulating layer 252 and a wiring structure 254 forming the redistribution structures 252, 254. It can be understood that the wiring structure 254 includes first and second lower contact pads 253a, 253b.

[0061] The through electrode 255 of the bridge die 250 can extend from the upper surface to the lower surface of the semiconductor block 251 and penetrate the semiconductor block 251. The through electrode 255 can extend into the internal of the rewiring structures 252 and 254 and be electrically connected to the wiring structure 254 through the lower pad 256 of the wiring structure 254. In one example, when the semiconductor block 251 is silicon, the through electrode 255 can be referred to as a TSV (Through Silicon Via).

[0062] In the present embodiment, an upper pad 256 connected to the through via 255 can be arranged on the upper surface of the silicon block 251 of the bridge die 250 employed.

[0063] Hereinafter, with reference to FIGS. 7 to 13, various arrangement examples and electrical connection relationships of semiconductor packages according to various embodiments of the present invention will be described.

[0064] FIG. 7 shows the electrical connection in the semiconductor package 300 of FIGS. 1 to 6.

[0065] Referring to FIG. 7, as for the processor, the electrical signal from the first semiconductor chip 210(C) can be transmitted to the bridge die 250(B1 - B4) by the upper bonding pad 213 in contact by the hybrid bonding C1 and the first lower contact pad 253a of the bridge die 250(B1 - B4). When the bridge die 250(B1 - B4) includes a memory controller (MC1 - MC4) and an L3 cache memory (L31 - L34) respectively, in the bridge die 250(B1 - B4), the operation of the memory controller MC can be performed by the electrical signal, and it can be transmitted to the corresponding second semiconductor chip 220 by the connection of the second lower contact pad 253b and the vertical bump 240, and the wiring layer 172 of the interposer 100 and the pad connection (C3) between the interposer 100 and the second semiconductor chip 220. The electrical signal from the second semiconductor chip 220 can also be transmitted and stored in the cache memory L3 through the wiring layer 172 - vertical bump 240 - memory controller MC of the bridge die 250, and can be transmitted to the first semiconductor chip 210 through the hybrid bonding C1.

[0066] In this way, the functional block in the first semiconductor chip 210 is formed as a separate chip structure, and this is arranged in a structure connected to the first semiconductor chip 210 via hybrid bonding on the first semiconductor chip 210 as the bridge die 250(B1 - B4), and one side of the bridge die 250(B1 - B4) is protrudingly configured to overlap with the interposer 100, and an electrical path connected to the interposer 100 via a separate vertical bump 240 can be formed.

[0067] Therefore, the area of the first semiconductor chip 210 can be epoch - makingly reduced, and not only the second semiconductor chip 220 which is a memory block, but also the first semiconductor chip 210 which is a processor can be epoch - makingly reduced in the area of the semiconductor package 300 by vertical stacking, and the memory capacity such as the cache memory can be epoch - makingly increased.

[0068] Referring to FIG. 8, in the semiconductor package 300d according to this embodiment, a first semiconductor chip 210(C) is disposed in a central region on the upper surface of the interposer 100, and second semiconductor chips 220(M1-M4) can be disposed surrounding the first semiconductor chip 210. The number of the second semiconductor chips 220 can be set variously. In FIG. 8, two second semiconductor chips 220 are disposed on each of the left and right sides of the first semiconductor chip 210, which is the same as FIGS. 1 to 7.

[0069] Two bridge dies 250(B R 、B L ) can be disposed on the first semiconductor chip 210. The bridge die 250 can include a right bridge die 250(B R ) disposed on the right side and a left bridge die 250(B L ) disposed on the left side. The configurations and sizes of the bridge dies 250 may all be the same and may be symmetrically disposed on the first semiconductor chip 210. As described above, the bridge die 250 is formed by separating a part of the functional blocks of the first semiconductor chip 210 into individual chip structures, and each bridge die B R 、B L can include a memory controller and a cache memory.

[0070] The memory controllers MC1-MC4 may be functional blocks that are respectively connected to the first semiconductor chip 210, transmit and receive signals, and can read and write data stored in the second semiconductor chips 220(M1-M4). Therefore, one memory controller MC1-MC4 can correspond to each of the second semiconductor chips 220(M1-M4). The first and second memory controllers MC1 and MC2 are disposed in the right bridge die 250(B R ) and can be electrically connected to share the right L3 cache memory L3 R . The left bridge die 250(B L) Inside, a third and a fourth memory controller MC3 and MC4 are arranged, and the left L3 cache memory L3 L can be electrically connected so as to be shared.

[0071] Therefore, the electrical signal from the first semiconductor chip 210 is in contact with the upper bonding pad 213 by the hybrid bonding C1 and the first lower contact pad 253a of the left or right bridge die 250 (B R , B L ) and can be transmitted to the bridge die 250. In the bridge die 250, the operation of a specific memory controller MC1-MC4 can be performed by the electrical signal, and it can be transmitted to the corresponding second semiconductor chip 220 by the connection of the second lower contact pad 253b and the vertical bump 240, and the wiring layer 172 of the interposer 100 and the pad connection (C3) between the interposer 100 and the second semiconductor chip 220. The electrical signal from the second semiconductor chip 220 can also be stored in the cache memory L3 R , L3 L and can be transmitted to the first semiconductor chip 210 through the hybrid bonding C1. Therefore, in each bridge die 250, the L3 cache memory L3 R , L3 L for storing data of a plurality of second semiconductor chips 220 can be shared, and even when two bridge dies 250 are arranged, in the central region of the first semiconductor chip 210, it can be arranged to be exposed to the outside without arranging a separate die.

[0072] FIGS. 9 and 10 show a semiconductor package according to another embodiment of the present invention. FIG. 9 shows the arrangement of the semiconductor package of another embodiment, and FIG. 10 is a cross-sectional view showing the semiconductor package of FIG. 9 cut along the line III-III'.

[0073] Referring to FIGS. 9 and 10, in the semiconductor package 300e according to this embodiment, the first semiconductor chip 210 is disposed in the central region on the upper surface of the interposer 100, and four second semiconductor chips 220 (M1 - M4) are disposed surrounding the first semiconductor chip 210 (C), which is the same as FIGS. 1 to 7.

[0074] One bridge die 250 (B) can be disposed on the first semiconductor chip 210. The bridge die 250 (B) can cover the entire upper surface of the first semiconductor chip 210 and include a first region 250a overlapping the first semiconductor chip 210 and a second region 250b protruding outside the first semiconductor chip 210.

[0075] As described above, the bridge die 250 is formed by separating a part of the functional blocks of the first semiconductor chip 210 into separate chip structures, and the bridge die 250 can include memory controllers MC1 - MC4 and cache memory L3. The memory controllers MC1 - MC4 can be connected to correspond to the respective second semiconductor chips M1 - M4. At this time, a plurality of memory controllers MC1 - MC4 can be disposed in the bridge die 250 and electrically connected to share one L3 cache memory LC.

[0076] At this time, as shown in FIG. 10, a heat dissipation portion 260 may be disposed in the central region of the bridge die 250, that is, the central region of the first semiconductor chip 210. The heat dissipation portion 260 is not formed with devices and can be filled with a material having a high thermal conductivity such as bulk silicon. Therefore, the heat generated in the central region of the first semiconductor chip 210 can be conducted and released to the outside.

[0077] The lower insulating layer 252 and the lower contact pad 253 can also be disposed at the lower part of the heat dissipation part 260. The lower contact pad 253 can include highly conductive copper or the like and can be effective for heat conduction. When one bridge die 250 is disposed for a plurality of second semiconductor chips 220, a second region 250b protruding so as to be close to each of the second semiconductor chips 220 can be disposed. Accordingly, the area of the bridge die 250 can be larger than that of the first semiconductor chip 210. Also, the width of the second region 250b protruding into the above-mentioned space may be larger than the width of the region protruding to the side where the second semiconductor chip 220 is not disposed. Even when the heat dissipation part 260 is disposed in the central region of the bridge die 250, the upper surface of the bridge die 250 can be formed such that the heat dissipation part 260 and the semiconductor block 251 have a coplanar surface. The structure for signal connection between the first semiconductor chip 210, the bridge die 250, the interposer 100, and the second semiconductor chip 220 is the same as that described above, and one cache memory can be shared.

[0078] Referring to FIG. 11, in the semiconductor package 300f according to the present embodiment, a first semiconductor chip 210 (C) is disposed in the central region on the upper surface of the interposer 100, and second semiconductor chips 220 (M1-M8) can be disposed surrounding the first semiconductor chip 210 (C). The number of the second semiconductor chips 220 (M1-M8) can be variously set. In FIG. 8, eight second semiconductor chips 220 (M1-M8) can be disposed two by two on each side surface centering on the first semiconductor chip 210.

[0079] Four bridge dies 250 (B1-B4) can be disposed on the first semiconductor chip 210. The first to fourth bridge dies 250 (B1-B4) can be disposed in respective corner regions of the first semiconductor chip 210. When having a rectangular shape, one vertex can be disposed on the first semiconductor chip 210, and the remaining three vertices can be disposed so as to protrude from the first semiconductor chip 210. It can be connected to the interposer 100 through the vertical bump 240 below the protruding second region 250b.

[0080] The configurations and sizes of the respective bridge dies 250 (B1 - B4) may all be the same and may be symmetrically arranged on the first semiconductor chip 210. As described above, the bridge die 250 (B1 - B4) is formed by a part of the functional block of the first semiconductor chip 210 as a separate chip structure, and the bridge die 250 (B1 - B4) can include memory controllers MC1 - MC8 and cache memories L31 - L34. The memory controllers MC1 - MC8 can correspond one by one to each of the second semiconductor chips 220 (M1 - M8). Each bridge die 250 (B1 - B4) includes two memory controllers (e.g., MC1, MC2) connected to two adjacent first and second semiconductor chips (e.g., M1, M2), and can be electrically connected to share one L3 cache memory (e.g., L31).

[0081] Therefore, the electrical signal from the first semiconductor chip 210 is transmitted to the bridge die 250 by the hybrid bonding C1. In the bridge die 250, the operation of a specific memory controller MC1 - MC8 can be performed by the electrical signal, and it can be transmitted to the corresponding second semiconductor chip 220 through the connection of the second lower contact pad 253b and the vertical bump 240, and the wiring layer 172 of the interposer 100 and the pad connection (C3) between the interposer 100 and the second semiconductor chip 220. The electrical signal from the second semiconductor chip 220 can also be stored in the cache memory L3 by the memory controller MC through the connection of the wiring layer 172 - vertical bump 240 - bridge die 250 of the interposer 100, and can be transmitted to the first semiconductor chip 210 through the hybrid bonding C1. Therefore, the L3 cache memory for data storage of a plurality of second semiconductor chips 220 can be shared in each bridge die 250. Even when four bridge dies 250 (B1 - B4) are arranged, in the central region of the first semiconductor chip 210, it can be arranged to be exposed to the outside without arranging a separate die.

[0082] Referring to FIG. 12, in the semiconductor package 300g according to the present embodiment, the first semiconductor chip 210 is disposed in the central region on the upper surface of the interposer 100, and the second semiconductor chips 220 (M1-M10) can be disposed surrounding the first semiconductor chip 210. The number of the second semiconductor chips 220 (M1-M10) can be variously set. In FIG. 8, ten second semiconductor chips 220 (M1-M10) are disposed around the first semiconductor chip 210, two second semiconductor chips 220 (M1-M10) are disposed on each side, and three second semiconductor chips M1-M10 can be disposed on each of the upper and lower sides.

[0083] Therefore, compared with the semiconductor package 300f in FIG. 11, the semiconductor package further includes one semiconductor chip M5 and one semiconductor chip M10 on the upper and lower sides, respectively, and further includes corresponding bridge dies 250 (B3, B6), and can include a total of six bridge dies 250 (B1-B6).

[0084] At this time, the first type bridge dies 250 (B1, B2, B4, B5) connected to two second semiconductor chips 220 (M1-M10) and the second type bridge dies 250 (B3, B6) connected to one second semiconductor chip M5, M10 may be different from each other.

[0085] The first type bridge dies 250 (B1, B2, B4, B5) can occupy a larger area than the second type bridge dies 250 (B3, B6), include two memory controllers (for example, MC1, MC2) inside, and can also have a larger capacity of L3 cache memory. By disposing the second type bridge dies 250 (B3, B6) having a small area between the first type bridge dies 250 (B1, B2, B4, B5), additional bridge dies can be attached according to the increasing number of the second semiconductor chips 220, so that the bridge dies 250 and the second semiconductor chips 220 can be selectively attached according to the required memory capacity without changing the design of the entire semiconductor package.

[0086] As described above, the bridge die 250 is formed such that a part of the functional blocks of the first semiconductor chip 210 is formed as a separate chip structure, and the bridge die 250 can include a memory controller MC and a cache memory L3.

[0087] Therefore, the electrical signal from the first semiconductor chip 210 can be transmitted to the bridge die 250 by the hybrid bonding C1. In the bridge die 250, it can be transmitted to the corresponding second semiconductor chip 220 by the connection of the first lower contact pad 253b and the vertical bump 240, and the wiring layer 172 of the interposer 100 and the pad connection (C3) between the interposer 100 and the second semiconductor chip 220. The electrical signal from the second semiconductor chip 220 is also possible via the vertical bump 240 and can be transmitted to the first semiconductor chip 210 via the hybrid bonding C1. Therefore, the L3 cache memory L3 for storing the data of a plurality of second semiconductor chips 220 can be shared by each bridge die 250, and even when six bridge dies 250 (B1 - B6) are arranged, they can be arranged so as to be exposed to the outside without arranging a separate die in the central region of the first semiconductor chip 210.

[0088] Referring to FIG. 13, in the semiconductor package 300h according to the present embodiment, the first semiconductor chip 210 is arranged in the central region on the upper surface of the interposer 100, and the second semiconductor chips 220 (M1 - M10) can be arranged surrounding the first semiconductor chip 210. The number of the second semiconductor chips 220 (M1 - M10) can be set variously. In FIG. 8, ten second semiconductor chips 220 (M1 - M10) are arranged around the first semiconductor chip 210, two second semiconductor chips 220 (M1 - M10) are arranged on each side left and right, and three second semiconductor chips 220 (M1 - M10) can be arranged on each side up and down.

[0089] Therefore, the semiconductor package 300f in FIG. 11 can further include semiconductor chips M5 and M10, one each on the top and bottom, and can include two bridge dies 250 (B1, B2).

[0090] That is, the first bridge die 250 (B1) is disposed at the top and can be connected via vertical bumps 240 and an interposer 100 to be connected to five second semiconductor chips 220 (M1, M2, M8 - M10) above the central region of the first semiconductor chip 210.

[0091] The second bridge die 250 (B2) is disposed at the bottom and can be connected via vertical bumps 240 and an interposer 100 to be connected to five second semiconductor chips 220 (M3 - M7) below the central region of the first semiconductor chip 210.

[0092] The forms and configurations of the first and second bridge dies 250 (B1, B2) may be the same, and can be disposed to be exposed to the outside without a separate die disposed in the central region of the first semiconductor chip 210. The first and second bridge dies 250 (B1, B2) can each include memory controllers MC1 - MC10 connected to their respective memories and can be connected to share L3 cache memories L31 and L32.

[0093] At this time, when the ten second semiconductor chips M1 - M10 are disposed, there are separation spaces between the second semiconductor chips M1 - M10. Specifically, there are regions without the second semiconductor chips M1 - M10 in each corner region of the package 300h, and dummy chips (DM) 280 can be further included to prevent collapse of the above - mentioned corner regions.

[0094] In FIG. 13, when a large number of second semiconductor chips M1 - M10 are arranged within the semiconductor package 300h, in order to prevent sinking in the separated regions where the second semiconductor chips M1 - M10 are not arranged, by arranging a three - dimensional structure with a density similar to that of the second semiconductor chips M1 - M10, warpage of the substrate can be prevented. As the dummy chip (DM) 280, it can include a substance with a thermal conductivity and density similar to those of the second semiconductor chips M1 - M10, and can include substances such as bulk silicon to expand the heat dissipation function, but is not limited thereto.

[0095] The present invention is not limited by the above - described embodiments and the accompanying drawings, but is limited by the appended claims. Therefore, within the scope not departing from the technical idea of the present invention described in the claims, various forms of substitution, modification, and change are possible by those with ordinary knowledge in the art, and it can be said that these also belong to the scope of the present invention.

Explanation of Reference Numerals

[0096] 300: Semiconductor package 210, 220: Semiconductor chips 250: Bridge die 240: Vertical bump 100: Interposer 390: Heat dissipation part 311: Package substrate

Claims

1. A semiconductor package comprising a semiconductor substrate, a first semiconductor chip having upper bonding pads disposed on an upper surface of the semiconductor substrate, a bridge die disposed on the first semiconductor chip, including a bridge substrate and lower pads disposed on a lower surface of the bridge substrate and contacting the upper bonding pads, with at least a part protruding outside the first semiconductor chip. The bridge die and the first semiconductor chip include different structures from each other.

2. The lower pads include: a first lower pad contacting and bonded to the upper bonding pad of the first semiconductor chip; and a second lower pad coplanar with the first lower pad and exposed outside the first semiconductor chip. The semiconductor package according to claim 1.

3. The bridge die further includes a lower insulating layer exposing the lower pads below the bridge substrate. The first semiconductor chip further includes an upper insulating layer exposing the upper bonding pads on an upper surface of the semiconductor substrate. The lower insulating layer and the upper insulating layer are joined to each other, and the first lower pad and the upper bonding pad are joined to each other to form a hybrid bonding. The semiconductor package according to claim 2.

4. The second lower pad has a width larger than that of the first lower pad. The semiconductor package according to claim 2.

5. The first semiconductor chip further includes a through via connected to the upper bonding pad and penetrating the semiconductor substrate. The semiconductor package according to claim 1.

6. The bridge die further includes a through via connected to the lower pad and penetrating the bridge substrate. The semiconductor package according to claim 5.

7. A redistribution structure including an insulating layer and a wiring layer disposed within the insulating layer, an upper contact pad disposed on an upper surface of the insulating layer, and a lower contact pad disposed on a lower surface of the insulating layer; a first semiconductor chip disposed on the redistribution structure, having a semiconductor substrate and upper bonding pads disposed on an upper surface of the semiconductor substrate; at least one second semiconductor chip disposed on the redistribution structure and around the first semiconductor chip. Disposed on the first semiconductor chip, including a bridge substrate and a lower pad disposed on the lower surface of the bridge substrate and in contact with the upper bonding pad, and at least a part of the bridge die protrudes outside the first semiconductor chip. A semiconductor package including a vertical conductive structure that connects the lower pad of the bridge die exposed outside the first semiconductor chip and the upper contact pad of the redistribution structure. **Claim 8** The lower pad of the bridge die includes a first lower pad that is bonded to the upper bonding pad of the first semiconductor chip and a second lower pad that is bonded to the vertical conductive structure. The upper contact pad of the redistribution structure includes a first upper contact pad disposed below the first semiconductor chip and the second semiconductor chip and a second upper contact pad disposed below the vertical conductive structure. The semiconductor package according to claim 7. **Claim 9** The bridge die protrudes into the gap space between the first semiconductor chip and the second semiconductor chip. The semiconductor package according to claim 7. **Claim 10** The semiconductor package is electrically connected to the second semiconductor chip through the wiring layer of the redistribution structure from the vertical conductive structure. The semiconductor package according to claim 7.

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