Field effect transistor

Abstract

To provide a field effect transistor capable of preferably reducing an electric resistance of a path where an electric field relaxation region is connected to a source electrode, and provide a manufacturing method of them.SOLUTION: A field effect transistor 10 includes: a gate insulation film 16 and a gate electrode 18 that are arranged into a trench 14; and a source electrode 22. A semiconductor substrate 12 includes: a p-type electric field relaxation region 56; and a p-type pillar region 50 that is extended along a depth direction from a position where it is contacted to the source electrode to a position where it is contacted to the field relaxation region. The pillar region includes: a p-type contact region 52 that is provided at a position where it is contacted to the source electrode, and includes a p-type impurity concentration that is higher than a body region 42; and a p-type connection region 54 that is extended from a lower end of the contact region to a position where it is connected to the electric field relaxation region, and includes a p-type impurity concentration that is lower than that of the contact region, and is higher than the body region. A boundary of the contact region and the connection region is positioned onto an upper side of a z direction from the lower end of the body region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a field-effect transistor.

[0002] A trench-type gate electrode and a field-effect transistor having an electric field relaxation region for relaxing the electric field at the lower end of the trench are known. For example, Patent Document 1 discloses a field-effect transistor having an electric field relaxation region in contact with the lower end of the trench. Note that the electric field relaxation region may be disposed at a position away from the lower end of the trench. When the field-effect transistor is turned off, the depletion layer spreads from the electric field relaxation region to its surroundings, thereby relaxing the electric field at the lower end of the trench.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The field-effect transistor of Patent Document 1 has a contact region, a body region (also referred to as a base region), and a connection region. The contact region has a high p-type impurity concentration and is in contact with the source electrode. The body region is disposed below the contact region. Since the body region is a region where a channel is formed when the field-effect transistor is turned on, the p-type impurity concentration in the body region is low. The connection region is disposed below the body region and connects the body region and the electric field relaxation region. The connection region has a higher p-type impurity concentration than the body region. The electric field relaxation region is connected to the source electrode through the connection region, the body region, and the contact region. Since the p-type impurity concentration in the body region is low, the electrical resistance of the body region is high. Since the body region with a high electrical resistance is disposed between the connection region and the contact region, the electrical resistance of the path connecting the electric field relaxation region to the source electrode is high. For this reason, the potential of the electric field relaxation region is unstable. Also, by forming the body region deeply so that the contact region penetrates the body region, the electrical resistance of the connection path between the electric field relaxation region and the source electrode can be reduced. However, if the contact region with a high p-type impurity concentration is formed deeply, crystal defects increase in the semiconductor substrate and leakage current is likely to occur. In this specification, a technique for suitably reducing the electrical resistance of the path connecting the electric field relaxation region to the source electrode is proposed.

Means for Solving the Problems

[0005] The field-effect transistor disclosed in this specification includes a semiconductor substrate provided with a trench on its upper surface, a gate insulating film and a gate electrode disposed in the trench, and a source electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has a source region, a body region, a lower n-type region, an electric field relaxation region, and a pillar region. The source region is an n-type region in contact with the source electrode and the gate insulating film. The body region is a p-type region in contact with the gate insulating film below the source region. The lower n-type region is in contact with the body region from below, is in contact with the gate insulating film below the body region, and is an n-type region distributed below the lower end of the trench. The electric field relaxation region is disposed within a depth range including the lower end of the trench or within a depth range below the lower end of the trench, and is a p-type region in contact with the lower n-type region. The pillar region is a p-type region extending along the depth direction from the position in contact with the source electrode to the position in contact with the electric field relaxation region. The pillar region has a contact region and a connection region. The contact region is provided at the position in contact with the source electrode and is a p-type region having a p-type impurity concentration higher than that of the body region. The connection region extends from the lower end of the contact region to the position in contact with the electric field relaxation region and is a p-type region having a p-type impurity concentration lower than that of the contact region and higher than that of the body region. The boundary between the contact region and the connection region is located above the lower end of the body region.

[0006] In this field-effect transistor, there is no body region with a low p-type impurity concentration intervening between the contact region and the connection region, and the contact region and the connection region are in contact. Therefore, the electric field relaxation region is connected to the source electrode through the connection region and the contact region. As a result, the electrical resistance of the path connecting the electric field relaxation region to the source electrode is low, and the potential of the electric field relaxation region is stabilized. Further, since the boundary between the contact region and the connection region is located above the lower end of the body region, the contact region with a high p-type impurity concentration is provided within a shallow range near the upper surface of the semiconductor substrate. For this reason, there are few crystal defects present in the semiconductor substrate, and a leakage current is less likely to occur. Thus, according to this configuration, the electrical resistance of the path connecting the electric field relaxation region to the source electrode can be suitably reduced.

Brief Description of the Drawings

[0007]

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Mode for Carrying Out the Invention

[0008] The field-effect transistor 10 of Example 1 shown in FIGS. 1 and 2 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductor materials (for example, Si, GaN, Ga2O3, etc.). Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, and the direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction.

[0009] A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. On the upper surface 12a, each trench 14 extends linearly in the y direction. Each trench 14 is arranged at intervals in the x direction. A gate insulating film 16 and a gate electrode 18 are provided in each trench 14. The gate insulating film 16 covers the inner surface of each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered by an interlayer insulating film 20. As shown in FIG. 1, in the vicinity of the upper surface 12a of the semiconductor substrate 12, the semiconductor region is partitioned into a plurality of regions by the trenches 14. Hereinafter, each semiconductor region partitioned by the trench 14 (that is, the semiconductor region sandwiched by the trenches 14) is referred to as a partitioned region 60.

[0010] The field effect transistor 10 has a source electrode 22 and a drain electrode 24. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from each gate electrode 18 by the interlayer insulating film 20. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0011] The semiconductor substrate 12 has a source region 40, a body region 42, a lower n-type region 44, a plurality of pillar regions 50, and a plurality of electric field relaxation regions 56.

[0012] The source region 40 is an n-type region and has a high n-type impurity concentration. The source region 40 is provided within the partition region 60. The source region 40 is provided in a range including the upper surface 12a and is in ohmic contact with the source electrode 22. The source region 40 is in contact with the gate insulating film 16 on the side surface of the trench 14.

[0013] The body region 42 is a p-type region and has a low p-type impurity concentration. The body region 42 is provided within the partition region 60. The body region 42 is disposed below the source region 40 and is in contact with the source region 40 from below. The body region 42 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the source region 40.

[0014] The lower n-type region 44 is disposed below the body region 42. The lower n-type region 44 extends from the position in contact with the body region 42 to the lower surface 12b of the semiconductor substrate 12. The lower n-type region 44 has a current dispersion region 45, a JFET region 46, a drift region 47, and a drain region 48.

[0015] The current dispersion region 45 has a medium n-type impurity concentration. The current dispersion region 45 is provided within the partition region 60. The current dispersion region 45 is disposed below the body region 42 and is in contact with the body region 42 from below. The current dispersion region 45 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the body region 42.

[0016] The JFET region 46 is an n-type region having an n-type impurity concentration lower than that of the current dispersion region 45. The JFET region 46 is distributed across the regions within each partition region 60 and the regions below each partition region 60. The JFET region 46 is disposed below the current dispersion region 45 and is in contact with the current dispersion region 45 from below. The JFET region 46 is in contact with the gate insulating film 16 below the current dispersion region 45.

[0017] The drift region 47 is an n-type region having an n-type impurity concentration lower than that of the JFET region 46. The drift region 47 is disposed below the JFET region 46 and is in contact with the JFET region 46 from below.

[0018] The drain region 48 is an n-type region having an n-type impurity concentration higher than that of the current dispersion region 45. The drain region 48 is disposed below the drift region 47 and is in contact with the drift region 47 from below. The drain region 48 makes an ohmic contact with the drain electrode 24 on the lower surface 12b.

[0019] Each electric field relaxation region 56 is a p-type region and is disposed within a depth range below the lower end of the trench 14. Each electric field relaxation region 56 is disposed at a position surrounded by the JFET region 46 and is in contact with the JFET region 46. Each electric field relaxation region 56 is disposed at the lower part of each partition region 60 (more specifically, at the lower center in the x direction of each partition region 60). The width of the electric field relaxation region 56 in the x direction is wider than the width of the pillar region 50 in the x direction. FIG. 3 shows the arrangement of the trench 14, the pillar region 50, and the electric field relaxation region 56 when the semiconductor substrate 12 is viewed from above. In FIG. 3, the pillar region 50 overlaps with the electric field relaxation region 56. As shown in FIGS. 1 and 3, each electric field relaxation region 56 extends linearly in the y direction.

[0020] The pillar region 50 is a p-type region and is disposed within each partition region 60. Each pillar region 50 is disposed at the center in the x direction of each partition region 60. Each pillar region 50 extends along the z direction from the position in contact with the source electrode 22 to the position in contact with the electric field relaxation region 56. Each pillar region 50 penetrates through the source region 40 and the body region 42. As shown in FIGS. 1 and 3, each pillar region 50 extends linearly in the y direction. Each pillar region 50 has a contact region 52 and a connection region 54.

[0021] The contact region 52 is the upper portion of the pillar region 50 and has a high p-type impurity concentration. The contact region 52 extends along the z direction from the position in contact with the source electrode 22 to the depth range of the body region 42. Note that the depth range of the body region 42 means the depth range between the upper end and the lower end of the body region 42. That is, the contact region 52 penetrates through the source region 40. The p-type impurity concentration of the contact region 52 is higher than the n-type impurity concentration of the source region 40.

[0022] The connection region 54 is the lower portion of the pillar region 50 and has a p-type impurity concentration lower than that of the contact region 52 and higher than that of the body region. The p-type impurity concentration of the connection region 54 is higher than the n-type impurity concentration of the current dispersion region 45. The connection region 54 extends along the z direction from the position in contact with the lower end of the contact region 52 to the electric field relaxation region 56. The boundary between the contact region 52 and the connection region 54 is located within the depth range of the body region 42.

[0023] The graph G3 in FIG. 4 shows the distribution of the concentration D of p-type impurities on the center line CL (see FIG. 2) in the x direction of the pillar region 50. FIG. 4 shows the p-type impurity concentration distribution on the path from the center position CP in the z direction of the electric field relaxation region 56 to the upper surface 12a (i.e., the source electrode 22). Note that the vertical axis in FIG. 4 is displayed logarithmically. As shown in FIG. 4, the p-type impurity concentration is higher than the p-type impurity concentration Dc at the center position CP at any position on the path from the center position CP to the source electrode 22. Therefore, the electrical resistance is low throughout the path from the electric field relaxation region 56 to the source electrode 22.

[0024] Next, the operation of the field effect transistor 10 will be described. When the field effect transistor 10 is in use, a potential higher than that of the source electrode 22 is applied to the drain electrode 24. When a potential equal to or higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 42 within the range adjacent to the gate insulating film 16, and the source region 40 is connected to the current dispersion region 45 through the channel. Then, electrons flow from the source electrode 22 through the source region 40, the channel, the current dispersion region 45, the JFET region 46, the drift region 47, and the drain region 48 to the drain electrode 24. Since the current dispersion region 45 with a relatively high n-type impurity concentration is provided below the body region 42, the electrons flowing into the current dispersion region 45 from the channel are likely to diffuse in the x direction within the current dispersion region 45. Therefore, the electrons can be dispersed and flow within the lower n-type region 44. As a result, the on-resistance of the field effect transistor 10 is reduced.

[0025] When the potential of the gate electrode 18 is decreased to a value lower than the gate threshold value, the channel disappears and the field-effect transistor 10 is turned off. Then, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the lower n-type region 44, and depletion layers spread in the current dispersion region 45, the JFET region 46, and the drift region 47. Further, since the electric field relaxation region 56 is connected to the source electrode 22 by the pillar region 50, when the field-effect transistor 10 is turned off, a reverse voltage is also applied to the pn junction at the interface between the electric field relaxation region 56 and the JFET region 46. For this reason, the depletion layer spreads from the electric field relaxation region 56 to the JFET region 46. The depletion layer spreading from the electric field relaxation region 56 to the JFET region 46 suppresses the electric field concentration at the lower end of each trench 14. Therefore, this field-effect transistor has high breakdown voltage characteristics.

[0026] Also, in this field-effect transistor 10, the electric field relaxation region 56 is connected to the source electrode 22 by the pillar region 50 having a high p-type impurity concentration. That is, there is no region with a low p-type impurity concentration on the path from the electric field relaxation region 56 to the source electrode 22. For this reason, the electrical resistance of the path from the electric field relaxation region 56 to the source electrode 22 is low. Therefore, during the operation of the field-effect transistor 10, the potential of the electric field relaxation region 56 stabilizes at substantially the same potential as the source electrode 22. That is, during the operation of the field-effect transistor 10, the potential of the electric field relaxation region 56 is difficult to fluctuate. Therefore, the width of the depletion layer spreading from the electric field relaxation region 56 to the JFET region 46 can change with a fast response speed with respect to the operation of the field-effect transistor 10.

[0027] Next, a method for manufacturing the field-effect transistor 10 will be described. First, as shown in FIG. 5, a semiconductor substrate 12 having a lower n-type region 44, a body region 42, and an electric field relaxation region 56 is prepared. Note that at this stage, the trenches 14 and the pillar regions 50 are not provided in the semiconductor substrate 12. Each region shown in FIG. 5 may be formed by epitaxial growth or may be formed by ion implantation.

[0028] Next, as shown in FIG. 6, a mask 90 having an opening 92 is formed on the upper surface 12a of the semiconductor substrate 12. The opening 92 is disposed above the region where the pillar region 50 is to be formed. Next, p-type impurities are ion-implanted into the semiconductor substrate 12 through the mask 90. Here, p-type impurities are implanted at a high concentration into a shallow region near the upper surface 12a. More specifically, p-type impurities are implanted at a high concentration into a region shallower than the lower end of the body region 42. Thereby, the contact region 52 is formed. Next, as shown in FIG. 7, p-type impurities are implanted into the semiconductor substrate 12 through the mask 90 common to FIG. 6. Here, p-type impurities are implanted at a lower concentration than the contact region 52 in the range between the contact region 52 and the electric field relaxation region 56 (i.e., at a deep position as viewed from the upper surface 12a). Also, here, p-type impurities are implanted at a concentration higher than the n-type impurity concentration of the current dispersion region 45. Thereby, the connection region 54 is formed below the contact region 52. As a result, the pillar region 50 is formed.

[0029] The graph G1 in FIG. 4 shows the concentration distribution of p-type impurities implanted in the ion implantation process of FIGS. 6 and 7. Further, the graph G2 in FIG. 4 shows the p-type impurity concentration distribution in the electric field relaxation region 56 before the ion implantation process of FIGS. 6 and 7 is carried out. By adding the graph G1 and the graph G2, the distribution of the graph G3 is formed. As shown in the graph G1, the p-type impurities implanted in the ion implantation process are distributed such that the p-type impurities decrease more towards the lower side in the portion 54x located at the lower end of the implantation range. Also, as shown in the graph G2, before the ion implantation process, the electric field relaxation region 56 has a portion 56x at its upper end where the p-type impurity concentration decreases as it goes upward. Since the portion 54x and the portion 56x overlap, the graph G1 and the graph G2 intersect. The p-type impurity concentration Dx1 at the intersection of the graph G1 and the graph G2 is higher than half of the p-type impurity concentration Dc at the center position CP of the electric field relaxation region 56. Therefore, in the graph G3 obtained by adding the graph G1 and the graph G2, the p-type impurity concentration Dx2 at the position of the intersection is higher than the p-type impurity concentration Dc at the center position CP. For this reason, as shown in the graph G3, the p-type impurity concentration becomes high throughout the path from the center position CP to the source electrode 22.

[0030] Next, as shown in FIG. 8, the mask 90 is removed, and n-type impurities are ion-implanted into a shallow region near the upper surface 12a to form the source region 40. Here, n-type impurities are implanted at a concentration lower than the p-type impurity concentration in the contact region 52 and higher than the p-type impurity concentration in the body region 42 in a region shallower than the lower end of the contact region 52. For this reason, the shallow region of the body region 42 is n-type converted to become the source region 40, while the contact region 52 remains without being n-type converted. For this reason, the boundary between the contact region 52 and the connection region 54 is located within a depth range below the source region 40 and above the lower end of the body region 42.

[0031] After that, by forming the trench 14, the gate electrode 18, the source electrode 22, the drain electrode 24, etc., the field effect transistor 10 shown in FIGS. 1 to 3 is completed.

[0032] In the above manufacturing method, since p-type impurities are implanted into the semiconductor substrate 12 at a high concentration in the step of forming the contact region 52, crystal defects are formed at a high density around the contact region 52. Since the contact region 52 is formed in a shallow region near the upper surface 12a, high-density crystal defects are not formed at a deep position. Therefore, in the field-effect transistor manufactured by this manufacturing method, leakage current is less likely to occur.

[0033] Further, in the field-effect transistor 10 manufactured by the above manufacturing method, since the body region 42 does not intervene between the contact region 52 and the connection region 54, the electrical resistance between the electric field relaxation region 56 and the source electrode 22 is low. Therefore, the potential of the electric field relaxation region 56 can be stabilized. In particular, since the p-type impurity concentration is higher than the p-type impurity concentration Dc at the center position CP over the entire path from the center position CP of the electric field relaxation region 56 to the source electrode 22, the potential of the electric field relaxation region 56 can be made more stable.

[0034] Further, in the above manufacturing method, since the contact region 52 and the connection region 54 are formed by ion implantation through a common mask 90, the contact region 52 and the connection region 54 can be formed efficiently. In the above-described embodiment, the contact region 52 was formed prior to the connection region 54, but the contact region 52 may be formed after the connection region 54.

[0035] In the manufacturing method of the above-described Example 1, the electric field relaxation region 56 was formed prior to the pillar region 50, but the electric field relaxation region 56 may be formed after the pillar region 50.

[0036] Further, in the above-described Example 1, the lower n-type region 44 had the current dispersion region 45. However, as shown in FIG. 9, the lower n-type region 44 may not have the current dispersion region 45, and the JFET region 46 may be in contact with the body region 42.

[0037] In addition, in the above-described Example 1, the electric field relaxation region 56 was disposed below the lower end of the trench 14. However, as shown in FIG. 10, the electric field relaxation region 56 may be disposed within the depth range including the lower end of the trench 14.

[0038] In addition, in the above-described Example 1, the interface between the contact region 52 and the connection region 54 was disposed within the depth range of the body region 42. However, as shown in FIG. 11, the interface between the contact region 52 and the connection region 54 may be disposed within the depth range of the source region 40.

[0039] In addition, in the above-described Example 1, the electric field relaxation region 56 did not contact the trench 14. However, as shown in FIGS. 12 and 13, the electric field relaxation region 56 may contact the lower end of the trench 14. In this case, as shown in FIG. 12, the pillar region 50 may extend linearly along the x direction (i.e., the direction intersecting the trench 14). Even with this configuration, since the pillar region 50 is disposed within each partition region 60, the potential of each electric field relaxation region 56 can be stabilized.

[0040] In addition, in the above-described Example 1, the trench 14 extended linearly. However, as shown in FIGS. 14 and 15, the trench 14 may extend in a lattice shape. A plurality of square partition regions 60 are formed on the upper surface 12a of the semiconductor substrate 12. In this case, for example, the pillar region 50 can be provided at the center of each partition region 60. Even with this configuration, since the pillar region 50 is disposed within each partition region 60, the potential of each electric field relaxation region 56 can be stabilized.

[0041] In addition, as shown in FIG. 16, the connection region 54 may penetrate the electric field relaxation region 56. However, it is easier to reduce the electric field concentration around the electric field relaxation region 56 when the connection region 54 does not penetrate the electric field relaxation region 56 as shown in FIGS. 1 and 2.

[0042] The configurations of the technology disclosed in this specification are listed below. (Configuration 1) A field effect transistor, A semiconductor substrate provided with a trench on it, A gate insulating film and a gate electrode disposed in the trench, A source electrode in contact with the upper surface of the semiconductor substrate, having, the semiconductor substrate is, an n-type source region in contact with the source electrode and the gate insulating film, a p-type body region in contact with the gate insulating film below the source region, in contact with the body region from below, in contact with the gate insulating film below the body region, and distributed below the lower end of the trench, a lower n-type region, disposed within a depth range including the lower end of the trench or within a depth range below the lower end of the trench, a p-type electric field relaxation region in contact with the lower n-type region, a p-type pillar region extending along the depth direction from a position in contact with the source electrode to a position in contact with the electric field relaxation region, having, the pillar region is, provided at a position in contact with the source electrode and has a p-type contact region having a higher p-type impurity concentration than the body region, extending from the lower end of the contact region to a position in contact with the electric field relaxation region and having a p-type connection region having a lower p-type impurity concentration than the contact region and higher than the body region, having, a boundary between the contact region and the connection region is located above the lower end of the body region, a field effect transistor. (Configuration 2) In at least a part of the cross section, the width of the electric field relaxation region is wider than the width of the pillar region, On the center line in the width direction of the pillar region, the p-type impurity concentration on the path from the center position in the depth direction of the electric field relaxation region to the source electrode is higher than the p-type impurity concentration at the center position, The field effect transistor according to Configuration 1. (Configuration 3) A plurality of the trenches are provided on the upper surface of the semiconductor substrate, and the pillar regions are provided in respective semiconductor regions partitioned by the trenches. The field effect transistor according to Configuration 1 or 2. (Configuration 4) The field effect transistor according to any one of Configurations 1 to 3, wherein the connection region does not penetrate the electric field relaxation region. (Configuration 5) The lower n-type region has a first n-type region in contact with the body region from below, and a second n-type region in contact with the first n-type region from below and having a lower n-type impurity concentration than the first n-type region. The field effect transistor according to any one of Configurations 1 to 4, wherein the p-type impurity concentration of the connection region is higher than the n-type impurity concentration of the first n-type region. (Configuration 6) (Configuration 6) The field effect transistor according to any one of Configurations 1 to 5, wherein within the depth range of the source region, the p-type impurity concentration of the pillar region is higher than the n-type impurity concentration of the source region. (Configuration 7) A method for manufacturing a field effect transistor according to any one of Configurations 1 to 6, the method comprising: a contact region forming step of forming the contact region by implanting p-type impurities into the semiconductor substrate through a mask; and a connection region forming step of forming the connection region by implanting p-type impurities into the semiconductor substrate through the mask common to the contact region forming step. The manufacturing method having the above steps. (Configuration 8) In a first concentration distribution which is the concentration distribution of the p-type impurities implanted in the connection region forming step, a portion where the concentration decreases more towards the lower side overlaps with a portion where the concentration decreases more towards the upper side in a second concentration distribution which is the concentration distribution of the p-type impurities in the electric field relaxation region. The p-type impurity concentration at the intersection where the first concentration distribution and the second concentration distribution intersect is higher than half of the p-type impurity concentration at the central position in the depth direction of the electric field relaxation region. The manufacturing method according to Configuration 7.

[0043] As described in detail above for the embodiments, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples exemplified above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology exemplified in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Reference Numerals

[0044] 14: Trench 16: Gate Insulating Film 18: Gate Electrode 22: Source Electrode 40: Source Region 42: Body Region 44: Lower n-Type Region 50: Pillar Region 52: Contact Region 54: Connection Region 56: Electric Field Relaxation Region

Claims

1. A field effect transistor, comprising: a semiconductor substrate having a trench formed on its upper surface; a gate insulating film and a gate electrode disposed in the trench; a source electrode in contact with the upper surface of the semiconductor substrate; wherein the semiconductor substrate includes an n-type source region in contact with the source electrode and the gate insulating film; a p-type body region in contact with the gate insulating film below the source region; a lower n-type region in contact with the body region from below, in contact with the gate insulating film below the body region, and distributed below the lower end of the trench; a p-type electric field relaxation region disposed within a depth range including the lower end of the trench or within a depth range below the lower end of the trench, and in contact with the lower n-type region; a p-type pillar region extending along the depth direction from a position in contact with the source electrode to a position in contact with the electric field relaxation region; wherein the pillar region includes a p-type contact region provided at a position in contact with the source electrode and having a p-type impurity concentration higher than that of the body region; a p-type connection region extending from the lower end of the contact region to a position in contact with the electric field relaxation region, having a p-type impurity concentration lower than that of the contact region and higher than that of the body region; wherein a boundary between the contact region and the connection region is located above the lower end of the body region; a field effect transistor.

2. In at least a part of a cross section, a width of the electric field relaxation region is wider than a width of the pillar region, and on a center line in a width direction of the pillar region, a p-type impurity concentration on a path from a center position in a depth direction of the electric field relaxation region to the source electrode is higher than a p-type impurity concentration at the center position, the field effect transistor according to Claim 1.

3. a plurality of the trenches are formed on the upper surface of the semiconductor substrate, and the pillar region is provided in each of semiconductor regions partitioned by the trenches, the field effect transistor according to Claim 1 or 2.

4. the field effect transistor according to Claim 1 or 2, wherein the connection region does not penetrate the electric field relaxation region.

5. the lower n-type region includes a first n-type region in contact with the body region from below, and a second n-type region in contact with the first n-type region from below and having an n-type impurity concentration lower than that of the first n-type region, wherein The field-effect transistor according to claim 1 or 2, wherein the p-type impurity concentration in the connection region is higher than the n-type impurity concentration in the first n-type region.

6. The field-effect transistor according to claim 1 or 2, wherein the p-type impurity concentration in the pillar region is higher than the n-type impurity concentration in the source region within the depth range of the source region.

7. A method for manufacturing a field-effect transistor according to claim 1 or 2, comprising: a contact region forming step of forming the contact region by implanting p-type impurities into the semiconductor substrate through a mask; a connection region forming step of forming the connection region by implanting p-type impurities into the semiconductor substrate through the mask common to the contact region forming step; A manufacturing method having the above steps.

8. In a first concentration distribution which is the concentration distribution of the p-type impurities implanted in the connection region forming step, a portion where the concentration decreases toward the lower side overlaps with a portion where the concentration decreases toward the upper side in a second concentration distribution which is the concentration distribution of the p-type impurities in the electric field relaxation region, and the p-type impurity concentration at an intersection where the first concentration distribution and the second concentration distribution intersect is higher than half of the p-type impurity concentration at the central position in the depth direction of the electric field relaxation region. The manufacturing method according to claim 7.

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