Plasma chamber and method for cleaning chamber component

Abstract

To provide a plasma processing system and a method for processing plasma for preferentially cleaning a desired surface of a substrate supporting assembly by manipulating at least one characteristic of an on-site plasma.SOLUTION: The method for processing plasma includes the steps of: generating plasma in a processing region defined by a chamber lid and a substrate support assembly; exposing an edge ring and a substrate support surface to the plasma; and establishing a pulse voltage (PV) waveform in an edge control electrode.SELECTED DRAWING: Figure 7A

Description

Technical Field

[0001]

[0001] Embodiments herein are directed to a processing chamber configured to generate capacitively coupled plasma or inductively coupled plasma of a gas or vapor material supplied to a chamber space, particularly for a processing chamber configured to generate capacitively coupled plasma or inductively coupled plasma of a gas or vapor material supplied to a chamber space and process a semiconductor substrate therein, which is used in semiconductor device manufacturing, particularly for a processing chamber configured to generate capacitively coupled plasma or inductively coupled plasma of a gas or vapor material supplied to a chamber space and process a semiconductor substrate therein.

Background Art

[0002]

[0002] An electrostatic chuck (ESC) is commonly used in semiconductor device manufacturing processes where a vacuum chuck is not feasible and a mechanical clamp is undesirable, such as for supporting and fixing a substrate in a low-pressure environment of a processing chamber. A typical ESC is formed of one or more layers of a dielectric material providing a surface (e.g., a substrate support surface) for supporting the substrate, and further includes chucking electrodes embedded in one or more layers of the dielectric material or disposed between one or more layers of the dielectric material. By applying a potential difference between the substrate and the chuck electrodes to generate an electrostatic attraction therebetween, the substrate is fixed to the ESC.

[0003]

[0003] The ESC is often part of an assembly configured to control aspects of a plasma-assisted process performed within a processing chamber, such as a plasma-assisted etching process in which ions are collided with a material surface of the substrate through an opening in a mask layer formed on the substrate surface. In a typical plasma-assisted etching process, the substrate is placed on the ESC, plasma is formed on the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath, i.e., a region depleted of electrons formed between the plasma and the substrate surface.

[0004]

[0004] The ESC assembly may include an edge ring used to improve the non-uniformity of plasma processing near the edge of the substrate by reducing the electrical and thermal discontinuity between the edge of the substrate and the portion of the ESC assembly disposed outwardly from the edge of the substrate. Typically, the edge ring is disposed to surround the substrate and is sized to allow at least some tolerance for positioning the substrate on the ESC such that an inward surface of the edge ring and the outer peripheral edge of the substrate define a gap region therebetween.

[0005]

[0005] Generally, process by-products from plasma-assisted processes will accumulate on the chamber surfaces, including the surface of the ESC assembly. Conventional methods of cleaning such by-products involve exposing the chamber surface to reactive species of a cleaning gas, which can be formed using a remote plasma source and flowed into the processing chamber or formed by flowing the cleaning gas into the chamber to form in-situ plasma. The reactive species of the cleaning gas react with the process by-products formed on the chamber surface to form volatile species, which are discharged from the processing chamber through the exhaust. In general, it is optimal to minimize the number and / or duration of chamber cleaning processes, as they are associated with downtime and surface damage to chamber components caused by repeated exposure to the activated cleaning gas.

[0006]

[0006] Unfortunately, undesirable process by-products often accumulate in a gap between a part of the ESC assembly, e.g., between the outer peripheral edge of the substrate and the inward portion of the edge ring, well before a chamber cleaning process is required for other processing components disposed therein. The process by-products accumulated in the gap can be transferred to the bevel edge of the substrate and / or can cause plasma instabilities that cause undesirable arc discharges between the substrate and the edge ring. Surface defects due to the transferred process by-products and / or damage related to arc discharges at the substrate edge can cause reliability problems or failures of the devices formed on the substrate, and as a result, the yield of usable devices formed on the substrate may be suppressed. Particles induced by the arc discharge can also increase chamber contamination and increase the chamber downtime for cleaning and maintenance, thus potentially reducing the system's operating rate and production capacity. Frequently using conventional chamber cleaning methods to clean the gap of the ESC reduces the system's operating rate and production capacity, and further has the problem of potentially damaging other surfaces of the ESC, such as the substrate support surface, and reducing its service life.

[0007]

[0007] Accordingly, what is needed in the art is a system and method for solving the above problems.

Summary of the Invention

[0008]

[0008] Embodiments provided herein generally include a plasma processing system configured to preferentially clean a desired surface of a substrate support assembly by manipulating one or more characteristics of in-situ plasma, and related methods.

[0009]

[0009] In one embodiment, the plasma processing method is: (a) generating plasma within a processing region defined by a chamber lid and a substrate support assembly, the substrate support assembly including a first portion of a dielectric material forming a substrate support surface, an edge ring surrounding the substrate support surface, the edge ring including a plasma facing surface and one or more edge pocket surfaces disposed inwardly from the plasma facing surface, a bias electrode disposed spaced apart from the substrate support surface by the first portion of the dielectric material, and an edge control electrode disposed at a distance from the center of the bias electrode, the bias electrode being electrically connected to a first pulse voltage (PV) waveform generator configured to establish a first pulse voltage (PV) waveform at the bias electrode, and the edge control electrode being electrically connected to a second bias generator configured to establish a second pulse voltage (PV) waveform at the edge control electrode; (b) exposing the edge ring and the substrate support surface to the plasma; and (c) simultaneously with (b), establishing a second pulse voltage (PV) waveform at the edge control electrode.

[0010] In another embodiment, the plasma processing method comprises: (a) igniting and maintaining a plasma within a processing region of a processing chamber, the plasma including a first portion disposed between a substrate support surface of a substrate support assembly and a chamber lid, and a second portion disposed between an edge ring and the chamber lid, the substrate support assembly including a first portion of a dielectric material forming the substrate support surface, and a bias electrode spaced from the substrate support surface by the first portion of the dielectric material, the bias electrode being electrically connected to a first pulse voltage (PV) waveform generator configured to establish a first pulse voltage (PV) waveform at the bias electrode, an edge control electrode disposed at a distance from the center of the bias electrode and electrically connected to a second pulse voltage (PV) waveform generator, and an edge ring surrounding the substrate support surface and including one or more edge pocket surfaces that may define an edge pocket region by at least a partially lifted substrate disposed on the substrate support surface, the method including igniting and maintaining the plasma; (b) using the second pulse voltage (PV) waveform generator to establish a second pulse voltage (PV) waveform at the edge control electrode; and (c) exposing at least a partially lifted substrate to the plasma.

[0011]

[0011] In another embodiment, the processing method is (a) igniting and maintaining a plasma from a gas or vapor supplied to a processing region, the processing region being defined by a chamber lid and a substrate support assembly facing the chamber lid, the substrate support assembly including a first portion of a dielectric material forming a substrate support surface, a first electrode spaced from the substrate support surface by the first portion of the dielectric material, an edge ring surrounding the substrate support surface and having one or more edge pocket surfaces defining an edge pocket region by an outer peripheral edge of a substrate disposed at least partially lifted on the substrate support surface, and a second electrode spaced from the edge ring by a second portion of the dielectric material, the substrate support assembly being electrically connected to an RF generator that supplies a radio frequency (RF) signal used to ignite and maintain the plasma, the RF signal establishing a first RF waveform at the first electrode and a second RF waveform at the second electrode, the second electrode being electrically connected to an edge tuning circuit configured to adjust one or more characteristics of the second RF waveform relative to the first RF waveform to control the uniformity of the plasma density within the processing region, at least one characteristic of the second RF waveform being different from the characteristics of the first RF waveform, and the second electrode, and (b) exposing one or more edge pocket surfaces to the plasma.

[0012]

[0012] In another embodiment, the plasma chamber includes a chamber body defining a processing space and a chamber lid, and the substrate support assembly is disposed within the processing space facing the chamber lid. The substrate support assembly may include a support base and a substrate support disposed on the support base. The substrate support may include a dielectric material forming a substrate support surface, a bias electrode disposed within the dielectric material and spaced from the substrate support surface and the support base by portions of the dielectric material, and an edge control electrode disposed at a distance from the center of the bias electrode. The chamber also includes an edge tuning circuit electrically connected to the edge control electrode and a non-transitory computer-readable medium having instructions for performing the method, the method including: a) generating a plasma from a gas or vapor supplied to the processing space by using a radio frequency (RF) signal supplied to the support base, the RF signal being supplied to the support base by an RF signal generator and establishing a first RF waveform at the bias electrode and a second RF waveform at the edge control electrode; and b) adjusting one or more characteristics of the second RF waveform relative to the first RF waveform by using the edge tuning circuit.

[0013]

[0013] Other embodiments include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method.

[0014]

[0014] Note, however, that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, and other equally valid embodiments may be tolerated. Note, however, that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, and other equally valid embodiments may be tolerated.

Brief Description of the Drawings

[0015]

Figure 1A

Figure 1B

Figure 1C

[0016] Proximate schematic cross-sectional view of a portion of the substrate support assembly shown in FIG. 1A according to one embodiment.

Figure 1D

Figure 2

[0017] Simplified schematic diagram of a biasing and edge control scheme that can be used with one or both of the processing systems shown in FIGS. 1A - 1B according to one or more embodiments.

Figure 3A

[0018] Schematically shows an exemplary edge alignment circuit that can be used with one or both of the processing systems shown in FIGS. 1A - 1B according to one or more embodiments.

Figure 3B

Figure 3C

Figure 3D

[0019] Functionally equivalent circuit diagrams of different electrostatic chuck (ESC) types that can be used with one or both of the processing systems shown in FIGS. 1A - 1B.

Figure 3E

Figure 4

[0020] An example of a pulse voltage (PV) waveform that can be established using the embodiments described in this specification is shown.

Figure 5

[0021] A~B show exemplary high-frequency (RF) waveforms that can be established using the embodiments described in this specification.

Figure 6

[0022] A~D are graphs of simulation results using an exemplary edge synchronization circuit configuration according to the embodiments of this specification.

Figure 7A

[0023] It is a diagram showing a method that can be executed using the embodiments described in this specification.

Figure 7B

Figure 7C

Figure 8A

[0024] It is a schematic cross-sectional view of an edge portion of a substrate support assembly showing aspects of the method described in FIGS. 7A - 7C according to the embodiments of this specification.

Figure 8B

Figure 8C

Mode for Carrying Out the Invention

[0016]

[0025] Embodiments provided herein are directed to a processing system used in a semiconductor device manufacturing process and related methods. In particular, embodiments herein provide for cleaning portions of a substrate support assembly using plasma formed within a processing chamber, such as in-situ cleaning plasma. For example, in some embodiments, the system and method are preferentially used to clean accumulated processing by-products from portions of the substrate support assembly that define a gap region formed when a substrate is disposed on the substrate support assembly. Accordingly, the methods described herein can be used to beneficially in-situ plasma clean the gap region surface of the substrate support assembly while reducing plasma damage to other surfaces, such as the substrate support surface, and extending its useful life.

[0017]

[0026] In some embodiments, the processing system is configured for a plasma-assisted etching process in which plasma-generated ions are used to impinge on a material surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface. In a typical plasma-assisted etching process, a substrate is disposed on a substrate receiving surface of a substrate support assembly, a plasma is formed on the substrate using radio frequency (RF) power, and ions are accelerated from the plasma toward the substrate across a plasma sheath. The plasma sheath generally exhibits characteristics similar to those of a non-linear diode, such that the applied RF electric field is rectified and a DC voltage drop (i.e., self-bias) occurs between the substrate and the plasma.

[0018]

[0027] In some embodiments, the processing system is configured to control the characteristics of the plasma sheath using a pulsed voltage (PV) waveform supplied from one or more pulsed voltage (PV) generators to the bias electrode and the edge control electrode. In some embodiments, an RF waveform in which RF is generated from an RF generator to one or more power electrodes in the processing chamber is supplied to establish and maintain a plasma in the processing chamber, while one or more PV waveforms supplied from one or more PV generators are configured to establish a substantially constant sheath voltage (e.g., a constant difference between the plasma potential and the substrate potential) across the surface of the substrate and the surface of the substrate support assembly adjacent thereto. The established substantially constant sheath voltage provides a desired ion energy distribution function (IEDF) at the surface of the substrate during one or more plasma processing steps performed in the processing chamber.

[0019]

[0028] Some embodiments of the present disclosure include apparatuses and methods for controlling plasma uniformity, for example, by controlling the electron density in the bulk plasma across the outer peripheral edge region of the substrate and the adjacent surface of the substrate support assembly relative to the center of the substrate. In some embodiments, the plasma uniformity is controlled using an edge tuning circuit to control one or a combination of the voltage amplitude ratio between the RF waveform established at the edge control electrode and the RF waveform established at the bias electrode (e.g., the chucking electrode), the current amplitude ratio between the RF waveforms at the edge control electrode and the bias electrode, and the phase difference between the RF waveforms at each electrode.

[0020]

[0029] In some embodiments, the ion energy and directionality are controlled by biasing the substrate and the edge ring surrounding the substrate separately using a pulsed voltage (PV) waveform. The PV waveform can be established by electrodes that form part of the substrate support assembly and are generally located beneath the substrate (bias electrode) and the portion of the substrate support assembly located beneath the edge ring (edge control electrode), respectively. As described below, the PV waveform can be used to manipulate the shape of the plasma sheath boundary and focus ions accelerated across the sheath toward a desired region of the underlying surface. In some embodiments, the chamber component cleaning method targets the gap region between the edge of the substrate and / or the substrate support surface and the surrounding edge ring using focused ions, and removes unwanted process by-products such as polymers formed on the surface of the edge pocket region during a reactive ion etching (RIE) plasma process therefrom.

[0021]

[0030] In some embodiments, the ion flux (plasma density uniformity) is controlled by using an edge tuning circuit to adjust one or more characteristics of the RF waveform established at the edge control electrode relative to one or more characteristics of the RF waveform established at the bias electrode. For example, the edge tuning circuit can be used to adjust the voltage amplitude ratio or current amplitude ratio between the RF waveforms established at the edge control electrode and the bias electrode. The amplitude ratio of the voltage and / or current can be used to adjust the distribution of the plasma (plasma density) on the substrate support assembly, increasing or decreasing the density of the plasma on the edge ring relative to the density of the plasma on the central region of the substrate support assembly.

[0022]

[0031] In some embodiments, the edge tuning circuit is used to provide a desired phase difference between the RF waveforms established by the bias electrode and the edge control electrode. By adjusting the phase difference, the electric field generated between the two electrodes can be amplified. The amplification of the electric field can be manipulated to increase the concentration of ions and reactive neutral species in the gap region disposed between the edge of the substrate and the inward-facing surface of the edge ring. In some embodiments, the phase difference between the RF waveforms is controlled to concentrate the plasma between the bias electrode and the edge control electrode, and thus concentrate the plasma in the gap region.

[0023]

[0032] In some embodiments, the pulsed voltage (PV) waveform and / or the edge tuning circuit are used alone or in combination with a substrate unchucking method to preferentially clean the gap region while protecting the dielectric substrate support surface from ion-induced damage. For example, in some embodiments, the method includes focusing ions towards the gap region and / or concentrating the plasma in the gap region while the substrate is partially lifted from the substrate support surface.

[0024]

[0033] Advantageously, the present apparatus and method, alone or in combination, provide individual process tuning knobs for controlling the uniformity of ion energy and directionality, and can be used to individually control the uniformity of ion flux and / or reactive neutrals across the surface of the substrate support assembly and / or the substrate disposed thereon. For example, in some embodiments, the uniformity of ion energy and directionality can be controlled by adjusting the PV waveforms established by the edge control electrode and the bias electrode, respectively, to control the thickness profile of the plasma sheath and the shape of the sheath boundary (between the plasma sheath and the plasma) formed over the gap region of the substrate support assembly. The uniformity of ion flux and / or reactive neutral species concentration can be individually controlled by adjusting the RF waveforms established by the respective electrodes. Thus, the apparatus and method described herein facilitate targeted cleaning of the gap region of the substrate support assembly by controlling ion energy, ion directionality, and / or the concentration of ions and reactive neutrals. Exemplary processing systems that can be used to perform the method are shown in FIGS. 1A - 1D.

[0025] Example of a Plasma Processing System

[0034] FIGS. 1A and 1B are schematic cross-sectional views of processing systems 10A and 10B, respectively, each configured to perform one or more of the plasma processing methods specified herein. FIG. 1C is a close-up view of a portion of the substrate support assembly 136 shown in FIG. 1A. FIG. 2 is a simplified schematic diagram of a processing scheme that can be used with one or both of the processing systems 10A and 10B. FIGS. 3A - 3B are examples of an edge tuning circuit 170 that can be used with one or both of the processing systems 10A and 10B to control and adjust plasma uniformity.

[0026]

[0035] In some embodiments, the processing systems 10A and 10B shown in FIGS. 1A and 1B are configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. However, it should be noted that the multiple embodiments described herein may also be used with processing systems configured to be used in other plasma-assisted processes, such as plasma deposition processes, for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0027]

[0036] As shown in FIGS. 1A - 1B, the processing systems 10A - 10B are configured to form capacitively coupled plasma (CCP). The processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed within the processing space 129, and this upper space faces a lower electrode (e.g., substrate support assembly 136) disposed within the processing space 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically connected to one of the upper or lower electrodes and supplies an RF signal configured to ignite and maintain a plasma (e.g., plasma 101). This RF signal is capacitively coupled to each of the upper and lower electrodes and is disposed in the processing region therebetween. Usually, one of the opposing upper or lower electrodes is connected to ground or a second RF power source. In FIGS. 1A - 1B, one or more components of the substrate support assembly 136, such as the support base 107, are electrically connected to a plasma generator assembly 163 that includes the RF generator 118, and the chamber lid 123 is electrically connected to ground.

[0028]

[0037] As shown in FIGS. 1A-1B, each of the processing systems 10A and 10B includes a processing chamber 100, a substrate support assembly 136, a system controller 126, and a plasma control scheme 188. In the embodiments described herein, any one or combination of the features, configurations, and / or structural components of the processing system 10A, e.g., the structural components of the substrate support assembly 136 and / or the electrical components of the plasma control scheme 188, may be used in the processing system 10B, and vice versa is contemplated.

[0029]

[0038] The processing chamber 100 generally includes a chamber body 113 that includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define a processing space 129. The one or more sidewalls 122 and the chamber base 124 are generally materials sized and shaped to form a structural support for the elements of the processing chamber 100 and configured to withstand the pressures and additional energies applied thereto. On the other hand, the plasma 101 is generated within a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0030]

[0039] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more processing gases from a processing gas source 119 in fluid communication therewith to the processing space 129. In some embodiments, the gas is supplied through a showerhead (not shown). In another embodiment, the gas is supplied through the sidewall 122 (not shown). The substrate 103 is carried into and out of the processing space 129 through an opening (not shown) in one of the one or more sidewalls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0031]

[0040] In some embodiments, a plurality of lift pins 20 movably disposed through openings formed in the substrate support assembly 136 facilitate the transfer of the substrate to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are disposed upwardly and are connected to and / or engageable with a lift pin hoop (not shown) disposed within the processing space 129. The lift pin hoop may be connected to a shaft (not shown) that extends sealingly through the chamber base 124. The shaft may be connected to an actuator (not shown) used to raise and lower the lift pin hoop. When the lift pin hoop is in the raised position, it engages the plurality of lift pins 20 to raise the upper surfaces of the lift pins above the substrate support surface 105A, lift the substrate 103 therefrom, and enable access by a robot handler (not shown) to the non-active (back) surface of the substrate 103. When the lift pin hoop is in the lowered position, the plurality of lift pins 20 are flush with or recessed below the substrate support surface 105A and the substrate 103 is placed thereon.

[0032]

[0041] As used herein, system controller 126, also referred to as a process chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuitry 135. System controller 126 is used to control the process sequence (including the substrate bias method described herein) used to process substrate 103. CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control a process chamber and sub-processors associated with the process chamber. Memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). Support circuitry 135 is conventionally connected to CPU 133 and includes a cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data can be encoded and stored in memory 134 to instruct the processor within CPU 133. A software program (or computer instruction command) readable by CPU 133 within system controller 126 identifies which operations are executable by components within processing systems 10A and / or 10B.

[0033]

[0042] Typically, the program is readable by CPU 133 within system controller 126 and includes code. When this code is executed by the processor (CPU 133), it performs operations related to the plasma processing scheme described herein. The program may include instructions. These instructions are used to control various hardware and electrical components within processing systems 10A and / or 10B. Thereby, various process operations and various process sequences used to implement the methods described herein are executed. In one embodiment, the program includes instructions for performing one or more of the operations described hereinafter in connection with FIGS. 7 and 8A - 8C.

[0034]

[0043] The plasma control scheme 188 illustrated in FIGS. 1A-1B generally includes a plasma generator assembly 163, a first bias generator 196 for establishing a first PV waveform at the bias electrode 104, and a second bias generator 197 for establishing a second PV waveform at the edge control electrode 115. In some embodiments, the plasma generator assembly 163 supplies an RF signal to a support base 107 (e.g., a power electrode or a cathode), which can be used to generate (maintain and / or ignite) a plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency greater than 400 kHz, such as an RF frequency of about 1 MHz or greater, or about 2 MHz or greater, for example about 13.56 MHz or greater, about 27 MHz or greater, or about 40 MHz or greater.

[0035]

[0044] In some embodiments, the plasma control scheme 188 further includes an edge tuning circuit 170, which can be used to adjust one or more characteristics of the plasma 101 formed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the edge tuning circuit 170 can be used to adjust the density of a portion of the plasma 101 formed on the outer peripheral edge of the substrate 103 disposed on the substrate support assembly 136 relative to the density of a portion of the plasma 101 formed on the surface at the center of the substrate 103.

[0036]

[0045] Generally, as used herein, plasma density refers to the number of free electrons in the bulk plasma per unit volume (e.g., number of free electrons / cm 3 ), which in some embodiments is about 10 8 cm -3 ~ about 10 11 cm -3It can be within the range. The edge tuning circuit 170 enables the operation of one or more characteristics of the RF power used to maintain the plasma 101 in the region on the edge of the substrate support assembly 136 with respect to the RF power used to maintain the plasma 101 in the region on the central portion of the substrate support assembly 136. For example, the edge tuning circuit 170 can be used to adjust one or more of the voltage, current, and / or phase of the RF power at the edge of the substrate support assembly 136 with respect to the RF power within the central region 103A of the substrate support assembly 136.

[0037]

[0046] As will be described later, the edge tuning circuit 170 can be electrically connected to the edge control electrode 115 disposed on the substrate support assembly 136. In some embodiments, the RF signal used to ignite and / or maintain the plasma 101 is supplied from the plasma generator assembly 163 to the support base 107, and the support base 107 is capacitively coupled to the edge control electrode 115 through a layer of dielectric material disposed therebetween. The edge tuning circuit 170 can be used to adjust one or more characteristics of the RF power used to maintain the plasma in the region on the edge control electrode 115 by, for example, adjusting the voltage, current, and / or phase of the RF power at the edge control electrode 115 with respect to the RF power supplied to the support base 107.

[0038]

[0047] In some embodiments, the difference between the voltage, current, and / or phase of the RF power used to ignite and / or maintain the plasma in the region on the edge control electrode 115 and the bias electrode 104 is determined and / or monitored by measuring or determining the respective voltage, current, and / or phase of the RF power at the edge control electrode 115 and / or the bias electrode 104. In some embodiments, one or more characteristics of the RF power at the edge control electrode 115 and / or the bias electrode 104 are measured and / or determined using the signal detection module 187 described below.

[0039]

[0048] As described above, in some embodiments, the plasma generator assembly 163, which includes the RF generator 118 and the RF generator assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to the support base 107 of the substrate support assembly 136 based on control signals supplied from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107 disposed within the substrate support assembly 136 and proximate to the substrate support 105. The RF power supplied to the support base 107 is configured to ignite and sustain a processing plasma 101 of a processing gas disposed within the processing space 129.

[0040]

[0049] In some embodiments, the support base 107 is an RF electrode electrically connected to the RF generator 118 via the RF matching circuit 162 and the first filter assembly 161, and both the RF matching circuit 162 and the first filter assembly 161 are disposed within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator P1 within the PV waveform generator 150 and suppresses the flow of current to the RF matching circuit 162 and the RF generator 118.

[0041]

[0050] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and maintain the processing plasma 101 using an electric field generated by a processing gas disposed within the processing space 129 and RF power (RF signal) supplied to the support base 107 by the RF generator 118. The processing space 129 is in fluid communication with one or more dedicated vacuum pumps through a vacuum outlet 120. The one or more dedicated vacuum pumps maintain the processing space 129 at a near-atmospheric pressure state and exhaust the processing gas and / or other gases from the processing space 129. In some embodiments, the substrate support assembly 136 disposed within the processing space 129 is grounded and disposed on a support shaft 138 extending through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to supply RF power to a bias electrode 104 disposed within the substrate support 105 relative to the support base 107.

[0042]

[0051] In some embodiments, the edge tuning circuit 170 is used to control and / or adjust one or more characteristics of an RF waveform (e.g., the second RF waveform 502 illustrated in FIG. 5) established at the edge control electrode 115 relative to one or more characteristics of an RF waveform (e.g., the first RF waveform 501 shown in FIG. 5) established at the bias electrode 104. In some embodiments as shown in FIGS. 1A and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and ground. In other embodiments as shown in FIG. 1B and also shown in dashed lines in FIG. 2, the edge tuning circuit 170 can be electrically connected between the edge control electrode 115 and the plasma generator assembly 163, and thus electrically connected between the edge control electrode 115 and the support base 107.

[0043]

[0052] As briefly described above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a ground plate 112, which will be further described below. The support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is inserted between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and is disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0044]

[0053] In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein. The one or more cooling channels are in fluid communication and fluidly coupled to a coolant source (not shown) such as a refrigerant source or a water source having a relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater (not shown) such as a resistive heating element embedded in the dielectric material of the substrate support 105. Here, the support base 107 is formed of a corrosion-resistant heat-conductive material such as a corrosion-resistant metal (e.g., aluminum, an aluminum alloy, or stainless steel) and is connected to the substrate support by an adhesive or mechanical means.

[0045]

[0054] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material (a corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof, etc.). In the embodiments of the present specification, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region on the bias electrode 104 are determined and / or monitored by measuring the RF waveform (e.g., the first RF waveform 501 in FIG. 5) established at the bias electrode 104. Typically, the first RF waveform 501 is established by supplying an RF signal from the plasma generator assembly 163 to the substrate support 105, and the substrate support 105 is capacitively coupled to the bias electrode 104 through a dielectric material layer 105C (FIG. 1C) disposed therebetween.

[0046]

[0055] In one configuration, the bias electrode 104 is a chucking pole that fixes (i.e., chucks or electrostatically clamps) the substrate 103 to the substrate support surface 105A of the substrate support 105 and is used to bias the substrate 103 with respect to the processing plasma 101 using one or more of the pulse voltage bias schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0047]

[0056] In some embodiments, the bias electrode 104 is electrically connected to the clamping network 116. The clamping network 116 uses an electrical conductor such as a coaxial power supply line 106 (e.g., a coaxial cable) to supply a clamping voltage, such as a static DC voltage between approximately -5000V and approximately 5000V, to the bias electrode 104. As further discussed below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor. The bias compensation module blocking capacitor is also referred to herein as blocking capacitor C5. The blocking capacitor C5 is disposed between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0048]

[0057] Referring to FIGS. 1A and 1B, the substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is disposed below the edge ring 114, surrounds the bias electrode 104, and / or is disposed at a distance from the center of the bias electrode 104. Generally, in a processing chamber 100 configured to process a circuit board, the edge control electrode 115 is annular, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments as shown in FIG. 1A, the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 1A, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed at the same distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 as the bias electrode 104 from the edge ring 114. In some other embodiments as shown in FIG. 1B, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed on or within the region of the dielectric tube 110. The dielectric tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. The dielectric tube 110 can be made of various insulators such as aluminum oxide, aluminum nitride, quartz. In some embodiments, the dielectric tube 110 can include several parts made of the same material or different materials. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or connected to the edge ring 114 disposed adjacent to the substrate support 105.

[0049]

[0058] FIG. 1D is a close-up view of a portion of the substrate support assembly 136 shown in FIG. 1A. As shown, the edge ring 114 is disposed on the substrate support 105 and surrounds the substrate 103. The edge ring 114 protects the edge of the substrate support 105 and can be used, in some cases, to minimize electrical and / or thermal discontinuities formed at the substrate and substrate support edges. The edge ring 114 includes one or more inner surfaces 114A that face a portion of the substrate support 105 and the beveled outer edge of the substrate 103 disposed thereon. The inner surface 114A of the edge ring 114 is spaced apart from the substrate support 105 and the substrate 103 disposed thereon, defines one or more gaps 117A-B, and may include a ledge portion 114B that is disposed beneath the beveled substrate edge when the substrate 103 is disposed on the substrate support 105.

[0050]

[0059] In a typical etching process, ions impinge on the upper plasma-facing surface (e.g., surface 114C) of the edge ring 114 during processing, resulting in ion-induced erosion of the dielectric material forming the edge ring 114. Unfortunately, since the surfaces of the edge ring 114 that define the gap regions 117A-B are less exposed to the plasma 101, there is a tendency for processing etch by-products to accumulate, and these by-products can cause undesirable plasma arcs and / or particle movement between the edge ring 114 and the surface of the substrate 103 unless removed. Thus, in some embodiments, the bias and plasma control methods used to improve process non-uniformity at the substrate edge can also be used to preferentially clean the surfaces that define the edge pocket regions 117.

[0051]

[0060] As described below, the edge ring 114 can be energized using a pulsed voltage (PV) waveform to control the shape of the plasma sheath boundary 11 that extends across the edge pocket region 117 beyond the substrate edge and the edge ring 114. The shape of the plasma sheath boundary 11 affects the energy and directionality of the ions accelerated across the plasma sheath. For example, as described below and shown in FIGS. 9A-9C, the height difference between a portion (portion 11A) of the sheath boundary 11 formed on the substrate 103 and a portion (portion 11C) of the sheath boundary formed on the edge ring 114 causes the sheath boundary to bend at a portion (bend 11B) of the sheath boundary that spans the edge pocket region 117. The sheath thickness and the bending change of the sheath boundary respectively affect the ion energy and ion directionality of the ions impinging on the surface of the substrate 103 and the edge ring 114 disposed thereunder. Thus, by controlling the plasma sheath boundary 11 across the edge pocket region 117, adjustment of the ion energy and ion directionality on the surface of the substrate edge region 103B is permitted. This can be used to improve the uniformity of substrate processing. The improved control over the plasma sheath boundary 11 can also be used to perform the in-situ plasma cleaning method described herein to clean unwanted processing by-products from the surfaces 114A-B of the edge ring 114 as a target.

[0052]

[0061] The edge control electrode 115 is generally positioned such that when used with the edge tuning circuit 170 and / or when biased using the pulse bias scheme 140 (Figs. 1A - 1B), it can affect or modify a portion of the generated plasma 101 over or outside the outer peripheral edge of the substrate 103 due to its position relative to the substrate 103. In some embodiments, the bias generators 196, 197 can be used to control the shape of the sheath boundary 11 on the surface of the substrate support assembly 136 facing the plasma. For example, due to repeated ion collisions, the edge ring 114 typically undergoes plasma-based erosion, and the thickness of the edge ring decreases over its service life. If the thickness of the plasma sheath formed on the edge ring 114 remained the same, the wear of the edge ring 114 would ultimately cause the bending of the plasma sheath boundary and result in non-uniform processing results at the substrate edge. Thus, in some embodiments, one or more characteristics of the pulsed voltage (PV) waveform established by the bias electrode 104 and / or the edge control electrode 115 can be adjusted to compensate for changes in the height of the edge ring 114 over its service life to maintain a substantially uniform sheath boundary 11 across the edge of the substrate 103.

[0053]

[0062] In some embodiments, an edge tuning circuit 170 electrically connected to the edge control electrode 115 can be used to manipulate one or more characteristics of the RF power used to ignite and / or sustain the plasma within the processing region 129A above the edge control electrode 115. For example, in some embodiments, the edge tuning circuit 170 can be used to adjust and / or manipulate one or more of the voltage, current, and / or phase of the RF power used to ignite and / or sustain the plasma 101 within the processing region disposed between the edge control electrode 115 and the chamber lid 123.

[0054]

[0063] In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region on the edge control electrode 115 are determined and / or monitored by measuring one or more differences between a second RF waveform 502 and a first RF waveform 501 respectively established at the edge control electrode 115 and the bias electrode 104. In some embodiments, the difference in one or more characteristics between the second RF waveform 502 and the first RF waveform 501 can be manipulated by using the edge tuning circuit 170 to adjust the plasma density in the region on the outer circumferential edge of the substrate 103 and / or the region spanning the edge pocket region 117.

[0055]

[0064] In some embodiments, by utilizing the difference in characteristics between the second RF waveform 502 and the first RF waveform 501, plasma can be preferentially formed between the edge ring 114 and the edge of the substrate 103, and the plasma can be effectively concentrated in the edge pocket region 117 to remove undesirable processing by-products from the surface therein. Thus, the edge tuning circuit 170 is advantageously used to control the generation of active species in the bulk plasma, thereby enabling fine control of the flux of ions and / or radicals at the edge (edge region 103B) of the substrate 103 relative to the central region 103A of the substrate 103, and / or the density of the plasma in the edge pocket region 117.

[0056]

[0065] The edge control electrode 115 can be energized using a PV waveform generator 150 different from the PV waveform generator 150 used to energize the bias electrode 104. In some embodiments, the edge control electrode 115 can be energized by using the PV waveform generator 150 which is also used to energize the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, the first PV waveform generator 150 of the first bias generator 196 is configured to energize the bias electrode 104, and the second PV waveform generator 150 of the bias generator 197 is configured to energize the edge control electrode 115.

[0057]

[0066] In some embodiments, a signal detection module 187 communicatively coupled to system controller 126 is used to measure and / or determine one or more characteristics of the generated RF power. The signal detection module 187 is generally configured to receive electrical signals from various components within processing systems 10A and 10B, such as electrical signal traces (not shown) that are electrically connected to node N. The signal detection module 187 can include a plurality of input channels 172 each configured to receive an electrical signal from a corresponding electrical signal trace, and a data acquisition module 169. The received electrical signals can include, but are not limited to, an RF signal supplied to support base 107, an RF waveform established on one or both of bias electrode 104 and edge control electrode 115, a pulse voltage (PV) waveform established on one or both of bias electrode 104 and edge control electrode 115, and one or more characteristics of a checking voltage supplied to one or both of bias electrode 104 and edge control electrode 115.

[0058]

[0067] In some embodiments, data acquisition module 169 is configured to generate control signals used to automatically control one or more characteristics of the RF signal, RF waveform, PV waveform, and / or checking voltage during substrate processing. In some embodiments, a desired change in one or more characteristics is communicated by system controller 126 to signal detection module 187, and data acquisition module 169 can be used to implement the desired change.

[0059]

[0068] Referring to FIGS. 1A and 1B, a second bias generator 197 includes a clamping network 116 such that the bias applied to edge control electrode 115 can be configured similar to the bias applied to bias electrode 104 by clamping network 116 connected within first bias generator 196.

[0060]

[0069] In some embodiments, the processing chamber 100 further includes a dielectric tube 110 or a collar that at least partially surrounds a portion of the substrate support assembly 136 as a dielectric barrier between the RF hot substrate support assembly 136 and the ground liner 108, and also prevents the substrate support 105 and / or the support base 107 from contacting corrosive process gases or plasmas, cleaning gases or plasmas, or their by-products. Typically, the liner 108 is externally connected to the dielectric tube 110, the insulator plate 111, and the ground plate 112. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma from being generated in the space below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0061] Configuration of the substrate support assembly

[0070] FIG. 1C is a close-up view of a portion of the substrate support assembly 136 shown in FIG. 1A and includes a simplified electrical schematic of the electrical characteristics of various structural elements within one or more embodiments of the substrate support assembly 136. The simplified electrical schematic shown in FIG. 1C is equally applicable to the corresponding structural elements of the substrate support assembly 136 depicted in FIG. 1B. Here, the substrate support assembly 136 is configured as an electrostatic chuck (ESC) and can be either a Coulombic type ESC or a Johnsen-Rahbek type ESC. Simplified equivalent circuit models 191 of the Coulombic type ESC and the Johnsen-Rahbek type ESC are shown in FIGS. 3D and 3E, respectively, and will be described later. Generally, in any ESC configuration of the substrate support assembly 136, the substrate 103 is fixed to the substrate support 105 by applying a potential between the substrate 103 and the bias electrode 104, resulting in an electrostatic attraction force therebetween. In one embodiment, the bias electrode 104 is also used to facilitate the bias method of the pulse voltage (PV) waveform described herein.

[0062]

[0071] The substrate support 105 is formed of a dielectric material and provides a substrate support surface 105A that includes a bias electrode 104 embedded in the dielectric material. The bias electrode 104 is spaced apart from the substrate support surface 105A, and thus from the substrate 103, by a first dielectric material layer 105B and from the support base 107 by a second dielectric material layer 105C.

[0063]

[0072] In some embodiments, the ESC configuration can be used to secure the substrate 103 to the substrate support 105 in a relatively low-pressure (e.g., ultra-high vacuum) processing environment. In some embodiments, it may be desirable to heat and / or cool the substrate 103 during processing to maintain the substrate at a desired processing temperature. In these embodiments, the substrate support assembly 136 can be configured to maintain the substrate 103 at the desired temperature by heating or cooling the substrate support 105, and thus the substrate 103 disposed thereon. In many of those embodiments, the substrate support surface 105A is patterned to have a raised portion (e.g., mesa) that contacts the substrate 103 and a recess that defines a backside space 105D with the substrate 103. During substrate processing, an inert gas such as helium can be supplied to the backside space 105D using a gas source 173 fluidly connected to the substrate support assembly 136 to enhance heat transfer between the substrate support surface 105A and the substrate 103 disposed thereon. In some embodiments, the gas source 173 is used to supply an inert gas to a region disposed between the edge ring 114 and the surface of the substrate support assembly 136 disposed thereunder.

[0064]

[0073] The bias electrode 104 is electrically connected to a DC power supply 155 (described above in FIGS. 1A - 1B), and this DC power supply 155 is configured to apply a potential between the substrate 103 and the bias electrode 104, and as a result, generate an electrostatic attraction force (chucking force) therebetween. The substrate support assembly 136 can be configured as either a Coulomb - type ESC or a Johnsen - Rahbek - type ESC. The Johnsen - Rahbek - type ESC can provide a higher chucking force and use a lower chucking voltage compared to the Coulomb - type ESC. In the Coulomb - type ESC, the dielectric material selected for the first dielectric material layer 105B will generally have a higher electrical resistance than the dielectric material selected for the Johnsen - Rahbek - type ESC. As a result, there is a difference in the simplified functional equivalent circuit models 191 shown in FIGS. 3D and 3E respectively.

[0065]

[0074] In the simplest case (e.g., the circuit model 191 of the Coulomb - type ESC shown in FIG. 3D), the first dielectric layer 105B is formed of a dielectric material (e.g., having an infinite resistance R JR assumed to function as an insulator). Thus, the functionally equivalent circuit model 191 includes a direct capacitance C1 between the bias electrode 104 and the substrate 103 through the first dielectric layer 105B. In some embodiments of the Coulomb - type ESC, the dielectric material and thickness T DL1 of the first dielectric material layer 105B are selected such that the capacitance C1 is between about 5 nF and about 100 nF, for example, between about 7 nF and about 20 nF. For example, the dielectric material layer 105B is formed of a ceramic material (e.g., aluminum oxide (Al2O3), etc.) and can have a thickness T DL1 between about 0.1 mm and about 1 mm, for example, between about 0.1 mm and about 0.5 mm, for example, about 0.3 mm.

[0066]

[0075] In a more complex case, as shown in the circuit model 191 of the Johnsen - Rahbek - type ESC shown in FIG. 3E, the circuit model 191 includes a dielectric material resistance R JR and a gap capacitance C JRIt includes a capacitor C1 connected in parallel. Typically, in a Johnson-Larkin type ESC, the dielectric material layer 105B is considered "leaky" in the sense that it is not a perfect insulator and has some conductivity. For example, the dielectric material can be doped aluminum nitride (AlN) having a dielectric constant (ε) of about 9. Similar to the circuit model 191 of the Coulomb type ESC shown in FIG. 3D, a direct capacitor C1 exists between the bias electrode 104 and the substrate 103 through the dielectric material layer 105B and the backside space 105D filled with helium. The volume resistance of the dielectric layer in the Johnson-Larkin type ESC is about 10 12 ohm·cm (Ω·cm) or less, or about 10 10 Ω·cm or less, further in the range between 10 8 Ω·cm and 10 12 Ω·cm. Therefore, the dielectric material layer 105B can have a dielectric material resistance R 6 in the range between 10 11 Ω and 10 JR Ω. In the model 191 of FIG. 3E, a gap capacitance C JR is used to account for the gas-containing backside space 105D between the substrate 103 and the substrate support surface 105A. The gap capacitance C JR is expected to have a capacitance slightly larger than that of the capacitor C1.

[0067]

[0076] Returning to FIG. 1C, the electrical schematic of the circuit formed within the substrate support assembly 136 includes a support base dielectric layer capacitance C2, which represents the capacitance of the second dielectric material layer 105C. In some embodiments, the thickness of a portion of the second dielectric material layer 105C is greater than the thickness of the first dielectric material layer 105B. In some embodiments, the dielectric material used to form the dielectric layers on both sides of the bias electrode is the same material and forms the structural body of the substrate support 105. In one example, the thickness of the second dielectric material layer 105C (e.g., Al2O3 or AlN) measured in the direction extending between the support base 107 and the bias electrode 104 is greater than 1 mm, such as having a thickness between about 1.5 mm and about 100 mm. The support base dielectric layer capacitance C2 typically has a capacitance between about 0.5 nanofarads (nF) and about 10 nF.

[0068]

[0077] As shown in FIG. 1C, the electrical schematic of the circuit formed within the substrate support assembly 136 also includes a support base resistance R P , an insulator plate capacitance C3, and a ground plate resistance R G that is connected to ground at one end. Since the support base 107 and the ground plate 112 are typically formed of a metallic material, the support base resistance R P and the ground plate resistance R G are very low, such as less than a few milliohms. The insulator plate capacitance C3 represents the capacitance of the dielectric layer located between the bottom surface of the support base 107 and the top surface of the ground plate 112. In one example, the insulator plate capacitance C3 has a capacitance between about 0.1 nF and about 1 nF.

[0069] Bias and Edge Control Scheme

[0078] FIG. 2 is a simplified schematic diagram of a bias and edge control scheme that can be used with one or both of the processing systems 10A-10B shown in FIGS. 1A and 1B. As shown in FIG. 2, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform, respectively, to one or more electrodes disposed within the processing space 129 of the processing chamber 100. In one embodiment, the RF generator 118 and the PV waveform generator 150 are configured to simultaneously supply an RF waveform and a pulsed voltage waveform to one or more electrodes disposed within the substrate support assembly 136.

[0070]

[0079] As described above, the edge tuning circuit 170 is generally configured to control the uniformity of the plasma formed between the chamber lid 123 and the substrate support assembly 136, for example, by controlling the plasma density (i.e., the free electron density in the bulk plasma) across the outer periphery of the substrate 103. In some embodiments, as shown in FIGS. 1A and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 (edge bias electrode) and ground. In other embodiments, as shown by the dashed lines in FIGS. 1B and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and the plasma generator assembly 163, for example, between the edge control electrode 115 and the RF generator 118.

[0071]

[0080] In some embodiments, the edge tuning circuit 170 may be configured as a resonant circuit including an inductor and a capacitor (e.g., an LC circuit) that can be used to adjust the voltage, current, and / or phase of the RF power used to maintain plasma in the region on the edge control electrode. Exemplary electrical circuits 170a, 170b, 170c that can be used as the edge tuning circuit 170 in any one of the embodiments described herein are illustrated in FIGS. 3A-3C. As shown, each of the edge tuning circuits 170a, 170b is electrically connected between the power supply line 158 and ground (i.e., between the edge control electrode 115 and ground). However, it is contemplated that each of the exemplary edge tuning circuits 170a, 170b may also be electrically connected between the power supply line 158 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF generator 118), as shown in FIG. 1B. In some other embodiments, the edge tuning circuit 170 can be electrically connected to the power supply line 158, the plasma generator assembly 163, and ground simultaneously, as shown for the exemplary edge tuning circuit 170c in FIG. 3C.

[0072]

[0081] In one embodiment shown in FIG. 3A, the edge tuning circuit 170a includes an inductor L2 and a variable capacitor C7 arranged in parallel (i.e., a parallel LC resonant circuit). In another embodiment shown in FIG. 3B, the edge tuning circuit 170b includes an inductor L2 and a variable capacitor C7 arranged in series (i.e., a series LC resonant circuit). In another embodiment shown in FIG. 3C, the edge tuning circuit 170c includes an inductor L2 and a variable capacitor C8 arranged in series between the edge control electrode 115 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF generator 118) (i.e., a series LC resonant circuit), and a second variable capacitor C7 connected to a node arranged between the inductor L2 and the variable capacitor C8 in the power supply line 158 and ground.

[0073]

[0082] In some embodiments, one or both of the variable capacitors C7, C8 are adjustable from at least about 50 pF to at least about 200 pF, for example from at least about 20 pF to at least about 250 pF.

[0074]

[0083] The type of LC resonant circuit selected for the edge tuning circuit 170, e.g., parallel, series, or other configuration, may depend on the mechanical dimensions of the substrate support assembly 136 and the resulting electrical connections between conductive components or electrodes such as the edge ring 114, edge control electrode 115, support base 107, bias electrode 104, substrate 103, and ground plate 112.

[0075]

[0084] In some embodiments, the type of LC resonant circuit is selected based on the desired ability to control the plasma density distribution that can be achieved by adjusting one or more parameters of the LC resonant circuit such that one or more characteristics of the second RF waveform 502 (Figs. 5A - 5B) established by the edge control electrode 115 can be adjusted relative to one or more characteristics of the first RF waveform 501 established by the bias electrode 104. Simulation results of various control characteristics achievable for an exemplary edge tuning circuit 170 are described below with reference to Figs. 6A - 6D.

[0076]

[0085] Returning to Fig. 2, as a non - limiting example, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform to the support base 107 and the bias electrode 104 disposed in the substrate support assembly 136, respectively. In another example, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to supply an RF waveform, a first pulsed voltage waveform, and a second pulsed voltage waveform to the support base 107, the bias electrode 104, and the edge control electrode 115 disposed in the substrate support assembly 136, respectively.

[0077]

[0086] As shown in FIG. 2, the RF generator 118 is configured to supply an RF signal, a sinusoidal RF waveform, here sinusoidal RF waveforms 501, 502 (FIGS. 5A-5B), through an RF (plasma) generator assembly 160 including an RF matching circuit 162 and a first filter assembly 161, to one or more electrodes disposed within the chamber body 113. Further, each of the PV waveform generators 150 is configured to supply a PV waveform, typically a series of voltage pulses (e.g., nanosecond voltage pulses), to one or more electrodes disposed within the chamber body 113 by establishing the PV waveform on the bias electrode 104 through a second filter assembly 151. Components within the clamping network 116 can optionally be disposed between each PV waveform generator 150 and the second filter assembly 151.

[0078]

[0087] During processing, a PV waveform is supplied to the bias electrode 104 by the PV waveform generator 150 of the first bias generator 196, and a PV waveform is supplied to the edge control electrode 115 by the PV waveform generator 150 of the second bias generator 197. The PV waveform is supplied to a load (e.g., composite load 130 shown in FIGS. 3D-3E) disposed within the processing chamber 100. The PV waveform generators 150 are connected to the bias electrode 104 and the edge control electrode 115 through respective power supply lines 157 and 158. Control of the supply of the PV waveform from each of the PV waveform generators 150 is performed using signals supplied from the system controller 126.

[0079]

[0088] In one embodiment, the PV waveform generator 150 is configured to output a periodic voltage function at time intervals of a predetermined length, for example, using a signal from a transistor-transistor logic (TTL) source (not shown). The periodic voltage function generated by the transistor-transistor logic (TTL) source can be two-states DC pulses between a predetermined negative or positive voltage and zero. In one embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant negative voltage across its output (i.e., with respect to ground) while time intervals of a predetermined length are periodically repeated by repeatedly opening and closing one or more switches at a predetermined rate. In one example, during the first phase of the pulse interval, a first switch is used to connect the high voltage power supply to the bias electrode 104, and during the second phase of the pulse interval, a second switch is used to connect the bias electrode 104 to ground. In another embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant positive voltage across its output (i.e., with respect to ground) while time intervals of a predetermined length are periodically repeated by repeatedly opening and closing its internal switches (not shown) at a predetermined rate.

[0080]

[0089] In one configuration, during the first phase of the pulse interval, a first switch is used to connect the bias electrode 104 to ground, and during the second phase of the pulse interval, a second switch is used to connect the high voltage power supply to the bias electrode 104. In another configuration, during the first phase of the pulse interval, the bias electrode 104 is disconnected from the high voltage power supply and the first switch is placed in the open state such that the bias electrode 104 is coupled to ground through an impedance network (e.g., an inductor and a resistor connected in series). Next, during the second phase of the pulse interval, the first switch is placed in the closed state to connect the high voltage supply to the bias electrode 104, while the bias electrode 104 remains connected to ground through the impedance network.

[0081]

[0090] The PV waveform generator 150 may include, but is not limited to, a PV generator and one or more electrical components such as a high-repetition-rate switch (not shown), a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown) configured to supply a PV waveform to an output. The actual PV waveform generator 150, which can be configured as a nanosecond pulse generator, may include any number of internal components.

[0082]

[0091] The power supply line 157 electrically connects the output of the PV waveform generator 150 of the first bias generator 196 to the optional filter assembly 151 and the bias electrode 104. In the following discussion, the power supply line 157 of the first bias generator 196 used to connect the PV waveform generator 150 to the bias electrode 104 will be mainly described. However, the power supply line 158 of the second bias generator 197 that connects the PV waveform generator 150 to the edge control electrode 115 may also include the same or similar components. One or more electrical conductors in various portions of the power supply line 157 may include the following: (a) one or a combination of coaxial cables such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hook-up wire, (c) a bare wire, (d) a metal bar, (e) an electrical connector, or (f) any combination of the electrical elements of (a) to (e). The optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power supply line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118 and suppresses the flow of current to the PV waveform generator 150.

[0083]

[0092] In some embodiments, as shown in FIGS. 1A - 1B, the PV waveform generator 150 of the first bias generator 196 supplies the generated pulse voltage (PV) waveform to the bias electrode 104, and thus to the composite load 130 (FIGS. 3D - 3E), by supplying it through the blocking capacitor C5, the filter assembly 151, the power supply line 157, and the capacitor C1 (FIG. 1C), so as to supply a pulse voltage (PV) waveform signal. In some embodiments, the plasma control scheme 188 may further include a blocking resistor (not shown) disposed within a component that connects the clamping network 116 to a point within the power supply line 157. The main function of the blocking capacitor C5 is to protect the PV waveform generator 150 from the DC voltage generated by the DC power supply 155. This DC voltage drops across the blocking capacitor C5 and does not disturb the output of the PV waveform generator 150. The purpose of the blocking resistor of the clamping network 116 is to block the pulse voltage generated by the PV waveform generator 150 to such an extent as to minimize the current induced in the DC power supply 155.

[0084] Waveform example

[0093] FIG. 4 shows an example of the PV waveform 402 established on the substrate 103 by the PV waveform 401 established at the bias electrode 104. Here, the PV waveform 401 is established at the bias electrode 104 and / or the edge control electrode 115 by using the PV waveform generators 150 within the respective bias generators 196, 197 and the DC voltage source 155 of the corresponding clamping network 116.

[0085]

[0094] Generally, the output of the PV waveform generator 150, which can be controlled by the settings of the plasma processing recipe stored in the memory of the controller 126, forms a PV waveform 401 that includes a peak - to - peak voltage VPP, also referred to as the pulse voltage level Vpp.

[0086]

[0095] Waveform period T PThe PV waveform 402 having [the relevant characteristics] is the waveform seen by the substrate 103 for the supply of the PV waveform 401 to the bias electrode 104, and includes a sheath collapse and recharge phase 450 (or, for simplicity of discussion, the sheath collapse phase 450) extending between point 420 and point 421, a sheath formation phase 451 extending between point 421 and point 422, and an ion current phase 452 extending between point 422 and the starting point of point 420 of the next continuously established pulsed voltage waveform. The sheath collapse phase 450 generally includes a period during which the capacitance of the sheath is discharged and the substrate potential is brought to the level of the local plasma potential 433.

[0087]

[0096] Depending on the desired plasma processing conditions, in order to obtain desired plasma processing results on the substrate, it may be desirable to control and set at least PV waveform characteristics such as the PV waveform frequency (1 / T P ), the pulse voltage level Vpp, the pulse voltage on-time, and / or other parameters of the PV waveform 401. In one embodiment, the pulse voltage (PV) on-time is defined as the ratio of the ion current period (e.g., the time between point 422 and the next point 420 in FIG. 4) to the waveform period Tp, and is greater than 50%, or greater than 70%, for example, between 80% and 95%. In some embodiments, the PV waveform generator 150 is configured to supply a constant voltage during the ion current phase 452, as shown in FIG. 4. In some embodiments, the PV waveform generator 150 is configured to provide a shaped pulsed voltage waveform (not shown) with a non-zero slope during the ion current phase 452 by using one or more internal switches and a DC power supply. In some embodiments, the PV waveform generator 150 is configured to supply a constant positive voltage during only one of the phases of the voltage pulse, such as during the sheath collapse phase 450 (not shown). Generally, the DC offset ΔV seen in each PV waveform of the bias electrode depends on the bias applied by the DC power supply 155 of the clamping network 116 and the various characteristics of the configuration of the PV waveform generator 150 used to establish the PV waveform 401.

[0088]

[0097] In some embodiments, during the ion current phase 452, since the ion current (Ii) deposits a positive charge on the substrate surface, the voltage of the substrate surface will increase over time as seen by the positive slope of the straight line between point 422 and point 420. The increasing voltage over time at the substrate surface will reduce the sheath voltage and result in a broadening of the ion energy distribution. Therefore, it is desirable to control and set at least the PV waveform frequency (1 / T PD ), where T PD is the PV waveform period, to minimize the effects of the sheath voltage reduction and the broadening of the ion energy distribution.

[0089]

[0098] FIGS. 5A - 5B show a first RF waveform 501 established by the bias electrode 104 and a second RF waveform 502 established by the edge control electrode 115, due to capacitive coupling of the RF signal supplied to the support base 107 by the RF generator 118 within the plasma generator assembly 163. The waveform characteristics of the first RF waveform 501 and the second RF waveform 502 are controlled by using the configuration of an edge tuning circuit 170, such as one of the configurations illustrated in FIGS. 3A (parallel LC resonance circuit), 3B (series resonance circuit), and 3C (more complex resonance circuit). The exemplary waveforms shown in FIGS. 5A - 5B and the simulation results shown in FIGS. 6A - 6D below are not intended to limit the scope of the present disclosure provided herein, but are provided to simplify the discussion.

[0090]

[0099] Generally, since the RF signal supplied to the support base 107 has a relatively high frequency, the first RF waveform 501 and the second RF waveform 502 have corresponding high frequencies of about 1 MHz or more, for example, between about 30 MHz and about 60 MHz (1 / T RF) has. The edge synchronization circuit 170 described in various embodiments disclosed herein can be used to adjust one or more characteristics of a second RF waveform 502 established by an edge control electrode 115 with respect to one or more characteristics of a first RF waveform 501 established by a bias electrode 104. In some embodiments, one or more relative characteristics are the RF waveform amplitude ratio (e.g., voltage amplitude ratio V RF2 / V RF1 ) between the second RF waveform 502 and the first RF waveform 501, the RF current amplitude ratio between the second RF waveform 502 and the first RF waveform 501 (e.g., the current amplitude ratio is not shown), the phase difference (ΔΦ) between the second RF waveform 502 and the first RF waveform 501, and / or the RF supply power ratio between the second RF waveform 502 and the first RF waveform 501 (e.g., the supply power ratio is not shown).

[0091]

[0100] One or more characteristics of the second RF waveform 502 with respect to the first RF waveform 501 can be determined and / or monitored by measuring the respective voltage, current, phase, and / or power of the RF waveforms established at the edge control electrode 115 and the bias electrode 104. The measured characteristics of the second RF waveform 502 and the first RF waveform 501 respectively correspond to the characteristics of the bulk plasma in the portion formed above the edge control electrode 115 and the bias electrode 104, such as the plasma density. The difference determined between the second RF waveform 502 and the first RF waveform 501 can be used to monitor and control the difference in the electron density of the portion of the bulk plasma formed on the edge ring 114 and the electron density of the portion of the bulk plasma formed on the central portion of the substrate 103. The uniformity and / or distribution of the plasma density can be controlled and / or adjusted to achieve a desired processing result by using the edge synchronization circuit 170, such as by using the system controller 126 to adjust the variable capacitor C7.

[0092]

[0101] Non-limiting simulation results of the edge tuning circuit 170 shown in FIGS. 3A and 3B are shown in FIGS. 6A-6B, and simulation results of the edge tuning circuit 170 combining the series and parallel configurations shown in FIG. 3C are shown in FIGS. 6C-6D. In FIGS. 6A and 6C, the simulation results show the effect of varying the capacitance (e.g., variable capacitor C of the configuration of each edge tuning circuit 170) over a range of about 20 pF to about 250 pF (e.g., adjusting it), on the voltage amplitude ratio (e.g., V 7を / V RF2 / V RF1 ) between the second RF waveform 502 and the first RF waveform 501, by providing an example of an LC circuit tuning curve. In FIGS. 6B and 6D, the simulation results show the effect of varying the capacitance of C7 on the phase difference (e.g., Φ RF2 -Φ RF1 ) between the second RF waveform 502 and the first RF waveform 501, by providing an example of an LC circuit adjustment curve.

[0093]

[0102] As shown in FIG. 6A, the variable capacitor C7 of the edge tuning circuit 170 (configuration of FIG. 3A) having a value of about 170 pF has a corresponding voltage amplitude ratio (V RF2 / V RF1 ) of about 1.5. As shown in FIG. 6B, the phase difference corresponding to the 170 pF capacitance of the edge tuning circuit 170 having the same configuration as FIG. 6A is relatively small, e.g., less than 5 degrees. Therefore, as shown in FIG. 6A, amplification of the second RF waveform 502 with respect to the first RF waveform 501 and a small phase difference (ΔΦ) therebetween occur.

[0094]

[0103] In FIGS. 6C-6D, the variable capacitor C7 of the edge tuning circuit 170 (configuration of FIG. 3C) can be set to a value of about 25 pF. As a result, the voltage amplitude ratio (V RF2 / V RF1 ) is equal to about 0.5 (FIG. 6C), and the phase difference (ΔΦ) is about zero as shown in FIG. 6D.

[0095]

[0104] As shown in FIG. 6A, simulation results based on the configuration of the edge tuning circuit 170 of FIG. 3A (e.g., a parallel LC resonance circuit) show resonance peaks at approximately 100 pF and approximately 120 pF. In FIG. 6D, the simulation results of the edge tuning circuit 170 (the configuration of FIG. 3C) show resonance phase transitions at 60 pF and 250 pF. In some embodiments, it may be desirable to operate each edge tuning circuit 170 on either side of resonance during the period in which the RF plasma is maintained. In some embodiments, the edge tuning circuit 170 may be configured to allow switching operation of the edge tuning circuit 170 on both sides of a resonance peak (between either side of a resonance peak) without crossing the resonance region, for example, by using a variable capacitor that combines parallel and series LC circuits. As described above, the simulation results shown in FIGS. 6A-6D are not intended to be limiting. This is because other configurations of the edge tuning circuit 170 may be used to provide other desired operating ranges for amplifying, reducing, and / or equalizing the voltage amplitude ratio (V RF2 / V RF1 ) and / or the current amplitude ratio and / or the phase difference between the second RF waveform 502 and the first RF waveform 501.

[0096]

[0105] In some embodiments, it may be desirable to select a tuning circuit configuration and / or a variable capacitance C7 that creates a phase difference between each RF waveform, thereby amplifying the electric field between the edge control electrode 115 and the bias electrode 104. The amplified electric field results in a corresponding increase in plasma density in a portion of the plasma 101 formed on the substrate support assembly 136 at a certain distance between the two electrodes. In some embodiments, it may be desirable to select a tuning circuit configuration and / or a variable capacitance C7 that does not create a phase difference between the RF waveforms established at each electrode such that the plasma density remains substantially uniform across the region extending to the edge of the substrate 103.

[0097]

[0106] Advantageously, the edge tuning circuit 170 can be configured to provide a wide range of desired plasma processing conditions to control and / or adjust the plasma density distribution at different points between the center and the edge of the substrate 103. The characteristics of the edge tuning circuit 170, and thus the position of the system on the tuning curve (Figs. 6A - 6D), can be controlled by adjusting one or more variable capacitors C7 using the system controller 126. By the controlled adjustment of the characteristics of the edge tuning circuit by the system controller 126, it will be possible to relatively easily change the plasma processing conditions within a single substrate plasma process, between successive substrate plasma processes, and / or for different types of substrates, without the need to manually change hardware - related configurations. In some embodiments, one or both of the bias generators 196, 197, the edge tuning circuit 170, or combinations thereof can be used to preferentially clean the surface of the substrate support assembly 136 within the edge pocket region 117 during an in - situ plasma cleaning method as described below in connection with Figs. 7A - 7C and Figs. 8A - 8C.

[0098]

[0107] In some embodiments, the edge tuning circuit 170 is automatically adjusted to maintain desired processing conditions, such as taking into account plasma uniformity drift due to changes over time in the shape dimensions and / or materials of various components of the processing chamber 100. For example, the method can be used to automatically adjust the tuning circuit, such as by changing the capacitance C7, taking into account changes in the thickness of the edge ring 114 that can be caused by erosion of the dielectric material from the edge ring 114 due to ion collisions. For example, in some embodiments, the system controller 126 uses the signal detection module 187 to detect signals of one or more electrical parameters at corresponding nodes N of the processing systems 10A, 10B, and compares the characteristics of the detected signals with one or more control limits to determine whether the processing systems 10A, 10B are operating within the desired processing conditions. If the electrical signal characteristics are outside the control limits, one or more components of the edge tuning circuit 170 can be configured to be adjusted. Some embodiments include automatically adjusting the edge tuning circuit, such as by adjusting the capacitance C7, to maintain a desired RF voltage amplitude ratio, RF current amplitude ratio, and / or RF phase difference between different RF waveforms at the edge control electrode 115 and the bias electrode 104.

[0099]

[0108] In some embodiments, the system controller 126 compares one or more processing conditions and / or RF waveforms with a predetermined limit, such as a control limit value, and changes one or more set points, such as the capacitance C7 of the edge tuning circuit 170, based on an algorithm or look-up table stored in the memory 134 of the system controller 126, to automatically adjust the edge tuning circuit 170 based on the desired processing conditions and / or desired characteristics between the RF waveforms of the edge control electrode 115 and the bias electrode 104.

[0100]

[0109] In some embodiments, the edge synchronization circuit 170 can be manually adjusted and / or controlled by adjusting one or more components of the edge synchronization circuit 170 to a desired set point and / or within a desired control limit. The desired set point and / or control list is selected by the user and stored in the instructions used to control the processing systems 10A, 10B. For example, the capacitance C7 of the edge synchronization circuit 170 can be determined by the user and controlled to a desired capacitance stored in the memory of the system controller 126.

[0101]

[0110] Generally, the pulsed voltage (PV) waveform established on electrodes 104 and 115, such as any of the negative pulse waveform 401, the shaped pulse waveform 441, or the positive pulse waveform 431, is a periodic series of pulsed voltage (PV) waveforms repeated with a period T on top of a voltage offset (ΔV). PD In one example, the period T of the PV waveform PD can be between about 1 μs and about 5 μs, for example about 2.5 μs, between about 200 kHz and about 1 MHz, or about 400 kHz, for example about 1 MHz or less, or about 500 kHz or less.

[0102]

[0111] As described above, in some embodiments, the processing chamber 100 includes at least one or more RF generators 118 and their associated first filter assembly 161, and one or more PV generators 314 and their associated second filter assembly 151, which together are configured to supply a desired waveform to one or more electrodes disposed within the substrate support assembly 136. The software instructions stored in the memory of the system controller 126 are configured to generate an RF waveform configured to establish, maintain, and control one or more aspects of the plasma formed within the processing chamber. One or more aspects of the plasma to be controlled can include, but are not limited to, plasma density, plasma chemistry, and ion energy in the plasma formed within the processing space 129.

[0103] Examples of processing methods

[0112] Figures 7A - 7C are process flow diagrams showing respective methods that can be used to clean processing by - products from the surface of the substrate support assembly. Figures 8A - 8C are proximity views of the substrate support assembly 136 used to illustrate aspects of the methods described in Figures 7A - 7C. In Figures 8A - 8C, a portion of the substrate support assembly 136 is configured as shown in Figure 1B, and the edge control electrode 115 is disposed within or on the material of the dielectric tube 110 surrounding the substrate support 105. However, the methods described below are contemplated to be used with any one or combination of the substrate support assembly configurations described herein, such as when the edge control electrode 115 is disposed within the dielectric material of the substrate support 105 (Figures 1A, 1D), disposed within the edge ring 114, and / or connected to the edge ring 114.

[0104]

[0113] FIG. 7A is a process flow diagram showing a method 700 for preferentially cleaning the surface defining the edge pocket region 117 of the substrate support assembly 136 according to one embodiment. FIGS. 1A-1D and 8A are referred to in the following description to explain aspects of method 700, but are not intended to be limiting. This is because it is contemplated that method 700 can be implemented in other processing systems configured to bias the substrate and edge ring separately. Generally, method 700 uses in-situ plasma (the plasma formed within the processing chamber 100) to remove processing by-products accumulated from the edge ring 114 and / or portions of the substrate support surface 105A adjacent thereto. Method 700 is used to manipulate the shape of the plasma sheath boundary 11 (FIG. 8A) formed on the substrate support assembly 136 by increasing or decreasing the voltage between the edge ring 114 and the plasma relative to the voltage between the substrate support surface 105A and the plasma 101. The voltage difference creates a corresponding difference in ion energy at surfaces 114A-C and 105A, which in some embodiments results in a bend in the plasma sheath boundary that can be advantageously used to preferentially direct plasma-generated ions towards desired portions of the substrate support assembly 136. For example, as shown in FIG. 8A, due to the height difference between a portion 11A of the sheath boundary 11 formed on the substrate support surface 105A and a portion 11C of the sheath boundary 11 formed on the edge ring 114, the sheath boundary bends at the portion (bend 11B) spanning the edge pocket region 117.

[0105]

[0114] In operation 702, method 700 includes generating a first plasma in a processing region of a processing chamber, where processing chamber 100 can include any one or combination of the features illustrated in FIGS. 1A - 1D. Here, processing region 129A is defined by chamber lid 123 and substrate support assembly 136. Referring now to FIG. 8A, substrate support assembly 136 generally includes a first portion of dielectric material 105B that forms substrate support surface 105A, and an edge ring 114 that surrounds substrate 103 (shown in dashed lines) when substrate 103 is disposed on substrate support surface 105A. One or more edge pocket surfaces 114A, B of edge ring 114 and the outer peripheral edge of the first portion 105B of the dielectric material define an edge pocket region 117 where edge pocket surfaces 114A, B are disposed inside chamber lid facing surface 114C.

[0106]

[0115] In some embodiments, substrate support assembly 136 further includes a bias electrode 104 spaced from substrate support surface 105A by a first portion of dielectric material 105B, and an edge control electrode 115 spaced from the center of bias electrode 104. Generally, edge control electrode 115 is spaced from bias electrode 104 by dielectric material of substrate support 105, dielectric material used to form dielectric tube 110, dielectric material of edge ring 114 when edge control electrode 115 is embedded therein, or dielectric material of substrate support assembly 136 that can include a combination thereof. Here, bias electrode 104 is electrically connected to a first bias generator 196 configured to establish a first pulse voltage (PV) waveform on bias electrode 104. Edge control electrode 115 is electrically connected to a second bias generator 197 configured to establish a second pulse voltage (PV) waveform on edge control electrode 115.

[0107]

[0116] In some embodiments, the first plasma generated in step 702 is a capacitively coupled plasma (CCP) generated using a radio frequency (RF) signal from an RF waveform generator 163 that is electrically connected to the substrate support assembly 136, such as being electrically connected to the support base 107. In this case, the chamber lid 123 is grounded (as shown) or electrically connected to a second RF generator. In other embodiments (not shown), the first plasma can be a CCP formed using an RF generator electrically connected to the chamber lid 123. In this case, the substrate support assembly 136 is electrically connected to ground. In other embodiments, the first plasma can be an inductively coupled plasma (ICP) formed using an RF generator electrically connected to one or more ICP coils (not shown) disposed on the chamber lid 123.

[0108]

[0117] In some embodiments, the RF signal used to generate the first plasma has a frequency greater than about 400 kHz, such as greater than or equal to about 1 MHz, or greater than or equal to about 2 MHz, such as greater than or equal to about 13.56 MHz, greater than or equal to about 27 MHz, greater than or equal to about 40 MHz, or, for example, between about 30 MHz and about 200 MHz, such as between about 30 MHz and about 160 MHz, between about 30 MHz and about 120 MHz, or between about 30 MHz and about 60 MHz.

[0109]

[0118] In step 704, the method includes exposing the edge ring 114 and the substrate support surface 105A to the first plasma. In some embodiments, the first plasma is formed from an oxygen-containing gas, a hydrogen-containing gas, a halogen-containing gas such as a fluorine and / or chlorine-based gas, or a combination thereof. In some embodiments, the radical species generated in the plasma react with the processing by-products accumulated on the surfaces within the processing space 129, such as the surfaces 114A - C of the edge ring 114. Volatile substances are formed by the reaction and are discharged from the processing space 129 through the vacuum outlet 120. In some embodiments, the first time by the RF plasma can be about 1 second or more, such as about 5 seconds or more, or about 10 seconds or more.

[0110]

[0119] In step 706 of method 700, the plasma sheath boundary of the first plasma over the edge pocket region is adjusted by tuning variable capacitor C7 and / or C8 in edge tuning circuit 170 and / or by establishing a pulsed voltage (PV) waveform at edge control electrode 115 to supply a larger voltage between the bulk plasma and edge ring 114 than between the bulk plasma and substrate support surface 105A.

[0111]

[0120] In some embodiments, the second pulsed voltage (PV) waveform established at the edge control electrode during step 706 includes a series of repeating cycles where the voltage waveform within each cycle has a first portion that occurs during a first time interval (e.g., sheath collapse phase 452) and a second portion that occurs during a second time interval (e.g., sheath formation phase 451 and ion current phase 452). Generally, the voltage during the first interval is different from the voltage during the second interval, and the voltage difference determines the energy of the ions accelerated across the sheath to edge ring 114.

[0112]

[0121] In some embodiments, the voltage established on the bias electrode by the first pulse voltage (PV) waveform generator 150 (here the bias voltage) is actually maintained at zero volts VPP (e.g., about 0 volts ± 1 volt (zero (null) volts)) during at least a plurality of repetitive cycles of the second PV waveform established on the edge control electrode 115 in step 704. For example, in some embodiments, the second PV waveform can be established on the edge control electrode 115 at a non-zero VPP. The pulse voltage VPP established on the bias electrode using the first PV waveform generator can be actually maintained at zero volts (e.g., about 0 volts ± 1 volt (zero (null) volts)) for about 1 second or more, such as about 5 seconds or more, or about 10 seconds or more. In some embodiments, the bias electrode 104 is connected to ground during the first period by using a switch connected between the power supply line 157 and ground. In another embodiment, the PV waveform generator 150 or another driver (not shown) can be used to drive the bias voltage to zero volts (null volt).

[0113]

[0122] In some embodiments as shown in FIG. 8A, steps 702, 704, and 706 are performed with the substrate 103 (shown in dashed lines) absent such that the substrate support surface 105A is exposed to the first plasma. Advantageously, due to the potential difference between the portion of the plasma formed on the substrate support surface 105A and the portion of the plasma formed on the edge ring 114, the plasma sheath boundary 11 bends at portion 11B. The shape of the plasma sheath boundary shown in FIG. 8A is configured to preferentially direct the plasma-generated ions based on the formed bend 11B towards the edge pocket surface 114A-B. By directing the plasma-generated ions towards the edge pocket surface 114A-B and simultaneously reducing the voltage between the plasma and the substrate support surface 105A, method 700 can be used to preferentially clean the surface of the edge ring 114 while substantially reducing unwanted plasma-based erosion of the substrate support 105.

[0114]

[0123] In some embodiments, method 700 optionally includes processing substrate 103 using a second plasma formed before or after the pre-cleaning steps described in steps 702 - 706. For example, method 700 may optionally include positioning substrate 103 on substrate support surface 105A in step 708, generating a second plasma within processing region 129A in step 710, exposing substrate 103 to the second plasma for a second time period in step 712, and establishing a first pulsed voltage (PV) waveform on bias electrode 104 in step 714. In some embodiments, substrate 103 used to perform the optional steps 708 - 714 of method 700 is a non-production substrate. That is, the substrate is of the type used to perform cleaning operations, test operations, and / or maintenance operations, commonly referred to as "blanket" or "dummy" wafers.

[0115]

[0124] In some embodiments, step 708 of method 700 further includes electrostatically clamping substrate 103 to substrate support 105 by supplying a chucking voltage from DC power supply 155 electrically connected to bias electrode 104 using power supply line 157. The chucking voltage creates a voltage potential difference between substrate 103 and bias electrode 104, and as a result, is used to create an electrostatic attraction force (chucking force) through capacitance C1 (FIG. 1C) of a first portion of the dielectric material disposed therebetween. In some embodiments, method 700 further includes electrostatically clamping edge ring 114 to substrate support assembly 136 by supplying a chucking voltage from DC power supply 155 electrically connected to edge control electrode 115 using power supply line 158. In some embodiments, method 700 includes flowing an inert gas (e.g., helium) into backside space 105D (FIG. 1D) disposed between substrate 103 and substrate support surface 105A and / or between edge ring 114 and the surface of substrate support assembly 136 to facilitate heat transfer therebetween.

[0116]

[0125] In some embodiments, step 714 of method 700 further includes adjusting one or more characteristics of a second pulse voltage (PV) waveform relative to one or more characteristics of a first pulse voltage (PV) waveform to control the shape of the plasma sheath boundary 11 formed on substrate 103 and edge ring 114 during a second period. Thus, in some embodiments, step 714 includes adjusting one or more characteristics of a first PV waveform established by bias electrode 104 relative to one or more characteristics of a second PV waveform established by edge control electrode 115. In some embodiments, adjusting one or more characteristics includes adjusting one or a combination of the PV waveform frequencies (1 / T P ), pulse voltage levels Vpp, and pulse voltage on-times of the first and / or second PV waveforms respectively established on bias electrode 104 and edge control electrode 115. In some embodiments, one or more characteristics are controlled to increase or decrease the height of the sheath on edge control electrode 115 relative to the height of the sheath on bias electrode 104 and to bend the plasma sheath at the edge of the substrate or substrate support 105 to enable fine-tuning of ion trajectories and ion energies in the edge region of substrate 103 or substrate support 105.

[0117]

[0126] FIG. 7B is a process flow diagram showing a method 720 for preferentially cleaning the surface defining the edge pocket region 117 of substrate support assembly 136 according to one embodiment. Aspects of method 720 are schematically shown in FIG. 8B. However, it is contemplated that method 720 can be implemented using any of the processing system configurations described in FIGS. 1A-1D. In some embodiments, substrate 103 is a non-production substrate. That is, the substrate is of the type used to perform cleaning operations, test operations, and / or maintenance operations, commonly referred to as "blanket" or "dummy" wafers. In other embodiments, method 720 can be implemented to remove processing by-product residues, for example, from the beveled edge or backside edge of a manufacturing substrate during plasma processing of a manufacturing substrate having semiconductor devices at least partially formed thereon.

[0118]

[0127] Here, method 720 generally includes preferentially cleaning the surface that defines the edge pocket region 117 by adjusting the characteristics of the respective pulsed voltage (PV) waveforms established by the bias electrode 104 and the edge control electrode 115. During the cleaning process, the substrate 103 remains on the substrate support surface 105A such that the substrate 103 is disposed between the substrate support surface 105A and the plasma. The substrate 103 serves as a cover to prevent ion collision and erosion of the substrate support surface 105A. In some embodiments, the substrate 103 is at least partially lifted from the substrate support surface 105A such that plasma and / or radical species formed in the plasma can more readily diffuse into the edge pocket region 117 and react with processing by-products (e.g., carbon-containing polymers) formed on the surfaces therein. It is contemplated that at least some of the steps of method 720 may be the same as or substantially similar to the corresponding steps of method 700 described above.

[0119]

[0128] Method 720 generally includes positioning the substrate 103 on the substrate support assembly 136 in step 722, generating a plasma in step 724, and exposing the substrate 103 and the edge ring 114 (optionally) to the plasma for a first period in step 726, and optionally adjusting the plasma sheath boundary in step 728 by biasing one or both of the substrate 103 and the edge ring 114.

[0120]

[0129] Positioning the substrate 103 in step 722 generally includes transferring the substrate 103 to the substrate support surface 105A. In some embodiments, the substrate is electrically clamped to the substrate support assembly as described in step 708 of method 700. The plasma can be generated in step 724 using an RF signal as described above in steps 702 and / or 710 of method 700.

[0121]

[0130] In some embodiments, the substrate 103 is optionally exposed to plasma for a first period in step 728. The substrate 103 and the edge ring 114 are optionally biased by using first and second pulse voltage waveform generators to establish a PV waveform at the bias electrode and the edge control electrode, as described, for example, in steps 712 and 714 of method 700.

[0122]

[0131] In step 730, method 720 includes at least partially lifting the substrate 103 from the substrate support surface 105A, as shown in FIG. 8B. Typically, the substrate 103 is at least partially lifted from the substrate support surface 105A using a plurality of lift pins 20 extending through the substrate support assembly 136. When the substrate is electrostatically clamped to the substrate support 105 as described in step 708, at least partially lifting the substrate 103 may include stopping or adjusting the supply of the chucking voltage to the bias electrode 104 and / or discharging the electrostatic charge between the substrate 103 and the bias electrode 104, for example, by setting the DC voltage potential of the bias electrode 104 to be similar to the DC voltage potential of the substrate 103.

[0123]

[0132] In steps 732 and 734, method 720 each includes exposing the edge pocket surfaces 114A - B to plasma and simultaneously adjusting the plasma sheath boundary 11. Steps 732 and 734 may be performed using a process substantially similar to that used to perform steps 704 and 706 of method 700 with the addition of the substrate 103 partially lifted on the substrate support surface 105A. It is contemplated that any one or more of the steps of method 720 may be used in combination with method 740, or vice versa, to increase the in - situ plasma cleaning efficiency in the edge pocket region 117 while protecting the substrate support surface 105A from unwanted plasma - based erosion.

[0124]

[0133] FIG. 7C is a process flow diagram showing a method 740 for preferentially cleaning the edge pocket surfaces 114A - B of the substrate support assembly 136 according to another embodiment. It is contemplated that the method 740 can be executed using any of the processing systems described herein, such as any one of the substrate support assemblies 136 of FIGS. 1A - 1D and FIGS. 8A - 8C. As shown in FIG. 8C, the method 740 generally includes using the tuning circuit 170 to concentrate plasma between the outer peripheral edge of the substrate 103 that is at least partially lifted from the substrate support surface 105A and the edge pocket surfaces 114A - B, such as the edge pocket region 117. The concentrated plasma increases the radical and ion concentration in the edge pocket region 117, which can be used to preferentially clean the surfaces 114A - B therein. Typically, the substrate 103 is only partially lifted to a distance sufficient to prevent plasma from forming between the substrate 103 and the substrate support surface 105A, thus preventing plasma - based erosion. In some embodiments, the substrate 103 is a non - production substrate, generally referred to as a "blanket" or "dummy" wafer. In other embodiments, the method 740 can be implemented during plasma processing of a manufacturing substrate having semiconductor devices at least partially formed thereon, for example, to remove processing by - product residues from the beveled edge or backside edge of the manufacturing substrate.

[0125]

[0134] Step 742 of method 740 includes positioning the substrate 103 on the substrate support surface 105A of the substrate support assembly 136 as shown in FIG. 8C. Step 742 can be the same as or substantially similar to step 722 of method 720.

[0126]

[0135] Step 744 of method 740 includes igniting and maintaining a plasma by using a radio frequency (RF) signal. In some embodiments, the RF signal is supplied to support base 107 of substrate support assembly 136 using an electrically connected plasma generator assembly 163. Here, the RF signal is configured to ignite and / or maintain process plasma 101 in process region 129A of process chamber 100. Process region 129A is disposed between substrate support assembly 136 and chamber lid 123. In some embodiments, the RF signal has a frequency of about 1 MHz or more, such as about 20 MHz or more, such as between about 30 MHz and about 60 MHz, or about 40 MHz.

[0127]

[0136] Typically, the RF signal supplied to support base 107 establishes a first RF waveform 501 (FIGS. 6A - 6B) at bias electrode 104. This bias electrode 104 is capacitively coupled to support base 107 through a third portion of a dielectric material (e.g., dielectric material layer 105C) disposed therebetween. Bias electrode 104 is spaced from process plasma by a first portion of the dielectric material (e.g., dielectric material layer 105B), and substrate 103 is disposed on substrate support surface 105A. In some embodiments, method 740 further includes electrostatically clamping substrate 103 to substrate support 105 as described in step 708 of method 700.

[0128]

[0137] In operation 746, method 740 includes exposing a surface of substrate 103 to a plasma over a first period. Step 748 of method 740 optionally includes adjusting one or both of the plasma density and / or the shape of the plasma sheath boundary 11. In some embodiments, adjusting the plasma density includes adjusting one or more characteristics of a second RF waveform 502 established at edge control electrode 115 relative to one or more characteristics of a first RF waveform 501 established at bias electrode 104. In some embodiments, adjusting one or more characteristics of the second RF waveform 502 relative to one or more characteristics of the first RF waveform 501 includes changing the voltage amplitude ratio (e.g., V RF2 / V RF1 ) between the second RF waveform 502 and the first RF waveform 501, adjusting the current amplitude ratio between the second RF waveform 502 and the first RF waveform, adjusting the phase difference (e.g., delta Φ) between the second RF waveform 502 and the first RF waveform 501, or a combination thereof, as shown in FIGS. 5A or 5B. In some embodiments, adjusting one or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 is performed by adjusting the electrical characteristics of one or more elements within edge tuning circuit 170.

[0129]

[0138] In some embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 varies the plasma uniformity across at least a portion of the processing region 129A (FIGS. 1A - 1B). For example, in one embodiment, the processing region 129A is defined by the chamber lid 123 and the substrate support assembly 136, and the plasma 101 is the bulk plasma formed therebetween. In some embodiments, a first portion of the plasma 101 is formed in a region disposed between the chamber lid 123 and the bias electrode 104. A second portion of the plasma 101 is formed in a region disposed between the chamber lid 123 and the edge control electrode 115. In those embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 varies the plasma density in the second portion of the plasma 101 relative to the plasma density in the first portion of the plasma 101.

[0130]

[0139] In some embodiments, adjusting one or more characteristics of the second RF waveform 502 established by the edge control electrode 115 relative to one or more characteristics of the first RF waveform 501 established by the bias electrode 104 includes using the edge tuning circuit 170. In some embodiments, the edge tuning circuit 170 includes one or more variable capacitors C7, C8, and adjusting one or more characteristics of the second RF waveform 502 relative to one or more characteristics of the first RF waveform 501 includes changing one or more of the capacitances C7, C8. Adjustment of the edge tuning circuit 170 can be automatically performed such that the system controller 126 adjusts the electrical characteristics of one or more components of the edge tuning circuit 170, such as the capacitances C7, C8, based on the desired characteristics of the RF waveforms 501, 502 and / or the desired differences therebetween.

[0131]

[0140] For example, in some embodiments, system controller 126 may be configured to determine the characteristics of each waveform by measuring one or more characteristics of the electrical signals taken at one or more nodes N by using signal detection module 187, compare the determined characteristics with the desired characteristics, and based on that comparison, change the output of the components of edge tuning circuit 170. In some embodiments, edge tuning circuit 170 may be manually adjusted when the user changes the set point of a component of edge tuning circuit 170, such as the capacitance of variable capacitors C7, C8 or the inductance L of the circuit. The user may change the set point by using system controller 126 and / or signal detection module 187 to change recipe parameters corresponding to components or other settings in the instructions used by system controller 126 to operate processing systems 10A, 10B, for example.

[0132]

[0141] Assuming generally that a relatively constant RF power is supplied from plasma generator assembly 163 to support base 107, an increase in the V RF2 / V RF1 ratio due to the use of edge tuning circuit 170 will result in an increase in the ratio of the plasma density near the edge of the substrate to the plasma density near the center of the substrate. The relative increase in plasma density causes a corresponding increase in the plasma generating species in the bulk plasma, resulting in a relative increase in the ion flux and the concentration of reactive neutral molecules at the edge of the underlying substrate surface. Similarly, when the V RF2 / V RF1 ratio decreases, the ratio of the plasma density near the edge of the substrate to the plasma density near the center of the substrate decreases, and the ion flux and the concentration of reactive neutral molecules at the edge of the substrate decrease correspondingly.

[0133]

[0142] By controlling the relative plasma density between the first and second portions of the plasma, the corresponding distribution of active species within the processing region 129A is also controlled and can be used to improve overall process non-uniformities such as in-wafer process non-uniformities. Advantageously, step 748 can be implemented as a process parameter adjustment by using the system controller 126 to control the edge tuning circuit 170 and adjusting the capacitances C7 and / or C8. Thus, method 740 can be implemented without relying on mechanical adjustments or changes to the hardware configuration that are typically required to adjust the bulk plasma distribution in a capacitively coupled plasma (CCP) system and thus impede its fine control.

[0134]

[0143] Step 750 of method 700 optionally includes biasing the substrate 103 and / or the edge ring 114 by establishing a pulsed voltage (PV) waveform at one or both of the bias electrode 104 and the edge control electrode 115. The process used to bias the substrate 103 and / or the edge ring 114 during the first period can be the same as or substantially similar to the process described in step 714 of method 700.

[0135]

[0144] Step 752 of method 740 includes at least partially lifting the substrate from the substrate support surface 105A, which can be performed using the same or substantially similar process as described in step 830 of method 720. In step 754, method 740 includes exposing the edge pocket surfaces 114A - B to the plasma for a period of time.

[0136]

[0145] Prior to or during processes 752 and 754, process 756 of method 740 includes adjusting one or more characteristics of radio frequency (RF) waveforms respectively established by bias electrode 104 and edge control electrode 115 to form plasma in edge pocket region 117 over at least a portion of a period. In some embodiments, adjusting one or more characteristics of the RF waveforms includes adjusting the phase difference (e.g., delta Φ) between a second RF waveform 502 and a first RF waveform 501 such that plasma is formed between the outer peripheral edge of substrate 103 and edge pocket surfaces 114A - B. Here, the substrate is at least partially lifted to provide a gap or space sufficient for plasma to be formed between the substrate and edge pocket surfaces 114A - B while maintaining a gap small enough to prevent plasma from being formed between the substrate and substrate support surface 105A. In some embodiments, the bias voltages respectively established on bias electrode 104 and edge control electrode 115 using electrically connected waveform generator 150 are maintained at a constant value or a zero value (null value) for at least a portion of the period. For example, in some embodiments, the bias voltage established on one or both of bias electrode 104 and edge control electrode 115 is actually maintained at zero volts VPP (e.g., about 0 volts ± 1 volt (null volt)) over at least a portion of a period such as about 1 second or more, about 5 seconds or more, or about 10 seconds or more. Maintaining the bias voltage at actually zero volts VPP can include connecting each electrode to ground or using PV waveform generator 150 or another driver (not shown) to drive the bias voltage to zero volts as described in relation to FIG. 7A for method 700.

[0137]

[0146] In some embodiments, method 740 further includes preferentially adjusting the plasma density toward a portion of plasma 101 formed on edge control electrode 115 relative to the plasma density of a portion of the plasma formed on bias electrode 104. Here, preferentially adjusting the plasma density includes, as shown in FIG. 6A or FIG. 6B, the voltage amplitude ratio (e.g., VRF2 / V RF1 changing the ( ), adjusting the current amplitude ratio between the second RF waveform 502 and the first RF waveform, adjusting the phase difference (e.g., delta Φ) between the second RF waveform 502 and the first RF waveform 501, or combinations thereof.

[0138]

[0147] To provide fine control over the generation and distribution of active species within the processing region of an inductively coupled plasma (ICP) chamber or capacitively coupled plasma (CCP) chamber, the above-described embodiments can be used alone or in combination. Advantageously, this embodiment can be implemented by using a system controller without adjusting or modifying individual chamber components. Accordingly, a process recipe parameter is provided that can be easily adjusted during the processing of a single substrate and / or between substrates being processed continuously. The RF plasma density control method can be implemented independently and / or in combination with the pulsed voltage (PV) waveform bias method to independently and finely control ion energy, IEDF, ion directionality, ion flux, and the concentration of reactive neutral molecules at the substrate surface, as compared to conventional RF bias CCP systems.

[0139]

[0148] While the foregoing description has been directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof. The scope of the present disclosure is determined by the following claims.

Claims

1. A plasma processing method, comprising: (a) generating plasma within a processing region defined by a chamber lid and a substrate support assembly, the substrate support assembly comprising: a first portion of a dielectric material forming a substrate support surface; an edge ring surrounding the substrate support surface, the edge ring comprising a plasma facing surface and one or more edge pocket surfaces disposed inwardly from the plasma facing surface; a bias electrode disposed spaced apart from the substrate support surface by the first portion of the dielectric material; an edge control electrode disposed at a distance from the center of the bias electrode; wherein the bias electrode is electrically connected to a first bias generator configured to establish a first pulse voltage (PV) waveform at the bias electrode; the edge control electrode is electrically connected to a second bias generator configured to establish a second pulse voltage (PV) waveform at the edge control electrode, and generating plasma; (b) exposing the edge ring and the substrate support surface to the plasma; (c) simultaneously with (b), establishing the second pulse voltage (PV) waveform at the edge control electrode. A plasma processing method comprising the above steps.

2. The method according to claim 1, wherein the first pulse voltage (PV) waveform generator does not establish the first pulse voltage (PV) waveform at the bias electrode for at least a portion of the time during which the edge ring and the substrate support surface are exposed to the plasma.

3. The method according to claim 1, wherein the first pulse voltage (PV) waveform and the second pulse voltage (PV) waveform have a frequency of about 1 MHz or less.

4. The method according to claim 1, wherein the second pulse voltage (PV) waveform comprises a series of repeating cycles, each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval, wherein the voltage during the second time interval is lower than the voltage during at least a portion of the first time interval.

5. The method according to claim 4, wherein the voltage established at the bias electrode is maintained at about 0 ± 1 volt (V) by electrically connecting the bias electrode to ground.

6. The method according to claim 4, wherein by controlling the first pulse voltage (PV) bias generator, the voltage established at the bias electrode is maintained at about 0 ± 1 volt (V).

7. (d)Adjusting one or more characteristics of the second pulse voltage (PV) waveform relative to one or more characteristics of the first pulse voltage (PV) waveform to control the shape of the plasma sheath boundary formed on the substrate support surface and the edge ring The method according to claim 4, further comprising.

8. The method according to claim 7, wherein the shape of the plasma sheath boundary is at least partially determined by a difference in frequency, duration, and / or amplitude of the voltage pulses between the first pulse voltage (PV) waveform and the second pulse voltage (PV) waveform.

9. The plasma is generated using a radio frequency (RF) signal from an RF waveform generator, The RF signal has a frequency of about 1 MHz or more, The RF generator is Electrically connected to a support base having the chamber lid or a substrate support disposed thereon, configured to supply an RF signal to ignite and maintain the plasma, or Electrically connected to a plasma generator assembly configured to generate an electromagnetic field used to ignite and maintain the plasma, The method according to claim 8.

10. (d)By adjusting one or more characteristics of the second pulse voltage (PV) waveform relative to one or more characteristics of the first pulse voltage (PV) waveform, a bend is generated within the plasma sheath boundary, and the plasma-generated ions are preferentially directed towards the edge pocket region of the substrate support assembly. The method according to claim 9.

11. A plasma processing method, comprising (a)Igniting and maintaining a plasma within a processing region of a processing chamber, wherein the plasma includes a first portion disposed between a substrate support surface of a substrate support assembly and a chamber lid, and a second portion disposed between an edge ring and the chamber lid, and the substrate support assembly includes A first portion of a dielectric material forming the substrate support surface, A bias electrode disposed at a distance from the substrate support surface by the first portion of the dielectric material, the bias electrode being electrically connected to a first pulse voltage (PV) waveform generator configured to establish a first pulse voltage waveform in the bias electrode. An edge control electrode disposed at a distance from the center of the bias electrode, the edge control electrode being electrically connected to a second pulse voltage (PV) waveform generator. The edge ring surrounding the substrate support surface, the edge ring including one or more edge pocket surfaces defining an edge pocket region by at least a partially lifted substrate disposed on the substrate support surface. Comprising igniting and maintaining a plasma. (b) Using the second pulse voltage (PV) waveform generator to establish a second pulse voltage (PV) waveform at the edge control electrode. (c) Exposing the at least partially lifted substrate to the plasma. A plasma processing method including.

12. The second pulse voltage (PV) waveform established at the edge control electrode includes a series of repeating cycles. The waveform within each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval. The method according to claim 11, wherein the voltage during the second time interval is lower than the voltage during at least a part of the first time interval.

13. The voltage established at the bias electrode using the first pulse voltage (PV) waveform generator is maintained between about -1 volt (V) and about 1 V for at least a part of the period during which the partially lifted substrate is exposed to the plasma. The method according to claim 12.

14. The first pulse voltage (PV) waveform generator does not establish the first pulse voltage (PV) waveform at the bias electrode for at least a part of the period during which the partially lifted substrate is exposed to the plasma. The method according to claim 12.

15. The method according to claim 12, wherein the repeating cycle of the second pulse voltage (PV) waveform has a frequency of about 1 MHz or less.

16. To change the shape of the plasma sheath formed on the substrate support, adjusting one or more characteristics of the first pulse voltage (PV) waveform, the second pulse voltage (PV) waveform, or both The method according to claim 12, further comprising: **Claim 17** The method according to claim 16, wherein (e) comprises increasing the frequency, duration, and / or amplitude of the voltage pulses within the second pulse voltage (PV) waveform. **Claim 18** The plasma is ignited and sustained using a radio frequency (RF) signal from an RF generator, The method according to claim 17, wherein the RF signal has a frequency of about 1 MHz or more. **Claim 19** The substrate support assembly further comprises a support base and a second portion of a dielectric material disposed on the support base, The RF generator is electrically connected to the support base, The method according to claim 18, wherein the bias electrode is spaced from the support base by the second portion of the dielectric material. **Claim 20** The method according to claim 19, wherein changing the shape of the plasma sheath in (d) causes a bend at the plasma sheath boundary and preferentially directs plasma-generated ions toward the surface of the edge pocket region.

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