Divider circuit and oscillator

Abstract

To solve the problem that the duty ratio of a clock signal with an odd frequency division ratio cannot be adjusted to 50%.SOLUTION: A divider circuit comprises: an internal clock generation circuit that is connected with first to n-th (n is an integer of 2 or more) flip flop circuits, and divides an input clock signal by (2n-1) to generate a first internal clock signal; an edge timing generation circuit that, on the basis of the input clock signal, generates a second internal clock signal having a rising edge at a timing delayed by ((2n-1) / 2) of the period of the input clock signal from a rising edge of the first internal clock signal; and an RS latch circuit that has a reset terminal to which the first internal clock signal is input, and a set terminal to which the second internal clock signal is input.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a frequency division circuit and an oscillator.

Background Art

[0002] Conventionally, a frequency division circuit capable of switching the division ratio has been known. For example, Patent Document 1 discloses a frequency division circuit capable of setting an odd division ratio.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the conventional technology, it has not been possible to make the duty ratio of the clock signal with an odd division ratio 50%.

Means for Solving the Problems

[0005] The frequency division circuit according to one embodiment includes an internal clock generation circuit to which first to nth (n is an integer of 2 or more) flip-flop circuits are connected and which divides an input clock signal by (2n - 1) to generate a first internal clock signal, an edge timing generation circuit that generates a second internal clock signal having a rising edge at a timing delayed by ((2n - 1) / 2) periods of the input clock signal with respect to the rising edge of the first internal clock signal based on the input clock signal, and an RS latch circuit having a reset terminal to which the first internal clock signal is input and a set terminal to which the second internal clock signal is input.

[0006] Also, the frequency division circuit according to one embodiment includes a first D-type flip-flop circuit that operates based on an input clock signal, a second D-type flip-flop circuit that operates based on the input clock signal, a first AND circuit having an output signal of the first D-type flip-flop circuit input to one input terminal and outputting a signal to the second D-type flip-flop circuit, a first inverter circuit that inverts a feedback clock signal based on the output signal of the second D-type flip-flop circuit and outputs it to the first D-type flip-flop circuit, a second inverter circuit that inverts the feedback clock signal and outputs it to the other input terminal of the first AND circuit, a second AND circuit having the input clock signal input to one input terminal, a third inverter circuit that inverts the output signal of the first D-type flip-flop circuit and outputs it to the other input terminal of the second AND circuit, and an RS latch circuit having the output signal of the second D-type flip-flop circuit input to a reset terminal and the output signal of the second AND circuit input to a set terminal.

Brief Description of the Drawings

[0007]

Figure 1

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Embodiments for Carrying Out the Invention

[0008] Here, embodiments of the present invention will be described in the following order. (1) Configuration of the oscillator (2) Configuration of the frequency division circuit (3) Second Embodiment (4) Third Embodiment (5) Fourth Embodiment (6) Fifth Embodiment (7) Sixth Embodiment (8) Seventh Embodiment (9) Eighth Embodiment (10) Ninth Embodiment (11) Tenth Embodiment (12) Other Embodiments, etc.

[0009] (1) Configuration of the oscillator FIG. 1 is a functional block diagram of the oscillator 200 of the present embodiment. As shown in FIG. 1, the oscillator 200 of the present embodiment includes an integrated circuit 201 and a resonator 202. As the resonator 202, for example, a crystal resonator, a SAW (Surface Acoustic Wave) resonator, other piezoelectric vibration elements, MEMS (Micro Electro Mechanical Systems) resonators, etc. can be used.

[0010] In the present embodiment, the integrated circuit 201 is composed of one chip and includes an XG terminal, an XD terminal, an SCLK terminal, an SDIO terminal, a VDD terminal, a VSS terminal, an OUT terminal, and an OUTB terminal. The integrated circuit 201 includes an oscillation circuit 210, a PLL circuit 220, an output circuit 230, a communication interface circuit 240, a memory circuit 250, a division ratio generation circuit 260, and a power supply circuit 270. Note that the integrated circuit 201 may be configured by omitting or changing some of these elements, or adding other elements.

[0011] Each circuit of the integrated circuit 201 operates with reference to the ground voltage (0V) supplied via the VSS terminal. The power supply circuit 270 generates various voltages with reference to the ground voltage based on the power supply voltage supplied via the VDD terminal. The voltages generated by the power supply circuit 270 serve as the power supply voltages for the oscillation circuit 210, the PLL circuit 220, and the output circuit 230.

[0012] The oscillation circuit 210 is connected to one end of the resonator 202 via the XG terminal and to the other end of the resonator 202 via the XD terminal. The oscillation circuit 210 amplifies the output signal of the resonator 202 input via the XG terminal and feeds back the amplified signal to the resonator 202 via the XD terminal to oscillate the resonator 202. For example, the oscillation circuit composed of the resonator 202 and the oscillation circuit 210 may be various types of oscillation circuits such as a Pierce oscillation circuit, an inverter type oscillation circuit, a Colpitts oscillation circuit, a Hartley oscillation circuit, etc.

[0013] The PLL circuit 220 is phase-locked to the oscillation signal output from the oscillation circuit 210, and generates and outputs a clock signal obtained by multiplying and dividing the frequency of the oscillation signal. In the present embodiment, the PLL circuit 220 is a fractional N-PLL circuit. Specifically, the PLL circuit 220 includes a phase comparator 221, a charge pump 222, a low-pass filter 223, a voltage-controlled oscillator 224, a feedback divider circuit 225, a clock conversion circuit 226, a delta-sigma modulation circuit 227, a divider circuit 228, and a second divider circuit 229.

[0014] The phase comparator 221 compares the phase difference between the oscillation signal output from the oscillation circuit 210 and the clock signal FBCK output from the feedback divider circuit 225, and outputs the comparison result as a pulse voltage. The charge pump 222 converts the pulse voltage output from the phase comparator 221 into a current, and the low-pass filter 223 smoothes the current output from the charge pump 222 and converts it into a voltage.

[0015] The voltage-controlled oscillator 224 outputs a clock signal CK whose frequency changes according to the output voltage of the low-pass filter 223. For example, the voltage-controlled oscillator 224 is realized by an LC oscillation circuit composed of an inductor and a variable capacitance element. The feedback divider circuit 225 outputs a clock signal FBCK obtained by integer-dividing the clock signal CK at a division ratio corresponding to the output signal of the delta-sigma modulation circuit 227.

[0016] The clock conversion circuit 226 converts the clock signal FBCK into a clock signal DSMCK. For example, the clock conversion circuit 226 may output the clock signal FBCK as the clock signal DSMCK as it is, or may output a clock signal DSMCK obtained by integer-dividing the clock signal FBCK.

[0017] The delta-sigma modulation circuit 227 performs delta-sigma modulation that integrates and quantizes the division ratio N+F / M output by the division ratio generation circuit 260 in synchronization with the clock signal DSMCK output by the clock conversion circuit 226. Here, N is an integer division ratio, and F / M is a fractional division ratio. The output signal of the delta-sigma modulation circuit 227 is input to the feedback division circuit 225. As a result, the division ratio of the feedback division circuit 225 changes in time series to a plurality of integer values in the range near the integer division ratio N, and the time average value thereof becomes N+F / M. Therefore, in the steady state where the phase of the oscillation signal output from the oscillation circuit 210 and the phase of the clock signal FBCK output from the feedback division circuit 225 are synchronized, the frequency of the clock signal CK output from the voltage controlled oscillator 224 is N+F / M times the frequency of the oscillation signal output from the oscillation circuit 210.

[0018] In this embodiment, it is assumed that the division ratio N+F / M is input to the delta-sigma modulation circuit 227. However, for example, the delta-sigma modulation circuit 227 may perform delta-sigma modulation on the fractional division ratio F / M, and the output signal of the delta-sigma modulation circuit 227 and the integer division ratio N may be added and subtracted and input to the feedback division circuit 225.

[0019] The clock signal CK is input to the division circuit 228. Therefore, the clock signal CK is the clock signal input to the division circuit 228, and hereinafter, it is also referred to as the input clock signal CK. In this embodiment, the oscillator 202, the oscillation circuit 210, the phase comparator 221, the charge pump 222, the low-pass filter 223, the voltage controlled oscillator 224, the feedback division circuit 225, the clock conversion circuit 226, and the delta-sigma modulation circuit 227 constitute a clock signal generation circuit 280 that supplies the input clock signal CK to the division circuit 228.

[0020] The division circuit 228 outputs a clock signal CKO obtained by integer-dividing the input clock signal CK output by the voltage controlled oscillator 224 at a predetermined division ratio of 3. The configuration of the division circuit 228 will be described later.

[0021] The second frequency division circuit 229 outputs a clock signal obtained by integer-dividing the clock signal CKO output from the frequency division circuit 228 at a frequency division ratio set by the second frequency division ratio setting signal ODIVL output from the frequency division ratio generation circuit 260. In the present embodiment, the second frequency division circuit 229 divides the clock signal CKO by 2 m (m is an integer of 0 or more). That is, according to ODIVL, a frequency division ratio that is a power of 2 or a frequency division ratio of 1 can be selected.

[0022] The output circuit 230 generates two output signals with inverted polarities based on the clock signal output from the second frequency division circuit 229, and outputs them to the outside of the integrated circuit 201 via the OUT terminal and the OUTB terminal. The output format from the output circuit 230 may be, for example, PECL (Positive Emitter Coupled Logic) output, LVDS (Low Voltage Differential Signaling) output, HCSL (High-Speed Current Steering Logic) output, etc. Alternatively, the output circuit 230 may generate a single-ended clock signal such as CMOS (Complementary Metal Oxide Semiconductor) output based on the clock signal output from the second frequency division circuit 229, and output it to the outside of the integrated circuit 201 via the OUT terminal or the OUTB terminal.

[0023] The communication interface circuit 240 is, for example, an interface circuit compatible with the I2C (Inter-Integrated Circuit) bus. It receives a serial data signal input via the SDIO terminal in synchronization with a serial clock signal input via the SCLK terminal from an external device (not shown), and stores various data in the register 251 or the non-volatile memory 252 of the storage circuit 250 according to the received serial data. Note that the communication interface circuit 240 is not limited to an interface circuit compatible with the I2C bus, and may be, for example, an interface circuit compatible with the SPI (Serial Peripheral Interface) bus or the like.

[0024] The memory circuit 250 has a register 251 and a non-volatile memory 252. The non-volatile memory 252 is a storage unit for storing various control data, and may be various rewritable non-volatile memories such as EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash memory, or various non-rewritable non-volatile memories such as one-time PROM (One Time Programmable Read Only Memory). For example, in the manufacturing process of the oscillator 200, various control data is written into the non-volatile memory 252 via the communication interface circuit 240. Then, the various control data stored in the non-volatile memory 252 is transferred from the non-volatile memory 252 to the register 251 when the oscillator 200 is powered on, held in the register 251, and supplied to each circuit.

[0025] The frequency division ratio generation circuit 260 generates a frequency division ratio N+F / M and a second frequency division ratio setting signal ODIVL based on various data stored in the register 251 of the memory circuit 250.

[0026] The oscillator 200 configured as described above generates and outputs a clock signal having a frequency according to a setting based on the oscillation signal output from the resonator 202, and can be used, for example, as a clock signal generation device (clock generator). The clock signal output by the oscillator 200 can be set to a constant frequency according to the control data stored in the non-volatile memory 252, or can be set to a variable frequency according to the control data written into the register 251 via the communication interface circuit 240.

[0027] According to this embodiment, the frequency divider circuit 228 can convert the input clock signal CK into the clock signal CKO with a division ratio of 3, which is an odd division ratio. Also, according to the oscillator 200 of this embodiment, the clock signal CKO output by the frequency divider circuit 228 can be further divided by the second frequency divider circuit 229. The division ratio in the second frequency divider circuit 229 is determined by the second division ratio setting signal ODIVL, and the clock signal CKO can be divided by 2 m by the second frequency divider circuit 229. Thus, by combining the frequency divider circuit 228 and the second frequency divider circuit 229, the division ratio can be made 3×2 m without complicating the circuit.

[0028] Note that the oscillator according to the present invention is applicable not only to the oscillator 200 but also to oscillators without a PLL circuit, oscillators having a temperature compensation function such as a TCXO (Temperature Compensated Crystal Oscillator), and oscillators having a frequency control function such as a VCXO (Voltage Controlled Crystal Oscillator).

[0029] (2) Configuration of the frequency divider circuit As described above, the frequency divider circuit 228 according to this embodiment is a circuit that divides the input clock signal CK by 3. However, in a conventional frequency divider circuit that can divide by an odd division ratio, the duty ratio (the ratio of the period during which the pulse signal is at a high level in one cycle) does not become 50%. Therefore, when the division ratio 1 is selected in the second frequency divider circuit 229, in the prior art, the duty ratio of the clock signal output from the output circuit 230 does not become 50%. Since such a clock signal often does not meet the required specifications for the oscillator 200, in order to make the duty ratio 50%, it was necessary to provide, for example, a circuit for dividing by 2 after the odd division by the frequency divider circuit 228.

[0030] Therefore, the frequency division circuit 228 according to the present embodiment has a configuration capable of performing odd-frequency division with a duty ratio of 50%. FIG. 2 is a block diagram showing the configuration of the frequency division circuit 228. The frequency division circuit 228 includes an internal clock generation circuit 10, an edge timing generation circuit 20, and an RS latch circuit 30.

[0031] The internal clock generation circuit 10 is a circuit in which first to second flip-flop circuits are connected and the input clock signal CK is divided by 3 to generate a first internal clock signal Q1. Specifically, the internal clock generation circuit 10 includes a first D-type flip-flop circuit 11 and a second D-type flip-flop circuit 12 that operate based on the input clock signal CK. The internal clock generation circuit 10 also includes a first AND circuit 13 to which the output signal of the first D-type flip-flop circuit 11 is input to one input terminal and that outputs a signal to the second D-type flip-flop circuit 12.

[0032] Furthermore, the internal clock generation circuit 10 includes a first inverter circuit 14 that inverts the first internal clock signal Q1, which is a feedback clock signal based on the output signal of the second D-type flip-flop circuit 12, and outputs it to the first D-type flip-flop circuit 11. Furthermore, the internal clock generation circuit 10 includes a second inverter circuit 15 that inverts the first internal clock signal Q1, which is a feedback clock signal, and outputs it to the other input terminal of the first AND circuit 13.

[0033] The edge timing generation circuit 20 is a circuit that generates a second internal clock signal Q2 having a rising edge at a timing delayed by 3 / 2 cycles of the input clock signal with respect to the rising edge of the first internal clock signal Q1 based on the input clock signal CK. Specifically, the edge timing generation circuit 20 includes a second AND circuit 21 to which the input clock signal CK is input to one input terminal, and a third inverter circuit 22 that inverts the output signal of the first D-type flip-flop circuit 11 and outputs it to the other input terminal of the second AND circuit 21.

[0034] The RS latch circuit 30 has a reset terminal R to which a first internal clock signal Q1 is input and a set terminal S to which a second internal clock signal Q2 is input. That is, in the RS latch circuit 30, the first internal clock signal Q1, which is the output signal of the second D flip-flop circuit 12, is input to the reset terminal R, and the second internal clock signal Q2, which is the output signal of the second AND circuit 21, is input to the set terminal S.

[0035] Figure 3 is a timing chart showing the signals of each part in the frequency division circuit 228. As shown in Figure 3, the input clock signal CK input to the frequency division circuit 228 is a pulse signal with a constant period T. Also, the duty ratio of the input clock signal CK is 50%. The first D flip-flop circuit 11 and the second D flip-flop circuit 12 according to this embodiment perform a latch operation in synchronization with the falling edge of the input clock signal CK. For this reason, when the falling edge of the input clock signal CK is input to the first D flip-flop circuit 11, the signal obtained by inverting the first internal clock signal Q1 is latched.

[0036] For example, in a state where the first internal clock signal Q1 is at a low level, when the falling edge of the input clock signal CK is input to the first D flip-flop circuit 11 at time t0, the high-level state in which the first internal clock signal Q1 is inverted by the first inverter circuit 14 is latched by the first D flip-flop circuit 11. As a result, the output signal Q0 of the first D flip-flop circuit 11 becomes high level.

[0037] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a low level before time t0, even when the falling edge of the input clock signal CK is input to the second D flip-flop circuit 12 at time t0, the first internal clock signal Q1, which is the output of the second D flip-flop circuit 12, is at a low level.

[0038] Furthermore, at time t0, the signal input to the first AND circuit 13 is a high-level signal obtained by inverting the first internal clock signal Q1 by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes high level.

[0039] Furthermore, the signal input to the second AND circuit 21 is an inverted signal InvQ0 obtained by inverting the output signal Q0 of the first D flip-flop circuit 11 by the third inverter circuit 22. At time t0, since the inverted signal InvQ0 is at a low level, the signal input to the second AND circuit 21 is the inverted signal InvQ0 at a low level and a low-level signal after the falling edge of the input clock signal CK. Therefore, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, becomes low level. Even when half of the period T of the input clock signal CK has elapsed and the rising edge of the input clock signal CK occurs, since the inverted signal InvQ0 input to the second AND circuit 21 is at a low level, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, is at a low level.

[0040] As a result of the above, the first internal clock signal Q1 at a low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q2 at a low level is input to the set terminal S. For this reason, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t0 and becomes high level also during the period from time t0 to t1.

[0041] Next, when the period T of the input clock signal CK elapses from time t0, time t1 is reached, and the falling edge of the input clock signal CK is input to the first D flip-flop circuit 11, the state before time t1, that is, the high-level state obtained by inverting the first internal clock signal Q1 by the first inverter circuit 14 is latched in the first D flip-flop circuit 11. As a result, the output signal Q0 of the first D flip-flop circuit 11 remains in the high-level state.

[0042] Also, since the output signal D1 of the first AND circuit 13 is at a high level before time t1, when the falling edge of the input clock signal CK is input to the second D flip-flop circuit 12 at time t1, the first internal clock signal Q1, which is the output of the second D flip-flop circuit 12, becomes a high level.

[0043] Furthermore, at time t1, the signals input to the first AND circuit 13 are a low-level signal obtained by inverting the first internal clock signal Q1 by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes a low level.

[0044] Furthermore, at time t1, the signals input to the second AND circuit 21 are the inverted signal InvQ0, which is at a low level, and a low-level signal after the falling edge of the input clock signal CK. Therefore, the output signal Q2 output from the second AND circuit 21 becomes a low level. Here too, even when half of the period T of the input clock signal CK has elapsed and the rising edge of the input clock signal CK occurs, since the inverted signal InvQ0 input to the second AND circuit 21 is at a low level, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, is at a low level.

[0045] As a result of the above, the high-level first internal clock signal Q1 is input to the reset terminal R of the RS latch circuit 30, and the low-level second internal clock signal Q2 is input to the set terminal S. For this reason, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a low level during the period from time t1 to t2.

[0046] Next, when the period T of the input clock signal CK elapses from time t1 to reach time t2 and the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11, the state before time t2, that is, the low-level state in which the first internal clock signal Q1 is inverted by the first inverter circuit 14, is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes low level.

[0047] Also, since the output signal D1 of the first AND circuit 13 is low level before time t2, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t2, the first internal clock signal Q1, which is the output of the second D-type flip-flop circuit 12, becomes low level.

[0048] Furthermore, at time t2, the signals input to the first AND circuit 13 are the high-level signal in which the first internal clock signal Q1 is inverted by the second inverter circuit 15 and the low-level signal as the output signal Q0 of the first D-type flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes low level.

[0049] Furthermore, at time t2, the signals input to the second AND circuit 21 are the inverted signal InvQ0 which is high level and the low-level signal after the falling edge of the input clock signal CK. Therefore, the output signal Q2 output from the second AND circuit 21 becomes low level.

[0050] As a result of the above, the first internal clock signal Q1 which is low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q2 which is low level is input to the set terminal S. For this reason, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t2 and becomes low level during the period from time t2 to time t3.

[0051] Furthermore, during the time period from time t2 to time t4, since the inversion signal InvQ0 is at a high level, a high-level signal is input to one input terminal of the second AND circuit 21. Also, the input clock signal CK is input to the other input terminal of the second AND circuit 21. Therefore, when the input clock signal CK changes to a high level at time t3, the output signal Q2 output from the second AND circuit 21 becomes a high level.

[0052] As a result of the above, the low-level first internal clock signal Q1 is input to the reset terminal R of the RS latch circuit 30, and the high-level second internal clock signal Q2 is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a high level after time t3.

[0053] When half of the period T of the input clock signal CK has elapsed from time t3 and time t4 is reached, the operation is the same as the operation at time t1. That is, the output signal Q2 of the second AND circuit 21 becomes a low level at time t4. As a result of the above, the low-level first internal clock signal Q1 is input to the reset terminal R of the RS latch circuit 30, and the low-level second internal clock signal Q2 is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t4 and becomes a high level even after time t4.

[0054] After time t4, the same operation as the above-described operation is repeated. As a result, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period three times the period of the input clock signal CK and a duty ratio of 50%, as shown in FIG. 3. For example, focusing on the period from time t1 to time t5, the clock signal CKO becomes a low level during the period from time t1 to time t3, which is the first half of the period, and becomes a high level during the period from time t3 to time t5, which is the remaining half of the period. According to the above configuration, the frequency divider circuit 228 performs a three-division with an odd division ratio and the duty ratio of the clock signal becomes 50%.

[0055] Also, in FIG. 3, for example, as indicated by the signal in the period from time t1 to time t2, the second internal clock signal Q2 is at a low level during the period when the first internal clock signal Q1 is at a high level. Therefore, the second internal clock signal Q2 and the first internal clock signal Q1 do not simultaneously become high level and are not input to the RS latch circuit 30. In the RS latch circuit 30, an input in which both the reset terminal R and the set terminal S are at a high level is prohibited, but in this embodiment, a prohibited input signal is not input to the RS latch circuit 30.

[0056] (3) Second Embodiment The division ratio in the division circuit is not limited to 3. FIG. 4 is a block diagram showing the configuration of a division circuit 2281 that divides the input clock signal CK by a division ratio of 5 and outputs a clock signal CKO with a duty ratio of 50%. In FIG. 4, the same components as those in FIG. 2 are denoted by the same reference numerals.

[0057] The division circuit 2281 has a configuration in which a third D-type flip-flop circuit 16 is added to the division circuit 228. That is, in the internal clock generation circuit 101 included in the division circuit 2281, the output of the second D-type flip-flop circuit 12 included in the internal clock generation circuit 10 shown in FIG. 2 is configured to be input to the third D-type flip-flop circuit 16. Also, the output of the third D-type flip-flop circuit 16 is input to the first inverter circuit 14 and the second inverter circuit 15 as a feedback clock signal Q3. The input clock signal CK is input to the third D-type flip-flop circuit 16, and the third D-type flip-flop circuit 16 performs a latch operation in synchronization with the falling edge of the input clock signal CK.

[0058] FIG. 5 is a timing chart showing the signals of each part in the division circuit 2281. As shown in FIG. 5, the input clock signal CK input to the division circuit 2281 is a pulse signal with a constant period T. Also, the duty ratio of the input clock signal CK is 50%.

[0059] In the frequency division circuit 2281, an operation similar to that of the frequency division circuit 228 is performed. That is, the first internal clock signal Q1 in the frequency division circuit 2281 becomes a pulse signal with a period of 5T. In this sense, the input clock signal CK is divided by 5, but the duty ratio is not 50%. Therefore, a configuration is adopted in which the edge timing generation circuit 20 and the RS latch circuit 30 are used to generate a clock signal CKO with a duty ratio of 50%.

[0060] Here, a timing chart will be described focusing on the operation for making the duty ratio 50%. Specifically, the operation after time t7 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t7 in a state where the feedback clock signal Q3 output from the third D-type flip-flop circuit 16 is at a high level, the first inverter circuit 14 inverts the feedback clock signal Q3 to a low level state, which is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes a low level.

[0061] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a low level before time t7, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t7, the first internal clock signal Q1, which is the output of the second D-type flip-flop circuit 12, becomes a low level.

[0062] Furthermore, in this example, since the first internal clock signal Q1, which is the output of the second D-type flip-flop circuit 12, is at a high level before time t7, when the falling edge of the input clock signal CK is input to the third D-type flip-flop circuit 16 at time t7, the feedback clock signal Q3, which is the output of the third D-type flip-flop circuit 16, is at a high level.

[0063] Furthermore, at time t7, the signals input to the first AND circuit 13 are a low-level signal obtained by inverting the feedback clock signal Q3 by the second inverter circuit 15 and a low-level signal as the output signal Q0 of the first D flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes low level.

[0064] Furthermore, the signal input to the second AND circuit 21 is an inverted signal InvQ0 obtained by inverting the output signal Q0 of the first D flip-flop circuit 11 by the third inverter circuit 22. At time t7, since the inverted signal InvQ0 is at high level, the signals input to the second AND circuit 21 are the inverted signal InvQ0 at high level and a low-level signal after the falling edge of the input clock signal CK. Therefore, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, becomes low level. When half of the period T of the input clock signal CK has elapsed and the rising edge of the input clock signal CK occurs at time t8, since the inverted signal InvQ0 input to the second AND circuit 21 is at high level, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, becomes high level.

[0065] As a result of the above, at time t7, the low-level first internal clock signal Q1 is input to the reset terminal R of the RS latch circuit 30, and the low-level second internal clock signal Q2 is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t7 and becomes low level during the period from time t7 to t8.

[0066] On the other hand, at time t8, the low-level first internal clock signal Q1 is input to the reset terminal R of the RS latch circuit 30, and the high-level second internal clock signal Q2 is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, changes to high level at time t8.

[0067] In the operation after time t9, while the first internal clock signal Q1 input to the reset terminal R of the RS latch circuit 30 is at a low level, the output of the RS latch circuit 30 does not change regardless of whether the second internal clock signal Q2 is at a low level or a high level. Then, at time t10, when the first internal clock signal Q1 changes to a high level, the output of the RS latch circuit 30 is reset, and the clock signal CKO changes to a low level.

[0068] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period five times that of the input clock signal CK as shown in FIG. 5, and the duty ratio becomes 50%. For example, focusing on the period from time t6 to time t10, the clock signal CKO is at a low level during the period from time t6 to time t8, which is the first half of the period, and is at a high level during the period from time t8 to time t10, which is the remaining half of the period. According to the above configuration, the frequency divider circuit 2281 performs a five-frequency division with an odd division ratio, and the duty ratio of the clock signal becomes 50%.

[0069] Also, in FIG. 5, for example, as shown by the signal during the period from time t6 to time t10, the second internal clock signal Q2 is at a low level during the period when the first internal clock signal Q1 is at a high level. Therefore, the second internal clock signal Q2 and the first internal clock signal Q1 do not simultaneously become high levels and are input to the RS latch circuit 30. Therefore, in the present embodiment, a prohibited input signal is not input to the RS latch circuit 30.

[0070] (4) Third Embodiment FIG. 6 is a block diagram showing the configuration of a frequency divider circuit 2282 that divides the input clock signal CK by a division ratio of 7 and outputs a clock signal CKO having a duty ratio of 50%. In FIG. 6, the same components as those in FIG. 4 are denoted by the same reference numerals.

[0071] The frequency division circuit 2282 has a configuration in which a fourth D-type flip-flop circuit 17 is added to the frequency division circuit 2281. That is, in the internal clock generation circuit 102 included in the frequency division circuit 2282, the output of the third D-type flip-flop circuit 16 included in the internal clock generation circuit 101 shown in FIG. 4 is configured to be input to the fourth D-type flip-flop circuit 17. Further, the output of the fourth D-type flip-flop circuit 17 is input to the first inverter circuit 14 and the second inverter circuit 15 as a feedback clock signal Q4. The input clock signal CK is input to the fourth D-type flip-flop circuit 17, and the fourth D-type flip-flop circuit 17 performs a latch operation in synchronization with the falling edge of the input clock signal CK.

[0072] FIG. 7 is a timing chart showing signals of each part in the frequency division circuit 2282. As shown in FIG. 7, the input clock signal CK input to the frequency division circuit 2282 is a pulse signal with a constant period T. Further, the duty ratio of the input clock signal CK is 50%.

[0073] In the frequency division circuit 2282, an operation similar to that of the frequency division circuits 228 and 2281 is also performed. That is, the first internal clock signal Q1 in the frequency division circuit 2282 becomes a pulse signal with a period of 7T. In this sense, the input clock signal CK is divided by 7, but the duty ratio is not 50%. Therefore, a configuration is adopted in which a clock signal CKO with a duty ratio of 50% is generated by using the edge timing generation circuit 20 and the RS latch circuit 30.

[0074] Here, the timing chart will be described by focusing on the operation for setting the duty ratio to 50%. Specifically, the operation after time t12 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t12 in a state where the feedback clock signal Q4 output from the fourth D-type flip-flop circuit 17 is at a high level, the first inverter circuit 14 inverts the feedback clock signal Q4 to a low level state, which is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes a low level.

[0075] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a low level before time t12, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t12, the first internal clock signal Q1, which is the output of the second D-type flip-flop circuit 12, becomes a low level.

[0076] Furthermore, in this example, since the first internal clock signal Q1, which is the output of the second D-type flip-flop circuit 12, is at a high level before time t12, when the falling edge of the input clock signal CK is input to the third D-type flip-flop circuit 16 at time t12, the output signal Q3 of the third D-type flip-flop circuit 16 is at a high level.

[0077] Furthermore, in this example, since the output signal Q3 of the third D-type flip-flop circuit 16 is at a high level before time t12, when the falling edge of the input clock signal CK is input to the fourth D-type flip-flop circuit 17 at time t12, the feedback clock signal Q4, which is the output signal of the fourth D-type flip-flop circuit 17, is at a high level.

[0078] Furthermore, at time t12, the signals input to the first AND circuit 13 are the low-level signal obtained by inverting the feedback clock signal Q4 by the second inverter circuit 15 and the low-level signal as the output signal Q0 of the first D flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes low level.

[0079] Furthermore, the signal input to the second AND circuit 21 is the inverted signal InvQ0 obtained by inverting the output signal Q0 of the first D flip-flop circuit 11 by the third inverter circuit 22. At time t12, since the inverted signal InvQ0 is at high level, the signals input to the second AND circuit 21 are the inverted signal InvQ0 at high level and the low-level signal after the falling edge of the input clock signal CK. Therefore, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, becomes low level. When half of the period T of the input clock signal CK has elapsed and the rising edge of the input clock signal CK occurs at time t13, since the inverted signal InvQ0 input to the second AND circuit 21 is at high level, the second internal clock signal Q2, which is the output signal of the second AND circuit 21, becomes high level.

[0080] As a result of the above, at time t12, the first internal clock signal Q1 at low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q2 at low level is input to the set terminal S. For this reason, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t12 and becomes low level during the period from time t12 to t13.

[0081] On the other hand, at time t13, the first internal clock signal Q1 at low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q2 at high level is input to the set terminal S. For this reason, the clock signal CKO, which is the output of the RS latch circuit 30, changes to high level at time t13.

[0082] In the operation after time t14, while the first internal clock signal Q1 input to the reset terminal R of the RS latch circuit 30 is at a low level, the output of the RS latch circuit 30 does not change regardless of whether the second internal clock signal Q2 is at a low level or a high level. Then, at time t15, when the first internal clock signal Q1 changes to a high level, the output of the RS latch circuit 30 is reset and the clock signal CKO changes to a low level.

[0083] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period seven times that of the input clock signal CK's period T, as shown in FIG. 7, and the duty ratio becomes 50%. For example, focusing on the period from time t11 to time t15, the clock signal CKO is at a low level during the period from time t11 to time t13, which is the first half of the period, and is at a high level during the period from time t13 to time t15, which is the remaining half of the period. According to the above configuration, the frequency divider circuit 2282 performs a 7 - division with an odd division ratio, and the duty ratio of the clock signal becomes 50%.

[0084] Also, in FIG. 7, for example, as shown by the signal during the period from time t11 to time t15, the second internal clock signal Q2 is at a low level during the period when the first internal clock signal Q1 is at a high level. Therefore, the second internal clock signal Q2 and the first internal clock signal Q1 do not simultaneously become high levels and are input to the RS latch circuit 30. Thus, in this embodiment, no prohibited input signal is input to the RS latch circuit 30.

[0085] (5) Fourth Embodiment Furthermore, the division ratio in the frequency divider circuit may be selectable. FIG. 8 is a block diagram showing the configuration of a frequency divider circuit 2283 that can select any one of division ratios 3, 5, and 7. In FIG. 8, the same components as those in FIG. 6 are denoted by the same reference numerals.

[0086] The frequency division circuit 2283 has a configuration in which a selector 18 is added to the frequency division circuit 2282. That is, in the internal clock generation circuit 103 included in the frequency division circuit 2283, the outputs of the second D-type flip-flop circuit 12, the third D-type flip-flop circuit 16, and the fourth D-type flip-flop circuit 17 are input to the selector 18. The selector 18 outputs one of the signals input to the selector 18 based on the DIV_setteing signal input from the outside.

[0087] Also, the output of the selector 18 is input to the first inverter circuit 14 and the second inverter circuit 15. Therefore, the selector 18 is a circuit that inputs one of the feedback clock signals Q1, Q3, Q4 to the first inverter circuit 14 and the second inverter circuit 15 based on the DIV_setteing signal. That is, the frequency division circuit 2283 is a circuit that divides the input clock signal CK at a frequency division ratio of 3, 5, or 7 according to the DIV_setteing signal. Note that the DIV_setteing signal may be any signal input from the outside of the frequency division circuit 2283. For example, a configuration in which the DIV_setteing signal is supplied from the frequency division ratio generation circuit 260 to the frequency division circuit 2283 according to the data stored in the register 251 can be adopted. According to the above configuration, a desired frequency division ratio can be selected from the frequency division ratios that can be realized in the frequency division circuit 2283 and divided.

[0088] Note that the frequency division circuit capable of selecting the frequency division ratio is not limited to the configuration shown in FIG. 8, and the number of selectable frequency division ratios may be two or four or more. That is, a frequency division circuit may be configured that includes a selector that inputs a plurality of signals including the output signals of the j-th and k-th (j and k are integers of 2 or more and n or less, and j≠k) flip-flop circuits and operates the frequency division circuit at any of a plurality of frequency division ratios including (2j - 1) and (2k - 1).

[0089] (6) Fifth Embodiment Furthermore, in the frequency division circuit, the internal clock generation circuit 10 and the edge timing generation circuit 20 may be circuits different from the configurations shown in FIG. 2. FIG. 9 shows a frequency division circuit 2284 realized by a configuration in which the internal clock generation circuit 10 shown in FIG. 2 is changed to an internal clock generation circuit 104 and the edge timing generation circuit 20 is changed to an edge timing generation circuit 204. In the frequency division circuit 2284, an input clock signal CK is divided by a division ratio of 3, and a clock signal CKO with a duty ratio of 50% is output. In FIG. 9, the same components as those in FIG. 2 are denoted by the same reference numerals.

[0090] The internal clock generation circuit 104 of the frequency division circuit 2284 has a configuration in which a third inverter circuit 19 is added to the internal clock generation circuit 10 shown in FIG. 2. The output signal Q0 of the first D flip-flop circuit 11 is input to the third inverter circuit 19, and the inverted signal InvQ0, which is the output signal of the third inverter circuit 19, is input to the reset terminal R of the RS latch circuit 30. Therefore, the inverted signal InvQ0 is the first internal clock signal.

[0091] The edge timing generation circuit 204 of the frequency division circuit 2284 includes a second AND circuit 214. In the second AND circuit 214, the input clock signal CK is input to one input terminal, and the output signal D1 of the first AND circuit 13 is input to the other input terminal.

[0092] FIG. 10 is a timing chart showing the signals of each part in the frequency division circuit 2284. In the frequency division circuit 2284, since the internal clock generation circuit 104 has the same configuration as that shown in FIG. 2 except for the third inverter circuit 19, the input clock signal CK, the output signals Q0, D1, and the feedback clock signal Q1 have the same operations as those in FIG. 3. Since the inverted signal InvQ0 is the inverted signal of the output signal Q0, the inverted signal InvQ0 also has the same operation as that in FIG. 3.

[0093] In the frequency division circuit 2284, an operation similar to that of the frequency division circuit 228 is performed. That is, the inverted signal InvQ0, which is the first internal clock signal generated in the frequency division circuit 2284, becomes a pulse signal with a period of 3T. In this sense, the input clock signal CK is divided by 3, but the duty ratio is not 50%. Therefore, a configuration is adopted in which the edge timing generation circuit 204 and the RS latch circuit 30 are used to generate a clock signal CKO with a duty ratio of 50%.

[0094] Here, the timing chart will be described focusing on the operation for making the duty ratio 50%. Specifically, the operation after time t16 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t16 in a state where the feedback clock signal Q1 output from the second D-type flip-flop circuit 12 is at a low level, the high-level state in which the feedback clock signal Q1 is inverted by the first inverter circuit 14 is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes high level.

[0095] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a low level before time t16, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t16, the feedback clock signal Q1, which is the output of the second D-type flip-flop circuit 12, becomes low level.

[0096] Furthermore, at time t16, the signals input to the first AND circuit 13 are a high-level signal in which the feedback clock signal Q1 is inverted by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D-type flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes high level.

[0097] Furthermore, an inverted signal InvQ0 obtained by inverting the output signal Q0 of the first D-type flip-flop circuit 11 is input to the reset terminal R of the RS latch circuit 30 by the third inverter circuit 19. Therefore, at time t16, a low level is input to the reset terminal R of the RS latch circuit 30.

[0098] The signals input to the second AND circuit 214 are the output signal D1 of the first AND circuit 13 and the input clock signal CK. Therefore, the second internal clock signal Q24, which is the output signal of the second AND circuit 214, is at a low level during the period from time t16 to time t17 when the input clock signal CK is at a low level. On the other hand, during the period from time t17 to time t18 when the input clock signal CK is at a high level, the second internal clock signal Q24 becomes high level.

[0099] Since the second internal clock signal Q24 is input to the set terminal S of the RS latch circuit 30, during the period from time t16 to time t17, a signal at a low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q2 at a low level is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t16 and becomes low level during the period from time t16 to time t17.

[0100] On the other hand, at time t17, an inverted signal InvQ0 at a low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q24 at a high level is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, changes to a high level at time t17.

[0101] In the operation after time t18, while the inverted signal InvQ0 input to the reset terminal R of the RS latch circuit 30 is at the low level, the output of the RS latch circuit 30 does not change regardless of whether the second internal clock signal Q24 is at the low level or the high level. Then, at time t19, when the inverted signal InvQ0 changes to the high level, the output of the RS latch circuit 30 is reset and the clock signal CKO changes to the low level.

[0102] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period three times that of the input clock signal CK as shown in FIG. 10, and the duty ratio becomes 50%. For example, focusing on the period from time t17 to time t20, the clock signal CKO is at the high level during the first half period, i.e., from time t17 to time t19, and at the low level during the remaining half period, i.e., from time t19 to time t20. According to the above configuration, the frequency divider circuit 2284 performs a three-frequency division with an odd division ratio, and the duty ratio of the clock signal becomes 50%.

[0103] Also, in FIG. 10, for example, as shown by the signal during the period from time t17 to time t20, the second internal clock signal Q24 is at the low level during the period when the inverted signal InvQ0 is at the high level. Therefore, the second internal clock signal Q2 and the inverted signal InvQ0 do not simultaneously become high level and are input to the RS latch circuit 30. Therefore, in this embodiment, no prohibited input signal is input to the RS latch circuit 30.

[0104] (7) Sixth Embodiment Furthermore, the division ratio of the frequency divider is not limited to 3. FIG. 11 shows a frequency divider circuit 2285 realized by a configuration in which the internal clock generation circuit 104 shown in FIG. 9 is changed to an internal clock generation circuit 105. In the frequency divider circuit 2285, the input clock signal CK is divided by a division ratio of 5, and a clock signal CKO with a duty ratio of 50% is output. In FIG. 11, the same components as those in FIG. 9 are denoted by the same reference numerals.

[0105] The internal clock generation circuit 105 of the frequency division circuit 2285 has a configuration in which a third D-type flip-flop circuit 16 is added to the internal clock generation circuit 104 shown in FIG. 9. The output of the second D-type flip-flop circuit 12 is input to the third D-type flip-flop circuit 16. Further, the output of the third D-type flip-flop circuit 16 is input to the first inverter circuit 14 and the second inverter circuit 15 as a feedback clock signal Q3. The input clock signal CK is input to the third D-type flip-flop circuit 16, and the third D-type flip-flop circuit 16 performs a latch operation in synchronization with the falling edge of the input clock signal CK.

[0106] FIG. 12 is a timing chart showing the signals of each part in the frequency division circuit 2285. In the frequency division circuit 2285, since the internal clock generation circuit 105 has the same configuration as that shown in FIG. 4 except for the third inverter circuit 19, the input clock signal CK, the output signal Q0, D1, Q1, and the feedback clock signal Q3 have the same operation as in FIG. 5. Since the inverted signal InvQ0 is the inverted signal of the output signal Q0, the inverted signal InvQ0 also has the same operation as in FIG. 5.

[0107] In the frequency division circuit 2285, an operation similar to that of the frequency division circuit 2281 is performed. That is, the inverted signal InvQ0, which is the first internal clock signal generated in the frequency division circuit 2285, becomes a pulse signal with a period of 5T. In this sense, the input clock signal CK is divided by 5, but the duty ratio is not 50%. Therefore, a configuration is adopted in which a clock signal CKO with a duty ratio of 50% is generated by using the edge timing generation circuit 204 and the RS latch circuit 30.

[0108] Here, a timing chart will be described by focusing on the operation for setting the duty ratio to 50%. Specifically, the operation after time t21 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t21 in a state where the feedback clock signal Q3 output from the third D-type flip-flop circuit 16 is at a low level, the high-level state in which the feedback clock signal Q3 is inverted by the first inverter circuit 14 is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes high level.

[0109] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a low level before time t21, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t21, the output signal Q1 of the second D-type flip-flop circuit 12 becomes low level.

[0110] Furthermore, in this example, since the output signal Q1 of the second D-type flip-flop circuit 12 is at a low level before time t21, when the falling edge of the input clock signal CK is input to the third D-type flip-flop circuit 16 at time t21, the feedback clock signal Q3, which is the output signal of the third D-type flip-flop circuit 16, becomes low level.

[0111] Furthermore, at time t21, the signal input to the first AND circuit 13 is a high-level signal in which the feedback clock signal Q3 is inverted by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D-type flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes high level.

[0112] Furthermore, an inverted signal InvQ0 obtained by inverting the output signal Q0 of the first D-type flip-flop circuit 11 is input to the reset terminal R of the RS latch circuit 30 by the third inverter circuit 19. Therefore, at time t21, a low level is input to the reset terminal R of the RS latch circuit 30.

[0113] The signals input to the second AND circuit 214 are the output signal D1 of the first AND circuit 13 and the input clock signal CK. Therefore, the second internal clock signal Q24, which is the output signal of the second AND circuit 214, is at a low level during the period from time t21 to time t22 when the input clock signal CK is at a low level. On the other hand, during the period from time t22 to time t23 when the input clock signal CK is at a high level, the second internal clock signal Q24 becomes high level.

[0114] Since the second internal clock signal Q24 is input to the set terminal S of the RS latch circuit 30, during the period from time t21 to time t22, a signal of low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q24 of low level is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t21 and becomes low level during the period from time t21 to time t22.

[0115] On the other hand, at time t22, an inverted signal InvQ0 of low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q24 of high level is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, changes to high level at time t22.

[0116] In the operation after time t23, while the inverted signal InvQ0 input to the reset terminal R of the RS latch circuit 30 is at the low level, the output of the RS latch circuit 30 does not change regardless of whether the second internal clock signal Q24 is at the low level or the high level. Then, at time t24, when the inverted signal InvQ0 changes to the high level, the output of the RS latch circuit 30 is reset and the clock signal CKO changes to the low level.

[0117] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period five times that of the input clock signal CK's period T as shown in FIG. 12, and the duty ratio becomes 50%. For example, focusing on the period from time t22 to time t25, the clock signal CKO is at the high level during the period from time t22 to time t24, which is the first half of the period, and is at the low level during the period from time t24 to time t25, which is the remaining half of the period. According to the above configuration, the frequency division circuit 2285 performs frequency division with an odd division ratio of 5 division, and the duty ratio of the clock signal becomes 50%.

[0118] Also, in FIG. 12, for example, as shown by the signal during the period from time t22 to time t25, the second internal clock signal Q24 is at the low level during the period when the inverted signal InvQ0 is at the high level. For this reason, the second internal clock signal Q24 and the inverted signal InvQ0 do not simultaneously become high level and are input to the RS latch circuit 30. Therefore, in the present embodiment, a prohibited input signal is not input to the RS latch circuit 30.

[0119] (8) Seventh Embodiment FIG. 13 shows a frequency division circuit 2286 realized by a configuration in which the internal clock generation circuit 105 shown in FIG. 11 is changed to an internal clock generation circuit 106. In the frequency division circuit 2286, the input clock signal CK is frequency-divided by a division ratio of 7, and a clock signal CKO with a duty ratio of 50% is output. In FIG. 13, the same components as those in FIG. 11 are denoted by the same reference numerals.

[0120] The internal clock generation circuit 106 of the frequency division circuit 2286 has a configuration in which a fourth D-type flip-flop circuit 17 is added to the internal clock generation circuit 105 shown in FIG. 11. The output of the third D-type flip-flop circuit 16 is input to the fourth D-type flip-flop circuit 17. Further, the output of the fourth D-type flip-flop circuit 17 is input to the first inverter circuit 14 and the second inverter circuit 15 as a feedback clock signal Q4. The input clock signal CK is input to the fourth D-type flip-flop circuit 17, and the fourth D-type flip-flop circuit 17 performs a latching operation in synchronization with the falling edge of the input clock signal CK.

[0121] FIG. 14 is a timing chart showing signals of each part in the frequency division circuit 2286. In the frequency division circuit 2286, since the internal clock generation circuit 106 has the same configuration as that shown in FIG. 6 except for the third inverter circuit 19, the input clock signal CK, the output signals Q0, D1, Q1, Q3, and the feedback clock signal Q4 have the same operations as those in FIG. 7. Since the inverted signal InvQ0 is the inverted signal of the output signal Q0, the inverted signal InvQ0 also has the same operation as that in FIG. 7.

[0122] In the frequency division circuit 2286, an operation similar to that of the frequency division circuit 2282 is performed. That is, the inverted signal InvQ0, which is the first internal clock signal generated in the frequency division circuit 2286, becomes a pulse signal with a period of 7T. In this sense, the input clock signal CK is divided by 7, but the duty ratio is not 50%. Therefore, a configuration is adopted in which a clock signal CKO with a duty ratio of 50% is generated by using the edge timing generation circuit 204 and the RS latch circuit 30.

[0123] Here, the timing chart will be described by focusing on the operation for setting the duty ratio to 50%. Specifically, the operation after time t26 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t26 in a state where the feedback clock signal Q4 output from the fourth D-type flip-flop circuit 17 is at a low level, the high-level state in which the feedback clock signal Q4 is inverted by the first inverter circuit 14 is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes high level.

[0124] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a low level before time t26, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t26, the output signal Q1 of the second D-type flip-flop circuit 12 becomes low level.

[0125] Furthermore, in this example, since the output signal Q1 of the second D-type flip-flop circuit 12 is at a low level before time t26, when the falling edge of the input clock signal CK is input to the third D-type flip-flop circuit 16 at time t26, the feedback clock signal Q4, which is the output signal of the third D-type flip-flop circuit 16, becomes low level.

[0126] Furthermore, in this example, since the output signal Q3 of the third D-type flip-flop circuit 16 is at a low level before time t26, when the falling edge of the input clock signal CK is input to the fourth D-type flip-flop circuit 17 at time t26, the feedback clock signal Q4, which is the output signal of the fourth D-type flip-flop circuit 17, becomes low level.

[0127] Furthermore, at time t26, the signal input to the first AND circuit 13 is a high-level signal obtained by inverting the feedback clock signal Q4 by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes high level.

[0128] Furthermore, an inverted signal InvQ0 obtained by inverting the output signal Q0 of the first D flip-flop circuit 11 is input to the reset terminal R of the RS latch circuit 30 by the third inverter circuit 19. For this reason, at time t26, a low level is input to the reset terminal R of the RS latch circuit 30.

[0129] The signals input to the second AND circuit 214 are the output signal D1 of the first AND circuit 13 and the input clock signal CK. Therefore, the second internal clock signal Q24, which is the output signal of the second AND circuit 214, is low level during the period from time t26 to time t27 when the input clock signal CK is low level. On the other hand, during the period from time t27 to time t28 when the input clock signal CK is high level, the second internal clock signal Q24 becomes high level.

[0130] Since the second internal clock signal Q24 is input to the set terminal S of the RS latch circuit 30, during the period from time t26 to time t27, a low-level signal is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q24, which is low level, is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t26 and becomes low level during the period from time t26 to time t27.

[0131] On the other hand, at time t27, an inverted signal InvQ0, which is low level, is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q24, which is high level, is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, changes to high level at time t27.

[0132] In the operation after time t28, while the inverted signal InvQ0 input to the reset terminal R of the RS latch circuit 30 is at the low level, the output of the RS latch circuit 30 does not change regardless of whether the second internal clock signal Q24 is at the low level or the high level. Then, at time t29, when the inverted signal InvQ0 changes to the high level, the output of the RS latch circuit 30 is reset, and the clock signal CKO changes to the low level.

[0133] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period 7 times that of the period T of the input clock signal CK, as shown in FIG. 14, and the duty ratio becomes 50%. For example, focusing on the period from time t27 to time t30, the clock signal CKO is at the high level during the period from time t27 to time t29, which is the first half of the period, and is at the low level during the period from time t29 to time t30, which is the remaining half of the period. According to the above configuration, the frequency divider circuit 2286 performs a 7 - division with an odd division ratio, and the duty ratio of the clock signal becomes 50%.

[0134] Also, in FIG. 14, for example, as shown by the signal during the period from time t27 to time t30, the second internal clock signal Q24 is at the low level during the period when the inverted signal InvQ0 is at the high level. Therefore, the second internal clock signal Q24 and the inverted signal InvQ0 do not simultaneously become high level and are input to the RS latch circuit 30. Thus, in the present embodiment, a prohibited input signal is not input to the RS latch circuit 30.

[0135] (9) Eighth Embodiment Furthermore, in the frequency division circuit, the edge timing generation circuit 20 may be a circuit different from the configuration shown in FIG. 2. FIG. 15 shows a frequency division circuit 2287 realized by a configuration in which the edge timing generation circuit 20 shown in FIG. 2 is changed to an edge timing generation circuit 207. In the frequency division circuit 2287, an input clock signal CK is divided by a division ratio of 3, and a clock signal CKO with a duty ratio of 50% is output. In FIG. 9, the same components as those in FIG. 2 are denoted by the same reference numerals.

[0136] The internal clock generation circuit 10 of the frequency division circuit 2287 has the same circuit configuration as the internal clock generation circuit 10 shown in FIG. 2. However, in the frequency division circuit 2287, the output of the first AND circuit 13 is input to the reset terminal R of the RS latch circuit 30. Therefore, in the frequency division circuit 2287, the output signal D1 output from the first AND circuit 13 is the first internal clock signal.

[0137] The edge timing generation circuit 207 of the frequency division circuit 2287 includes a second AND circuit 217. In the second AND circuit 217, the input clock signal CK is input to one input terminal, and the output signal Q1 of the second D flip-flop circuit 12 is input to the other input terminal.

[0138] FIG. 16 is a timing chart showing the signals of each part in the frequency division circuit 2287. In the frequency division circuit 2287, since the internal clock generation circuit 10 is the same as the frequency division circuit 228 shown in FIG. 2, the input clock signal CK, the output signals Q0, D1, and the feedback clock signal Q1 have the same operations as those in FIG. 3.

[0139] In the frequency division circuit 2287, an operation similar to that of the frequency division circuit 228 is performed. That is, the output signal D1, which is the first internal clock signal generated in the frequency division circuit 2287, becomes a pulse signal with a period of 3T. In this sense, the input clock signal CK is divided by 3, but the duty ratio is not 50%. Therefore, a configuration is adopted in which an edge timing generation circuit 207 and an RS latch circuit 30 are used to generate a clock signal CKO with a duty ratio of 50%.

[0140] Here, a timing chart will be described focusing on the operation for making the duty ratio 50%. Specifically, the operation after time t31 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t31 in a state where the feedback clock signal Q1 output from the second D-type flip-flop circuit 12 is at a low level, the high-level state in which the feedback clock signal Q1 is inverted by the first inverter circuit 14 is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes high level.

[0141] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a high level before time t31, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t31, the feedback clock signal Q1, which is the output of the second D-type flip-flop circuit 12, becomes high level.

[0142] Furthermore, at time t31, the signal input to the first AND circuit 13 is a low-level signal in which the feedback clock signal Q1 is inverted by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D-type flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes low level. The said output signal D1 is input to the reset terminal R of the RS latch circuit 30. For this reason, at time t31, a low level is input to the reset terminal R of the RS latch circuit 30.

[0143] The signals input to the second AND circuit 217 are the output signal Q1 of the second D flip-flop circuit 12 and the input clock signal CK. Since the output signal Q1 of the second D flip-flop circuit 12 is at a high level during the period from time t31 to time t33, the second internal clock signal Q27, which is the output signal of the second AND circuit 217, is at a low level during the period from time t31 to time t32 when the input clock signal CK is at a low level. On the other hand, during the period from time t32 to time t33 when the input clock signal CK is at a high level, the second internal clock signal Q27 becomes a high level.

[0144] Since the second internal clock signal Q27 is input to the set terminal S of the RS latch circuit 30, during the period from time t31 to time t32, a signal at a low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q27 at a low level is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, maintains the state before time t31 and becomes a low level during the period from time t31 to time t32.

[0145] On the other hand, at time t32, the output signal D1 at a low level is input to the reset terminal R of the RS latch circuit 30, and the second internal clock signal Q27 at a high level is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 30, changes to a high level at time t32.

[0146] In the operation after time t33, as long as the output signal D1 input to the reset terminal R of the RS latch circuit 30 is at a low level, the output of the RS latch circuit 30 does not change regardless of whether the second internal clock signal Q27 is at a low level or a high level. Then, at time t34, when the output signal D1 changes to a high level, the output of the RS latch circuit 30 is reset and the clock signal CKO changes to a low level.

[0147] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 30, becomes a clock signal having a period three times that of the input clock signal CK as shown in FIG. 16, and the duty ratio becomes 50%. For example, focusing on the period from time t32 to time t35, the clock signal CKO is at a high level during the first half period, i.e., from time t32 to time t34, and at a low level during the remaining half period, i.e., from time t34 to time t35. According to the above configuration, the frequency division circuit 2287 performs frequency division with an odd frequency division ratio of 3 and the duty ratio of the clock signal becomes 50%.

[0148] Also, in FIG. 16, for example, as indicated by the signal during the period from time t32 to time t35, the second internal clock signal Q27 is at a low level during the period when the output signal D1 is at a high level. Therefore, the second internal clock signal Q27 and the output signal D1 do not simultaneously become high level and are not input to the RS latch circuit 30. Accordingly, in the present embodiment, a prohibited input signal is not input to the RS latch circuit 30.

[0149] (10) Ninth Embodiment FIG. 17 shows a frequency division circuit 2288 realized by a configuration in which the edge timing generation circuit 20 shown in FIG. 4 is changed to an edge timing generation circuit 208 and the RS latch circuit 30 is changed to an RS latch circuit 308. In the frequency division circuit 2288, the input clock signal CK is frequency-divided with a frequency division ratio of 5, and a clock signal CKO with a duty ratio of 50% is output. In FIG. 17, the same components as those in FIG. 4 are denoted by the same reference numerals.

[0150] The internal clock generation circuit 101 of the frequency division circuit 2288 has the same circuit configuration as the internal clock generation circuit 101 shown in FIG. 4. However, in the frequency division circuit 2288, the output of the first AND circuit 13 is input to the reset terminal R of the RS latch circuit 308. Therefore, in the frequency division circuit 2288, the output signal D1 output from the first AND circuit 13 is the first internal clock signal.

[0151] The edge timing generation circuit 207 of the frequency division circuit 2288 includes a second AND circuit 218. In the second AND circuit 218, an input clock signal CK is input to one input terminal, and the output signal Q1 of the second D flip-flop circuit 12 is input to the other input terminal.

[0152] The RS latch circuit 308 of the frequency division circuit 2288 is an RS latch circuit with reset priority. That is, in the RS latch circuit 308, when the reset terminal R and the set terminal S are both at the high level at the same time, the operation corresponding to the reset terminal R being at the high level takes precedence. As a result, when the reset terminal R and the set terminal S of the RS latch circuit 308 are both at the high level at the same time, the output becomes the low level.

[0153] FIG. 18 is a timing chart showing the signals of each part in the frequency division circuit 2288. In the frequency division circuit 2288, since the internal clock generation circuit 101 has the same configuration as that shown in FIG. 4, the input clock signal CK, the output signals Q0, D1, Q1, and the feedback clock signal Q3 have the same operations as those in FIG. 5.

[0154] In the frequency division circuit 2288, an operation similar to that of the frequency division circuit 2281 is also performed. That is, the output signal D1, which is the first internal clock signal generated in the frequency division circuit 2288, becomes a pulse signal with a period of 5T. In this sense, the input clock signal CK is divided by 5, but the duty ratio is not 50%. Therefore, a configuration is adopted in which a clock signal CKO with a duty ratio of 50% is generated by using the edge timing generation circuit 208 and the RS latch circuit 308.

[0155] Here, a timing chart will be described by focusing on the operation for setting the duty ratio to 50%. Specifically, the operation after time t36 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t36 in a state where the feedback clock signal Q3 output from the third D-type flip-flop circuit 16 is at a low level, the high-level state in which the feedback clock signal Q3 is inverted by the first inverter circuit 14 is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes high level.

[0156] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a high level before time t36, when the falling edge of the input clock signal CK is input to the second D-type flip-flop circuit 12 at time t36, the output signal Q1 of the second D-type flip-flop circuit 12 becomes high level.

[0157] Furthermore, in this example, since the output signal Q1 of the second D-type flip-flop circuit 12 is at a low level before time t36, when the falling edge of the input clock signal CK is input to the third D-type flip-flop circuit 16 at time t36, the feedback clock signal Q3, which is the output signal of the third D-type flip-flop circuit 16, becomes low level.

[0158] Furthermore, at time t36, the signal input to the first AND circuit 13 is a high-level signal in which the feedback clock signal Q3 is inverted by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D-type flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes high level. The output signal D1 is input to the reset terminal R of the RS latch circuit 308. For this reason, a high level is input to the reset terminal R of the RS latch circuit 308 at time t36.

[0159] The signals input to the second AND circuit 218 are the output signal Q1 of the second D flip-flop circuit 12 and the input clock signal CK. During the period from time t36 to time t37, the output signal Q1 of the second D flip-flop circuit 12 is at a high level, but since the input clock signal CK is at a low level, the second internal clock signal Q27, which is the output signal of the second AND circuit 218, is at a low level. On the other hand, during the period from time t37 to time t38 when the input clock signal CK is at a high level, the second internal clock signal Q27 becomes a high level.

[0160] Since the second internal clock signal Q27 is input to the set terminal S of the RS latch circuit 308, during the period from time t36 to time t37, a high-level signal is input to the reset terminal R of the RS latch circuit 308, and the second internal clock signal Q27, which is at a low level, is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 308, becomes a low level.

[0161] On the other hand, during the period from time t37 to time t38, a high-level signal is input to the reset terminal R of the RS latch circuit 308, and the second internal clock signal Q27, which is at a high level, is input to the set terminal S. That is, the reset terminal R and the set terminal S become high levels at the same time, but since the RS latch circuit 308 has reset priority, the clock signal CKO, which is the output of the RS latch circuit 308, becomes a low level during the period from time t37 to time t38.

[0162] At time t38, when the falling edge of the input clock signal CK is input to the third D flip-flop circuit 16, the third D flip-flop circuit 16 latches the output signal Q1, which is at a high level, and becomes a high level. When the high-level feedback clock signal Q3 is input to the second inverter circuit 15, the inverted and output low-level signal is input to the first AND circuit 13. As a result, the output signal D1 of the first AND circuit 13 becomes a low level.

[0163] At time t38, a high-level output signal Q1 and a low-level input clock signal CK are input to the second AND circuit 218. Therefore, the second internal clock signal Q27 output from the second AND circuit 218 becomes low level. As a result, an output signal D1 which is low level is input to the reset terminal R of the RS latch circuit 308, and the second internal clock signal Q27 which is low level is input to the set terminal S. Therefore, the clock signal CKO output from the RS latch circuit 308 becomes low level.

[0164] On the other hand, at time t39, when the rising edge of the input clock signal CK is input to the second AND circuit 218, a high-level output signal Q1 and a high-level input clock signal CK are input to the second AND circuit 218. Therefore, the second internal clock signal Q27 output from the second AND circuit 218 becomes high level. As a result, an output signal D1 which is low level is input to the reset terminal R of the RS latch circuit 308, a high-level input clock signal CK is input to the set terminal S, and the clock signal CKO output from the RS latch circuit 308 becomes high level.

[0165] In the operation after time t39, as long as the output signal D1 input to the reset terminal R of the RS latch circuit 308 is low level, the output of the RS latch circuit 308 does not change regardless of whether the second internal clock signal Q27 is low level or high level. Then, at time t40, when the output signal D1 changes to high level, the output of the RS latch circuit 308 is reset and the clock signal CKO changes to low level.

[0166] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 308, becomes a clock signal having a period five times that of the input clock signal CK's period T, as shown in FIG. 18, and has a duty ratio of 50%. For example, focusing on the period from time t39 to time t41, the clock signal CKO is at a high level during the first half period, i.e., from time t39 to time t40, and at a low level during the remaining half period, i.e., from time t40 to time t41. According to the above configuration, the frequency division circuit 2288 performs frequency division with an odd division ratio of 5, and the duty ratio of the clock signal becomes 50%.

[0167] (11) Tenth Embodiment FIG. 19 shows a frequency division circuit 2289 realized by a configuration in which the edge timing generation circuit 20 shown in FIG. 6 is changed to an edge timing generation circuit 209 and the RS latch circuit 30 is changed to an RS latch circuit 308. In the frequency division circuit 2289, the input clock signal CK is divided by a division ratio of 7, and a clock signal CKO with a duty ratio of 50% is output. In FIG. 19, the same components as those in FIG. 6 are denoted by the same reference numerals.

[0168] The internal clock generation circuit 102 of the frequency division circuit 2289 has the same circuit configuration as the internal clock generation circuit 102 shown in FIG. 6. However, in the frequency division circuit 2289, the output of the first AND circuit 13 is input to the reset terminal R of the RS latch circuit 308. Therefore, in the frequency division circuit 2289, the output signal D1 output from the first AND circuit 13 is the first internal clock signal.

[0169] The edge timing generation circuit 209 of the frequency division circuit 2289 includes a second AND circuit 219. In the second AND circuit 219, the input clock signal CK is input to one input terminal, and the output signal Q1 of the second D flip-flop circuit 12 is input to the other input terminal.

[0170] The RS latch circuit 308 of the frequency division circuit 2289 is a reset-priority RS latch circuit. That is, in the RS latch circuit 308, when the reset terminal R and the set terminal S are both at the high level at the same time, the operation corresponding to the reset terminal R being at the high level is prioritized. As a result, when the reset terminal R and the set terminal S of the RS latch circuit 308 are both at the high level at the same time, the output becomes the low level.

[0171] FIG. 20 is a timing chart showing signals of each part in the frequency division circuit 2289. In the frequency division circuit 2289, since the internal clock generation circuit 102 has the same configuration as that shown in FIG. 6, the input clock signal CK, the output signals Q0, D1, Q1, Q3, and the feedback clock signal Q4 have the same operation as in FIG. 7.

[0172] In the frequency division circuit 2289, an operation similar to that of the frequency division circuit 2282 is also performed. That is, the output signal D1, which is the first internal clock signal generated in the frequency division circuit 2289, becomes a pulse signal with a period of 7T. In this sense, the input clock signal CK is divided by 7, but the duty ratio is not 50%. Therefore, a configuration is adopted in which the edge timing generation circuit 209 and the RS latch circuit 308 are used to generate a clock signal CKO with a duty ratio of 50%.

[0173] Here, the timing chart will be described by focusing on the operation for making the duty ratio 50%. Specifically, the operation after time t42 will be described. When the falling edge of the input clock signal CK is input to the first D-type flip-flop circuit 11 at time t42 in a state where the feedback clock signal Q4 output from the fourth D-type flip-flop circuit 17 is at the low level, the high-level state in which the feedback clock signal Q4 is inverted by the first inverter circuit 14 is latched in the first D-type flip-flop circuit 11. As a result, the output signal Q0 of the first D-type flip-flop circuit 11 becomes the high level.

[0174] Also, in this example, since the output signal D1 of the first AND circuit 13 is at a high level before time t42, when the falling edge of the input clock signal CK is input to the second D flip-flop circuit 12 at time t42, the output signal Q1 of the second D flip-flop circuit 12 becomes high level.

[0175] Furthermore, in this example, since the output signal Q1 of the second D flip-flop circuit 12 is at a low level before time t42, when the falling edge of the input clock signal CK is input to the third D flip-flop circuit 16 at time t42, the output signal Q3 of the third D flip-flop circuit 16 becomes low level.

[0176] Furthermore, in this example, since the output signal Q3 of the third D flip-flop circuit 16 is at a low level before time t42, when the falling edge of the input clock signal CK is input to the fourth D flip-flop circuit 17 at time t42, the feedback clock signal Q4, which is the output signal of the fourth D flip-flop circuit 17, becomes low level.

[0177] Furthermore, at time t42, the signals input to the first AND circuit 13 are a high-level signal obtained by inverting the feedback clock signal Q4 by the second inverter circuit 15 and a high-level signal as the output signal Q0 of the first D flip-flop circuit 11. Therefore, the output signal D1 output from the first AND circuit 13 becomes high level. The output signal D1 is input to the reset terminal R of the RS latch circuit 308. For this reason, at time t42, a high level is input to the reset terminal R of the RS latch circuit 308.

[0178] The signals input to the second AND circuit 219 are the output signal Q1 of the second D flip-flop circuit 12 and the input clock signal CK. Since the output signal Q1 of the second D flip-flop circuit 12 is at a high level during the period from time t42 to time t44, the second internal clock signal Q27, which is the output signal of the second AND circuit 219, is at a low level during the period from time t42 to time t43 when the input clock signal CK is at a low level. On the other hand, during the period from time t43 to time t44 when the input clock signal CK is at a high level, the second internal clock signal Q27 becomes a high level.

[0179] Since the second internal clock signal Q27 is input to the set terminal S of the RS latch circuit 308, during the period from time t42 to time t43, a high-level signal is input to the reset terminal R of the RS latch circuit 308, and the second internal clock signal Q27, which is at a low level, is input to the set terminal S. Therefore, the clock signal CKO, which is the output of the RS latch circuit 308, becomes a low level.

[0180] On the other hand, during the period from time t43 to time t44, a high-level signal is input to the reset terminal R of the RS latch circuit 308, and the second internal clock signal Q27, which is at a high level, is input to the set terminal S. That is, the reset terminal R and the set terminal S become high level at the same time, but since the RS latch circuit 308 gives priority to reset, the clock signal CKO, which is the output of the RS latch circuit 308, becomes a low level during the period from time t43 to time t44.

[0181] Since the output signal D1 is also at a high level during the period from time t44 to time t46, a high-level signal is input to the reset terminal R of the RS latch circuit 308. Since the RS latch circuit 308 gives priority to reset, regardless of the change in the second internal clock signal Q27 during the period from time t44 to time t46, the high-level input to the reset terminal R is prioritized, and the clock signal CKO, which is the output of the RS latch circuit 308, becomes a low level during the period from time t44 to time t46.

[0182] At time t46, when the falling edge of the input clock signal CK is input to the fourth D-type flip-flop circuit 17, the fourth D-type flip-flop circuit 17 latches the output signal Q3 which is at a high level and becomes high level. When the high-level feedback clock signal Q4 is input to the second inverter circuit 15, the inverted and output low-level signal is input to the first AND circuit 13. As a result, the output signal D1 of the first AND circuit 13 becomes low level.

[0183] At time t46, a high-level output signal Q1 and a low-level input clock signal CK are input to the second AND circuit 219. Therefore, the second internal clock signal Q27 output from the second AND circuit 219 becomes low level. As a result, the output signal D1 which is at a low level is input to the reset terminal R of the RS latch circuit 308, and the second internal clock signal Q27 which is at a low level is input to the set terminal S. Therefore, the clock signal CKO output from the RS latch circuit 308 becomes low level.

[0184] On the other hand, at time t47, when the rising edge of the input clock signal CK is input to the second AND circuit 219, a high-level output signal Q1 and a high-level input clock signal CK are input to the second AND circuit 219. Therefore, the second internal clock signal Q27 output from the second AND circuit 219 becomes high level. As a result, the output signal D1 which is at a low level is input to the reset terminal R of the RS latch circuit 308, the input clock signal CK which is at a high level is input to the set terminal S, and the clock signal CKO output from the RS latch circuit 308 becomes high level.

[0185] In the operation after time t47, while the output signal D1 input to the reset terminal R of the RS latch circuit 308 is at a low level, the output of the RS latch circuit 308 does not change regardless of whether the second internal clock signal Q27 is at a low level or a high level. Then, at time t49, when the output signal D1 changes to a high level, the output of the RS latch circuit 308 is reset and the clock signal CKO changes to a low level.

[0186] As a result of the above processing, the clock signal CKO, which is the output of the RS latch circuit 308, becomes a clock signal having a period seven times that of the input clock signal CK's period T and a duty ratio of 50%, as shown in FIG. 20. For example, focusing on the period from time t47 to time t50, the clock signal CKO is at a high level during the first half period, i.e., from time t47 to time t49, and at a low level during the remaining half period, i.e., from time t49 to time t50. According to the above configuration, the frequency division circuit 2289 performs frequency division by an odd division ratio of 7 and the duty ratio of the clock signal becomes 50%.

[0187] (12) Other embodiments, etc. The above embodiments are examples for implementing the present invention, and various other embodiments can also be adopted. For example, the PLL circuit may not be a fractional N-PLL circuit, but a PLL circuit that does not include a delta-sigma modulation circuit 227 and a clock conversion circuit 226. The application target of the PLL circuit according to an embodiment of the present invention is not limited, and it can be used for various targets, such as various electronic devices, automotive electrical components, etc. Also, the frequency division circuit may be used together with a circuit other than the PLL circuit, or may be used for a circuit other than the oscillator. The frequency division ratio of the frequency division circuit is not limited to 3, 5, 7, and may be an odd value of a larger number. Also, the reference for the timing of generating the second internal clock signal is not limited to the rising edge. For example, the edge timing generation circuit generates a second internal clock signal having a falling edge at a timing delayed by ((2n - 1) / 2) periods of the input clock signal with respect to the falling edge of the first internal clock signal based on the input clock signal, and in the RS latch circuit, a clock signal with a duty ratio of 50% may be generated based on the first internal clock signal and the second internal clock signal.

[0188] The internal clock generation circuit is a circuit to which first to nth (n is an integer of 2 or more) flip-flop circuits are connected, and it is sufficient if it can generate a first internal clock signal by dividing an input clock signal by (2n - 1). That is, a circuit that divides by an odd division ratio may be configured by combining n known flip-flop circuits. n, which is the number of flip-flop circuits constituting the internal clock generation circuit, only needs to be 2 or more and is not limited to the above example. Also, a flip-flop circuit other than the D flip-flop circuit may be used.

[0189] The edge timing generation circuit only needs to be able to generate a second internal clock signal having a rising edge at a timing delayed by ((2n - 1) / 2) periods of the input clock signal with respect to the rising edge of the first internal clock signal. That is, since the first internal clock signal is a pulse having a length that is an integer multiple of the period of the input clock signal, it does not have an edge at a timing that is 50% of the length of an odd multiple of the period of the input clock signal. For this reason, when the first internal clock signal divides the input clock signal by an odd number, the duty ratio does not become 50%.

[0190] Therefore, the edge timing generation circuit generates a second internal clock signal having a rising edge at a timing delayed by ((2n - 1) / 2) periods, thereby generating a second internal clock signal having a rising edge at a timing that is half of an odd multiple of the period of the input clock signal. By using the second internal clock signal having a rising edge at the said timing, it becomes possible to change the signal level at a timing where the duty ratio becomes 50% by using the said edge.

[0191] The RS latch circuit only needs to have a reset terminal to which the first internal clock signal is input and a set terminal to which the second internal clock signal is input. That is, if the first internal clock signal resets with a pulse having a length that is an integer multiple of the period of the input clock signal and sets with the second internal clock signal having a rising edge at a timing that is half of an odd multiple of the period of the input clock signal, it only needs to be able to make the duty ratio of the clock signal divided by an odd number 50%.

Explanation of Signs

[0192] 10…Internal clock generation circuit, 11…First D-type flip-flop circuit, 12…Second D-type flip-flop circuit, 13…First AND circuit, 14…First inverter circuit, 15…Second inverter circuit, 16…Third D-type flip-flop circuit, 17…Fourth D-type flip-flop circuit, 18…Selector, 19…Third inverter circuit, 20…Edge timing generation circuit, 21…Second AND circuit, 22…Third inverter circuit, 30…RS latch circuit, 101~106…Internal clock generation circuit, 200…Oscillator, 201…Integrated circuit, 202…Vibrator, 204…Edge timing generation circuit, 207…Edge timing generation circuit, 208…Edge timing generation circuit, 209…Edge timing generation circuit, 210…Oscillation circuit, 214~219…Second AND circuit, 220…PLL circuit, 221…Phase comparator, 222…Charge pump, 223…Low-pass filter, 224…Voltage-controlled oscillator, 225…Feedback frequency division circuit, 226…Clock conversion circuit, 227…Delta-sigma modulation circuit, 228…Frequency division circuit, 229…Second frequency division circuit, 230…Output circuit, 240…Communication interface circuit, 250…Memory circuit, 251…Register, 252…Non-volatile memory, 260…Frequency division ratio generation circuit, 270…Power supply circuit, 280…Clock signal generation circuit, 308…RS latch circuit, 2281~2289…Frequency division circuit,

Claims

1. An internal clock generation circuit to which flip-flop circuits numbered from 1 to n (n is an integer of 2 or more) are connected, and which divides an input clock signal by (2n - 1) to generate a first internal clock signal; An edge timing generation circuit that generates a second internal clock signal having a rising edge at a timing delayed by ((2n - 1) / 2) periods of the input clock signal with respect to the rising edge of the first internal clock signal based on the input clock signal; An RS latch circuit having a reset terminal to which the first internal clock signal is input and a set terminal to which the second internal clock signal is input. A frequency division circuit comprising:

2. The second internal clock signal is at a low level during a period in which the first internal clock signal is at a high level, The frequency division circuit according to claim 1.

3. The RS latch circuit is an RS latch circuit with reset priority, The frequency division circuit according to claim 1.

4. A plurality of signals including output signals of the flip-flop circuits numbered j and k (j and k are integers of 2 or more and n or less, and j ≠ k) are input, A selector that operates the frequency division circuit at any of a plurality of division ratios including (2j - 1) and (2k - 1) is provided, The frequency division circuit according to claim 1.

5. The frequency division circuit according to claim 1; A clock signal generation circuit that generates the input clock signal; An oscillator comprising:

6. The output signal of the RS latch circuit is divided by 2 ｍ and further includes a second frequency divider circuit that divides the signal by m (where m is an integer greater than or equal to 0). The oscillator according to claim 5.

7. A first D-type flip-flop circuit operated by an input clock signal; A second D-type flip-flop circuit operated by the input clock signal; A first AND circuit having an output signal of the first D-type flip-flop circuit input to one input terminal and outputting a signal to the second D-type flip-flop circuit; A first inverter circuit that inverts a feedback clock signal based on the output signal of the second D-type flip-flop circuit and outputs it to the first D-type flip-flop circuit; A second inverter circuit that inverts the feedback clock signal and outputs it to the other input terminal of the first AND circuit; A second AND circuit having the input clock signal input to one input terminal; A third inverter circuit that inverts the output signal of the first D-type flip-flop circuit and outputs it to the other input terminal of the second AND circuit; An RS latch circuit in which the output signal of the second D-type flip-flop circuit is input to the reset terminal and the output signal of the second AND circuit is input to the set terminal, A frequency division circuit comprising the same.

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