Neutral network circuit device, failure detection method, learning model generation program, learning model generation device and learning model generation method

Abstract

To provide a neural network circuit device, a failure detection method, a learning model generation program, a learning model generation device and a learning model generation method, capable of detecting a failure while reducing circuit area and power consumption.SOLUTION: A neural network circuit device that performs operations corresponding to a plurality of neural networks, comprising: a plurality of arithmetic circuits that respectively perform operations in the plurality of neural networks, in which structures and parameters from a first layer to a specific layer are the same, and parameters from the specific layer to a final layer are different from each other; an output circuit that determines and outputs a specific operation result from a plurality of first operation results from the first layer to the final layer in each of the plurality of arithmetic circuits; and a failure detection circuit that detects a failure occurring in the plurality of arithmetic circuits based on a plurality of second operation results from the first layer to the specific layer in each of the plurality of arithmetic circuits.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a neural network circuit device, a fault detection method, a learning model generation program, a learning model generation device, and a learning model generation method.

Background Art

[0002] A circuit that performs operations of a deep neural network (DNN) (hereinafter also referred to as a neural network circuit) may, for example, operate unintentionally due to aging deterioration. Therefore, for example, a neural network circuit may be implemented with a function capable of detecting a fault (see Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, as a method for detecting a fault in a neural network circuit as described above, for example, n-MR (n-modular redundancy) for detecting a fault by comparing outputs from the same n circuits is known.

[0005] However, a neural network circuit in which n-MR is implemented has, for example, a larger circuit area and power consumption than a neural network circuit in which n-MR is not implemented. Therefore, a neural network circuit in which n-MR is implemented may, for example, have limited applicable uses.

[0006] Therefore, an object of the present invention is to provide a neural network circuit device, a fault detection method, a learning model generation program, a learning model generation device, and a learning model generation method that enable fault detection while suppressing circuit area and power consumption.

Means for Solving the Problems

[0007] The neural network circuit device according to the present invention for achieving the above object is a neural network circuit device that performs operations corresponding to a plurality of neural networks, and includes a plurality of arithmetic circuits that respectively perform operations in the plurality of neural networks in which the structure and parameters from the first layer to a specific layer are the same and the parameters from the specific layer to the last layer are different from each other, an output circuit that determines and outputs a specific operation result from a plurality of first operation results from the first layer to the last layer in each of the plurality of arithmetic circuits, and a fault detection circuit that detects a fault occurring in the plurality of arithmetic circuits based on a plurality of second operation results from the first layer to the specific layer in each of the plurality of arithmetic circuits.

Effects of the Invention

[0008] According to the neural network circuit device, fault detection method, learning model generation program, learning model generation device, and learning model generation method of the present invention, it is possible to perform fault detection while suppressing circuit area and power consumption.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, such description should not be construed in a limiting sense and does not limit the subject matter recited in the claims. Also, various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure. Further, different embodiments can be combined as appropriate.

[0011] [Configuration Example of Information Processing Apparatus 1 in the First Embodiment] First, a configuration example of the information processing apparatus 1 in the first embodiment will be described. FIGS. 1 to 3 are diagrams showing the configuration example of the information processing apparatus 1 in the first embodiment.

[0012] The information processing apparatus 1 in the present embodiment is a computer apparatus, and performs a process (hereinafter, also simply referred to as an inference process) of inferring output data (for example, data indicating the type of an object shown in image data) from input data (for example, image data) by using a plurality of learning models (a plurality of deep neural networks) each learned with a plurality of teacher data.

[0013] Specifically, as shown in FIG. 1 for example, the information processing apparatus 1 includes a CPU (Central Processing Unit) 101, a memory 102, a communication interface 103, a storage medium 104, and an AI processor 110 (hereinafter also referred to as a neural network circuit device). Each unit is connected to each other via a bus 105. Note that the information processing apparatus 1 may have a dedicated circuit (not shown) that performs the same processing as the CPU 101 instead of the CPU 101, for example.

[0014] The storage medium 104 has, for example, a program storage area (not shown) that stores a program (not shown) for performing inference processing.

[0015] Also, the storage medium 104 has, for example, a storage area (not shown) that stores information used when performing inference processing. Note that the storage medium 104 may be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0016] The CPU 101 performs inference processing by executing a program (not shown) loaded from the storage medium 104 into the memory 102. The memory 102 is, for example, a DRAM (Dynamic Random Access Memory).

[0017] The AI processor 110 is an accelerator such as an FPGA (Field Programmable Gate Array), and has a plurality of arithmetic circuits 120 that perform various arithmetic operations corresponding to a plurality of learning models. Specifically, the plurality of arithmetic circuits 120 perform arithmetic operations corresponding to a plurality of learning models generated by, for example, ensemble learning.

[0018] The communication interface 103 communicates with the operator terminal 2 via a network NW such as the Internet. Note that the operator terminal 2 is, for example, a PC (Personal Computer), and is a terminal for an operator to input necessary information and the like.

[0019] Also, the AI processor 110 in the present embodiment has, for example, a plurality of arithmetic circuits 120 (hereinafter also referred to as a plurality of arithmetic circuits 121) that perform arithmetic operations for each of a plurality of learning models. Hereinafter, as shown in FIG. 2, a case where the AI processor 110 has three arithmetic circuits 121 (arithmetic circuit 121a, arithmetic circuit 121b, and arithmetic circuit 121c) will be described. However, the AI processor 110 may have, for example, two or four or more arithmetic circuits 121.

[0020] Specifically, each of the plurality of arithmetic circuits 121 performs arithmetic operations corresponding to each learning model in which, for example, the structure and parameters of one or more layers from the first layer to a specific layer (hereinafter also referred to as a specific layer) are the same as those of other learning models, and the parameters of one or more layers from the specific layer to the last layer are different from those of other learning models. Hereinafter, one or more layers from the first layer to the specific layer (layers with the same structure and parameters as other learning models) corresponding to each learning model are collectively referred to as fixed layers. Also, hereinafter, one or more layers from the specific layer to the last layer corresponding to each learning model (layers with the same structure as other learning models and different parameters from other learning models, or layers with both different structures and parameters from other learning models) are collectively referred to as individual layers.

[0021] That is, in the present embodiment, the plurality of learning models in which arithmetic operations are performed in each of the plurality of arithmetic circuits 121 are, for example, a plurality of learning models in which the structures and parameters of the fixed layers are the same as each other, and the parameters of the individual layers are at least different from each other.

[0022] Note that the layers corresponding to each learning model may include, for example, a convolutional layer, a pooling layer, a batch normalization layer, and a fully connected layer.

[0023] More specifically, as shown in FIG. 3, for example, the plurality of arithmetic circuits 121 include an arithmetic circuit 121a that performs arithmetic operations on a learning model NN1 composed of a fixed layer NNa1 and an individual layer NNb1. Further, the plurality of arithmetic circuits 121 include an arithmetic circuit 121b that performs arithmetic operations on a learning model NN2 composed of a fixed layer NNa2 and an individual layer NNb2. Further, the plurality of arithmetic circuits 121 include an arithmetic circuit 121c that performs arithmetic operations on a learning model NN3 composed of a fixed layer NNa3 and an individual layer NNb3. Hereinafter, the learning model NN1, the learning model NN2, and the learning model NN3 are collectively referred to simply as the learning model NN. Also, hereinafter, the fixed layer NNa1, the fixed layer NNa2, and the fixed layer NNa3 are collectively referred to simply as the fixed layer NNa, and the individual layer NNb1, the individual layer NNb2, and the individual layer NNb3 are collectively referred to simply as the individual layer NNb.

[0024] That is, in the example shown in FIG. 3, each of the learning model NN1, the learning model NN2, and the learning model NN3 is a learning model learned such that the structures and parameters in each of the fixed layer NNa1, the fixed layer NNa2, and the fixed layer NNa3 are the same, and the parameters in each of the fixed layer NNa1, the fixed layer NNa2, and the fixed layer NNa3 are different from each other.

[0025] Also, the AI processor 110 has, for example, an arithmetic circuit 120 (hereinafter also referred to as an output circuit 122) that determines and outputs an arithmetic result (hereinafter also referred to as a specific arithmetic result) of the entire AI processor 110 from a plurality of arithmetic results (hereinafter also referred to as a plurality of first arithmetic results) from the first layer to the last layer in each of the plurality of arithmetic circuits 121. That is, the output circuit 122 determines and outputs an inference result (hereinafter also simply referred to as an inference result) in the inference process from the arithmetic results of the individual layer NNb in each of the plurality of arithmetic circuits 121.

[0026] Specifically, the output circuit 122 outputs, for example, the most frequent operation result among the operation results of the individual layer NNb in each of the plurality of operation circuits 121. Further, the output circuit 122 outputs, for example, the average value of the operation results of the individual layer NNb in each of the plurality of operation circuits 121.

[0027] More specifically, as shown in FIG. 3, the output circuit 122 determines and outputs an inference result from, for example, each of the operation results in the individual layer NNb1, the operation result in the individual layer NNb2, and the operation result in the individual layer NNb3.

[0028] The AI processor 110 further includes, for example, an operation circuit 120 (hereinafter also referred to as a failure detection circuit 123) that detects a failure that has occurred in the plurality of operation circuits 121 based on a plurality of operation results (hereinafter also referred to as a plurality of second operation results) from the first layer to a specific layer in each of the plurality of operation circuits 121. That is, the failure detection circuit 123 detects a failure that has occurred in the plurality of operation circuits 121 by using, for example, the operation results of the fixed layer NNa in each of the plurality of operation circuits 121.

[0029] Specifically, for example, when any one of the operation results of the fixed layer NNa in each of the plurality of operation circuits 121 does not match other operation results, the failure detection circuit 123 determines that there may be a failure in the operation circuit 121 corresponding to the operation result that does not match the other operation results among the plurality of operation circuits 121.

[0030] More specifically, as shown in FIG. 3, the failure detection circuit 123 compares, for example, the operation result in the fixed layer NNa1, the operation result in the fixed layer NNa2, and the operation result in the fixed layer NNa3 with each other. Then, for example, when the operation result in the fixed layer NNa1 is different from other operation results (the operation result in the fixed layer NNa2 and the operation result in the fixed layer NNa3), the failure detection circuit 123 notifies the CPU 101 of information indicating that there may be a failure in the operation circuit 121a corresponding to the fixed layer NNa1.

[0031] That is, the fixed layers NNa1, NNa2, and NNa3 are, for example, one or more layers learned so that the structure and parameters are the same. Therefore, for example, when no abnormality such as a failure occurs in each of the arithmetic circuits 121a, 121b, and 121c, the outputs from the fixed layers NNa1, NNa2, and NNa3 can be determined to match each other. On the other hand, for example, when an abnormality such as a failure occurs in at least any one of the arithmetic circuits 121a, 121b, and 121c, the outputs from the fixed layers NNa1, NNa2, and NNa3 can be determined such that some of the outputs do not match the other outputs.

[0032] Therefore, the plurality of arithmetic circuits 121 in the present embodiment not only output the arithmetic results in the individual layers NNb1, NNb2, and NNb3 to the output circuit 122, but also output the arithmetic results in the fixed layers NNa1, NNa2, and NNa3 to the failure detection circuit 123.

[0033] Thereby, the AI processor 110 in the present embodiment can output, for example, information indicating that a failure may have occurred in the plurality of arithmetic circuits 121.

[0034] Further, in the AI processor 110 in the present embodiment, for example, inference processing is executed by implementing a plurality of learning models NN generated by ensemble learning in a plurality of arithmetic circuits 121.

[0035] As a result, the AI processor 110 in the present embodiment can, for example, suppress the size of each learning model NN implemented in each arithmetic circuit 121 to be smaller than the size of the learning model implemented in each arithmetic circuit in the case of conventional n-MR. Therefore, the AI processor 110 in the present embodiment can, for example, suppress the circuit area and power consumption of the plurality of arithmetic circuits 121 while outputting information indicating that a failure may have occurred in the plurality of arithmetic circuits 121. Therefore, the AI processor 110 can be implemented, for example, also for each device such as an edge AI device with restrictions on circuit area, power consumption, etc.

[0036] Furthermore, each learning model NN corresponding to the plurality of arithmetic circuits 121 in the present embodiment is learned, for example, such that some layers become individual layers NNb without making all layers fixed layers NNa. In other words, each learning model NN is learned, for example, to have a fixed layer NNa and an individual layer NNb, respectively.

[0037] As a result, the AI processor 110 in the present embodiment can, for example, realize both detection of a failure occurring in the plurality of arithmetic circuits 121 and suppression of the circuit area and power consumption in the plurality of arithmetic circuits 121, and further maintain the inference accuracy in the inference process.

[0038] Note that the failure detection circuit 123 may, for example, notify the output circuit 122 of information indicating the arithmetic circuit 121 (hereinafter also referred to as the failed arithmetic circuit 121) determined to have a possible failure when it is determined that a failure may have occurred in the plurality of arithmetic circuits 121. And in this case, the output circuit 122 may, for example, determine the inference result without using the arithmetic result in the failed arithmetic circuit 121. In other words, in this case, the output circuit 122 may, for example, determine the inference result by using the arithmetic results in each arithmetic circuit 121 other than the failed arithmetic circuit 121 among the plurality of arithmetic circuits 121.

[0039] Specifically, in this case, the output circuit 122 outputs, for example, the most frequent operation result among the operation results of the individual layer NNb in each operation circuit 121 other than the faulty operation circuit 121 among the plurality of operation circuits 121. Further, the output circuit 122 outputs, for example, the average value of the operation results of the individual layer NNb in each operation circuit 121 other than the faulty operation circuit 121 among the plurality of operation circuits 121.

[0040] As a result, in the AI processor 110 according to the present embodiment, for example, when three or more operation circuits 121 are mounted on the AI processor 110, even when a potentially faulty operation circuit 121 is detected, it is possible to continue executing the inference process.

[0041] In the above example, the case where the plurality of operation circuits 121, the output circuit 122, and the fault detection circuit 123 are mounted on a single AI processor 110 has been described, but it is not limited to this. Specifically, each of the plurality of operation circuits 121, the output circuit 122, and the fault detection circuit 123 may be divided and mounted on a plurality of AI processors (not shown), for example.

[0042] In the above example, the case where the CPU 101 is separate from the AI processor 110 has been described, but it is not limited to this. Specifically, the CPU 101 may be mounted inside the AI processor 110, for example.

[0043] [Inference Process in AI Processor 110] Next, the inference process performed in the AI processor 110 will be described. FIG. 4 is a flowchart for explaining the inference process.

[0044] As shown in FIG. 4, the AI processor 110 (each of the plurality of operation circuits 121) waits, for example, until the input of input data is received (NO in S1).

[0045] Specifically, the arithmetic circuit 121 waits, for example, until it receives the input of input data (e.g., image data) input by an operator.

[0046] And when receiving the input of the input data (YES in S1), the AI processor 110 (each of the plurality of arithmetic circuits 121) performs, for example, operations corresponding to each layer constituting each learning model NN (each learning model NN corresponding to each arithmetic circuit 121) on the received input data (S2).

[0047] Specifically, as described with reference to FIG. 3, the arithmetic circuit 121a, for example, performs an operation corresponding to the fixed layer NNa1 on the input data and then further performs an operation corresponding to the individual layer NNb1. Further, the arithmetic circuit 121b, for example, performs an operation corresponding to the fixed layer NNa2 on the input data and then further performs an operation corresponding to the individual layer NNb2. Furthermore, the arithmetic circuit 121c, for example, performs an operation corresponding to the fixed layer NNa3 on the input data and then further performs an operation corresponding to the individual layer NNb3.

[0048] And the AI processor 110 (output circuit 122) determines and outputs an inference result (a specific operation result) from a plurality of operation results up to the individual layer NNb regarding the operations performed in the process of S2, for example (S3).

[0049] Specifically, the output circuit 122 outputs, for example, the most frequent operation result among the operation results in the individual layer NNb1, the operation result in the individual layer NNb2, and the operation result in the individual layer NNb3. Also, the output circuit 122 outputs, for example, the average value of the operation result in the individual layer NNb1, the operation result in the individual layer NNb2, and the operation result in the individual layer NNb3.

[0050] Also, the AI processor 110 (fault detection circuit 123) detects faults occurring in the plurality of arithmetic circuits 121 from a plurality of operation results up to the fixed layer NNa regarding the operations performed in the process of S2, for example (S4).

[0051] Specifically, for example, when the calculation result in the fixed layer NNa1 does not match other calculation results (the calculation result in the fixed layer NNa2 and the calculation result in the fixed layer NN3a), the failure detection circuit 123 determines that there may be a failure in the calculation circuit 121a that performs the calculation corresponding to the fixed layer NNa1. Also, for example, when the calculation result in the fixed layer NNa2 does not match other calculation results (the calculation result in the fixed layer NNa2 and the calculation result in the fixed layer NN3a), the failure detection circuit 123 determines that there may be a failure in the calculation circuit 121b that performs the calculation corresponding to the fixed layer NNa2. Further, the failure detection circuit 1 23 determines that, for example, when the calculation result in the fixed layer NN3a does not match other calculation results (the calculation result in the fixed layer NNa1 and the calculation result in the fixed layer NNa2), there may be a failure in the calculation circuit 121c that performs the calculation corresponding to the fixed layer NN3a.

[0052] Note that, for example, after the process of S2 is performed, the AI processor 110 may perform the processes of S3 and S4 in parallel in each of the output circuit 122 and the failure detection circuit 123.

[0053] [Configuration example of the information processing apparatus 1 in the first modification example] Next, a configuration example of the information processing apparatus 1 in a modification example of the first embodiment (hereinafter also referred to as the first modification example) will be described. FIG. 5 is a diagram showing a configuration example of the information processing apparatus 1 in the first modification example. Note that, in FIG. 5, the notation of each calculation circuit 121 is omitted.

[0054] In the example described with reference to FIGS. 1 to 3, the case where the fixed layer NNa having the same structure and parameters is implemented in all the calculation circuits 121 has been described, but it is not limited thereto. Specifically, for example, if each of the fixed layers NNa having the same structure and parameters is implemented in two or more calculation circuits 121, a plurality of types of fixed layers NNa having different structures and parameters may be implemented in a plurality of calculation circuits 121.

[0055] Specifically, as shown in FIG. 5, for example, when a learning model NN4 composed of a fixed layer NNa4 and an individual layer NNb4, a learning model NN5 composed of a fixed layer NNa5 and an individual layer NNb5, a learning model NN6 composed of a fixed layer NNa6 and an individual layer NNb6, and a learning model NN7 composed of a fixed layer NNa7 and an individual layer NNb7 are implemented in each of a plurality of arithmetic circuits 121, the AI processor 110 may make the structures and parameters in each of the fixed layer NNa4 and the fixed layer NNa5 the same, and make the structures and parameters in each of the fixed layer NNa6 and the fixed layer NNa7 the same. And at least one of the structures and parameters in each of the fixed layer NNa4 and the fixed layer NNa5 may be different from at least one of the structures and parameters in each of the fixed layer NNa6 and the fixed layer NNa7 in this case, for example.

[0056] Furthermore, in this case, the AI processor 110 has, for example, a failure detection circuit 123 (hereinafter also referred to as the failure detection circuit 123a) that detects the occurrence of a failure in the arithmetic circuit 121 in which the learning model NN4 is executed and the arithmetic circuit 121 in which the learning model NN5 is executed from the arithmetic result in the fixed layer NNa4 and the arithmetic result in the fixed layer NNa5. Also, in this case, the AI processor 110 further has, for example, a failure detection circuit 123 (hereinafter also referred to as the failure detection circuit 123b) that detects the occurrence of a failure in the arithmetic circuit 121 in which the learning model NN6 is executed and the arithmetic circuit 121 in which the learning model NN7 is executed from the arithmetic result in the fixed layer NNa6 and the arithmetic result in the fixed layer NNa7.

[0057] As a result, in the AI processor 110, for example, it is no longer necessary to make the structures and parameters in all the fixed layers NNa the same. Therefore, in the AI processor 110, for example, for each group of learning models NN classified according to the characteristics of each learning model NN, etc., different types of fixed layers NNa (fixed layers NNa in which at least one of the structure and parameters is different from each other) can be implemented. Therefore, in the AI processor 110, for example, it becomes possible to further improve the inference accuracy in the inference process.

[0058] [Learning process of learning model NN] Next, a process of learning the learning model NN (hereinafter also referred to as a learning process) will be described. FIGS. 6 to 8 are diagrams for explaining the learning process of the learning model NN. Specifically, FIG. 6 is a diagram for explaining the functions of the information processing apparatus 11. FIG. 7 is a flowchart for explaining the learning process. FIG. 8 is a diagram for explaining the relationship between the learning model NN and the teacher model TNN. Hereinafter, a case where the learning process is performed in an information processing apparatus 11 different from the information processing apparatus 1 will be described.

[0059] As shown in FIG. 6, the information processing apparatus 11 realizes each function including, for example, an information management unit 111, a data generation unit 112, a model generation unit 113, and a model output unit 114 as functions for executing the learning process.

[0060] The information management unit 111 stores various information input by the operator via the operator terminal 2 in a storage medium (not shown), for example. Specifically, when the information management unit 111 receives the input of a plurality of image data (input data), for example, it stores the received plurality of image data in the storage medium. Further, when the information management unit 111 receives the input of a plurality of pieces of information indicating the types of objects reflected in each of the plurality of image data (hereinafter also referred to as a plurality of type information), it stores the received plurality of type information in the storage medium.

[0061] The data generation unit 112 generates a plurality of teacher data (not shown), for example, by using a plurality of image data stored in a storage medium. Specifically, the data generation unit 112 generates teacher data including each image data and classification information corresponding to each image data for each of the plurality of image data stored in the storage medium. Then, the data generation unit 112 stores the generated plurality of teacher data in the storage medium, for example.

[0062] The model generation unit 113 generates a plurality of learning models NN by performing learning (machine learning) on a plurality of teacher data stored in a storage medium. Specifically, the model generation unit 113 generates a plurality of learning models NN such that the structures and parameters of the fixed layer NNa are the same, and the structures of the individual layers NNb are the same while the parameters are different from each other. Also, the model generation unit 113 generates a plurality of learning models NN such that the structures and parameters of the fixed layer NNa are the same, and the structures and parameters of the individual layers NNb are different from each other. Then, the model generation unit 113 stores the generated plurality of learning models NN in the storage medium, for example.

[0063] More specifically, as described with reference to FIG. 3, the model generation unit 113 generates, for example, a learning model NN1 including a fixed layer NNa1 and an individual layer NNb1, a learning model NN2 including a fixed layer NNa2 and an individual layer NNb2, and a learning model NN3 including a fixed layer NNa3 and an individual layer NNb3.

[0064] Note that the model generation unit 113 may generate a plurality of learning models NN by using a plurality of mutually different teacher data, or may generate a plurality of learning models NN by using a plurality of identical teacher data.

[0065] The model output unit 114 outputs a plurality of learning models NN stored in a storage medium. Specifically, the model output unit 114 outputs a plurality of learning models NN stored in the storage medium to the operator terminal 2, for example.

[0066] [Learning Process in Information Processing Apparatus 11] Next, the learning process in the information processing apparatus 11 will be described.

[0067] As shown in FIG. 7, the information processing apparatus 11 (data generation unit 112) waits, for example, until the learning timing (NO in S11). The learning timing may be, for example, the timing when an operator inputs information indicating that the learning model NN is to be generated via the operator terminal 2. .

[0068] When the learning timing arrives (YES in S11), the information processing apparatus 11 (data generation unit 112) generates teacher data including each image data and the type information corresponding to each image data for each of a plurality of image data stored in the storage medium, for example (S12).

[0069] Subsequently, the information processing apparatus 11 (model generation unit 113) generates a plurality of learning models NN by performing learning (machine learning) on a plurality of pieces of teacher data stored in the storage medium, for example (S13).

[0070] Specifically, the model generation unit 113 generates a plurality of learning models NN such that, for example, the structure and parameters of the fixed layer NNa are the same, and the structure of the individual layer NNb is the same while the parameters are different from each other. Also, the model generation unit 113 generates a plurality of learning models NN such that, for example, the structure and parameters of the fixed layer NNa are the same, and the structure and parameters of the individual layer NNb are different from each other.

[0071] Thereby, the information processing apparatus 11 in the present embodiment can generate a plurality of learning models NN that can detect, for example, the arithmetic circuit 121 that may have failed while executing the inference process.

[0072] Note that the model generation unit 113 may, for example, generate in advance a plurality of other learning models (hereinafter also referred to as teacher models) having the same configuration as each learning model NN for each of the plurality of learning models NN by performing learning on a plurality of teacher data stored in a storage medium. Specifically, in this case, the model generation unit 113 may generate each of the plurality of teacher models such that at least one of the structure and parameters of each layer from the first layer to the last layer is different from each other.

[0073] Then, as shown in FIG. 8, the model generation unit 113 may generate each of the plurality of learning models NN such that the difference between the calculation result in each learning model NN and the calculation result in the teacher model TNN corresponding to each learning model NN becomes small.

[0074] That is, the teacher model TNN is, for example, a learning model that does not have the fixed layer NNa (a learning model having only the individual layer NNb). Therefore, it can be determined that the teacher model TNN is, for example, a learning model with higher estimation accuracy than the learning model NN.

[0075] Therefore, the model generation unit 113 may perform learning of the learning model NN, for example, by performing processing (so-called distillation processing) using the calculation result in the teacher model TNN.

[0076] As a result, the information processing apparatus 11 in the present embodiment can, for example, further improve the inference accuracy of the learning model NN.

Description of Reference Numerals

[0077] 1: Information processing apparatus 2: Operator terminal 11: Information processing apparatus 101: CPU 102: Memory 103: Communication interface 104: Storage medium 105: Bus 110: AI processor 111: Information Management Department 112: Data Generation Department 113: Model Generation Department 114: Model Output Department 120: Arithmetic Circuit 121: Arithmetic Circuit 121a: Arithmetic Circuit 121b: Arithmetic Circuit 121c: Arithmetic Circuit 122: Output Circuit 123: Fault Detection Circuit 123a: Fault Detection Circuit 123b: Fault Detection Circuit

Claims

1. A neural network circuit device that performs operations corresponding to a plurality of neural networks, a plurality of arithmetic circuits that respectively perform operations in the plurality of neural networks, wherein the structure and parameters from the first layer to a specific layer are the same, and the parameters from the specific layer to the last layer are different from each other; an output circuit that determines and outputs a specific operation result from a plurality of first operation results from the first layer to the last layer in each of the plurality of arithmetic circuits; and a failure detection circuit that detects a failure that has occurred in the plurality of arithmetic circuits based on a plurality of second operation results from the first layer to the specific layer in each of the plurality of arithmetic circuits. A neural network circuit device.

2. In claim 1, the output circuit outputs the most frequent operation result among the plurality of first operation results as the specific operation result. A neural network circuit device.

3. In claim 1, the output circuit outputs the average value of the plurality of first operation results as the specific operation result. A neural network circuit device.

4. In claim 1, when any one of the plurality of second operation results does not match other operation results, the failure detection circuit determines that there may be a failure in a specific arithmetic circuit corresponding to the any one of the plurality of arithmetic circuits. A neural network circuit device.

5. In claim 1, when the failure detection circuit determines that a failure has occurred in a specific arithmetic circuit, the output circuit determines and outputs the specific operation result from the plurality of first operation results in each of the arithmetic circuits other than the specific arithmetic circuit among the plurality of arithmetic circuits. A neural network circuit device.

6. In claim 5, the plurality of arithmetic circuits are three or more arithmetic circuits. A neural network circuit device.

7. In claim 1, the plurality of arithmetic circuits include a plurality of first arithmetic circuits that respectively perform operations in a plurality of first neural networks, wherein the structure and parameters from the first layer to a first specific layer are the same, and the parameters from the first specific layer to the last layer are different from each other; A plurality of second arithmetic circuits that respectively perform operations in a plurality of second neural networks where the structure and parameters from the first layer to the second specific layer are the same and the parameters from the second specific layer to the last layer are different from each other, The failure detection circuit detects a failure that occurred in the plurality of first arithmetic circuits based on the second arithmetic results corresponding to each of the plurality of first arithmetic circuits, and detects a failure that occurred in the plurality of second arithmetic circuits based on the second arithmetic results corresponding to each of the plurality of second arithmetic circuits. A neural network circuit device.

8. A neural network circuit device that performs operations corresponding to a plurality of neural networks A failure detection method in The plurality of arithmetic circuits included in the neural network circuit device respectively perform operations in the plurality of neural networks where the structure and parameters from the first layer to the specific layer are the same and the parameters from the specific layer to the last layer are different from each other, The output circuit included in the neural network circuit device determines and outputs a specific arithmetic result from a plurality of first arithmetic results from the first layer to the last layer in each of the plurality of arithmetic circuits, The failure detection circuit included in the neural network circuit device detects a failure that occurred in the plurality of arithmetic circuits based on a plurality of second arithmetic results from the first layer to the specific layer in each of the plurality of arithmetic circuits. A failure detection method.

9. A learning model generation program that causes a computer to execute a process of generating a plurality of neural networks by performing machine learning on a plurality of teacher data, A learning model generation program that generates each of the plurality of neural networks such that the structure and parameters from the first layer to the specific layer are the same and the parameters from the specific layer to the last layer are different from each other.

10. In Claim 9, By performing machine learning on a plurality of teacher data, a process of generating a plurality of other neural networks having the same configuration as each of the plurality of neural networks is caused to be executed by a computer, In the process of generating the plurality of other neural networks, the plurality of other neural networks are generated such that the parameters from the first layer to the last layer are different from each other, In the process of generating the plurality of neural networks, for each of the plurality of neural networks, each neural network is generated such that the difference between the operation result in each neural network and the operation results in the other neural networks corresponding to each of the plurality of other neural networks is reduced. A learning model generation program. **Claim 11** A learning model generation device that generates a plurality of neural networks by performing machine learning on a plurality of teacher data, A learning model generation device that generates each of the plurality of neural networks such that the structures and parameters from the first layer to a specific layer are the same, and the parameters from the specific layer to the last layer are different from each other. **Claim 12** A learning model generation method in which a computer executes a process of generating a plurality of neural networks by performing machine learning on a plurality of teacher data, A learning model generation method in which each of the plurality of neural networks is generated such that the structures and parameters from the first layer to a specific layer are the same, and the parameters from the specific layer to the last layer are different from each other.

Images