Error correction circuit

Abstract

To provide an error correction circuit that can change correction performance according to line conditions and required performance.SOLUTION: An error correction circuit 3 includes soft-decision decoders 230 to 235 respectively having a plurality of threshold tables 230a to 230d, 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, and 235a to 235d therein. Each of the soft-decision decoders 230 to 235 selects one of the plurality of threshold tables 230a to 230d, 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, and 235a to 235d to increase or decrease the amount of error correction, thereby reducing miscorrections.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an error correction circuit and an error correction method for a digital coherent optical transmission system.

Background Art

[0002] In coherent optical communication, in order to improve transmission characteristics, distortion and frequency / phase fluctuations that occur during transmission are compensated by digital signal processing. In order to further improve transmission characteristics, in addition to the above compensation function, an error correction device is provided between the transmitter and the receiver to reduce data errors in transmission characteristics. Generally, error correction encoding is performed on data on the transmission side, and error correction is performed on the reception side according to the encoding, thereby improving transmission characteristics.

[0003] As error correction methods, for example, Hamming codes, BCH codes, Reed-Solomon codes, and convolutional codes / Viterbi decoding are generally well known. In particular, in recent communication devices, due to the development of the computing power of CPUs, complex and large-scale processing has become possible, so high-performance error correction methods such as LDPC (low-density parity-check code) are used. In error correction processing, there are hard decision-making in which correction processing is performed based on the result of decoding to "1" or "0", and soft decision-making in which correction processing is performed based on the coordinates on the complex plane of the received signal (before decoding to "1" or "0") (see Patent Document 1).

[0004] In the case of soft decision error correction processing by software, the correction amount can be adjusted by changing the multiplication coefficient of the correction threshold calculation. On the other hand, when implementing soft decision error correction processing in hardware, it is particularly difficult to implement a multiplication circuit that operates at high speed such as a throughput of 1 Tbps.

[0005] Therefore, in a conventional digital coherent optical transmission system, it is common to implement a soft decision error correction circuit with a fixed correction threshold, and there is a problem that the correction performance cannot be changed according to the line condition and the required performance. In addition, when the correction amount is increased, miscorrection also increases, which causes an error floor, so there is a problem that the performance deteriorates.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] The present invention has been made to solve the above problems, and an object thereof is to provide an error correction circuit and an error correction method capable of changing the correction performance according to the line condition and the required performance.

Means for Solving the Problems

[0008] The error correction circuit of the present invention is an error correction circuit in a digital coherent optical transmission system, and includes a plurality of threshold tables that store different thresholds. By selecting any one of the plurality of threshold tables, the error correction amount is increased or decreased to reduce miscorrection. In addition, one configuration example of the error correction circuit of the present invention includes a plurality of soft decision decoding units each having the plurality of threshold tables therein, and is characterized in that the plurality of soft decision decoding units are connected in cascade. In addition, in one configuration example of the error correction circuit of the present invention, each of the plurality of soft decision decoding units selects any one of the plurality of threshold tables in its own circuit according to a threshold control signal supplied from the outside, so that the threshold of each soft decision decoding unit is set to be smaller than when the number of the soft decision decoding units connected in cascade is small. Also, one configuration example of the error correction circuit of the present invention further includes one or more hard decision decoding units, and the one or more hard decision decoding units are connected in cascade after the soft decision decoding unit at the final stage.

[0009] Also, in one configuration example of the error correction circuit of the present invention, the plurality of soft decision decoding units each select one of the plurality of threshold tables in their own circuits according to a threshold control signal supplied from the outside, so that the thresholds of the plurality of soft decision decoding units are set to increase stepwise as they go to the subsequent stage. Also, one configuration example of the error correction circuit of the present invention further includes a plurality of switches for individually setting whether to skip the plurality of soft decision decoding units according to a switch control signal supplied from the outside. Also, in one configuration example of the error correction circuit of the present invention, the plurality of switches are set such that there is one or more of the soft decision decoding units that are not skipped and one or more of the soft decision decoding units that are skipped, and the plurality of soft decision decoding units each select one of the plurality of threshold tables in their own circuits according to a threshold control signal supplied from the outside, so that the threshold of at least one of the soft decision decoding units that are not skipped is set to be larger than in the case where the number of cascaded soft decision decoding units is large.

[0010] Also, one configuration example of the error correction circuit of the present invention further includes a plurality of switches for individually setting whether to skip the plurality of soft decision decoding units and the one or more hard decision decoding units according to a switch control signal supplied from the outside. Also, in one configuration example of the error correction circuit of the present invention, the plurality of switches are set to cascade-connect the plurality of soft decision decoding units and skip the one or more hard decision decoding units. Each of the plurality of soft decision decoding units selects one of the plurality of threshold tables in its own circuit according to a threshold control signal supplied from the outside, so that the thresholds of the plurality of soft decision decoding units increase step by step toward the subsequent stage, and the threshold of at least one of the soft decision decoding units is set to be larger than when the one or more hard decision decoding units are not skipped.

[0011] Further, the present invention relates to an error correction method for a digital coherent optical transmission system, characterized in that by selecting one of a plurality of threshold tables storing different thresholds provided in an error correction circuit, the error correction amount is increased or decreased to reduce error correction.

Advantages of the Invention

[0012] According to the present invention, by providing a plurality of threshold tables storing different thresholds in an error correction circuit, when the error correction circuit is realized by hardware, it is possible to change the correction performance according to the line situation and required performance.

Brief Description of the Drawings

[0013]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0014] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transmission device of a communication system according to a first embodiment of the present invention. The communication system is composed of a transmission device 1 and a reception device. The transmission device 1 encodes and modulates transmission data to generate a transmission signal. The transmission signal is received by the reception device via a wired or wireless communication path. The reception device demodulates and decodes the reception signal to generate reception data.

[0015] The transmission device 1 includes an error correction encoding circuit 10, a symbol mapping circuit 11, a modulation circuit 12, and a DA conversion circuit 13. The error correction encoding circuit 10 generates encoded data by performing, for example, turbo encoding or LDPC (Low Density Parity Check) encoding on the transmission data.

[0016] The symbol mapping circuit 11 performs carrier modulation by assigning the encoded data output from the error correction encoding circuit 10 to symbol points such as QPSK (Quadrature Phase Shift Keying) and 16QAM (Quadrature Amplitude Modulation). The modulation circuit 12 generates a modulation signal by performing, for example, OFDM (Orthogonal Frequency Division Multiplexing) modulation or the like on the data carrier-modulated by the symbol mapping circuit 11.

[0017] The DA conversion circuit 13 converts the modulation signal from a digital signal to an analog signal to generate a transmission signal. The transmission signal is converted into an optical signal by an optical transmission module (not shown) and sent out to an optical fiber transmission line.

[0018] Figure 2 is a block diagram showing the configuration of the receiving apparatus of the communication system according to this embodiment. The receiving apparatus 2 includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, an error correction circuit 23, and a control circuit 24.

[0019] The optical receiving module (not shown) of the receiving apparatus 2 converts the optical signal received from the optical fiber transmission line into an analog received signal. The AD conversion circuit 20 converts the analog received signal into a digital signal. The demodulation circuit 21 performs demodulation processing corresponding to the OFDM modulation or the like performed on the transmitting apparatus 1 side on the signal output from the AD conversion circuit 20, and outputs the demodulated received signal to the symbol demapping circuit 22.

[0020] The symbol demapping circuit 22 outputs a bit string corresponding to the ideal signal point closest to the received signal (received symbol) by hard decision from the received signal output from the demodulation circuit 21. The error correction circuit 23 performs error correction decoding processing on the bit string output from the symbol demapping circuit 22 based on the likelihood information for each bit of the bit string.

[0021] FIG. 3 is a block diagram showing the configuration of the error correction circuit 23 of this embodiment. The error correction circuit 23 includes a plurality of serially connected soft decision decoders (SD-DEC: Soft Decision Decoder) 230 to 235, and hard decision decoders (HD-DEC: Hard Decision Decoder) 236 and 237 serially connected after the last-stage soft decision decoder 235. The number of hard decision decoders may be one or more, or the hard decision decoder may not be provided.

[0022] The soft decision decoder 230 includes four threshold tables 230a to 230d that store different threshold values, and any one of the threshold tables 230a to 230d can be selected by a threshold control signal input from the outside. Similarly, the soft decision decoders 231 to 235 each include threshold tables 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, 235a to 235d, and any one of the threshold tables 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, 235a to 235d can be selected by a threshold control signal input from the outside.

[0023] FIG. 4 is a flowchart for explaining the operation of the error correction circuit 23 in this embodiment. In this embodiment, the threshold values stored in the threshold tables 230a, 231a, 232a, 233a, 234a, 235a are 10%, the threshold values stored in the threshold tables 230b, 231b, 232b, 233b, 234b, 235b are 20%, the threshold values stored in the threshold tables 230c, 231c, 232c, 233c, 234c, 235c are 30%, and the threshold values stored in the threshold tables 230d, 231d, 232d, 233d, 234d, 235d are 40%. Here, the threshold is incremented by 10%, but the range of the threshold (10% to 40%) and the increment width (10%) are not limited to the values of this embodiment.

[0024] First, the control circuit 24 of the receiving device 2 gives a threshold control signal to the soft decision decoding units 230 to 235 of the error correction circuit 23 according to an instruction from a user, designer, or the like of the receiving device 2. As a result, the soft decision decoding units 230 to 235 each select one of the four threshold tables 230a to 230d, 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, and 235a to 235d that they have. In this embodiment, it is assumed that the soft decision decoding units 230 to 235 each select the threshold tables 230b, 231b, 232b, 233b, 234b, and 235b. As a result, the thresholds of the soft decision decoding units 230 to 235 are each set to 20% (step S100 in FIG. 4).

[0025] Next, during the operation of the receiving device 2 after the threshold is set, the first-stage soft decision decoding unit 230 calculates likelihood information indicating the probability of each bit of the data (symbol) output from the symbol demapping circuit 22, and performs error correction decoding processing on the data output from the symbol demapping circuit 22 based on the likelihood information (step S101 in FIG. 4). The method for calculating the likelihood information is disclosed in, for example, Patent Document 1. The soft decision decoding unit 230 corrects errors for bits whose likelihood information value is smaller than the set threshold (20%). The soft decision decoding unit 230 outputs the data after error correction decoding.

[0026] The second-stage soft decision decoding unit 231 calculates likelihood information for each bit of the data after error correction decoding output from the soft decision decoding unit 230, and performs error correction decoding processing on the data output from the soft decision decoding unit 230 based on the likelihood information (step S102 in FIG. 4). The soft decision decoding unit 231 corrects errors for bits whose likelihood information value is smaller than the set threshold (20%). The soft decision decoding unit 231 outputs the data after error correction decoding.

[0027] The soft decision decoding unit 232 in the third stage calculates the likelihood information for each bit of the data after error correction decoding output from the soft decision decoding unit 231, and performs error correction decoding processing on the data output from the soft decision decoding unit 231 based on the likelihood information (step S103 in FIG. 4). The soft decision decoding unit 232 corrects errors for bits whose likelihood information value is smaller than the set threshold value (20%). The soft decision decoding unit 232 outputs the data after error correction decoding.

[0028] The soft decision decoding unit 233 in the fourth stage calculates the likelihood information for each bit of the data after error correction decoding output from the soft decision decoding unit 232, and performs error correction decoding processing on the data output from the soft decision decoding unit 232 based on the likelihood information (step S104 in FIG. 4). The soft decision decoding unit 233 corrects errors for bits whose likelihood information value is smaller than the set threshold value (20%). The soft decision decoding unit 233 outputs the data after error correction decoding.

[0029] The soft decision decoding unit 234 in the fifth stage calculates the likelihood information for each bit of the data after error correction decoding output from the soft decision decoding unit 233, and performs error correction decoding processing on the data output from the soft decision decoding unit 233 based on the likelihood information (step S105 in FIG. 4). The soft decision decoding unit 234 corrects errors for bits whose likelihood information value is smaller than the set threshold value (20%). The soft decision decoding unit 234 outputs the data after error correction decoding.

[0030] The soft decision decoding unit 235 in the sixth stage calculates the likelihood information for each bit of the data after error correction decoding output from the soft decision decoding unit 234, and performs error correction decoding processing on the data output from the soft decision decoding unit 234 based on the likelihood information (step S106 in FIG. 4). The soft decision decoding unit 235 corrects errors for bits whose likelihood information value is smaller than the set threshold value (20%). The soft decision decoding unit 235 outputs the data after error correction decoding.

[0031] The hard decision decoding unit 236 in the seventh stage performs error correction decoding processing on the error-corrected decoded data output from the soft decision decoding unit 235 by hard decision, and outputs the error-corrected decoded data (step S107 in FIG. 4).

[0032] The hard decision decoding unit 237 in the eighth stage performs error correction decoding processing on the error-corrected decoded data output from the hard decision decoding unit 236 by hard decision, and outputs the error-corrected decoded data (step S108 in FIG. 4).

[0033] As described above, in this embodiment, by providing a plurality of threshold tables for storing different thresholds in the soft decision decoding units 230 to 235 respectively, when the error correction circuit 23 is realized by hardware, it is possible to change the correction performance according to the line status and required performance.

[0034] In order to correspond to this embodiment, on the transmission device 1 side, the error correction encoding circuit 10 needs to perform encoding corresponding to the hard decision decoding unit 237, encoding corresponding to the hard decision decoding unit 236, encoding corresponding to the soft decision decoding unit 235, encoding corresponding to the soft decision decoding unit 234, encoding corresponding to the soft decision decoding unit 233, encoding corresponding to the soft decision decoding unit 232, encoding corresponding to the soft decision decoding unit 231, and encoding corresponding to the soft decision decoding unit 230 on the transmission data in order.

[0035] An example of the error correction encoding circuit 10 is shown in FIG. 5. The error correction encoding circuit 10 includes an error correction encoding unit 100 corresponding to the hard decision decoding unit 237, an error correction encoding unit 101 corresponding to the hard decision decoding unit 236, an error correction encoding unit 102 corresponding to the soft decision decoding unit 235, an error correction encoding unit 103 corresponding to the soft decision decoding unit 234, an error correction encoding unit 104 corresponding to the soft decision decoding unit 233, an error correction encoding unit 105 corresponding to the soft decision decoding unit 232, an error correction encoding unit 106 corresponding to the soft decision decoding unit 231, and an error correction encoding unit 107 corresponding to the soft decision decoding unit 230.

[0036] In this embodiment, the number of stages of the soft decision decoder is set to six, and the threshold value of each soft decision decoder is set to 20%. However, the present invention is not limited thereto. For example, the number of stages of the soft decision decoder may be set to three, and the threshold value of each soft decision decoder may be set to 30%. Alternatively, the number of stages of the soft decision decoder may be set to seven, and the threshold value of each soft decision decoder may be set to 20%. By setting the threshold value of each soft decision decoder to be smaller when the number of stages of the soft decision decoder is small (three stages in the above example), the error correction ability can be improved.

[0037] [Second Embodiment] Next, a second embodiment of the present invention will be described. Also in this embodiment, the configurations of the transmission device 1 and the reception device 2 are the same as those in the first embodiment. In this embodiment, the control circuit 24 of the reception device 2 gives a threshold control signal to the soft decision decoders 230 to 235 of the error correction circuit 23, and causes the soft decision decoders 230 to 235 to select threshold tables 230b, 231b, 232c, 233c, 234d, and 235d, respectively. As a result, the threshold values of the soft decision decoders 230 and 231 are set to 20%, the threshold values of the soft decision decoders 232 and 233 are set to 30%, and the threshold values of the soft decision decoders 234 and 235 are set to 40% (step S100 in FIG. 4). Other operations are the same as those in the first embodiment.

[0038] In this embodiment, by gradually increasing the threshold values of the soft decision decoders 230 to 235 toward the latter stage, the error correction performance can be improved as compared with the first embodiment. Since the number of miscorrections increases as the amount of error correction increases, increasing the amount of error correction in the latter stage can increase the amount of error correction while suppressing miscorrections.

[0039] [Third Embodiment] Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the error correction circuit 23 of the reception device 2 according to the third embodiment of the present invention. The same components as those in FIG. 3 are denoted by the same reference numerals.

[0040] The error correction circuit 23 of this embodiment is composed of soft decision decoding units 230 to 235, hard decision decoding units 236 and 237, and switches 238 to 244. In FIG. 6, for simplicity of description, the description of the threshold value table in the soft decision decoding units 230 to 235 is omitted.

[0041] The switch 238 selects either the output of the soft decision decoding unit 230 or the output of the soft decision decoding unit 231 and inputs it to the soft decision decoding unit 232. The switch 239 selects either the output of the switch 238 or the output of the soft decision decoding unit 232 and inputs it to the soft decision decoding unit 233. The switch 240 selects either the output of the switch 239 or the output of the soft decision decoding unit 233 and inputs it to the soft decision decoding unit 234. The switch 241 selects either the output of the switch 240 or the output of the soft decision decoding unit 234 and inputs it to the soft decision decoding unit 235. The switch 242 selects either the output of the switch 241 or the output of the soft decision decoding unit 235 and inputs it to the hard decision decoding unit 236. The switch 243 selects either the output of the switch 242 or the output of the hard decision decoding unit 236 and inputs it to the hard decision decoding unit 237. The switch 244 selects either the output of the switch 243 or the output of the hard decision decoding unit 236.

[0042] FIG. 7 is a flowchart for explaining the operation of the error correction circuit 23 in this embodiment. First, the control circuit 24 of the receiving device 2 gives a switch control signal to the switches 238 to 244 of the error correction circuit 23 according to an instruction from a user or designer of the receiving device 2 or the like. In this embodiment, the switches 238 and 239 respectively select the outputs of the soft decision decoding units 231 and 232. The switches 240 to 242 respectively select the outputs of the switches 239 to 241. The switches 243 and 244 respectively select the outputs of the hard decision decoding units 236 and 237 (step S100a in FIG. 7). With such settings of the switches 238 to 244, the soft decision decoding units 233 to 235 are skipped and not used.

[0043] Also, similar to the first and second embodiments, the control circuit 24 gives a threshold control signal to the soft decision decoding units 230 to 235 of the error correction circuit 23. In this embodiment, it is assumed that the soft decision decoding units 230 to 232 each select threshold tables 230d, 231d, and 232d. As a result, the thresholds of the soft decision decoding units 230 to 232 are each set to 40% (step S100a).

[0044] The processing of steps S101 to S103, S107, and S108 during the operation of the receiving device 2 after the switch setting and the threshold setting is the same as that in the first embodiment.

[0045] As described above, in this embodiment, switches 238 to 244 for selecting whether to skip the decoding units 231 to 237 are provided after each of the decoding units 231 to 237. Thereby, the number of error correction iterations can be made variable. In the soft decision decoding unit and the hard decision decoding unit, the soft decision decoding unit consumes more power. Therefore, in this embodiment, by setting not to use the soft decision decoding units 233 to 235, the power consumption can be reduced compared to the first embodiment. The magnitude of the threshold does not affect the power consumption. Therefore, instead of not using the soft decision decoding units 233 to 235, by increasing the thresholds of the soft decision decoding units 230 to 232 that are not skipped from 20% to 40% to increase the correction amount, it is possible to reduce the power consumption while realizing an error correction ability equivalent to that of the first embodiment.

[0046] Note that, in order to correspond to this embodiment, on the transmitting device 1 side, the error correction encoding circuit 10 needs to perform encoding corresponding to the hard decision decoding unit 237, encoding corresponding to the hard decision decoding unit 236, encoding corresponding to the soft decision decoding unit 232, encoding corresponding to the soft decision decoding unit 231, and encoding corresponding to the soft decision decoding unit 230 on the transmission data in order.

[0047] [Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. FIG. 8 is a block diagram showing the configuration of the error correction circuit 23 of the receiving apparatus 2 according to the fourth embodiment of the present invention, and the same components as those in FIGS. 3 and 6 are denoted by the same reference numerals. Similar to the third embodiment, the error correction circuit 23 includes soft decision decoding units 230 to 235, hard decision decoding units 236 and 237, and switches 238 to 244. In FIG. 8, for simplicity of description, the description of the threshold tables in the soft decision decoding units 230 to 235 is omitted.

[0048] FIG. 9 is a flowchart for explaining the operation of the error correction circuit 23 in this embodiment. First, the control circuit 24 of the receiving apparatus 2 gives a switch control signal to the switches 238 to 244 of the error correction circuit 23 according to an instruction from a user or designer of the receiving apparatus 2 or the like. In this embodiment, the switches 238 to 242 respectively select the outputs of the soft decision decoding units 231 to 235. The switches 243 and 244 respectively select the outputs of the switches 242 and 243 (step S100b in FIG. 9). With such settings of the switches 238 to 244, the hard decision decoding units 236 and 237 are skipped and not used.

[0049] Also, similar to the first to third embodiments, the control circuit 24 gives a threshold control signal to the soft decision decoding units 230 to 235 of the error correction circuit 23. In this embodiment, the soft decision decoding unit 230 selects the threshold table 230a, the soft decision decoding units 231 and 232 select the threshold tables 231b and 232b, the soft decision decoding units 233 and 234 select the threshold tables 233c and 234c, and the soft decision decoding unit 235 selects the threshold table 235d. As a result, the threshold of the soft decision decoding unit 230 is set to 10%, the thresholds of the soft decision decoding units 231 and 232 are set to 20%, the thresholds of the soft decision decoding units 233 and 234 are set to 30%, and the threshold of the soft decision decoding unit 235 is set to 40% (step S100b).

[0050] The processing of steps S101 to S106 during the operation of the receiving apparatus 2 after the switch setting and the threshold setting is the same as that in the first embodiment.

[0051] As described above, in this embodiment, by setting not to use the hard decision decoding units 236 and 237, the latency can be reduced compared to the first embodiment. The magnitude of the threshold does not affect the latency. Therefore, instead of using the hard decision decoding units 236 and 237, the thresholds of the soft decision decoding units 230 to 235 are gradually increased as going to the subsequent stage, and the thresholds of the soft decision decoding units 232 to 235 are made larger than those in the first embodiment to increase the correction amount, so that while reducing the latency, an error correction ability equivalent to that of the first embodiment can be realized.

[0052] Note that, in order to correspond to this embodiment, on the transmission device 1 side, the error correction encoding circuit 10 needs to perform encoding corresponding to the soft decision decoding unit 235, encoding corresponding to the soft decision decoding unit 234, encoding corresponding to the soft decision decoding unit 233, encoding corresponding to the soft decision decoding unit 232, encoding corresponding to the soft decision decoding unit 231, and encoding corresponding to the soft decision decoding unit 230 on the transmission data in order.

Industrial Applicability

[0053] The present invention can be applied to a technique for decoding a received signal in a digital coherent optical transmission system.

Explanation of Signs

[0054] 1... Transmission device, 2... Reception device, 10... Error correction encoding circuit, 11... Symbol mapping circuit, 12... Modulation circuit, 13... DA conversion circuit, 20... AD conversion circuit, 21... Demodulation circuit, 22... Symbol demapping circuit, 23... Error correction circuit, 24... Control circuit, 230 to 235... Soft decision decoding units, 230a to 230d, 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, 235a to 235d... Threshold tables, 236, 237... Hard decision decoding units, 238 to 244... Switches.

Claims

1. In an error correction circuit of a digital coherent optical transmission system, a plurality of threshold tables for storing different thresholds are provided, and by selecting any one of the plurality of threshold tables, the error correction amount is increased or decreased to reduce miscorrection. An error correction circuit characterized by this.

2. In the error correction circuit according to Claim 1, a plurality of soft decision decoding units each having the plurality of threshold tables inside are provided, An error correction circuit characterized in that the plurality of soft decision decoding units are connected in cascade.

3. In the error correction circuit according to Claim 2, The plurality of soft decision decoding units each select any one of the plurality of threshold tables in their own circuits according to a threshold control signal supplied from the outside, so that the threshold of each soft decision decoding unit is compared with that when the number of the soft decision decoding units connected in cascade is small. An error correction circuit characterized in that it is set to be smaller.

4. In the error correction circuit according to Claim 2, One or more hard decision decoding units are further provided, An error correction circuit characterized in that the one or more hard decision decoding units are connected in cascade after the last-stage soft decision decoding unit.

5. In the error correction circuit according to Claim 2, The plurality of soft decision decoding units each select any one of the plurality of threshold tables in their own circuits according to a threshold control signal supplied from the outside, so that the thresholds of the plurality of soft decision decoding units are set to increase step by step toward the latter stage. An error correction circuit characterized by this.

6. In the error correction circuit according to Claim 2, A plurality of switches for individually setting whether to skip the plurality of soft decision decoding units according to a switch control signal supplied from the outside are further provided. An error correction circuit characterized by this.

7. In the error correction circuit according to Claim 6, The plurality of switches are set so that there is one or more of the soft decision decoding units that are not skipped and one or more of the soft decision decoding units that are skipped, The plurality of soft decision decoding units each select any one of the plurality of threshold tables in their own circuits according to a threshold control signal supplied from the outside, so that the threshold of at least one of the soft decision decoding units that are not skipped is larger than when the number of the soft decision decoding units connected in cascade is large. An error correction circuit characterized by this.

8. In the error correction circuit according to claim 4, further comprising a plurality of switches for individually setting whether to skip the plurality of soft decision decoding units and the one or more hard decision decoding units according to a switch control signal supplied from the outside. An error correction circuit characterized by that.

9. In the error correction circuit according to claim 8, the plurality of switches are set to cascade-connect the plurality of soft decision decoding units and skip the one or more hard decision decoding units, each of the plurality of soft decision decoding units selects any one of the plurality of threshold tables in its own circuit according to a threshold control signal supplied from the outside, so that the thresholds of the plurality of soft decision decoding units increase step by step as they go to the subsequent stage, and the threshold of at least one of the soft decision decoding units is set to be larger than when the one or more hard decision decoding units are not skipped. An error correction circuit characterized by that.

10. In an error correction method for a digital coherent optical transmission system, An error correction method characterized by reducing error correction by increasing or decreasing the error correction amount by selecting any one of a plurality of threshold tables storing different thresholds provided in the error correction circuit.

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