Isolation amplifier, analog front end and vehicle

Abstract

To transmit a signal without excess or deficiency regardless of a downstream AD converter.SOLUTION: An isolation amplifier (10, 10B, 10C, 10D) includes a primary-side AD converter (1) configured to convert an analog input signal into a digital signal, and a secondary-side DA converter (2, 2C, 2D) that is electrically insulated from the primary-side AD converter (1) and configured to be able to receive a digital signal (Dgn1) from the primary-side AD converter (Dgn1) and convert it into an analog output signal, and is configured such that when the input range of the subsequent-stage AD converter (20, 20C, 20D) connected to the secondary-side DA converter (2, 2C, 2D) is configured to change depending on the power supply voltage (V1), the secondary-side DA converter (2, 2C, 2D) is supplied with the same voltage as the first voltage (V1) supplied to the subsequent-stage AD converter (20, 20C, 20D).SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to an isolation amplifier, and to an analog front end and a vehicle using the isolation amplifier.

Background Art

[0002] An isolation amplifier is known to be used for removing ground noise during signal transmission and removing noise caused by a DC power supply (see, for example, Patent Document 1, etc.).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] As shown in Patent Document 1, since the isolation amplifier outputs a signal with a fixed range, depending on the characteristics of the AD converter provided in the subsequent stage, there may be a deviation between the output range of the isolation amplifier and the input range of the AD converter, making it difficult to correctly transmit the signal.

[0005] An isolation amplifier according to one aspect of the present disclosure includes a primary-side AD converter configured to convert an analog input signal into a digital signal, and a secondary-side DA converter that is electrically insulated from the primary-side AD converter and is configured to receive a digital signal from the primary-side AD converter and convert it into an analog output signal. When the input range of the subsequent-stage AD converter connected to the secondary-side DA converter changes depending on the power supply voltage, the secondary-side DA converter is configured to be supplied with the same voltage as the first voltage supplied to the subsequent-stage AD converter.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] <Signal Transmission Device (Basic Configuration)> FIG. 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 in this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from a primary circuit system 200p (VCC1-GND1 system) to a secondary circuit system 200s (VCC2-GND2 system) while insulating between the primary circuit system 200p and the secondary circuit system 200s, and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by encapsulating a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0008] The controller chip 210 is a semiconductor chip that operates by receiving a supply of a power supply voltage VCC1 (for example, up to 7V with respect to GND1). For example, a pulse transmission circuit 211, buffers 212 and 213 are integrated in the controller chip 210.

[0009] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to an input pulse signal IN. More specifically, when the input pulse signal IN notifies that it is at a high level, the pulse transmission circuit 211 performs pulse driving (single-shot or multiple-shot transmission pulse output) of the transmission pulse signal S11, and when the input pulse signal IN notifies that it is at a low level, the pulse transmission circuit 211 performs pulse driving of the transmission pulse signal S21. That is, the pulse transmission circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 according to the logic level of the input pulse signal IN.

[0010] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transchip 230 (specifically, the transformer 231).

[0011] The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transchip 230 (specifically, the transformer 232).

[0012] The driver chip 220 is a semiconductor chip that operates by receiving the supply of a power supply voltage VCC2 (for example, up to 30V with respect to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse reception circuit 223, and a driver 224.

[0013] The buffer 221 waveform-shapes the received pulse signal S12 induced in the transchip 230 (specifically, the transformer 231) and outputs it to the pulse reception circuit 223.

[0014] The buffer 222 waveform-shapes the received pulse signal S22 induced in the transchip 230 (specifically, the transformer 232) and outputs it to the pulse reception circuit 223.

[0015] The pulse receiving circuit 223 generates an output pulse signal OUT by driving the driver 224 according to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 to raise the output pulse signal OUT to a high level upon receiving the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level upon receiving the pulse drive of the received pulse signal S22. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. As the pulse receiving circuit 223, for example, an RS flip-flop can be preferably used.

[0016] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0017] The transchip 230 uses the transformers 231 and 232 to insulate the controller chip 210 and the driver chip 220 from each other in a DC manner, and outputs the transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 to the pulse receiving circuit 223 as the received pulse signals S12 and S22, respectively. In this specification, "insulating in a DC manner" means that the objects to be insulated are not connected as conductors.

[0018] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s according to the transmission pulse signal S11 input to the primary coil 231p. On the other hand, the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s according to the transmission pulse signal S21 input to the primary coil 232p.

[0019] Thus, due to the characteristics of the spiral coil used for communication between insulated circuits, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and the fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via the two transformers 231 and 232.

[0020] Note that the signal transmission device 200 of this configuration example independently has a transformer chip 230 that mounts only transformers 231 and 232, separately from the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0021] With such a configuration, both the controller chip 210 and the driver chip 220 can be formed by a general low breakdown voltage to medium breakdown voltage process (breakdown voltage of several V to several tens of V), so there is no need to use a dedicated high breakdown voltage process (breakdown voltage of several kV), and the manufacturing cost can be reduced.

[0022] Note that the signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device of in-vehicle equipment mounted on a vehicle. The above vehicle includes, in addition to an engine vehicle, electric vehicles (xEVs) such as battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles / plug-in hybrid vehicles (PHEVs / PHVs), or fuel cell electric vehicles / fuel cell vehicles (FCEVs / FCVs).

[0023] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. FIG. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 of this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0024] The primary coils 231p and 232p are both formed on the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. Note that the secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. Also, the secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0025] Starting from the first end connected to the internal terminal X21, the primary coil 231p is laid in a spiral shape so as to surround the periphery of the internal terminal X21 in a clockwise direction, and the second end corresponding to its end point is connected to the internal terminal X22. On the other hand, starting from the first end connected to the internal terminal X23, the primary coil 232p is laid in a spiral shape so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and the second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0026] The internal terminal X21 is connected to the external terminal T21 of the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 of the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 of the second layer 230b via the conductive wiring Y23 and the via Z23. Note that the external terminals T21 to T23 are arranged linearly side by side and are used for wire bonding with the controller chip 210.

[0027] The secondary coil 231s is laid out in a spiral shape starting from the first end connected to the external terminal T24 and surrounding the periphery of the external terminal T24 counterclockwise, and the second end corresponding to its end point is connected to the external terminal T25. On the other hand, the secondary coil 232s is laid out in a spiral shape starting from the first end connected to the external terminal T26 and surrounding the periphery of the external terminal T26 clockwise, and the second end corresponding to its end point is connected to the external terminal T25. Note that the external terminals T24, T25, and T26 are arranged linearly side by side in the order shown in the figure and are used for wire bonding with the driver chip 220.

[0028] The secondary coils 231s and 232s are respectively AC-connected to the primary coils 231p and 232p by magnetic coupling and are DC-insulated from the primary coils 231p and 232p. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230 and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0029] <Transformer Chip (2-Channel Type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a 2-channel type transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing the layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing the layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7 and shows the isolation structure 130.

[0030] Referring to FIGS. 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped-shaped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0031] A wide-bandgap semiconductor is composed of a semiconductor having a bandgap exceeding that of silicon (about 1.12 eV). The bandgap of the wide-bandgap semiconductor is preferably 2.0 eV or more. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0032] In this form, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a laminated structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0033] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (a rectangular shape in this form) in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal direction Z.

[0034] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face each other in the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face each other in the first direction X. The chip sidewalls 44A to 44D are composed of ground surfaces.

[0035] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a rectangular shape (a rectangular shape in this form) that aligns with the first main surface 42 in plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0036] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a flush grinding surface with the chip sidewalls 44A to 44D.

[0037] The insulating layer 51 has a multilayer insulating laminated structure including a bottommost insulating layer 55, a topmost insulating layer 56, and a plurality (11 layers in this form) of interlayer insulating layers 57. The bottommost insulating layer 55 is an insulating layer that directly covers the first main surface 42. The topmost insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottommost insulating layer 55 and the topmost insulating layer 56. In this form, the bottommost insulating layer 55 has a single-layer structure containing silicon oxide. In this form, the topmost insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottommost insulating layer 55 and the thickness of the topmost insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0038] The plurality of interlayer insulating layers 57 each have a laminated structure including a first insulating layer 58 on the bottommost insulating layer 55 side and a second insulating layer 59 on the topmost insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0039] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 preferably exceeds the thickness of the first insulating layer 58.

[0040] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of stacked layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the insulation breakdown voltage (dielectric breakdown withstand voltage) to be achieved. Also, the insulating materials of the bottommost insulating layer 55, the topmost insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to specific insulating materials.

[0041] The semiconductor device 5 includes a first functional device 45 formed in the insulating layer 51. The first functional device 45 includes one or a plurality (a plurality in this form) of transformers 21 (corresponding to the aforementioned transformer). That is, the semiconductor device 5 is a multi-channel type device including a plurality of transformers 21. The plurality of transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating sidewalls 53A to 53D. The plurality of transformers 21 are formed at intervals in the first direction X.

[0042] Specifically, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D formed in this order from the insulating sidewall 53C side to the insulating sidewall 53D side in a plan view. The plurality of transformers 21A to 21D each have a similar structure. Hereinafter, the structure of the first transformer 21A will be described as an example. Regarding the description of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D, the description of the structure of the first transformer 21A shall apply mutatis mutandis and will be omitted.

[0043] Referring to FIGS. 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this form, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0044] The low-potential coil 22 is formed on the side of the lowermost insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the uppermost insulating layer 56 (insulating main surface 52) with respect to the low-potential coil 22 within the insulating layer 51. That is, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 interposed therebetween. The arrangement positions of the low-potential coil 22 and the high-potential coil 23 are arbitrary. Further, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 interposed therebetween.

[0045] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of stacked interlayer insulating layers 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this form, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counted from the side of the lowermost insulating layer 55. In this form, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counted from the side of the uppermost insulating layer 56.

[0046] The low-potential coil 22 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 spirally wound between the first inner end 24 and the first outer end 25. The first spiral portion 26 is spirally wound and extends in an elliptical shape (oval shape) in plan view. The portion forming the innermost periphery of the first spiral portion 26 demarcates an elliptical first inner region 66 in plan view.

[0047] The number of turns of the first spiral portion 26 may be 5 or more and 30 or less. The width of the first spiral portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first spiral portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first spiral portion 26 is defined by the width in the direction orthogonal to the spiral direction. The first winding pitch of the first spiral portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions in the direction orthogonal to the spiral direction in the first spiral portion 26.

[0048] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in FIG. 5 and the like. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in plan view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in plan view according to the winding shape of the first spiral portion 26.

[0049] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recessed space in the interlayer insulating layer 57. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0050] The high-potential coil 23 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 spirally wound between the second inner end 27 and the second outer end 28. The second spiral portion 29 is spirally wound and extends in an elliptical shape (oval shape) in plan view. The portion forming the innermost peripheral edge of the second spiral portion 29 demarcates a second inner region 67 having an elliptical shape in plan view in this form. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0051] The number of turns of the second spiral portion 29 may be 5 or more and 30 or less. The number of turns of the second spiral portion 29 with respect to the number of turns of the first spiral portion 26 is adjusted according to the voltage value to be boosted. Preferably, the number of turns of the second spiral portion 29 exceeds the number of turns of the first spiral portion 26. Of course, the number of turns of the second spiral portion 29 may be less than the number of turns of the first spiral portion 26, or may be equal to the number of turns of the first spiral portion 26.

[0052] The width of the second spiral portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second spiral portion 29 is 1 μm or more and 3 μm or less. The width of the second spiral portion 29 is defined by the width in the direction orthogonal to the spiral direction. Preferably, the width of the second spiral portion 29 is equal to the width of the first spiral portion 26.

[0053] The second winding pitch of the second spiral portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the direction orthogonal to the spiral direction in the second spiral portion 29. Preferably, the second winding pitch is equal to the first winding pitch of the first spiral portion 26.

[0054] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in FIG. 6 and the like. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a plan view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a plan view according to the winding shape of the second spiral portion 29.

[0055] The high-potential coil 23 is preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes a barrier layer and a main body layer, similarly to the low-potential coil 22.

[0056] Referring to FIG. 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0057] The plurality of low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low-potential terminals 11 are formed in a region on the insulating side wall 53B side at an interval in the second direction Y from the plurality of transformers 21A to 21D and are arranged at an interval in the first direction X.

[0058] The plurality of low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this form, two of the plurality of low-potential terminals 11A to 11F are formed respectively. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0059] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in a region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in a region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0060] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0061] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0062] The plurality of high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low-potential terminals 11. Specifically, the plurality of high-potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals from the plurality of low-potential terminals 11 in the second direction Y and are arranged at intervals in the first direction X.

[0063] The plurality of high-potential terminals 12 are respectively formed in regions that are close to the corresponding transformers 21A to 21D in a plan view. For the high-potential terminals 12 to be close to the transformers 21A to 21D means that the distance between the high-potential terminals 12 and the transformers 21 in a plan view is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0064] Specifically, the plurality of high-potential terminals 12 are formed at intervals along the first direction X so as to face the plurality of transformers 21A to 21D along the first direction X in a plan view. More specifically, the plurality of high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and the region between adjacent high-potential coils 23 in a plan view. As a result, the plurality of high-potential terminals 12 are arranged in a line with the plurality of transformers 21A to 21D in the first direction X in a plan view.

[0065] The plurality of high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this form, two of the plurality of high-potential terminals 12A to 12F are formed respectively. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0066] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0067] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0068] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0069] Referring to FIGS. 5 to 7, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34 respectively formed in the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0070] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coils 22 of the first transformer 21A and the second transformer 21B at the same potential. Also, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coils 22 of the third transformer 21C and the fourth transformer 21D at the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of the transformers 21A to 21D at the same potential.

[0071] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coils 23 of the first transformer 21A and the high-potential coils 23 of the second transformer 21B at the same potential. Also, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coils 23 of the third transformer 21C and the high-potential coils 23 of the fourth transformer 21D at the same potential. In this form, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D at the same potential.

[0072] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. Hereinafter, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. Regarding the description of the structures of the other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A shall apply mutatis mutandis and will be omitted.

[0073] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (a plurality in this form) pad plug electrodes 76, and one or more (a plurality in this form) substrate plug electrodes 77.

[0074] The through-wiring 71, the low-potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrodes 76, and the substrate plug electrodes 77 are preferably formed of the same conductive material as the low-potential coil 22 or the like. That is, the through-wiring 71, the low-potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrodes 76, and the substrate plug electrodes 77 preferably each include a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0075] The through-wiring 71 penetrates a plurality of interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this form, the through-wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end portion on the uppermost insulating layer 56 side and a lower end portion on the lowermost insulating layer 55 side. The upper end portion of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end portion of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0076] In this form, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed of the same conductive material as the low-potential coil 22 or the like. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0077] The first electrode layer 78 forms the upper end portion of the through-wiring 71. The second electrode layer 79 forms the lower end portion of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0078] The plurality of wiring plug electrodes 80 are respectively embedded in a plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area smaller than the planar area of the first electrode layer 78 and the planar area of the second electrode layer 79.

[0079] Note that the number of stacked wiring plug electrodes 80 matches the number of stacked interlayer insulating layers 57. In this form, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating through the plurality of interlayer insulating layers 57 may be formed.

[0080] The low potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low potential coil 22) within the same interlayer insulating layer 57 as the low potential coil 22. The low potential connection wiring 72 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. The low potential connection wiring 72 preferably has a planar area exceeding the planar area of the wiring plug electrode 80. The low potential connection wiring 72 is electrically connected to the first inner end 24 of the low potential coil 22.

[0081] The lead-out wiring 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this form, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counted from the bottommost insulating layer 55. The lead-out wiring 73 includes a first end portion on one side, a second end portion on the other side, and a wiring portion connecting the first end portion and the second end portion. The first end portion of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end portion of the through-wiring 71. The second end portion of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end portion and the second end portion.

[0082] The first connection plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first end portions of the through-wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the region between the low potential connection wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second end portions of the low potential connection wiring 72 and the lead-out wiring 73.

[0083] The plurality of pad plug electrodes 76 are formed in the region between the low potential terminal 11 (the first low potential terminal 11A) and the through wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper end portions of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this form, the substrate plug electrode 77 is formed in the region between the semiconductor chip 41 and the first end portion of the lead-out wiring 73, and is electrically connected to the semiconductor chip 41 and the first end portion of the lead-out wiring 73, respectively.

[0084] Referring to FIGS. 6 and 7, the plurality of first high potential wirings 33 are electrically connected to the corresponding high potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high potential coils 23), respectively. The plurality of first high potential wirings 33 each have the same structure. Hereinafter, the structure of the first high potential wiring 33 connected to the first high potential terminal 12A and the first transformer 21A will be described as an example. Regarding the description of the structures of the other first high potential wirings 33, the description of the structure of the first high potential wiring 33 connected to the first transformer 21A shall apply mutatis mutandis and will be omitted.

[0085] The first high potential wiring 33 includes a high potential connection wiring 81 and one or a plurality (a plurality in this form) of pad plug electrodes 82. The high potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low potential coil 22 or the like. That is, the high potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a main body layer, similar to the low potential coil 22 or the like.

[0086] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulation layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the breakdown voltage of the insulation layer 51 is enhanced.

[0087] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulation layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0088] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0089] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulation layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0090] The dummy pattern 85 is formed in a pattern (a discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to that of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0091] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 with respect to the normal direction Z. Note that that the dummy pattern 85 is closer to the high-potential coil 23 with respect to the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0092] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. With respect to the normal direction Z, the smaller the distance between the dummy pattern 85 and the high-potential coil 23, the more the electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed. The dummy pattern 85 includes a plurality of dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0093] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 with respect to the normal direction Z. That the high-potential dummy pattern 86 is close to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0094] The dummy pattern 85 includes a floating dummy pattern formed in an electrically floating state in the insulating layer 51 so as to be located around the transformers 21A to 21D.

[0095] In this form, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the region around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed in an end shape or an endless shape.

[0096] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed.

[0097] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. The floating dummy pattern may be composed of a plurality of floating lines.

[0098] Referring to FIG. 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in the device region 62. The second functional device 60 is formed by using the surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by the insulating layer 51 (the bottommost insulating layer 55). In FIG. 7, the second functional device 60 is schematically shown by a broken line shown in the surface layer portion of the first main surface 42.

[0099] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. Specific descriptions of the low-potential wiring and the high-potential wiring related to the second functional device 60 are omitted.

[0100] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of a passive device, a semiconductor rectifying device, and a semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0101] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT [Bipolar Junction Transistor], a MISFET [Metal Insulator Semiconductor Field Effect Transistor], an IGBT [Insulated Gate Bipolar Junction Transistor], and a JFET [Junction Field Effect Transistor].

[0102] Referring to FIGS. 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 suppresses the entry of moisture and cracks from the outer region 63 into the device region 62.

[0103] The device region 62 is a region including a first functional device 45 (a plurality of transformers 21), a second functional device 60, a plurality of low potential terminals 11, a plurality of high potential terminals 12, a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, a second high potential wiring 34, and a dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0104] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (a plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connected to the device region 62.

[0105] In a plan view, the seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D. In this form, the seal conductor 61 is formed in a square ring shape (specifically, a rectangular ring shape) in a plan view. Thereby, the seal conductor 61 divides the device region 62 having a square shape (specifically, a rectangular shape) in a plan view. Also, the seal conductor 61 divides the outer region 63 having a square ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view.

[0106] Specifically, the seal conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending in a wall shape between the upper end portion and the lower end portion. In this form, the upper end portion of the seal conductor 61 is formed at a distance from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this form, the upper end portion of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end portion of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end portion of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end portion of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end portion side.

[0107] Thus, in this form, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Further, the seal conductor 61 faces the first functional device 45 (a plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52 within the insulating layer 51. The seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating main surface 52 within the insulating layer 51.

[0108] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this form) seal via conductors 65. The number of the seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low potential coil 22. That is, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22 and the like.

[0109] The plurality of seal plug conductors 64 are respectively embedded in the plurality of interlayer insulating layers 57 and are each formed in a rectangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The plurality of seal plug conductors 64 are laminated from the bottommost insulating layer 55 toward the topmost insulating layer 56 so as to be connected to each other. The number of laminated seal plug conductors 64 matches the number of laminated interlayer insulating layers 57. Of course, one or more seal plug conductors 64 penetrating the plurality of interlayer insulating layers 57 may be formed.

[0110] If an annular seal conductor 61 is formed by the aggregate of the plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped manner. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of end-shaped strip portions. However, in view of the risk of entry of moisture and cracks into the device region 62, the plurality of seal plug conductors 64 are preferably formed in an endless (annular) shape.

[0111] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottommost insulating layer 55. The plurality of seal via conductors 65 are formed at intervals from the semiconductor chip 41 and are connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area less than the planar area of the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of the seal plug conductor 64.

[0112] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the seal conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in a direction orthogonal to the direction in which the seal conductor 61 extends.

[0113] Referring to FIGS. 7 and 8, the semiconductor device 5 further includes a separation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61, which electrically isolates the seal conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this form, the separation structure 130 is composed of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0114] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 preferably consists of a LOCOS (local oxidation of silicon) film as an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0115] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this form, the separation structure 130 is formed in a square ring shape (specifically, a rectangular ring shape) in a plan view. The separation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 bites into the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the separation structure 130.

[0116] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A partitions the region (that is, the device region 62) where the second functional device 60 is formed in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0117] The outer end portion 130B is exposed from the chip side walls 44A to 44D of the semiconductor chip 41 and is continuous with the chip side walls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip side walls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip side walls 44A to 44D of the semiconductor chip 41 and the insulating side walls 53A to 53D of the insulating layer 51. Of course, in other forms, the outer end portion 130B may be formed in the first main surface 42 at an interval from the chip side walls 44A to 44D.

[0118] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body portion 130C that is spaced apart from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms in addition to the field insulating film 131.

[0119] Referring to FIG. 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0120] In this form, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is impurity-free silicon oxide. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the breakdown voltage on the high-potential coil 23 can be increased.

[0121] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds that of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0122] The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass) as an example of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the breakdown voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure composed of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0123] The inorganic insulating layer 140 covers the entire area of the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the region outside the seal conductor 61. The plurality of low-potential pad openings 143 expose the plurality of low-potential terminals 11 respectively. The plurality of high-potential pad openings 144 expose the plurality of high-potential terminals 12 respectively. The inorganic insulating layer 140 may have an overlap portion that rides on the peripheral edge of the low-potential terminal 11. The inorganic insulating layer 140 may have an overlap portion that rides on the peripheral edge of the high-potential terminal 12.

[0124] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0125] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Further, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low potential coil 22 and the high potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. According to these structures, it is possible to suppress the thickening of the inorganic insulating layer 140 and the organic insulating layer 145, and at the same time, the insulation breakdown voltage on the high potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0126] The organic insulating layer 145 includes a first portion 146 that covers the low potential side region and a second portion 147 that covers the high potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 interposed therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rides on the peripheral edge (overlapping portion) of the low potential pad opening 143.

[0127] The second portion 147 is formed at an interval from the first portion 146, and exposes the inorganic insulating layer 140 from between the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose a plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlapping portion that rides on the peripheral edge (overlapping portion) of the high potential pad opening 144.

[0128] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers a plurality of high potential coils 23, a plurality of high potential terminals 12, a first high potential dummy pattern 87, a second high potential dummy pattern 88, and a floating dummy pattern 121.

[0129] Embodiments of the present invention can be implemented in still other forms. In the foregoing embodiments, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form having only the second functional device 60 without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects (excluding the effects related to the dummy pattern 85) as those described in the first embodiment.

[0130] That is, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the high-potential terminal 12 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the low-potential terminal 11 and the seal conductor 61 can be suppressed.

[0131] Also, in the foregoing embodiments, an example in which the second functional device 60 is formed has been described. However, the second functional device 60 is not necessarily required and may be removed.

[0132] Also, in the foregoing embodiments, an example in which the dummy pattern 85 is formed has been described. However, the dummy pattern 85 is not necessarily required and may be removed.

[0133] Also, in the foregoing embodiments, an example in which the first functional device 45 has a multi-channel type including a plurality of transformers 21 has been described. However, a first functional device 45 having a single-channel type including a single transformer 21 may be adopted.

[0134] <Transformer array> FIG. 9 is a plan view (top view) schematically showing an example of a transformer array in a two-channel type of transchip 300 (corresponding to the prior semiconductor device 5). The transchip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0135] In the transchip 300, pads a1 and b1 are connected to one end of the secondary coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0136] Also, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0137] Note that the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not shown in this figure. However, each primary coil basically has the same configuration as the secondary coils L1s to L4s, and is arranged directly below each of the secondary coils L1s to L4s in a form facing each of the secondary coils L1s to L4s.

[0138] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0139] Also, pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Also, pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0140] However, for the above pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4, they are drawn out from the inside to the surface of the transformer chip 300 via vias (not shown).

[0141] Among the above plurality of pads, pads a1 to a8 respectively correspond to the first current supply pads, and pads b1 to b8 respectively correspond to the first voltage measurement pads. Also, pads c1 to c4 respectively correspond to the second current supply pads, and pads d1 to d4 respectively correspond to the second voltage measurement pads.

[0142] Therefore, in the case of the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is of course possible to reject defective products in which a disconnection has occurred in each coil, and it is also possible to appropriately reject defective products in which an abnormal resistance value (for example, a short circuit between coils) has occurred in each coil. Consequently, it becomes possible to prevent the outflow of defective products into the market.

[0143] Regarding the transformer chip 300 that has passed the above defective product inspection, the plurality of pads may be used as connection means to the primary chip and the secondary chip (for example, the aforementioned controller chip 210 and driver chip 220).

[0144] Specifically, pad a1 and b1, pad a2 and b2, pad a3 and b3, and pad a4 and b4 may be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pad c1 and d1, and pad c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0145] On the other hand, pad a5 and b5, pad a6 and b6, pad a7 and b7, and pad a8 and b8 may be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pad c3 and d3, and pad c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0146] Here, as shown in FIG. 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled manner for each respective signal transmission direction. Speaking with reference to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary chip to the secondary chip are paired as the first pair by the first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary chip to the primary chip are paired as the second pair by the second guard ring 306.

[0147] The reason for performing such coupling is to ensure withstand voltage between the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 when they are laminated in a form where the primary coil and the secondary coil are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0148] Note that the first guard ring 305 and the second guard ring 306 may be connected to a low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0149] Also, in the transchip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Also, pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Also, pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Also, pads c4 and d4 are shared with the corresponding respective primary coils. By adopting such a configuration, it is possible to reduce the number of pads and downsize the transchip 300.

[0150] Also, as shown in FIG. 9, it is desirable that the primary coils and the secondary coils forming the first transformer 301 to the fourth transformer 304 be wound so as to be rectangular (or a track shape with rounded corners) in a plan view of the transchip 300. By adopting such a configuration, the area of the overlapping portion between the primary coil and the secondary coil increases, and it is possible to improve the transmission efficiency of the transformer.

[0151] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, arrangement of the coils, and the arrangement of the pads are arbitrary. Also, the chip structure and the transformer arrangement described so far can be applied to a semiconductor device in which coils are integrated on a semiconductor chip.

[0152] <First Embodiment> A first embodiment of the present disclosure will be described. FIG. 10 is a configuration diagram of an example of a signal transmission device A using an isolation amplifier 400 according to the first embodiment. As shown in FIG. 10, the signal transmission device A includes an isolation amplifier 400 and a subsequent-stage AD converter 500 connected to the isolation amplifier 400. The signal transmission device A is configured to transmit analog input signals AgnP and AgnN, which are differential signals, from an input-side device DvI to an output-side device DvO. Examples of the input-side device DvI include sensors configured to detect surrounding conditions such as optical sensors and temperature sensors. Examples of the output-side device DvO include processing devices such as computers. The above are examples and are not limited thereto.

[0153] <isolation amplifier 400> As shown in FIG. 10, the isolation amplifier 400 includes a primary-side AD converter 410, a secondary-side DA converter 420, an isolator 430, and a switching circuit 440. The isolation amplifier 400 also has a first input terminal InP and a second input terminal InN. The isolation amplifier 400 further has an output terminal Out and a control terminal Ct.

[0154] Analog input signals AgnP and AgnN, which are differential input signals, are input to the isolation amplifier 400 via the first input terminal InP and the second input terminal InN. The primary-side AD converter 410 converts the input analog input signals AgnP and AgnN into a digital signal Dgn1. The primary-side AD converter 410 has a fixed output range. The primary-side AD converter 410 is an AD converter corresponding to differential inputs. However, it is not limited thereto, and the primary-side AD converter 410 may be an AD converter corresponding to single inputs, or may be an AD converter corresponding to both differential inputs and single inputs.

[0155] A primary-side AD converter 410 is connected to the primary side of the isolator 430, and a secondary-side DA converter 420 is connected to the secondary side. The isolator 430 is an insulating element that utilizes magnetic coupling and has a primary-side coil 431 and a secondary-side coil 432. In the isolator 430, the primary-side coil 431 and the secondary-side coil 432 are electrically insulated but electromagnetically coupled. The isolator 430 has the same configuration as the transchip 230 of the signal transmission device 200.

[0156] The isolator 430 has a configuration that can transmit a signal from the primary side to the secondary side while suppressing the transmission of spike current generated in the primary-side circuit, noise superimposed on the current flowing through the primary-side circuit, etc. to the secondary-side circuit. Conversely, it can also suppress the transmission of spike current, noise, etc. generated in the secondary-side circuit to the primary-side circuit.

[0157] The primary-side coil 431 is connected to the primary-side AD converter 410, and a digital signal Dgn1 is input to the primary-side coil 431. In the isolator 430, the digital signal Dgn1 input to the primary-side coil 431 is transmitted to the secondary-side coil 432 by electromagnetic induction. As a result, the isolation amplifier 400 has a configuration that can transmit information from the primary side to the secondary side while suppressing the transmission of spike current, noise, etc.

[0158] The secondary-side DA converter 420 is connected to the secondary-side coil 432. The digital signal Dgn1 transmitted from the primary-side coil 431 to the secondary-side coil 432 by electromagnetic induction is converted into an analog output signal AgnT by the secondary-side DA converter 420. The secondary-side DA converter 420 outputs the analog output signal AgnT to the subsequent-stage AD converter 500 provided outside the isolation amplifier 400 via the output terminal Out.

[0159] The switching circuit 440 has three input terminals 441, 442, 443 and one output terminal 444. The input terminal 441 is connected to a common power supply Vin1 that supplies a first voltage V1, and the first voltage V1 is input to the input terminal 441.

[0160] Also, the input terminal 442 is connected to an individual power supply Vin2 that supplies a second voltage V2 different from the first voltage V1. Further, the input terminal 443 is connected to a control terminal Ct. A control signal for controlling the switching circuit 440 is input to the control terminal Ct. Note that the individual power supply Vin2 may be an external power supply that supplies the second voltage V2 from the outside, or may be an internal power supply that generates the second voltage V2 from the first voltage V1 generated from the common power supply Vin1.

[0161] The output terminal 44 is connected to the secondary-side DA converter 420, and either the first voltage V1 or the second voltage V2 is output to the secondary-side DA converter 420. The secondary-side DA converter 420 generates an analog output signal AgnT from the digital signal Dgn1 with the first voltage V1 or the second voltage V2 as a reference. That is, the range of the secondary-side DA converter 420 changes depending on the voltage supplied from the switching circuit 440.

[0162] Here, the operation of the switching circuit 440 will be described with reference to the drawings. FIG. 11 is a timing chart showing the operation of the switching circuit 440. FIG. 12 is a configuration diagram of the signal transmission device A when the subsequent-stage AD converter 500 corresponds to a ratio metric input. FIG. 13 is a configuration diagram of the signal transmission device A when the subsequent-stage AD converter 500 corresponds to a non-ratio metric input. The timing chart shown in FIG. 11 shows the relationship between the control signal SgC and the voltage output from the output terminal 444.

[0163] The control signal SgC is a voltage signal that takes a low level (Lo) lower than a threshold value or a high level (Hi) of a voltage higher than the low level (Lo). The switching circuit 440 switches between a state in which the input terminal 441 and the output terminal 444 are connected and a state in which the input terminal 442 and the output terminal 444 are connected according to the signal input to the input terminal 443.

[0164] As shown in FIG. 11, when the control signal SgC input to the input terminal 443 is higher than the threshold value, that is, at the high level (Hi), the switching circuit 440 causes the first voltage V1 to be input to the secondary-side DA converter 420. Also, when the control signal SgC input to the input terminal 443 is lower than the threshold value, that is, at the low level (Lo), the switching circuit 440 causes the second voltage V2 to be input to the secondary-side DA converter 420.

[0165] As shown in FIG. 12, when the control signal SgC is at the high level (Hi), the switching circuit 440 connects the input terminal 441 and the output terminal 444. Thereby, the first voltage V1 is supplied from the output terminal 444 to the secondary-side DA converter 420.

[0166] As shown in FIG. 13, when the control signal SgC is at the low level (Lo), the switching circuit 440 connects the input terminal 442 and the output terminal 444. Thereby, the second voltage V2 is supplied from the output terminal 444 to the secondary-side DA converter 420.

[0167] In the signal transmission device A, when the subsequent-stage AD converter 500 is configured to handle a ratiometric input, a high-level (Hi) control signal SgC is input to the control terminal Ct. Also, when the subsequent-stage AD converter 500 is configured to handle a non-ratiometric input, a low-level (Lo) control signal SgC is input.

[0168] Note that the control signal SgC can be supplied, for example, from a controller (not shown). However, it is not limited thereto. The signal transmission device A may be configured to supply a control signal SgC of a predetermined high level (Hi) or low level (Lo) voltage, and input the control signal SgC of high level (Hi) or low level (Lo) to the input terminal 443. Also, when the subsequent-stage AD converter 500 is connected to the isolation amplifier 400, the subsequent-stage AD converter 500 may be connected to the control terminal Ct, and the subsequent-stage AD converter 500 may supply the control signal SgC to the control terminal Ct.

[0169] <subsequent-stage AD converter 500> The subsequent-stage AD converter 500 is disposed outside the isolation amplifier 400. The subsequent-stage AD converter 500 converts the analog output signal AgnT output from the output terminal Out of the isolation amplifier 400 into a digital output signal Dgn2 and outputs it to the output-side device DvO. The subsequent-stage AD converter 500 is connected to the common power supply Vin1, and a first voltage V1 is supplied to the subsequent-stage AD converter 500.

[0170] <Operation of signal transmission device A> The signal transmission device A has the above-described configuration. Next, the operation of the signal transmission device A will be described. In the signal transmission device A, the subsequent-stage AD converter 500 may be configured to correspond to a ratiometric input. When corresponding to a ratiometric input, the input range of the subsequent-stage AD converter 500 varies depending on the first voltage V1, which is the reference voltage.

[0171] In the signal transmission device A, when the subsequent-stage AD converter 500 corresponds to a ratiometric input, a high-level (Hi) control signal SgC is supplied to the control terminal Ct. As a result, the input terminal 441 and the output terminal 444 of the switching circuit 440 are connected, and the first voltage V1 is supplied to the secondary-side DA converter 420.

[0172] Then, the secondary-side DA converter 420 converts the digital signal Dgn1 into an analog output signal AgnT with the first voltage V1 as the reference voltage. By setting the reference voltage of the secondary-side DA converter 420 to the first voltage V1, the output range of the analog output signal AgnT can be matched to the input range of the subsequent-stage AD converter 500. Thereby, the secondary-side DA converter 420 can transmit an analog output signal AgnT without excess or deficiency to the input range of the subsequent-stage AD converter 500.

[0173] Also, there may be a case where the subsequent-stage AD converter 500 is configured to handle non-ratio metric inputs. At this time, the input range of the subsequent-stage AD converter 500 is fixed regardless of the first voltage V1 which is the reference voltage. Therefore, it is not necessary to set the reference voltage of the secondary-side DA converter 420 to the first voltage V1.

[0174] From this, in the signal transmission device A, when the subsequent-stage AD converter 500 is configured to handle non-ratio metric inputs, a low-level (Lo) control signal SgC is supplied to the control terminal Ct. Thereby, the input terminal 442 and the output terminal 444 of the switching circuit 440 are connected, and the second voltage V2 is supplied to the secondary-side DA converter 420.

[0175] The secondary-side DA converter 420 generates an analog output signal AgnT from the digital signal Dgn1 with the second voltage V2 as the reference voltage, and outputs it to the subsequent-stage AD converter 500.

[0176] As described above, in the isolation amplifier 400, when the connected subsequent-stage AD converter 500 has a ratio metric input, the reference voltage of the secondary-side DA converter 420 is set to the first voltage V1, and when it has a non-ratio metric input, the reference voltage of the secondary-side DA converter 420 is set to the second voltage V2.

[0177] By doing so, the isolation amplifier 400 can output an analog output signal AgnT within a range that can be stably detected by the subsequent-stage AD converter 500 regardless of whether the subsequent-stage AD converter 500 supports a photometric input. That is, the isolation amplifier 400 has versatility that can be used regardless of whether the subsequent-stage AD converter 500 supports a photometric input.

[0178] <Modification Example> FIG. 14 is a configuration diagram of an example of a signal transmission device B according to a modification of the first embodiment. The signal transmission device B shown in FIG. 14 is different from the signal transmission device A in that the isolation amplifier 400B does not include a switching circuit 440, but is substantially the same as the signal transmission device A in other respects. Therefore, substantially the same reference numerals are given to substantially the same parts of the signal transmission device B as those of the signal transmission device A, and detailed descriptions of the same parts are omitted.

[0179] In the signal transmission device B shown in FIG. 14, the subsequent-stage AD converter for photometric input is connected. In such a case, the isolation amplifier 400B may be directly connected to the common power supply Vin1 so that the switching circuit 440 is eliminated and the first voltage V1 is input to the secondary-side DA converter 420 of the isolation amplifier 400B. By configuring in this way, the configuration of the isolation amplifier 400B can be simplified.

[0180] <Second Embodiment> FIG. 15 is a configuration diagram of an example of the high-precision mode MdH of a signal transmission device C according to the second embodiment. FIG. 16 is a configuration diagram of an example of the normal mode MdN of the signal transmission device C according to the second embodiment.

[0181] The signal transmission device C shown in FIGS. 15 and 16 has input / output terminals IOt instead of the control terminal Ct of the isolation amplifier 400C, and the secondary-side DA converter 420C is different. It is different from the signal transmission device A, but in other respects, it is the same as the signal transmission device A. Therefore, the parts that are substantially the same as those of the signal transmission device A in the signal transmission device C are given the same reference numerals, and detailed descriptions of the same parts are omitted. Also, in the signal transmission device C, a subsequent-stage AD converter 500 (see FIG. 13) or a subsequent-stage AD converter 500C (see FIG. 15) is connected to the isolation amplifier 400C.

[0182] As shown in FIGS. 15 and 16, the secondary-side DA converter 420C of the signal transmission device C has two output-side terminals. The secondary-side DA converter 420C corresponds to differential output. That is, the secondary-side DA converter 420C is configured to be able to output differential output signals AgmP and AgmN to the output terminal Out and the input / output terminal IOt, respectively. Also, the secondary-side DA converter 420C is configured to be able to output a single analog output signal AgnT to the output terminal Out.

[0183] As shown in FIG. 15, in the isolation amplifier 400C, the input terminal 443 of the switching circuit 440 is connected to the input / output terminal IOt. Also, the differential output signal AgmN of the secondary-side DA converter 420C is configured to be input to the input / output terminal IOt.

[0184] The signal transmission device C is configured to be able to switch between a normal mode MdN (see FIG. 16) for transmitting a signal with a certain accuracy and a high-precision mode MdH (see FIG. 15) for transmitting a signal with higher accuracy than the normal mode MdN.

[0185] First, the high-precision mode MdH will be described. Generally, in the signal transmission device C, by using the differential output signal AgmP and the differential output signal AgmN, common-mode noise can be cut, so the influence of power supply fluctuations on the output is suppressed, and high-accuracy signal transmission becomes possible.

[0186] Therefore, when the signal transmission device C operates in the high-precision mode MdH, differential input is possible, and the subsequent-stage AD converter 500C configured to support non-ratio metric input is adopted. Also, the secondary-side DA converter 420C of the isolation amplifier 400C can output differentially and operates with a non-ratio metric output. At this time, the first voltage V1 is supplied from the common power supply Vin1 to the subsequent-stage AD converter 500C. Also, the secondary-side DA converter 420C is configured such that the second voltage V2 is input from the individual power supply Vin2 by the switching circuit 440.

[0187] Next, the normal mode MdN will be described. In the signal transmission device C, depending on the signal to be transmitted, there are times when accuracy higher than that of the high-precision mode MdH is not required. In such a case, the signal transmission device C operates in the normal mode MdN.

[0188] In the normal mode MdN, since there are advantages such as being able to simplify signal processing, as shown in FIG. 16, single input is possible, and the subsequent-stage AD converter 500C configured to support ratio metric input is adopted. Also, the secondary-side DA converter 420C of the isolation amplifier 400C can output singly and operates with a ratio metric output.

[0189] At this time, the analog output signal AgnT is output from the secondary-side DA converter 420C to the output terminal Out. Also, the subsequent-stage AD converter 500C is connected to the output terminal Out and is configured such that the analog output signal AgnT output to the output terminal Out is input. At this time, the first voltage V1 is supplied from the common power supply Vin1 to the subsequent-stage AD converter 500C. Also, the secondary-side DA converter 420C is configured such that the first voltage V1 is input from the common power supply Vin1 by the switching circuit 440.

[0190] Next, the operation of the switching circuit 440 will be described. FIG. 17 is a diagram showing waveforms of a control signal input to the switching circuit 440 and a reference current of the secondary-side DA converter 420C in the normal mode MdN and the high-precision mode MdH.

[0191] As shown in FIG. 15, in the high-precision mode MdH, the secondary-side DA converter 420C outputs differentially, and a differential output signal AgmN is input to the input terminal 443 of the switching circuit 440. As shown in FIG. 17, the amplitude of the differential output signal AgmN is smaller than the threshold Th for switching the switching circuit 440. That is, even when the differential output signal AgmN is input to the input terminal 443 of the switching circuit 440, the switching circuit 440 recognizes that a low-level signal is being input. Therefore, a second voltage V2 is input from the switching circuit 440 to the secondary-side DA converter 420C, and the secondary-side DA converter 420C operates to output non-ratio metrically with the second voltage V2 as a reference voltage.

[0192] On the other hand, as shown in FIG. 16, in the normal mode MdN, the input / output terminal IOt is connected to a switching power supply Vin3 that supplies a third voltage V3. The input terminal 443 of the switching circuit 440 is connected to the input / output terminal IOt, and the third voltage V3 is supplied to the input terminal 443 of the switching circuit 440. As shown in FIG. 17, the third voltage V3 is a voltage higher than the threshold Th. When the third voltage V3 is input to the input terminal 443, the switching circuit 440 determines that a high-level signal is input to the input terminal 443. As a result, a first voltage V1 from the common power supply Vin1 is input to the switching circuit 440. Thereby, the secondary-side DA converter 420C operates to output ratio metrically.

[0193] Note that the third voltage V3 may be supplied from a constant voltage circuit (not shown) provided outside the isolation amplifier 400C.

[0194] By having the isolation amplifier 400C have the structure shown above, the subsequent-stage AD converter 500C that accepts differential inputs and the subsequent-stage AD converter 500 that accepts single inputs can be connected to the common isolation amplifier 400C without increasing the number of terminals. As a result, the versatility of the isolation amplifier 400C can be enhanced. Also, by using the subsequent-stage AD converter 500C for differential inputs, common-mode noise can be cut, and the accuracy of the output due to power supply fluctuations can be improved. Further, when the accuracy may be lower than high accuracy, the subsequent-stage AD converter 500 for single inputs can be used. Thereby, the signal transmission device C can be configured according to the required accuracy using the common isolation amplifier 400C.

[0195] <Modification Example> FIG. 18 is a configuration diagram of an example of a signal transmission device D according to a modification of the second embodiment. In the signal transmission device D shown in FIG. 18, the isolation amplifier 400D is different from the signal transmission device C in that it does not include a switching circuit 440, but in other respects, it is substantially the same as the signal transmission device C. Therefore, substantially the same reference numerals are given to the substantially same parts of the signal transmission device D as those of the signal transmission device C, and detailed descriptions of the same parts are omitted.

[0196] In the signal transmission device D shown in FIG. 18, the subsequent-stage AD converter 500D is a ratiometric input and a differential input. In such a case, the switching circuit 440 may be eliminated, and the isolation amplifier 400D may be directly connected to the common power supply Vin1 so that the first voltage V1 is input to the secondary-side DA converter 420D of the isolation amplifier 400D. By configuring in this way, the configuration of the isolation amplifier 400D can be simplified.

[0197] Also, by configuring in this way, common-mode noise can be cut, so that a decrease in the accuracy of information transmission due to power supply fluctuations can be suppressed.

[0198] <Usage> FIG. 19 is a schematic diagram of a vehicle Vc which is an example of an apparatus in which the analog front end 600 is used. The analog front end 600 is an example of a signal transmission device A using the isolation amplifier 400.

[0199] As shown in FIG. 19, an ultrasonic sonar sensor 700 is attached to the vehicle Vc to detect the positions of obstacles such as a leading vehicle and a wall surface. The computer 800 mounted on the vehicle Vc has a configuration capable of acquiring the shape, position of the obstacle, and the distance to the obstacle based on the information from the ultrasonic sonar sensor 700 and controlling the vehicle Vc so that the vehicle Vc does not contact the obstacle.

[0200] The ultrasonic sonar sensor 700 outputs the detected information as an analog signal. The analog signal from the ultrasonic sonar sensor 700 is transmitted to the computer 800 via an analog front end 600 which is an example of a signal transmission device A using the isolation amplifier 400. As described above, the isolation amplifier 400 can accurately transmit a signal from the primary side to the secondary side while suppressing the transmission of a spike current, noise, etc. on the primary side. That is, by using the analog front end 600 using the isolation amplifier 400, it is possible to transmit the information detected by the ultrasonic sonar sensor 700 to the computer 800 accurately and without excess or deficiency.

[0201] In addition to the engine vehicle, the above vehicle Vc also includes electric vehicles (xEVs) such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle / plug-in hybrid vehicle (PHEV / PHV), or a fuel cell electric vehicle / fuel cell vehicle (FCEV / FCV).

[0202] In the above description, the analog front end 600 using the isolation amplifier 400 is described as being used for signal transmission between the sensor mounted on the vehicle Vc and the ultrasonic sonar sensor 700, but it is not limited to this. The isolation amplifier can be widely adopted in an analog front end used for signal transmission between various sensors mounted on the vehicle Vc, such as a sensor for acquiring GPS radio waves, a sensor for detecting the ambient brightness, etc., and a computer. Further, as the analog front end 600 shown in FIG. 19, the signal transmission device A using the isolation amplifier 400 is adopted, but it may also be configured by the signal transmission devices B, C, and D using the isolation amplifiers 400B, 400C, and 400D.

[0203] <Others> The above embodiments should be considered as illustrative in all respects and not restrictive. Also, the technical scope of the present invention is shown not by the description of the above embodiments but by the claims. Furthermore, it should be understood that all modifications belonging to the meaning and scope equivalent to the claims are included.

[0204] <Supplementary Note> The isolation amplifiers (400, 400B, 400C, 400D) described above include a primary side AD converter (410) configured to convert an analog input signal (AgnP, AgnN) into a digital signal (Dgn1), and a secondary side DA converter (420, 420C, 420D) that is electrically insulated from the primary side AD converter (410) and is configured to receive the digital signal (Dgn1) from the primary side AD converter (410) and convert it into an analog output signal (AgnT). When the input range of the subsequent stage AD converter (500, 500C, 500D) connected to the secondary side DA converter (420, 420C, 420D) changes depending on the power supply voltage, the secondary side DA converter (420, 420C, 420D) is configured to be supplied with the same voltage as the first voltage (V1) supplied to the subsequent stage AD converter (500, 500C, 500D) (first configuration).

[0205] In the isolation amplifier (400, 400C) of the first configuration, the secondary-side DA converter (420, 420C) is configured to be supplied with either the first voltage (V1) or a second voltage (V2) different from the first voltage (V1). When the input range of the subsequent-stage AD converter (500, 500C) is independent of the power supply voltage, the secondary-side DA converter (420, 420C) is supplied with the second voltage (V2) (second configuration).

[0206] In the isolation amplifier (400, 400C) of the first configuration, it further includes a switching circuit (440) connected to a common power supply (Vin1) that supplies the first voltage (V1) to the subsequent-stage AD converter (500, 500C) and an individual power supply (Vin2) that supplies the second voltage (V2), and having a configuration capable of supplying either the first voltage (V1) or the second voltage (V2) to the secondary-side DA converter (420, 420C). When the input range of the subsequent-stage AD converter (500, 500C) changes depending on the power supply voltage, the switching circuit (440) is controlled to supply the first voltage (V1) from the common power supply (Vin1) to the secondary-side DA converter (420, 420C). When the input range of the subsequent-stage AD converter (500, 500C) is independent of the power supply voltage, the switching circuit (440) is controlled to supply the second voltage (V2) from the individual power supply (Vin2) to the secondary-side DA converter (420, 420C) (third configuration).

[0207] In the isolation amplifier (400C) of the first configuration, the secondary-side DA converter (420C) can be supplied with either the first voltage (V1) or a second voltage (V2) different from the first voltage (V1), and has a configuration including an output terminal (Out) and an input / output terminal (IOt) used for input or output. The secondary-side DA converter (420C) is connected to each of the output terminal (Out) and the input / output terminal (IOt), and is capable of differential output to the output terminal (Out) and the input / output terminal (IOt), and is also capable of single output to the output terminal (Out). When the subsequent-stage AD converter (500C) supports differential input and the input range is independent of the power supply voltage, the output terminal (Out) and the input / output terminal (IOt) of the secondary-side DA converter (420C) are connected to each input terminal of the subsequent-stage AD converter (500C), and the second voltage (V2) is supplied to the secondary-side DA converter (420C). When the subsequent-stage AD converter (500C) has a single input and the input range depends on the power supply voltage, the subsequent-stage AD converter (500C) is connected to the output terminal (Out), and the first voltage (V1) is supplied to the secondary-side DA converter (420C) (the fourth configuration).

[0208] In the isolation amplifier (400C) of the fourth configuration, there is a switching circuit (440) connected to a common power supply (Vin1) supplying the first voltage (V1) and an individual power supply (Vin2) supplying the second voltage (V2), and having a configuration capable of supplying the first voltage (V1) or the second voltage (V2) to the secondary-side DA converter (420C). The switching circuit (440) has a configuration in which a third voltage (V3) can be supplied via the input / output terminal (IOt). When the third voltage (V3) is supplied to the switching circuit (440), it is a configuration (the fifth configuration) in which the first voltage (V1) is supplied to the secondary-side DA converter (420C).

[0209] In the isolation amplifier (400D) of the first configuration, the primary-side AD converter (410) is composed of a differential-input type AD converter, and the secondary-side DA converter (420D) is composed of a differential-output type DA converter (the sixth configuration).

[0210] An isolation amplifier (400, 400B, 400C, 400D) having any one of the above-described first to sixth configurations, and a subsequent-stage AD converter (500, 500C, 500D) configured such that the output of the isolation amplifier (400, 400B, 400C, 400D) is input thereto, and an analog front end (600) that converts an analog signal from an input-side device (DVI) into a digital signal and transmits the digital signal to an output-side device (DVO) is configured (seventh configuration).

[0211] A vehicle (Vc) having the analog front end (600) of the above-described seventh configuration and configured to transmit a signal from a sensor (700) to a computer (800) via the analog front end (600) is configured (eighth configuration).

Description of Reference Numerals

[0212] 11, 11A to 11F Low-potential terminals 12, 12A to 12F High-potential terminals 21, 21A to 21D Transformers 22 Low-potential coil (primary coil) 23 High-potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral part 27 Second inner end 28 Second outer end 29 Second spiral part 31 First low-potential wiring 32 Second low-potential wiring 33 First high-potential wiring 34 Second high-potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side walls 45 First functional device 5 Semiconductor device 51 Insulating layer 52 Insulating main surface Insulating side walls 53A to 53D Lowermost insulating layer 55 Topmost insulating layer 56 Interlayer insulating layer 57 First insulating layer 58 Second insulating layer 59 Second functional device 60 Seal conductor 61 Device region 62 Outer region 63 Seal plug conductor 64 Seal via conductor 65 First inner region 66 Second inner region 67 Through wiring 71 Low potential connection wiring 72 Lead-out wiring 73 First connection plug electrode 74 Second connection plug electrode 75 Pad plug electrode 76 Substrate plug electrode 77 First electrode layer 78 Second electrode layer 79 Wiring plug electrode 80 High potential connection wiring 81 Pad plug electrode 82 Dummy pattern 85 High potential dummy pattern 86 First high potential dummy pattern 87 Second high potential dummy pattern 88 First region 89 Second region 90 Third region 91 First connection part 92 First pattern 93 Second pattern 94 Third pattern 95 First outer peripheral line 96 Second outer peripheral line 97 First intermediate line 98 First connection line 99 Slit 100 Separation structure 130 Inorganic insulating layer 140 First inorganic insulating layer 141 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First part 147 Second part 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse reception circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary side coil 231s, 232s Secondary side coil 300 Transformer chip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring A, B, C, D Signal transmission device 400, 400B, 400C, 400D Isolation amplifier 420, 420C, 420D Subsequent stage AD converter 410 Primary side AD converter 420, 420C, 420D Secondary side DA converter 430 Isolator 431 Primary coil 432 Secondary coil 440 Switching circuit 441, 442, 443 Input terminals 444 Output terminal 100 Analog front end 200 Ultrasonic sonar sensor 300 Computer 500, 500C, 500D Rear - end AD converter 600 Analog front end 700 Ultrasonic sonar sensor 800 Computer AgmP, AgmN Differential output signal AgnP, AgnN Analog input signal AgnT Analog output signal Dgn1 Digital signal Dgn2 Digital output signal Ct Control terminal DvI Input - side device DvO Output - side device IOt Input / output terminal InN Second input terminal InP First input terminal Out Output terminal Vc Vehicle Vin1 Common power supply Vin2 Individual power supply Vin3 Switching power supply

Claims

1. A primary-side AD converter configured to convert an analog input signal into a digital signal, and a secondary-side DA converter that is electrically insulated from the primary-side AD converter and is configured to receive a digital signal from the primary-side AD converter and convert it into an analog output signal. In the case where the input range of a subsequent-stage AD converter connected to the secondary-side DA converter changes depending on the power supply voltage, an isolation amplifier configured to supply the secondary-side DA converter with the same voltage as a first voltage supplied to the subsequent-stage AD converter.

2. The secondary-side DA converter is configured to be capable of being supplied with either the first voltage or a second voltage different from the first voltage. The isolation amplifier according to claim 1, wherein when the input range of the subsequent-stage AD converter does not depend on the power supply voltage, the secondary-side DA converter is configured to be supplied with the second voltage.

3. A switching circuit connected to a common power supply that supplies the first voltage to the subsequent-stage AD converter and an individual power supply that supplies the second voltage, and having a configuration capable of supplying the first voltage or the second voltage to the secondary-side DA converter. The switching circuit is controlled to supply the first voltage from the common power supply to the secondary-side DA converter in the case where the input range of the subsequent-stage AD converter changes depending on the power supply voltage, and is configured to supply the second voltage from the individual power supply to the secondary-side DA converter in the case where the input range of the subsequent-stage AD converter does not depend on the power supply voltage. The isolation amplifier according to claim 2.

4. The secondary-side DA converter is configured to be capable of being supplied with either the first voltage or a second voltage different from the first voltage. It has an output terminal and an input / output terminal used for input or output. The secondary-side DA converter is connected to each of the output terminal and the input / output terminal, and is configured to be capable of differential output to the output terminal and the input / output terminal, and also capable of single output to the output terminal. When the subsequent-stage AD converter supports differential input and the input range is independent of the power supply voltage, the output terminal and the input / output terminal of the secondary-side DA converter are connected to each input terminal of the subsequent-stage AD converter, and the second voltage is supplied to the secondary-side DA converter. The isolation amplifier according to claim 1, wherein when the subsequent-stage AD converter has a single input and the input range depends on the power supply voltage, the subsequent-stage AD converter is connected to the input terminal, and the first voltage is supplied to the secondary-side DA converter.

5. It has a switching circuit connected to a common power supply for supplying the first voltage and an individual power supply for supplying the second voltage, and having a configuration capable of supplying the first voltage or the second voltage to the secondary-side DA converter. The isolation amplifier according to claim 4, wherein the switching circuit has a configuration in which a third voltage can be supplied via the input / output terminal, and when the third voltage is supplied to the switching circuit, the switching circuit is configured to supply the first voltage to the secondary-side DA converter.

6. The primary-side AD converter is composed of a differential-input type AD converter. The isolation amplifier according to claim 1, wherein the secondary-side DA converter is composed of a differential-output type DA converter.

7. An isolation amplifier having the configuration according to any one of claims 1 to 6. And a subsequent-stage AD converter configured such that the output of the isolation amplifier is input thereto. An analog front end configured to convert an analog signal from an input-side device into a digital signal and transmit it to an output-side device.

8. Having the analog front end according to claim 7. A vehicle configured to transmit a signal from a sensor to a computer via the analog front end.

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