Image sensor

Abstract

To provide an image sensor.SOLUTION: An image sensor includes: an uppermost layer that incudes a first substrate, a first front bonding pad disposed on the first substrate, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction, and a first shield structure spaced apart from the first front bonding pad in a first horizontal direction; an intermediate layer that includes a second substrate, a second front surface bonding pad disposed on the second substrate, a second front surface bonding plug connected to the second front surface bonding pad and extending in a vertical direction, and a second shield structure spaced apart from the second front surface bonding pad in a first horizontal direction, and is bonded to the uppermost layer at a lower part of the uppermost layer; and a lowermost layer that is bonded to the intermediate layer at a lower part of the intermediate layer. A vertical level of an upper surface of the first shield structure is higher than the vertical level of the upper surface of the first front surface bonding pad.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly, to an image sensor capable of improving coupling generated by miniaturization of the image sensor.

Background Art

[0002] An image sensor that captures an image and converts it into an electrical signal is used not only in general consumer electronic devices such as digital cameras, mobile phone cameras, and portable camcorders, but also in cameras mounted on automobiles, security devices, and robots. Image sensors are becoming smaller and smaller, and it is necessary to improve the coupling generated by miniaturization of the image sensor.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the present invention is to provide an image sensor capable of improving coupling generated by miniaturization of the image sensor.

[0004] The problem to be solved by the technical idea of the present invention is to provide an image sensor with improved electrical characteristics and reliability.

[0005] The problem to be solved by the technical idea of the present invention is to provide an image sensor with improved integration density.

[0006] The problem to be solved by the technical idea of the present invention is not limited to the problems described above, and other problems not mentioned will be clearly understood by those having ordinary knowledge in the technical field from the following description.

Means for Solving the Problems

[0007] To solve the above-described problems, an image sensor according to an embodiment of the technical idea of the present invention includes a first substrate including a first front surface and a first back surface opposite to the first front surface, a first front bonding pad disposed on the first front surface of the first substrate, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and a topmost layer including a first shield structure spaced apart from the first front bonding pad in a first horizontal direction; an intermediate layer bonded to the topmost layer below the topmost layer, the intermediate layer including a second substrate including a second front surface and a second back surface opposite to the second front surface, a second front bonding pad disposed on the second front surface of the second substrate, a second front bonding plug connected to the second front bonding pad and extending in the vertical direction toward the second front surface, and a second shield structure spaced apart from the second front bonding pad in the first horizontal direction; a bottommost layer bonded to the intermediate layer below the intermediate layer; wherein the bottommost layer includes a third substrate and a transistor disposed on the third substrate, and a vertical level of an upper surface of the first shield structure is higher than a vertical level of an upper surface of the first front bonding pad.

[0008] An image sensor according to an embodiment of the technical idea of the present invention includes a first substrate including a first front surface and a first back surface opposite to the first front surface, a first front bonding pad disposed on the first front surface of the first substrate, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and a first shield structure including a first portion spaced apart from the first front bonding pad in a first horizontal direction and a second portion spaced apart from the first front bonding plug in the first horizontal direction; a second substrate including a second front surface and a second back surface opposite to the second front surface, a second front bonding pad disposed on the second front surface of the second substrate, a second front bonding plug connected to the second front bonding pad and extending in the vertical direction toward the second front surface, and a second shield structure including a third portion spaced apart from the second front bonding pad in the first horizontal direction and a fourth portion spaced apart from the second front bonding plug in the first horizontal direction, the intermediate layer bonded to the uppermost layer below the uppermost layer; a lowermost layer bonded to the intermediate layer below the intermediate layer; and the lowermost layer includes a third substrate and a transistor disposed on the third substrate, and the first shield structure and the second shield structure may extend in a second horizontal direction intersecting the first horizontal direction.

[0009] An image sensor according to an embodiment of the technical idea of the present invention includes a first substrate including a first front surface and a first back surface opposite to the first front surface, a color filter and a lens sequentially stacked on the first back surface of the first substrate, a pixel separation layer penetrating the first substrate, a first transistor disposed on the first front surface of the first substrate, a first contact plug connected to the first transistor, a first wiring layer disposed under the first contact plug and connected to the first contact plug, a first front bonding plug disposed under the first wiring layer and connected to the first wiring layer, a first front bonding pad disposed under the first front bonding plug and in contact with the first front bonding plug, and a first shield structure spaced apart from the first front bonding pad in a first horizontal direction; an intermediate layer bonded to the uppermost layer at the lower part of the uppermost layer, including a second substrate including a second front surface and a second back surface opposite to the second front surface, a second transistor disposed on the second front surface of the second substrate, a second contact plug connected to the second transistor, a second wiring layer disposed on the second contact plug and connected to the second contact plug, a second front bonding plug disposed on the second wiring layer and connected to the second wiring layer, a second front bonding pad disposed on the second front bonding plug and in contact with the second front bonding plug, and a second shield structure spaced apart from the second front bonding pad in the first horizontal direction; a lowermost layer bonded to the intermediate layer at the lower part of the intermediate layer; the lowermost layer includes a third substrate and a transistor disposed on the third substrate, and a vertical level of an upper surface of the first shield structure is higher than a vertical level of an upper surface of the first front bonding pad.

Effect of the Invention

[0010] An image sensor according to the technical idea of the present invention may include a first front bonding pad, a first front bonding plug connected to the first front bonding pad, and a first shield structure spaced apart from the first front bonding pad and the first front bonding plug in a first horizontal direction. Further, the image sensor may include a second front bonding pad, a second front bonding plug connected to the second front bonding pad, and a second shield structure spaced apart from the second front bonding pad and the second front bonding plug in the first horizontal direction. The thickness of the first shield structure may be made thicker than the thickness of the first front bonding pad, and the thickness of the second shield structure may be made thicker than the thickness of the second front bonding pad. Thereby, coupling generated between the first front bonding plugs adjacent in the first horizontal direction and between the second front bonding plugs may be prevented. For the reasons as described above, the electrical characteristics and reliability of the image sensor may be improved.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments of the present invention can be implemented by any one or in combination of one or more. Therefore, the technical idea of the present invention is not construed as being limited to one embodiment.

[0013] In this specification, the singular form of a component may include a plurality of forms unless the context clearly indicates otherwise. In this specification, the drawings are exaggerated for clearer illustration of the invention. In this specification, the order such as first, second, etc. is for convenience of explanation and the present invention is not limited thereto.

[0014] FIG. 1 is a block diagram showing an image sensor according to an embodiment of the technical idea of the present invention.

[0015] Specifically, the image sensor 100 may include a pixel array 110, a row driver 120, a lamp signal generator 130, a counting code generator 140, an analog-to-digital conversion circuit 150 (hereinafter referred to as an ADC circuit), a data output circuit 180, and a timing controller 190. The image sensor 100 may further include a signal processing unit 195. The configuration including the ADC circuit 150 and the data output circuit 180 is referred to as a lead-out circuit.

[0016] The pixel array 110 may include a plurality of row lines RL and a plurality of column lines CL. The pixel array 110 is connected to the plurality of row lines RL and the plurality of column lines CL and may include a plurality of pixels PX arranged in a matrix. The plurality of pixels PX are also APS (active pixel sensor).

[0017] Each of the plurality of pixels PX includes at least one photoelectric conversion element. The pixel PX senses light using the photoelectric conversion element and outputs an image signal that is an electrical signal converted from the sensed light. For example, the photoelectric conversion element may include a photo diode, a phototransistor, a photogate, or a pinned photo diode.

[0018] Each of the plurality of pixels PX senses light in a specific spectral region. For example, some of the plurality of pixels PX can convert light in the red spectral region into an electrical signal, convert light in the green spectral region into an electrical signal, or convert light in the blue spectral region into an electrical signal. However, it is not limited thereto, and at least some of the plurality of pixels can convert light in the white spectral region into an electrical signal.

[0019] As another example, at least some of the plurality of pixels PX can convert light in other color spectrum regions into electrical signals. For example, at least some of the plurality of pixels PX can convert light in any one of the spectrum regions of yellow, cyan, or magenta into electrical signals.

[0020] A color filter for transmitting light in a specific spectrum region can be disposed above each of the plurality of pixels PX. The hue sensed by the pixel PX can be determined by the color filter. However, the present disclosure is not limited thereto. In some embodiments, a specific photoelectric conversion element can also convert light in a specific wavelength band into an electrical signal according to the level of the electrical signal applied to the photoelectric conversion element.

[0021] In some embodiments, each of the plurality of pixels PX has a dual conversion gain. The dual conversion gain includes a low conversion gain and a high conversion gain. Here, the conversion gain means the ratio at which the charge accumulated in the floating diffusion node (or floating diffusion region) is converted into a voltage. The charge generated by the photoelectric conversion element is transmitted to and accumulated in the floating diffusion node FD, and the charge accumulated in the floating diffusion node FD can be converted into a voltage by the conversion gain. At this time, the conversion gain is variable according to the capacitance of the floating diffusion node FD. If the capacitance increases, the conversion gain decreases, and if the capacitance decreases, the conversion gain can increase.

[0022] The row driver 120 can drive the pixel array 110 in row units. The row driver 120 can decode a row control signal (e.g., an address signal) received from the timing controller 190. The row driver 120 can select at least one of a plurality of row lines RL that make up the pixel array 110 in response to the decoded row control signal.

[0023] For example, the row driver 120 can generate a selection signal for selecting one row out of a plurality of rows. The selection signal can be transmitted to the pixel array 110 via the row line RL. The pixel array 110 outputs a pixel signal (e.g., a pixel voltage) from the row selected by the selection signal provided by the row driver 120. The pixel signal can include a reset signal and an image signal. The row driver 120 can transmit a control signal to the pixel array 110. The control signal is also a signal for outputting the pixel signal. The pixel PX can output the pixel signal by operating in response to the control signal.

[0024] The ramp signal generator 130 can generate a ramp signal (e.g., a ramp voltage) whose level rises or falls at a predetermined gradient under the control of the timing controller 190. The ramp signal RAMP can be provided to each of a plurality of correlated double sampling (CDS) circuits 160 provided in the ADC circuit 150.

[0025] The counting code generator 140 can generate a counting code CCD under the control of the timing controller 190. The counting code CCD can be provided to each of the plurality of counter circuits 170. In some embodiments, the counting code generator 140 can be implemented by a gray code generator. The counting code generator 140 can generate a plurality of code values with a resolution based on the set number of bits as the counting code CCD. For example, when a 10-bit code is set, the counting code generator 140 can generate a counting code CCD including 1024 code values that sequentially increase or decrease.

[0026] The ADC circuit 150 can include a plurality of CDS circuits 160 and a plurality of counter circuits 170. The ADC circuit 150 can convert the pixel signal input from the pixel array 110 into a pixel value that is a digital signal. Each pixel signal received via each of the plurality of column lines CL is converted into a pixel value that is a digital signal by the CDS circuit 160 and the counter circuit 170.

[0027] The CDS circuit 160 can compare the pixel signal received via the column line CL with the ramp signal RAMP and output the comparison result as a comparison result signal. The CDS circuit 160 can output a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low) when the level of the ramp signal RAMP and the level of the pixel signal are the same. The time point at which the level of the comparison signal transitions can be determined by the level of the pixel signal.

[0028] The CDS circuit 160 can sample the pixel signal provided from the pixel PX by the Correlated Double Sampling method. The CDS circuit 160 can sample the reset signal received as the pixel signal, compare the reset signal with the ramp signal RAMP, and generate a comparison signal by the reset signal. Thereafter, the CDS circuit 160 can sample the image signal correlated with the reset signal, compare the image signal with the ramp signal RAMP, and generate a comparison signal by the image signal.

[0029] The counter circuit 170 can count the time point of the level transition of the comparison result signal output from the CDS circuit 160 and output a count value. In some embodiments, the counter circuit 170 may include a latch circuit and an arithmetic circuit. The latch circuit can receive the counting code CCD from the counting code generator 140 and the comparison signal from the CDS circuit 160, and latch the code value of the counting code CCD when the level of the comparison signal transitions.

[0030] The latch circuit can latch the code value corresponding to the reset signal. For example, the latch circuit can latch the code values corresponding to the reset value and the image signal respectively. For example, the latch circuit can latch the image signal value. The arithmetic circuit can perform an operation on the reset value and the image signal value and generate an image signal value with the reset level of the pixel PX removed. The counter circuit 170 can output the image signal value with the reset level removed as the pixel value.

[0031] In this embodiment, the image sensor 100 includes the counting code generator 140, and the counter circuit 170 has been described as including a circuit that latches the code value of the counting code CCD received from the counting code generator 140, but it is not limited thereto.

[0032] In one embodiment, the image sensor 100 does not include a separate counting code generator 140, and the counter circuit 170 is also implemented by an up-counter and arithmetic circuit, or an up / down counter, or a bit-wise inversion counter in which the count value sequentially increases based on a counting clock signal provided from the timing controller 190.

[0033] The data output circuit 180 can output the pixel values output from the ADC circuit 150 after temporarily storing them. The data output circuit 180 may include a plurality of column memories 181 and a column decoder 182. The column memory 181 stores the pixel values received from the counter circuit 170. In some embodiments, each of the plurality of column memories 181 may be provided in the counter circuit 170. The plurality of pixel values stored in the plurality of column memories 181 can be output as image data IDT under the control of the column memory 181.

[0034] The timing controller 190 outputs control signals to the row driver 120, the ramp signal generator 130, the counting code generator 140, the ADC circuit 150, and the data output circuit 180 respectively, and can control the operations or timings of the row driver 120, the ramp signal generator 130, the counting code generator 140, the ADC circuit 150, and the data output circuit 180.

[0035] The signal processing unit 195 can perform noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, binning, etc. on the image data. In some embodiments, the signal processing unit 195 may be provided in an external processor of the image sensor 100.

[0036] FIG. 2 is a circuit diagram of an image sensor according to an embodiment of the technical idea of the present invention.

[0037] Referring to FIG. 2, the image sensor 100 may include a photodiode PD, a transfer transistor TX, a floating diffusion node FD, a conversion gain transistor DCG, a reset transistor RX, a source follower transistor SF, and a selection transistor SEL.

[0038] Each of the transfer transistor TX, the conversion gain transistor DCG, the reset transistor RX, the source follower transistor SF, and the selection transistor SEL may include a transfer gate TG, a conversion gain gate, a reset gate, a source follower gate SFG, and a selection gate.

[0039] In some embodiments, the transfer gate TG may be a vertical gate. In some embodiments, each of the conversion gain gate, the reset gate, the source follower gate SFG, and the selection gate may be a planar gate.

[0040] The photodiode PD may generate charges in proportion to the amount of incident light. The photodiode PD may generate electrons, which are negative charges, and holes, which are positive charges, in response to the incident light.

[0041] The photodiode PD may share the floating diffusion node FD, the reset transistor RX, the conversion gain transistor DCG, the source follower transistor SF, and the selection transistor SEL. Alternatively, although not shown, a plurality of photodiodes PD may be provided. The plurality of photodiodes PD may share one floating diffusion node FD, reset transistor RX, conversion gain transistor DCG, source follower transistor SF, and selection transistor SEL. However, the fact that one or eight photodiodes PD are provided is only one embodiment, and the number of photodiodes PD is not limited thereto.

[0042] The transfer gate TG is disposed between the photodiode PD and the floating diffusion node FD, and can transfer the charge generated by the photodiode PD to the floating diffusion node FD. The transfer transistor TX can include a transfer gate TG, a drain connected to the photodiode PD, and a source connected to the floating diffusion node FD.

[0043] The conversion gain transistor DCG can include a conversion gain gate, a source connected to the drain of the reset transistor RX, and a drain connected to the floating diffusion node FD.

[0044] The conversion gain transistor DCG can change the capacitance of the floating diffusion node FD by a conversion gain signal. If the conversion gain transistor DCG is turned on, the capacitance increases, so the image sensor 100 can operate in a low conversion gain mode. Conversely, if the conversion gain transistor DCG is turned off, the capacitance decreases, so the image sensor 100 can operate with a high conversion gain.

[0045] The reset transistor RX can include a reset gate, a source connected to the power supply voltage Vpix, and a drain connected to the source of the conversion gain transistor DCG. If the reset transistor RX is turned on by a reset control signal and the conversion gain transistor DCG is turned on by a conversion gain signal, the floating diffusion node FD can be reset based on the power supply voltage Vpix. Specifically, the charge accumulated in the floating diffusion node FD can be discharged and the floating diffusion node FD can be reset. At this time, a reset signal corresponding to the voltage level of the floating diffusion node FD can be output.

[0046] The gate of the source follower transistor SF can be electrically connected to the floating diffusion node FD. The source of the source follower transistor SF can be electrically connected to the source of the selection transistor SEL. The drain of the source follower transistor SF can be electrically connected to the power supply voltage Vpix.

[0047] The potential of the floating diffusion node FD changes according to the amount of charge accumulated in the floating diffusion node FD, and the source follower transistor SF can amplify the potential change at the floating diffusion node FD and output it as the source of the source follower transistor SF.

[0048] The source of the selection transistor SEL can be electrically connected to the selection gate and the source of the source follower transistor SF. The drain of the selection transistor SEL can be electrically connected to the output voltage line Vout.

[0049] FIG. 3 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention. FIG. 4 is an enlarged view of the PP1 portion of FIG. 3. Specifically, the image sensor EX1 in FIG. 3 is also an embodiment in which the image sensor 100 in FIG. 1 is implemented.

[0050] Referring to FIGS. 3 and 4, the image sensor EX1 may include the pixel PX in FIG. 1. The image sensor EX1 may include the uppermost layer 200, the intermediate layer 300, and the lowermost layer 400.

[0051] The intermediate layer 300 and the uppermost layer 200 can be sequentially stacked on the lowermost layer 400. The image sensor EX1 can be composed of three layers in which the intermediate layer 300 and the uppermost layer 200 are stacked on the lowermost layer 400. The image sensor EX1 can be composed of three layers in which the lowermost layer 400, the intermediate layer 300, and the uppermost layer 200 are bonded to each other.

[0052] The transistors described below may include planar transistors, MBC (multi bridge channel) transistors, GAA (gate all around) transistors, or Fin FET transistors (Fin FET: field effect transistor).

[0053] The top layer 200 may include a first substrate 201, a pixel isolation layer 217, a color filter 219, a lens 221, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first via plug 209, a first front bonding pad 211, a first front bonding plug 213, a first shield structure 230, a first insulating layer 215, and a first passivation layer 216.

[0054] The first substrate 201 may be a silicon substrate. The first substrate 201 may include a first front surface 201f and a first back surface 201b opposite to the first front surface 201f. A photodiode (PD in FIG. 2, hereinafter, the drawing reference numeral is omitted) may be disposed on the first substrate 201. In some embodiments, one photodiode may be disposed corresponding to one color filter 219 and lens 221. In some embodiments, a plurality of photodiodes may be disposed corresponding to one color filter 219 and lens 221.

[0055] The color filter 219 and the lens 221 may be disposed on the first back surface 201b of the first substrate 201. The color filter 219 and the lens 221 may be sequentially stacked on the first back surface 201b of the first substrate 201.

[0056] In FIG. 3, a plurality of lenses 221 are illustrated as being separated from each other, but the plurality of lenses 221 may be integrally formed with each other. This also varies depending on the design of the image sensor EX1 to be manufactured.

[0057] A pixel separation layer 217 can be disposed within the first substrate 201. The pixel separation layer 217 can perform a function of separating a plurality of pixels PX in FIG. 1 from each other. The pixel separation layer 217 can penetrate the first substrate 201. The pixel separation layer 217 can include two or more substances. The pixel separation layer 217 can include, for example, a semiconductor substance and an insulating substance having a refractive index different from that of the first substrate 201. The semiconductor substance can include, for example, a polysilicon film doped with impurities or a silicon germanium film. The impurities doped in the polysilicon or the silicon germanium film can be, for example, one of boron, phosphorus, and arsenic. The insulating substance can include, for example, silicon oxide. The pixel separation layer 217 can include a metal film instead of the semiconductor substance.

[0058] A fence pattern 220 can be disposed on the pixel separation layer 217. For example, the fence pattern 220 can overlap the pixel separation layer 217 in a direction perpendicular thereto. However, this is only an example, and the fence pattern 220 does not have to overlap the pixel separation layer 217 in a direction perpendicular thereto.

[0059] The fence pattern 220 can be interposed between a pair of color filters 219 adjacent in the first horizontal direction D1. The fence pattern 220 can separate a plurality of color filters 219. For example, a plurality of color filters 219 can be physically and optically separated from each other by the fence pattern 220.

[0060] In plan view, the fence pattern 220 can surround each of the plurality of pixels PX in FIG. 1. For example, the fence pattern 220 can surround each color filter 219.

[0061] The fence pattern 220 can include a first fence configuration 220a and a second fence configuration 220b on the first fence configuration 220a. For example, the first fence configuration 220a and the second fence configuration 220b have a rectangular cross section.

[0062] The first fence structure 220a can function as a barrier layer. The first fence structure 220a can include a conductive material such as a metal and / or a metal nitride. For example, the first fence structure 220a can include titanium and / or titanium nitride.

[0063] The second fence structure 220b can include a material different from that of the first fence structure 220a. For example, the second fence structure 220b can include an organic material. The second fence structure 220b includes a low refractive index material and has insulating properties.

[0064] The first transistor 203 can be disposed on the first front surface 201f. In FIG. 3, the first source and drain regions constituting the first transistor 203 are disposed on the first substrate 201, but are omitted for convenience.

[0065] The first contact plug 207 and the first wiring layer 205 can be connected to the first transistor 203. The first contact plug 207 can include a conductive metal. For example, the first contact plug 207 can include tungsten. A plurality of first wiring layers 205 can be provided. Among the plurality of first wiring layers 205, two different first wiring layers 205 can be located at different vertical levels. That is, the plurality of first wiring layers 205 can form a multilayer structure.

[0066] The first wiring layer 205 can be connected to the first via plug 209. The first via plug 209 can connect at least two first wiring layers 205 disposed at different vertical levels to each other.

[0067] The first front bonding pad 211 can be disposed below the uppermost layer 200. The first front bonding pad 211 can be connected to the first front bonding plug 213. The first front bonding plug 213 extends in the vertical direction D3 and can be connected to the first wiring layer 205.

[0068] In this specification, a first horizontal direction D1 is a direction parallel to a first front surface 201f of a first substrate 201, a second horizontal direction D2 is a direction parallel to the first front surface 201f of the first substrate 201 and intersects the first horizontal direction D1, and a vertical direction D3 is defined as a direction perpendicular to the first front surface 201f of the first substrate 201.

[0069] As an example, a first front bonding pad 211 and a first front bonding plug 213 may be integrally formed. That is, a boundary between the first front bonding pad 211 and the first front bonding plug 213 is not observed.

[0070] The first front bonding pad 211 may be electrically connected to a first transistor 203 via the first front bonding plug 213, a first wiring layer 205, a first via plug 209, and a first contact plug 207. As an example, the first front bonding pad 211 may be electrically connected to a floating diffusion node FD in FIG. 2.

[0071] The first wiring layer 205 has a first thickness T1. The first via plug 209 has a second thickness T2. The first front bonding pad 211 has a third thickness T3. The first front bonding plug 213 has a fourth thickness T4.

[0072] The first thickness T1 is also a length of the first wiring layer 205 in the vertical direction D3. The second thickness T2 is also a length of the first via plug 209 in the vertical direction D3. The third thickness T3 is also a length of the first front bonding pad 211 in the vertical direction D3. The fourth thickness T4 is also a length of the first front bonding plug 213 in the vertical direction D3.

[0073] The third thickness T3 is thinner than the first thickness T1. The fourth thickness T4 is thicker than the second thickness T2.

[0074] The first shield structure 230 can be disposed on the side of the first front bonding pad 211. The first shield structure 230 can be spaced apart from the first front bonding pad 211 in the first horizontal direction D1. The first shield structure 230 can be disposed between two first front bonding pads 211 adjacent in the first horizontal direction D1. The first shield structure 230 extends in the vertical direction D3 toward the first front surface 201f of the first substrate 201. The first shield structure 230 can be spaced apart from the second front bonding pad 211, the first front bonding plug 213, the first wiring layer 205, and the first via plug 209.

[0075] The first shield structure 230 can include a first portion spaced apart from the first front bonding pad 211 in the first horizontal direction D1 and a second portion spaced apart from the first front bonding plug 213 in the first horizontal direction D1. The first portion can be disposed at a vertical level such as the first front bonding pad 211, and the second portion can be disposed at a vertical level such as the first front bonding plug 213. The first portion and the second portion can be integrally formed.

[0076] The first shield structure 230 can overlap the pixel isolation layer 217 in the vertical direction. In a plan view, the first shield structure 230 can overlap the pixel isolation layer 217.

[0077] The lower surface 230b of the first shield structure 230 can be coplanar with the lower surface 211b of the first front bonding pad 211. The vertical level of the upper surface 230a of the first shield structure 230 is higher than the vertical level of the upper surface 211a of the first front bonding pad 211. The vertical level of the upper surface 230a of the first shield structure 230 is lower than the vertical level of the upper surface 213a of the first front bonding plug 213.

[0078] The first shield structure 230 has a fifth thickness T5. The fifth thickness T5 is also the length of the first shield structure 230 in the vertical direction D3. The fifth thickness T5 is thicker than the third thickness T3. The fifth thickness T5 is thinner than or equal to the sum of the third thickness T3 and the fourth thickness T4. As an example, the fifth thickness T5 can be different from the fourth thickness T4. As an example, the fifth thickness T5 is thinner than or equal to the fourth thickness T4. As an example, the fifth thickness T5 is thicker than the fourth thickness T4.

[0079] In a cross-sectional view as shown in FIG. 4, the width of the first shield structure 230 in the first horizontal direction D1 is narrower than the width of the first front bonding pad 211 in the first horizontal direction D1. The width of the first shield structure 230 in the first horizontal direction D1 is substantially the same as the width of the first front bonding plug 213 in the first horizontal direction D1 or narrower than the width of the first front bonding plug 213 in the first horizontal direction D1.

[0080] The first wiring layer 205, the first via plug 209, the first front bonding pad 211, the first front bonding plug 213, and the first shield structure 230 can include the same material. The first wiring layer 205, the first via plug 209, the first front bonding pad 211, the first front bonding plug 213, and the first shield structure 230 can include a conductive metal. For example, the first wiring layer 205, the first via plug 209, the first front bonding pad 211, the first front bonding plug 213, and the first shield structure 230 can include copper.

[0081] The first insulating layer 215 can be disposed on the first front surface 201f of the first substrate 201. The first wiring layer 205, the first contact plug 207, the first via plug 209, and the first front bonding plug 213 can be disposed within the first insulating layer 215. The first insulating layer 215 can surround a part of the first shield structure 230. The first shield structure 230 can further extend downward in the vertical direction D3 from the lower surface 215b of the first insulating layer 215. The first front bonding pad 211 can be disposed below the lower surface 215b of the first insulating layer 215.

[0082] The vertical level of the lower surface 215b of the first insulating layer 215 is higher than the vertical levels of the lower surface 211b of the first front bonding pad 211 and the lower surface 230b of the first shield structure 230. The first insulating layer 215 may contain silicon oxide.

[0083] A first passivation layer 216 may be disposed under the lower surface 215b of the first insulating layer 215. The first passivation layer 216 may surround the side surface of the first front bonding pad 211. The lower surface of the first passivation layer 216 may be coplanar with the lower surface 211b of the first front bonding pad 211 and the lower surface 230b of the first shield structure 230. The first passivation layer 216 may contain silicon oxynitride.

[0084] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, back bonding through vias 317, a second wiring layer 305, second contact plugs 307, second via plugs 309, second front bonding pads 311, second front bonding plugs 313, a second shield structure 330, a second insulating layer 315, and a second passivation layer 316.

[0085] The first front bonding pad 211 constituting the top layer 200 may be bonded to the second front bonding pad 311 constituting the intermediate layer 300. The first passivation layer 216 constituting the top layer 200 may be bonded to the second passivation layer 316 constituting the intermediate layer 300. The top layer 200 and the intermediate layer 300 have an interface F-F where the front surface F and the front surface F are bonded.

[0086] The second substrate 301 may be a silicon substrate. The second substrate 301 may include a second front surface 301f and a second back surface 301b on the opposite side of the second front surface 301f. The second transistors 303 may be disposed on the second front surface 301f. In FIG. 3, the second source and drain regions constituting the second transistors 303 are disposed in the second substrate 301, but are omitted for convenience.

[0087] In the second substrate 301, through-via holes VHO penetrating the second front surface 301f and the second back surface 301b may be arranged. In the through-via holes VHO, back-bonding through-vias 317 insulated from the second substrate 301 by the second insulating layer 315 may be arranged.

[0088] The second transistor 303 may be connected to the second contact plug 307 and the second wiring layer 305. The second contact plug 307 may contain a conductive metal. For example, the second contact plug 307 may contain tungsten. The second contact plug 307 and the second wiring layer 305 may be connected to the second front-bonding pad 311 and the back-bonding through-via 317.

[0089] A plurality of second wiring layers 305 may be provided. Among the plurality of second wiring layers 305, two different second wiring layers 305 are located at different vertical levels. That is, the plurality of second wiring layers 305 may form a multilayer structure.

[0090] The second wiring layer 305 may be connected to the second via plug 309. The second via plug 309 may connect at least two second wiring layers 305 arranged at different vertical levels to each other.

[0091] The second front-bonding pad 311 may be arranged on the upper part of the intermediate layer 300. The second front-bonding pad 311 may be connected to the second front-bonding plug 313. The second front-bonding plug 313 extends in the vertical direction D3 and may be connected to the second wiring layer 305.

[0092] As an example, the second front-bonding pad 311 and the second front-bonding plug 313 may be integrally formed. That is, the boundary between the second front-bonding pad 311 and the second front-bonding plug 313 is not observed.

[0093] The second front bonding pad 311 can be electrically connected to the second transistor 303 via the second front bonding plug 313, the second wiring layer 305, the second via plug 309, and the second contact plug 307. As an example, the second front bonding pad 311 can be electrically connected to the gate of the source follower transistor SF in FIG. 2.

[0094] The second wiring layer 305 has a sixth thickness T6. The second via plug 309 has a seventh thickness T7. The second front bonding pad 311 has an eighth thickness T8. The second front bonding plug 313 has a ninth thickness T9.

[0095] The sixth thickness T6 is also the length of the second wiring layer 305 in the vertical direction D3. The seventh thickness T7 is also the length of the second via plug 309 in the vertical direction D3. The eighth thickness T8 is also the length of the second front bonding pad 311 in the vertical direction D3. The ninth thickness T9 is also the length of the second front bonding plug 313 in the vertical direction D3.

[0096] The eighth thickness T8 is thinner than the sixth thickness T6. The ninth thickness T9 is thicker than the seventh thickness T7.

[0097] The second shield structure 330 can be disposed on the second front bonding pad 311 side. The second shield structure 330 can be spaced apart from the second front bonding pad 311 in the first horizontal direction D1. The second shield structure 330 can be disposed between two second front bonding pads 311 adjacent in the first horizontal direction D1. The second shield structure 330 extends in the vertical direction D3 toward the second front surface 301f of the second substrate 301. The second shield structure 330 can be spaced apart from the second front bonding pad 211, the second front bonding plug 313, the second wiring layer 305, and the second via plug 309.

[0098] The second shield structure 330 may include a third portion spaced from the second front bonding pad 311 in the first horizontal direction D1, and a fourth portion spaced from the second front bonding plug 313 in the first horizontal direction D1. The third portion may be disposed at a vertical level such as the second front bonding pad 311, and the fourth portion may be disposed at a vertical level such as the second front bonding plug 313. The third portion and the fourth portion may be integrally formed.

[0099] The second shield structure 330 may overlap the pixel isolation layer 217 in the vertical direction. In plan view, the second shield structure 330 may overlap the pixel isolation layer 217.

[0100] The upper surface 330a of the second shield structure 330 may be coplanar with the upper surface 311a of the second front bonding pad 311. The vertical level of the lower surface 330b of the second shield structure 330 is lower than the vertical level of the lower surface 311b of the second front bonding pad 311. The vertical level of the lower surface 330b of the second shield structure 330 is higher than the vertical level of the lower surface 313b of the second front bonding plug 313.

[0101] The second shield structure 330 has a tenth thickness T10. The tenth thickness T10 is also the length of the second shield structure 330 in the vertical direction D3. The tenth thickness T10 is thicker than the eighth thickness T8. The tenth thickness T10 is thinner than the sum of the eighth thickness T8 and the ninth thickness T9.

[0102] As an example, the width of the second shield structure 330 in the first horizontal direction D1 may be substantially the same as the width of the first shield structure 230 in the first horizontal direction D1.

[0103] In a cross-sectional view as shown in FIG. 4, the width of the second shield structure 330 in the first horizontal direction D1 is narrower than the width of the second front bonding pad 311 in the first horizontal direction D1. The width of the second shield structure 330 in the first horizontal direction D1 is substantially the same as the width of the second front bonding plug 313 in the first horizontal direction D1 or narrower than the width of the second front bonding plug 313 in the first horizontal direction D1.

[0104] The second shield structure 330 can contact the first shield structure 230. Specifically, at least a part of the upper surface 330a of the second shield structure 330 can contact at least a part of the lower surface 230b of the first shield structure 230. The second shield structure 330 can be connected to the first shield structure 230.

[0105] The second wiring layer 305, the second via plug 309, the second front bonding pad 311, the second front bonding plug 313, and the second shield structure 330 can include the same material. The second wiring layer 305, the second via plug 309, the second front bonding pad 311, the second front bonding plug 313, and the second shield structure 330 can include a conductive metal. As an example, the second wiring layer 305, the second via plug 309, the second front bonding pad 311, the second front bonding plug 313, and the second shield structure 330 can include copper.

[0106] The second insulating layer 315 can be disposed on the second front surface 301f of the second substrate 301. The second wiring layer 305, the second contact plug 307, the second via plug 309, and the second front bonding plug 313 can be disposed in the second insulating layer 315. The second insulating layer 315 can surround a part of the second shield structure 330. The second shield structure 330 can further extend upward in the vertical direction D3 from the upper surface 315a of the second insulating layer 315. The second front bonding pad 311 can be disposed on the upper surface 315a of the second insulating layer 315.

[0107] The vertical level of the upper surface 315a of the second insulating layer 315 is lower than the vertical levels of the upper surface 311a of the second front bonding pad 311 and the upper surface 330a of the second shield structure 330. The second insulating layer 315 may contain silicon oxide.

[0108] A second passivation layer 316 may be disposed on the upper surface 315a of the second insulating layer 315. The second passivation layer 316 may surround the side surface of the second front bonding pad 311. The upper surface of the second passivation layer 316 may be coplanar with the upper surface 311a of the second front bonding pad 311 and the upper surface 330a of the second shield structure 330. The second passivation layer 316 may contain silicon oxynitride.

[0109] The bottom layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, a third contact plug 407, a third front bonding pad 411, a third via plug 406, and a third insulating layer 415.

[0110] The back bonding through via 317 constituting the intermediate layer 300 may be bonded to the third front bonding pad 411 constituting the bottom layer 400. The second insulating layer 315 and the second substrate 301 constituting the intermediate layer 300 may be bonded to the third insulating layer 415 constituting the bottom layer 400. The intermediate layer 300 and the bottom layer 400 have an interface B-F where the back B and the front F are bonded.

[0111] The third substrate 401 may be a silicon substrate. The third substrate 401 may include a third front surface 401f and a third back surface 401b opposite to the third front surface 401f. The third transistors 403 may be formed on the third front surface 401f. In FIG. 3, a fourth source and drain region constituting the third transistor 403 is formed in the third substrate 401, but is omitted here for convenience.

[0112] The third transistor 403 may be connected to a third contact plug 407 and a third wiring layer 405. The third contact plug 407 may be formed of a metal layer, for example, a tungsten layer. The third wiring layer 405 may be connected to a third front bonding pad 411 via a third via plug 406. The third contact plug 407 and the third wiring layer 405 may be connected to the third front bonding pad 411. The third front bonding pad 411, the third wiring layer 405, and the third via plug 406 may include a conductive metal. For example, the third front bonding pad 411, the third wiring layer 405, and the third via plug 406 may include copper.

[0113] In the image sensor EX1, the first front bonding pad 211 constituting the uppermost layer 200 and the second front bonding pad 311 constituting the intermediate layer 300 are bonded, and the uppermost layer 200 and the intermediate layer 300 have an interface F-F where the front surface F and the front surface F are bonded.

[0114] In the image sensor EX1, the back bonding through via 317 constituting the intermediate layer 300 may be bonded to the third front bonding pad 411 constituting the lowermost layer 400. The intermediate layer 300 and the lowermost layer 400 have an interface B-F where the back surface B and the front surface F are bonded.

[0115] If the vertical level of the upper surface 230a of the first shield structure 230 is lower than the vertical level of the upper surface 211a of the first front bonding pad 211, it is difficult to prevent the coupling phenomenon that occurs between the two first front bonding plugs 213 adjacent in the first horizontal direction D1. The coupling phenomenon may become more pronounced as the image sensor EX1 is miniaturized.

[0116] The image sensor EX1 according to the technical idea of the present invention may include a lowermost layer 400, an intermediate layer 300, and an uppermost layer 200 that are stacked in this order. The uppermost layer 200 may include a first front bonding pad 211 disposed below the uppermost layer 200, a first front bonding plug 213 connected to the first front bonding pad 211 and extending upward in the vertical direction D3, and a first shield structure 230 disposed between two first front bonding pads 211 adjacent in the first horizontal direction D1. The vertical level of the upper surface 230a of the first shield structure 230 is higher than the vertical level of the upper surface 211a of the first front bonding pad 211.

[0117] The intermediate layer 300 may include a second front bonding pad 311 disposed above the intermediate layer 300, a second front bonding plug 313 connected to the second front bonding pad 311 and extending downward in the vertical direction D3, and a second shield structure 330 disposed between two second front bonding pads 311 adjacent in the first horizontal direction D1. The vertical level of the lower surface 330b of the second shield structure 330 is lower than the vertical level of the lower surface 311b of the second front bonding pad 311.

[0118] Therefore, no coupling occurs between two first front bonding plugs 213 adjacent in the first horizontal direction D1. For the reasons as above, the electrical characteristics and reliability of the image sensor EX1 can be improved.

[0119] Also, in a cross-sectional view as shown in FIG. 4, the width of the first shield structure 230 in the first horizontal direction D1 is narrower than the width of the first front bonding pad 211 in the first horizontal direction D1. The width of the first shield structure 230 in the first horizontal direction D1 is substantially the same as the width of the first front bonding plug 213 in the first horizontal direction D1 or narrower than the width of the first front bonding plug 213 in the first horizontal direction D1.

[0120] In a cross-sectional view as shown in FIG. 4, the width of the second shield structure 330 in the first horizontal direction D1 is narrower than the width of the second front bonding pad 311 in the first horizontal direction D1. The width of the second shield structure 330 in the first horizontal direction D1 is substantially the same as the width of the second front bonding plug 313 in the first horizontal direction D1, or is narrower than the width of the second front bonding plug 313 in the first horizontal direction D1.

[0121] Therefore, the space occupied by the first shield structure 230 and the second shield structure 330 can be minimized. For the reasons described above, the integration degree of the image sensor EX1 can be improved.

[0122] FIG. 5 is a schematic plan view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention. Specifically, FIG. 5 is a plan view showing the planar arrangement relationship between the first front bonding pad 211 and the first shield structure 230 having the configuration described in FIGS. 3 and 4, or the planar arrangement relationship between the second front bonding pad 311 and the second shield structure 330 having the configuration described in FIGS. 3 and 4. Hereinafter, except for the description with reference to FIG. 5, it is the same as that described with reference to FIGS. 3 and 4, and thus the description thereof is omitted.

[0123] Referring to FIG. 5, the first front bonding pad 211 and the second front bonding pad 311 have a square planar shape. However, this is only an embodiment, and the first front bonding pad 211 and the second front bonding pad 311 may include various planar shapes such as circular, elliptical, polygonal, or annular.

[0124] A plurality of the first front bonding pads 211 may be provided. A plurality of the second front bonding pads 311 may be provided. The plurality of first front bonding pads 211 may be two-dimensionally arranged along the first horizontal direction D1 and the second horizontal direction D2. The plurality of second front bonding pads 311 may be two-dimensionally arranged along the first horizontal direction D1 and the second horizontal direction D2.

[0125] Any one of the plurality of first front bonding pads 211 and any one of the plurality of second front bonding pads 311 can be overlapped in the vertical direction D3. The first front bonding pad 211 and the first front bonding plug 213 can be overlapped in the vertical direction D3. The second front bonding pad 311 and the second front bonding plug 313 can be overlapped in the vertical direction D3.

[0126] A first shield structure 230 can be disposed between two first front bonding pads 211 adjacent to each other in the first horizontal direction D1. A plurality of first shield structures 230 can be provided. The first shield structure 230 extends in the second horizontal direction D2. A second shield structure 330 can be disposed between two second front bonding pads 311 adjacent to each other in the first horizontal direction D1. A plurality of second shield structures 330 can be provided. The second shield structure 330 extends in the second horizontal direction D2.

[0127] Any one of the plurality of first shield structures 230 and any one of the plurality of second shield structures 330 can be overlapped in the vertical direction D3.

[0128] FIG. 6 is a schematic plan view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0129] Specifically, FIG. 6 is a plan view showing the planar arrangement relationship between the first front bonding pad 211 and the first shield structure 230 having the configuration described in FIGS. 3 and 4, or the planar arrangement relationship between the second front bonding pad 311 and the second shield structure 330 having the configuration described in FIGS. 3 and 4. Hereinafter, except for those described with reference to FIG. 6, since they are the same as those described with reference to FIGS. 3 and 4, the description thereof will be omitted.

[0130] Referring to FIG. 6, the first front bonding pad 211 and the second front bonding pad 311 can have a rectangular planar shape. However, this is only an example, and the first front bonding pad 211 and the second front bonding pad 311 can include various planar shapes such as circular, elliptical, polygonal, or annular shapes.

[0131] A plurality of the first front bonding pads 211 can be provided. A plurality of the second front bonding pads 311 can be provided. The plurality of first front bonding pads 211 can be two-dimensionally arranged along the first horizontal direction D1 and the second horizontal direction D2. The plurality of second front bonding pads 311 can be two-dimensionally arranged along the first horizontal direction D1 and the second horizontal direction D2.

[0132] Any one of the plurality of first front bonding pads 211 and any one of the plurality of second front bonding pads 311 can be overlapped in the vertical direction D3. The first front bonding pad 211 and the first front bonding plug 213 can be overlapped in the vertical direction D3. The second front bonding pad 311 and the second front bonding plug 313 can be overlapped in the vertical direction D3.

[0133] In a plan view, the first shield structure 230 can surround the first front bonding pad 211. In a plan view, the first shield structure 230 can surround the first front bonding plug 213. In a plan view, the first shield structure 230 has a mesh shape. The first shield structure 230 extends in the first horizontal direction D1 and the second horizontal direction D2.

[0134] In a plan view, the second shield structure 330 can surround the second front bonding pad 311. In a plan view, the second shield structure 330 can surround the second front bonding plug 313. In a plan view, the second shield structure 330 has a mesh shape. The second shield structure 330 extends in the first horizontal direction D1 and the second horizontal direction D2.

[0135] FIG. 7 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention. FIG. 8 is an enlarged view of the PP2 portion of FIG. 7. In the following, except where otherwise described with reference to FIGS. 7 and 8, the description is the same as that described with reference to FIGS. 3 and 4, and thus the description thereof is omitted.

[0136] Referring to FIGS. 7 and 8, the image sensor EX2 may include a lowermost layer 400, an intermediate layer 300, and an uppermost layer 200 that are stacked in this order.

[0137] The uppermost layer 200 may include a first substrate 201, a pixel isolation layer 217, a color filter 219, a lens 221, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 207, a first via plug 209, a first front bonding pad 211, a first front bonding plug 213, a first shield structure 230, a first insulating layer 215, and a first passivation layer 216.

[0138] The vertical level of the upper surface 230a of the first shield structure 230 is higher than the vertical level of the upper surface 213a of the first front bonding plug 213.

[0139] The first front bonding pad 211 has a third thickness T3. The first front bonding plug 213 has a fourth thickness T4. The first shield structure 230 has a fifth thickness T5. The fifth thickness T5 is thicker than the sum of the third thickness T3 and the fourth thickness T4. The fifth thickness T5 may be different from the fourth thickness T4. The fifth thickness T5 is thicker than the fourth thickness T4.

[0140] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a back bonding through via 317, a second wiring layer 305, a second contact plug 307, a second via plug 309, a second front bonding pad 311, a second front bonding plug 313, a second shield structure 330, a second insulating layer 315, and a second passivation layer 316.

[0141] The vertical level of the lower surface 330b of the second shield structure 330 is lower than the vertical level of the lower surface 313b of the second front bonding plug 313.

[0142] The second front bonding pad 311 has an eighth thickness T8. The second front bonding plug 313 has a ninth thickness T9. The second shield structure 330 has a tenth thickness T10. The tenth thickness T10 is thicker than the sum of the eighth thickness T8 and the ninth thickness T9.

[0143] FIGS. 9 to 15 are cross-sectional views for explaining a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention.

[0144] Specifically, in FIGS. 9 to 15, the content described in FIGS. 3 and 4 will be briefly described or omitted. Referring to FIG. 9, a first substrate 201 is prepared. The first substrate 201 may include a first front surface 201f and a first back surface 201b opposite to the first front surface 201f. A pixel isolation layer 217 may be formed in the first substrate 201. A plurality of first transistors 203 may be formed on the first front surface 201f of the first substrate 201. A first contact plug 207, a first wiring layer 205, and a first via plug 209 connected to the first transistor 203 may be formed. A first insulating layer 215 may be formed on the first front surface 201f of the first substrate 201 to cover the first contact plug 207, the first wiring layer 205, and the first via plug 209.

[0145] A first passivation film 216a may be formed on the first insulating layer 215. A protective insulating layer ILD may be formed on the first passivation film 216a. The first passivation film 216a may include silicon oxynitride. The protective insulating layer ILD may include silicon oxide.

[0146] A first mask pattern PM1 may be formed on the protective insulating layer ILD. The first mask pattern PM1 may include a first opening OP1 that exposes at least a part of the upper surface of the protective insulating layer ILD. A plurality of first openings OP1 are provided.

[0147] Referring to FIG. 10, a first etching process ET1 can be performed on the protective insulating layer ILD, the first passivation film 216a, and the first insulating layer 215 using the first mask pattern PM1 as an etching mask. The first etching process ET1 can utilize a dry etching process.

[0148] By the first etching process ET1, a first hole H1 and a second hole H2 penetrating the protective insulating layer ILD and the first passivation film 216a can be formed. The first hole H1 and the second hole H2 can further penetrate a part of the first insulating layer 215. However, the first wiring layer 205 is not exposed by the first hole H1 and the second hole H2. Each of the first hole H1 and the second hole H2 can overlap with at least one of the plurality of first openings OP1 in the vertical direction D3. A plurality of the first holes H1 and the second holes H2 can be provided.

[0149] Referring to FIG. 11, the first mask pattern PM1 in FIG. 10 can be removed. Then, a sacrificial film SL filling the first hole H1 and the second hole H2 can be formed. The sacrificial film SL can cover the upper surface of the protective insulating layer ILD. The sacrificial film SL can contain a polymer material.

[0150] A second mask pattern PM2 can be formed on the sacrificial film SL. The second mask pattern PM2 can include a second opening OP2 exposing at least a part of the upper surface of the sacrificial film SL. The second opening OP2 can overlap with the first hole H1 in the vertical direction D3. The width of the second opening OP2 in the first horizontal direction D1 can be made wider than the width of the first hole H1 in the first horizontal direction D1. The second opening OP2 does not overlap with the second hole H2 in the vertical direction D3.

[0151] Referring to FIG. 12, the second etching process ET2 on the sacrificial film SL can be advanced using the second mask pattern PM2 in FIG. 11 as an etching mask. The second etching process ET2 can use a dry etching process.

[0152] In the second etching process ET2, a part of the sacrificial film SL can be removed. A part of the sacrificial film SL to be removed is also a part of the sacrificial film SL that overlaps in the vertical direction Z with the second opening OP2. The sacrificial film SL that filled the first hole H1 can be removed by the second etching process ET2. A part of the sacrificial film SL disposed on the protective insulating layer ILD can be removed by the second etching process ET2.

[0153] While a part of the sacrificial film SL is removed by the second etching process ET2, a third opening OP3 can be formed in the sacrificial film SL. The width of the third opening OP3 in the first horizontal direction D1 can be substantially the same as the width of the second opening OP2 in the first horizontal direction D1. The width of the third opening OP3 in the first horizontal direction D1 is wider than the width of the first hole H1 in the first horizontal direction D1.

[0154] The thickness of the second mask pattern PM2 can be reduced by the second etching process ET2. However, the second mask pattern PM2 is not completely removed and a part can remain.

[0155] Referring to FIG. 13, a third etching process ET3 can be performed on the protective insulating layer ILD, the first passivation film 216a, and the first insulating layer 215 using the second mask pattern PM2 in FIG. 12 as an etching mask. The third etching process ET3 can use a dry etching process.

[0156] While a part of the protective insulating layer ILD, the first passivation film 216a, and the first insulating layer 215 is further removed by the third etching process ET3, a third hole H3 can be formed. At a vertical level where the protective insulating layer ILD and the first passivation film 216a overlap in the first horizontal direction D1, the width of the third hole H3 in the first horizontal direction D1 can be substantially the same as the width of the third opening OP3 in the first horizontal direction D1.

[0157] While a part of the first insulating layer 215 is further etched by the third etching process ET3, at least a part of the first wiring layer 205 can be exposed.

[0158] Next, the second mask pattern PM2 can be removed.

[0159] Referring to FIG. 14, a conductive film PCL filling the second hole H2 and the third hole H3 can be formed. The conductive film PCL can also be disposed on the upper surface of the protective insulating layer ILD. The conductive film PCL can contact the first wiring layer 205 through the third hole H3.

[0160] Referring to FIG. 15, a planarization process can be performed on the conductive film PCL, the protective insulating layer ILD, and the first passivation film 216a of FIG. 14. As an example, the planarization process can include chemical mechanical polishing (CMP). By the planarization process, the first front bonding pad 211, the first front bonding plug 213, and the first shield structure 230 can be formed from the conductive film PCL of FIG. 14. By the planarization process, all of the protective insulating layer ILD of FIG. 14 can be removed. By the planarization process, the first passivation layer 216 can be formed from the first passivation film 216a of FIG. 14.

[0161] Referring again to FIG. 3, the first substrate 201 in FIG. 15 can be inverted, and a color filter 219 and a lens 221 can be formed on the first back surface 201b of the first substrate 201. Thereby, the top layer 200 can be formed.

[0162] The intermediate layer 300 can be prepared separately from the top layer 200. The intermediate layer 300 can include a second substrate 301, a plurality of second transistors 303, a back bonding through via 317, a second wiring layer 305, a second contact plug 307, a second via plug 309, a second front bonding pad 311, a second front bonding plug 313, a second shield structure 330, a second insulating layer 315, and a second passivation layer 316.

[0163] The second substrate 301 may include a second front surface 301f and a second back surface 301b opposite to the second front surface 301f. Through via holes VHO penetrating the second front surface 301f and the second back surface 301b may be formed in the second substrate 301. Back bonding through vias 317 insulated from the second substrate 301 by a second insulating layer 315 may be formed in the through via holes VHO.

[0164] A plurality of second transistors 303 may be formed on the second front surface 301f of the second substrate 301. Second contact plugs 307, a second wiring layer 305, and second via plugs 309 connected to the second transistors 303 may be formed. A first insulating layer 215 disposed on the second front surface 301f of the second substrate 301 and covering the second contact plugs 307, the second wiring layer 305, and the second via plugs 309 may be formed.

[0165] The second front bonding pads 311, the second front bonding plugs 313, the second shield structure 330, and the second passivation layer 316 constituting the intermediate layer 300 may be formed by a method similar to the method of forming the first front bonding pads 211, the first front bonding plugs 213, the first shield structure 230, and the first passivation layer 216 described with reference to FIGS. 9 to 15.

[0166] Next, the first front bonding pads 211 constituting the uppermost layer 200 may be bonded to the second front bonding pads 311 constituting the intermediate layer 300. When the first front bonding pads 211 and the second front bonding pads 311 contain copper, the copper pads may be bonded to each other.

[0167] The lowermost layer 400 may be prepared separately from the uppermost layer 200 and the intermediate layer 300. The lowermost layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, third contact plugs 407, third front bonding pads 411, third via plugs 406, and a third insulating layer 415.

[0168] The back bonding through-via 317 that constitutes the intermediate layer 300 can be bonded to the third front bonding pad 411 that constitutes the bottom layer 400. The second insulating layer 315 and the second substrate 301 that constitute the intermediate layer 300 can be bonded to the third insulating layer 415 that constitutes the bottom layer 400. When the back bonding through-via 317 and the third front bonding pad 411 contain copper, the copper via and the copper pad can be bonded. Thereby, the image sensor EX1 of FIG. 3 can be manufactured.

Explanation of Reference Numerals

[0169] 100 Image sensor 200 Top layer 201 First substrate 201b First back surface 201f First front surface 203 First transistor 205 First wiring layer 207 First contact plug 209 First via plug 211 First front bonding pad 211b Lower surface of the first front bonding pad 213 First front bonding plug 215 First insulating layer 215b Lower surface of the first insulating layer 215 216 First passivation layer 217 Pixel isolation layer 219 Color filter 220a First fence structure 220b Second fence structure 221 Lens 230 First shield structure 230b Lower surface of the first shield structure 300 Intermediate layer 301 Second substrate 301b Second back surface 301f Second front surface 303 Second transistor 305 Second wiring layer 307 Second contact plug 309 Second via plug 311 Second front bonding pad 313 Second front bonding plug 315 Second insulating layer 316 Second passivation layer 317 Back bonding through via 330 Second shield structure 330a Upper surface of the second shield structure 400 Lowermost layer 401 Third substrate 401b Third back surface 401f Third front surface 403 Third transistor 405 Third wiring layer 406 Third via plug 407 Third contact plug 411 Third front bonding pad 415 Third insulating layer D1 First horizontal direction D2 Second horizontal direction D3 Vertical direction EX1 Image sensor PX Pixel T1~T10 First thickness~Tenth thickness VHO Through via hole

Claims

1. A top layer including a first substrate including a first front surface and a first back surface opposite to the first front surface, a first front bonding pad disposed on the first front surface of the first substrate, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and a first shield structure spaced apart from the first front bonding pad in a first horizontal direction; An intermediate layer bonded to the top layer below the top layer, including a second substrate including a second front surface and a second back surface opposite to the second front surface, a second front bonding pad disposed on the second front surface of the second substrate, a second front bonding plug connected to the second front bonding pad and extending in the vertical direction toward the second front surface, and a second shield structure spaced apart from the second front bonding pad in the first horizontal direction; A bottom layer bonded to the intermediate layer below the intermediate layer, including: The bottom layer includes a third substrate and a transistor disposed on the third substrate, An image sensor, wherein a vertical level of an upper surface of the first shield structure is higher than a vertical level of an upper surface of the first front bonding pad.

2. The image sensor according to claim 1, wherein a vertical level of a lower surface of the second shield structure is lower than a vertical level of a lower surface of the second front bonding pad.

3. The image sensor according to claim 1, wherein a width of the first shield structure in the first horizontal direction is narrower than a width of the first front bonding pad in the first horizontal direction.

4. The top layer includes: A first wiring layer and a second wiring layer disposed between the first substrate and the first front bonding plug, the first wiring layer and the second wiring layer being disposed at different vertical levels, and the first wiring layer being connected to the first front bonding plug; A first via plug connecting the first wiring layer and the second wiring layer; The image sensor according to claim 1, wherein a length of the first front bonding plug in the vertical direction is longer than a length of the first via plug in the vertical direction.

5. The image sensor according to claim 1, wherein a length of the first shield structure in the vertical direction is longer than a sum of a length of the first front bonding pad in the vertical direction and a length of the first front bonding plug in the vertical direction.

6. The image sensor according to claim 1, wherein a vertical level of an upper surface of the first shield structure is higher than a vertical level of an upper surface of the first front bonding plug.

7. An uppermost layer including a first substrate including a first front surface and a first back surface opposite to the first front surface, a first front bonding pad disposed on the first front surface of the first substrate, a first front bonding plug connected to the first front bonding pad and extending in a vertical direction toward the first front surface, and a first shield structure including a first portion spaced apart from the first front bonding pad in a first horizontal direction and a second portion spaced apart from the first front bonding plug in the first horizontal direction. An intermediate layer bonded to the uppermost layer below the uppermost layer, including a second substrate including a second front surface and a second back surface opposite to the second front surface, a second front bonding pad disposed on the second front surface of the second substrate, a second front bonding plug connected to the second front bonding pad and extending in the vertical direction toward the second front surface, and a second shield structure including a third portion spaced apart from the second front bonding pad in the first horizontal direction and a fourth portion spaced apart from the second front bonding plug in the first horizontal direction. A lowermost layer bonded to the intermediate layer below the intermediate layer, including: The lowermost layer includes a third substrate and a transistor disposed on the third substrate. The first shield structure and the second shield structure extend in a second horizontal direction intersecting the first horizontal direction, the image sensor.

8. The image sensor according to claim 7, wherein in a plan view, the first shield structure has a mesh shape.

9. The image sensor according to claim 7, wherein the first front bonding pad and the first front bonding plug are integrally formed.

10. The image sensor according to claim 7, wherein a length of the first shield structure in the vertical direction is longer than a length of the first front bonding plug in the vertical direction.

Images