Implantation process to mitigate bowing of wafers introduced by splitting process

Abstract

To disclose methods of forming crystalline wafers such as silicon carbide wafers.SOLUTION: Such a method may include providing a crystalline substrate comprising a substrate first surface and a substrate second surface opposite the substrate first surface. The method may also include creating a separation layer at a first depth from the substrate first surface and creating a mitigation layer at a second depth from the substrate second surface. Creating the separation layer may cause the crystalline substrate to bow, and creating the mitigation layer may reduce the bow of the crystalline substrate. The method may further include separating the wafer from the crystalline substrate along the separation layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Claims of Priority

[0001] This patent application claims the priority and the benefit of U.S. Provisional Patent Application No. 63 / 620,479, filed on January 12, 2024, the entire disclosure of which is incorporated herein by reference.

Background Art

[0002]

[0002] Crystal substrates, such as silicon carbide (SiC) substrates, may account for a majority of the overall manufacturing cost of semiconductor devices. One option for reducing such costs is to divide wafers from the crystal substrate and manufacture semiconductor devices from the wafers divided from the crystal substrate. Further wafers can be divided from the crystal substrate, and further semiconductor devices can be manufactured from such wafers. In this way, the costs associated with a single crystal substrate can be spread over more semiconductor devices, reducing the average manufacturing cost of the semiconductor devices. Wafer dicing can improve the device yield from a single substrate, but wafer dicing can cause warping (curvature of the surface) of the wafer. Such warping can make subsequent process integration steps more complex.

Summary of the Invention

[0003]

[0003] Illustrated and / or described in connection with at least one of the drawings and more fully set forth in the claims is a process for alleviating warping of wafers divided from a crystal substrate.

[0004]

[0004] These and other advantages, aspects and novel features of the present disclosure, as well as details of its illustrated embodiments, will be more fully understood from the following description and the drawings.

[0005] The various features and advantages of the present disclosure will be more readily understood by reference to the following detailed description in conjunction with the accompanying drawings, in which like reference numerals refer to like structural elements.

Brief Description of the Drawings

[0005]

Figure 1

[0006] FIG. 1 is a flowchart of a process for alleviating warping of a substrate in accordance with various aspects of the present disclosure.

Figure 2

[0007] FIG. 2 is a cross-sectional view of the substrate at various stages of the process of FIG. 1.

Figure 3

[0008] FIG. 3 is a graph showing the relationship between the vacancy and depth of ion species at respective implantation energies and doses.

Modes for Carrying Out the Invention

[0006]

[0009] The following discussion provides various examples for alleviating warping of a substrate and / or a wafer divided from such a substrate. Such examples are non-limiting, and the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms “example” and “for example” are not limiting.

[0007]

[0010] The figures illustrate a general configuration scheme, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated compared to other elements to assist in a better understanding of the examples discussed in the present disclosure. The same reference numerals in different figures denote the same elements.

[0008]

[0011] The term "and / or" means any one or more of the items in the list joined by "and / or". By way of example, "x and / or y" means any element of the three-element set {(x), (y), (x, y)}. As another example, "x, y and / or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0009]

[0012] The terms "comprise", "comprising", "include" and / or "including" are terms without limitation, specifying the presence of the recited features, but not precluding the presence or addition of one or more other features.

[0010]

[0013] Terms such as "first", "second" etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0011]

[0014] Unless otherwise specified, the term "coupled" can be used to represent two elements in direct contact with each other or two elements indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A can be in direct contact with element B or can be indirectly connected to element B by intervening element C. Similarly, the terms "above" or "on" can be used to describe two elements in direct contact with each other or two elements indirectly connected by one or more other elements.

[0012]

[0015] Generally, aspects of the present disclosure are directed to a process for relaxing the warp of a wafer or film separated from a crystalline substrate. In some embodiments, the process can implant cleavage ion species into the crystalline substrate from a first surface of the substrate to a first depth. Implantation of the cleavage ion species can cause warping of the crystalline substrate and / or the attached wafer. To relax such warping, the process can implant non-cleavage ion species into the crystalline substrate from a second surface of the substrate to a second depth.

[0013]

[0016] Next, as shown with reference to FIGS. 1 and 2, a process 100 for relaxing the warp of a wafer separated from a crystalline substrate is illustrated. Process 100 is illustrated and described below with respect to separating a silicon carbide (SiC) wafer or film from a silicon carbide substrate, but process 100 can be used to form a crystalline wafer or film from a crystalline substrate material other than silicon carbide.

[0014]

[0017] At 110, process 100 can prepare a silicon carbide substrate 10 for ion implantation. The silicon carbide substrate 10 can comprise a single crystal structure defining a substrate top surface 12, a substrate bottom surface 14, and a substrate side surface 16 between the substrate top surface 12 and the substrate bottom surface 14. The single crystal structure of the silicon carbide substrate 10 can exhibit one of many silicon carbide polytypes, such as 3C-SiC, 4C-SiC, 6H-SiC, etc. Further, the substrate top surface 12 can correspond to the Si face of the silicon carbide substrate 10, and the substrate bottom surface 14 can correspond to the C face of the silicon carbide substrate 10. At 110, the substrate top surface 12 can be polished to remove surface defects in the single crystal structure of the silicon carbide substrate 10, for example, by pre-separating a wafer from the silicon carbide substrate 10.

[0015]

[0018] Despite such preparations, the upper surface 12 of the substrate may not be completely flat. FIG. 2 shows four exemplary wafers (i.e., wafer 1, wafer 2, wafer 3, and wafer 4). The initial warp of wafer 1 is -1.1 μm (i.e., slightly concave), the initial warp of wafer 2 is -1.03 μm (i.e., slightly concave), the initial warp of wafer 3 is 5.188 μm (i.e., slightly convex), and the initial warp of wafer 4 is 0.07 (i.e., slightly convex).

[0016]

[0019] At 120, process 100 can generate the separation layer 20 at a desired depth D1 from the lower surface 14 of the substrate. For this, cleavage ions 22 can be implanted through the C-plane or the lower surface 14 of the substrate to a desired depth D1 in the silicon carbide substrate 10. Such implantation may damage the crystal structure of the silicon carbide substrate 10 (e.g., generate bond vacancies in the crystal structure). Depending on the crystal material of the substrate, various cleavage ion species can be implanted. In particular, in the case of silicon carbide, hydrogen (H) ions can be used as the cleavage ions 22. The depth at which such hydrogen (H) ions are implanted into the lower surface 14 depends on the implantation energy. See FIGS. 2 and 3. Further, the amount of damage (e.g., generated vacancies) can depend on the amount or dose of the implanted hydrogen (H) ions.

[0017]

[0020] As shown in FIG. 2, the hydrogen (H) ions in the illustrated embodiment can be implanted with a dose of 8e16 ions / cm 2 using an implantation energy of 150 kiloelectron volts (keV). However, as described above, the implantation energy controls the depth of implantation, and the dose controls the amount of damage or vacancies introduced into the crystal structure. Thus, the above values are merely exemplary. Other embodiments can adjust these values based on the desired implantation depth, the ion species to be implanted, the crystal material to be implanted, etc.

[0018]

[0021] As shown in FIG. 3, the vacancies generated from the implanted ions are distributed over a range of depths rather than simply at a single depth. In particular, FIG. 3 shows hydrogen (H) ions implanted at a dose of 8e16 ions / cm 2 with an implantation energy of 150 keV. Due to such implantation of hydrogen (H) ions, the peak concentration implantation depth is approximately 6400 Å, and the number of vacancies is approximately 1.6e22 / cm 3 .

[0019]

[0022] Furthermore, as shown in FIG. 2, due to the formation of the separation layer 20, the crystal structure of the silicon carbide substrate 10 is stressed, and the upper surface 12 of the substrate may warp. In the example of FIG. 2, hydrogen (H) ions are implanted at a dose of 8e16 ions / cm 2 with an implantation energy of 150 keV, and each wafer 1, 2, 3, 4 may exhibit a warp exceeding -350 μm (i.e., significantly convex).

[0020]

[0023] At 130, the process 100 can generate a relaxation layer 30 from the upper surface 12 of the substrate to a desired depth D2. For this purpose, non-split ions 32 can be implanted through the Si surface or the upper surface 12 of the substrate to a desired depth D2 of the silicon carbide substrate 10. Such implantation may damage the crystal structure of the silicon carbide substrate 10 (e.g., generate bonding vacancies in the crystal structure). Depending on the crystal material of the substrate, various non-split ion species can be implanted. In particular, in the case of silicon carbide, helium (He) ions can be used as the non-split ions 32. The depth at which such helium (He) ions are implanted into the upper surface 12 of the substrate depends on the implantation energy. See FIGS. 2 and 3. Furthermore, the amount of damage (e.g., generated vacancies) can depend on the amount, i.e., the dose, of the implanted helium (He) ions.

[0021]

[0024] As shown in FIG. 2, the process 100 uses a dose of 6e15 ions / cm 2 to implant helium (He) ions into wafer 1 at an implantation energy of 180 keV, and 1e16 ions / cm at an implantation energy of 180 keV2 Using the input amount, helium (He) ions can be implanted into wafer 2. Further, in process 100, with an implantation energy of 280 keV and an input amount of 1e15 ions / cm 2 Using the input amount, helium (He) ions are implanted into wafer 3, and with an implantation energy of 280 keV and an input amount of 6e15 ions / cm 2 Using the input amount, helium (He) ions can be implanted into wafer 4. As described above, the implantation energy controls the depth of implantation, and the input amount controls the amount of damage or the amount of vacancies introduced into the crystal structure. Therefore, the above values are merely examples of specific embodiments. Further, these values are selected at least in part based on the amount of warpage counteracted by relaxation layer 30.

[0022]

[0025] As shown in FIG. 3, the vacancies generated from the implanted ions are distributed over a range of depths rather than simply at a single depth. In particular, FIG. 3 shows helium (He) ions implanted with an implantation energy of 180 keV and an input amount of 6e15 ions / cm 2 and helium (He) ions implanted with an implantation energy of 280 keV and an input amount of 6e15 ions / cm 2 As shown, for implantation at 180 keV, the peak concentration implantation depth is approximately 6400 Å and the number of vacancies is approximately 1.5e22 / cm 3 and for implantation at 280 keV, the peak concentration implantation depth is approximately 8400 Å and the number of vacancies is approximately 1.5e22 / cm 3 respectively.

[0023]

[0026] Further, as shown in FIG. 2, due to the generation of relaxation layer 30, the crystal structure of silicon carbide substrate 10 is stressed and the stress introduced by separation layer 20 can be cancelled out. In particular, by relaxation layer 30 generated above, the warp of wafer 1 can be reduced from more than -350 μm to -22.1 μm, the warp of wafer 2 can be reduced from more than -350 μm to -66.59 μm, the warp of wafer 3 can be reduced from more than -350 μm to -17.75 μm, and the warp of wafer 4 can be reduced from more than -350 μm to -39.5 μm.

[0024]

[0027] After generating the relaxation layer 30, at 140, the process 100 can separate the wafer 18 from the silicon carbide substrate 10. To do this, the process 100 applies thermal energy to the silicon carbide substrate 10 to combine the pores or bubbles in the separation layer 20, and can separate the wafer 18 from the silicon carbide substrate 10. In particular, the amount of energy required to combine the pores in the separation layer 20 is much less than the amount of energy required to combine the pores in the relaxation layer 30. This energy difference is due to the ion species selected to form the separation layer 20 and the relaxation layer 30. For example, in the above example, hydrogen (H) ions are considered to be the cleavage ion species for the silicon carbide substrate 10 because only a small amount of energy (e.g., 0.35 keV) is required to combine each bubble and separate the wafer 18 from the silicon carbide substrate 10. Conversely, helium (He) ions are considered to be non-cleavage ion species for the silicon carbide substrate 10 because a large amount of energy (e.g., 2.40 keV) is required to combine each bubble. Due to this gap in the energy required to induce separation, at 140, the process 100 can apply energy (e.g., heat) to the silicon carbide substrate 10 along the separation layer 20 at a level sufficient to separate the wafer 18 from the silicon carbide substrate 10, but is insufficient to further separate along the relaxation layer 30.

[0025]

[0028] At 150, the process 100 can output a silicon carbide wafer or film by finishing the separated wafer 18. In particular, the process 100 can polish and / or etch the wafer 18 to remove residues of the separation layer 20. Such polishing and / or etching can also remove and / or reduce defects introduced during the separation of the silicon carbide wafer 18 from the silicon carbide substrate 10.

[0026]

[0029] Furthermore, process 100 can be repeated on the same silicon carbide substrate. In this way, a plurality of silicon carbide wafers 18 can be obtained from a single silicon carbide substrate 10.

[0027]

[0030] This disclosure includes references to specific examples, but it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of the disclosure. In addition, modifications can be made to the disclosed examples without departing from the scope of the disclosure. Therefore, this disclosure is not limited to the disclosed examples, but is intended to include all examples included in the appended claims.

Claims

1. A method of forming a wafer, comprising: providing a single crystal substrate including a first surface of the substrate and a second surface of the substrate opposite to the first surface of the substrate; generating a separation layer at a first depth from the first surface of the substrate; generating a relaxation layer at a second depth from the second surface of the substrate; separating the wafer from the single crystal substrate along the separation layer; and a method including the above steps.

2. The method according to claim 1, wherein the step of generating the separation layer warps the single crystal substrate, and the step of generating the relaxation layer reduces the warp of the single crystal substrate. A method.

3. The method according to claim 1, wherein the step of generating the separation layer includes injecting cleavage ions into the single crystal substrate, and the step of generating the relaxation layer includes injecting non-cleavage ions into the single crystal substrate. A method.

4. The method according to claim 1, wherein the step of generating the separation layer includes injecting cleavage ions into the single crystal substrate through the first surface of the substrate, and the step of generating the relaxation layer includes injecting non-cleavage ions into the single crystal substrate through the second surface of the substrate. A method.

5. The method according to claim 1, wherein the step of generating the separation layer includes injecting hydrogen ions into the single crystal substrate.

6. The method according to claim 1, wherein the step of generating the relaxation layer includes injecting helium ions into the single crystal substrate.

7. The method according to claim 1, wherein the step of separating the wafer from the single crystal substrate includes applying a level of thermal energy sufficient to coalesce the pores of the separation layer.

8. The method according to claim 7, wherein the level of the thermal energy is insufficient to coalesce the pores of the relaxation layer.

9. The method according to claim 1, further comprising removing residues of the separation layer from the wafer.

10. The method according to claim 1, further comprising reusing the single crystal substrate to form another wafer after separating the wafer from the single crystal substrate.

11. A method of forming a silicon carbide wafer, comprising: providing a silicon carbide substrate including an Si surface and a C surface; Injecting cleavage ion species into the C-plane of the silicon carbide substrate to form a separation layer; Injecting non-cleavage ion species into the Si-plane of the silicon carbide substrate to form a relaxation layer that cancels the warp of the silicon carbide substrate; Separating the silicon carbide wafer from the silicon carbide substrate along the separation layer; A method including.

12. The method according to claim 11, wherein the step of injecting the cleavage ion species contributes to the warp of the silicon carbide substrate.

13. The method according to claim 11, wherein The step of injecting the cleavage ion species forms the separation layer at a first depth from the C-plane of the silicon carbide substrate, The step of injecting the non-cleavage ion species forms the relaxation layer at a second depth from the Si-plane of the silicon carbide substrate. Method.

14. The method according to claim 11, wherein the step of injecting the non-cleavage ion species forms the relaxation layer between the Si-plane of the silicon carbide substrate and the separation layer.

15. The method according to claim 11, wherein the step of injecting the cleavage ion species includes injecting hydrogen ions into the silicon carbide substrate.

16. The method according to claim 11, wherein the step of injecting the non-cleavage ion species includes injecting helium ions into the silicon carbide substrate.

17. The method according to claim 11, wherein the step of separating the silicon carbide wafer from the silicon carbide substrate includes applying energy at a level sufficient to coalesce the pores of the separation layer.

18. The method according to claim 17, wherein the level of the energy is insufficient to coalesce the pores of the relaxation layer.

19. The method according to claim 11, including removing the residue of the separation layer from the silicon carbide wafer.

20. The method according to claim 11, including reusing the silicon carbide substrate to form another silicon carbide wafer after separating the silicon carbide wafer from the silicon carbide substrate.

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