Semiconductor device

Abstract

To provide a semiconductor device which uses an oxide semiconductor and achieves fining while maintaining good electrical characteristics.SOLUTION: A semiconductor device has: an oxide semiconductor film and a blocking film; a source electrode and a drain electrode which are electrically connected with the oxide semiconductor film; a gate insulation film contacting the oxide semiconductor film, the source electrode and the drain electrode; and a gate electrode contacting the gate insulation film. The blocking film uses the same material with the oxide semiconductor film formed on the same surface with the oxide semiconductor film and has higher conductivity than the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. Note that in this specification, the semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics. A display device, an electro-optical device, a semiconductor circuit, and an electric device may include a semiconductor device.

[0002]

Background Art

[0003] Techniques for constructing a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0004] For example, a transistor using an amorphous oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] With the high integration of circuits, an opening is provided in the interlayer insulating film between elements, and electrodes or wirings or the like are provided in the opening to electrically connect between the elements. When the element is a transistor using an oxide semiconductor film impurities such as hydrogen may enter the oxide semiconductor film from the opening, resulting in a reduction in resistance due to oxygen vacancies and hydrogen in the oxide semiconductor film, leading to poor electrical characteristics of the transistor.

[0007] In view of such problems, one aspect of the present invention is a semiconductor device using an oxide semiconductor, and one of the problems is to provide a highly reliable semiconductor device. Or, one aspect of the present invention is to provide a novel semiconductor device as one of the problems.

[0008] In addition, in order to achieve high-speed operation, low power consumption, low cost, high integration etc. of the transistor, miniaturization of the transistor is essential.

[0009] Therefore, one aspect of the present invention is a semiconductor device using an oxide semiconductor, and one of the problems is to provide a semiconductor device that achieves miniaturization while maintaining good electrical characteristics.

[0010] Note that the description of these problems does not prevent the existence of other problems. One aspect of the present invention is not required to solve all of these problems. Also, problems other than the above will be naturally revealed from the description in the specification etc., and it is possible to extract problems other than the above from the description in the specification etc.

Means for Solving the Problems

[0011] One aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using the same material and is characterized by having higher conductivity than the oxide semiconductor film. One aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using a material different from that of the oxide semiconductor film, the source electrode, and the drain electrode, and is characterized by having higher conductivity than the oxide semiconductor film. One aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using the same material and is characterized by having higher conductivity than the oxide semiconductor film. One aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using the same material and is characterized by having higher conductivity than the oxide semiconductor film.

[0012] Another aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using a material different from that of the oxide semiconductor film, the source electrode, and the drain electrode, and is characterized by having higher conductivity than the oxide semiconductor film. Another aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using a material different from that of the oxide semiconductor film, the source electrode, and the drain electrode, and is characterized by having higher conductivity than the oxide semiconductor film. Another aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using the same material and is characterized by having higher conductivity than the oxide semiconductor film. Another aspect of the present invention includes an oxide semiconductor film and a blocking film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is formed on the same surface as the oxide semiconductor film using the same material and is characterized by having higher conductivity than the oxide semiconductor film.

[0013] Also, in the above configuration, an insulating film is provided directly under the oxide semiconductor film and the blocking film, an opening is provided in the insulating film, and the distance between the blocking film and the oxide semiconductor film is shorter than the distance between the opening and the oxide semiconductor film. Also, in the above configuration, an insulating film is provided directly under the oxide semiconductor film and the blocking film, an opening is provided in the insulating film, and the distance between the blocking film and the oxide semiconductor film is shorter than the distance between the opening and the oxide semiconductor film. Also, in the above configuration, an insulating film is provided directly under the oxide semiconductor film and the blocking film, an opening is provided in the insulating film, and the distance between the blocking film and the oxide semiconductor film is shorter than the distance between the opening and the oxide semiconductor film.

[0014] Also, in the above configuration, a first transistor is provided under the insulating film. The first transistor includes a substrate containing a semiconductor material and is electrically connected to the source electrode or the drain electrode through the opening. Also, in the above configuration, a first transistor is provided under the insulating film. The first transistor includes a substrate containing a semiconductor material and is electrically connected to the source electrode or the drain electrode through the opening. Also, in the above configuration, a first transistor is provided under the insulating film. The first transistor includes a substrate containing a semiconductor material and is electrically connected to the source electrode or the drain electrode through the opening.

Advantages of the Invention

[0015] By using one aspect of the present invention, water in the oxide semiconductor film from other layers can be blocked by the blocking film. Since it has a function of suppressing the intrusion of impurities such as elements, it is possible to suppress defects in the electrical characteristics of the semiconductor device. Therefore, a highly reliable semiconductor device can be provided. Note that one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention may, in some cases or depending on the situation, have effects other than these effects. Or, for example, one aspect of the present invention may, in some cases or depending on the situation, not have these effects.

Brief Description of the Drawings

[0016]

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Mode for Carrying Out the Invention

[0017] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description thereof may be omitted.

[0018] Note that the functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are adopted or when the direction of current changes in the circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

[0019] Note that ordinal numbers such as "first" and "second" in this specification and the like are used to avoid confusion of components ​It is attached for the purpose of, and it is noted that it is not numerically limited.

[0020] (Embodiment 1) In this embodiment, a semiconductor device according to an aspect of the present invention will be described with reference to the drawings.

[0021] FIG. 1(A) and FIG. 1(B) are a top view and a cross-sectional view of a transistor according to an aspect of the present invention respectively. FIG. 1(A) is a top view, and the cross-section along the dashed-dotted line A1 - A2 shown in FIG. 1(A) corresponds to FIG. 1 (B). In the top view of FIG. 1(A), some elements are omitted for clarity of the drawing and shown. Also, the direction of the dashed-dotted line A1 - A2 may be referred to as the channel length direction, and the direction perpendicular to the direction of the dashed-dotted line A1 - A 2 may be referred to as the channel width direction. Note that the example of the top view is not limited to FIG. 1 (A). For example, a top view like FIG. 20 may also be used.

[0022] The transistor 150 shown in FIG. 1(A) and FIG. 1(B) includes a base insulating film 102 on the substrate 100, a conductive film 104a, a conductive film 104b, and a conductive film 104c on the base insulating film 102, an interlayer insulating film 106 on the base insulating film 102, the conductive film 104a, the conductive film 104b, and the conductive film 104c, an oxide semiconductor film 108a, a blocking film 108 b, and a blocking film 108c on the interlayer insulating film 106, a source electrode 110a that is electrically connected to the conductive film 104b through an opening 120a provided in the interlayer insulating film 106 and is on the oxide semiconductor film 108a and the blocking film 108b, and a drain electrode 110b that is electrically connected to the conductive film 104c through an opening 120b provided in the interlayer insulating film 106 and is on the oxide semiconductor film 108a and the blocking film 108c, and on the oxide semiconductor film 108a and the source electrode 1 and is electrically connected to the conductive film 104b through the opening 120a provided in the interlayer insulating film 106, and is on the oxide semiconductor film 108a and the blocking film 108b, and a drain electrode 110b that is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106 and is on the oxide semiconductor film 108a and the blocking film 108c, and on the oxide semiconductor film 108a and the source electrode 1 and is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106, and is on the oxide semiconductor film 108a and the blocking film 108c, and a drain electrode 110b that is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106 and is on the oxide semiconductor film 108a and the blocking film 108c, and on the oxide semiconductor film 108a and the source electrode 1 and is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106, and is on the oxide semiconductor film 108a and the blocking film 108c, and a drain electrode 110b that is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106 and is on the oxide semiconductor film 108a and the blocking film 108c, and on the oxide semiconductor film 108a and the source electrode 1 and is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106, and is on the oxide semiconductor film 108a and the blocking film 108c, and a drain electrode 110b that is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106 and is on the oxide semiconductor film 108a and the blocking film 108c, and on the oxide semiconductor film 108a and the source electrode 1 The gate insulating film 112 on the 10a and the drain electrode 110b, and the oxide semiconductor film 108a superimposed thereon, the gate electrode 114 on the gate insulating film 112, and the oxide insulating film 116 on the gate insulating film 112 and the gate electrode 114.

[0023] Note that the channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor film and the gate electrode overlap in the top view. That is, in Fig. 1(A), the channel length is the distance between the source electrode 110a and the drain electrode 11 0b in the region where the oxide semiconductor film 108 a and the gate electrode 114 overlap. The channel width refers to the width of the source or drain in the region where the semiconductor film and the gate electrode overlap. That is, in Fig. 1(A), the channel width is the width of the source electrode 110a or the drain electrode 110b in the region where the oxide semiconductor film 108a and the gate electrode 114 overlap. When the channel length and channel width of the transistor are miniaturized, if the electrode, semiconductor film, etc. are processed while retracting the resist mask, the upper ends of the electrode, semiconductor film, etc. may become rounded (have a curved surface). With such a configuration, the coverage of the gate insulating film 112, the gate electrode 114, and the oxide insulating film 116 formed on the oxide semiconductor film 108a can be improved. In addition, the possible electric field concentration occurring at the ends of the source electrode 110a and the drain electrode 110b can be alleviated, and the deterioration of the transistor can be suppressed.

[0024] When miniaturizing the channel length and channel width of the transistor, if the electrode, semiconductor film, etc. are processed while retracting the resist mask, the upper ends of the electrode, semiconductor film, etc. may become rounded (have a curved surface). With such a configuration, the coverage of the gate insulating film 112, the gate electrode 114, and the oxide insulating film 116 formed on the oxide semiconductor film 108a can be improved. In addition, the possible electric field concentration occurring at the ends of the source electrode 110a and the drain electrode 110b can be alleviated, and the deterioration of the transistor can be suppressed. Moreover, the blocking film 108b is closer to the oxide semiconductor film 108a than the opening 120a,

[0025] ​ That is, the distance between the blocking film 108b and the oxide semiconductor film 108a is shorter than the distance between the opening 120a and the oxide semiconductor film 108a. Similarly, the blocking film 108c is closer to the oxide semiconductor film 108a than the opening 1 20b. That is, the distance between the blocking film 108c and the oxide semiconductor film 108a is shorter than the distance between the opening 120b and the oxide semiconductor film 108a . .

[0026] By providing the blocking film as described above, impurities such as hydrogen that enter from other layers (for example, the layer between the silicon transistor and the like) through the opening are adsorbed by the blocking film, thereby having a function of suppressing the intrusion of impurities into the oxide semiconductor film, and thus it is possible to suppress deterioration of the electrical characteristics of the semiconductor device .

[0027] In addition, the blocking film can be formed on the same surface using the same material as the oxide semiconductor film . Therefore, the blocking film can be formed without increasing the number of processes . However, the blocking film is not limited to this, and may be made of a material different from the oxide semiconductor film and the source electrode (or drain electrode) .

[0028] Since the blocking film adsorbs impurities such as hydrogen, the impurity concentration is higher than that of the oxide semiconductor film . Therefore, the blocking film has higher conductivity than the oxide semiconductor film

[0029] In addition, the electric field of the gate electrode 114 can electrically surround the oxide semiconductor film 108a (The structure of the transistor that electrically surrounds the oxide semiconductor film by the electric field of the gate electrode is called a surrounded channel (s-channel) structure ). Therefore, a channel is formed in the entire (bulk) of the oxide semiconductor film 108a. In an n-channel structure, a large current can flow between the source and drain of the transistor, and a high on-current can be obtained.

[0030] Since a high on-current can be obtained, the n-channel structure can be said to be a structure suitable for miniaturized transistors. Since the transistors can be miniaturized, a semiconductor device having the transistors can be made into a highly integrated and high-density semiconductor device. For example, the channel length of the transistor is preferably 40 nm or less, more preferably 30 nm or less, even more preferably 20 nm or less, and the channel width of the transistor is preferably 4 0 nm or less, more preferably 30 nm or less, even more preferably 20 nm or less.

[0031] The substrate 100 is not limited to a mere support, and may be a substrate on which other elements such as other transistors and capacitors are formed. In this case, at least one of the gate electrode, source electrode, and drain electrode of the transistor may be electrically connected to the above-described other elements.

[0032] The underlying insulating film 102 has a role of preventing diffusion of impurities from the substrate 100, and can also play a role of supplying oxygen to the oxide semiconductor film 108a. Therefore, the underlying insulating film 102 is preferably an insulating film containing oxygen. For example, it is more preferably an insulating film containing more oxygen than the stoichiometric composition. Further, as described above, when the substrate 100 is a substrate on which other elements are formed, the underlying insulating film 102 also has a function as an interlayer insulating film. In that case, the surface of the underlying insulating film 102 may be planarized. For example, the underlying insulating film 10 ​​​It may be planarized by a CMP (Chemical Mechanical Polishing) method or the like in 2. It is sufficient to perform a planarization process.

[0033] The conductive film 104a can be used as the second gate electrode, and further increase the on-current or control the threshold voltage. To increase the on-current, the conductive film 10 4a and the gate electrode 114 are electrically connected to the same potential and driven as a dual-gate transistor It is sufficient. Also, to control the threshold voltage, the conductive film 104a and the gate electrode 114 are not electrically connected, and a fixed potential different from the gate electrode 114 is supplied to the conductive film 104a.

[0034] In addition, the conductive film 104b functions as a wiring electrically connected to the source electrode 110a, and the conductive film 104c functions as a wiring electrically connected to the drain electrode 110b. The conductive films 104b and 104c may be electrically connected to other elements such as transistors and capacitors.

[0035] However, one aspect of the embodiment of the present invention is not limited to this. The conductive film 104a does not necessarily have to be provided. Also, the conductive films 104b and 104c do not necessarily have to be provided. Top views and cross-sectional views in the case where the conductive films 104a, 104b, and 104c are not provided are shown in FIGS. 21(A) and 21(B).

[0036] The interlayer insulating film 106, like the underlying insulating film 102, has a role of preventing impurity diffusion and can also play a role of supplying oxygen to the oxide semiconductor film 108a. Therefore, the interlayer insulating film 106 is preferably an insulating film containing oxygen.

[0037] Hereinafter, the oxide semiconductor film 108a will be described in detail.

[0038] The oxide semiconductor film 108a is an oxide containing indium. The oxide, for example, when containing indium, has a high carrier mobility (electron mobility). Further, the oxide semiconductor film 10 8a preferably contains an element M. Examples of the element M include aluminum, gallium, y ttrium, or tin. The element M is, for example, an element having a high binding energy with oxygen. The element M is, for example, an element having a function of increasing the energy gap of the oxide. Further, the oxide semiconductor film 108a preferably contains zinc. When the oxide contains zinc, for example, the oxide is easily crystallized. The energy of the upper end of the valence band of the oxide can be controlled, for example, by the atomic ratio of zinc.

[0039] However, the oxide semiconductor film 108a is not limited to an oxide containing indium. The oxide semiconductor film 108a may be, for example, a Zn-Sn oxide or a Ga-Sn oxide.

[0040] Further, the oxide semiconductor film 108a uses an oxide having a large energy gap. The energy gap of the oxide semiconductor film 108a is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

[0041] When forming the oxide semiconductor film 108a by a sputtering method, it is preferable to use a target containing indium in order to reduce the number of particles. Further, the atomic ratio of the element M is When using a high-oxide target, the conductivity of the target may decrease. Indium When using a target containing um, the conductivity of the target can be increased, and DC discharge , AC discharge becomes easier, making it easier to handle large-area substrates. Therefore, semiconductor device productivity can be improved.

[0042] When forming the oxide semiconductor film 108a by sputtering, the atomic ratio of the target is , In:M:Zn can be 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1 , 1:1:2, etc.

[0043] When forming the oxide semiconductor film 108a by sputtering, a film with an atomic ratio deviated from the atomic ratio of the target may be formed. In particular, zinc may have a smaller atomic ratio in the film than in the atomic ratio of the target. Specifically, it may be about 40 atomic% or more and 90 atomic% or less of the atomic ratio of zinc contained in the target.

[0044] Hereinafter, the influence of impurities in the oxide semiconductor film 108a will be described. In order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor film 108a and achieve low carrier density and high purity. The carrier density of the oxide semiconductor film 108a is less than 1×10 17 3 15 3 13 3

[0045] ​​​​​​​​​​​​​​ For example, silicon in the oxide semiconductor film 108a may serve as a carrier trap or a carrier generation source. Therefore, the silicon concentration between the oxide semiconductor film 108a and the interlayer insulating film 106 is less than 1×10 atoms / cm in secondary ion mass spectrometry (SIMS), preferably less than 5×10 19 atoms / cm 3 , more preferably less than 2×10 atoms / cm 18 . Also, the silicon concentration between the oxide semiconductor film 108a and the gate insulating film 112 is less than 1×10 3 atoms / cm 18 in SIMS, preferably less than 5×10 atoms / cm 3 , more preferably less than 2×10 atoms / cm 19 . 3 Preferably , it is less than 5×10 18 atoms / cm 3 , and even more preferably less than 2×10 18 atoms / cm 3 .

[0046] In addition, if hydrogen is contained in the oxide semiconductor film 108a, the carrier density may increase. The hydrogen concentration of the oxide semiconductor film 108a is 2×10 20 atoms / cm or less in SIMS, preferably 5×10 3 atoms / cm 19 or less, more preferably 3 1×10 atoms / cm 19 or less, even more preferably 5×10 3 atoms / cm 18 or less. Also, if nitrogen is contained in the oxide semiconductor film 108a, the carrier density will 3 increase. may increase. The nitrogen concentration of the oxide semiconductor film 108a is , less than 5×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 or less, still more preferably 5×10 18 atoms / cm 3 or less. 1 7 atoms / cm 3 It is set as follows.

[0047] In addition, in order to reduce the hydrogen concentration of the oxide semiconductor film 108a, it is preferable to reduce the hydrogen concentration of the underlying insulating film 102 and the interlayer insulating film 106. The hydrogen concentration of the underlying insulating film 102 and the interlayer insulating film 106 is, in SIMS, 2×10 or less, preferably 5×1 20 atoms / cm 3 or less, more preferably 1×10 0 19 atoms / cm 3 or less, 19 atoms / cm 3 still more preferably 5×10 or less. Also, in order to reduce the nitrogen concentration of the oxide semiconductor film 1 18 atoms / cm 3 08a, it is preferable to reduce the nitrogen concentration of the underlying insulating film 102 and the interlayer insulating film 106. The nitrogen concentration of the underlying insulating film 102 and the interlayer insulating film 106 is, in SIMS , less than 5×10 , preferably less than 5×10 atoms / cm 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×1 0 17 atoms / cm 3 or less. It is set as follows.

[0048] Also, in order to reduce the hydrogen concentration of the oxide semiconductor film 108a, it is preferable to reduce the hydrogen concentration of the gate insulating film 112. The hydrogen concentration of the gate insulating film 112 is 2 × 10 in SIMS, preferably 5 × 10 20 atoms / cm 3 or less, more preferably 1 × 10 19 atoms / cm 3 or less, still more preferably 5 × 10 atoms / cm 19 or less, and even more preferably 5 × 10 3 atoms / cm 18 or less. Also, in order to reduce the nitrogen concentration of the oxide semiconductor film 108a, it is preferable to reduce the nitrogen concentration of the gate insulating film 112. The nitrogen concentration of the gate insulating film 112 is less than 5 × 10 3 atoms / cm in SIMS, preferably 5 × 10 atoms / cm 19 or less, more preferably 1 × 10 3 atoms / cm 18 or less, still more preferably 5 × 10 3 atoms / cm 18 or less, and even more preferably 5 × 10 3 atoms / cm or less. 17 atoms / cm 3

[0049] Hereinafter, the structure of the oxide semiconductor film applicable to the oxide semiconductor film 108a will be described.

[0050] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Cry stalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. ​​

[0051] First, we will explain the CAAC-OS film.

[0052] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is small enough to fit inside a cube with one side less than 100 nm. The crystals contained in the C-OS film are vertically aligned with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the size fits within a square.

[0053] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz crystal microscope, clear boundaries between crystal parts were observed, i.e. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0054] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on the surface (also called the surface on which the film is to be formed) or on the upper surface. The shape is a reflection of the CAAC-OS film and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0055] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0056] From cross-sectional TEM observation and plan-view TEM observation, it can be seen that the crystalline portions of the CAAC-OS film have orientation. It can be seen that.

[0057] For the CAAC-OS film, when structural analysis is performed using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystals, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0058] In this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

[0059] On the other hand, for the CAAC-OS film, in the analysis by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystals. If it is a single crystal oxide semiconductor film of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed in the vicinity of 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed in the vicinity of 56°.

[0060] From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystalline portions, but it has c-axis orientation and the c-axis is parallel to the normal vector of the formed surface or the upper surface. ​ Therefore, the layers confirmed by the cross-sectional TEM observation mentioned above are aligned in the same direction. Each layer of metal atoms arranged in a lattice pattern is parallel to the ab plane of the crystal.

[0061] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. Orientation is parallel to the normal vector of the top surface. When the shape of the film is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the forming surface or the top surface.

[0062] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to the AC-OS film, the crystallinity of the region to which the impurities are added changes, resulting in a partial In some cases, regions of differing crystallinity may be formed.

[0063] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0064] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon , silicon, and transition metal elements. In particular, elements such as silicon that have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film will disrupt the atomic arrangement of the oxide semiconductor film by depriving it of oxygen, resulting in a decrease in crystallinity . Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing crystallinity . Note that impurities contained in the oxide semiconductor film may serve as carrier traps or carrier generation sources . Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or may become carrier generation sources by capturing hydrogen .

[0065] When the impurity concentration is low and the defect level density is low (i.e., there are few oxygen deficiencies), it is called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered . Therefore, a transistor using such an oxide semiconductor film is less likely to have an electrical characteristic where the threshold voltage becomes negative (also called normally-on) . Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and is a highly reliable transistor

[0066] . . . . This becomes the case. Note that the charges trapped in the carrier traps of the oxide semiconductor film may take a long time to be released and may behave like fixed charges. Therefore, transistors using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. Moreover, the time required for release is long, and it may behave as if it were a fixed charge. Therefore, transistors using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. Moreover, the time required for release is long, and it may behave as if it were a fixed charge. Therefore, transistors using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. Moreover, the time required for release is long, and it may behave as if it were a fixed charge. Therefore, transistors using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0067] In addition, transistors using a CAAC-OS film have little variation in electrical characteristics due to irradiation with visible light or ultraviolet light. In addition, transistors using a CAAC-OS film have little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0068] Next, the microcrystalline oxide semiconductor film will be described.

[0069] In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film. In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film. In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film. In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film. In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film. In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film. In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, a nano crystal (nc: nanocrystalline) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is often present. An oxide semiconductor film having such nano crystals is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the crystal grain boundaries in the nc-OS film.

[0070] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, there is no overall orientation. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, there is no overall orientation. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, there is no overall orientation. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, there is no overall orientation. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. This may be the case. For example, when performing structural analysis on an nc-OS film using an XR D apparatus, in the analysis by the out-of-plane method, peaks indicating crystal planes are not detected. Also, for the nc-OS film, electron beam diffraction (also referred to as limited field of view electron beam diffraction) using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more) is performed, and a diffraction pattern such as a halo pattern is observed. On the other hand, for the nc-OS film , when electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less ) is performed, spots are observed. Also, when nano-beam electron beam diffraction is performed on the nc-OS film, regions with high luminance may be observed in a circular (ring-shaped) manner. Also, when nano-beam electron beam diffraction is performed on the nc-OS film, multiple spots may be observed within the ring-shaped region .

[0071] The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower defect level density than an amorphous oxide semiconductor film. However , the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher defect level density than the CAAC-OS film.

[0072] Note that the oxide semiconductor film may have two or more of, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C AAC-OS film.

[0073] The oxide semiconductor film 108a may be a laminated film of oxide semiconductor films. For example, the oxide semiconductor film 108a may have a two-layer structure or a three-layer structure.

[0074] For example, the case where the oxide semiconductor film 108a has a three-layer structure will be described. In FIG. 1(C), a case is shown where the oxide semiconductor film 108a is a laminated film in which an oxide semiconductor film 108a1, an oxide semiconductor film 108a2, and an oxide semiconductor film 108a3 are provided in this order.

[0075] For the oxide semiconductor film 108a2 (the middle layer), refer to the description of the oxide semiconductor film 108a up to this point. The oxide semiconductor film 108a1 (the lower layer) and the oxide semiconductor film 108a3 ( the upper layer) are oxide semiconductor films composed of one or more elements other than oxygen that constitute the oxide semiconductor film 108a2, or two or more elements. Since the oxide semiconductor films 108a1 and 108a3 are composed of one or more elements other than oxygen that constitute the oxide semiconductor film 108a2, or two or more elements, it is difficult for interface levels to be formed at the interface between the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2, and at the interface between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3. When the oxide semiconductor film 108a1 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 75 ato mic% or more for M. When the oxide semiconductor film 108a2 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomi c% or more for In and less than 75 atomic% for M, more preferably 34 atomic% or more for In and less than 66 atomic% for M. When the oxide semiconductor film 108a3 is an In-M-

[0076] Note that when the oxide semiconductor film 108a1 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 75 atomic% or more for M. When the oxide semiconductor film 108a2 is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomi c% or more for In and less than 75 atomic% for M, more preferably 34 atomic% or more for In and less than 66 atomic% for M. When the oxide semiconductor film 108a3 is an In-M- Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 75 ato mic% or more for M. Also, when the oxide semiconductor film 108a3 is an In-M- When it is a zinc oxide, the atomic ratio of In and M excluding Zn and O is preferably I n is less than 50 atomic %, M is 50 atomic % or more, more preferably In is 2 less than 5 atomic %, and M is 75 atomic % or more. Note that the oxide semiconductor film 10 8a3 may be made of the same kind of oxide as the oxide semiconductor film 108a1.

[0077] Here, between the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2, there may be a mixed region of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2. Also, between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3, there may be a mixed region of the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3. The mixed region has a lower interface level density. Therefore, the laminate of the oxide semiconductor film 108a1, the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 has a band structure in which energy changes continuously (also referred to as a continuous junction) near each interface. The oxide semiconductor film 108a2 is made of an oxide having a larger electron affinity than the oxide semiconductor film 108a1 and the oxide semiconductor film 108 a3. For example, as the oxide semiconductor film 108a2, an oxide having an electron affinity 0.

[0078] 07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3 is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. At this time, when an electric field is applied to the gate electrode 114, the oxide semiconductor film 108a1, the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3

[0079] When an electric field is applied to the gate electrode 114 at this time, the oxide semiconductor film 108a1, the oxide Of the semiconductor film 108a2 and the oxide semiconductor film 108a3, a channel is formed in the oxide semiconductor film 108a2 having a large electron affinity.

[0080] Also, for the on-current of the transistor, the thickness of the oxide semiconductor film 108a3 is preferably thinner. For example, the oxide semiconductor film 108a3 is less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the oxide semiconductor film 108a3 has a function of blocking elements other than oxygen (such as silicon) constituting the gate insulating film 112 from entering the oxide semiconductor film 108a2 where the channel is formed. Therefore, the oxide semiconductor film 108a3 preferably has a certain thickness. For example, the thickness of the oxide semiconductor film 108a3 is 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more.

[0081] Also, in order to improve reliability, the oxide semiconductor film 108a1 is preferably thick and the oxide semiconductor film 108a3 is preferably thin. Specifically, the thickness of the oxide semiconductor film 108a1 is 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, and even more preferably 60 nm or more. By setting the thickness of the oxide semiconductor film 108a1 to 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, and even more preferably 60 nm or more, the distance from the interface between the interlayer insulating film 106 and the oxide semiconductor film 108a1 to the oxide semiconductor film 108a2 where the channel is formed can be 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, and even more preferably 60 nm or more. However, since the productivity of the semiconductor device may decrease, the thickness of the oxide semiconductor film 108a1 is 200 nm or less, preferably ​Preferably, it is 120 nm or less, more preferably 80 nm or less.

[0082] For example, the silicon concentration between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a1 is, in SIMS, 1×10 19 atoms / cm 3 less than, preferably 5×1 0 18 atoms / cm 3 less than, more preferably 2×10 18 atoms / cm 3 less than. Similarly, the silicon concentration between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 is, in SIMS, 1×10 19 atoms / cm 3 less than, preferably 5 ×10 18 atoms / cm 3 less than, more preferably 2×10 18 atoms / cm 3 less than.

[0083] In addition, in order to reduce the hydrogen concentration of the oxide semiconductor film 108a2, it is preferable to reduce the hydrogen concentrations of the oxide semiconductor film 108 a1 and the oxide semiconductor film 108a3. The hydrogen concentrations of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3 are, in SIMS, 2×10 2 0 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, even more preferably 5×10 18 atoms / cm 3 or less. Also, in order to reduce the nitrogen concentration of the oxide semiconductor film 108a2, the acid It is preferable to reduce the nitrogen concentration in the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3. The nitrogen concentrations in the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3 are less than 5×10 19 atoms / cm 3 in SIMS, preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5 ×10 17 atoms / cm 3 or less.

[0084] The above three-layer structure is an example. For example, a two-layer structure without the oxide semiconductor film 108a1 or the oxide semiconductor film 108a3 may be used.

[0085] It is preferable to use a conductive film having the property of extracting oxygen from the oxide semiconductor film for the source electrode 110a and the drain electrode 110b. For example, as the conductive film having the property of extracting oxygen from the oxide semiconductor film, conductive films containing aluminum, titanium, chromium, nickel, molybdenum, tantalum, tungsten, etc. can be mentioned.

[0086] Due to the action of the conductive film having the property of extracting oxygen from the oxide semiconductor film, oxygen in the oxide semiconductor film may desorb, and oxygen vacancies may be formed in the oxide semiconductor film. The extraction of oxygen is more likely to occur at higher heating temperatures. Since there are several heating steps in the manufacturing process of the transistor, there is a high possibility that oxygen vacancies are formed in the region near the source electrode or the drain electrode of the oxide semiconductor film. Also, due to heating, at the sites of these oxygen vacancies Hydrogen may penetrate, and the oxide semiconductor film may be n-type. Therefore, due to the action of the source electrode and the drain electrode, the region where the oxide semiconductor film is in contact with the source electrode or the drain electrode can be made to have a low resistance, and the on-resistance of the transistor can be reduced. When producing a transistor with a small channel length (for example, 200 nm or less, or 100 nm or less), the source-drain may be short-circuited due to the formation of the n-type region. Therefore, when forming a transistor with a small channel length, a conductive film having the property of moderately extracting oxygen from the oxide semiconductor film may be used for the source electrode and the drain electrode.

[0087] Examples of the conductive film having the property of moderately extracting oxygen include a conductive film containing nickel, molybdenum, or tungsten. When producing a transistor with an extremely small channel length (for example, 40 nm or less, or 30 nm or less), a conductive film that hardly extracts oxygen from the oxide semiconductor film may be used as the source electrode and the drain electrode. Examples of the conductive film that hardly extracts oxygen from the oxide semiconductor film include a conductive film containing tantalum nitride, titanium nitride, or ruthenium. Note that a plurality of types of conductive films may be laminated. The gate insulating film 112 may be an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Also, the gate insulating film 112 may be made of the above materials. Examples of the conductive film having the property of moderately extracting oxygen include a conductive film containing nickel, molybdenum, or tungsten. When producing a transistor with an extremely small channel length (for example, 40 nm or less, or 30 nm or less), a conductive film that hardly extracts oxygen from the oxide semiconductor film may be used as the source electrode and the drain electrode.

[0088] Examples of the conductive film that hardly extracts oxygen from the oxide semiconductor film include a conductive film containing tantalum nitride, titanium nitride, or ruthenium. Note that a plurality of types of conductive films may be laminated. The gate insulating film 112 may be an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Also, the gate insulating film 112 may be made of the above materials. Examples of the conductive film having the property of moderately extracting oxygen include a conductive film containing nickel, molybdenum, or tungsten. When producing a transistor with an extremely small channel length (for example, 40 nm or less, or 30 nm or less), a conductive film that hardly extracts oxygen from the oxide semiconductor film may be used as the source electrode and the drain electrode.

[0089] Examples of the conductive film that hardly extracts oxygen from the oxide semiconductor film include a conductive film containing tantalum nitride, titanium nitride, or ruthenium. Note that a plurality of types of conductive films may be laminated. The gate insulating film 112 may be an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Also, the gate insulating film 112 may be made of the above materials. The gate insulating film 112 may be an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Also, the gate insulating film 112 may be made of the above materials. It may be a stack of materials. Note that the gate insulating film 112 may contain lanthanum, nitrogen, zirconium, etc. as impurities. as impurities.

[0090] The gate electrode 114 may be made of a conductive film containing one or more selected from aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, tungsten, etc. It is sufficient to use a conductive film containing one or more selected therefrom.

[0091] The oxide insulating film 116 may be an insulating film containing one or more selected from aluminum oxide, magnesium oxide, silicon oxide, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. It is possible to use an insulating film containing one or more selected therefrom.

[0092] Next, a method for manufacturing a transistor will be described with reference to FIGS. 2 to 4.

[0093] First, a base insulating film 102 is formed on the substrate 100 (see FIG. 2(A)).

[0094] The base insulating film 102 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a metal organic chemical vapor deposition (MOCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, a molecular beam epitaxy (MBE) method, an atomic layer deposition (ALD) method, or a pulsed laser deposition (PLD) method. Vapor Deposition) method, a metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method, a plasma enhanced chemical vapor deposition (PECVD: Plasma-En hanced CVD) method, a molecular beam epitaxy (MBE: Molecular Bea m Epitaxy) method, an atomic layer deposition (ALD: Atomic Layer Depos ition) method, or a pulsed laser deposition (PLD: Pulsed Laser Depo ​It may be formed by using a (sition) method. To reduce the damage caused by plasma, MO The CVD method or the ALD method is preferred.

[0095] Next, in order to planarize the surface of the underlying insulating film 102, a CMP process may be performed. CM By performing the P process, the average surface roughness (Ra) of the underlying insulating film 102 is set to 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. By setting Ra to the above numerical values or less, the crystallinity of the oxide semiconductor film 108a may be increased. Ra can be measured by an atomic force microscope (AFM: Atomic Force Microscope).

[0096] Next, an insulating film containing excess oxygen may be formed by adding oxygen to the underlying insulating film 102. The addition of oxygen may be performed by plasma treatment or ion implantation method or the like. When the addition of oxygen is performed by the ion implantation method, for example, the acceleration voltage is set to 2 kV or more and 100 kV or less, and the dose amount is set to 5×10 14 ions / cm 2 or more and 5×10 16 ions / cm 2 or less, and that's it.

[0097] Next, a conductive film 104a, a conductive film 104b, and a conductive film 104c are formed on the underlying insulating film 102 (see FIG. 2(B)). The conductive film 104a, the conductive film 104b, and the conductive film 104c are formed by using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method, and the same material as that of the gate electrode 114 can be used. To reduce the damage caused by plasma, the MOCVD method or the ALD method is preferred.

[0098] Next, an interlayer insulating film 105 is formed on the base insulating film 102, the conductive film 104a, the conductive film 104b, and the conductive film 104c (see Fig. 2(C)). The interlayer insulating film 105 may be formed using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method. To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. To planarize the surface of the interlayer insulating film 105, CMP processing may be performed. By performing CMP processing, the average surface roughness (Ra) of the interlayer insulating film 105 is set to 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. By setting Ra to the values described above, the crystallinity of the oxide semiconductor film 108a may be increased. Next, openings 120a reaching the conductive film 104b and openings 120b reaching the conductive film 104c are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 3(A)). Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. To planarize the surface of the interlayer insulating film 105, CMP processing may be performed. By performing CMP processing, the average surface roughness (Ra) of the interlayer insulating film 105 is set to 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. By setting Ra to the values described above, the crystallinity of the oxide semiconductor film 108a may be increased. Next, openings 120a reaching the conductive film 104b and openings 120b reaching the conductive film 104c are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 3(A)). Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, openings 120a reaching the conductive film 104b and openings 120b reaching the conductive film 104c are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 3(A)). Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c.

[0099] Next, openings 120a reaching the conductive film 104b and openings 120b reaching the conductive film 104c are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 3(A)). Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c.

[0100] Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c. Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the interlayer insulating film 106 using a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method, or a PLD method (see Fig. 3(B)). To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable. At this time, the interlayer insulating film 106 may be moderately etched. By moderately etching the interlayer insulating film 106, it is possible to easily cover the oxide semiconductor film 108a with the gate electrode 114 formed later. In addition, in order to miniaturize the transistor, a hard mask may be used during the processing of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c.

[0101] Further, when forming a stacked film including the oxide semiconductor film 108a, the oxide semiconductor film 108a1, the oxide semiconductor film 1 08a2, and the oxide semiconductor film 108a3, it is preferable to form each layer continuously without exposing them to the air.

[0102] In order to reduce the incorporation of impurities and form an oxide semiconductor film with high crystallinity, the oxide semiconductor film 108a is formed with the substrate temperature being 100°C or higher, preferably 150°C or higher, and more preferably 2 00°C or higher. Also, the oxygen gas and argon gas used as the film-forming gas are highly purified gases with a dew point of -40°C or lower, preferably -80°C or lower, and more preferably -100°C or lower. Note that a low impurity concentration and a low defect level density (less oxygen deficiency) are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0103] After the formation of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c, a first heat treatment may be performed. The first heat treatment may be carried out at a temperature of 250°C or higher and 650°C or lower , preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under a reduced pressure state. Also, for the atmosphere of the first heat treatment, after heat treatment in an inert gas atmosphere, an atmosphere containing 10 p pm or more of an oxidizing gas may be used to supplement the desorbed oxygen. By the first heat treatment, the crystallinity of the oxide semiconductor film 108a is enhanced, and furthermore, impurities such as hydrogen and water can be removed from the oxide semiconductor film 108a, the underlying insulating film 102, and the interlayer insulating film 1 06.

[0104] Note that after forming an opening in the interlayer insulating film, the oxide semiconductor film and the blocking film are formed. This is not limited thereto, and an opening may be formed in the interlayer insulating film after forming the oxide semiconductor film and the blocking film. It may be formed.

[0105] Next, it is electrically connected to the conductive film 104b through the opening 120a provided in the interlayer insulating film 106, and the source electrode on the oxide semiconductor film 108a and the blocking film 108b 110a, and is electrically connected to the conductive film 104c through the opening 120b provided in the interlayer insulating film 106, and the drain electrode 110b on the oxide semiconductor film 108a and the blocking film 108c is formed (see FIG. 3(C)). The source electrode 110a and the drain electrode 110b may be formed by a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method , an ALD method or a PLD method. To reduce damage by plasma, the MOCVD method or the ALD method is preferable. When etching the conductive film that becomes the source electrode 110a and the drain electrode 110b, the upper ends of the source electrode 110a and the drain electrode 110b may be rounded (have a curved surface). Also, when etching the conductive film that becomes the source electrode 11 0a and the drain electrode 110b, the interlayer insulating film 106 may be appropriately etched. Next, a gate insulating film 112 is formed on the oxide semiconductor film 108a, on the source electrode 110a, and on the drain electrode 110b (see FIG. 4(A)). The gate insulating film 112 may be formed by a sputtering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method or a PL D method. To reduce damage by plasma, the MOCVD method or the ALD method is preferable.

[0106] tering method, a CVD method, a MOCVD method, a PECVD method, an MBE method, an ALD method or a PL D method. To reduce damage by plasma, the MOCVD method or the ALD method is preferable. D method. To reduce damage by plasma, the MOCVD method or the ALD method is preferable. Or the ALD method is preferable.

[0107] ​​​ Next, a gate electrode 114 is formed on the gate insulating film 112 (see FIG. 4(B)).

[0108] Next, an oxide insulating film 116 is formed on the gate insulating film 112 and the gate electrode 114 (see FIG. 4(C)). The oxide insulating film 116 may be formed using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

[0109] Next, a second heat treatment may be performed. The second heat treatment can be performed under the same conditions as the first heat treatment. The oxygen deficiency of the oxide semiconductor film 108a may be reduced by the second heat treatment.

[0110] Through the above steps, the transistors shown in FIGS. 1(A) and 1(B) can be fabricated.

[0111] <Modification Example of Transistor Structure> Also, conductive films 118a and 118b that are electrically connected to the source electrode 110a and the drain electrode 110b and function as wiring may be provided on the oxide insulating film 116 as in the transistor shown in FIG. 5(A). The conductive films 118a and 118b may be electrically connected to other elements such as transistors and capacitors.

[0112] Also, as in the transistor shown in FIG. 5(B), the oxide semiconductor film 108a has a three-layer structure, and an oxide semiconductor film 108a1, an oxide semiconductor film 108a2, blocking films 108b1, 108b2, 108c1, and 108c2 are provided on the interlayer insulating film, and an oxide semiconductor film 108a3 is provided on the source electrode and the drain electrode ​​​​​​​​​It may be configured to provide. Also, the oxide semiconductor film 108a3 and the gate insulating film may be etched using the gate electrode as a mask. electrode as a mask.

[0113] <Modification example of transistor structure> Also, a channel protection film 128 may be provided on the oxide semiconductor film 108a as in the transistor shown in FIG. 10. By providing the channel protection film 128, the oxide semiconductor film 108a is not exposed to the etching gas, and impurities between the oxide semiconductor film 108a and the channel protection film 128 can be reduced. As a result, the leakage current flowing between the source electrode and the drain electrode of the transistor can be reduced. 128 may be provided. By providing the channel protection film 128, the oxide semiconductor film 108a is not exposed to the etching gas, and impurities between the oxide semiconductor film 108a and the channel protection film 128 can be reduced. exposed to the etching gas, and impurities between the oxide semiconductor film 108a and the channel protection film 128 can be reduced. As a result, the leakage current flowing between the source electrode and the drain electrode of the transistor can be reduced. leakage current flowing between the source electrode and the drain electrode of the transistor can be reduced.

[0114] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. be combined.

[0115] (Embodiment 2) In this embodiment, a semiconductor device different from that in Embodiment 1 will be described with reference to the drawings. will be described with reference to the drawings.

[0116] FIGS. 6(A) and 6(B) are a top view and a cross-sectional view of a transistor according to an aspect of the present invention. FIG. 6(A) is a top view, and the cross-section along the dashed-dotted line B1 - B2 shown in FIG. 6(A) corresponds to FIG. 6(B). In the top view of FIG. 6(A), some elements are omitted for clarity of the drawing. Also, the direction of the dashed-dotted line B1 - B2 may be referred to as the channel length direction, and the direction perpendicular to the direction of the dashed-dotted line B1 - B2 may be referred to as the channel width direction. FIG. 6(A) is a top view, and the cross-section along the dashed-dotted line B1 - B2 shown in FIG. 6(A) corresponds to FIG. 6(B). In the top view of FIG. 6(A), some elements are omitted for clarity of the drawing. (B). In the top view of FIG. 6(A), some elements are omitted for clarity of the drawing. are shown. Also, the direction of the dashed-dotted line B1 - B2 may be referred to as the channel length direction, and the direction perpendicular to the direction of the dashed-dotted line B1 - B 2 may be referred to as the channel width direction.

[0117] The transistor 250 shown in FIGS. 6(A) and 6(B) includes a base insulating film 102 on the substrate 100, a gate electrode 114 on the base insulating film 102, and the base insulating film 102 and the gate electrode 102 and the gate electrode 114, The gate insulating film 112 on the pole 114, the source electrode 110a on the gate insulating film 112, and the drain electrode 110b, the gate insulating film 112, the source electrode 110a, and the drain electrode 110b, the oxide semiconductor film 108a thereon, the blocking film 108 b on the source electrode 110a, the blocking film 108c on the drain electrode 110b, the source electrode 110a, the dra in electrode 110b, the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c, the interlayer insulating film 106 thereon, the conductive film 104a on the interlayer insulating film 106, and the interlayer ins ulation film 106 is electrically connected to the source electrode 110a through the opening 120a provided therein, and the conductive film 104b on the interlayer insulating film 106, and the conductive film 104b is electrically connected to the drain electrode 110b through the opening 1 20b provided in the interlayer insulating film 106, and the conductive film 104c on the interlayer insulating film 106. It has.

[0118] The blocking film 108b is closer to the oxide semiconductor film 108a than the opening 120a, that is, the distance between the blocking film 108b and the oxide semiconductor film 108a is shorter than the distance between the opening 120a and the oxide semiconductor film 108a. Similarly, the blocking film 108c is closer to the oxide semiconductor film 108a than the opening 120b that is, the distance between the blocking film 108c and the oxide semiconductor film 108a is shorter than the distance between the opening 120b and the oxide semiconductor film 108a.

[0119] By providing the blocking film as described above, impurities such as hydrogen that enter from other layers through the opening are adsorbed by the blocking film, so that impurities do not enter the oxide semiconductor film. Therefore, it has a function of suppressing the intrusion of impurities, and it is possible to suppress deterioration of the electrical characteristics of the semiconductor device.

[0120] Further, the blocking film can be formed on the same surface using the same material as the oxide semiconductor film. Therefore, the blocking film can be formed without increasing the number of steps. Not limited to this, the blocking film may be made of a material different from the oxide semiconductor film and the source electrode (or drain electrode).

[0121] Since the blocking film adsorbs impurities such as hydrogen, the impurity concentration is higher than that of the oxide semiconductor film. Therefore, the blocking film has higher conductivity than the oxide semiconductor film.

[0122] Next, a method for manufacturing a transistor will be described with reference to FIGS. 7 to 9.

[0123] First, a base insulating film 102 is formed on a substrate 100 (see FIG. 7(A)). The material and manufacturing method of the base insulating film 102 can refer to Embodiment 1.

[0124] Next, a gate electrode 114 is formed on the base insulating film 102 (see FIG. 7(B)). The material and manufacturing method of the gate electrode 114 can refer to Embodiment 1.

[0125] Next, a gate insulating film 112 is formed on the base insulating film 102 and the gate electrode 114 (see FIG. 7(C)). The material and manufacturing method of the gate insulating film 112 can refer to Embodiment 1.

[0126] Next, a source electrode 110a and a drain electrode 110b are formed on the gate insulating film 112 (see FIG. 8(A)). The material and manufacturing method of the source electrode 110a and the drain electrode 110b can refer to Embodiment 1.

[0127] Next, an oxide semiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed on the gate insulating film 112, the source electrode 110a, and the drain electrode 110b. (see Fig. 8(B)). The materials and manufacturing methods of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c can refer to Embodiment 1. (see Fig. 8(B)). The materials and manufacturing methods of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c can refer to Embodiment 1. The materials and manufacturing methods of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c can refer to Embodiment 1.

[0128] Also, when forming a stacked film including the oxide semiconductor film 108a1, the oxide semiconductor film 108a2, and the oxide semiconductor film 108a3 as the oxide semiconductor film 108a, it is preferable to form each layer continuously without exposing it to the air. Also, when forming a stacked film including the oxide semiconductor film 108a1, the oxide semiconductor film 108a2, and the oxide semiconductor film 108a3 as the oxide semiconductor film 108a, it is preferable to form each layer continuously without exposing it to the air. Also, when forming a stacked film including the oxide semiconductor film 108a1, the oxide semiconductor film 108a2, and the oxide semiconductor film 108a3 as the oxide semiconductor film 108a, it is preferable to form each layer continuously without exposing it to the air.

[0129] After forming the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c, a first heat treatment may be performed. The details of the first heat treatment can refer to Embodiment 1. After forming the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c, a first heat treatment may be performed. The details of the first heat treatment can refer to Embodiment 1. The details of the first heat treatment can refer to Embodiment 1.

[0130] Next, an interlayer insulating film 105 is formed on the oxide semiconductor film 108a, the blocking film 108b, the blocking film 108c, the source electrode 110a, and the drain electrode 110b (see Fig. 8(C)). The materials and manufacturing methods of the interlayer insulating film 105 can refer to Embodiment 1. Next, an interlayer insulating film 105 is formed on the oxide semiconductor film 108a, the blocking film 108b, the blocking film 108c, the source electrode 110a, and the drain electrode 110b (see Fig. 8(C)). The materials and manufacturing methods of the interlayer insulating film 105 can refer to Embodiment 1. The materials and manufacturing methods of the interlayer insulating film 105 can refer to Embodiment 1. The materials and manufacturing methods of the interlayer insulating film 105 can refer to Embodiment 1.

[0131] Next, an opening 120a reaching the source electrode 110a and an opening 120b reaching the drain electrode 110b are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 9(A)). Next, an opening 120a reaching the source electrode 110a and an opening 120b reaching the drain electrode 110b are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 9(A)). Next, an opening 120a reaching the source electrode 110a and an opening 120b reaching the drain electrode 110b are formed in the interlayer insulating film 105, and an interlayer insulating film 106 is formed (see Fig. 9(A)).

[0132] Next, the conductive film 104a on the interlayer insulating film 106 is electrically connected to the source electrode 110a through the opening 120a provided in the interlayer insulating film 106, and the conductive film 104a on the interlayer insulating film 106 is electrically connected to the source electrode 110a through the opening 120a provided in the interlayer insulating film 106, and the conductive film The drain electrode 1 is connected to the insulating film 104b via an opening 120b provided in the interlayer insulating film 106. 10b and a conductive film 104c on the interlayer insulating film 106. 9B). The conductive film 104a, the conductive film 104b, and the conductive film 104c are Condition 1 may be taken into consideration.

[0133] Next, a second heat treatment may be performed. The second heat treatment may be performed under the same conditions as the first heat treatment. The second heat treatment can be performed under the following conditions. It may be possible to reduce it.

[0134] Through the above steps, the transistor shown in FIG. 6 can be manufactured.

[0135] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0136] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to FIG. This will be described with reference to the following.

[0137] [Cross-sectional structure] FIG. 11A shows a cross-sectional view of a semiconductor device of one embodiment of the present invention. The device has a transistor 2200 using a first semiconductor material on the bottom and a second The transistor 2100 is made of a semiconductor material. As the transistor 2100 using a dielectric material, the transistor exemplified in Embodiment 1 is used. An example of its use is shown.

[0138] The first and second semiconductor materials preferably have different band gaps. Yes. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material can be an oxide semiconductor. Transistors using materials other than oxide semiconductors, such as single-crystal silicon, are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors have low off-currents.

[0139] Transistor 2200 can be either an n-channel transistor or a p-channel transistor, and an appropriate transistor can be used depending on the circuit. Also, except for using the transistor of one aspect of the present invention using an oxide semiconductor, the specific configuration of the semiconductor device, such as the materials and structures used, need not be limited to what is shown here.

[0140] In the configuration shown in FIG. 11(A), transistor 2100 is provided above transistor 2200 via insulating film 2201 and insulating film 2207. Also, a plurality of wirings 2202 are provided between transistor 220 0 and transistor 2100. Also, a plurality of plugs 2203 embedded in various insulating films electrically connect the wirings and electrodes provided in the upper and lower layers, respectively. Further, an insulating film 2204 covering transistor 2100, a wiring 2205 on insulating film 2204, and a wiring 2206 obtained by processing the same conductive film as a pair of electrodes of transistor 2100 are provided.

[0141] In this way, by stacking two types of transistors, the occupied area of the circuit is reduced, and a plurality of circuits can be arranged at higher density.

[0142] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer , hydrogen in the insulating film provided near the semiconductor film of the transistor 2200 terminates the dangling bond of silicon, and has the effect of improving the reliability of the transistor 2200. On the other hand , when an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulating film provided near the semiconductor film of the transistor 2 100 becomes one of the factors for generating carriers in the oxide semiconductor, so there is a case where it becomes a factor for reducing the reliability of the transistor 2100 . Therefore, when the transistor 2100 using an oxide semiconductor is laminated and provided on the upper layer of the transistor 2200 using a silicon-based semiconductor material, it is particularly effective to provide the insulating film 2207 having a function of preventing the diffusion of hydrogen between them. By the insulating film 22 07, by confining hydrogen in the lower layer, the reliability of the transistor 2200 is improved. In addition , by suppressing the diffusion of hydrogen from the lower layer to the upper layer, the reliability of the transistor 2100 can also be improved simultaneously . As the insulating film 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide , gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide , hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used .

[0143]

[0144] In addition, it is preferable to form an insulating film 2208 having a function of preventing the diffusion of hydrogen on the transistor 2100 so as to cover the transistor 2100 including the oxide semiconductor film . As the insulating film 2208, the same material as the insulating film 2207 can be used . Particularly, it is preferable to apply aluminum oxide. The aluminum oxide film has a high blocking effect that does not allow the film to permeate both hydrogen, moisture, any impurities, and oxygen. Therefore, by using an aluminum oxide film as the insulating film 2208 covering the transistor 2100, desorption of oxygen from the oxide semiconductor film contained in the transistor 2100 can be prevented, and at the same time, the entry of water and hydrogen into the oxide semiconductor film can be prevented.

[0145] [Circuit configuration example] In the above configuration, various circuits can be configured by varying the connection configuration of the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0146] [CMOS circuit] The circuit diagram shown in FIG. 11(B) shows a configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

[0147] [Analog switch] Also, the circuit diagram shown in FIG. 11(C) shows a configuration in which the sources and drains of the transistor 2100 and the transistor 2200 are connected. With such a configuration, it can function as a so-called analog switch.

[0148] [Example of memory device] An example of a semiconductor device (memory device) that can hold the stored content even when power is not supplied and has no limitation on the number of write operations by using the transistor according to one aspect of the present invention is shown in FIG. 12.

[0149] The semiconductor device shown in Fig. 12(A) includes a transistor 3200 using a first semiconductor material and a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that as the transistor 3300, the transistor described in the above embodiment can be used.

[0150] The transistor 3300 is a transistor in which a channel is formed in a semiconductor film having an oxide semiconductor. Since the transistor 3300 has a small off-current, it is possible to retain the stored content for a longer period by using it. That is, it is possible to make a semiconductor memory device that does not require a refresh operation or requires a very low frequency of refresh operation, so that the power consumption can be sufficiently reduced.

[0151] In Fig. 12(A), the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Also, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. Then, the gate electrode of the transistor 3200 and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other electrode of the capacitor element 3400.

[0152] In the semiconductor device shown in Fig. 12(A), the potential of the gate electrode of the transistor 3200 is held. ​​​​​By taking advantage of the feature of being possible, writing, holding, and reading of information can be performed as follows. This is the case.

[0153] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, and the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (writing). Here, either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Subsequently, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, and the transistor 3300 is turned off. As a result, the charge applied to the gate electrode of the transistor 3200 is held (holding). Since the off-current of the transistor 3300 is extremely small, the charge of the gate electrode of the transistor 3200 is held for a long time.

[0154]

[0155] Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes different potentials according to the amount of charge held in the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold value V when a High level charge is applied to the gate electrode of the transistor 3200 th_ H ​​​​​​​​​​​This is because the apparent threshold voltage V is lower when a low-level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to turn on the transistor 3200. th_L Therefore, by setting the potential of the fifth wiring 3005 to V0 between V and V, the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, when a high-level charge is applied, if the potential of the fifth wiring 3005 becomes V0 (> V), th_H the transistor 3200 turns on. When a low-level charge is applied, th_L even if the potential of the fifth wiring 3005 becomes V0 (< V), the transistor 3200 remains off. Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out. th_H th_L

[0156]

[0157] When the memory cells are arranged and used in an array, it is necessary to be able to read out only the information of the desired memory cell. When the information is not read out in this way, a potential such that the transistor 3200 turns off regardless of the state of the gate electrode, that is, a potential smaller than V, th_ H may be applied to the fifth wiring 3005. Or, a potential such that the transistor 3200 turns on regardless of the state of the gate electrode, that is, a potential larger than V, th_L

[0157] may be applied to the fifth wiring 3005.

[0157] The semiconductor device shown in Fig. 12(B) is mainly different from Fig. 1 2(A) in that it does not have transistor 3200. Also in this case, writing and holding of information operations are possible by the same operation as above.

[0158] Next, reading of information will be described. When transistor 3300 is turned on, the floating third wiring 3003 and the capacitor element 3400 are electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor element 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 takes different values depending on the potential of one of the electrodes of the capacitor element 3400 (or the charge stored in the capacitor element 3400).

[0159] For example, if the potential of one of the electrodes of the capacitor element 3400 is V, the capacitance of the capacitor element 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge redistribution is VB0, then the potential of the third wiring 3003 after charge redistribution is (CB ×VB0 + C×V) / (CB + C). Therefore, assuming that the potential of one of the electrodes of the capacitor element 3400 takes two states of V1 and V0 (V1 > V0) as the state of the memory cell, it can be seen that the potential of the third wiring 3003 when holding the potential V1 (=(CB×VB0 + C×V1 ) / (CB + C)) is higher than the potential of the third wiring 3003 when holding the potential V0 (=( CB×VB0 + C×V0) / (CB + C)). And by comparing the potential of the third wiring 3003 with a predetermined potential, information can be read

[0160] out.

[0161] ​In this case, the first semiconductor material is applied to a drive circuit for driving a memory cell using a transistor, and a transistor to which a second semiconductor material is applied as transistor 3300 is stacked and provided on the drive circuit.

[0162] In the semiconductor device according to the present embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for a long time. Also, in the semiconductor device according to the present embodiment, a high voltage is not required for writing information, and there is no problem of element degradation. For example, unlike a conventional nonvolatile memory, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, problems such as degradation of the gate insulating film do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional nonvolatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can also be easily realized.

[0163]

[0164] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0165] (Embodiment 4) ​​​​​​​​​​​​​In this embodiment, an R including the transistor or the memory device described in the previous embodiment The RF tag will be described with reference to FIG. 13.

[0166] The RF tag in this embodiment has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Due to such characteristics, the RF tag can be used in an individual authentication system that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. The configuration of the RF tag will be described with reference to FIG. 13. FIG. 13 is a block diagram showing a configuration example of the RF tag. As shown in FIG. 13, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication For use in these applications Extremely high reliability is required.

[0167] The configuration of the RF tag will be described with reference to FIG. 13. FIG. 13 is a block diagram showing a configuration example of the RF tag. block diagram.

[0168] As shown in FIG. 13, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication A material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for the transistor showing a rectifying action included in the demodulation circuit 807. Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication Thereby, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication The output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format includes an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a method in which radio waves are used for communication communication The RF tag 800 shown in this embodiment can be used with any of these three methods. It is also possible to use it in the method.

[0169] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential. A limiter circuit may be provided on the output side or on the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0170] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0171] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0172] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds the input information, including a row decoder, a column decoder, a memory area, etc. It has. Also, ROM811 stores unique numbers (IDs), etc., and outputs according to the processing. It is a circuit for performing.

[0173] Note that each of the above circuits can be appropriately selected or discarded as necessary.

[0174] Here, the storage device described in the previous embodiment can be used as the storage circuit 810. . Since the storage device according to one aspect of the present invention can hold information even when the power is cut off, it can be suitably used for RF tags. Furthermore, since the storage device according to one aspect of the present invention requires significantly less power (voltage) for writing data compared to conventional non-volatile memories, it is also possible not to cause a difference in the maximum communication distance between reading and writing of data. Furthermore, it is possible to suppress the occurrence of malfunction or incorrect writing due to insufficient power during data writing.

[0175] Also, the storage device according to one aspect of the present invention can be used as a non-volatile memory, so it can also be applied to ROM811. In that case, it is preferable for the manufacturer to prepare a separate command for writing data to ROM811 and prevent the user from freely rewriting it. By doing so, after the manufacturer writes the unique number before shipping and then ships the product, it becomes possible to assign unique numbers only to the good products to be shipped, rather than to all the manufactured RF tags, and it becomes easier to manage customers corresponding to the products after shipping without the unique numbers of the products after shipping being discontinuous.

[0176] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. It can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0177] (Embodiment 5) In this embodiment, at least the transistors described in the above embodiments can be used, and a CPU including the memory device described in the previous embodiments will be described. It can be implemented using at least some of the transistors described in the previous embodiments, and a CPU including the memory device described in the previous embodiments will be described.

[0178] FIG. 14 is a block diagram showing a configuration example of a CPU using at least some of the transistors described in the previous embodiments. It is a block diagram showing a configuration example of a CPU using at least some of the transistors described in the previous embodiments.

[0179] The CPU shown in FIG. 14 has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 14 is only an example shown with its configuration simplified, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU or the arithmetic circuit shown in FIG. 14 may be regarded as one core, and a configuration in which a plurality of such cores are included and each core operates in parallel may be used. Also, the number of bits that the CPU can handle with an internal arithmetic circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 bits, 32 bits, 64 bits, etc. bits, 32 bits, 64 bits, etc. It can be 4 bits or the like.

[0180] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, and after being decoded, they are input to the ALU controller 1192, the inter rupt controller 1194, the register controller 1197, and the timing controller 1195.

[0181] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program, based on their priorities and mask states. The register controller 1197 generates the addresses of the registers 1196 and performs read and write operations on the registers 1196 according to the state of the CPU. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program, based on their priorities and mask states. The register controller 1197 generates the addresses of the registers 1196 and performs read and write operations on the registers 1196 according to the state of the CPU. The register controller 1197 generates the addresses of the registers 1196 and performs read and write operations on the registers 1196 according to the state of the CPU.

[0182] In addition, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, the ALU controller 11 92, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits described above. The timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits described above.

[0183] In the CPU shown in FIG. 14, a memory cell is provided in register 1196. The register As the memory cell of register 1196, the transistors shown in the previous embodiment can be used for this purpose.

[0184] In the CPU shown in FIG. 14, register controller 1197 selects the holding operation in register 1196 according to an instruction from ALU 1191. That is, in the memory cell included in register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cell in register 1196 is performed. When holding data in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power supply voltage to the memory cell in register 1196 can be stopped.

[0185] FIG. 15 is an example of a circuit diagram of a storage element that can be used as register 1196. Storage element 1200 includes a circuit 1201 in which stored data is volatile when the power supply is cut off, a circuit 1202 in which stored data is non-volatile when the power supply is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210. Note that storage element 1200 may further include other elements such as a diode, a resistance element, and an inductor as necessary.

[0186] Here, the storage device described in the previous embodiment can be used for circuit 1202. ​​​​​​​​​​​​​When the supply of the power voltage to the memory element 1200 is stopped, the gate of the transistor 12 09 is input with the ground potential (0V) or a potential at which the transistor 1209 is turned off and continues to be so. For example, the gate of the transistor 1209 is grounded via a load such as a resistor to form a configuration.

[0187] The switch 1203 is configured using a transistor 1213 of one conductivity type (for example, an n-channel type), and the switch 1204 is configured using a transistor 1214 of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example is shown here. Here, the first terminal of the switch 1203 corresponds to one of the source and drain of the transistor 1213, and the second terminal of the switch 1203 corresponds to the other of the source and drain of the transistor 1213. The switch 1203 is controlled by a control signal RD input to the gate of the transistor 1213 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 1213). The first terminal of the switch 1204 corresponds to one of the source and drain of the transistor 1214, and the second terminal of the switch 1204 corresponds to the other of the source and drain of the transistor 1214. The switch 1204 is controlled by a control signal RD input to the gate of the transistor 1214 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 1214). One of the source and drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitor element 1208 and the gate of the transistor 1210. Here, the connection is made. The switch 1204 is controlled by a control signal RD input to the gate of the transistor 1214 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 1214). The on state or off state of the transistor 1214) is selected.

[0188] One of the source and drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitor element 1208 and the gate of the transistor 1210. Here, the connection is made. Let the part be node M2. One of the source and drain of transistor 1210 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage, and the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). The other of the source and drain of transistor 1210 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage, and the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). One of the source and drain of transistor 1210 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage, and the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). One of the source and drain of transistor 1210 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage, and the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). The second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain of transistor 1214). The second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain of transistor 1214). The second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of switch 1203 (the other of the source and drain of transistor 1213), the first terminal of switch 1204 (one of the source and drain of transistor 1214), the input terminal of logic element 1206, and one of the pair of electrodes of capacitive element 1207 are electrically connected. Here, let the connection part be node M1. The second terminal of switch 1203 (the other of the source and drain of transistor 1213), the first terminal of switch 1204 (one of the source and drain of transistor 1214), the input terminal of logic element 1206, and one of the pair of electrodes of capacitive element 1207 are electrically connected. Here, let the connection part be node M1. The other of the pair of electrodes of capacitive element 1207 can be configured to have a constant potential input. For example, it can be configured to have a low power supply voltage (such as GND) or a high power supply voltage (such as VDD) input. The other of the pair of electrodes of capacitive element 1207 can be configured to have a constant potential input. For example, it can be configured to have a low power supply voltage (such as GND) or a high power supply voltage (such as VDD) input. The other of the pair of electrodes of capacitive element 1207 can be configured to have a constant potential input. For example, it can be configured to have a low power supply voltage (such as GND) or a high power supply voltage (such as VDD) input. The other of the pair of electrodes of capacitive element 1207 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage. The other of the pair of electrodes of capacitive element 1207 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage. The other of the pair of electrodes of capacitive element 1208 can be configured to have a constant potential input. For example, it can be configured to have a low power supply voltage (such as GND) or a high power supply voltage (such as VDD) input. The other of the pair of electrodes of capacitive element 1208 can be configured to have a constant potential input. For example, it can be configured to have a low power supply voltage (such as GND) or a high power supply voltage (such as VDD) input. The other of the pair of electrodes of capacitive element 1208 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage. The other of the pair of electrodes of capacitive element 1208 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply voltage.

[0189] Note that the capacitance elements 1207 and 1208 can also be omitted by actively using parasitic capacitances of transistors, wirings, etc. It is also possible to omit them.

[0190] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state. When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state. When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

[0191] A signal corresponding to the data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. In FIG. 15, an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209 is shown. The signal output from the second terminal (the other of the source and the drain of the transistor 1213) of the switch 1203 becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220.

[0192] Note that in FIG. 15, an example in which the signal output from the second terminal (the other of the source and the drain of the transistor 1213) of the switch 1203 is input to the circuit 1201 via the logic element 1206 and the circuit 1220 is shown, but the present invention is not limited to this. The signal output from the second terminal (the other of the source and the drain of the transistor 1213) of the switch 1203 may be input to the circuit 1201 without inverting its logical value. For example, the signal output from the second terminal (the other of the source and the drain of the transistor 1213) of the switch 1203 may be input to the circuit 1201 without inverting its logical value. For example, within the circuit 1201 may be input to the circuit 1201 without inverting its logical value. For example, within the circuit 1201 may be input to the circuit 1201 without inverting its logical value. For example, within the circuit 1201 may be input to the circuit 1201 without inverting its logical value. For example, within the circuit 1201 、When there is a node that holds a signal whose logic value is inverted from the signal input from the input terminal in the case, the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213 ) can be input to the node.

[0193] Also, in FIG. 15, among the transistors used in the memory element 1200, transistors other than the transistor 1209 can be transistors in which a channel is formed in a layer or substrate 11 90 made of a semiconductor other than an oxide semiconductor. For example, it can be a transistor in which a channel is formed in a silicon layer or a silicon substrate. Also, all the transistors used in the memory element 1200 can be transistors in which a channel is formed of an oxide semiconductor film . Or, the memory element 1200 may also include transistors in which a channel is formed of an oxide semiconductor film in addition to those other than the transistor 1209, and the remaining transistors can also be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor.

[0194] For the circuit 1201 in FIG. 15, for example, a flip - flop circuit can be used . Also, as the logic element 1206, for example, an inverter, a clocked inverter, etc. can be used .

[0195] In the semiconductor device according to one aspect of the present invention, when the power supply voltage is not supplied to the memory element 1200 , the data stored in the circuit 1201 can be held by the capacitor element 12 08 provided in the circuit 1202.

[0196] ​​​In addition, a transistor in which a channel is formed in an oxide semiconductor film has an extremely small off-current. . For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using such a transistor as transistor 1209, the signal held in capacitor element 1208 can be maintained for a long time even while no power supply voltage is supplied to memory element 1200. Thus, memory element 1200 can hold the stored content ( data) even when the supply of the power supply voltage is stopped.

[0197] In addition, by providing switch 1203 and switch 1204, since it is a memory element characterized by performing a precharge operation, after the resumption of the power supply voltage supply, the time until circuit 1201 retains the original data again can be shortened.

[0198] Also, in circuit 1202, the signal held by capacitor element 1208 is input to the gate of transistor 1210. Therefore, after the supply of the power supply voltage to memory element 1200 is resumed, the signal held by capacitor element 1208 can be converted into the state (on state or off state) of transistor 1210 and read out from circuit 1202. Therefore, even if the potential corresponding to the signal held in capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0199] By using such a memory element 1200 in a memory device such as a register or cache memory that a processor has, the loss of data in the memory device due to the stop of the power supply voltage supply can be prevented. It is possible. Also, after resuming the supply of the power voltage, it can return to the state before the power supply stop in a short time. Therefore, in the entire processor or one or more logic circuits constituting the processor, the power supply can be stopped even for a short time, so that the power consumption can be suppressed.

[0200] In this embodiment, the memory element 1200 has been described as an example used for the CPU. However, the memory element 1200 can also be applied to LSI such as DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), and RF (Radio Frequency) devices.

[0201] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0202] (Embodiment 6) In this embodiment, a configuration example of a display panel according to one aspect of the present invention will be described.

[0203] [Configuration Example] FIG. 19(A) is a top view of a display panel according to one aspect of the present invention, and FIG. 19(B) is a circuit diagram for explaining a pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one aspect of the present invention. Further, FIG. 19(C) is a circuit diagram for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel of a display panel according to one aspect of the present invention.

[0204] The transistor arranged in the pixel portion can be formed according to the above embodiment. Also, since it is easy to make the transistor an n-channel type, among the drive circuits, the n-channel​​​​ A part of the drive circuit that can be composed of n-channel transistors is formed on the same substrate as the transistors in the pixel portion. In this way, by using the transistors shown in the above embodiment in the pixel portion and the drive circuit, a highly reliable display device can be provided.

[0205] An example of a block diagram of an active matrix type display device is shown in FIG. 19(A). On the substrate 700 of the display device, there are a pixel portion 701, a first scanning line drive circuit 702, a second scanning line drive circuit 703, and a signal line drive circuit 704. A plurality of signal lines are arranged extending from the signal line drive circuit 704 in the pixel portion 701, and a plurality of scanning lines are arranged extending from the first scanning line drive circuit 702 and the second scanning line drive circuit 703. Note that pixels each having a display element are provided in a matrix in the intersection region of the scanning lines and the signal lines. Also, the substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0206] In FIG. 19(A), the first scanning line drive circuit 702, the second scanning line drive circuit 703, and the signal line drive circuit 704 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as a drive circuit provided outside is reduced, so that cost reduction can be achieved. Also, when a drive circuit is provided outside the substrate 700, it is necessary to extend the wiring, and the number of connections between the wirings increases. When the drive circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced, and the reliability or the yield can be improved.

[0207] [Liquid Crystal Panel] Further, an example of the circuit configuration of a pixel is shown in FIG. 19(B). Here, it shows a pixel circuit applicable to the pixels of a VA type liquid crystal display panel.

[0208] This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thus, the signals applied to the individual pixel electrode layers of the pixels designed with multi-domains can be controlled independently.

[0209] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be applied thereto. On the other hand, the source electrode layer or the drain electrode layer 714 that functions as a data line is commonly used by the transistor 716 and the transistor 717. The transistor 716 and the transistor 717 can appropriately use the transistors described in the above form. Thus, a highly reliable liquid crystal display panel can be provided.

[0210] The shape of the first pixel electrode layer electrically connected to the transistor 716 and the shape of the second pixel electrode layer electrically connected to the transistor 717 will be described. The shape of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a shape that spreads in a V shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0211] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 713. The gate wiring 712 and the gate wiring 71 ​ Apply three different gate signals to vary the operation timings of transistors 716 and 717, and the liquid crystal alignment can be controlled.

[0212] Also, a holding capacitor may be formed by a capacitance wiring 710, a gate insulating film that functions as a dielectric, and a capacitance electrode that is electrically connected to the first pixel electrode layer or the second pixel electrode layer.

[0213] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween.

[0214] Note that the pixel circuit shown in FIG. 19(B) is not limited thereto. For example, a new switch, resistor element, capacitor element, transistor, sensor, or logic circuit may be added to the pixel shown in FIG. 19(B).

[0215] 〔Organic EL panel〕 Another example of the circuit configuration of a pixel is shown in FIG. 19(C). Here, the pixel structure of a display panel using an organic EL element is shown.

[0216] In an organic EL element, when a voltage is applied to a light-emitting element, electrons are injected from one of a pair of electrodes and holes are injected from the other into a layer containing a light-emitting organic compound, and a current flows. Then when the electrons and holes recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0217] FIG. 19(C) is a diagram showing an example of an applicable pixel circuit. Here, an example of using two n-channel type transistors in one pixel is shown. Note that the metal oxide film of one aspect of the present invention can be used for the channel formation region of an n-channel type transistor. Further, the pixel circuit can apply digital time gradation driving.

[0218] The configuration of the applicable pixel circuit and the operation of the pixel when digital time gradation driving is applied will be described.

[0219] The pixel 720 has a switching transistor 721, a driving transistor 722, a light emitting element 724, and a capacitive element 723. The switching transistor 721 has a gate electrode layer connected to the scanning line 726, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 725, and a second electrode (the other of the source electrode layer and the drain electrode layer) connected to the gate electrode layer of the driving transistor 722. The driving transistor 722 has a gate electrode layer connected to the power supply line 727 via the capacitive element 723, a first electrode connected to the power supply line 727, and a second electrode connected to the first electrode (pixel electrode) of the light emitting element 724 . The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed on the same substrate.

[0220] The switching transistor 721 and the driving transistor 722 can appropriately use the transistors described in the above embodiment . Thereby, a highly reliable organic EL display panel can be provided.

[0221] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that The low power supply potential is a potential lower than the high power supply potential set on the power supply line 727. For example, GN D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the forward threshold voltage of the light-emitting element 724 is equal to or higher than the forward threshold voltage, and the potential difference is applied to the light-emitting element 72 4 to cause a current to flow through the light-emitting element 724 and emit light. Note that the forward voltage of the light-emitting element 7 24 refers to the voltage when a desired luminance is obtained, and includes at least the forward threshold voltage.

[0222] Note that the capacitor element 723 can be omitted by substituting for the gate capacitance of the driving transistor 722. Regarding the gate capacitance of the driving transistor 722, a capacitance may be formed between the channel formation region and the gate electrode layer. Next, the signal input to the driving transistor 722 will be described. In the case of the voltage input voltage driving

[0223] method, a video signal that causes the driving transistor 722 to be fully on or off is input to the driving transistor 722. Note that in order to operate the driving transistor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722. Also, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

[0224] When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light-emitting element 7

[0224] 24 is applied to the gate electrode layer of the driving transistor 722. ​Apply. Note that the video signal is input so that the driving transistor 722 operates in the saturation region. Then, a current is passed through the light-emitting element 724. Also, the driving transistor 722 is operated in the saturation region. In order to do so, the potential of the power supply line 727 is made higher than the gate potential of the driving transistor 722. By making the video signal analog, a current corresponding to the video signal can be passed through the light-emitting element 724, and analog gradation driving can be performed. Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 19(C). For example, a switch, a resistance element, a capacitance element, a sensor, a transistor, or a logic circuit may be added to the pixel circuit shown in FIG. 19(C).

[0225] When the transistors exemplified in the above-described embodiment are applied to the circuit exemplified in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. A configuration that can input the potentials exemplified above may be used. 9(C) may be used. Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0226] When the transistors exemplified in the above-described embodiment are applied to the circuit exemplified in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. A configuration that can input the potentials exemplified above may be used. When the transistors exemplified in the above-described embodiment are applied to the circuit exemplified in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. A configuration that can input the potentials exemplified above may be used. When the transistors exemplified in the above-described embodiment are applied to the circuit exemplified in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. A configuration that can input the potentials exemplified above may be used. When the transistors exemplified in the above-described embodiment are applied to the circuit exemplified in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. A configuration that can input the potentials exemplified above may be used. When the transistors exemplified in the above-described embodiment are applied to the circuit exemplified in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than the potential applied to the source electrode by a wiring (not shown) is input to the second gate electrode. A configuration that can input the potentials exemplified above may be used.

[0227] Note that this embodiment can be appropriately combined with other embodiments described in this specification. Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0228] (Embodiment 7) A semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, or an image reproduction device (typically, a device having a display capable of reproducing a recording medium such as a DVD: Digital Versatile Disc and displaying the image thereof). c and displaying the image thereof). It is possible. In addition, an electronic device that can use the semiconductor device according to one aspect of the present invention Examples include mobile phones, game machines including portable types, portable data terminals, e-books, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 16

[0229] . FIG. 16(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 90 8, etc. Note that the portable game machine shown in FIG. 16(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this .

[0230] FIG. 16(B) is a portable data terminal, which has a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 91 3 is provided on the first housing 911, and the second display unit 914 is provided on the second housing 912 . The first housing 911 and the second housing 912 are connected by a connection unit 915 , and the angle between the first housing 911 and the second housing 912 can be changed by the connection unit 915 . The video on the first display unit 913 may be configured to be switched according to the angle between the first housing 911 and the second housing 912 at the connection unit 915. In addition, the first display unit 913 and It is also possible to use a display device to which a function as a position input device is added to at least one of the call and the second display unit 914. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It may be used. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It can be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It can also be added.

[0231] FIG. 16(C) is a notebook personal computer and has a housing 921, a display unit 922, a keyboard 923, a pointing device 924, and the like. It has a housing 921, a display unit 922, a keyboard 923, a pointing device 924, and the like.

[0232] FIG. 16(D) is an electric refrigerator and has a housing 931, a refrigerator door 932, a freezer door 933, and the like. It has a housing 931, a refrigerator door 932, a freezer door 933, and the like.

[0233] FIG. 16(E) is a video camera and has a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946. It has a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946. The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946. The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946. The video on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946.

[0234] FIG. 16(F) is an ordinary automobile and has a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like. It has a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

[0235] In addition, this embodiment can be appropriately combined with other embodiments shown in this specification. It is.

[0236] (Embodiment 8) In this embodiment, a usage example of the RF device according to one aspect of the present invention will be described with reference to FIG. 17. Although the uses of RF devices are extensive, for example, banknotes, coins, securities types, bearer bonds, certificates (such as driver's licenses and resident cards, see FIG. 17(A)), recording media (D VDs, video tapes, etc., see FIG. 17(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 17 (C)), vehicles (such as bicycles, see FIG. 17(D)), personal items (bags, glasses, etc.), foods, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electrical electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), etc., or it can be provided and used on tags attached to each item (see FIGS. 17(E) and 17(F)). It can be done.

[0237] The RF device 4000 according to one aspect of the present invention is fixed to an article by being pasted or embedded on the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each article. The RF device 4000 according to one aspect of the present invention realizes small size, thin thickness, and light weight, so that the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the RF device 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and by utilizing this authentication function, forgery can be prevented. Also, for packaging containers, recording media, personal items, foods, clothing, daily necessities, or electronic devices ​​​​​By attaching an RF device according to one aspect of the present invention to a system such as an inspection system, In addition, the R according to one aspect of the present invention can be used for vehicles as well. By installing the F device, you can increase security against theft, etc. Cut.

[0238] As described above, the RF device according to one aspect of the present invention can be used for each of the applications described in this embodiment. By using this technology, the power consumption during operation, including writing and reading information, can be reduced, enabling maximum It is possible to extend the transmission distance. In addition, information can be transmitted even when the power is cut off. Since the data can be stored for a long period of time, it is also suitable for applications where the frequency of writing and reading is low. It is possible.

[0239] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do. EXAMPLES

[0240] In this embodiment, a transistor having a similar structure to that shown in FIG. A transistor was fabricated and its electrical characteristics were evaluated.

[0241] First, a method for preparing the example samples will be described.

[0242] A 900 nm thick TEOS (Tetra Elastomer) film was placed on the silicon transistor as an interlayer insulating film. Silicon oxide film made from ethyl ortho silicate is produced by CVD. More formed.

[0243] Next, the silicon oxide film was subjected to a CMP process to flatten the surface of the silicon oxide film. The conditions were as follows: a polyurethane-based polishing cloth was used as the CMP polishing pad, and NP8 was used as the slurry. Using the stock solution (silica particle size 60 nm to 80 nm) of 020 (manufactured by Nitto Haas Co., Ltd.) , the slurry temperature was set at room temperature, the polishing pressure was 0.08 MPa, and the spindle on the side where the substrate was fixed had a rotation speed of 51 rpm, and the table rotation speed where the polishing cloth was fixed was 50 rpm. It was processed for 1 .6 minutes.

[0244] Next, an opening reaching the electrode of the silicon transistor was formed in the silicon oxide film by etching . First, as the first etching, by the ICP (Inductiv ely Coupled Plasma: inductively coupled plasma) etching method, tri fluoromethane and helium (CHF3:He = 50 sccm:100 sccm) were mixed under an atmosphere, with a power supply power of 475 W, a bias power of 300 W, and a pressure of 5.5 Pa for 3 seconds etched. Next, as the second etching, by the ICP etching method, trifluorometh ane and helium (CHF3:He = 7.5 sccm:142.5 sccm) were mixed under an atmosphere, with a power supply power of 475 W, a bias power of 300 W, and a pressure of 5.5 Pa for 79 seconds etched . After etching again under the first etching conditions and then etching under the second etching conditions .

[0245] Next, a tungsten film with a film thickness of 150 nm serving as a relay wiring was formed by sputtering . The film formation conditions were as follows: using a tungsten target, under an argon (Ar = 80 sccm) atmosphere , a pressure of 0.8 Pa and a power supply power of 1 kW were applied, and the distance between the target and the substrate was 60 mm, and the film was formed with a substrate temperature of 230 °C.

[0246] Next, the tungsten film was etched to form a relay wiring. The etching conditions were IC By the P-etching method, in a mixed atmosphere of chlorine, carbon tetrafluoride and oxygen (Cl2:CF4:O2 = 45 s ccm:55 sccm:55 sccm), etching was performed for 5 seconds at a power supply power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa.

[0247] Next, a silicon oxide film made of TEOS with a film thickness of 500 nm serving as an interlayer insulating film was formed by the CVD method.

[0248] Next, the silicon oxide film was subjected to CMP treatment to expose the relay wiring. The treatment conditions were that a polyurethane-based polishing cloth was used as the CMP polishing pad, and the undiluted solution of NP8020 (manufactured by Nitta Haas Co., Ltd.) (silica particle size: 60 nm to 80 nm) was used as the slurry. The slurry temperature was set at room temperature, the polishing pressure was 0.08 MPa, the spindle rotation speed on the side where the substrate was fixed was 51 rpm, and the table rotation speed where the polishing cloth was fixed was 50 rpm. The treatment was performed for 1.4 minutes.

[0249] Next, a silicon oxide film made of TEOS with a film thickness of 100 nm serving as an interlayer insulating film, a silicon nitride film with a film thickness of 50 nm on the silicon oxide film, and a silicon oxide film with a film thickness of 300 nm on the silicon nitride film were formed by the CVD method.

[0250] Next, a first oxide semiconductor film with a film thickness of 20 nm and a second oxide semiconductor film with a film thickness of 15 nm were stacked and formed. The film formation conditions were that for the first oxide semiconductor film, sputtering using an oxide target with In:Ga:Zn = 1:3:2 (atomic ratio) was performed in a mixed atmosphere of argon and oxygen ( Ar:O2 = 30 sccm:15 sccm) at a pressure of 0.4 Pa and an electric ​​​​Apply a source power of 0.5 kW, set the distance between the target and the substrate to 60 mm, and the substrate temperature to 200 °C to form a film. The second oxide semiconductor film is an oxide with an atomic ratio of In:Ga:Zn = 1:1:1 using a sputtering method with an argon and oxygen (Ar:O2 = 30 sccm:15 sccm) mixed atmosphere, at a pressure of 0.4 Pa and a power supply power of 0.5 kW applied, with the distance between the target and the substrate set to 60 mm and the substrate temperature set to 300 °C to form a film. Note that the first oxide semiconductor film and the second oxide semiconductor film were continuously formed without exposure to the atmosphere. This was carried out.

[0251] Subsequently, a heat treatment was performed. The heat treatment was carried out at 450 °C for 1 hour in a nitrogen atmosphere, and then at 450 °C for 1 hour in an oxygen atmosphere. This was carried out.

[0252] Next, the first oxide semiconductor film and the second oxide semiconductor film were etched by the ICP etching method in a mixed atmosphere of boron trichloride and chlorine (BCl3:Cl2 = 60 sccm:20 sccm), at a power supply power of 450 W, a bias power of 100 W, and a pressure of 1.9 Pa for 89 seconds to etch and process into island-shaped first and second oxide semiconductor films. Also simultaneously, island-shaped first and second blocking films were formed from the first and second oxide semiconductor films. This was carried out.

[0253] Next, an opening reaching the intermediate wiring was formed by etching in a silicon oxide film made from TEOS with a film thickness of 100 nm, a silicon nitride film with a film thickness of 50 nm on the silicon oxide film, and a silicon oxide film with a film thickness of 300 nm on the silicon nitride film. The etching conditions were first, as the first etching using the ICP etching method, with trifluoromethane and helium (CHF3 and helium (CHF3 and helium (CHF3​ : Under a mixed atmosphere of He = 50 sccm:100 sccm, with a power supply power of 475 W and a bias power of 300 W, etching was performed for 3 seconds at a pressure of 5.5 Pa. Next, as the second etching, by the ICP etching method, in a mixed atmosphere of trifluoromethane and helium (CHF3:He = 7. 5 sccm:142.5 sccm), with a power supply power of 475 W and a bias power of 30 0 W, etching was performed for 69 seconds at a pressure of 5.5 Pa. After etching again under the first etching conditions, etching was performed under the second etching conditions.

[0254] Next, a tungsten film serving as the source electrode and the drain electrode was formed to a film thickness of 100 nm. The film formation conditions were as follows: by sputtering using a tungsten target, in an argon (Ar = 80 sccm) atmosphere, at a pressure of 0.8 Pa and a power supply power (power supply output) of 1.0 kW was applied, and film formation was carried out under the conditions of a distance of 60 mm between the substrate and the target and a substrate temperature of 230 °C. The film was formed.

[0255] Next, a resist mask was formed on the tungsten film and etching was performed. The etching was carried out by the ICP etching method, in a mixed atmosphere of carbon tetrafluoride, chlorine, and oxygen (CF4:Cl2:O2 = 55 sccm:45 sccm:55 sccm), with a power supply power of 3000 W and a bias power of 110 W, and the first etching was performed for 13 seconds at a pressure of 0.67 Pa. Then, in an oxygen (O2 = 100 sccm) atmosphere, with a power supply power of 2000 W and a bias power of 0 W, and a pressure of 3.0 Pa, the second etching was performed for 15 seconds. Further, after that, carbon tetrafluoride, chlorine, and oxygen (CF4:Cl2:O2 = 55 sccm:45 sccm:55 sccm) mixed atmosphere Under reduced pressure, at a power supply power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa, the third etching was performed for 14 seconds to form source and drain electrodes.

[0256] Next, a third oxide semiconductor film with a thickness of 5 nm was formed on the second oxide semiconductor film, the source electrode, and the drain electrode. The film formation conditions were as follows: sputtering method using an oxide target with In:Ga:Zn = 1:3:2 (atomic ratio) in an argon and oxygen (Ar:O2 = 30 sccm:15 sccm) mixed atmosphere, at a pressure of 0.4 Pa and a power supply power of 0.5 kW, with a distance of 60 mm between the target and the substrate and a substrate temperature of 200 °C.

[0257] Next, a 20-nm silicon oxynitride film to be a gate insulating film was formed by CVD method in a mixed atmosphere of silane and nitrous oxide (SiH4:N2O = 1 sccm:800 sccm), at a pressure of 200 Pa and a power supply power of 150 kW, with a distance of 28 mm between the target and the substrate and a substrate temperature of 350 °C.

[0258] Next, a titanium nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm were formed by sputtering method. The film formation conditions for the titanium nitride film were as follows: in a nitrogen (N2 = 50 sccm) atmosphere, at a pressure of 0.2 Pa and a power supply power of 12 kW, with a distance of 400 mm between the target and the substrate and a substrate temperature of 25 °C. The film formation conditions for the tungsten film were as follows: in an argon (Ar = 100 sccm) atmosphere, at a pressure of 2.0 Pa and a power supply power of 4 kW, with a distance of 60 mm between the target and the substrate and a substrate temperature of 230 °C.

[0259] Next, by ICP etching method, a titanium nitride film with a thickness of 30 nm and a film with a thickness of 135 nm​​​​​​​​​​​​​ The tungsten film stack was etched. The etching conditions were in a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm), with a power supply power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa for the first etching operation. After the first etching, in a mixed atmosphere of chlorine and boron trichloride (Cl2:BCl3 = 5 0 sccm:150 sccm), with a power supply power of 1000 W, a bias power of 50 W and a pressure of 0.67 Pa, the second etching was performed to form the gate electrode.

[0260] Next, using the gate electrode as a mask, the gate insulating film and the third oxide semiconductor film stack were etched. The etching conditions were in an atmosphere of boron trichloride (BCl3 = 80 sccm), with a power supply power of 450 W, a bias power of 100 W, and a pressure of 1.0 Pa for the etching operation.

[0261] Next, an aluminum oxide film with a thickness of 150 nm was formed on the gate electrode by sputtering. The film formation conditions were in a mixed atmosphere of argon:oxygen (Ar:O2 = 25 sccm:25 sccm), with a pressure of 0.4 Pa and a power supply power of 2.5 kW applied, and the distance between the target and the substrate was 60 mm, and the substrate temperature was 250 °C.

[0262] Through the above processes, a transistor of an example with a channel length of 0.8 μm and a channel width of 10 μm was fabricated. Also, as a comparative example, a transistor having a configuration without only the first blocking film and the second blocking film of the above transistor was fabricated.

[0263] Next, in the two types of transistors fabricated, the drain voltage (V d :[V]) was 0.1 Set it to V or 2.7V, and when sweeping the gate voltage (V g :[V]) from -3V to 3V, the drain current (I d :[A]) was measured. The measurement results are shown in Fig. 18. In Fig. 18, the solid line is the measurement result when the drain voltage (V d :[V]) is 0.1V, and the dotted line is the measurement result when the drain voltage (V d :[V]) is 2.7V. The horizontal axis is the gate voltage ( V g :[V]), and the vertical axis is the drain current (I d :[A]). Note that the "drain voltage ( V d :[V])" is the potential difference between the drain and the source with the source as the reference, and the "gate voltage (V g :[V])" is the potential difference between the gate and the source with the source as the reference. Also, Fig. 18(A) shows the measurement results of the transistor of the comparative example, and Fig. 18(B) shows the measurement results of the transistor of the example.

[0264] It was confirmed that the variation in characteristics was large in Fig. 18(A). On the other hand, it was confirmed that the variation in characteristics was small in Fig. 18(B). It was suggested that by providing the blocking film, the variation in characteristics could be reduced.

Explanation of Reference Signs

[0265] 100 Substrate 102 Underlying insulating film 104a Conductive film 104b Conductive film 104c Conductive film 105 Interlayer insulating film 106 Interlayer insulating film 108a Oxide semiconductor film 108a1 Oxide semiconductor film 108a2 Oxide semiconductor film​​ 108a3 Oxide semiconductor film 108b Blocking film 108b1 Blocking film 108b2 Blocking film 108c Blocking film 108c1 Blocking film 108c2 Blocking film 110a Source electrode 110b Drain electrode 112 Gate insulating film 114 Gate electrode 116 Oxide insulating film 118a Conductive film 118b Conductive film 120a Opening 120b Opening 128 Channel protection film 150 Transistor 250 Transistor 700 Substrate 701 Pixel section 702 Scanning line drive circuit 703 Scanning line drive circuit 704 Signal line drive circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Driving transistor 723 Capacitance element 724 Light-emitting element 725 Signal line 726 Scanning line 727 Power supply line 728 Common electrode 800 RF tag 801 Communicator 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Memory circuit 811 ROM 901 Housing 902 Housing 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 First housing 912 Second housing 913 Display unit 914 Display unit 915 Connection part 916 Operation key 921 Housing 922 Display unit 923 Keyboard 924 Pointing device 931 Housing 932 Refrigerator door 933 Freezer door 941 First housing 942 Second housing 943 Display unit 944 Operation key 945 Lens 946 Connection part 951 Vehicle body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface 1190 Substrate 1191 ALU 1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 Memory Element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive Element 1208 Capacitive Element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 2201 Insulating Film 2202 Wiring 2203 Plug 2204 Insulating Film 2205 Wiring 2206 Wiring 2207 Insulating Film 2208 Insulating Film 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitive Element 4000 RF Device

Claims

1. a first insulating film; a first conductive film having a region in contact with the upper surface of the first insulating film and functioning as a source electrode; a second conductive film having a region in contact with the upper surface of the first insulating film and functioning as a drain electrode; a first oxide semiconductor film having a region in contact with the upper surface of the first insulating film, a region in contact with the upper surface of the first conductive film, and a region in contact with the upper surface of the first conductive film, and having a channel formation region; a second oxide semiconductor film having a region in contact with the upper surface of the first conductive film; a second insulating film having a region in contact with the upper surface of the first conductive film, a region in contact with the upper surface of the second conductive film, a region in contact with the upper surface of the first oxide semiconductor film, and a region in contact with the upper surface of the second oxide semiconductor film; a third conductive film having a region in contact with the upper surface of the second insulating film and a region in contact with the upper surface of the first conductive film through an opening provided in the second insulating film; a fourth conductive film having a region in contact with the upper surface of the second insulating film and functioning as a gate electrode; wherein the second oxide semiconductor film has a lower resistance than the first oxide semiconductor film; wherein the distance between the second oxide semiconductor film and the first oxide semiconductor film is shorter than the distance between the opening and the first oxide semiconductor film; a semiconductor device in which, in a plan view, the second oxide semiconductor film intersects the first conductive film.

2. a first insulating film; a first conductive film having a region in contact with the upper surface of the first insulating film and functioning as a source electrode; a second conductive film having a region in contact with the upper surface of the first insulating film and functioning as a drain electrode; a first oxide semiconductor film having a region in contact with the upper surface of the first insulating film, a region in contact with the upper surface of the first conductive film, and a region in contact with the upper surface of the second conductive film, and having a channel formation region; a second oxide semiconductor film having a region in contact with the upper surface of the first conductive film; a third oxide semiconductor film having a region in contact with the upper surface of the second conductive film; a second insulating film having a region in contact with the upper surface of the first conductive film, a region in contact with the upper surface of the second conductive film, a region in contact with the upper surface of the first oxide semiconductor film, a region in contact with the upper surface of the second oxide semiconductor film, and a region in contact with the upper surface of the third oxide semiconductor film; A third conductive film having a region in contact with the upper surface of the second insulating film and a region in contact with the upper surface of the first conductive film through a first opening provided in the second insulating film; A fourth conductive film having a region in contact with the upper surface of the second insulating film and a region in contact with the upper surface of the second conductive film through a second opening provided in the second insulating film; A fifth conductive film having a region in contact with the upper surface of the second insulating film and having a function as a gate electrode; and The second oxide semiconductor film has a lower resistance than the first oxide semiconductor film; The third oxide semiconductor film has a lower resistance than the first oxide semiconductor film; The distance between the second oxide semiconductor film and the first oxide semiconductor film is shorter than the distance between the first opening and the first oxide semiconductor film; The distance between the third oxide semiconductor film and the first oxide semiconductor film is shorter than the distance between the second opening and the first oxide semiconductor film; In plan view, the second oxide semiconductor film intersects the first conductive film; In plan view, the third oxide semiconductor film intersects the second conductive film, a semiconductor device.

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