Semiconductor device

Abstract

To improve the reliability of a transistor with an oxide semiconductor by suppressing the variation in electric characteristics.SOLUTION: A semiconductor device includes a transistor. The transistor includes a first oxide semiconductor film on a first insulating film, a gate insulating film on the first oxide semiconductor film, a second oxide semiconductor film on the gate insulating film, and a second insulating film on the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region overlapping with the second oxide semiconductor film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The channel region includes a first layer and a second layer in contact with an upper surface of the first layer and covering a side surface of the first layer in a channel width direction. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device having an oxide semiconductor film and a display device having the semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor devices include semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including thin-film solar cells, organic thin-film solar cells, etc.), and an electronic device may have a semiconductor device.

Background Art

[0004] Techniques for forming a transistor (also referred to as a field-effect transistor (FET) or a thin-film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). As a semiconductor thin film applicable to a transistor, semiconductor materials typified by silicon are widely known, but oxide semiconductors are attracting attention as other materials. ​​​​​​​​​​​​is aimed at.

[0005] For example, as the oxide semiconductor, an amorphous oxide containing In, Zn, Ga, Sn, etc. is used to fabricate a transistor (see Patent Document 1). Also, a technique for fabricating a transistor of an oxide thin film having a self-aligned top gate structure is disclosed (see Patent Document 2).

[0006] In addition, a semiconductor device is disclosed in which an insulating layer that releases oxygen by heating is used for the underlying insulating layer of the oxide semiconductor layer that forms the channel, and the oxygen deficiency of the oxide semiconductor layer is reduced (see Patent Document 3).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0008] As a transistor having an oxide semiconductor film, for example, an inverted staggered type (also referred to as a bottom gate structure) or a staggered type (also referred to as a top gate structure) can be mentioned. When applying a transistor having an oxide semiconductor film to a display device, the inverted staggered type transistor is more used in many cases because the manufacturing process is relatively simple and the manufacturing cost can be suppressed compared to the staggered type transistor. However, with the increase in the size of the screen of the display device or the display device High definition of image quality (for example, high definition display devices represented by 4K×2K (number of horizontal pixels = 3840 pixels, number of vertical pixels = 2160 pixels) or 8K×4K (number of horizontal pixels = 7680 pixels, number of vertical pixels = 4320 pixels)) is progressing. In the case of an inverted staggered transistor, since there is a parasitic capacitance between the gate electrode and the source and drain electrodes, the parasitic capacitance causes problems such as a large signal delay and deterioration of the image quality of the display device. Therefore, for a staggered transistor having an oxide semiconductor film, the development of a structure having stable semiconductor characteristics and high reliability is desired.

[0009] In addition, when manufacturing a transistor using an oxide semiconductor film in the channel region, oxygen deficiency formed in the channel region of the oxide semiconductor film affects the transistor characteristics and thus becomes a problem. For example, when oxygen deficiency is formed in the channel region of the oxide semiconductor film, carriers are generated due to the oxygen deficiency. When carriers are generated in the channel region of the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film in the channel region occur, typically a shift in the threshold voltage. In addition, there is a problem that the electrical characteristics vary from transistor to transistor . Therefore, in the channel region of the oxide semiconductor film, it is preferable that the oxygen deficiency is less. On the other hand, in a transistor using an oxide semiconductor film in the channel region , as the oxide semiconductor film in contact with the source and drain electrodes, it is preferable that there is a large amount of oxygen deficiency and the resistance is low in order to reduce the contact resistance with the source and drain electrodes. In view of the above problems, one aspect of the present invention is a transistor having an oxide semiconductor, in which the electrical

[0010] One of the problems is to improve reliability by suppressing variations in air characteristics. Or, One of the problems of one aspect of the present invention is to provide a staggered transistor having an oxide semiconductor. Or, one aspect of the present invention is to provide a transistor having a large on-current and having an oxide semiconductor. Or, one aspect of the present invention is to provide a transistor having a small off-current and having an oxide semiconductor. Or, one aspect of the present invention is to provide a semiconductor device with reduced power consumption. Or, one aspect of the present invention is to provide a novel semiconductor device. Note that the description of the above problems does not prevent the existence of other problems. Note that one

[0011] aspect of the present invention does not necessarily need to solve all of these problems. Other problems will be apparent from the description in the specification and the like, and it is possible to extract other problems than the above from the description in the specification and the like.

Means for Solving the Problems

[0012] One aspect of the present invention is a semiconductor device having a transistor, wherein the transistor has a first oxide semiconductor film on a first insulating film, a gate insulating film on the first oxide semiconductor film, a second oxide semiconductor film on the gate insulating film, a second insulating film on the first oxide semiconductor film and the second oxide semiconductor film, the first oxide semiconductor film has a channel region that overlaps with the second oxide semiconductor film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film, the channel region has a first layer and a second layer that contacts the upper surface of the first layer and covers the side surfaces in the channel width direction of the first layer, and the second oxide semiconductor film has a first acid This semiconductor device has a higher carrier density than a nitride semiconductor film.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor. The gate insulating film includes a first oxide semiconductor film on the first insulating film and a gate insulating film on the first oxide semiconductor film. a second oxide semiconductor film on the gate insulating film; a first oxide semiconductor film and a second oxide semiconductor film on the gate insulating film; and a second insulating film on the first oxide semiconductor film, the first oxide semiconductor film being a second oxide semiconductor film. a channel region overlapping the first insulating film, a source region in contact with the second insulating film, and a second insulating film in contact with the second insulating film. a drain region in contact with the first layer, and a channel region in contact with an upper surface of the first layer; A second layer covers the side surface of the first layer in the channel width direction, and a third layer contacts the bottom surface of the first layer. the second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film. It is a semiconductor device.

[0014] Another embodiment of the present invention is a semiconductor device including a transistor. The gate insulating film includes a first oxide semiconductor film on the first insulating film and a gate insulating film on the first oxide semiconductor film. a gate insulating film, a second oxide semiconductor film over the gate insulating film, and a conductive film over the second oxide semiconductor film; a first oxide semiconductor film and a second insulating film over the conductive film; a channel region overlapping with the second oxide semiconductor film and a source region in contact with the second insulating film and a drain region in contact with the second insulating film, and the channel region is formed of the first layer and the first a second layer in contact with the upper surface of the first layer and covering the side surface of the first layer in the channel width direction; The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film. do.

[0015] Another aspect of the present invention is a semiconductor device having a transistor, where the transist or has a first oxide semiconductor film on a first insulating film, a gate insulating film on the first oxide semiconductor film, a second oxide semiconductor film on the gate insulating film, a conductive film on the second oxide semiconductor film, a first insulating film on the first oxide semiconductor film and the conductive film, and the first oxide semiconductor film has a channel region that overlaps with the second oxide semiconductor film, a source region that contacts the second insulating film, and a drain region that contacts the second insulating film. The channel region has a first layer, a second layer that contacts the upper surface of the first layer and covers the side surfaces of the first layer in the channel width direction, and a third layer that contacts the lower surface of the first layer. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film, and it is a semiconductor device.

[0016] Also, in the above aspect, the upper end portion of the gate insulating film preferably has a region that aligns with the lower end portion of the second oxide semiconductor film or a region that is located outside the lower end portion of the second oxide semiconductor film.

[0017] Also, in the above aspect, the second insulating film preferably contains either nitrogen or hydrogen or both.

[0018] Also, in the above aspect, the transistor preferably further has a third insulating film on the second insulating film and a source electrode that connects to the source region through openings provided in the second insulating film and the third insulating film, and a drain electrode that connects to the drain region through openings provided in the second insulating film and the third insulating film.

[0019] Also, in the above aspect, the source region and the drain region are in contact with the second oxide semiconductor film and water It is preferable to have regions with the same element concentration. Further, in the above aspect, the source region and the drain region preferably contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, or noble gases.

[0020] Further, in the above aspect, either one or both of the first oxide semiconductor film and the second oxide semiconductor film preferably contain oxygen, In, Zn, and M (where M is Al, Ga, Y, or Sn). Further, in the above aspect, either one or both of the first oxide semiconductor film and the second oxide semiconductor film have a crystal part, and the crystal part preferably has c-axis orientation.

[0021] Another aspect of the present invention is a display device having the semiconductor device and display elements described in any one of the above aspects. Another aspect of the present invention is a display module having the display device and a touch sensor. Another aspect of the present invention is an electronic device having the semiconductor device, the display device, or the display module described in any one of the above aspects, and an operation key or a battery.

Advantages of the Invention

[0022] According to one aspect of the present invention, in a transistor having an oxide semiconductor, the reliability can be improved by suppressing fluctuations in electrical characteristics. Or, according to one aspect of the present invention, a staggered transistor having an oxide semiconductor can be provided. Or, according to one aspect of the present invention, a transistor having a large on-current and having an oxide semiconductor can be provided. Or, according to one aspect of the present invention, a transistor having a small off-current and having an oxide semiconductor can be provided. ​​​​​​​​​A register can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0026] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic illustrations of ideal examples and are not limited to the shapes or values shown in the drawings.

[0027] Also, the ordinal numbers "first", "second", "third", etc. used in this specification are added to avoid confusion of components, and it should be noted that they do not numerically limit.

[0028] Also, in this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0029] Also, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And the drain (drain terminal, drain between a drain (drain terminal, drain region or drain electrode) and a source (source terminal, source region or source electrode) has a channel region, and can conduct current through the drain, the channel region, and the source In this specification and the like, the channel region refers to the region through which current mainly flows flows

[0030] In addition, the functions of the source and drain may be interchanged when transistors with different polarities are adopted or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably In addition, in this specification and the like, "electrically connected" includes cases where they are connected through "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included

[0031] In this specification and the like, the term "membrane" and the term "layer" can be used interchangeably In addition, in this specification and the like, "electrically connected" includes cases where they are connected through "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included

[0032] In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included In addition, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included

[0033] In addition, in this specification and the like, the term "membrane" and the term "layer" can be used interchangeably It is possible to replace. For example, the term "conductive layer" may be changed to the term "conductive film". Alternatively, for example, the term "insulating film" may be changed to the term "insulating layer". There may be cases where it is possible.

[0034] Also, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as a non-conducting state or a cut-off state). The off state refers to, unless otherwise specified, in an n-channel transistor, a state where the voltage V gs between the gate and the source is lower than the threshold voltage Vth, and in a p-channel transistor, a state where the voltage Vgs between the gate and the so urce is higher than the threshold voltage Vth. For example, the off-current of an n-channel type transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vt h.

[0035] The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off state at a predetermined Vgs, the off state at Vgs within a predetermined range, or the off state at Vgs where a sufficiently reduced off-current is obtained, etc.

[0036] As an example, the threshold voltage Vth is 0.5 V, the drain current at Vgs = 0.5 V is 1×10 A, the drain current at Vgs = 0.1 V is 1×10 -9 A, and the drain current at Vgs = -0.5 V is 1×10 -1 3 A.-19 is A and Vg the drain current at Vgs = -0.8V is 1×10 -22 A for an n-channel type transistor. The drain current of the transistor is at Vgs = -0.5V or, in the range of Vgs from -0.5V to -0.8V, 1×10 A or less. Therefore, the off-current of the transistor may be said to be 1×10 -19 A or less. There may be a case where the drain current of the transistor is 1×10 A or less, so the off-current of the transistor may be said to be 1×10 -19 A or less. Since there exists a Vgs at which the drain current of the transistor becomes 1×10 A or less, the off-current of the transistor may be said to be 1×10 -22 A or less. A or less. -22 There may be a case where the off-current of the transistor is 1×10

[0037] Also, in this specification and the like, the off-current of a transistor having a channel width W may be expressed by the current value flowing per channel width W. Also, it may be expressed by the current value flowing through a predetermined channel width (for example, 1μm). In the latter case, the unit of the off-current may be expressed in a unit having a unit of current / length (for example, A / μm). The off-current of a transistor may depend on temperature. In this specification, unless otherwise specified, the off-current

[0038] may represent the off-current at room temperature, 60°C, 85°C, 95°C, or 125°C. Or, it may represent the off-current at the temperature at which the reliability of the semiconductor device including the transistor is ensured, or the temperature at which the semiconductor device including the transistor is used (for example any one temperature in the range of 5°C to 35°C). When it is said that the off-current of a transistor is I or less, it means at room temperature, 60°C, 85°C, 95°C, 125°C ​​​​There may be a case where there exists a value of Vgs such that the off-current of the transistor becomes I or less at a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or at a temperature (for example, any one of 5°C to 35°C) at which the semiconductor device including the transistor is used. The off-current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-current may represent the off-current at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or

[0039] 20V. Or it may represent the off-current at Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or the off-current at Vds used in the semiconductor device including the transistor. When it is said that the off-current of the transistor is I or less, it may mean that there exists a value of Vgs such that the off-current of the transistor becomes I or less at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or Vds used in the semiconductor device including the transistor. In the description of the off-current above, the drain and the source may be read as interchanged. That is, the off-current may also refer to the current flowing through the source when the transistor is in the off state. Also, in this specification etc., the leakage current may be described in the same meaning as the off-current.

[0040]

[0041] ​​​​​​​​​In this specification and the like, the off-current refers to, for example, the current flowing between the source and the drain when the transistor is in the off state. In some cases, it may refer to the current flowing between the source and the drain.

[0042] In this specification and the like, the impurities in a semiconductor refer to components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are included, DOS (Density of States) may be formed in the semiconductor, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor has an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen etc. In the case of an oxide semiconductor, for example, oxygen vacancies may be formed due to the incorporation of impurities such as hydrogen. When the semiconductor has silicon, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements other than oxygen and hydrogen, etc. In the case of an oxide semiconductor, for example, oxygen vacancies may be formed due to the incorporation of impurities such as hydrogen. When the semiconductor has silicon, examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen, etc. 15 elements, etc.

[0043] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 22. An example of a semiconductor device having a transistor is shown in FIGS. 1(A), (B), and (C). Note that the transistor shown in FIGS. 1(A), (B), and (C) has a top gate structure.

[0044] <1-1. Configuration Example 1 of Semiconductor Device> An example of a semiconductor device having a transistor is shown in FIGS. 1(A), (B), and (C). Note that the transistor shown in FIGS. 1(A), (B), and (C) has a top gate structure. The transistor shown in FIGS. 1(A), (B), and (C) has a top gate structure.

[0045] FIG. 1(A) is a top view of the transistor 100, and FIG. 1(B) is a cross-sectional view taken along the dash-dot line X1-X2 in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along the dash-dot line Y1-Y2 in FIG. 1(A). In FIG. 1(A), for clarity, components such as the insulating film 110 are omitted from the illustration. In the top view of the transistor, as in FIG. 1(A) in subsequent drawings, a part of the components may be omitted from the illustration. Also, the dash-dot line X1-X 2 direction is sometimes referred to as the channel length (L) direction, and the dash-dot line Y1-Y2 direction is sometimes referred to as the channel width (W) direction.

[0046] The transistor 100 shown in FIGS. 1(A), 1(B), and 1(C) includes an insulating film 104 formed on the substrate 102, an oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, an oxide semiconductor film 112 on the insulating film 110, and an insulating film 116 on the insulating film 104, the oxide semiconductor film 108, and the oxide semiconductor film 112. Also, the oxide semiconductor film 108 has a channel region 108i that overlaps the oxide semiconductor film 112, a source region 108s that contacts the insulating film 116, and a drain region 108d that contacts the insulating film 116. The channel region 108i has a layer 108_2 and a layer 108_3 that contacts the upper surface of the layer 108_2 and covers the side surfaces of the layer 108_ 2 in the channel width direction.

[0047] The transistor 100 may also include an insulating film 118 on the insulating film 116, and a conductive film 120a that is electrically connected to the source region 108s through an opening 141a provided in the insulating films 116 and 11 8, and a conductive film 120b that is electrically connected to the drain region 108d through an opening 141b provided in the insulating films 116 and 118.​

[0048] In the present specification and the like, the insulating film 104 may be referred to as the first insulating film, the insulating film 116 may be referred to as the second insulating film, and the insulating film 118 may be referred to as the third insulating film. Further, the insulating film 110 has a function as a gate insulating film, and the oxide semiconductor film 112 has a function as a gate electrode. Also, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode. In the case where the insulating film 110 is referred to as the first insulating film, the insulating film 116 is referred to as the second insulating film, and the insulating film 118 is referred to as the third insulating film. Further, the insulating film 110 has a function as a gate insulating film, and the oxide semiconductor film 112 has a function as a gate electrode. Also, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode. In the case where the insulating film 110 is referred to as the first insulating film, the insulating film 116 is referred to as the second insulating film, and the insulating film 118 is referred to as the third insulating film. Further, the insulating film 110 has a function as a gate insulating film, and the oxide semiconductor film 112 has a function as a gate electrode. Also, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode. In the case where the insulating film 110 is referred to as the first insulating film, the insulating film 116 is referred to as the second insulating film, and the insulating film 118 is referred to as the third insulating film. Further, the insulating film 110 has a function as a gate insulating film, and the oxide semiconductor film 112 has a function as a gate electrode. Also, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode. In the case where the insulating film 110 is referred to as the first insulating film, the insulating film 116 is referred to as the second insulating film, and the insulating film 118 is referred to as the third insulating film. Further, the insulating film 110 has a function as a gate insulating film, and the oxide semiconductor film 112 has a function as a gate electrode. Also, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode.

[0049] In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed. In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed. In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed. In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed. In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed. In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed. In the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is activated and is likely to become a low-resistance (n-type) region. Also, when the side surface or the vicinity of the side surface in the channel width (W) direction of the channel region 108i is an n-type region, since the n-type region serves as a carrier path, a parasitic channel may be formed.

[0050] Therefore, in the semiconductor device according to one aspect of the present invention, the channel region 108i has a stacked structure, and the side surface in the channel width (W) direction of one layer of the stacked structure is covered with the other layer. By adopting such a configuration, it is possible to reduce defects or the adhesion of impurities in the side surface or the vicinity of the side surface of the channel region 108i. By adopting such a configuration, it is possible to reduce defects or the adhesion of impurities in the side surface or the vicinity of the side surface of the channel region 108i. By adopting such a configuration, it is possible to reduce defects or the adhesion of impurities in the side surface or the vicinity of the side surface of the channel region 108i.

[0051] In FIGS. 1(B) and 1(C), the stacked structure of the channel region 108i is the layer 108_. Although a two-layer structure with layer 2 and layer 108_3 is used, it is not limited to this. For example, a stacked structure as shown in FIGS. 2(A) and (B ) may be used.

[0052] FIGS. 2(A) and (B) are cross-sectional views of the transistor 100A. Since the top view of the transistor 100A is the same as that of the transistor 100 shown in FIG. 1(A), FIG. 1(A) is incorporated for explanation. FIG. 2(A) is a cross-sectional view between the dashed-dotted line X1-X2 in FIG. 1(A), and FIG. 2(B) is a cross-sectional view between the dashed-dotted line Y1-Y2 in FIG. 1(A).

[0053] The oxide semiconductor film 108 included in the transistor 100A has a channel region 108i that overlaps with the oxide semiconductor film 112, a source region 108s that contacts the insulating film 116, and a drain region 108d that contacts the insulating film 11 6. Further, the channel region 108i has a layer 108_3 that contacts the upper surface of the layer 108_2 and covers the side surface in the channel width direction of the layer 108_2, and a layer 108_1 that contacts the lower surface of the layer 108_2.

[0054] As described above, the transistor 100A has a different configuration of the oxide semiconductor film 108 included in the transistor 100 shown above. For other configurations, the transistor 100 has the same configuration and exhibits the same effects.

[0055] The layer 108_1, the layer 108_2, and the layer 108_3 in the oxide semiconductor film 108 have at least one identical element. Therefore, interface scattering hardly occurs at the interface between the layer 108_1 and the layer 108_2 or at the interface between the layer 108_2 and the layer 108_3. Accordingly, since the movement of carriers is not inhibited at the interface, the transistors 100 and the transistor The field-effect mobility (sometimes simply referred to as mobility or μFE) of the STA 100A increases. It becomes.

[0056] Layers 108_1, 108_2, and 108_3 each have a metal oxide, and it is preferable that the metal oxide has at least indium (In) or zinc (Zn). When the oxide semiconductor film has In, for example, the carrier mobility (electron mobility) increases.

[0057] When the oxide semiconductor film has Zn, crystallization of the oxide semiconductor film is likely to occur. Moreover, when the oxide semiconductor film has an element M having a function as a stabilizer, for example, the energy gap (Eg) of the oxide semiconductor film becomes large. The oxide semiconductor film suitable for one aspect of the present invention has an energy gap of 2 eV or more, preferably 2.5 eV or more,

[0058] more preferably 3 eV or more. Thus, by using a metal oxide having a large energy gap for the oxide semiconductor film 108, the off-current of the transistors 100 and 100A can be reduced. Note that the element M is an element having a high binding energy with oxygen, and the binding energy with oxygen is higher than that of In. As the oxide semiconductor film suitable for the semiconductor device of one aspect of the present invention, typically, In-Zn oxide, In-M oxide, In-M-Zn oxide can be used. Among them, it is preferable to use In-M-Zn oxide (M represents aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)). In particular, it is preferable to use In-Ga-Zn oxide (hereinafter sometimes referred to as IGZO) with M being Ga.

[0059]

[0060] ​​​​​​​​​ When layer 108_2 has an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and oxygen is preferably such that In is greater than 25 atomic% and M is less than 75 atomic%. More preferably, In is greater than 34 atomic% and M is less than 66 atomic%. In particular, layer 108_2 preferably has a region where the atomic ratio of In is equal to or greater than the atomic ratio of M.

[0061] Also, by having a region where the atomic ratio of In is equal to or greater than the atomic ratio of M in layer 108_2, the field-effect mobility of the transistor can be increased. Specifically, the field-effect mobility of transistor 100, 100A can exceed 10 cm / Vs, and more preferably, the field-effect mobility of transistor 100, 100A can exceed 30 cm 2 / Vs. 2

[0062] For example, a transistor with a high field-effect mobility can have a smaller channel width. Therefore, by using such a transistor in a scanning line driving circuit (also referred to as a gate driver) that generates a gate signal, or in a demultiplexer connected to the output terminal of a shift register included in the scanning line driving circuit, the size of the scanning line driving circuit can be reduced, and a semiconductor device or a display device with a narrow frame width (also referred to as a narrow bezel) can be provided. Alternatively, since the gate voltage can be reduced, the power consumption of the display device can be reduced.

[0063] Also, by increasing the field-effect mobility of the transistor, the display device can be made high-definition. It is possible. For example, it can be suitably used as a transistor in a pixel circuit or a drive circuit of a high-definition display device represented by 4K×2K (number of horizontal pixels = 3840 pixels, number of vertical pixels = 216 0 pixels) or 8K×4K (number of horizontal pixels = 7680 pixels, number of vertical pixels = 4320 pixels). On the other hand, when the layer 108_2 has a region where the atomic ratio of In is equal to or more than the atomic ratio of M

[0064] , since the energy gap (Eg) becomes small, the electrical characteristics of the transistor are likely to vary during light irradiation. However, in the semiconductor device according to one aspect of the present invention, a layer 108_ 3 is formed on the layer 108_2. Alternatively, the layer 108_2 is formed on the layer 108_1 .

[0065]

[0066]

[0067] When the layers 108_1 and 108_3 have In-M-Zn oxide, the atomic ratio of In and M excluding Zn and oxygen is preferably such that In is less than 75 atomic% and M is greater than 25 atom ic%, more preferably In is less than 66 atomic% and M is greater than 34 atomic%. In particular, it is preferable that the layers 108_1 and 108_3 have a region where the atomic ratio of M is equal to or more than the atomic ratio of In.

[0067] ​In addition, when layers 108_1 and 108_3 contain element M at an atomic ratio of In or more, the following effects may be obtained. (1) The energy gap becomes larger. (2) The electron affinity becomes smaller. (3) Impurities from the outside are shielded. (4) The insulating property becomes higher. Further, since element M is a metal element having a strong binding force with oxygen, having M at an atomic ratio of In or more makes it difficult for oxygen deficiency to occur. (1) The energy gap becomes larger. (2) The electron affinity becomes smaller. (3) Impurities from the outside are shielded. (4) The insulating property becomes higher. In addition, when layers 108_1 and 108_3 contain element M at an atomic ratio of In or more, the following effects may be obtained. (1) The energy gap becomes larger. (2) The electron affinity becomes smaller. (3) Impurities from the outside are shielded. (4) The insulating property becomes higher. Further, since element M is a metal element having a strong binding force with oxygen, having M at an atomic ratio of In or more makes it difficult for oxygen deficiency to occur. In addition, when layers 108_1 and 108_3 contain element M at an atomic ratio of In or more, the following effects may be obtained. (1) The energy gap becomes larger. (2) The electron affinity becomes smaller. (3) Impurities from the outside are shielded. (4) The insulating property becomes higher.

[0068] Also, the number of atoms of element M contained in layers 108_1 and 108_3 is preferably equal to or more than the number of atoms of element M contained in layer 108_2. Typically, compared with the number of atoms of element M contained in layer 108_2, the atomic ratio of element M contained in layers 108_1 and 108_3 is preferably 1.5 times or more, more preferably 2 times or more. Also, the number of atoms of element M contained in layers 108_1 and 108_3 is preferably equal to or more than the number of atoms of element M contained in layer 108_2. Typically, compared with the number of atoms of element M contained in layer 108_2, the atomic ratio of element M contained in layers 108_1 and 108_3 is preferably 1.5 times or more, more preferably 2 times or more. Also, the number of atoms of element M contained in layers 108_1 and 108_3 is preferably equal to or more than the number of atoms of element M contained in layer 108_2. Typically, compared with the number of atoms of element M contained in layer 108_2, the atomic ratio of element M contained in layers 108_1 and 108_3 is preferably 1.5 times or more, more preferably 2 times or more. Also, the number of atoms of element M contained in layers 108_1 and 108_3 is preferably equal to or more than the number of atoms of element M contained in layer 108_2. Typically, compared with the number of atoms of element M contained in layer 108_2, the atomic ratio of element M contained in layers 108_1 and 108_3 is preferably 1.5 times or more, more preferably 2 times or more.

[0069] Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Also, the number of atoms of In contained in layer 108_2 is preferably equal to or more than the number of atoms of In contained in layers 108_1 and 108_3. Typically, compared with the number of atoms of In contained in layer 108_1 or layer 108_3, the atomic ratio of In contained in layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more. At this time, layer 108_2 can function as a channel region in transistors 100 and 100A. Further, with this configuration, in transistors 100 and 100A, an increase in on-current and an increase in field-effect mobility can be expected. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. In a transistor having a high field-effect mobility, the threshold voltage may become negative (also referred to as normally-on characteristics). This is because charges are generated due to oxygen deficiency contained in the oxide semiconductor film of the transistor, resulting in low resistance. When the transistor has normally-on characteristics, malfunction may occur during operation. Various problems occur, such as being prone to occur or having high power consumption during non-operation. Therefore, as the layer 108_2, it is preferably the following C AAC-OS with few impurities and defects (such as oxygen deficiency).

[0070] <1-2. Band Structure> Next, regarding the band structure of the oxide semiconductor film and the insulating film in contact with the oxide semiconductor film in the transistor 100 shown in FIG. 1 and the transistor 100A shown in FIG. 2, it will be described with reference to FIG. 15.

[0071] FIG. 15(A) shows the band structure in the film thickness direction of the insulating film 104, layer 108_2, layer 108_3, and insulating film 110, and FIG. 15(B) shows the band structure in the film thickness direction of the insulating film 104, layer 108_1, layer 108_ 2, layer 108_3, and insulating film 110. Note that the band structure shows the energy level (Ec) of the lower end of the conduction band of the insulating film 104, layer 108_1, 108_2, 108_3, and insulating film 110 for easy understanding.

[0072] Here, a silicon oxide film is used as the insulating film 104 and the insulating film 110, and a metal oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2 in layer 10 8_1 is used to form an oxide semiconductor film, and a metal oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1 in layer 108_2 is used to form an oxide semiconductor film, and a metal oxide target with an atomic ratio of In:Ga:Zn = 1:1 :1.2 in layer 108_3 is used to form an oxide semiconductor film.

[0073] As shown in FIGS. 15(A) and 15(B), in layers 108_1, 108_2, and 108_3 the energy at the lower end of the conduction band has no barrier and changes smoothly. In other words, it can be said that it changes continuously or forms a continuous junction. Therefore, such an energy band is also referred to as an embedded channel structure.

[0074] This is because layers 108_1, 108_2, and 108_3 have common elements, and an oxygen mixture layer is formed due to the mutual movement of oxygen among layers 108_ 1, 108_2, and 108_3. Further, in order to have such a band structure, a stacked structure is adopted such that there are no impurities that form defect energy levels such as trap centers or recombination centers at the interface between layer 108_1 and layer 108_ 2, or at the interface between layer 108_2 and layer 108_3. If a continuous junction is not formed and impurities are mixed at the interface between layer 108_1 and layer 108_2 or at the interface between layer 108 _2 and layer 108_3, the continuity of the energy band is lost, carriers are trapped at the interface, or recombine and disappear.

[0075]

[0076] In order to form a continuous junction, it is preferable to use a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber to continuously stack each film without exposing it to the atmosphere. Each chamber in the sputtering apparatus should use an adsorption-type vacuum pump such as a cryopump to exhaust to a high vacuum (up to about 5×10 -7 Pa to 1×10 -4 Pa) as much as possible to remove impurities such as water that would become impurities for the oxide semiconductor film. ​​​​​​​Or, it is preferable to combine a turbo molecular pump and a cold trap so that gas, particularly gas containing carbon or hydrogen, does not flow backward from the exhaust system into the chamber. Preferably, the gas is prevented from flowing backward.

[0077] With the configuration shown in FIGS. 15(A) and (B), layer 108_2 becomes a well, and it can be seen that in transistor 100 having layers 108_2 and 108_3, and in transistor 100A having layers 108_1, 108_2, and 108_3, the channel region is formed in layer 108_2. In transistor 100, even if trap levels are formed near the interface between layer 108_3 and insulating film 110 due to impurities or defects, layer 108_3 can be provided to separate layer 108_2 from the region where the trap levels are formed. Also, in transistor 100A, even if trap levels are formed near the interface between layer 108_1 and insulating film 104 and near the interface between layer 108_3 and insulating film 110 due to impurities or defects, layers 108_1 and 108_3 can be provided to separate layer 108_2 from the region where the trap levels are formed. However, when the energy level of the trap level is lower than the energy level (Ec) at the lower end of the conduction band of layer 108_2 that functions as the channel region, electrons are likely to be captured by the trap level. When electrons are captured and accumulated in the trap level, negative fixed charges are generated on the surface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy level of the trap level is the energy level at the lower end of the conduction band of layer 108_2.

[0078] In transistor 100, even if trap levels are formed near the interface between layer 108_3 and insulating film 110 due to impurities or defects, layer 108_3 can be provided to separate layer 108_2 from the region where the trap levels are formed. Also, in transistor 100A, even if trap levels are formed near the interface between layer 108_1 and insulating film 104 and near the interface between layer 108_3 and insulating film 110 due to impurities or defects, layers 108_1 and 108_3 can be provided to separate layer 108_2 from the region where the trap levels are formed. However, when the energy level of the trap level is lower than the energy level (Ec) at the lower end of the conduction band of layer 108_2 that functions as the channel region, electrons are likely to be captured by the trap level. When electrons are captured and accumulated in the trap level, negative fixed charges are generated on the surface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy level of the trap level is the energy level at the lower end of the conduction band of layer 108_2. In transistor 100A, even if trap levels are formed near the interface between layer 108_1 and insulating film 104 and near the interface between layer 108_3 and insulating film 110 due to impurities or defects, layers 108_1 and 108_3 can be provided to separate layer 108_2 from the region where the trap levels are formed. However, when the energy level of the trap level is lower than the energy level (Ec) at the lower end of the conduction band of layer 108_2 that functions as the channel region, electrons are likely to be captured by the trap level. When electrons are captured and accumulated in the trap level, negative fixed charges are generated on the surface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy level of the trap level is the energy level at the lower end of the conduction band of layer 108_2.

[0079] However, when the energy level of the trap level is lower than the energy level at the lower end of the conduction band of layer 108_2 that functions as the channel region, electrons are likely to be captured by the trap level. When electrons are captured and accumulated in the trap level, negative fixed charges are generated on the surface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy level of the trap level is lower than the energy level at the lower end of the conduction band of layer 108_2, the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy level of the trap level is the energy level at the lower end of the conduction band of layer 108_2.​​​​​ It is preferably configured to be higher than (Ec). By doing so, it becomes difficult for electrons to accumulate in the trap level, and it is possible to increase the on-current of the transistor. At the same time, the field-effect mobility can be increased. Also, the variation of the threshold voltage of the transistor is reduced, resulting in stable electrical characteristics, which is preferable.

[0080] Also, to prevent the layers 108_1 and 108_3 from functioning as part of the channel region, it is preferable to use a material with a lower conductivity than that of the layer 108_2 for the layers 108_1 and 108_3. Therefore, the layers 108_1 and 108_3 can be referred to as oxide insulating films respectively from their physical properties and / or functions. Also, for the layers 108_1 and 108_3, the electron affinity (the energy level difference between the vacuum level and the lower end of the conduction band) is smaller than that of the layer 108_2, and it is preferable to use a material having an energy level difference (band offset) at the lower end of the conduction band from the lower end of the conduction band energy level of the layer 108_2. Also, to suppress the occurrence of a difference in the threshold voltage depending on the magnitude of the drain voltage, it is preferable to use a material in which the energy level at the lower end of the conduction band of the layers 108_1 and 108_3 is closer to the vacuum level than the energy level at the lower end of the conduction band of the layer 108_2. For example, the difference between the energy level at the lower end of the conduction band of the layer 108_2 and the energy levels at the lower ends of the conduction bands of the layers 108_1 and 108_3 is preferably 0.2 eV or more, preferably 0.5 eV or more. By having such a configuration, among the channel regions 108i, the layer 108_2 becomes the main current path. That is, the layer 108_2 has a function as a channel region, and the layer 10

[0081] ​​​​​8_1 and 108_3 have the function as an oxide insulating film. Also, layers 108_1 and 10 8_3 are oxide semiconductor films composed of one or more of the metal elements constituting layer 108_2 in which the channel region is formed. Therefore, interface scattering hardly occurs at the interface between layer 108_1 and layer 108_2 or at the interface between layer 1 08_2 and layer 108_3. Thus, since the movement of carriers is not inhibited at the interface, the field-effect mobility of the transistor becomes high.

[0082] <1-3. Oxide Semiconductor Film Functioning as Gate Electrode> Next, the oxide semiconductor film functioning as the gate electrode will be described. The oxide semiconductor film 112 functioning as the gate electrode has the function of supplying oxygen to the insulating film 110. Since the oxide semiconductor film 112 has the function of supplying oxygen to the insulating film 110, it becomes possible to include excess oxygen in the insulating film 110. Since the insulating film 110 has an excess oxygen region, the excess oxygen can be supplied to the oxide semiconductor film 108, more specifically, into the channel region 108i. Therefore, by compensating for the oxygen deficiency in the channel region 108i with excess oxygen, a highly reliable semiconductor device can be obtained.

[0083] Note that in order to supply excess oxygen into the oxide semiconductor film 108, the insulating film 104 formed below the oxide semiconductor film 10 8 may have excess oxygen. However, when the insulating film 10 4 has excess oxygen, the oxygen contained in the insulating film 104 can also be supplied to the source region 108s and the drain region 108d that the oxide semiconductor film 108 has. When excess oxygen is supplied into the source region 1 08s and the drain region 108d, the source region 108s, ​​​​​​​​​And the resistance in the drain region 108d may become high.

[0084] On the other hand, the insulating film 110 formed above the oxide semiconductor film 108 has excess oxygen. By forming the semiconductor layer 108 in this manner, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, the channel region 108i, the source region 108s, and the drain region 10 After supplying excess oxygen to the source region 108s and the drain region 108d, The carrier density can be selectively increased.

[0085] The insulating film 116 contains either nitrogen or hydrogen, or both. By configuring 16 to have either nitrogen or hydrogen or both, an oxide semiconductor Either nitrogen or hydrogen or both are supplied to the oxide semiconductor film 108 and the oxide semiconductor film 112. It can be provided.

[0086] Note that the oxide semiconductor film 112 is formed by heating the insulating film 116 after oxygen is supplied to the insulating film 110. By supplying either nitrogen or hydrogen or both from the source, the carrier density becomes higher. In other words, the oxide semiconductor film 112 is an oxide conductor (OC). Therefore, the oxide semiconductor film 112 also functions as an oxide semiconductor. The carrier density is higher than that of the solid film 108, and the solid film 108 can function as a gate electrode.

[0087] In addition, the source region 108s and the drain region 108d of the oxide semiconductor film 108 The oxide semiconductor film 112 may each contain an element that forms oxygen vacancies. Representative elements that form the oxygen vacancies are hydrogen, boron, carbon, nitrogen, and fluorine. Examples include elements such as silicon, phosphorus, sulfur, chlorine, and noble gas elements. Representative examples of noble gas elements include , helium, neon, argon, krypton, and xenon.

[0088] When an impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and oxygen deficiency is formed. Or, when an impurity element is added to the oxide semiconductor film , the oxygen that was bonded to the metal element in the oxide semiconductor film bonds with the impurity element, and oxygen is desorbed from the metal element, forming oxygen deficiency. As a result, the carrier density in the oxide semiconductor film increases, and the conductivity increases.

[0089] Further, in the transistors 100 and 100A, it is preferable to have a region where the side end of the insulating film 110 and the side end of the oxide semiconductor film 112 are aligned. In other words, in the transistor 10 0, the upper end of the insulating film 110 and the lower end of the oxide semiconductor film 112 are substantially aligned. For example, by processing the insulating film 110 using the oxide semiconductor film 112 as a mask, the above structure can be obtained.

[0090] As described above, in the semiconductor device according to one aspect of the present invention, an oxide semiconductor film that functions as a gate electrode contains excess oxygen in the insulating film that covers the side surface of the oxide semiconductor film that becomes the channel region and is formed above the channel region. By adopting such a configuration, a highly reliable semiconductor device can be provided.

[0091] Next, the details of the components of the semiconductor device shown in FIGS. 1(A), (B), and (C) will be described.

[0092] <1-4. Components of the semiconductor device> [Substrate] ​​​As the substrate 102, various substrates can be used and it is not limited to a specific one. As an example of the substrate, there are a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SO I substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate , a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil , a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film etc. As an example of the glass substrate, there are barium borosilicate glass, aluminoboro silicate glass, or soda lime glass etc. As an example of the flexible substrate, the laminated film , the base film etc., there are the following. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES) and other plastics. Or, as an example, there are synthetic resins such as acrylic etc. . Or, as an example, there are polypropylene, polyester, polyvinyl fluoride , polyvinyl chloride etc. Or, as an example, there are polyamide, polyimide , aramid, epoxy, an inorganic vapor deposition film, or papers etc. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate etc., variations in characteristics, size, or shape etc. are small, a transistor with high current capacity and small size can be manufactured. When a circuit is configured with such a transistor, power consumption reduction of the circuit or high integration of the circuit can be achieved.

[0093] Also, as the substrate 102, a flexible substrate is used and a transistor is formed directly on the flexible substrate. It may be formed. Alternatively, a release layer may be provided between the substrate 102 and the transistor. The release layer is used to separate from the substrate 102 after partially or completely completing a semiconductor device thereon and transfer it to another substrate. At this time, the transistor can also be transferred to a substrate with poor heat resistance or a flexible substrate. Note that, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on the substrate can be used for the above-mentioned release layer .

[0094] As an example of the substrate onto which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon , polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates , it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is difficult to break, impart heat resistance, reduce weight, or make it thinner . .

[0095] [First insulating film] As the insulating film 104, it can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition ( PLD) method, a printing method, a coating method, etc. Further, as the insulating film 104 , for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a laminate . In order to improve the interface characteristics with the oxide semiconductor film 108, the insulating film 104 ​At least the region in contact with the oxide semiconductor film 108 is preferably formed of an oxide insulating film. Further, an oxide insulating film that releases oxygen by heating is used as the insulating film 104. By heat treatment, the oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108. This is possible.

[0096] The thickness of the insulating film 104 can be 50 nm or more, or 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, and the interface states at the interface between the insulating film 104 and the oxide semiconductor film 108, as well as the oxygen deficiency contained in the channel region 108i of the oxide semiconductor film 108, can be reduced.

[0097] As the insulating film 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide etc. can be used, and it can be provided as a single layer or a laminate. In this embodiment, as the insulating film 104, a laminated structure of a silicon nitride film and a silicon oxynitride film is used. In this way, by using a laminated structure for the insulating film 104, with a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side, oxygen can be efficiently introduced into the oxide semiconductor film 108. This is possible.

[0098] [Oxide Semiconductor Film] As the oxide semiconductor film 108, the materials shown above can be used. Further, either one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 is In-M-Zn oxide ( M is formed of a metal oxide such as Al, Ga, Y, or Sn). Also, the oxide semiconductor film 108 and the oxide semiconductor film 112 may be made of In-Ga oxide or In-Zn oxide. In particular, when the oxide semiconductor film 108 and the oxide semiconductor film 112 are formed of a metal oxide composed of the same constituent elements, it is preferable because the manufacturing cost can be reduced.

[0099] When the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxide, the atomic ratio of In to M is such that In is higher than 2 5 atomic% and M is less than 75 atomic%, or In is higher than 34 atomi c% and M is less than 66 atomic%.

[0100] The oxide semiconductor film 108 and the oxide semiconductor film 112 preferably have an energy gap of 2 eV or more , or 2.5 eV or more, or 3 eV or more.

[0101] The thickness of the oxide semiconductor film 108 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 1 00 nm or less, more preferably 3 nm or more and 60 nm or less. Also, the oxide semiconductor film 112 has a thickness of 5 nm or more and 500 nm or less, preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 100 nm or less.

[0102] When the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxide, I n order to form the In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used is preferably such that In ≧ M and Zn ≧ M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1: 1:1, etc. are preferable. 1:1.2, In:M:Zn = 2:1:1.5, In:M:Zn = 2:1:2.3, In :M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4. 1, In:M:Zn = 5:1:7 etc. are preferable. Note that the atomic ratio of the oxide semiconductor film 108 to be formed , and the oxide semiconductor film 112 may each vary by about plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target . For example, when using a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1 , the atomic ratio of the formed oxide semiconductor film may be in the vicinity of In:Ga:Zn = 4:2:3 .

[0103] Also, in the oxide semiconductor film 108, if silicon or carbon, which is one of the Group 14 elements, is contained , oxygen deficiency may increase and it may become n-type. To prevent this, in the oxide semiconductor film 108, especially in the channel region 108i, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) should be 2 × 10 18 atoms / cm 3 or less, or 2 × 10 17 atoms / cm 3 or less. As a result, the transistor has electrical characteristics (also called normally-off characteristics) in which the threshold voltage is positive.

[0104] Also, in the channel region 108i, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry should be 1 × 10 18 atoms / cm 3 or less, or 2 × 10 16 atoms / cm 3 ​The following is recommended: Alkali metals and alkaline earth metals When the oxide semiconductor is bonded to the oxide semiconductor, carriers may be generated, and the off-state current of the transistor may decrease. Therefore, the alkali metal or aluminum in the channel region 108i may be increased. It is preferable to reduce the concentration of potassium earth metals. This results in a transistor with a lower threshold voltage. It has electrical characteristics in which the applied voltage is positive (also called normally-off characteristics).

[0105] In addition, when nitrogen is contained in the channel region 108i, electrons that act as carriers are generated, and The carrier density increases and the semiconductor becomes n-type. As a result, the oxide semiconductor containing nitrogen A transistor using a thin film is likely to have normally-on characteristics. In the 08i, it is preferable that nitrogen is reduced as much as possible. For example, secondary ions The nitrogen concentration obtained by mass spectrometry was 5×10 18 atoms / cm 3 Let's say the following: stomach.

[0106] In addition, by reducing the impurity elements in the channel region 108i, Therefore, in the channel region 108i, the carrier density can be reduced. Carrier density is 1×10 17 pieces / cm 3 or less, or 1×10 15 pieces / cm 3 The following also is 1×10 13 pieces / cm 3 or less, or 1×10 11 pieces / cm 3 It can be .

[0107] The channel region 108i is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using this, a transistor having further excellent electrical characteristics can be manufactured. Here, an oxide semiconductor having a low impurity concentration and a low density of defect levels (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Alternatively, it is called intrinsic or substantially intrinsic. An oxide semiconductor that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density may be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage becomes positive. In addition, since the oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the trap level density may also be low. In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic can obtain characteristics in which the off-current is extremely small. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may be a transistor with small fluctuations in electrical characteristics and high reliability. In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic can obtain characteristics in which the off-current is extremely small. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may be a transistor with small fluctuations in electrical characteristics and high reliability. In addition, since the oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the trap level density may also be low. In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic can obtain characteristics in which the off-current is extremely small. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may be a transistor with small fluctuations in electrical characteristics and high reliability. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases.

[0108] On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases. On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. Since the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116, either one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s, the drain region 108d, and the oxide semiconductor film 112, so that the carrier density increases.

[0109] In addition, either one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 may have a non-single crystal structure. The non-single crystal structure is, for example, CAAC-OS (C Ax In addition, either one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 may have a non-single crystal structure. The non-single crystal structure is, for example, CAAC-OS (C Ax is Aligned Crystalline Oxide Semiconduct or), a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single crystal structure the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels .

[0110] Note that the oxide semiconductor film 108 may be a single-layer film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, or it may be a structure in which these films are stacked. Also, the oxide semiconductor film 112 may be a single-layer film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, or a structure in which these films are stacked . In the oxide semiconductor film 108, the crystallinity of the channel region 108i may be different from that of the source region 108s and the drain region 108d. Specifically, in the oxide semiconductor film

[0111] 108, the source region 108s and the drain region 10 8d may have lower crystallinity than the channel region 108i. This is because when impurity elements are added to the source region 108s and the drain region 1 08d, damage occurs in the source region 108s and the drain region 108d, resulting in a decrease in crystallinity .

[0112] [Insulating film functioning as a gate insulating film] The insulating film 110 can be formed by laminating a single layer or a stack of an oxide insulating film or a nitride insulating film . In order to improve the interface characteristics with the oxide semiconductor film 108, at least the region of the insulating film 110 in contact with the oxide semiconductor film 108 is formed using an oxide insulating film​​ is preferable. As the insulating film 110, for example, silicon oxide, silicon oxynitride, nitrided silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga -Zn oxide or the like may be used, and it can be provided as a single layer or a laminate.

[0113] Further, by providing an insulating film having a blocking effect on oxygen, hydrogen, water, etc. as the insulating film 110, diffusion of oxygen from the oxide semiconductor film 108 to the outside and intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 108 can be prevented. Examples of the insulating film having a blocking effect on oxygen, hydrogen, water, etc. include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, and the like.

[0114] Further, as the insulating film 110, hafnium silicate (HfSiO x ), hafnium silicate (HfSi to which nitrogen is added x O y N z ), hafnium aluminate (HfAl to which nitrogen is added x O y N z ), high-k materials such as hafnium oxide and yttrium oxide are used to reduce the gate leakage of the transistor.

[0115] Further, by using an oxide insulating film that releases oxygen by heating as the insulating film 110, it is possible to move the oxygen contained in the insulating film 110 to the oxide semiconductor film 108 by heat treatment.

[0116] ​The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less , or 10 nm or more and 250 nm or less.

[0117] [Second insulating film] The insulating film 116 contains either or both of nitrogen and hydrogen. Examples of the insulating film 116 include a nitride insulating film. As the nitride insulating film, silicon nitride, oxynitride silicon, aluminum nitride, aluminum oxynitride, etc. can be used to form it. The hydrogen concentration contained in the insulating film 116 is preferably 1×10 22 atoms / cm 3 or more. Further, the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108, and is also in contact with the oxide semiconductor film 112. Therefore, the hydrogen concentration in the source region 108s, the drain region 108d, and the oxide semiconductor film 112 in contact with the insulating film 116 increases, and the carrier density of the source region 108s, the drain region 1 08d, and the oxide semiconductor film 112 can be increased. Note that as the source region 108s, the drain region 108d, and the oxide semiconductor film 112, there may be cases where they have regions with the same hydrogen concentration by being in contact with the insulating film 116 respectively.

[0118] [Third insulating film] As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed by a single layer or a laminate. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or G a-Zn oxide, etc. can be used, and it can be provided in a single layer or a laminate. ​​​

[0119] Further, the insulating film 118 is preferably a film that functions as a barrier film against hydrogen, water, etc. from the outside. It is preferable.

[0120] The thickness of the insulating film 118 can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. It can be set.

[0121] [Conductive film] As the conductive films 120a and 120b, they can be formed by using a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. Further, as the conductive films 120a and 120b, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements can be used. Also, a metal element selected from one or more of manganese and zirconium may be used. Further, the conductive films 120a and 120b may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, a two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. They can be formed. 、120b, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten, a metal element selected therefrom, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements can be used. element, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements can be used to form it. It can be formed. Also, a metal element selected from one or more of manganese and zirconium may be used. element may be used. Further, the conductive films 120a and 120b may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, a two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. structure. structure, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, a two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, a two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. structure, a two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. layer structure, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. layer structure, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed thereon. There is a three-layer structure or the like. Also, one or a combination of multiple elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be combined with aluminum and used as a metal film or a nitride film.

[0122] Also, the conductive films 120a and 120b may be made of a conductive material with light transmittance such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon (also referred to as In-Sn-Si oxide: ITSO), etc. Also, a laminated structure of the above-mentioned conductive material with light transmittance and the above-mentioned metal element can also be formed.

[0123] The thickness of the conductive films 120a and 120b can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

[0124] <1-5. Configuration Example 2 of Semiconductor Device> Next, a configuration different from the semiconductor device shown in FIGS. 1(A), (B), and (C) will be described with reference to FIGS. 3(A) and (B).

[0125] FIGS. 3(A) and (B) are cross-sectional views of the transistor 100B. Since the top view of the transistor 100B is the same as that of the transistor 100 shown in FIG. 1(A), FIG. 1(A) will be incorporated for explanation. FIG. 3(A) is a cross-sectional view between the dashed-dotted line X1-X2 in FIG. 1(A), and FIG. 3(B) is a cross-sectional view between the dashed-dotted line Y1-Y2 in FIG. 1(A).

[0126] The transistor 100B is a transistor 100 shown above, and a conductor that functions as a gate electrode. The other configurations are the same as those of the transistor 100. This has the same effect.

[0127] The gate electrode of the transistor 100B is formed by a gate electrode including an oxide semiconductor film 112 and an oxide semiconductor and a conductive film 114 on the film 112.

[0128] The conductive film 114 is made of a material that can be used for the conductive films 120a and 120b described above. A fee can be used.

[0129] In this manner, in the transistor of one embodiment of the present invention, The conductive film has a stacked structure of an oxide semiconductor film 112 and a conductive film 114 over the oxide semiconductor film 112. For example, the conductive film 114 may be made of a conductive material having low resistance. This makes it possible to reduce the wiring resistance of the gate electrode.

[0130] In addition, in the transistor 100A shown above, as in the transistor 100B, The gate electrode is formed by stacking the oxide semiconductor film 112 and the conductive film 114 on the oxide semiconductor film 112. A layered structure can be used. An example of this is shown in Figure 4(A)(B). ) is a cross-sectional view of transistor 100C.

[0131] In this manner, in the transistor of one embodiment of the present invention, the transistor described above They can be used in appropriate combination.

[0132] <1-6. Configuration example 3 of semiconductor device> Next, regarding the semiconductor device having a different structure from that shown in FIG. 1(A)(B)(C), This will be described with reference to (B).

[0133] FIGS. 5(A) and (B) are cross-sectional views of the transistor 100D. The transistor 100D has a different shape of the insulating film 110 from that of the transistor 100 shown above. For other configurations is the same as that of the transistor 100 shown above and exhibits the same effects.

[0134] The insulating film 110 included in the transistor 100D is located inside the oxide semiconductor film 112 In other words, the side surface of the insulating film 110 is located inside the lower end of the oxide semiconductor film 112 For example, after processing the oxide semiconductor film 112, the insulating film 110 can be side-etched using an etchant or the like to obtain the configuration shown in FIGS. 5(A) and (B). By setting the insulating film 110 to the above structure, a hollow region 147 is formed below the oxide semiconductor film 112

[0135] The hollow region 147 contains air and functions as part of the gate insulating film. The relative permittivity of the hollow region 147 is approximately 1, the same as that of air. Therefore, with the structure of the transistor 100D when a voltage is applied to the oxide semiconductor film 112 that functions as a gate electrode the voltage applied to the oxide semiconductor film 108 below the hollow region 147 is lower than the voltage applied to the oxide semiconductor film 108 (channel region 108i) below the insulating film 110 As a result, the oxide semiconductor film 108 below the hollow region 147 effectively functions as an overlap region (also referred to as a Lov region). By providing a Lov region in the oxide semiconductor film 108 the electric field concentrated at the source end and the drain end can be relaxed. Note that ​​​​​The Lov region overlaps with the oxide semiconductor film 112 that functions as a gate electrode and has a lower resistance than the channel region 108i.

[0136] Also, in the transistor 100A shown above, the insulating film 110 can be configured in the same manner as in the transistor 100D. An example in that case is shown in FIGS. 6(A) and (B). FIGS. 6( A) and (B) are cross-sectional views of the transistor 100E.

[0137] <1-7. Configuration Example 4 of Semiconductor Device> Next, a configuration different from that of the semiconductor device shown in FIGS. 1(A), (B), and (C) will be described with reference to FIGS. 7(A) and ( B).

[0138] FIGS. 7(A) and (B) are cross-sectional views of the transistor 100F. The transistor 100F has different shapes of the insulating film 110 and the insulating film 116 from those of the transistor 100 shown above . For other configurations, it has the same configuration as the transistor 100 shown above and exhibits the same effects.

[0139] The insulating film 110 included in the transistor 100F is positioned inside the oxide semiconductor film 112 . In other words, the side surface of the insulating film 110 is positioned inside the lower end portion of the oxide semiconductor film 112 . For example, after processing the oxide semiconductor film 112, the insulating film 110 can be side-etched using an etchant or the like to obtain the configuration shown in FIGS. 7(A) and (B). Also, after forming the insulating film 110 with the above structure, by forming the insulating film 116, the insulating film 116 also penetrates under the oxide semiconductor film 112 and contacts the oxide semiconductor film 108 positioned below the oxide semiconductor film 112 .

[0140] ​With the above configuration, the source region 108s and the drain region 108d are located inside the lower end of the oxide semiconductor film 112. Therefore, the transistor 100F has a Lov region. By configuring the transistor to have a Lov region, the electric field concentration is alleviated, and a high-resistance region is not formed between the channel region 108i, the source region 108s, and the drain region 108d. Thus, it is possible to increase the on-current of the transistor.

[0141] Also, in the transistor 100A shown above, similar to the transistor 100F, the structure of the insulating film 110 and the insulating film 116 can be made the same as the above-described embodiment. An example in that case is shown in FIGS. 8(A) and 8(B). FIGS. 8(A) and 8(B) are cross-sectional views of the transistor 100G.

[0142]

[0143] <1-8. Configuration Example 5 of Semiconductor Device> Next, a configuration different from the semiconductor device shown in FIGS. 1(A), 1(B), and 1(C) will be described with reference to FIGS. 9(A), 9(B), and 9(C).

[0144] FIG. 9(A) is a top view of the transistor 150, FIG. 9(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 9(A), and FIG. 9(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 9(A).

[0145] The transistor 150 shown in FIGS. 9(A), 9(B), and 9(C) includes a conductive film 106 formed on the substrate 102, an insulating film 104 on the conductive film 106, an oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, and an oxide semiconductor film 112 on the insulating film 110. ​​​​​​​​​​​​and an insulating film 104, an oxide semiconductor film 108, and an insulating film 116 on the oxide semiconductor film 112 and has. Further, the oxide semiconductor film 108 has a channel region 108i that overlaps the oxide semiconductor film 112, a source region 108s that contacts the insulating film 116, and a drain region 108d that contacts the insulating film 116. The channel region 108i has a layer 108_2 and a layer 108 _3 that contacts the upper surface of layer 108_2 and covers the side surface of layer 108_2 in the channel width direction. has.

[0146] Also, the oxide semiconductor film 112 is electrically connected to the conductive film 106 through an opening 143 provided in the insulating film 110, the layer 108_3, and the insulating film 104. Therefore, the same potential is applied to the conductive film 1 06 and the oxide semiconductor film 112. Also, different potentials may be applied to the conductive film 106 and the oxide semiconductor film 112 without providing the opening 143.

[0147] Thus, in addition to the configuration of the transistor 100 shown above, the transistor 150 has a conductive film 106 and an opening 143.

[0148] Note that the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the oxide semiconductor film 112 functions as a second gate electrode (also referred to as a top gate electrode). Also, the insulating film 104 functions as a first gate insulating film, and the insulating film 110 functions as a second gate insulating film.

[0149] Thus, unlike the transistor 100 described above, the transistor 150 shown in FIGS. 9(A), (B), and (C) has conductive films that function as gate electrodes above and below the oxide semiconductor film 108. It has a so-called dual gate structure having a film and an oxide semiconductor film. Transistor 150 As shown in, a semiconductor device according to an aspect of the present invention may be provided with two or more gate electrodes .

[0150] Also, as shown in FIG. 9(C), the oxide semiconductor film 108 is positioned to face the conductive film 106 that functions as the first gate electrode and the oxide semiconductor film 112 that functions as the second gate electrode, and is sandwiched between the conductive film and the oxide semiconductor film that function as the two gate electrodes respectively .

[0151] Further, the length of the oxide semiconductor film 112 in the channel width (W) direction is longer than the length of the oxide semiconductor film 108 in the channel width (W) direction, and the entire oxide semiconductor film 108 in the channel width (W) direction is covered by the oxide semiconductor film 112 via the insulating film 110. Also, the oxide semiconductor film 112 and the conductive film 106 are connected at the opening 143 provided in the insulating film 104, layer 108_3, and insulating film 110, so one of the side surfaces of the oxide semiconductor film 108 in the channel width (W) direction faces the oxide semiconductor film 112 . .

[0152] In other words, in the channel width (W) direction of the transistor 150, the conductive film 106 and the oxide semiconductor film 112 are connected at the opening 143 provided in the insulating film 104, layer 108_3, and insulating film 110, and surround the oxide semiconductor film 108 via the insulating film 104, layer 108_3, and insulating film 110 . .

[0153] By having such a configuration, the oxide semiconductor film 108 included in the transistor 150 is formed by the conductive film 106 that functions as the first gate electrode and the oxide semiconductor film that functions as the second gate electrode that functions as the second gate electrode​​​​​ can be electrically surrounded by the electric field of the oxide semiconductor film 112. Transistor 15 As in 0, the channel region is formed by the electric fields of the first gate electrode and the second gate electrode, and the device structure of the transistor that electrically surrounds the oxide semiconductor film to be formed can be called a surrounded channel (S-channel) structure.

[0154] Since the transistor 150 has an S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 106 or the oxide semiconductor film 112. Therefore, the current driving ability of the transistor 150 is improved, and high on-current characteristics can be obtained. In addition, since the on-current can be increased, the transistor 150 can be miniaturized. Further, since the oxide semiconductor film 108 has a structure surrounded by the conductive film 106 and the oxide semiconductor film 112, the mechanical strength of the oxide semiconductor film 108 can be increased.

[0155] Note that, in the channel width (W) direction of the transistor 150, an opening different from the opening 143 may be formed on the side surface side of the oxide semiconductor film 108 where the opening 143 is not formed.

[0156] Further, as shown in the transistor 150, when the transistor has a pair of gate electrodes sandwiching a semiconductor film therebetween, a signal A may be applied to one gate electrode and a fixed potential Vb may be applied to the other gate electrode. Alternatively, a signal A may be applied to one gate electrode and a signal B may be applied to the other gate electrode. Further, a fixed potential Va may be applied to one gate electrode and ​​​​​​​​​​​On the other hand, a fixed potential Vb may be applied to the other gate electrode.

[0157] Signal A is, for example, a signal for controlling a conductive state or a non-conductive state. Signal A is a digital signal that takes two types of potentials, potential V1 or potential V2 (where V1 > V2). For example, potential V1 can be set as the high power supply potential and potential V2 as the low power supply potential. Signal A may be an analog signal.

[0158] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor. The fixed potential Vb may be potential V1 or potential V2. The fixed potential Vb may be a potential different from potential V1 or potential V2. By lowering the fixed potential Vb, the threshold voltage VthA may be increased. As a result, the drain current when the gate-source voltage Vgs is 0V can be reduced, and the leakage current of the circuit having the transistor can be reduced. For example, the fixed potential Vb may be set lower than the low power supply potential. By increasing the fixed potential Vb, the threshold voltage VthA may be decreased. As a result, the drain current when the gate-source voltage Vgs is VDD can be improved, and the operating speed of the circuit having the transistor may be improved. For example, the fixed potential Vb may be set higher than the low power supply potential.

[0159] Signal B is, for example, a signal for controlling a conductive state or a non-conductive state. Signal B is a digital signal that takes two types of potentials, potential V3 or potential V4 (where V3 > V4). For example, potential V3 can be set as the high power supply potential and potential V4 as the low power supply potential. Signal B may be an analog signal.

[0160] When both signal A and signal B are digital signals, signal B may be a signal having the same digital value as signal A. In this case, the on-current of the transistor can be improved, and the operating speed of the circuit having the transistor may be improved. At this time, the potential V1 and the potential V2 in signal A may be different from the potential V3 and the potential V4 in signal B. For example, when the gate insulating film corresponding to the gate to which signal B is input is thicker than the gate insulating film corresponding to the gate to which signal A is input, the potential amplitude (V3 - V4) of signal B may be made larger than the potential amplitude (V1 - V2) of signal A. By doing so, the influence exerted by signal A and the influence exerted by signal B on the conductive state or non-conductive state of the transistor may be made approximately the same. When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having the same digital value as signal A. In this case, the on-current of the transistor can be improved, and the operating speed of the circuit having the transistor may be improved. At this time, the potential V1 and the potential V2 in signal A may be different from the potential V3 and the potential V4 in signal B. For example, when the gate insulating film corresponding to the gate to which signal B is input is thicker than the gate insulating film corresponding to the gate to which signal A is input, the potential amplitude (V3 - V4) of signal B may be made larger than the potential amplitude (V1 - V2) of signal A. By doing so, the influence exerted by signal A and the influence exerted by signal B on the conductive state or non-conductive state of the transistor may be made approximately the same. When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having the same digital value as signal A. In this case, the on-current of the transistor can be improved, and the operating speed of the circuit having the transistor may be improved. At this time, the potential V1 and the potential V2 in signal A may be different from the potential V3 and the potential V4 in signal B. For example, when the gate insulating film corresponding to the gate to which signal B is input is thicker than the gate insulating film corresponding to the gate to which signal A is input, the potential amplitude (V3 - V4) of signal B may be made larger than the potential amplitude (V1 - V2) of signal A. By doing so, the influence exerted by signal A and the influence exerted by signal B on the conductive state or non-conductive state of the transistor may be made approximately the same. When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having the same digital value as signal A. In this case, the on-current of the transistor can be improved, and the operating speed of the circuit having the transistor may be improved. At this time, the potential V1 and the potential V2 in signal A may be different from the potential V3 and the potential V4 in signal B. For example, when the gate insulating film corresponding to the gate to which signal B is input is thicker than the gate insulating film corresponding to the gate to which signal A is input, the potential amplitude (V3 - V4) of signal B may be made larger than the potential amplitude (V1 - V2) of signal A. By doing so, the influence exerted by signal A and the influence exerted by signal B on the conductive state or non-conductive state of the transistor may be made approximately the same. When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having the same digital value as signal A. In this case, the on-current of the transistor can be improved, and the operating speed of the circuit having the transistor may be improved. At this time, the potential V1 and the potential V2 in signal A may be different from the potential V3 and the potential V4 in signal B. For example, when the gate insulating film corresponding to the gate to which signal B is input is thicker than the gate insulating film corresponding to the gate to which signal A is input, the potential amplitude (V3 - V4) of signal B may be made larger than the potential amplitude (V1 - V2) of signal A. By doing so, the influence exerted by signal A and the influence exerted by signal B on the conductive state or non-conductive state of the transistor may be made approximately the same.

[0161] When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is When both signal A and signal B are digital signals, signal B may be a signal having a digital value different from that of signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized. For example, when the transistor is an n-channel type, when signal A is at potential V1 and signal B is at potential V3, the transistor is in a conducting state, or when signal A is at potential V2 and signal B is at potential V4, the transistor is in a non-conducting state only. In such cases, functions such as a NAND circuit or a NOR circuit may be realized with one transistor. Also, signal B may be a signal for controlling the threshold voltage VthA. For example, signal B may be a signal having different potentials during the period when the circuit having the transistor is operating and during the period when the circuit is not operating. Signal B is The signals may have different potentials according to the operation mode of the circuit. In this case, signal B may not switch its potential as frequently as signal A does.

[0162] When both signal A and signal B are analog signals, signal B may be an analog signal having the same potential as signal A, an analog signal obtained by multiplying the potential of signal A by a constant, or an analog signal obtained by adding or subtracting a constant from the potential of signal A. In this case, the on-current of the transistor may be increased, and the operation speed of the circuit having the transistor may be increased. Signal B may be an analog signal different from signal A. In this case, the transistor can be controlled separately by signal A and signal B, and higher functions may be realized.

[0163] Signal A may be a digital signal and signal B may be an analog signal. Or signal A may be an analog signal and signal B may be a digital signal.

[0164] When a fixed potential is applied to both gate electrodes of the transistor, the transistor may function as an element equivalent to a resistance element. For example, when the transistor is an n-channel type, by increasing (decreasing) the fixed potential Va or the fixed potential Vb, the effective resistance of the transistor may be decreased (increased). By increasing (decreasing) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by a transistor having only one gate may be obtained.

[0165] Note that the other configurations of the transistor 150 are the same as those of the transistor 100 shown above, and the same effects can be obtained.

[0166] ​​​​​​​​​​​​ Also, in the transistor 100A shown above, similar to the transistor 150, a conductive film 106 and an opening 143 may be provided. An example in that case is shown in FIGS. 10(A) and (B). . FIG. 10(A) is a cross-sectional view between the dashed-dotted line X1-X2 in FIG. 9(A), and FIG. 10(B) is a cross-sectional view between the dashed-dotted line Y1-Y2 in FIG. 9(A).

[0167] <1-9. Configuration Example 6 of Semiconductor Device> Next, a configuration different from the semiconductor device shown in FIGS. 1(A), (B), and (C) will be described with reference to FIGS. 11(A) (B), and (C).

[0168] FIG. 11(A) is a top view of the transistor 160, FIG. 11(B) is a cross-sectional view between the dashed-dotted line X1-X2 in FIG. 11(A), and FIG. 11(C) is a cross-sectional view between the dashed-dotted line Y1-Y 2 in FIG. 11(A).

[0169] The transistor 160 shown in FIGS. 11(A), (B), and (C) has a different shape of the oxide semiconductor film 112 from the transistor 150 shown above. Specifically, the lower end portion of the oxide semiconductor film 112 included in the transistor 160 is formed inside the upper end portion of the insulating film 110. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the oxide semiconductor film 112. For example, the oxide semiconductor film 112 and the insulating film 110 are processed using the same mask, and the oxide semiconductor film 112 is processed by a wet etching method and the insulating film 110 is processed by a dry etching method, respectively,

[0170] to obtain the above structure.

[0171] Also, by forming the oxide semiconductor film 112 in the above structure, in the oxide semiconductor film 108, ​​Region 108f may be formed. Region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

[0172] Region 108f functions as either a high-resistance region or a low-resistance region. The high-resistance region has the same resistance as the channel region 108i and is a region where the oxide semiconductor film 112 that functions as a gate electrode does not overlap. When region 108f is a high-resistance region, region 108f functions as a so-called offset region. When region 108f functions as an offset region, in order to suppress a decrease in the on-current of transistor 160, region 108f may be set to 1 μm or less in the channel length (L) direction.

[0173] The low-resistance region has a lower resistance than the channel region 108i and a higher resistance than the source region 108s and the drain region 108d. When region 108f is a low-resistance region, region 108f functions as a so-called LDD (Lightly Doped Drain) region. When region 108f functions as an LDD region, the electric field in the drain region can be relaxed, so that fluctuations in the threshold voltage of the transistor due to the electric field in the drain region can be reduced.

[0174] When region 108f is a low-resistance region, for example, hydrogen or nitrogen or both are supplied from the insulating film 116 to region 108f, or impurity elements are added from above the oxide semiconductor film 112 using the insulating film 110 and the oxide semiconductor film 112 as masks, so that the impurities are added to the oxide semiconductor film 108 through the insulating film 110.​​ As a result, region 108f is formed.

[0175] Also, the transistor 150 shown above can also have the same configuration as the transistor 160 by changing the shape of the oxide semiconductor film 112 that functions as the second gate electrode. An example of this case is shown in FIGS. 12(A) and 12(B). FIGS. 12(A) and 12(B) are cross-sectional views of the transistor 160A. FIG. 12(A) is a cross-sectional view between the dashed-dotted line X1-X2 in FIG. 11(A), and FIG. 12(B) is a cross-sectional view between the dashed-dotted line Y1-Y2 in FIG. 11(A). <1-10. Configuration Example 7 of Semiconductor Device>

[0176] Next, a configuration different from the semiconductor device shown in FIGS. 11(A), 11(B), and 11(C) will be described with reference to FIGS. 13(A) and 13(B).

[0177]

[0178]

[0179] ​​​​​​​​​​​​​Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, and the like. Examples of the organic material include photosensitive resin materials such as an acrylic resin or a polyimide resin.

[0180] In FIGS. 13(A) and 13(B), the size of the opening in the insulating film 122 is made smaller than that of the openings 141a and 141b, but it is not limited thereto. For example, it may be the same size as the openings 141a and 141b, or may be larger than the openings 141a and 141b.

[0181] Also, in FIGS. 13(A) and 13(B), a configuration in which the conductive films 120a and 120b are provided on the insulating film 122 is illustrated, but it is not limited thereto. For example, the conductive films 120a and 120b may be provided on the insulating film 118, and the insulating film 122 may be provided on the conductive films 120a and 120b.

[0182] Also, the transistor 160A shown above can have the same configuration as the transistor 160B by providing the insulating film 122. An example of this case is shown in FIGS. 14(A) and 14(B). Note that FIGS. 14(A) and 14(B) are cross-sectional views of the transistor 160C. FIG. 14(A) is a cross-sectional view taken between the dashed-dotted line X1-X2 in FIG. 11(A), and FIG. 14(B) is a cross-sectional view taken between the dashed-dotted line Y1-Y2 in FIG. 11(A).

[0183] <1-11. Manufacturing Method of Semiconductor Device 1> Next, an example of the manufacturing method of the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 16 to 18. FIGS. 16 to 18 are used to explain the manufacturing method of the transistor 100. ​​​​​​​​​​​​​It is a cross-sectional view in the channel length (L) direction and the channel width (W) direction.

[0184] First, an insulating film 104 is formed on a substrate 102, and an oxide semiconductor film is formed on the insulating film 104. Then, by processing the oxide semiconductor film into an island shape, a layer 108_2 is formed ( see Fig. 16(A)).

[0185] As the insulating film 104, it can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition ( PLD) method, a printing method, a coating method, etc. In the present embodiment, as the insulating film 104, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are formed using a PECVD apparatus.

[0186] Also, after forming the insulating film 104, oxygen may be added to the insulating film 104. As the oxygen added to the insulating film 10 4, there are oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. Also, as the addition method, there are an ion doping method, an ion implantation method, a plasma treatment method, etc. Also, after forming a film for suppressing the desorption of oxygen on the insulating film, oxygen may be added to the insulating film 104 through the film. As the film for suppressing the desorption of oxygen described above, indium, zinc, gallium, tin, aluminum,

[0187] chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten, or a metal element selected therefrom, an alloy containing the above-described metal element as a component, an alloy combining the above-described metal elements, a metal nitride having the above-described metal element, a metal oxide having the above-described metal element, a metal oxynitride having the above-described metal element, etc., a conductive material can be used to form it. ​​​​​

[0188] Also, when adding oxygen by plasma treatment, oxygen is excited by microwaves to generate a high-density oxygen plasma, thereby increasing the amount of oxygen added to the insulating film 104. .

[0189] The layer 108_2 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, etc. Note that for the processing of the layer 108_2, after forming a mask on the oxide semiconductor film by a lithography process, a part of the oxide semiconductor film is etched using the mask. Alternatively, an island-shaped layer 108_2 may be directly formed on the insulating film 104 using a printing method.

[0190] When forming an oxide semiconductor film by a sputtering method, a power supply device for generating plasma can be appropriately used, such as an RF power supply device, an AC power supply device, or a DC power supply device. Also, when forming an oxide semiconductor film, the sputtering gas can be appropriately used, such as a noble gas (typically argon ), oxygen, or a mixed gas of a noble gas and oxygen. In the case of a mixed gas of a noble gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0191] Note that when forming an oxide semiconductor film, for example, when using a sputtering method, it is preferable to form the oxide semiconductor film with the substrate temperature being 150°C or higher and 750°C or lower, or 150°C or higher and 450°C or lower, or 200°C or higher and 350°C or lower, in order to enhance crystallinity.

[0192] Note that in this embodiment, as the layer 108_2, a sputtering apparatus is used, and ​​​​​​Using In-Ga-Zn metal oxide (In:Ga:Zn = 4:2 :4.1 [atomic ratio]) as a patterning target, an oxide semiconductor film with a thickness of 30 nm is formed.

[0193] Also, after forming layer 108_2, heat treatment may be performed to dehydrogenate or de hydrate layer 108_2. The temperature of the heat treatment is typically 150°C or higher and less than the substrate distortion point, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0194] The heat treatment can be performed in an inert gas atmosphere containing a noble gas such as helium, neon, argon, xenon, krypton, or nitrogen. Or, after heating in an inert gas atmosphere, it may be heated in an oxygen atmosphere. Note that it is preferable that neither hydrogen nor water is contained in the above inert atmosphere and oxygen atmosphere. The treatment time may be 3 minutes or more and 24 hours or less.

[0195] The heat treatment can use an electric furnace, an RTA device, etc. By using an RTA device, heat treatment can be performed at a temperature equal to or higher than the substrate distortion point for a limited time. Therefore, the heat treatment time can be shortened.

[0196] By forming the oxide semiconductor film while heating or performing heat treatment after forming the oxide semiconductor film, in the oxide semiconductor film, the hydrogen concentration obtained by secondary ion mass spectrometry is 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 or less, 18 3 18 3 5×10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5×10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 Below It can be below.

[0197] Note that in the step of forming the layer 108_2, an oxide semiconductor film having a stacked structure is formed. The oxide semiconductor film having the stacked structure is processed into an island shape to form a layer 108_1 and a layer 108_2. In this way, the transistor 100A described above can be formed.

[0198] Next, the oxide semiconductor film 107_3 and the insulating film 110 are formed over the insulating film 104 and the layer 108_2. _0 is formed (see FIG. 16(B)).

[0199] The oxide semiconductor film 107_3 is formed to cover the side surfaces of the layer 108_2. The oxide semiconductor film 107_3 is formed of the same material and has the same structure as the layer 108_2 described above. It can be formed by the method described above.

[0200] In this embodiment, the oxide semiconductor film 107_3 is formed by a sputtering apparatus. As a sputtering target, In-Ga-Zn metal oxide (In:Ga:Zn = A 5-nm-thick oxide semiconductor film is formed using a 1:1:1.2 (atomic ratio) mixture.

[0201] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film. It can be formed by using a CVD method. In this case, the source gas contains silicon. It is preferable to use a deposition gas and an oxidizing gas. Representative examples of deposition gases containing silicon: Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. , there are oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0202] Further, as the insulating film 110_0, the flow rate of the oxidizing gas is 20 times greater than the flow rate of the depositing gas and less than 100 times, or 40 times or more and 80 times or less, and the pressure in the processing chamber is 100P a or less, or 50 Pa or less. By using the PECVD method, a silicon oxynitride film with a small amount of defects can be formed.

[0203] Further, as the insulating film 110_0, the substrate placed in the evacuated processing chamber of the PECVD apparatus is held at 280°C or higher and 400°C or lower, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is 20 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 250 Pa or lower. Under the condition of supplying high-frequency power to the electrode provided in the processing chamber, a dense silicon oxide film or silicon oxynitride film can be formed.

[0204] Further, the insulating film 110_0 may be formed by using the PECVD method using microwaves. Microwaves refer to the frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature and a small electron energy. Also, when using a PECVD apparatus using microwaves, among the supplied power, the power used to generate plasma, that is, the power used for ionization of molecules, has a high ratio, and the ratio of the power used for electron acceleration is small. Therefore, a plasma with a high density (high-density plasma) can be generated. For this reason, plasma damage to the film-forming surface and the deposited material is small, and an insulating film 110_0 with few defects can be formed.

[0205] Further, the insulating film 110_0 can be formed by using the CVD method using an organic silane gas. It is possible. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4 ), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotet rasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), he xamethyl disilazane (HMDS), triethoxysilane (SiH(OC2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3) and other silicon-containing compounds can be used. By using the CVD method with an organic silane gas, a highly conformal insulating film 110_0 can be formed.

[0206] In this embodiment, as the insulating film 110_0, a silicon oxynitride film with a thickness of 100 nm is formed using a PECVD apparatus.

[0207] Next, an oxide semiconductor film 112_0 is formed on the insulating film 110_0. Note that during the formation of the oxide semiconductor film 112_0, oxygen is added from the oxide semiconductor film 112_0 into the insulating film 110_0 (see FIG. 16(C)).

[0208] As a method for forming the oxide semiconductor film 112_0, a sputtering method is used, and it is preferable to form it in an atmosphere containing oxygen gas. By forming the oxide semiconductor film 112_0 in an atmosphere containing oxygen gas during formation, oxygen can be suitably added into the insulating film 110_0.

[0209] In FIG. 16(C), the oxygen added into the insulating film 110_0 is schematically represented by an arrow. Also, as the oxide semiconductor film 112_0, the same materials as those of the layer 108_2 described above can be used.

[0210] In this embodiment, as the oxide semiconductor film 112_0, a sputtering apparatus is used and In-Ga-Zn metal oxide (In:Ga:Zn = 4:2:4.1 [atomic ratio]) is used as the sputtering target to form an oxide semiconductor film with a thickness of 100 nm.

[0211] Next, a mask 1 40 is formed at a desired position on the oxide semiconductor film 112_0 by a lithography process (see FIG. 16(D)).

[0212] Next, by performing etching from above the mask 140, after processing the oxide semiconductor film 112_0, the insulating film 110_0, and the oxide semiconductor film 107_3, the mask 140 is removed to form an island-shaped oxide semiconductor film 112, an island-shaped insulating film 110, and an island-shaped layer 108_3 (see FIG. 17(A)).

[0213] Note that when forming the layer 108_3, a part of the surface of the layer 108_2 is exposed. The region where a part of the surface of the layer 108 _2 is exposed will later become the source region 108s and the drain region 108 d.

[0214] In this embodiment, the processing of the oxide semiconductor film 112_0, the insulating film 110_0, and the oxide semiconductor film 107_3 is performed using a dry etching method.

[0215] Note that when processing the oxide semiconductor film 112, the insulating film 110, and the layer 108_3, the film thickness of the layer 108_2 in the region where the oxide semiconductor film 112 does not overlap may become thin. Or when processing the oxide semiconductor film 112, the insulating film 110, and the layer 108_3, the film thickness of the insulating film 104 in the region where the layer 108_2 does not overlap may become thin.

[0216] Next, impurity element 1 is added on the insulating film 104, layer 108_2, and oxide semiconductor film 112 (see Fig. 17(B)).

[0217] As methods for adding impurity element 145, there are ion doping method, ion implantation method, plasma treatment method, etc. In the case of the plasma treatment method, plasma is generated in a gas atmosphere containing the impurity element to be added, and by performing plasma treatment, the impurity element can be added . As the apparatus for generating the above plasma, a dry etching apparatus, an ashing apparatus, PECVD apparatus, high-density PECVD apparatus, etc. can be used .

[0218] Note that as the source gas for impurity element 145, one or more of B2H6, PH3, CH4, N2, NH3 , AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, and noble gas (for example argon) can be used. Or, one or more of B2H6, PH 3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 diluted with noble gas can be used . By using one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3 , F2, HF, and H2 diluted with noble gas to add impurity element 145 to layer 108_2 and oxide semiconductor film 112, one or more of noble gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur and chlorine can be added to layer 108_2 and oxide semiconductor film 112 . .

[0219] Or, impurity element 145 is added using noble gas as the source gas, and then B2H6, PH3 , CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and adding one or more of H2 as a source gas to layer 108_2 and the oxide semiconductor film 112 is also acceptable.

[0220] Alternatively, the impurity element 145 may be B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and one or more of H2 as source gases, and then adding a noble gas as a source gas to layer 108_2 and the oxide semiconductor film 112 is also acceptable.

[0221] The addition of the impurity element 145 may be controlled by appropriately setting implantation conditions such as the acceleration voltage and the dose amount. For example, when adding argon by ion implantation, the acceleration voltage may be 10 kV or more and 1 00 kV or less, and the dose amount may be 1×10 13 ions / cm 2 or more and 1×10 16 ions / c m 2 or less, for example, 1×10 14 ions / cm 2 is acceptable. Also, when adding phosphorus ions by ion implantation, the acceleration voltage may be 30 kV, and the dose amount may be 1×10 ions / cm 13 or more and 5×10 2 ions / cm 16 or less, for example, 1×1 2 0 0 15 ions / cm 2 is acceptable.

[0222] In addition, in this embodiment, although the configuration of adding the impurity element 145 after removing the mask 140 has been exemplified, it is not limited thereto. For example, the impurity element 145 may be added while leaving the mask 140.

[0223] ​​Also, in the present embodiment, as the impurity element 145, using a doping device, argon is added to the layer 108_2 and the oxide semiconductor film 112. However, it is not limited thereto, for example, the step of adding the impurity element 145 may not be performed.

[0224] Next, an insulating film 116 is formed on the insulating film 104, the layer 108_2, and the oxide semiconductor film 112. By forming the insulating film 116, the layer 108_2 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. Also, the layer 108_2 not in contact with the insulating film 116 and the layer 108_3 become the channel region 108i. Thereby, an oxide semiconductor film 108 of one aspect of the present invention is formed (see FIG. 17(C)).

[0225] Thus, the oxide semiconductor film 108 has a channel region 108i that overlaps with the oxide semiconductor film 112, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116. The channel region 108i has the layer 108_2 and the layer 108_3 that is in contact with the upper surface of the layer 108_2 and covers the side surface of the layer 108_2 in the channel width direction. It has such a structure.

[0226] As the insulating film 116, it can be formed by selecting the materials described above. In the present embodiment, as the insulating film 116, using a PECVD apparatus, a silicon nitride film with a thickness of 100 nm is formed.

[0227] By using a silicon nitride film as the insulating film 116, the water in the silicon nitride film is in the oxide semiconductor film 112, the source region 108s, and the drain region 108d in contact with the insulating film 116. The element can penetrate into the oxide semiconductor film 112, the source region 108s, and the drain region 108d to increase the carrier density thereof.

[0228] Next, an insulating film 118 is formed on the insulating film 116 (see Fig. 17(D)).

[0229] As the insulating film 118, it can be formed by selecting the materials described above. In this embodiment using a PECVD apparatus, a silicon oxynitride film with a thickness of 300 nm is formed as the insulating film 118.

[0230] Next, after forming a mask at a desired position of the insulating film 118 by a lithography process, a part of the insulating film 118 and the insulating film 116 is etched to form an opening 141a reaching the source region 108s and an opening 141b reaching the drain region 108d (see Fig. 18(A)).

[0231] As a method for etching the insulating film 118 and the insulating film 116, a wet etching method and / or a dry etching method can be appropriately used. In this embodiment, a dry etching method is used to process the insulating film 118 and the insulating film 116.

[0232] Next, a conductive film 120 is formed on the insulating film 118 so as to cover the openings 141a and 141b (see Fig. 18(B)).

[0233] As the conductive film 120, it can be formed by selecting materials that can be used for the conductive films 120a and 120b. In this embodiment, using a sputtering apparatus, a laminated film of a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm is formed as the conductive film 120. ​

[0234] Next, after forming a mask at a desired position on the conductive film 120 by a lithography process, a part of the conductive film 120 is etched to form the conductive films 120a and 120b (see FIG. 18(C)).

[0235] As a method for processing the conductive film 120, a wet etching method and / or a dry etching method can be appropriately used. In this embodiment, the dry etching method is used to process the conductive film 120 to form the conductive films 120a and 120b.

[0236] Through the above steps, the transistor 100 shown in FIG. 1 can be fabricated.

[0237] Note that the films (insulating films, oxide semiconductor films, conductive films, etc.) or layers constituting the transistor 100 can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or an ALD (atomic layer deposition) method. Alternatively, they can be formed by a coating method or a printing method. As the film formation method, a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method is typical, but a thermal CVD method may also be used. As an example of the thermal CVD method, there is a metalorganic

[0238] chemical vapor deposition (MOCVD) method. The thermal CVD method forms a film by setting the inside of the chamber to atmospheric pressure or reduced pressure, simultaneously feeding a source gas and an oxidant into the chamber, reacting them near or on the substrate, and depositing the film on the substrate. Thus, since

[0239] the thermal CVD method is a film formation method that does not generate plasma, it has the advantage that defects are not generated due to plasma damage.In addition, in the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and raw material gases for the reaction are introduced into the chamber for reaction, and film formation is performed by repeating this process. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas together with the raw material gases. For example, two or more types of raw material gases may be sequentially supplied to the chamber. At that time, after the reaction of the first raw material gas, an inert gas is introduced so that the plurality of types of raw material gases are not mixed, and the second raw material gas is introduced. Alternatively, instead of introducing an inert gas, the first raw material gas may be discharged by evacuation, and then the second raw material gas may be introduced. The first raw material gas is adsorbed and reacts on the surface of the substrate to form the first layer, and the second raw material gas introduced later is adsorbed and reacts, so that the second layer is laminated on the first layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction is repeated, precise film thickness adjustment is possible, which is suitable for fabricating fine FETs.

[0240] Thermal CVD methods such as the MOCVD method can form films such as the conductive films, insulating films, and oxide semiconductor films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. The present invention is not limited to these combinations, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0241] ​​​For example, when forming a hafnium oxide film using a film-forming apparatus that utilizes ALD, a solvent and a liquid containing a hafnium precursor (such as hafnium alkoxide, tetrakis(dimethylamido) hafnium (TDMAH, Hf[N(CH3)2]4), or hafnium amide such as tetrakis(ethylmethylamido) hafnium) are vaporized to obtain a source gas, and two types of gases, namely ozone (O3) and an oxidizing agent, are used.

[0242] For example, when forming an aluminum oxide film using a film-forming apparatus that utilizes ALD, a solvent and a liquid containing an aluminum precursor (such as trimethylaluminum (TMA, Al(CH3) 3), etc.) are vaporized to obtain a source gas, and two types of gases, namely H2O as an oxidizing agent, are used. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc.

[0243] For example, when forming a silicon oxide film using a film-forming apparatus that utilizes ALD, hexachlorodisilane is adsorbed onto the film-forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed substance.

[0244] For example, when forming a tungsten film using a film-forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially introduced to form an initial tungsten film, and then WF6 gas and H2 gas are used to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0245] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn- When forming the O film, an In-O layer is formed using In(CH3)3 gas and O3 gas , and then, a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and further, a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer , or a Ga-Zn-O layer may be formed using these gases. Note that instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H.

[0246] <1-12. Fabrication method of semiconductor device 2> Next, an example of the fabrication method of the transistor 160B shown in FIG. 13 will be described with reference to FIGS. 19 to 2 2. FIGS. 19 to 22 are cross-sectional views in the channel length (L) direction and the channel width (W) direction for explaining the fabrication method of the transistor 160B.

[0247] First, a conductive film 106 is formed on the substrate 102. Next, an insulating film 104 is formed on the substrate 102 and the conductive film 106 , and an oxide semiconductor film is formed on the insulating film 104. Then, by processing the oxide semiconductor film into an island shape, a layer 108_2 is formed (see FIG. 19(A)) .

[0248] As the conductive film 106, it can be formed of the same material and in the same manner as the oxide semiconductor film 112 or the conductive films 120a and 120b. In the present embodiment, as the conductive film 106, a tungsten film with a thickness of 100 nm is formed by sputtering.

[0249] In the step of forming the layer 108_2, an oxide semiconductor film of a stacked structure is formed, and the oxide semiconductor film of the stacked structure is processed into an island shape to form the layer 108_1 and the layer 108_2. By doing so, the transistor 160C described above can be formed.

[0250] Next, an oxide semiconductor film 107_3 and an insulating film 110 _0 are formed on the insulating film 104 and the layer 108_2 (see FIG. 19(B)).

[0251] The oxide semiconductor film 107_3 is formed so as to cover the side surface of the layer 108_2. Note that the oxide semiconductor film 107_3 can be formed of the same material and by the same method as the layer 108_2 described above.

[0252] In this embodiment, as the oxide semiconductor film 107_3, a sputtering apparatus is used and an In-Ga-Zn metal oxide (In:Ga:Zn = 1:1:1.2 [atomic ratio]) is used as a sputtering target to form an oxide semiconductor film with a film thickness of 15 nm.

[0253] Next, after forming a mask at a desired position on the insulating film 110_0 by a lithography process, a part of the insulating film 110_0, the oxide semiconductor film 107_3, and the insulating film 104 is etched to form an opening 143 reaching the conductive film 106 (see FIG. 19(C)).

[0254] As a method for forming the opening 143, a wet etching method and / or a dry etching method can be appropriately used. In this embodiment, the dry etching method is used to form the opening 143.

[0255] Next, an oxide semiconductor film 112_0 is formed on the insulating film 110_0 so as to cover the opening 143. At the time of forming the oxide semiconductor film 112_0, oxygen is added from the oxide semiconductor film 112_ 0 into the insulating film 110_0 (see FIG. 19(D)).

[0256] In FIG. 19(D), the oxygen added into the insulating film 110_0 is schematically represented by an arrow. Also, by forming the oxide semiconductor film 112_0 so as to cover the opening 143, the conductive film 106 and the oxide semiconductor film 112_0 are electrically connected.

[0257] Next, a mask 1 40 is formed at a desired position on the oxide semiconductor film 112_0 by a lithography process (see FIG. 20(A)).

[0258] Next, the oxide semiconductor film 112_0 is processed by etching from above the mask 140, to form an island-shaped oxide semiconductor film 112 (see FIG. 20(B)).

[0259] In this embodiment, the wet etching method is used to process the oxide semiconductor film 112_0. Process.

[0260] Subsequently, the insulating film 110_0 and the oxide semiconductor film 107_3 are processed by etching from above the mask 140, to form an island-shaped insulating film 110 and an island-shaped layer 108_3 (see FIG. 20(C)). (See FIG. 20(C)).

[0261] When forming the layer 108_3, a part of the surface of the layer 108_2 is exposed. Layer 108 The region where a part of the surface of _2 is exposed will later become the source region 108s and the drain region 108 d.

[0262] In this embodiment, the processing of the oxide semiconductor film 112_0, the insulating film 110_0, and the oxide semiconductor film 107_3 is performed using a dry etching method.

[0263] Next, after removing the mask 140, an impurity element 145 is added from above the insulating film 104, the layer 108_2, and the oxide semiconductor film 112 (see Fig. 20(D)).

[0264] Note that when adding the impurity element 145, many impurities are added to the region where the surface of the layer 108_2 is exposed (the region that will later become the source region 108s and the drain region 108d). On the other hand, in the region where the oxide semiconductor film 112 of the layer 108_2 does not overlap and the insulating film 110 and the layer 108_3 overlap (the region that will later become the region 108f), the impurity element 145 is added through the insulating film 110 and the layer 108_3, so the amount of the impurity element 145 added is less than that in the source region 108s and the drain region 108d. Also, in this embodiment, as the impurity element 145, argon is added to the layer 108_2 and the oxide semiconductor film 112 using a doping device. However, it is not limited to this,

[0265] for example, the step of adding the impurity element 145 may not be performed. If the step of adding the impurity element 145 is not performed, the region 108f will have the same impurity concentration as the channel region 108i. That is, it is not limited to this. Next, an insulating film 116 is formed on the insulating film 104, the layer 108_2, the insulating film 110, and the oxide semiconductor film 112. Note that by forming the insulating film 116, the layer 108_2 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. Also, the insulating film 11 Note that by forming the insulating film 116, the layer 108_2 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. Also, the insulating film 11

[0266] Next, an insulating film 116 is formed on the insulating film 104, the layer 108_2, the insulating film 110, and the oxide semiconductor film 112. By forming the insulating film 116, the layer in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. Also, the insulating film 11 108_2 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. Also, the insulating film 11 The layer 108_2 that does not contact 6 and the layer 108_3 become the channel region 108i. Accordingly, an oxide semiconductor film 108 according to one embodiment of the present invention is formed (see FIG. 21(A)).

[0267] Thus, the oxide semiconductor film 108 has a channel region 108i that overlaps with the oxide semiconductor film 112, a source region 108s that contacts the insulating film 116, and a drain region 108d that contacts the insulating film 116. The channel region 108i has a layer 108_2 and a layer 108_3 that contacts the upper surface of the layer 108_2 and covers the side surface of the layer 108_2 in the channel width direction, and has such a structure. Note that a region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108

[0268] i and the drain region 108d. Next, an insulating film 118 is formed on the insulating film 116 (see FIG. 21(B)).

[0269] Next, after forming a mask by a lithography process at a desired position of the insulating film 118, a part of the insulating film 118 and the insulating film 116 is etched to form an opening 141a that reaches the source region 108s and an opening 141b that reaches the drain region 108d (see FIG. 21(C)).

[0270] Next, an insulating film 122 is formed on the insulating film 118 (see FIG. 22(A)). Note that the insulating film 122 functions as a planarization insulating film. Further, the insulating film 122 has openings at positions overlapping the opening 141a and the opening 141b.

[0271]

[0272]

[0273] ​​​​​As an embodiment, as the insulating film 122, a photosensitive acrylic resin is applied using a spin coater device, and then a desired region of the acrylic resin is exposed to light, thereby forming an insulating film 122 having openings. Next, a conductive film 120 is formed on the insulating film 122 so as to cover the openings 141a and 141b (see Fig. 22(B)). Next, after forming a mask at a desired position on the conductive film 120 by a lithography process, a part of the conductive film 120 is etched to form conductive films 120a and 120b (see Fig. 22(C)).

[0274] In this embodiment, a dry etching method is used for processing the conductive film 120. Also, when processing the conductive film 120, a part of the upper portion of the insulating film 122 may be removed. By the above steps, the transistor 160B shown in Fig. 13 can be manufactured.

[0275] Note that when manufacturing the above transistor 160B, the insulating film 104, layer 108_2, layer 108_3, insulating film 110_0, oxide semiconductor film 112_0, impurity element 145, insulating film 116, insulating film 118, openings 141a and 141b, and conductive film 120 can be formed by referring to the content described in <1-11. Method for manufacturing semiconductor device 1>. In addition, in this embodiment, an example in which the transistor has an oxide semiconductor film is shown, but one aspect of the present invention is not limited thereto. In one aspect of the present invention, the transistor is an acid By the above steps, the transistor 160B shown in Fig. 13 can be manufactured.

[0276] In this embodiment, a dry etching method is used for processing the conductive film 120. Also, when processing the conductive film 120, a part of the upper portion of the insulating film 122 may be removed. By the above steps, the transistor 160B shown in Fig. 13 can be manufactured.

[0277] By the above steps, the transistor 160B shown in Fig. 13 can be manufactured.

[0278] Note that when manufacturing the above transistor 160B, the insulating film 104, layer 108_2, layer 108_3, insulating film 110_0, oxide semiconductor film 112_0, impurity element 145, insulating film 116, insulating film 118, openings 141a and 141b, and conductive film 120 can be formed by referring to the content described in <1-11. Method for manufacturing semiconductor device 1>. In addition, in this embodiment, an example in which the transistor has an oxide semiconductor film is shown, but one aspect of the present invention is not limited thereto. In one aspect of the present invention, the transistor is an acid In addition, in this embodiment, an example in which the transistor has an oxide semiconductor film is shown, but one aspect of the present invention is not limited thereto. In one aspect of the present invention, the transistor is an acid -11. Method for manufacturing semiconductor device 1> can be formed by referring to the content described therein.

[0279] In addition, in this embodiment, an example in which the transistor has an oxide semiconductor film is shown, but one aspect of the present invention is not limited thereto. In one aspect of the present invention, the transistor is an acid -11. Method for manufacturing semiconductor device 1> can be formed by referring to the content described therein. It is not necessary to have an oxide semiconductor film. As an example, in the channel region of a transistor, in the vicinity of the channel region, the source region, or the drain region, it may be formed of a material containing Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like. In the vicinity of the channel region, the source region, or the drain region, it may be formed of a material containing Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like. In the vicinity of the channel region, the source region, or the drain region, it may be formed of a material containing Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like. In the vicinity of the channel region, the source region, or the drain region, it may be formed of a material containing Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like.

[0280] As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. As described above, the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0281] (Embodiment 2) In this embodiment, the structure of the oxide semiconductor and the like will be described with reference to FIGS. 23 to 27. In this embodiment, the structure of the oxide semiconductor and the like will be described with reference to FIGS. 23 to 27.

[0282] <2-1. Structure of Oxide Semiconductor> Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0283] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS. From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS. From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0284] An amorphous structure is generally in a metastable state where the atomic arrangement is not fixed, has no heterogeneous structure, is isotropic, has a flexible bond angle, has short-range order but no long-range order, etc. It is said that the atomic arrangement is not fixed, the bond angle is flexible, there is short-range order but no long-range order, etc. On the contrary, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Also, an anisotropic oxide semiconductor (for example, having a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor.

[0285] On the other hand, an a-like OS has an unstable structure that is anisotropic but has voids. In terms of being unstable, an a-like OS is physically close to an amorphous oxide semiconductor. In terms of being anisotropic (for example, having a periodic structure in a minute region), an oxide semiconductor cannot be called a completely amorphous oxide semiconductor. In terms of being anisotropic (for example, having a periodic structure in a minute region), an oxide semiconductor cannot be called a completely amorphous oxide semiconductor. On the other hand, an a-like OS has an unstable structure that is anisotropic but has voids (also called voids). In terms of being unstable, an a-like OS is physically close to an amorphous oxide semiconductor. In terms of being unstable, an a-like OS is physically close to an amorphous oxide semiconductor.

[0286] <2-2.CAAC-OS> First, CAAC-OS will be described.

[0287] CAAC-OS is a type of oxide semiconductor having a plurality of c-axis oriented crystal parts (also called pellets). CAAC-OS is a type of oxide semiconductor having a plurality of c-axis oriented crystal parts (also called pellets).

[0288] The case where CAAC-OS is analyzed by X-ray diffraction (XRD) will be described. For example, for CAAC-OS having crystals of InGaZnO4 classified into the space group R-3m, when performing a structure analysis by the out-of-plane method, as shown in Fig. 23(A), a peak appears at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, in CAAC-OS, the crystal has c-axis orientation, and the c-axis is the plane forming the CAAC-OS film (also called the film-forming surface). For example, for CAAC-OS having crystals of InGaZnO4 classified into the space group R-3m, when performing a structure analysis by the out-of-plane method, as shown in Fig. 23(A), a peak appears at around a diffraction angle (2θ) of 31°. For example, for CAAC-OS having crystals of InGaZnO4 classified into the space group R-3m, when performing a structure analysis by the out-of-plane method, as shown in Fig. 23(A), a peak appears at around a diffraction angle (2θ) of 31°. For example, for CAAC-OS having crystals of InGaZnO4 classified into the space group R-3m, when performing a structure analysis by the out-of-plane method, as shown in Fig. 23(A), a peak appears at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, in CAAC-OS, the crystal has c-axis orientation, and the c-axis is the plane forming the CAAC-OS film (also called the film-forming surface). Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, in CAAC-OS, the crystal has c-axis orientation, and the c-axis is the plane forming the CAAC-OS film (also called the film-forming surface). That is, it can be confirmed that it is oriented in a direction substantially perpendicular to the upper surface. In addition to the peak near 2θ of 31 °, a peak may also appear near 2θ of 36°. The peak near 2θ of 36° is due to the crystal structure classified into the space group Fd-3m. Therefore, CAA C-OS preferably does not show this peak.

[0289] On the other hand, for CAAC-OS, when performing structural analysis by the in-pl ane method of irradiating X-rays from a direction parallel to the surface to be formed, a peak appears near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. Then, fixing 2θ near 56° and analyzing (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in Fig. 23(B), no distinct peak appears. On the other hand, for single crystal InGa ZnO4, when performing φ scan with 2θ fixed near 56°, as shown in Fig. 23(C), six peaks attributed to crystal planes equivalent to the (110) plane are observed. Therefore, from the structural analysis using XRD, it can be confirmed that CAAC-OS has irregular orientations of the a-axis and b-axis.

[0290] Next, CAAC-OS analyzed by electron diffraction will be described. For example, for CAAC-OS having a crystal of InGa ZnO4, when irradiating an electron beam with a probe diameter of 300 nm parallel to the surface to be formed of CAAC-OS, a diffraction pattern as shown in Fig. 23(D) (also referred to as a limited-field electron diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO4 crystal. Therefore, also by electron diffraction, it can be seen that the pellets included in CAAC-OS have c-axis orientation, and the c-axis is the surface to be formed. ​ It can be seen that it is oriented in a direction substantially perpendicular to the plane or the upper surface. On the other hand, for the same sample, when an electron beam with a probe diameter of 300 nm is incident perpendicularly to the sample surface , the diffraction pattern is shown in Fig. 23(E ). From Fig. 23(E), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen that the a-axis and b-axis of the pellets contained in CAAC-OS have no orientation by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that in Fig. 23(E) , the first ring is considered to be due to the (010) plane and (100) plane of the InGaZnO4 crystal etc. Also, the second ring in Fig. 23(E) is considered to be due to the (110) plane etc. .

[0291] Also, by a transmission electron microscope (TEM: Transmission Electron M icroscope), when observing a composite image of a bright-field image and a diffraction pattern of CAAC-OS (also called a high-resolution TEM image).), a plurality of pellets can be confirmed . On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also called grain boundary ), may not be clearly confirmed. Therefore, it can be said that in CAAC C-OS, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0292] Fig. 24(A) shows a high-resolution TEM image of the cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical A berration Corrector) function was used. The high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image is For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0293] From FIG. 24(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. The surface on which the C-OS film is formed is uneven, and the surface on which the CAAC-OS film is formed or the top surface is uneven. It becomes parallel.

[0294] In addition, Fig. 24(B) and Fig. 24(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the C-OS surface. 24(B) and 24(C), respectively. First, the processing method of FIG. 24(B) is Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the acquired FFT image, the origin is used as the reference point, and the -1 From 5.0 nm -1 The range between Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT : Inverse Fast Fourier Transform) processing is used to The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic components from the Cs-corrected high-resolution TEM image, and shows the lattice array.

[0295] In Fig. 24(D), the disordered portions of the lattice array are indicated by broken lines. The region surrounded by the broken lines is one pellet. And the locations indicated by the broken lines are the connection parts between pellets. Since the broken lines are hexagonal, it can be seen that the pellets are hexagonal. Note that the shape of the pellets is not always a regular hexagon and is often an irregular hexagon.

[0296] In Fig. 24(E), the area between the aligned region of the lattice array and another aligned region of the lattice array is indicated by a dotted line. Even in the vicinity of the dotted line, no distinct grain boundary can be confirmed. When connecting the surrounding lattice points with the lattice points in the vicinity of the dotted line, a distorted hexagon can be formed. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice array. This is presumably because CAAC-OS can tolerate strain due to the fact that the atomic arrangement is not dense in the a-b plane direction and the interatomic bond distance changes when a metal element substitutes, etc.

[0297] As shown above, CAAC-OS has c-axis orientation and, in the a-b plane direction, a plurality of pellets (nanocrystals) are connected, forming a crystal structure with strain. Therefore, CAAC-OS can also be referred to as an oxide semiconductor having CAA crystal (c-axis-aligned a-b-p lane-anchored crystal).

[0298] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of the oxide semiconductor depends on the impurities ​​​​​​Since it may decrease due to mixing or defect generation, conversely, CAAC-O S can be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies).

[0299] Note that impurities are elements other than the main component of the oxide semiconductor, and include hydrogen, carbon, silicon, transition metals For example, elements with a stronger bonding force with oxygen than the metal elements constituting the oxide semiconductor, such as silicon, can take oxygen from the oxide semiconductor and disrupt the atomic arrangement of the oxide semiconductor, becoming a factor in reducing crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so they disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing crystallinity.

[0300] When the oxide semiconductor has impurities or defects, its characteristics may vary depending on light, heat, etc. For example, impurities contained in the oxide semiconductor may become carrier traps or carrier generation sources. For example, oxygen deficiencies in the oxide semiconductor may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0301] CAAC-OS with few impurities and oxygen deficiencies is an oxide semiconductor with a low carrier density Specifically, less than 8×10 11 per cm 3 preferably less than 1×10 11 / cm 3 and more preferably less than 1×10 per cm 10 less than 1×10 3 per cm -9 and can be an oxide semiconductor with a carrier density of 1×10 3 or more. Such an oxide semiconductor can be made into a high-purity vacuum ​​It is called a highly pure or substantially highly pure genuine oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect levels. That is, it can be said that it is an oxide semiconductor having stable characteristics.

[0302] <2-3.nc-OS> Next, nc-OS will be described.

[0303] A case where nc-OS is analyzed by XRD will be described. For example, when performing a structural analysis on nc-OS using the out-of-plane method, no peak indicating orientation appears. That is, the crystal of nc-OS has no orientation.

[0304] Also, for example, when a thin slice of nc-OS having a crystal of InGaZnO4 is thinned and an electron beam with a probe diameter of 50 nm is incident parallel to the formation surface on a region with a thickness of 34 nm, a ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in FIG. 25(A) is observed. Also, the diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample is shown in FIG. 25(B). From FIG. 25(B), a plurality of spots are observed within the ring-shaped region. Therefore, the order of nc-OS is not confirmed when an electron beam with a probe diameter of 50 nm is incident, but the order is confirmed when an electron beam with a probe diameter of 1 nm is incident.

[0305] Also, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, as shown in FIG. 25(C), an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape may be observed. Therefore, in the range where the thickness is less than 10 nm, the order of nc-OS It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0306] FIG. 25(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). o crystalline oxide semiconductor) For example, in the case of nc-OS, the grain boundaries are often not clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be referred to as a pellet.

[0307] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0308] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , or an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

[0309] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore , the density of defect energy levels in nc-OS is lower than that in a-like OS and amorphous oxide semiconductors . However, nc-OS does not show regularity in crystal orientation among different pellets. Therefore , the density of defect energy levels in nc-OS is higher than that in CAAC-OS

[0310] <2-4.a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors .

[0311] Fig. 26 shows a high-resolution cross-sectional TEM image of a-like OS. Here, Fig. 26(A) is the high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Fig. 26( B) is the high-resolution cross-sectional TEM image of a-like OS after electron irradiation at 4.3×10 8 e - / nm 2 of electrons (e - ). From Fig. 26(A) and Fig. 26(B), it can be seen that in a-like OS, stripe-like bright regions extending in the longitudinal direction are observed from the start of electron irradiation . Also, it can be seen that the shape of the bright regions changes after electron irradiation. Note that the bright regions are presumed to be loose or low-density regions . Since it has looseness, a-like OS has an unstable structure. In the following, a-lik .

[0312] Because it has looseness, a-like OS has an unstable structure. In the following, a-lik The e-OS shows a structure that is less stable compared to CAAC-OS and nc-OS, therefore, showing the change in structure due to electron irradiation.

[0313] Prepare a-like OS, nc-OS, and CAAC-OS as samples. Any of the samples is In-Ga-Zn oxide.

[0314] First, obtain a high-resolution cross-sectional TEM image of each sample. From the high-resolution cross-sectional TEM image, each sample has a crystalline part.

[0315] Note that the unit cell of the InGaZnO4 crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers stacked in the c-axis direction in a layered structure. It is known that the distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also called the d-value). From crystal structure analysis, the value is determined to be 0.29 nm. Therefore, in the following, a location where the lattice fringe spacing is between 0.28 nm and 0.30 nm is regarded as the crystalline part of InGaZnO4. Note that the lattice fringes correspond to the a-b plane of the InGaZnO4 crystal.

[0316] Figure 27 is an example of investigating the average size of the crystalline parts (from 22 to 30 locations) of each sample. Note that the length of the lattice fringes described above is used as the size of the crystalline part. From Figure 27, it can be seen that the crystalline part of a-like OS increases in size according to the cumulative irradiation dose of electrons involved in obtaining the TEM image, etc. From Figure 27, at the initial stage of observation by TEM, the crystalline part (also called the initial nucleus) with a size of about 1.2 nm becomes - when the cumulative irradiation dose of electrons (e 8 e - / nm 2 ​It can be seen that it has grown to a size of about 1.9 nm. On the other hand, n nc-OS and CAAC-OS show no change in the size of the crystalline part within the range where the cumulative electron irradiation dose is from the start of electron irradiation to 4.2×10 8 e - / nm 2 up to. As shown in Fig. 27 it can be seen that regardless of the cumulative electron irradiation dose, the sizes of the crystalline parts of nc-OS and CAAC-OS are about 1.3 nm and about 1.8 nm respectively. Note that the electron beam irradiation and TEM observation were carried out using Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7×10 5 e - / (nm 2 ·s), and the diameter of the irradiation area was 230 nm.

[0317] Thus, crystal growth of a-like OS can be observed by electron irradiation in some cases. On the other hand, nc-OS and CAAC-OS show almost no crystal growth by electron irradiation. That is, it can be seen that a-like OS has a less stable structure compared to nc-OS and CAAC-OS.

[0318] In addition, because it has looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal with the same composition. An oxide semiconductor with a density less than 78% of that of a single crystal is difficult to form a film itself.

[0319] ​​​​​​​​For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 . Thus, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0320] When there is no single crystal of the same composition, the density corresponding to the single crystal in the desired composition can be estimated by combining single crystals with different compositions at an arbitrary ratio. The density corresponding to the single crystal of the desired composition may be estimated using the weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures, each having various characteristics. In addition, the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0321] As described above, the configurations shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and used. In addition, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0322] As described above, the configurations shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and used. .

[0323] (Embodiment 3) In the present embodiment, regarding the display device having the transistor exemplified in the previous embodiment an example will be described below with reference to FIGS. 28 to 30.

[0324] FIG. 28 is a top view showing an example of the display device. The display device 700 shown in FIG. 28 includes a pixel portion 702 provided on a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701, a sealing material 712 disposed so as to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealing material 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in FIG. 28, a display element is provided between the first substrate 701 and the second substrate 705.

[0325] Further, the display device 700 has an FPC terminal portion 708 (FPC: Flexible printed circuit) that is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealing material 712 on the first substrate 701. Also, an FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Further, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708​​ Signal lines 710 are each connected to 708. Various signals and the like supplied by FPC 716 are given to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 via the signal lines 710.

[0326] Also, a plurality of gate driver circuit portions 706 may be provided in the display device 700. Further, as the display device 700, an example is shown in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702, but the configuration is not limited to this. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit or a gate driver circuit or the like is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. Note that the connection method of the separately formed driving circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

[0327] Further, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 have a plurality of transistors, and the transistors of one aspect of the present invention, which are semiconductor devices, can be applied.

[0328] Also, the display device 700 can have various elements. As an example of the element, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element), organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink elements, electrophoresis elements, electro-wetting elements, plasma displays (PDPs), MEMS (micro-electro -mechanical systems) displays (e.g., grating light valves (GLVs), digital micromirror devices (DMDs), digital microshutters (D MS) elements, interference modulation (IMOD) elements, etc.), piezoelectric laminate displays, etc.

[0329] Also, as an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron emitting element, there is a field emission display (FE D) or an SED-type flat panel display (SED: Surface-conductio n Electron-emitter Display), etc. As an example of a display device using a liquid crystal element there is a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal disp lay), etc. As an example of a display device using an electronic ink element or an electrophoresis element, there is electronic paper, etc. Note that when realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may function as reflective electrodes. For example, part or all of the pixel electrodes may have aluminum, silver, etc. Further, in that case, it is also possible to provide a memory circuit such as SRAM under the reflective electrode. This can further reduce power consumption. ​

[0330] Note that, as the display method in the display device 700, a progressive method, an interlace method, etc. can be used. Further, as color elements to be controlled by pixels when performing color display, it is not limited to the three colors of RGB (where R represents red, G represents green, and B represents blue). For example, it may be configured from four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, like a pentile arrangement, one color element is constituted by two of RGB, and different two colors may be selected and configured by the color elements. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be added to RGB. Note that the size of the display area may be different for each dot of the color elements. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device.

[0331] Further, in order to perform full-color display of the display device by using white light emission (W) for a backlight (such as an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, etc.), a coloring layer (also referred to as a color filter.) may be used. The coloring layer can be used by appropriately combining, for example, red (R), green (G), blue (B ), yellow (Y), etc. By using the coloring layer, the color reproducibility can be made higher than in the case where the coloring layer is not used. At this time, by arranging a region having the coloring layer and a region not having the coloring layer, the white light in the region not having the coloring layer may be directly used for display. By arranging a region not having the coloring layer in part, when performing bright display, the decrease in luminance due to the coloring layer can be reduced, and the power consumption may be reduced When performing full-color display using optical elements, R, G, B, Y, and W may be emitted from elements having their respective emission colors. By using a self-luminous element, it may be possible to further reduce power consumption compared to the case where a coloring layer is used.

[0332] In addition, as a color conversion method, in addition to the method of converting a part of the light emitted from the above-mentioned white light through a color filter into red, green, and blue (color filter method), a method of using red, green, and blue light emissions respectively (3-color method), or a method of converting a part of the light emitted from blue light emission into red or green (color conversion method, quantum dot method) may be applied.

[0333] In the present embodiment, a configuration using a liquid crystal element and an EL element as display elements will be described with reference to FIGS. 29 and 30. Note that FIG. 29 is a cross-sectional view taken along the dashed-dotted line Q-R shown in FIG. 28, and is a configuration using a liquid crystal element as a display element. FIG. 30 is also a cross-sectional view taken along the dashed-dotted line Q-R shown in FIG. 28, and is a configuration using an EL element as a display element.

[0334] First, the common parts shown in FIGS. 29 and 30 will be described first, and then the different parts will be described below.

[0335] <3-1. Explanation Regarding Common Parts of Display Device> The display device 700 shown in FIGS. 29 and 30 includes a routing wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The routing wiring portion 711 includes signal lines 710. The pixel portion 702 includes a transistor 750 and a capacitor element 790. The source driver circuit portion 704 includes a transistor 752. ​

[0336] Transistors 750 and 752 have the same configuration as transistor 100 shown above. Note that for the configurations of transistors 750 and 752, other transistors shown in the previous embodiment may be used.

[0337] The transistors used in this embodiment have an oxide semiconductor film with high purity and suppression of the formation of oxygen vacancies. The transistor can reduce the off-current. Therefore, the holding time of electrical signals such as image signals can be lengthened, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, resulting in an effect of suppressing power consumption.

[0338] Also, the transistors used in this embodiment can obtain a relatively high field-effect mobility, so they can be driven at high speed. For example, by using such a high-speed drivable transistor in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed on the same substrate. That is, there is no need to separately use a semiconductor device formed by a silicon wafer or the like, so the number of parts of the semiconductor device can be reduced. Also, in the pixel portion, by using a transistor that can be driven at high speed, a high-quality image can be provided.

[0339] The capacitive element 790 is formed through a process of processing an oxide semiconductor film formed in the same process as the first oxide semiconductor film that transistor 750 has, and a lower electrode is formed. The conductive film that functions as the source electrode and the drain electrode that transistor 75 0 has is formed in the same process, and the conductive film is formed. It has an upper electrode formed through a process of processing an electrofilm, and a lower electrode and the upper electrode Between them, an insulating film that functions as the second insulating film of the transistor 750 and a third An insulating film that functions as an insulating film are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric is sandwiched between a pair of electrodes

[0340] Also, in FIGS. 29 and 30, a planarization insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitor element 790.

[0341] As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin , benzocyclobutene resin, polyamide resin, epoxy resin, etc. can be used. Note that the planarization insulating film 770 may be formed by laminating a plurality of insulating films formed of these materials. Also, a configuration in which the planarization insulating film 770 is not provided may be adopted.

[0342] Also, the signal line 710 is formed through the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Note that the signal line 710 is a conductive film formed through a process different from that of the source electrode and the drain electrode of the transistors 750 and 752. For example, an oxide semiconductor film formed through the same process as the oxide semiconductor film that functions as a gate electrode may be used. When a material containing copper element is used as the signal line 710, for example, signal delay due to wire resistance is small, and display on a large screen is possible.

[0343] Also, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71 ​​​​​​​​It has 6. The connection electrode 760 is formed through the same process as the conductive film that functions as the source electrode and drain electrode of the transistors 750 and 752. Also, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780. Moreover, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Also, as the first substrate 701 and the second substrate 705, a flexible substrate may be used. Examples of the flexible substrate include a plastic substrate and the like.

[0344] Between the first substrate 701 and the second substrate 705, a structure 778 is provided. The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure 778.

[0345] On the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the colored film 736 are provided.

[0346]

[0347] <3-2. Configuration example of a display device using a liquid crystal element> The display device 700 shown in FIG. 29 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 shown in FIG. 29 has a conductive film ​​​​​​​​​​​​The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0348] The conductive film 772 serves as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. The liquid crystal display device 730 is a so-called reflective color liquid crystal display device, which reflects the light and displays it through the colored film 736.

[0349] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0350] In the display device 700 shown in FIG. 29, the planarization insulating film 770 of the pixel section 702 The unevenness is provided in a part. For example, the flattening insulating film 770 is made of a resin film. The surface of the resin film may be provided with irregularities to form the reflecting electrode. The conductive film 772 is formed along the above-mentioned unevenness. When the light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. It is possible to improve the performance.

[0351] The display device 700 shown in FIG. 29 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above-mentioned. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0352] Although not shown in FIG. 29, the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776 In addition, although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Crites, sidelights, etc. may also be used.

[0353] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0354] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The formed product is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so alignment treatment is unnecessary. Also, since an alignment film does not need to be provided, rubbing treatment is also unnecessary, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. In addition, the liquid crystal material exhibiting a blue phase has little viewing angle dependence. Also, when using a liquid crystal element as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB (Optical

[0355] Compensated Birefringence) mode, FLC (Ferroe lectric Liquid Crystal) mode, AFLC (AntiFerr oelectric Liquid Crystal) mode, etc. can be used.

[0356] Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include, but are not limited to, MVA (Multi-Domain Vertical Alignment ) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0357] <3-3. Display device using a light emitting element> The display device 700 shown in FIG. 30 has a light-emitting element 782. The light-emitting element 782 has a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 30 can display an image by the EL layer 786 included in the light-emitting element 782 emitting light.

[0358] Also, the conductive film 784 is connected to a conductive film that functions as a source electrode or a drain electrode included in the transistor 750. The conductive film 784 is formed on the planarization insulating film 770 and functions as a pixel electrode, that is, one of the electrodes of the display element. As the conductive film 784, a conductive film that is transmissive to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is transmissive to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film that is reflective to visible light, for example, a material containing aluminum or silver may be used.

[0359] Also, in the display device 700 shown in FIG. 30, an insulating film 730 is provided on the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers a part of the conductive film 784. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency and transmits the light emitted by the EL layer 786. Note that in this embodiment, the top emission structure is exemplified, but the present invention is not limited to this. For example, the present invention can also be applied to a bottom emission structure that emits light from the side of the conductive film 784 or a dual emission structure that emits light from both the conductive film 784 and the conductive film 788.

[0360] ​​​​​Further, a colored film 736 is provided at a position overlapping with the light-emitting element 782, and overlaps with the insulating film 730 A light-shielding film 738 is provided at a position where it overlaps, the wiring routing portion 711, and the source driver circuit portion 704. Also, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Also, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In FIG. 30 the configuration of providing the colored film 736 is illustrated in the display device 700, but this is not limited thereto. For example, in the case of forming the EL layer 786 by painting, a configuration in which the colored film 736 is not provided may be used.

[0361] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0362] (Embodiment 4) In this embodiment, an example of a circuit configuration of a semiconductor device that can retain stored content even when power is not supplied and has no limitation on the number of write cycles will be described with reference to FIG. 31.

[0363] <4-1. Circuit Configuration> FIG. 31 is a diagram for explaining the circuit configuration of a semiconductor device. In FIG. 31, the first wiring ( 1st Line) is electrically connected to one of the source electrode or the drain electrode of the p-type transistor 1280a. Also, the other of the source electrode or the drain electrode of the p-type transistor 1280a is electrically connected to one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the other of the source electrode or the drain electrode of the n-type transistor 1280b is electrically connected to one of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the other of the source electrode or the drain electrode of the n-type transistor 1280c is electrically connected to one of the source electrode or the drain electrode of the n-type transistor 1280c.

[0364] Also, the second wiring (2nd Line) is electrically connected to one of the source electrode or the drain electrode of the transistor 1282. Also, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitor element 1281, and the gate electrode of the n-type transistor 1280c are electrically connected. Also, the second wiring (2nd Line) is electrically connected to one of the source electrode or the drain electrode of the transistor 1282. Also, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitor element 1281, and the gate electrode of the n-type transistor 1280c are electrically connected. Also, the second wiring (2nd Line) is electrically connected to one of the source electrode or the drain electrode of the transistor 1282. Also, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitor element 1281, and the gate electrode of the n-type transistor 1280c are electrically connected. Also, the second wiring (2nd Line) is electrically connected to one of the source electrode or the drain electrode of the transistor 1282. Also, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitor element 1281, and the gate electrode of the n-type transistor 1280c are electrically connected.

[0365] Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b. Also, the third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. Also, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. Also, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor element 1281 and the other of the source electrode or the drain electrode of the n-type transistor 1280c. Also, the sixth wiring (6th Line) is electrically connected to the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b.

[0366] Note that the transistor 1282 can be formed of an oxide semiconductor (OS: Oxide Semiconductor). Therefore, in FIG. 31, the symbol "OS" is appended to the transistor 1282. Note that the transistor 1282 may be formed of a material other than the oxide semiconductor. Note that the transistor 1282 can be formed of an oxide semiconductor (OS: Oxide Semiconductor). Therefore, in FIG. 31, the symbol "OS" is appended to the transistor 1282. Note that the transistor 1282 may be formed of a material other than the oxide semiconductor. Note that the transistor 1282 can be formed of an oxide semiconductor (OS: Oxide Semiconductor). Therefore, in FIG. 31, the symbol "OS" is appended to the transistor 1282. Note that the transistor 1282 may be formed of a material other than the oxide semiconductor. Note that the transistor 1282 can be formed of an oxide semiconductor (OS: Oxide Semiconductor). Therefore, in FIG. 31, the symbol "OS" is appended to the transistor 1282. Note that the transistor 1282 may be formed of a material other than the oxide semiconductor.

[0367] Also, in FIG. 31, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitor element 1281, and the gate electrode of the n-type transistor 1280c Also, in FIG. 31, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitor element 1281, and the gate electrode of the n-type transistor 1280c A floating node (FN) is appended to the connection point. When the transistor 1282 is turned off, the potential applied to the floating node, one of the electrodes of the capacitive element 1281, and the gate electrode of the n -type transistor 1280c can be retained.

[0368] In the circuit configuration shown in FIG. 31, by taking advantage of the feature that the potential of the gate electrode of the n-type transistor 1280c can be retained, writing, retention, and reading of information can be performed as follows.

[0369] <4-2. Writing and Retention of Information> First, writing and retention of information will be described. The potential of the fourth wiring is set to a potential at which the transistor 1282 is turned on, and the transistor 1282 is turned on. As a result, the potential of the second wiring is applied to the gate electrode of the n-type transistor 1280c and the capacitive element 12 81. That is, a predetermined charge is applied to the gate electrode of the n-type transistor 1280c (writing). Thereafter, the potential of the fourth wiring is set to a potential at which the transistor 1282 is turned off, and the transistor 1282 is turned off. Thereby, the charge applied to the gate electrode of the n-type transistor 1280c is retained (retention). Since the off-current of the transistor 1282 is extremely small, the charge on the gate electrode of the n-type transistor 1280c is retained for a long time.

[0370] Since the off-current of the transistor 1282 is extremely small, the charge on the gate electrode of the n-type transistor 1280c is retained for a long time.

[0371] <4-3. Reading of Information> Next, reading of information will be described. When the potential of the third wiring is set to a Low-level potential, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. ​​​​It becomes the state. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, when the potential of the third wiring is set to the High-level potential, the p-type transistor 1280a turns off, and the n type transistor 1280b turns on. At this time, according to the amount of charge held in the floating node (FN), the sixth wiring takes different potentials. Therefore, by looking at the potential of the sixth wiring, the held information can be read out (read). charge held in the floating node (FN), the sixth wiring takes different potentials. Therefore, by looking at the potential of the sixth wiring, the held information can be read out (read). charge held in the floating node (FN), the sixth wiring takes different potentials. Therefore, by looking at the potential of the sixth wiring, the held information can be read out (read).

[0372] Also, since the transistor 1282 uses an oxide semiconductor for the channel formation region, it is a transistor with an extremely small off-current. The off-current of the transistor 1282 using an oxide semiconductor is an off-current of 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charge accumulated in the floating node (FN) due to the leakage of the transistor 1282. That is, by using the transistor 1282 using an oxide semiconductor, it is possible to realize a non-volatile memory circuit capable of holding information without power supply. an off-current of 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charge accumulated in the floating node (FN) due to the leakage of the transistor 1282. That is, by using the transistor 1282 using an oxide semiconductor, it is possible to realize a non-volatile memory circuit capable of holding information without power supply. an off-current of 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charge accumulated in the floating node (FN) due to the leakage of the transistor 1282. That is, by using the transistor 1282 using an oxide semiconductor, it is possible to realize a non-volatile memory circuit capable of holding information without power supply. an off-current of 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charge accumulated in the floating node (FN) due to the leakage of the transistor 1282. That is, by using the transistor 1282 using an oxide semiconductor, it is possible to realize a non-volatile memory circuit capable of holding information without power supply. an off-current of 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charge accumulated in the floating node (FN) due to the leakage of the transistor 1282. That is, by using the transistor 1282 using an oxide semiconductor, it is possible to realize a non-volatile memory circuit capable of holding information without power supply. an off-current of 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like. Therefore, it is possible to ignore the disappearance of the charge accumulated in the floating node (FN) due to the leakage of the transistor 1282. That is, by using the transistor 1282 using an oxide semiconductor, it is possible to realize a non-volatile memory circuit capable of holding information without power supply.

[0373] Also, by using such a circuit configuration for a semiconductor device in a memory device such as a register or a cache memory, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage. Also, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire memory device or one or more logic circuits constituting the memory device, the power supply can be stopped even for a short time in the standby state, so that the power consumption can be suppressed. Also, by using such a circuit configuration for a semiconductor device in a memory device such as a register or a cache memory, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage. Also, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire memory device or one or more logic circuits constituting the memory device, the power supply can be stopped even for a short time in the standby state, so that the power consumption can be suppressed. Also, by using such a circuit configuration for a semiconductor device in a memory device such as a register or a cache memory, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage. Also, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire memory device or one or more logic circuits constituting the memory device, the power supply can be stopped even for a short time in the standby state, so that the power consumption can be suppressed. Also, by using such a circuit configuration for a semiconductor device in a memory device such as a register or a cache memory, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage. Also, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire memory device or one or more logic circuits constituting the memory device, the power supply can be stopped even for a short time in the standby state, so that the power consumption can be suppressed. Also, by using such a circuit configuration for a semiconductor device in a memory device such as a register or a cache memory, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage. Also, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire memory device or one or more logic circuits constituting the memory device, the power supply can be stopped even for a short time in the standby state, so that the power consumption can be suppressed. Also, by using such a circuit configuration for a semiconductor device in a memory device such as a register or a cache memory, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage. Also, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire memory device or one or more logic circuits constituting the memory device, the power supply can be stopped even for a short time in the standby state, so that the power consumption can be suppressed.

[0374] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0375] (Embodiment 5) In this embodiment, the configuration of a pixel circuit that can be used in a semiconductor device according to one aspect of the present invention will be described below with reference to FIG. 32(A).

[0376] <5-1. Configuration of Pixel Circuit> FIG. 32(A) is a diagram for explaining the configuration of a pixel circuit. The circuit shown in FIG. 32(A) is a photoelectric conversion element 1360, transistor 1351, transistor 1352, transistor 13 53, and transistor 1354.

[0377] The anode of the photoelectric conversion element 1360 is connected to the wiring 1316, and the cathode is connected to either the source electrode or the drain electrode of the transistor 1351. The other of the source electrode or the drain electrode of the transistor 1351 is connected to the charge storage section (FD), and the gate electrode is connected to the wiring 1312 (TX). One of the source electrode or the drain electrode of the transistor 1352 is connected to the wiring 1314 (GND), and the other of the source electrode or the drain electrode is connected to either the source electrode or the drain electrode of the transistor 1354, and the gate electrode is connected to the charge storage section (FD). One of the source electrode or the drain electrode of the transistor 1353 is connected to the charge storage section (FD), and the other of the source electrode or the drain electrode is connected to the wiring 1317, and the gate electrode is connected to the wiring 1311 (RS). The other of the source electrode or the drain electrode of the transistor 1354 is connected to the wiring 1315 (OUT), and the gate is connected to The auto electrode is connected to wiring 1313 (SE). All the above connections are electrical connections. It shall be.

[0378] In addition, potentials such as GND, VSS, and VDD may be supplied to wiring 1314. Here, the potential and voltage are relative. Therefore, the magnitude of the GND potential is not necessarily 0 volts. It shall be. It is not necessarily 0 volts.

[0379] The photoelectric conversion element 1360 is a light receiving element and has a function of generating a current corresponding to the light incident on the pixel circuit. The transistor 1353 has a function of controlling the charge accumulation in the charge accumulation section (FD) by the photoelectric conversion element 1360. The transistor 1354 has a function of outputting a signal corresponding to the potential of the charge accumulation section (FD). The transistor 1352 has a function of resetting the potential of the charge accumulation section (FD). The transistor 1352 has a function of controlling the selection of the pixel circuit at the time of reading. The transistor 1353 has a function of controlling the charge accumulation in the charge accumulation section (FD) by the photoelectric conversion element 1360. The transistor 1354 has a function of outputting a signal corresponding to the potential of the charge accumulation section (FD). The transistor 1352 has a function of resetting the potential of the charge accumulation section (FD). The transistor 1352 has a function of controlling the selection of the pixel circuit at the time of reading. It shall be.

[0380] In addition, the charge accumulation section (FD) is a charge holding node and holds charges that change according to the amount of light received by the photoelectric conversion element 1360. It holds charges that change according to the amount of light received by the photoelectric conversion element 1360.

[0381] In addition, the transistor 1352 and the transistor 1354 may be connected in series between the wiring 1315 and the wiring 1314. Therefore, they may be arranged in the order of wiring 1314, transistor 1352, transistor 1354, wiring 1315, or in the order of wiring 1314, transistor 1354, transistor 1352, wiring 1315. Therefore, they may be arranged in the order of wiring 1314, transistor 1352, transistor 1354, wiring 1315, or in the order of wiring 1314, transistor 1354, transistor 1352, wiring 1315. They may be arranged in the order of wiring 1314, transistor 1352, transistor 1354, wiring 1315, or in the order of wiring 1314, transistor 1354, transistor 1352, wiring 1315. It shall be.

[0382] The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. It has. Wiring 1312 (TX) functions as a signal line for controlling transistor 1351. Wiring 1313 (SE) functions as a signal line for controlling transistor 1354. Wiring 1314 (GND) functions as a signal line for setting a reference potential (e.g., GND). Wiring 1315 (OUT) functions as a signal line for reading out the signal output from transistor 1352. Wiring 1316 is a signal line for outputting charges from the charge accumulation section (FD) to the photoelectric conversion element 1360 via the photoelectric conversion element 1360, and is a low potential line in the circuit of FIG. 32(A). Further, wiring 1317 functions as a signal line for resetting the potential of the charge accumulation section (FD), and is a high potential line in the circuit of FIG. 32(A). It has a function as a signal line for outputting charges from the charge accumulation section (FD) to the photoelectric conversion element 1360 via the photoelectric conversion element 1360, and is a low potential line in the circuit of FIG. 32(A). Wiring 1316 has a function as a signal line for outputting charges from the charge accumulation section (FD) to the photoelectric conversion element 1360 via the photoelectric conversion element 1360, and is a low potential line in the circuit of FIG. 32(A). Also, wiring 1317 has a function as a signal line for resetting the potential of the charge accumulation section (FD), and is a high potential line in the circuit of FIG. 32(A). It has a function as a signal line for resetting the potential of the charge accumulation section (FD), and is a high potential line in the circuit of FIG. 32(A). In the circuit of FIG. 32(A), it is a high potential line.

[0383] Next, the configuration of each element shown in FIG. 32(A) will be described.

[0384] <5-2. Photoelectric conversion element> As the photoelectric conversion element 1360, an element having selenium or a compound containing selenium (hereinafter referred to as a selenium-based material), or an element having silicon (for example, an element in which a pin-type junction is formed) can be used. Further, it is preferable to combine a transistor using an oxide semiconductor and a photoelectric conversion element using a selenium-based material in order to improve reliability. For the photoelectric conversion element 1360, an element having selenium or a compound containing selenium (hereinafter referred to as a selenium-based material), or an element having silicon (for example, an element in which a pin-type junction is formed) can be used. Also, it is possible to form transistors 1351, 1352, 1353, and 1354 using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon. However, Since the reliability can be improved by combining a transistor using an oxide semiconductor and a photoelectric conversion element using a selenium-based material, it is preferable.

[0385] <5-3. Transistor> Transistors 1351, 1352, 1353, and 1354 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon. However, Transistors 1351, 1352, 1353, and 1354 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon. However, transistors using an oxide semiconductor It is also possible to form transistors 1351, 1352, 1353, and 1354 using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon. However, transistors using an oxide semiconductor It is preferably formed of a transistor. A transistor having a channel formation region formed of an oxide semiconductor exhibits extremely low off-current characteristics. Further, as a transistor having a channel formation region formed of an oxide semiconductor, for example, the transistor shown in Embodiment 1 can be used.

[0386] In particular, if the leakage currents of the transistors 1351 and 1353 connected to the charge storage part (FD) are large, the time during which the charges stored in the charge storage part (FD) can be held becomes insufficient. Therefore, by using transistors in which at least these two transistors are made of an oxide semiconductor, it is possible to prevent unnecessary charges from flowing out of the charge storage part (FD).

[0387] Also, in the transistors 1352 and 1354, if the leakage current is large, unnecessary charges are output to the wiring 1314 or the wiring 1315. Therefore, as these transistors, it is preferable to use transistors having a channel formation region formed of an oxide semiconductor.

[0388] In FIG. 32(A), a transistor having one gate electrode is illustrated, but the present invention is not limited thereto. For example, a configuration having a plurality of gate electrodes may be used. As a transistor having a plurality of gate electrodes, for example, a configuration having a first gate electrode overlapping a semiconductor film in which a channel formation region is formed and a second gate electrode (also referred to as a back gate electrode) may be used. As the back gate electrode, for example, the same potential as the first gate electrode, a floating potential, or a potential different from the first gate electrode may be applied.

[0389] <5-4. Circuit operation timing chart> Next, an example of the circuit operation of the circuit shown in Fig. 32(A) will be described using the timing chart shown in Fig. 32(B).

[0390] In Fig. 32(B), for simplicity of explanation, the potential of each wiring is given as a signal that changes between two values. However, since each potential is an analog signal, in reality, it can take various values depending on the situation, not limited to two values. Note that the signal 1401 shown in Fig. 32(B) is the potential of the wiring 1311 (RS), the signal 1402 is the potential of the wiring 1312 (TX), the signal 1403 is the potential of the wiring 1313 (SE), the signal 1404 is the potential of the charge storage section (FD), and the signal 1405 is the potential corresponding to the potential of the wiring 1315 (OUT). The potential of the wiring 1316 is always "Low", and the potential of the wiring 1317 is always "High".

[0391] At time A, when the potential of the wiring 1311 (signal 1401) is set to "High" and the potential of the wiring 1312 (signal 1402) is set to "High", the potential of the charge storage section (FD) (signal 1404) is initialized to the potential of the wiring 1317 ("High"), and the reset operation is started. Note that the potential of the wiring 1315 (signal 1405) is pre-charged to "High".

[0392] At time B, when the potential of the wiring 1311 (signal 1401) is set to "Low", the reset operation ends and the accumulation operation starts. Here, since a reverse bias is applied to the photoelectric conversion element 1360, the potential of the charge storage section (FD) (signal 1404) starts to decrease due to the reverse current. Since the reverse current of the photoelectric conversion element 1360 increases when irradiated with light, ​​​​​​​​​The rate of decrease in the potential (signal 1404) of the charge storage section (FD) varies according to the amount of light irradiated. That is, according to the amount of light irradiated to the photoelectric conversion element 1360, the channel resistance between the source and drain of the transistor 135 4 changes.

[0393] At time C, when the potential of the wiring 1312 (signal 1402) is set to "Low", the accumulation operation ends, and the potential (signal 1404) of the charge storage section (FD) becomes constant. Here, the potential is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. That is, it varies according to the amount of light irradiated to the photoelectric conversion element 1360. Also, since the transistors 135 1 and 1353 are composed of transistors with an extremely low off-current formed in the channel formation region by an oxide film semiconductor, it is possible to keep the potential of the charge storage section (FD) constant until the subsequent selection operation (read operation) is performed.

[0394] When the potential of the wiring 1312 (signal 1402) is set to "Low", due to the parasitic capacitance between the wiring 1312 and the charge storage section (FD), the potential of the charge storage section (FD) may change. If the amount of change in the potential is large, the amount of charge generated by the photoelectric conversion element 136 0 during the accumulation operation cannot be accurately obtained. To reduce the amount of change in the potential, measures such as reducing the gate electrode-source electrode (or gate electrode-drain electrode ) capacitance of the transistor 1351, increasing the gate capacitance of the transistor 1352, and providing a holding capacitance in the charge storage section (FD ) are effective. In this embodiment, it is assumed that the change in the potential can be ignored by these countermeasures.

[0395] At time D, when the potential of the wiring 1313 (signal 1403) is set to “High”, the transistor The transistor 1354 becomes conductive to start the selection operation, and the wiring 1314 and the wiring 1315 become Then, the potential of the wiring 1315 ( The signal 1405) drops. Note that the precharge of the wiring 1315 is completed before time D. The rate at which the potential of the wiring 1315 (signal 1405) decreases is It depends on the current between the source and drain electrodes of the transistor 1352. It changes depending on the amount of light irradiated onto the photoelectric conversion element 1360 during operation.

[0396] At time E, when the potential of the wiring 1313 (signal 1403) is set to “Low”, the transistor The resistor 1354 is cut off, the selection operation is terminated, and the potential of the wiring 1315 (signal 1405) Here, the constant value is determined by the amount of light irradiated onto the photoelectric conversion element 1360. Therefore, by acquiring the potential of the wiring 1315, Therefore, the amount of light irradiated onto the photoelectric conversion element 1360 can be known.

[0397] More specifically, when the light irradiating the photoelectric conversion element 1360 is strong, the charge storage portion (F D), i.e., the gate voltage of transistor 1352, drops. The current flowing between the source electrode and the drain electrode of the transistor 1352 becomes small, and the wiring 1315 Therefore, the potential of the signal 1405 is relatively low from the wiring 1315. A high potential can be read out.

[0398] Conversely, when the light irradiating the photoelectric conversion element 1360 is weak, the potential of the charge storage unit (FD) , that is, the gate voltage of transistor 1352 increases. Therefore, the current flowing between the source electrode and the drain electrode of transistor 1 352 increases, and the potential of wiring 1315 ( signal 1405) decreases rapidly. Therefore, a relatively low potential can be read from wiring 1315.

[0399] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0400] (Embodiment 6) In this embodiment, a display device having a semiconductor device according to an aspect of the present invention will be described with reference to FIG. 33.

[0401] <6. Circuit Configuration of Display Device> The display device shown in FIG. 33(A) includes a region having pixels (hereinafter referred to as pixel portion 502), a circuit portion (hereinafter referred to as driving circuit portion 504) disposed outside the pixel portion 502 and having a circuit for driving the pixels, a circuit having an element protection function (hereinafter referred to as protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may not be provided.

[0402] It is desirable that part or all of the driving circuit portion 504 is formed on the same substrate as the pixel portion 502. This can reduce the number of components and terminals. When part or all of the driving circuit portion 504 is not formed on the same substrate as the pixel portion 502, part or all of the driving circuit portion 504 can be mounted by COG or TAB (Tape Automated B onding).

[0403] The pixel portion 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). It has a circuit (hereinafter referred to as pixel circuit 501) for driving a plurality of display elements, and the driving circuit unit 504 has driving circuits such as a circuit (hereinafter referred to as gate driver 504a) that outputs a signal (scanning signal) for selecting a pixel and a circuit (hereinafter referred to as source driver 504b) that supplies a signal (data signal) for driving the display element of the pixel. The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The source driver 504b has a shift register and the like. The source driver 504b receives, via the terminal portion 507, in addition to a signal for driving the shift register, a signal (image signal) that is the source of the data signal. The source driver 504b has a function of generating a data signal to be written into the pixel circuit 501 based on the image signal. Also, the source driver 504b generates a data signal according to a pulse signal obtained when a start pulse, a clock signal, etc. are input.

[0404] The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The source driver 504b has a shift register and the like. The source driver 504b receives, via the terminal portion 507, in addition to a signal for driving the shift register, a signal (image signal) that is the source of the data signal. The source driver 504b has a function of generating a data signal to be written into the pixel circuit 501 based on the image signal. Also, the source driver 504b generates a data signal according to a pulse signal obtained when a start pulse, a clock signal, etc. are input. However, it is not limited to this, and the gate driver 504a can also supply another signal. The source driver 504b has a shift register and the like. The source driver 504b receives, via the terminal portion 507, in addition to a signal for driving the shift register, a signal (image signal) that is the source of the data signal.

[0405] The source driver 504b has a shift register and the like. The source driver 504b receives, via the terminal portion 507, in addition to a signal for driving the shift register, a signal (image signal) that is the source of the data signal. The source driver 504b has a function of generating a data signal to be written into the pixel circuit 501 based on the image signal. Also, the source driver 504b generates a data signal according to a pulse signal obtained when a start pulse, a clock signal, etc. are input. The source driver 504b has a function of generating a data signal to be written into the pixel circuit 501 based on the image signal. Also, the source driver 504b generates a data signal according to a pulse signal obtained when a start pulse, a clock signal, etc. are input. It has a function of controlling the output of the signal. Also, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is supplied. Or, the source driver 504b has a function of being able to supply an initialization signal. However, it is not limited to this, and the source driver 504b can also supply another signal. The source driver 504b is configured by using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-division multiplexing the image signal as a data signal by sequentially turning on a plurality of analog switches. Also, the source driver 504b may be configured by using a shift register or the like.

[0406] Each of the plurality of pixel circuits 501 has a pulse signal input through one of the plurality of scan lines GL to which the scan signal is supplied, and a data signal input through one of the plurality of data lines DL to which the data signal is supplied. Also, the writing and holding of the data of the data signal are controlled for each of the plurality of pixel circuits 501 by the gate driver 504a. For example, the pixel circuit 501 at the m-th row and n-th column receives a pulse signal from the gate driver 504a through the scan line GL_m (m is a natural number less than or equal to X), and a data signal from the source driver 504b through the data line DL_n (n is a natural number less than or equal to Y) according to the potential of the scan line GL_m. The protection circuit 506 shown in FIG. 33(A) is connected to, for example, the scan line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Or, the protection circuit 506 is connected to the source driver

[0407]

[0408] ​​​​​​​​​​​​It is connected to the data line DL, which is a wiring between the IBA 504b and the pixel circuit 501. Or, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Or, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 refers to a portion where terminals for inputting power, a control signal, and an image signal from an external circuit to the display device are provided.

[0409] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 is a circuit that makes the wiring and another wiring in a conductive state.

[0410] As shown in FIG. 33(A), by providing the protection circuit 506 in the pixel portion 502 and the driving circuit portion 504 respectively, the resistance of the display device against overcurrent generated by ESD (Electro Static Discharge) etc. can be enhanced. However, the configuration of the protection circuit 506 is not limited to this. For example, a configuration in which the protection circuit 506 is connected to the gate driver 504a, or a configuration in which the protection circuit 506 is connected to the source driver 504b can also be adopted. Alternatively, a configuration in which the protection circuit 506 is connected to the terminal portion 507 can also be adopted.

[0411] Also, in FIG. 33(A), an example in which the driving circuit portion 504 is formed by the gate driver 504a and the source driver 504b is shown, but the configuration is not limited to this. For example, only the gate driver 504a is formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted.

[0412] Also, the plurality of pixel circuits 501 shown in FIG. 33(A) can have, for example, the configuration shown in FIG. 33(B). It can be set as follows.

[0413] The pixel circuit 501 shown in FIG. 33(B) includes a liquid crystal element 570, a transistor 550, and a capacitor element 560. The transistor shown in the previous embodiment can be applied to the transistor 550. It has a capacitor element 560. The transistor shown in the previous embodiment can be applied to the transistor 550. It can be applied.

[0414] One potential of a pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set according to the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuits 501 in each row. It is set as appropriate. The alignment state of the liquid crystal element 570 is set according to the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuits 501 in each row. One of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501 has a common potential (common potential). Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuits 501 in each row. It may be given different potentials.

[0415] For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode, or a TBA (Transverse Bend Alignment) mode may be used. -mode, a VA mode, an ASM (Axially Symmetric Aligned M icro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liqu id Crystal) mode, an AFLC (AntiFerroelectric Li quid Crystal) mode, an MVA mode, a PVA (Patterned Ve rtical Alignment) mode, an IPS mode, an FFS mode, or a TBA (Transverse Bend Alignment) mode or the like may be used. In addition to the driving method described above, as a driving method of the display device, there are an ECB (Electric ally Controlled Birefringence) mode, a PDLC (P olymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a guest ho st mode, and the like. However, the present invention is not limited thereto, and various liquid crystal elements and driving methods thereof can be used.

[0416] In the pixel circuit 501 at the m-th row and n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Further, the gate electrode of the transistor 550 is electrically connected to the scanning line G L_m. The transistor 550 has a function of controlling the writing of data of the data signal by being turned on or off.

[0417] One of the pair of electrodes of the capacitor element 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL ), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor element 560 has a function as a holding capacitor for holding the written data.

[0418] For example, in a display device having the pixel circuit 501 shown in FIG. 33(B), for example, each pixel circuit 501 in each row is sequentially selected by the gate driver 504a shown in FIG. 33(A), and the transistor 550 is turned on to write the data of the data signal.

[0419] ​​​ The pixel circuit 501 in which data is written enters a holding state when the transistor 550 turns off. By sequentially performing this operation for each row, an image can be displayed.

[0420] Also, the plurality of pixel circuits 501 shown in FIG. 33(A) can have, for example, the configuration shown in FIG. 33(C). It can be set as follows.

[0421] Also, the pixel circuit 501 shown in FIG. 33(C) includes transistors 552 and 554, a capacitor element 562, and a light-emitting element 572. Either one or both of the transistors 552 and 554 can be applied with the transistors shown in the previous embodiments. One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a data line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied. The transistor 552 has a function of controlling the writing of data of the data signal by turning on or off.

[0422] One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a data line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied. One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a data line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied. The gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied. The gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

[0423] The transistor 552 has a function of controlling the writing of data of the data signal by turning on or off. The transistor 552 has a function of controlling the writing of data of the data signal by turning on or off.

[0424] One of the pair of electrodes of the capacitor element 562 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL_a) to which a potential is supplied, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. One of the pair of electrodes of the capacitor element 562 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL_a) to which a potential is supplied, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. One of the pair of electrodes of the capacitor element 562 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL_a) to which a potential is supplied, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

[0425] The capacitor element 562 has a function as a holding capacitor for holding the written data.

[0426] ​One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Furthermore, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

[0427] One of the anode and the cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

[0428] As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

[0429] Note that a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other.

[0430] In the display device having the pixel circuit 501 shown in FIG. 33(C), for example, each row of pixel circuits 501 is sequentially selected by the gate driver 504a shown in FIG. 33(A), and the transistor 552 is turned on to write the data of the data signal.

[0431] The pixel circuit 501 in which the data is written enters a holding state when the transistor 552 is turned off. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with a luminance corresponding to the amount of current flowing. By sequentially performing this for each row, an image can be displayed.

[0432] ​​​​​​​​​​​The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. This is possible.

[0433] (Embodiment 7) In this embodiment, a display module and an electronic device having a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 34 and 35. This will be described with reference to FIGS. 34 and 35.

[0434] <7-1. Display module> The display module 8000 shown in FIG. 34 includes an upper cover 8001 and a lower cover 8002, and between them, a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery 8011. It has these components.

[0435] A semiconductor device according to one aspect of the present invention can be used, for example, for the display panel 8006.

[0436] The upper cover 8001 and the lower cover 8002 can be appropriately changed in shape and dimensions according to the sizes of the touch panel 8004 and the display panel 8006. This can be done as appropriate according to the sizes.

[0437] The touch panel 8004 can be used by superimposing a resistive film type or a capacitive type touch panel on the display panel 8006. Also, it is possible to provide a touch panel function on the counter substrate (sealing substrate) of the display panel 8006. Further, it is also possible to provide an optical sensor in each pixel of the display panel 8006 to form an optical touch panel. This can be achieved by superimposing a touch panel on the display panel. Also, it is possible to add a touch panel function to the counter substrate of the display panel. Additionally, it is possible to install an optical sensor in each pixel of the display panel to create an optical touch panel. board) of the display panel 8006. It is also possible to provide a touch panel function on the counter substrate (sealing substrate) of the display panel 8006. Further, it is also possible to provide an optical sensor in each pixel of the display panel 8006 to form an optical touch panel. 006 to make it an optical touch panel.

[0438] The backlight 8007 has a light source 8008. In FIG. 34, the configuration in which the light source 8008 is arranged on the backlight 8007 is illustrated, but it is not limited to this. For example, although the configuration where the light source 8008 is arranged on the backlight 8007 is exemplified in FIG. 34, it is not limited thereto. For example, For example, a light source 8008 may be arranged at the end of the backlight 8007, and a light diffusing plate may be further used in the configuration. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

[0439] The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010 in addition to the protection function of the display panel 8006. The frame 8009 may also have a function as a heat sink.

[0440] The printed circuit board 8010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As the power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply by a separately provided battery 8011 may be used. The battery 8011 can be omitted when using a commercial power supply.

[0441] In addition, the display module 8000 may be provided with additional members such as a polarizing plate, a retardation plate, and a prism sheet.

[0442] <7-2. Electronic device> FIGS. 35(A) to 35(G) are diagrams showing an electronic device. These electronic devices include a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, and a sensor 9007 (measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays). It can have functions, a microphone 9008, etc.

[0443] The electronic device shown in FIGS. 35(A) to 35(G) can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading out a program or data recorded on a recording medium and displaying it on the display unit, etc. can be had. Note that the functions that the electronic device shown in FIGS. 35(A) to 35(G) can have are not limited to these, and it can have various functions. Also, although not shown in FIGS. 35(A) to 35(G), the electronic device may have a configuration having a plurality of display units. Also, a camera or the like may be provided in the electronic device, and it may have functions such as a function of taking a still image, a function of taking a moving image, a function of saving the taken image in a recording medium (external or built into the camera), a function of displaying the taken image on the display unit, etc.

[0444] Details of the electronic device shown in FIGS. 35(A) to 35(G) will be described below.

[0445] FIG. 35(A) is a perspective view showing a television device 9100. The television device 9 100 can incorporate, for example, a large-screen display unit 9001 of 50 inches or more, or 100 inches or more.

[0446] FIG. 35(B) is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, etc. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may be provided with a speaker, a connection terminal, a sensor, etc. Also, the portable information terminal 9101 can display character and image information on its plurality of surfaces. For example, three operation buttons 9050 ( also referred to as operation icons or simply icons) can be displayed on one surface of the display unit 9001. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Note that as an example of the information 9051, there are displays notifying incoming calls such as e-mails, SNS (Social Networking Service), and telephone calls, titles of e-mails, SNS, etc., sender names of e-mails, SNS, etc., date and time, battery remaining amount, antenna reception strength, etc. Or, instead of the information 9051, operation buttons 9050, etc. may be displayed at the position where the information 9051 is displayed.

[0447] FIG. 35(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown where information 9052, information 9053, and information 9054 are displayed on different surfaces respectively. For example, a user of the portable information terminal 9102 can confirm the display (here, the information 9053) in a state where the portable information terminal 9102 is stored in the breast pocket of a coat. Specifically, the telephone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can view the display without taking the portable information terminal 9102 out of the pocket. ​ It can be confirmed and it can be determined whether to answer the phone or not.

[0448] FIG. 35(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as mobile phones, e-mails, text viewing and creation, music playback, Internet communication , computer games, etc. Also, the display unit 9001 has its display surface provided in a curved shape, and display can be performed along the curved display surface. Also, the portable information terminal 9200 can perform communication-standardized short-range wireless communication. For example, by communicating with a wireless communication-capable headset, it is also possible to make a hands-free call. Also, the portable information terminal 9200 has a connection terminal 9006, and can directly exchange data with other information terminals via a connector. Also, charging can be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without using the connection terminal 9006.

[0449] FIGS. 35(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. Also, FIG. 35(E) is a perspective view of the portable information terminal 9201 in an unfolded state, and FIG. 35 (F) is a perspective view of the portable information terminal 9201 in a state changing from one of the unfolded state or the folded state to the other, and FIG. 35(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 has excellent portability in the folded state and excellent display comprehensibility due to a seamless wide display area in the unfolded state. The display unit 9001 of the portable information terminal 9201 is composed of three housings 9000 connected by a hinge 9055. It is supported. By bending between the two casings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0450] The electronic device described in this embodiment is characterized by having a display unit for displaying some information. However, the semiconductor device according to one aspect of the present invention can also be applied to an electronic device that does not have a display unit.

[0451] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

Explanation of Reference Numerals

[0452] 100 Transistor 100A Transistor 100B Transistor 100C Transistor 100D Transistor 100E Transistor 100F Transistor 100G Transistor 102 Substrate 104 Insulating Film 106 Conductive Film 107_3 Oxide Semiconductor Film 108 Oxide Semiconductor Film 108_1 Layer 108_2 Layer 108_3 Layer 108d Drain Region 108f Region 108i Channel Region 108s Source Region 110 Insulating Film 110_0 Insulating Film 112 Oxide Semiconductor Film​​​​ 112_0 Oxide semiconductor film 114 Conductive film 116 Insulating film 118 Insulating film 120 Conductive film 120a Conductive film 120b Conductive film 122 Insulating film 140 Mask 141a Opening 141b Opening 143 Opening 145 Impurity ele...

Claims

【Claim 1】 A semiconductor device having a transistor, wherein the transistor has a first oxide semiconductor film on a first insulating film, a gate insulating film on the first oxide semiconductor film, a second oxide semiconductor film on the gate insulating film, and a second insulating film on the first oxide semiconductor film and the second oxide semiconductor film, wherein the first oxide semiconductor film has a channel region that overlaps with the second oxide semiconductor film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film, wherein the channel region has a first layer and a second layer that is in contact with the upper surface of the first layer and covers the side surfaces of the first layer in the channel width direction, and wherein the second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film, a semiconductor device.

Images