Semiconductor device

Abstract

To provide stable electrical characteristics to a semiconductor device using an oxide semiconductor to achieve high reliability.SOLUTION: In a transistor including an oxide semiconductor film, provided is a transistor where on a top face part of the oxide semiconductor film, a metal oxide film which functions as a channel protection film and consists of a component similar to that of the oxide semiconductor film is laminated. The oxide semiconductor film used for an active layer of the transistor is the oxide semiconductor film where an impurity such as hydrogen, moisture, a hydrogen group and hydride is excluded by a heat treatment; and the oxide semiconductor film which achieves high purity and electrically i-type (intrinsic) by supplying oxygen which is reduced simultaneously with the impurity exclusion process and which is a principal component material to compose the oxide semiconductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in such electronic devices. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. is.

[0004] For example, a semiconductor with an electron carrier concentration of 10 18 / cm 3 Less than The amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) is used. A transistor in which this is used has been disclosed (see Patent Document 1).

[0005] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. They are faster than silicon-based transistors and easier to manufacture than polysilicon transistors. However, it is known that the electrical characteristics of the MOSFET are easily fluctuated and the reliability is low. The threshold voltage of a transistor varies before and after the T test. Patent Document 2 and Patent Document 3 disclose a method for simulating the threshold voltage of a transistor using an oxide semiconductor. In order to suppress fluctuations, a technique is disclosed that prevents charge trapping at the interface of the oxide semiconductor layer by an interface stabilization layer provided on at least one of the upper and lower surfaces of the oxide semiconductor layer.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, the transistors disclosed in Patent Document 2 or Patent Document 3 use a layer having the same quality as the gate insulating layer and the protective layer as the interface stabilization layer, and cannot maintain the state of the interface with the active layer well. Therefore, it is difficult to suppress charge trapping between the active layer and the interface stabilization layer. In particular, when the interface stabilization layer and the active layer have the same bandgap, charge accumulation can easily occur.

[0008] Therefore, it cannot be said that transistors using oxide semiconductors have sufficient reliability yet.

[0009] In view of such problems, one of the objectives is to impart stable electrical characteristics to a semiconductor device using an oxide semiconductor and improve its reliability.

Means for Solving the Problems

[0010] One aspect of the disclosed invention is that there is a metal oxide film that functions as a channel protection film for the oxide semiconductor film in contact with the oxide semiconductor film and the metal oxide film has the same components as the oxide semiconductor film, which is the technical idea. That is, one aspect of the disclosed invention has a structure in which a metal oxide film and an oxide semiconductor film are laminated. Here, "the same components as the oxide semiconductor film" means containing one or more metal elements selected from the constituent elements of the oxide semiconductor film. By providing such a laminated structure, it is possible to sufficiently suppress charges and the like that may be generated due to the operation of the semiconductor device from being trapped at the interface between the insulating film and the oxide semiconductor film. This effect is achieved by the mechanism that by arranging a metal oxide film composed of a material with good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges and the like that may be generated due to the operation of the semiconductor device can be suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. And due to the above-mentioned effect of being able to suppress the trapping of charges at the interface of the oxide semiconductor film, it is possible to suppress malfunctions in the operation of the semiconductor device and improve the reliability of the semiconductor device. Furthermore, in addition to such a laminated structure, it is preferable to have a structure in which an insulating film containing components different from those of the metal oxide film and the oxide semiconductor film is provided in contact on the metal oxide film. That is, one aspect of the disclosed invention has a structure in which an oxide semiconductor film, a metal oxide film, and an insulating film are laminated.

[0011]

[0012]

[0013]

[0014] ​​​​​​​​​​​​​​ Thus, by providing an insulating film formed using a material capable of forming a charge trapping center at the interface in a manner that it is in contact with a metal oxide film, it is possible to preferentially trap the above-described charges at the interface between the metal oxide film and the insulating film as compared with the interface between the oxide semiconductor film and the metal oxide film. That is, by providing an insulating film in a manner that it is in contact with the metal oxide film, charges can be preferentially trapped at the interface between the metal oxide film and the insulating film, and the trapping of charges at the interface between the oxide semiconductor film and the metal oxide film can be more effectively suppressed. And, due to the above-described effect that the trapping of charges at the interface of the oxide semiconductor film can be suppressed and the charge trapping center can be moved away from the oxide semiconductor film, malfunctions in the operation of the semiconductor device can be suppressed, and the reliability of the semiconductor device can be improved. From the above-described mechanism, it is desirable that the metal oxide film has a sufficient thickness. This is because when the metal oxide film is thin, the influence of the charges trapped at the interface between the metal oxide film and the insulating film may become large. For example, it is preferable that the metal oxide film is thicker than the oxide semiconductor film. In addition, since the insulating metal oxide film is formed in a manner that does not interfere with the connection between the source electrode and the drain electrode and the oxide semiconductor film, an increase in resistance can be prevented as compared with the case where a metal oxide film is present between the source electrode or the drain electrode and the oxide semiconductor film. Therefore, a decrease in the electrical characteristics of the transistor can be suppressed. Note that in the thin film formation process of the oxide semiconductor, due to the stoichiometric composition caused by the excess or deficiency of oxygen, etc.

[0015]

[0016]

[0017]

[0018] ​ If there is a deviation from , or if hydrogen or moisture that forms an electron donor is mixed in, the electrical conductivity will change. Such a phenomenon becomes a factor in the variation of electrical characteristics for transistors using oxide semiconductors. Therefore, impurities such as hydrogen, moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds ) are intentionally removed from the oxide semiconductor, and at the same time, oxygen that is the main component material constituting the oxide semiconductor and would otherwise decrease due to the impurity removal process is supplied to purify the oxide semiconductor film to high purity and make it electrically i-type (intrinsic). An i-type (intrinsic) oxide semiconductor is obtained by removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to high purity so that it contains as few impurities as possible other than the main components of the oxide semiconductor

[0019] to make it an i-type (intrinsic) oxide semiconductor, or an oxide semiconductor that is as close as possible to i-type (intrinsic). (intrinsic), or an oxide semiconductor that is as close as possible to i-type (intrinsic). There is.

[0020] In addition, in the process of making the oxide semiconductor film i-type, it is also possible to simultaneously make an i-type a metal oxide film made of the same components as the oxide semiconductor film. In one aspect of the disclosed invention, the metal oxide films provided on the upper and lower surfaces of the oxide semiconductor film are preferably metal oxide films in which impurities such as moisture and hydrogen are sufficiently reduced and electrically i-type. oxide semiconductor film. oxide semiconductor film. oxide semiconductor film.

[0021] A transistor having a highly purified oxide semiconductor film shows almost no temperature dependence in electrical characteristics such as threshold voltage and on-current. Also, the variation in transistor characteristics due to photo-degradation is small. oxide semiconductor film. oxide semiconductor film.

[0022] Hereinafter, one aspect of the present invention will be specifically described.

[0023] One aspect of the disclosed invention includes a gate electrode, a gate insulating film covering the gate electrode, an oxide semiconductor film provided in a region overlapping the gate electrode on the gate insulating film, a metal oxide film provided in contact with the oxide semiconductor film, and a source electrode and a drain electrode provided on the metal oxide film and in contact with a part of the oxide semiconductor film. The metal oxide film is a semiconductor device composed of an oxide of one or more metal elements selected from the constituent elements of the oxide semiconductor film. On the gate insulating film, an oxide semiconductor film provided in a region overlapping the gate electrode, a metal oxide film provided in contact with the oxide semiconductor film, and a source electrode and a drain electrode provided on the metal oxide film and in contact with a part of the oxide semiconductor film. On the metal oxide film, a source electrode and a drain electrode provided in contact with a part of the oxide semiconductor film. The metal oxide film is a semiconductor device composed of an oxide of one or more metal elements selected from the constituent elements of the oxide semiconductor film. The metal oxide film contains an oxide of one or more metal elements selected from the constituent elements of the oxide semiconductor film. That is.

[0024] In addition, in the above, the semiconductor device may have an insulating film covering the source electrode and the drain electrode and provided in contact with the metal oxide film. Also, in the above, the insulating film may have a conductive film on it. In addition, in the above, the semiconductor device may have an insulating film covering the source electrode and the drain electrode and provided in contact with the metal oxide film. Also, in the above, the insulating film may have a conductive film on it. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film.

[0025] In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the width of the metal oxide film in the channel length direction is shorter than the width of the oxide semiconductor film in the channel length direction, and the source electrode and the drain electrode may be in a structure in contact with a part of the upper surface of the oxide semiconductor film. Also, in the above, the side end portions of the oxide semiconductor film in the channel length direction and the side end portions of the metal oxide film in the channel length direction may be in a structure that coincides. Also, in the above, the metal oxide film has an opening provided so as to cover at least the oxide semiconductor film and expose a part of the oxide semiconductor film, and the source electrode and the drain electrode may be in a structure in contact with the oxide semiconductor film through the opening. Also, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Also, in the above, the metal oxide film preferably functions as a channel protection film. In addition, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. In addition, in the above, the semiconductor device may have a second metal oxide film provided in contact with the gate insulating film and in contact with the lower surface of the oxide semiconductor film. Preferably.

[0026] In addition, in the above, it may be configured to have a protective insulating film that is provided in contact with the metal oxide film and is in contact with the source electrode and the drain electrode at a part of the upper surface. Here, the protective insulating film functions as a film that protects the channel formation region of the oxide semiconductor film when etching the source electrode and the drain electrode. In the above, it may be configured to have a protective insulating film that is provided in contact with the metal oxide film and is in contact with the source electrode and the drain electrode at a part of the upper surface. Here, the protective insulating film functions as a film that protects the channel formation region of the oxide semiconductor film when etching the source electrode and the drain electrode. In addition, in the above, it may be configured to have a protective insulating film that is provided in contact with the metal oxide film and is in contact with the source electrode and the drain electrode at a part of the upper surface. Here, the protective insulating film functions as a film that protects the channel formation region of the oxide semiconductor film when etching the source electrode and the drain electrode. In addition, in the above, it may be configured to have a protective insulating film that is provided in contact with the metal oxide film and is in contact with the source electrode and the drain electrode at a part of the upper surface. Here, the protective insulating film functions as a film that protects the channel formation region of the oxide semiconductor film when etching the source electrode and the drain electrode.

[0027] In the above, it is preferable that the energy gap of the metal oxide film is larger than the energy gap of the oxide semiconductor film. Also, it is preferable that the energy at the lower end of the conduction band of the metal oxide film is higher than the energy at the lower end of the conduction band of the oxide semiconductor film. In the above, it is preferable that the energy gap of the metal oxide film is larger than the energy gap of the oxide semiconductor film. Also, it is preferable that the energy at the lower end of the conduction band of the metal oxide film is higher than the energy at the lower end of the conduction band of the oxide semiconductor film. In the above, it is preferable that the energy gap of the metal oxide film is larger than the energy gap of the oxide semiconductor film. Also, it is preferable that the energy at the lower end of the conduction band of the metal oxide film is higher than the energy at the lower end of the conduction band of the oxide semiconductor film.

[0028] In addition, in the above, the metal oxide film may be configured to contain gallium oxide.

[0029] In addition, in the above, the gate insulating film may be configured to contain silicon oxide or hafnium oxide. In addition, in the above, the gate insulating film may be configured to contain silicon oxide or hafnium oxide.

[0030] Note that in the above, the channel length L of the transistor determined by the width in the channel length direction of the metal oxide film that functions as a channel protection film is 10 nm or more and 10 μm or less. For example, it can be 0.1 μm to 0.5 μm. Of course, the channel length L may be 1 μm or more. Also, the channel width W can be 10 nm or more. Note that in the above, the channel length L of the transistor determined by the width in the channel length direction of the metal oxide film that functions as a channel protection film is 10 nm or more and 10 μm or less. For example, it can be 0.1 μm to 0.5 μm. Of course, the channel length L may be 1 μm or more. Also, the channel width W can be 10 nm or more. Note that in the above, the channel length L of the transistor determined by the width in the channel length direction of the metal oxide film that functions as a channel protection film is 10 nm or more and 10 μm or less. For example, it can be 0.1 μm to 0.5 μm. Of course, the channel length L may be 1 μm or more. Also, the channel width W can be 10 nm or more. Note that in the above, the channel length L of the transistor determined by the width in the channel length direction of the metal oxide film that functions as a channel protection film is 10 nm or more and 10 μm or less. For example, it can be 0.1 μm to 0.5 μm. Of course, the channel length L may be 1 μm or more. Also, the channel width W can be 10 nm or more. Note that in the above, the channel length L of the transistor determined by the width in the channel length direction of the metal oxide film that functions as a channel protection film is 10 nm or more and 10 μm or less. For example, it can be 0.1 μm to 0.5 μm. Of course, the channel length L may be 1 μm or more. Also, the channel width W can be 10 nm or more.

Advantages of the Invention

[0031] One embodiment of the present invention can fabricate a transistor having stable electrical characteristics.

[0032] Also, one embodiment of the present invention has a semiconductor having a transistor with good electrical characteristics and high reliability. The device can be fabricated.

Brief Description of the Drawings

[0033]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that its form and details can be variously changed. Further, the present invention is not construed as being limited to the description of the embodiments shown below.

[0035] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, it does not indicate a unique name as a matter for specifying the invention in this specification.

[0036] (Embodiment 1) ​In this embodiment, one form of a semiconductor device and a method for manufacturing a semiconductor device will be described with reference to FIGS. 1 to 5 as follows.

[0037] <Example Configuration of Semiconductor Device> FIG. 1 shows a cross-sectional view and a plan view of a transistor of a channel protection type (also referred to as a channel stop type), which is one of the bottom gate structures, as an example of a semiconductor device. FIG. 1(A) is a plan view, and FIGS. 1(B) and 1(C) are cross-sectional views taken along the A-B cross-section and the C -D cross-section in FIG. 1(A). In FIG. 1(A), in order to avoid complication, some of the components of the transistor 310 (for example, the gate insulating film 402, etc.) are omitted .

[0038] The transistor 310 shown in FIG. 1(A) includes a gate electrode 401, a gate insulating film 402 covering the gate electrode 401, an oxide semiconductor film 403 provided in a region overlapping the gate electrode 401 on the gate insulating film 402, a metal oxide film 407 provided in contact with the oxide semiconductor film 403 on the oxide semiconductor film 403, and a source electrode 405a and a drain electrode 405b provided on the metal oxide film 407 and in contact with a part of the oxide semiconductor film 403 on the metal oxide film 407, on a substrate 400 having an insulating surface. In the transistor 310 shown in FIG. 1(A), the metal oxide film 407 functions as a channel protection film. Further, the transistor 310 preferably has a configuration in which the source electrode 405a and the drain electrode 40 5b are covered, and an insulating film 409 is provided in contact with the metal oxide film 407. (A) The metal oxide film 407 preferably uses an oxide made of the same components as the oxide semiconductor film 403. Specifically, one or more selected from the constituent elements of the oxide semiconductor film

[0039] Here, it is desirable to use an oxide made of the same components as the oxide semiconductor film 403 for the metal oxide film 407. Specifically, one or more selected from the constituent elements of the oxide semiconductor film It is preferable to use a film containing oxides of several metal elements. Such a material has good compatibility with the oxide semiconductor film 403, and by using this for the metal oxide film 407, the state of the interface with the oxide semiconductor film can be kept good. That is, by using the above-mentioned material for the metal oxide film 4 07, charge trapping at the interface between the oxide semiconductor film and the metal oxide film in contact therewith (here, the interface between the metal oxide film 407 and the oxide semiconductor film 403) can be suppressed. Here, the interface between the metal oxide film 407 and the oxide semiconductor film 403) can be suppressed. Charge trapping at the interface between the metal oxide film 407 and the oxide semiconductor film 403 can be suppressed. That is, it can be done.

[0040] In addition, due to the relationship of using the oxide semiconductor film 403 as the active layer, the energy gap of the metal oxide film 407 is required to be larger than the energy gap of the oxide semiconductor film 403. Moreover, between the metal oxide film 407 and the oxide semiconductor film 403, at room temperature (20 °C), the formation of an energy barrier to the extent that carriers do not flow out from the oxide semiconductor film 403 is required at a minimum. For example, the energy difference between the lower end of the conduction band of the metal oxide film 407 and the lower end of the conduction band of the oxide semiconductor film 403, or the energy difference between the upper end of the valence band of the oxide semiconductor film 403 and the upper end of the valence band of the metal oxide film 407 is desirably 0.5 eV or more, more desirably 0.7 eV or more. Also, it is desirably 1.5 eV or less. Specifically, for example, when an In-Ga-Zn-O-based material is used for the oxide semiconductor film 403, the metal oxide film 407 may be formed using a material containing gallium oxide. The energy barrier when gallium oxide is brought into contact with an In-Ga-Zn-O-based material is about 0.8 eV on the conduction band side and about 0.9 eV on the valence band side. In addition, gallium oxide is GaO

[0041] Specifically, for example, when an In-Ga-Zn-O-based material is used for the oxide semiconductor film 403, the metal oxide film 407 may be formed using a material containing gallium oxide. The energy barrier when gallium oxide is brought into contact with an In-Ga-Zn-O-based material is about 0.8 eV on the conduction band side and about 0.9 eV on the valence band side. The energy barrier when gallium oxide is brought into contact with an In-Ga-Zn-O-based material is about 0.8 eV on the conduction band side and about 0.9 eV on the valence band side.

[0042] In addition, gallium oxide is GaOx is also expressed as, and it is preferable to set the value of x such that oxygen is in excess of the stoichiometric ratio. For example, it is preferable to set the value of x to be 1.4 or more and 2.0 or less. More preferably, the value of x is 1.5 or more and 1.8 or less. When used as the metal oxide film 407, the gallium oxide film is desirably a film in which impurities such as hydrogen and water are sufficiently reduced. However, by including impurity elements other than hydrogen, such as group 3 elements such as yttrium, group 4 elements such as hafnium, group 13 elements such as aluminum, group 14 elements such as silicon, nitrogen, etc. in the gallium oxide film, the energy gap of gallium oxide can be expanded to enhance the insulating property. The energy gap of a gallium oxide film without impurities is 4.9 eV, but by including the above-mentioned impurities, for example, in an amount exceeding 0 atomic % and up to 20 atomic %, the energy gap can be expanded to about 6 eV.

[0043] From the viewpoint of reducing the charge generation source and the trapping center, it is desirable that impurities such as hydrogen and water in the metal oxide film are sufficiently reduced. This concept is common to the concept of impurity reduction in the oxide semiconductor film.

[0044] In addition, since the metal oxide film 407 that functions as a channel protection film is provided in the region overlapping with the channel formation region of the oxide semiconductor film 403, damage to the channel formation region due to etching of the source electrode 405a and the drain electrode 405b (for example, damage caused by plasma or an etching agent during etching) can be prevented. As a result, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. .

[0045] Also, as shown in FIG. 1(B), by making the width of the metal oxide film 407 in the channel length direction shorter than the width of the oxide semiconductor film 403 in the channel length direction, the source electrode 405a and the drain electrode 405b are in contact with a part of the upper surface of the oxide semiconductor film 403. That is, by shortening the width of the metal oxide film 407 in the channel length direction, the channel length of the transistor 310 can be shortened, and the transistor can be made faster and consume less power. Also, when compared with a so-called channel etching type transistor that does not have the metal oxide film 407, the contact area between the source electrode 405a and the drain electrode 405b and the oxide semiconductor film 403 is reduced. Therefore, the region near the interface between the source electrode 405a and the drain electrode 405b and the oxide semiconductor film 403 becomes a high-resistance region. This

[0046] makes it possible to relieve the concentration of the electric field in the transistor 310. Therefore, even when the transistor 310 is miniaturized, it is possible to suppress the short-channel effect.

[0047] When the insulating film 409 is provided in contact with the metal oxide film 407, it is desirable to use, for the insulating film 409, a material that can form a charge trapping center at the interface by contacting the metal oxide film 407. By using such a material for the insulating film 409, charges are preferentially trapped at the interface between the insulating film 409 and the metal oxide film 407. Therefore, charge trapping at the interface between the metal oxide film 407 and the oxide semiconductor film 403 can be more effectively suppressed. However, charge trapping at the interface between the insulating film 409 and the metal oxide film 407 ​​​If a large number of centers are formed, the transistor characteristics may conversely deteriorate. Therefore, it can be said that it is preferable that the degree of charge trapping centers being formed is slightly easier than that at the interface between the oxide semiconductor film 403 and the metal oxide film 407.

[0048] Specifically, for the insulating film 409, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, a mixed material thereof, etc. may be used either singly or in a stacked manner. For example, when a material containing gallium oxide is used for the metal oxide film 407, it is preferable to use silicon oxide, silicon nitride, etc. for the insulating film 409. Further, due to the contact relationship with the metal oxide film 407, the energy gap of the insulating film 409 is desirably larger than the energy gap of the metal oxide film 407.

[0049] In addition, if charge trapping centers can be formed at the interface between the insulating film 409 and the metal oxide film 407, it is not necessary to limit the material of the insulating film 409 to the above-mentioned ones. Further, a process of forming charge trapping centers may be performed at the interface between the insulating film 409 and the metal oxide film 407. Such processes include, for example, plasma treatment and element addition treatment (such as ion implantation).

[0050] In addition, in the transistor 310, although the metal oxide film 407 is patterned in an island shape, it does not necessarily have to be patterned in an island shape. Also, the side ends in the channel length direction of the oxide semiconductor film 403 and the side ends in the channel length direction of the metal oxide film 407 may coincide. Further, when forming the insulating film 409, there may be a second gate electrode above the oxide semiconductor film 403. In that case, the gate electrode 401 is not provided. ​ It may be a top-gate type transistor. Also, it may further have a second metal oxide film in contact with the gate insulating film 402. Also, the width of the oxide semiconductor film 403 in the channel length direction is made narrower than the width of the gate electrode 401 in the channel length direction, and the oxide semiconductor film 4 03 may be patterned. Also, an insulating film may be further provided on the transistor 310. Also, openings may be formed in the gate insulating film 402, the metal oxide film 407, the insulating film 409, etc. in order to electrically connect the source electrode 405a or the drain electrode 405b to the wiring. Note that the oxide semiconductor film 403 is preferably processed into an island shape, but it does not have to be processed into an island shape.

[0051] Figure 2 is an energy band diagram (schematic diagram) in the structure in which the above-described transistor 310, that is, the insulating film, the oxide semiconductor film, the metal oxide film, and the insulating film are joined from the gate electrode GE side, and E is the Fermi level of the oxide semiconductor film. In Figure 2, an ideal situation where all of the insulating film, the metal oxide film, and the oxide semiconductor film are intrinsic is assumed, and silicon oxide (SiO ) (band gap Eg 8 eV to 9 eV) is used as the insulating film, gallium oxide (GaO F )(band gap Eg 4.9 eV) is used as the metal oxide film, and an In-Ga-Zn-O based non-single crystal film (band gap Eg 3.15 eV) x x is used as the oxide semiconductor film (OS). Note that the energy difference between the vacuum level and the lower end of the conduction band of silicon oxide is 0.95 eV, the energy difference between the vacuum level and the lower end of the conduction band of gallium oxide is 3 .5 eV, and the energy difference between the vacuum level and the lower end of the conduction band of the In-Ga-Zn-O based non-single crystal film is ​​​​​​​​​​​​​ The difference is 4.3 eV.

[0052] As shown in FIG. 2, on the gate electrode side (channel side) of the oxide semiconductor film, there are energy barriers of about 3.35 eV and about 2.5 eV at the interface between the oxide semiconductor film and the insulating film. Similarly, on the side of the oxide semiconductor film opposite to the gate electrode (back channel side), there are also energy barriers of about 0.8 eV and about 0.95 eV at the interface between the oxide semiconductor film and the metal oxide film. At the interface between the oxide semiconductor film and the insulating film, and at the interface between the oxide semiconductor film and the metal oxide film, due to the existence of such energy barriers, the movement of carriers is hindered at these interfaces. Therefore, carriers move in the oxide semiconductor film without moving from the oxide semiconductor film to the insulating film or from the oxide semiconductor film to the metal oxide film. That is, by providing the oxide semiconductor film sandwiched between materials (here, the metal oxide film and the insulating film) having a larger band gap than the oxide semiconductor film, carriers will move in the oxide semiconductor film.

[0053] FIG. 3 and FIGS. 4(A) to 4(H) show configuration examples of transistors different from that of FIG. 1.

[0054] FIG. 3 shows a cross-sectional view and a plan view of a transistor in which a metal oxide film 407 covers an oxide semiconductor film 403. Here, FIG. 3(A) is a plan view, and FIGS. 3(B) and 3(C ) are cross-sectional views taken along the A - B cross-section and the C - D cross-section in FIG. 3(A). Note that in FIG. 3 (A), in order to avoid complication, some of the components of the transistor 320 (for example, the gate insulating film 402, etc.) are omitted. ​

[0055] The transistor 320 shown in FIG. 3 is common to the transistor 310 shown in FIG. 1 in that it includes a gate electrode 401, a gate insulating film 402, an oxide semiconductor film 403, a metal oxide film 407, a source electrode 405a, a drain electrode 405b, and an insulating film 409 on a substrate 400. The difference between the transistor 320 shown in FIG. 3 and the transistor 310 shown in FIG. 1 is that the metal oxide film 407 covers the oxide semiconductor film 403. Here, the transistor 32 0 is provided with an opening in the metal oxide film 407 so that a part of the oxide semiconductor film 403 is exposed, and through the opening, the source electrode 405a and the drain electrode 405b are in contact with the oxide semiconductor film 403. For other components, they are the same as those of the transistor 310 shown in FIG. 1. Details can be referred to the description related to FIG. 1. With such a configuration, compared with the transistor 31 0 shown in FIG. 1, the transistor 320 has a structure in which the contact area between the source electrode 405a and the drain electrode 405b and the oxide semiconductor film 403 is reduced, so that the vicinity of the interface between the source electrode 405a and the drain electrode 40

[0056] 5b and the oxide semiconductor film 403 becomes a higher-resistance region. As a result, the concentration of the electric field in the transistor 31 0 can be further alleviated, so that even when the transistor 31 0 is miniaturized, the short-channel effect can be more effectively suppressed. 5b and the oxide semiconductor film 403 becomes a higher-resistance region. Thus, the concentration of the electric field in the transistor 31 0 can be further alleviated, so that even when the transistor 31 0 is miniaturized, the short-channel effect can be more effectively suppressed.

[0057] The transistors 330 and 340 shown in FIGS. 4(A) and 4(B) are, with respect to the configurations of the above-described transistors 310 and 320, respectively, on the insulating film 409 above A conductive film 410 is provided in a region overlapping with the channel formation region of the oxide semiconductor film 403. This is the configuration. The conductive film 410 may be formed by the same material and method as the gate electrode 401. Regarding other components, they are the same as those of the above-described transistors 310 and 320. Note that the transistors 350 and 360 shown in FIGS. 4(C) and 4(D) have a configuration in which the gate electrode 401 and the gate insulating film 402 are not provided further with respect to the configuration of the transistors 330 and 340, and are top-gate type transistors.

[0058] The transistors 370 and 380 shown in FIGS. 4(E) and 4(F) are configured such that a metal oxide film 404 is further provided in contact with the gate insulating film 402 with respect to the configuration of the above-described transistors 310 and 320. The metal oxide film 404 may be formed by the same material and method as the metal oxide film 407. Also, the gate insulating film 402 is preferably formed by the same material and method as the insulating film 409. Regarding other components, they are the same as those of the above-described transistors 310 and 320.

[0059] With such a configuration, charge trapping can be suppressed also at the lower surface portion of the oxide semiconductor film 403, that is, at the interface between the oxide semiconductor film 403 and the metal oxide film 404. Furthermore, by using a material capable of forming a charge trapping center at the interface by bringing the gate insulating film 402 into contact with the metal oxide film 404, charges are preferentially trapped at the interface between the gate insulating film 402 and the metal oxide film 404, so that charge trapping at the interface between the metal oxide film 404 and the oxide semiconductor film 403 can be more effectively suppressed. ​

[0060] The transistor 390 shown in FIG. 4(G) has a structure in which, compared with the structure of the above-described transistor 310, the width of the oxide semiconductor film 403 in the channel length direction is made narrower than the width of the gate electrode 401 in the channel length direction. The oxide semiconductor film 403 is patterned. For other components, it is the same as the above-described transistor 310. By adopting such a structure, the oxide semiconductor film 403 can be made flat, so that it is possible to prevent carrier scattering and reduce interface levels at the interface between the oxide semiconductor film 403 and the gate insulating film 402.

[0061] The transistor 500 shown in FIG. 4(H) has a structure in which, compared with the structure of the above-described transistor 310, a protective insulating film 419 is further provided in contact with the metal oxide film 407. That is, a part of the upper surface of the protective insulating film 419 is in contact with the source electrode 405a and the drain electrode 405b, and together with the metal oxide film 407, it functions as a channel protection film. The protective insulating film 41 9 may be formed by the same material and method as the insulating film 409. For other components, it is the same as the above-described transistor 310.

[0062] By adopting such a structure, even in a configuration where the insulating film 409 is not provided, a protective insulating film 419 using a material capable of forming a charge trapping center at the interface by contacting and contacting the metal oxide film 407 can be provided on the metal oxide film 407. Therefore, even in a configuration where the insulating film 409 is not provided, compared with the interface between the oxide semiconductor film 403 and the metal oxide film 407, since charges are preferentially trapped at the interface between the protective insulating film 419 and the metal oxide film 407, , the charge trapping at the interface between the metal oxide film 407 and the oxide semiconductor film 403 can be more effectively suppressed.

[0063] Note that the configurations of the above transistors can be used in appropriate combinations with each other. can.

[0064] <Example of the manufacturing process of the transistor> Hereinafter, with reference to FIG. 5, an example of the manufacturing process of the transistor shown in FIG. 1, FIG. 3, or FIG. 4 will be described.

[0065] <Manufacturing process of the transistor 310> An example of the manufacturing process of the transistor 310 shown in FIG. 1 will be described with reference to FIGS. 5(A) to 5(E). described.

[0066] First, after forming a conductive film on a substrate 400 having an insulating surface, a gate electrode 401 is formed by a first photolithography process (see FIG. 5(A)). Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photo mask is not used, the manufacturing cost can be reduced. There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least

[0067] it is necessary to have heat resistance enough to withstand subsequent heat treatment. For example, substrates such as glass substrates, ceramic substrates, quartz substrates, and sapphire substrates can be used. In addition, as long as it has an insulating surface, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can be applied, and semiconductor elements may be provided on these substrates. possible, and semiconductor elements may be provided on these substrates.

[0068] Further, a flexible substrate may be used as the substrate 400. When using a flexible substrate, a transistor including an oxide semiconductor film 403 may be directly fabricated on the flexible substrate, or a transistor including an oxide semiconductor film 403 may be fabricated on another fabrication substrate and then peeled off and transferred onto the flexible substrate. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, it is advisable to provide a peeling layer between the fabrication substrate and the transistor including the oxide semiconductor film 403.

[0069] An insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode 401. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 400 and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0070] Also, the gate electrode 401 can be formed as a single layer or by lamination using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium or an alloy material mainly composed of these.

[0071] Next, a gate insulating film 402 is formed on the gate electrode 401 (see FIG. 5(A)).

[0072] Specifically, as the gate insulating film 402, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or a gallium oxide film, etc. can be formed as a single layer or by lamination.

[0073] ​​​​​​​The method for producing the gate insulating film 402 is not particularly limited. For example, a plasma CVD method or a spa The gate insulating film 402 can be formed by a deposition method such as a quartz deposition method.

[0074] After the gate insulating film 402 is formed, a metal oxide film 40 is further formed on the gate insulating film 402. 4, the transistor 370 shown in FIG. 4(E) or the transistor 370 shown in FIG. The metal oxide film 404 can be formed as a metal oxide film 4 It can be formed using the same materials and processes as 07.

[0075] Next, an oxide semiconductor film 40 with a thickness of 3 nm to 30 nm is formed on the gate insulating film 402. The oxide semiconductor film 403 is formed by a sputtering method (see FIG. 5A). If the thickness is too large (for example, 50 nm or more), the transistor becomes normally on. Therefore, it is preferable to set the thickness as described above. The oxide semiconductor film 402 and the oxide semiconductor film 403 are preferably formed in succession without exposure to air.

[0076] Note that before the oxide semiconductor film 403 was formed by a sputtering method, argon gas was The reverse sputtering is performed by introducing the ions into the gate insulating film 402 to generate plasma. It is preferable to remove the powdery material (also called particles or dust) that is stuck to the surface. is a method of modifying the surface of the substrate by applying a voltage to the substrate and forming plasma in the vicinity of the substrate. In place of argon, gas such as nitrogen, helium, or oxygen may be used.

[0077] The oxide semiconductor used for the oxide semiconductor film 403 is an In- Sn-Ga-Zn-O-based oxide semiconductors, and In-Ga-Zn-O which is a ternary metal oxide Based oxide semiconductors, In-Sn-Zn-O-based oxide semiconductors, In-Al-Zn-O-based oxide Semiconductors, Sn-Ga-Zn-O-based oxide semiconductors, Al-Ga-Zn-O-based oxide Semiconductors, Sn-Al-Zn-O-based oxide semiconductors, and In-Zn-O-based oxide which is a binary metal oxide Semiconductors, Sn-Zn-O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg -O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, and In-O-based oxide semiconductors which are single-element metal oxides, S n-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. can be used. Further, the above Oxide semiconductors may contain SiO2. Here, for example, the In-Ga-Zn-O-based oxide Refers to an oxide film having indium (In), gallium (Ga), and zinc (Zn), And the composition ratio is not particularly limited. Further, elements other than In, Ga, and Zn May be included.

[0078] Further, the oxide semiconductor film 403 can use a thin film represented by the chemical formula InMO3(ZnO) m (m>0), Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and M n, or Ga and Co, etc. n, or Ga and Co, etc.

[0079] In this embodiment, an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor film 403 A film is formed by a sputtering method using a film-forming target. Further, the oxide semiconductor film 40 3 can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen. It can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen.

[0080] As the oxide semiconductor film 403, a target for producing an In-Ga-Zn-O film by sputtering can be used, for example, an oxide semiconductor film-forming target having a composition ratio of In2O3:Ga2O3:ZnO = 1 :1:1 [molar ratio]. Further, the material and composition of this target are not limited. For example, an oxide semiconductor film-forming target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] may also be used. When using a material of the In-Zn-O system as the oxide semiconductor, the composition ratio of the target to be used is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (converted to molar ratio, In2O3 :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (converted to molar ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 15

[0081] :1 to 1.5:1 (converted to molar ratio, In2O3:ZnO = 15:2 to 3:4). For example, when the target used for forming the In-Zn-O-based oxide semiconductor has an atomic ratio of In :Zn:O = X:Y:Z, then Z > 1.5X + Y. :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (converted to molar ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 15 :1 to 1.5:1 (converted to molar ratio, In2O3:ZnO = 15:2 to 3:4). For example, when the target used for forming the In-Zn-O-based oxide semiconductor has an atomic ratio of In :Zn:O = X:Y:Z, then Z > 1.5X + Y. :Zn:O = X:Y:Z, then Z > 1.5X + Y. :Zn:O = X:Y:Z, then Z > 1.5X + Y.

[0082] Further, the filling rate of the target for forming the oxide semiconductor film is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for forming an oxide semiconductor film with a high filling rate, the formed oxide semiconductor film 403 can be made into a dense film. By using a target for forming an oxide semiconductor film with a high filling rate, the formed oxide semiconductor film 403 can be made into a dense film.

[0083] The sputtering gas used in forming the oxide semiconductor film 403 includes hydrogen, water, and a hydroxyl group. Alternatively, it is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0084] The oxide semiconductor film 403 was formed by holding the substrate 400 in a deposition chamber kept under reduced pressure. The substrate temperature is set to 100° C. or higher and 600° C. or lower, preferably 200° C. or higher and 400° C. or lower. By heating the substrate 400 during the deposition, the oxide semiconductor film 403 contains In addition, the concentration of impurities in the oxide semiconductor film 4 by sputtering can be reduced. Damage to the oxidized layer 03 is reduced. Hydrogen and moisture are removed while removing the residual moisture in the deposition chamber. The sputtering gas was introduced, and the oxide semiconductor film was deposited on the substrate 400 using the target. In order to remove the residual moisture in the deposition chamber, a vacuum pump of the adsorption type, e.g. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump contains hydrogen atoms, water (H2O), and other hydrogen gases. Since compounds containing atoms (and more preferably compounds containing carbon atoms) are exhausted, The impurity concentration in the oxide semiconductor film 403 formed in the deposition chamber can be reduced.

[0085] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 P. a. DC power supply 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere In addition, when a pulsed DC power supply is used, the powdery substances (particles, This is preferable because it reduces the amount of dust (also called dirt) and reduces the variation in film thickness.

[0086] Thereafter, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor film 403. By this first heat treatment, excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor film 403 is removed, the structure of the oxide semiconductor film 403 is adjusted, and the defect levels in the energy gap can be reduced. The temperature of the first heat treatment is 250°C or higher and 700°C or lower, preferably 450°C or higher and 600°C or lower. Note that the temperature of the first heat treatment is preferably lower than the distortion point of the substrate.

[0087] For the heat treatment, for example, the object to be treated can be introduced into an electric furnace using a resistance heating element or the like, and the treatment can be performed under a nitrogen atmosphere at 450°C for 1 hour. During this time, the oxide semiconductor film 403 is prevented from coming into contact with the atmosphere so that no water or hydrogen is mixed in.

[0088] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as a heated gas or heat radiation may also be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used. ​​​​​​​​​​

[0089] For example, as the first heat treatment, the object to be treated is put into a heated inert gas atmosphere, and after heating for several minutes, a GRTA treatment may be performed in which the object to be treated is taken out from the inert gas atmosphere. When the GRTA treatment is used, high-temperature heat treatment can be performed in a short time. Further, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the object to be treated. During the treatment, the inert gas may be switched to a gas containing oxygen. This is because by performing the first heat treatment in an atmosphere containing oxygen, the defect levels in the energy gap caused by oxygen deficiency can be reduced.

[0090] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc.) and not containing water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). (That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0091] In any case, by reducing impurities by the first heat treatment and forming an oxide semiconductor film 403 that is extremely close to an i-type (intrinsic) semiconductor or an i- type semiconductor, a transistor with extremely excellent characteristics can be realized.

[0092] By the way, since the above heat treatment (the first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydration treatment and the dehydrogenation treatment are, for example, at a timing such as after processing the oxide semiconductor film 403 into an island shape. ​​​It is also possible to perform in G. Further, such dehydration treatment and dehydrogenation treatment may be performed not only once but also multiple times.

[0093] Next, it is preferable to process the oxide semiconductor film 403 into an island-shaped oxide semiconductor film 403 by a second photolithography process (see Fig. 5(A)). Further, a resist mask for forming the island-shaped oxide semiconductor film 403 may be formed by an inkjet method. Since a photomask is not used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced. The etching of the oxide semiconductor film 403 here may be dry etching or wet etching, or both may be used.

[0094] Note that by processing the oxide semiconductor film 403 so that the width in the channel length direction of the island-shaped oxide semiconductor film 403 is narrower than the width in the channel length direction of the gate electrode 401, the transistor 390 shown in Fig. 4(G) can be formed.

[0095] Next, plasma treatment using a gas such as N2O, N2, or Ar may be performed to remove adsorbed water or the like attached to the surface of the exposed oxide semiconductor film 403. When plasma treatment is performed, it is desirable to form the metal oxide film 407 in contact with the oxide semiconductor film 403 without being exposed to the atmosphere following the plasma treatment.

[0096] Next, a metal oxide film 427 is formed covering the oxide semiconductor film 403 (see Fig. 5(B)). Note that the metal oxide film 427 becomes the metal oxide film 407 by being processed into an island shape in a later process.

[0097] The metal oxide film 427 (metal oxide film 407) is made of the same components as the oxide semiconductor film 403, and it is desirable to use an oxide containing the main component material of the oxide semiconductor film 403. Such a material has good compatibility with the oxide semiconductor film 403, and by using it for the metal oxide film 407, the state of the interface with the oxide semiconductor film can be kept good. That is, by using the above material for the metal oxide film 427 (metal oxide film 407), the capture of charges at the interface between the metal oxide film 407 and the oxide semiconductor film 403 can be suppressed.

[0098] The energy gap of the metal oxide film 407 is required to be larger than that of the oxide semiconductor film 403. Also, between the metal oxide film 407 and the oxide semiconductor film 403, at room temperature (20 °C), the formation of an energy barrier that prevents carriers from flowing out of the oxide semiconductor film 403 is required at a minimum.

[0099] From the viewpoint of reducing the charge generation source and capture center, it is desirable that the impurities such as hydrogen and water in the metal oxide film 407 are sufficiently reduced. This idea is common to the idea of impurity reduction in the oxide semiconductor film.

[0100] The metal oxide film 427 (metal oxide film 407) is preferably formed using a method that does not mix impurities such as water and hydrogen. If hydrogen is contained in the metal oxide film 427 (metal oxide film 407), the intrusion of that hydrogen into the oxide semiconductor film 403 or the extraction of oxygen in the oxide semiconductor film 403 by hydrogen occurs, and the back channel of the oxide semiconductor film 403 becomes low resistance. ​​It may be n-type (n-doped), and there is a risk of forming a parasitic channel. Therefore, the metal oxide film 427 (metal oxide film 407) should be a film that contains as little hydrogen as possible, so it is important not to use hydrogen in the film formation method.

[0101] Therefore, the metal oxide film 427 is preferably formed by sputtering. As the sputtering gas used during film formation, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed.

[0102] Also, in order to move the charge trapping centers away from the oxide semiconductor film 403, the metal oxide film 427 (metal oxide film 407) preferably has a sufficient film thickness. Specifically, the metal oxide film 427 (metal oxide film 407) has a film thickness exceeding 10 nm and preferably 100 nm or less.

[0103] Note that after forming the metal oxide film 427, by further providing a protective insulating film 419 on the metal oxide film 427, the transistor 500 shown in FIG. 4(H) can be formed. The protective insulating film 419 can be formed of the same material and in the same process as the insulating film 409 described later. Also, the protective insulating film 419 can be patterned simultaneously when forming the metal oxide film 427 into the metal oxide film 407 in a later process. Of course, the metal oxide film 427 and the insulating film 419 may be patterned in separate processes.

[0104] Next, a resist mask is formed on the metal oxide film 427 by a third photolithography process, and etching is performed to form the metal oxide film 407 that functions as a channel protection film. Thereafter, the resist mask is removed (see Fig. 5(C)). Also, a resist mask for forming the metal oxide film 407 may be formed by an inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced. Etching of the metal oxide film 427 here may be either dry etching or wet etching, or both may be used. For exposure during resist mask formation in the third photolithography process, it is advisable to use ultraviolet light, KrF laser light, or ArF laser light. The channel length L of the transistor formed later is determined by the width of the metal oxide film 407 in the channel length direction that functions as a channel protection film. When performing exposure with a channel length L of less than 25 nm, for example, extreme ultraviolet light with a very short wavelength of several nm to several 10 nm may be used for exposure during resist mask formation in the third photolithography process. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is possible to miniaturize the channel length L of the transistor formed later and increase the operating speed of the circuit. Here, by patterning so that the width of the metal oxide film 407 in the channel length direction is shorter than the width of the oxide semiconductor film 403 in the channel length direction, the source electrode 405a and the drain electrode 405b formed in a later process are in contact with a part of the upper surface of the oxide semiconductor film 403. Therefore, by shortening the width of the metal oxide film 407 in the channel length direction, the channel length of the transistor can be shortened, and the transistor can be made faster and consume less power.

[0105]

[0106]

[0107] Also, in the etching process of this metal oxide film 427, if the etching selectivity between the metal oxide film 427 and the oxide semiconductor film 403 is not sufficient, a part of the region of the oxide semiconductor film 403 that does not overlap with the metal oxide film 427 may be removed. In this case, the film thickness of the region of the oxide semiconductor film 403 that does not overlap with the metal oxide film 427 becomes thin.

[0108] If the oxide semiconductor film 403 is not processed into an island shape in the above process, it may be processed into an island shape simultaneously with the metal oxide film 427 here. By patterning the oxide semiconductor film 403 and the metal oxide film 427 simultaneously in this way, the photolithography process can be reduced. Also, by patterning the oxide semiconductor film 403 and the metal oxide film 427 using the same mask, the side ends in the channel length direction of the oxide semiconductor film 403 and the side ends in the channel length direction of the metal oxide film 407 coincide. Also, in this case, it is preferable to form the gate insulating film 402, the oxide semiconductor film 403, and the metal oxide film 427 continuously without exposing them to the outside air.

[0109] Also, the metal oxide film 427 does not necessarily have to be processed into an island shape. For example, in a later process, an opening may be provided so that a part of the oxide semiconductor film 403 is exposed so that it can be electrically connected to the source electrode 405a and the drain electrode 405b. By adopting such a configuration, the transistor 320 shown in FIG. 3, the transistor 340 shown in FIG. 4(B), the transistor 360 shown in FIG. 4(D), or the transistor 380 shown in FIG. 4(F) can be formed.

[0110] ​​Next, a conductive film for forming a source electrode and a drain electrode (including wiring formed in the same layer) is formed so as to cover the metal oxide film 407 and the oxide semiconductor film 403. As the conductive film used for the source electrode and the drain electrode, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) having the above-described elements as components can be used. Further, a high melting point metal film such as Ti, Mo, or W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be laminated on one or both of the lower side and the upper side of a metal film such as Al or Cu. Also, the conductive film used for the source electrode and the drain electrode may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (Zn O), indium tin oxide alloy (In2O3―SnO2, abbreviated as ITO), indium zinc oxide alloy (In2O3―ZnO), or a material in which these metal oxide materials contain silicon oxide can be used. A resist mask is formed on the conductive film by a fourth photolithography process, and selective etching is performed to form the source electrode 405a and the drain electrode 405b, and then the resist mask is removed (see FIG. 5(D)). When ultraviolet light, KrF laser light, or ArF laser light is used for the exposure during the formation of the resist mask in the third photolithography process, the gap width between the lower end portions of the adjacent source electrode 405a and the drain electrode 405b on the metal oxide film 407 becomes narrow. Therefore, in the fourth photolithography process as well, ultraviolet light or KrF laser light is similarly used. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (Zn O), indium tin oxide alloy (In2O3―SnO2, abbreviated as ITO), indium zinc oxide alloy (In2O3―ZnO), or a material in which these metal oxide materials contain silicon oxide can be used. A resist mask is formed on the conductive film by a fourth photolithography process, and selective etching is performed to form the source electrode 405a and the drain electrode 405b, and then the resist mask

[0111] is removed (see FIG. 5(D)). When ultraviolet light, KrF laser light, or ArF laser light is used for the exposure during the formation of the resist mask in the third photolithography process, the gap width between the lower end portions of the adjacent source electrode 405a and the drain electrode 405b on the metal oxide film 407 becomes narrow. Therefore, in the fourth photolithography process as well, ultraviolet light or KrF laser light is similarly used. A resist mask is formed on the conductive film by a fourth photolithography process, and selective etching is performed to form the source electrode 405a and the drain electrode 405b, and then the resist mask is removed (see FIG. 5(D)). When ultraviolet light, KrF laser light, or ArF laser light is used for the exposure during the formation of the resist mask in the third photolithography process, the gap width between the lower end portions of the adjacent source electrode 405a and the drain electrode 405b on the metal oxide film 407 becomes narrow. Therefore, in the fourth photolithography process as well, ultraviolet light or KrF laser light is similarly used. laser light is similarly used. It is preferable to use laser light or ArF laser light.

[0112] In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, an etching process may be performed using a resist mask formed by a halftone mask, which is an exposure mask in which the transmitted light has a plurality of intensities. The resist mask formed using the halftone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by etching, so it can be used in a plurality of etching processes for processing into different patterns. Therefore, a resist mask corresponding to at least two or more different patterns can be formed by a single halftone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified. Here, since the metal oxide film 407 is provided in the region overlapping with the channel formation region of the oxide semiconductor film 403, damage due to etching of the conductive film (for example, damage by plasma or an etching agent during etching) can be prevented. Thereby, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. .

[0113] Here, since the metal oxide film 407 is provided in the region overlapping with the channel formation region of the oxide semiconductor film 403, damage due to etching of the conductive film (for example, damage by plasma or an etching agent during etching) can be prevented. Thereby, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. 407 is provided, damage due to etching of the above conductive film (for example, damage by plasma or an etching agent during etching) can be prevented. Thereby, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. .

[0114] Next, it is preferable to form an insulating film 409 in contact with the metal oxide film 407 so as to cover the source electrode 405a and the drain electrode 405b (see FIG. 5(E)). The insulating film 409 preferably uses a material capable of forming a charge trapping center at the interface by bringing the metal oxide film 407 into contact with the insulating film 409. Using such a material for the insulating film 409 Thus, since charges are trapped at the interface between the insulating film 409 and the metal oxide film 407, charge trapping at the interface between the metal oxide film 4 07 and the oxide semiconductor film 403 can be sufficiently suppressed.

[0115] As the insulating film 409, an inorganic insulating film is used, such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a aluminum oxynitride film and other oxide insulating films, or a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film and other nitride insulating films in a single layer or a laminate may be used. For example, using a sputtering method, a laminate of a silicon oxide film and a silicon nitride film is formed in order from the side of the metal oxide film 4 07. The insulating film 409 is preferably a film containing components different from those of the oxide semiconductor film 403 or the metal oxide film 407. In addition, in the heat treatment step for the subsequent oxide semiconductor film 403, in order to efficiently remove impurities such as hydrogen and moisture from the metal oxide film 40 7, it is preferable that the insulating film 409 is a silicon oxide film. Further, due to the relationship of being in contact with the metal oxide film 407, it is desirable that the energy gap of the insulating film 409 is larger than the energy gap of the metal oxide film 407

[0116] In addition, if a charge trapping center can be formed at the interface between the insulating film 409 and the metal oxide film 407, it is not necessary to limit the material of the insulating film 409 to the above-mentioned ones. Further, a process for forming a charge trapping center may be performed at the interface between the insulating film 409 and the metal oxide film 407 as well. Examples of such a process include plasma treatment and element addition treatment (such as ion implantation).

[0117] ​​​​​​​Next, it is preferable to perform a second heat treatment on the oxide semiconductor film 403 in a state where it is in contact with the metal oxide film 407 at a part (channel formation region). The temperature of the second heat treatment is preferably 250°C or higher and 700 °C or lower, more preferably 450°C or higher and 600°C or lower. Note that the temperature of the first heat treatment is preferably lower than the strain point of the substrate.

[0118] The second heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (such as argon or helium). However, it is preferable that the atmosphere of the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Also, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, more preferably 7N (99.999 99%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0119] In the second heat treatment, the oxide semiconductor film 403 and the metal oxide film 407 are heated in a state of being in contact with each other. Therefore, oxygen, which is one of the main component materials constituting the oxide semiconductor that may be reduced by the above dehydration (or dehydrogenation) treatment, can be supplied from the metal oxide film 407 containing oxygen to the oxide semiconductor film 403. As a result, the charge trapping centers in the oxide semiconductor film 403 can be reduced. In the above steps, a highly purified and electrically i-type (intrinsic) oxide semiconductor film 403 can be formed. Also, by this heat treatment, impurities in the metal oxide film 407 are simultaneously removed and it can be highly purified.

[0120] In the present embodiment, the second heat treatment is performed after the formation of the insulating film 409. However, the timing of the second heat treatment is not particularly limited as long as it is after the formation of the metal oxide film 407. For example, the second heat treatment may be performed after the formation of the metal oxide film 407. Alternatively, when the insulating film 4 09 is formed by laminating, for example, a silicon oxide film and a silicon nitride film, a second heat treatment is performed after forming the silicon oxide film on the metal acid ide film 407, and then the silicon nitride film may be formed. Alternatively, the second heat treatment may be performed following the first heat treatment, or the second heat treatment may be combined with the first heat treatment, or the first heat treatment may be combined with the second heat treatment.

[0121] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide semiconductor film 403 can be purified to a high purity so that it contains as few impurities as possible other than its main components. In the highly purified oxide semiconductor film 403, carriers derived from donors are extremely few (close to zero), and the carrier concentration is less than 1×10 14 / cm 3 , preferably less than 1×1 0 12 / cm 3 , more preferably less than 1×10 11 / cm 3 .

[0122] The transistor 310 is formed through the above steps (see FIG. 5(E)). The transistor 31 0 intentionally excludes impurities such as hydrogen, moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) from the oxide semiconductor film 403 and is a transistor including the highly purified oxide semiconductor film 403. Therefore, the transistor 310 has suppressed electrical characteristic variations and is electrically stable.

[0123] Also, in the transistor having the metal oxide film 407, the generation of parasitic channels on the back channel side of the oxide semiconductor film 403 can be prevented. Further, in the transistor 310, the generation of parasitic channels on the back channel side of the oxide semiconductor film 403 can be prevented, and the variation of the threshold voltage can be suppressed, so that a transistor with improved reliability can be obtained. Furthermore, in the transistor 310, the generation of parasitic channels on the back channel side of the oxide semiconductor film 403 can be prevented, and the variation of the threshold voltage can be suppressed, so that a transistor with improved reliability can be obtained. In the transistor 310, the generation of parasitic channels on the back channel side of the oxide semiconductor film 403 can be prevented, and the variation of the threshold voltage can be suppressed, so that a transistor with improved reliability can be obtained. In the transistor 310, the generation of parasitic channels on the back channel side of the oxide semiconductor film 403 can be prevented, and the variation of the threshold voltage can be suppressed, so that a transistor with improved reliability can be obtained. In the transistor 310, the generation of parasitic channels on the back channel side of the oxide semiconductor film 403 can be prevented, and the variation of the threshold voltage can be suppressed, so that a transistor with improved reliability can be obtained.

[0124] After forming the insulating film 409, by providing the conductive film 410 in the region overlapping the channel formation region of the oxide semiconductor film 403 on the insulating film 409, the transistor 330 shown in FIG. 4(A) or the transistor 340 shown in FIG. 4(B) can be formed. Further, by adopting a configuration in which the gate electrode 401 and the gate insulating film 402 are not provided, the transistor 350 shown in FIG. 4(C) or the transistor 360 shown in FIG. 4(D) can be formed. The conductive film 410 can be formed of the same material and in the same process as the gate electrode 401. By providing the conductive film 410 at a position overlapping the channel formation region of the oxide semiconductor film 403, in the bias - thermal stress test (hereinafter referred to as the BT test) for examining the reliability of the transistor 340, the change amount of the threshold voltage of the transistor 340 before and after the BT test can be further reduced. Note that the potential of the conductive film 410 may be the same as that of the gate electrode 401 or different, and it can also function as a second gate electrode. Also, the potential of the conductive film 410 may be GND, 0V, or in a floating state. After forming the insulating film 409, by providing the conductive film 410 in the region overlapping the channel formation region of the oxide semiconductor film 403 on the insulating film 409, the transistor 330 shown in FIG. 4(A) or the transistor 340 shown in FIG. 4(B) can be formed. After forming the insulating film 409, by providing the conductive film 410 in the region overlapping the channel formation region of the oxide semiconductor film 403 on the insulating film 409, the transistor 330 shown in FIG. 4(A) or the transistor 340 shown in FIG. 4(B) can be formed. Furthermore, by adopting a configuration in which the gate electrode 401 and the gate insulating film 402 are not provided, the transistor 350 shown in FIG. 4(C) or the transistor 360 shown in FIG. 4(D) can be formed. Furthermore, by adopting a configuration in which the gate electrode 401 and the gate insulating film 402 are not provided, the transistor 350 shown in FIG. 4(C) or the transistor 360 shown in FIG. 4(D) can be formed. The conductive film 410 can be formed of the same material and in the same process as the gate electrode 401. The conductive film 410 can be formed of the same material and in the same process as the gate electrode 401. By providing the conductive film 410 at a position overlapping the channel formation region of the oxide semiconductor film 403, in the bias - thermal stress test (hereinafter referred to as the BT test) for examining the reliability of the transistor 340, the change amount of the threshold voltage of the transistor 340 before and after the BT test can be further reduced. By providing the conductive film 410 at a position overlapping the channel formation region of the oxide semiconductor film 403, in the bias - thermal stress test (hereinafter referred to as the BT test) for examining the reliability of the transistor 340, the change amount of the threshold voltage of the transistor 340 before and after the BT test can be further reduced. In the bias - thermal stress test (hereinafter referred to as the BT test) for examining the reliability of the transistor 340, the change amount of the threshold voltage of the transistor 340 before and after the BT test can be further reduced. Note that the potential of the conductive film 410 may be the same as that of the gate electrode 401 or different, and it can also function as a second gate electrode. Note that the potential of the conductive film 410 may be the same as that of the gate electrode 401 or different, and it can also function as a second gate electrode. Also, the potential of the conductive film 410 may be GND, 0V, or in a floating state.

[0125] Note that although not shown, a protective insulating film may be further formed to cover the transistor 310. This is acceptable. As the protective insulating film, a silicon nitride film, a silicon oxynitride film, aluminum nitride, or the like can be used.

[0126] Also, a planarizing insulating film may be provided on the transistor 310. As the planarizing insulating film, organic materials having heat resistance such as acrylic, polyimide, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that a plurality of insulating films formed of these materials may be laminated.

[0127] As described above, in the transistor according to this embodiment, a metal oxide film made of the same components as the oxide semiconductor film is laminated on the upper surface portion of the oxide semiconductor film. By disposing the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, it is possible to sufficiently suppress charges and the like that may be generated due to the operation of the semiconductor device from being trapped at the interface between the oxide semiconductor film and the metal oxide film. As a result, the influence of charges on the oxide semiconductor film can be mitigated, and thus threshold voltage fluctuations of the transistor due to charge trapping at the oxide semiconductor film interface can be suppressed.

[0128] Furthermore, an insulating film containing components different from those of the metal oxide film and the oxide semiconductor film is provided in contact with the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film. In this way, an insulator composed of a material capable of forming a charge trapping center at the interface is used to form the metal oxide film. By causing it to exist in a state of contact with, as compared with the interface between the oxide semiconductor film and the metal oxide film the above-described charges can be preferentially trapped at the interface between the metal oxide film and the insulator. This makes it possible to further mitigate the influence of charges on the oxide semiconductor film, and thus more effectively suppress the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface.

[0129] In addition, the oxide semiconductor film used for the active layer of the transistor is heat-treated to remove impurities such as hydrogen, moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) from the oxide semiconductor, and at the same time, the main component material of the oxide semiconductor that decreases due to the impurity removal process is supplied with oxygen, thereby purifying the oxide semiconductor film to a high purity and making it electrically i-type (intrinsic). A transistor including such a highly purified oxide semiconductor film has suppressed electrical property variations and is electrically stable.

[0130] When charges are trapped at the interface of the oxide semiconductor film, the threshold voltage of the transistor shifts (for example, when positive charges are trapped on the back channel side, the threshold voltage of the transistor shifts in the negative direction). As one of the factors for such charge trapping, a model of the movement and trapping of cations (or the atoms causing them) can be assumed. And in a transistor using an oxide semiconductor, hydrogen atoms can be considered as such a cation source. In the disclosed invention, a highly purified oxide semiconductor is used, and since this adopts a configuration in contact with the laminated structure of the metal oxide film and the insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that​​​ The model is considered to be valid when the ionization rate of hydrogen is about 10%, for example.

[0131] As described above, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. Therefore, a highly reliable semiconductor device can be provided.

[0132] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0133] (Embodiment 2) A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor exemplified in Embodiment 1. Further, part or all of the driving circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0134] In FIG. 6(A), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a first substrate 4001, and is sealed by a second substrate 4006. In FIG. 6(A), a scanning line driving circuit 4004 and a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film are mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Further, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from FPC (Flexible printed circuit) 4018a and FPC 4018b. (A), uit) 4018a, FPC 4018b.

[0135] ​​​​​​​​In FIGS. 6(B) and 6(C), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a first substrate 4001 and a scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005, and the second substrate 4006. In FIGS. 6(B) and 6(C), a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 6(B) and 6(C), various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from an FPC 4018. Also, in FIGS. 6(B) and 6(C), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, a TAB (Tape Automated Bonding) method, or the like can be used. FIG. 6(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method.

[0136]

[0137] ​​​​​​​​​​, FIG. 6(B) is an example of implementing the signal line driving circuit 4003 by the COG method, and FIG. 6( C) is an example of implementing the signal line driving circuit 4003 by the TAB method.

[0138] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller or the like is mounted on the panel.

[0139] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module to which a connector, for example, an FPC or a TAB tape or a TCP is attached, a module provided with a printed wiring board at the tip of the TAB tape or the TCP or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG method shall all be included in the display device.

[0140] Further, the pixel portion and the scanning line driving circuit provided on the first substrate have a plurality of transistors, and the transistors shown as an example in Embodiment 1 can be applied.

[0141] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. Also, a display medium whose contrast changes by an electric action, such as electronic ink, can also be applied.

[0142] One form of the semiconductor device will be described with reference to FIGS. 7 to 9. FIGS. 7 to 9 correspond to the cross-sectional view taken along M-N of FIG. 6 (B).

[0143] As shown in FIGS. 7 to 9, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 401 6, and the connection terminal electrodes 4015 and the terminal electrodes 4016 are electrically connected via an anisotropic conductive film 4019 to the terminals of the FPC 4018. The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode

[0144] 4016 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 4010 and 4011. The pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004

[0145] each have a plurality of transistors. In FIGS. 7 to 9, the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are exemplified. In the present embodiment, the transistors shown in Embodiment 1 can be applied as the transistors 4010 and 4011. The transistors 4010 and 4011 have suppressed electrical characteristic variations and are electrically stable. Therefore, it is possible to provide a highly reliable semiconductor device as the semiconductor device of the present embodiment shown in FIGS. 7 to

[0146] 9. The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used. can be provided.

[0147] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used.

[0148] Fig. 7 shows an example of a liquid crystal display device using a liquid crystal element as a display element. In Fig. 7, the liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Insulating films 4032 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4 006 side, and the first electrode layer 4030 and the second electrode layer 4031 are stacked via the liquid crystal layer 4008 .

[0149] In addition, the columnar spacer 4035 is obtained by selectively etching an insulating film and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that a spherical spacer may be used.

[0150] When a liquid crystal element is used as a display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a polymer liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0151] In addition, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, the ​ Since it is not necessary to provide an alignment film, rubbing treatment is also unnecessary, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0152] Also, the resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, more preferably 1×10 12 Ω·cm or more. Note that the resistivity values in this specification are the values measured at 20°C.

[0153] The size of the holding capacitor provided in the liquid crystal display device is set so as to be able to hold charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. By using a transistor having a high-purity oxide semiconductor film, it is sufficient to provide a holding capacitor having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel.

[0154] The transistor using the highly purified oxide semiconductor film used in this embodiment can lower the current value (off-current value) in the off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, and the effect of suppressing power consumption is achieved.

[0155] Also, the transistor using the highly purified oxide semiconductor film used in this embodiment Since a relatively high field-effect mobility can be obtained, high-speed driving is possible. Therefore, by using the transistor in the pixel portion of the liquid crystal display device, a high-quality image can be provided. Also, since the transistor can be manufactured separately for the drive circuit portion or the pixel portion on the same substrate, the number of components of the liquid crystal display device can be reduced. Moreover, since the transistor can be manufactured separately for the drive circuit portion or the pixel portion on the same substrate, the number of components of the liquid crystal display device can be reduced. Also, since the transistor can be manufactured separately for the drive circuit portion or the pixel portion on the same substrate, the number of components of the liquid crystal display device can be reduced.

[0156] For the liquid crystal display device, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. Plane-Switching) mode, an FFS (Fringe Field Swi tching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liqu id Crystal) mode, an AFLC (AntiFerroelectric Li quid Crystal) mode, etc. can be used.

[0157] Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in the liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Examples of the vertical alignment mode include, but are not limited to, the MVA (Multi-domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, the ASV (Advanced Super View) mode, etc. Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in the liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in the liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in the liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in the liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Also, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in the liquid crystal display panel, and it is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. For the liquid crystal display device, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. This can be achieved. Also, pixels can be divided into several regions (sub-pixels), and each a multi-domain method or multi-domain design in which molecules are arranged to fall in different directions can be used.

[0158] In addition, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source.

[0159] Moreover, as the backlight, a plurality of light-emitting diodes (LEDs) can be used to perform a time-division display method (field-sequential driving method). By applying the field-sequential driving method, color display can be performed without using a color filter.

[0160] In addition, the display method in the pixel portion can use a progressive method, an interlace method, etc. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white ), or RGB with one or more additional colors such as yellow, cyan, and magenta. Also, the size of the display area may be different for each dot of the color element. However, the present invention is not limited to a display device for color display, and can also be applied to a display device for monochrome display.

[0161] In addition, as a display element included in the display device, a light-emitting element that utilizes electroluminescence ​​​The light-emitting element that utilizes electroluminescence can be applied to a light-emitting material They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0162] In an organic EL element, electrons and positive electrodes are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0163] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized light emission that utilizes organic EL elements. do.

[0164] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission, bottom emission, and side emission. There are light emitting devices with a double-sided emission structure that emits light from the side, and light emitting devices with any emission structure are suitable. can be used.

[0165] Fig. 8 shows an example of a light-emitting device using a light-emitting element as a display element. The light-emitting element, which is the display element 4513 is electrically connected to a transistor 4010 provided in the pixel portion 4002 . The structure of the light-emitting element 4513 is a laminated structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the shown structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of light extracted from the light-emitting element 4513 and so on.

[0166] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, using a photosensitive resin material, an opening is formed on the first electrode layer 4030, and it is preferably formed such that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0167] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers laminated. Either way is acceptable.

[0168] A protective film may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4513. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC (Diamond-Like Carbon) film, etc. can be formed. Further, a filling material 4514 is provided and sealed in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. In this way, it has high airtightness so as not to be exposed to the outside air, and is packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing . ​​is preferred.

[0169] As the filler 4514, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. Alternatively, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter can be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection. In addition, as a display device, it is also possible to provide an electronic paper that drives electronic ink. The electronic paper is also called an electrophoretic display device, and has the advantages of being as easy to read as paper, having lower power consumption than other display devices, and being thin and light in shape. The electrophoretic display device can be in various forms, but is a microcapsule containing a first particle having a positive charge and a second particle having a negative charge, which is dispersed in a solvent or a solute in plural. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye, and when there is no electric field. is good.

[0170] Also, if necessary, an optical film such as a polarizing plate, or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses the reflected light due to surface irregularities and reduces the reflection can be performed. ), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses the reflected light due to surface irregularities and reduces the reflection can be performed. Also, it is possible to provide an electronic paper that drives electronic ink as a display device. The electronic paper is also called an electrophoretic display device, and has the advantages of being as easy to read as paper, having lower power consumption than other display devices, and being thin and light in shape. The electrophoretic display device can be in various forms, but is a microcapsule containing a first particle having a positive charge and a second particle having a negative charge, which is dispersed in a solvent or a solute in plural. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye, and when there is no electric field.

[0171] In addition, as a display device, it is also possible to provide an electronic paper that drives electronic ink. The electronic paper is also called an electrophoretic display device, and has the advantages of being as easy to read as paper, having lower power consumption than other display devices, and being thin and light in shape. The electronic paper is also called an electrophoretic display device, and has the advantages of being as easy to read as paper, having lower power consumption than other display devices, and being thin and light in shape. The electrophoretic display device can be in various forms, but is a microcapsule containing a first particle having a positive charge and a second particle having a negative charge, which is dispersed in a solvent or a solute in plural. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye, and when there is no electric field. is possible.

[0172] The electrophoretic display device can be in various forms, but is a microcapsule containing a first particle having a positive charge and a second particle having a negative charge, which is dispersed in a solvent or a solute in plural. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye, and when there is no electric field. and a second particle having a negative charge are dispersed in a solvent or a solute in plural, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. The electrophoretic display device can be in various forms, but is a microcapsule containing a first particle having a positive charge and a second particle having a negative charge, which is dispersed in a solvent or a solute in plural. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye, and when there is no electric field. The first particle or the second particle contains a dye, and when there is no electric field. It does not move. Also, the color of the first particle and the color of the second particle are different (including colorless). Let it be so.

[0173] In this way, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0174] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is also possible by using particles having a color filter or a dye.

[0175] Note that the first particle and the second particle in the microcapsule may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0176] Also, as an electronic paper, a display device using a twist ball display method can also be applied. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer, which are electrode layers using the spherical particles as display elements, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0177] FIG. 9 shows an active matrix type electronic paper as one form of a semiconductor device. The electronic paper in FIG. 9 is an example of a display device using the twist ball display method.

[0178] ​​​​​​A first electrode layer 4030 connected to the transistor 4010 and provided on the second substrate 4006 Between them and the second electrode layer 4031, there are provided spherical particles 4613 including a black region 4615a and a white region 4615b and having a cavity 4612 filled with liquid around them and the periphery of the spherical particles 4613 is filled with a filler 4614 such as resin. The second electrode layer 4031 corresponds to a common electrode (opposing electrode). The second electrode layer 4031 is electrically connected to a common potential line

[0179] In FIGS. 7 to 9, as the first substrate 4001 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a translucent plastic substrate such as a plastic substrate can be used. As the plastic, an FRP (Fiberglass Reinforced Plastics) plate, a PVF (polyvinyl fluoride ) film, a polyester film or an acrylic resin film can be used Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used

[0180] The insulating layer 4021 can be formed using an inorganic insulating material or an organic insulating material Note that when using an organic insulating material having heat resistance such as an acrylic resin, a polyimide, a benzocyclobutene resin, a polyamide, or an epoxy resin it is suitable as a planarizing insulating film. Also, in addition to the above organic insulating materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that an insulating layer may be formed by laminating a plurality of insulating films formed of these materials ​​​​

[0181] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, spin coating method, dipping method, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.) and the like can be applied. The insulating layer 4021 can also be formed using roll coating, curtain coating, knife coating, etc.

[0182] The display device performs display by transmitting light from a light source or a display element. Therefore, all thin films such as a substrate, an insulating film, and a conductive film provided in the pixel portion through which light passes are made translucent with respect to light in the wavelength region of visible light.

[0183] In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, translucency and reflectivity may be selected depending on the direction of the light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0184] The first electrode layer 4030 and the second electrode layer 4031 can be made of a conductive material having translucency such as indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

[0185] Further, the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium ( ​​​​​​Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc. metals , or one or more kinds thereof can be formed using an alloy thereof, or a nitride thereof. It can be done.

[0186] Further, as the first electrode layer 4030 and the second electrode layer 4031, it can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated system conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer composed of two or more of aniline, pyrrole and thiophene or a derivative thereof Conductors and the like can be mentioned.

[0187] In addition, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0188] By applying the transistor exemplified in Embodiment 1 as described above, a highly reliable semiconductor device can be provided. Note that the transistor exemplified in Embodiment 1 is not limited to the semiconductor device having the above-described display function, but also includes a power device mounted on a power supply circuit, a semiconductor integrated circuit such as an LSI , and can be applied to semiconductor devices having various functions such as a semiconductor device having an image sensor function for reading information of an object.

[0189] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0190] (Embodiment 3) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, cameras such as digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large gaming machines such as pachinko machines. Examples of electronic devices equipped with the semiconductor device described in the above embodiment will be described. Figure 10(A) shows a notebook personal computer, which is composed of a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable notebook personal computer can be obtained. Figure 10(B) shows a portable information terminal (PDA). The main body 3021 is provided with a display unit 3023, an external interface 3025, operation buttons 3024, etc. Also, there is a stylus 3022 as an accessory for operation. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a more reliable portable information terminal (PDA) can be obtained. Figure 10(C) shows an example of an e - book. For example, the e - book 2700 is composed of two housings, a housing 2701 and a housing 2703.

[0191] Figure 10(A) is a notebook personal computer, which is composed of a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable notebook personal computer can be obtained. Figure 10(A) is a notebook personal computer, which is composed of a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable notebook personal computer can be obtained. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable notebook personal computer can be obtained.

[0192] Figure 10(B) is a portable information terminal (PDA). The main body 3021 is provided with a display unit 3023, an external interface 3025, operation buttons 3024, etc. Also, there is a stylus 3022 as an accessory for operation. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a more reliable portable information terminal (PDA) can be obtained. Figure 10(B) is a portable information terminal (PDA). The main body 3021 is provided with a display unit 3023, an external interface 3025, operation buttons 3024, etc. Also, there is a stylus 3022 as an accessory for operation. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a more reliable portable information terminal (PDA) can be obtained. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a more reliable portable information terminal (PDA) can be obtained. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a more reliable portable information terminal (PDA) can be obtained.

[0193] Figure 10(C) shows an example of an e - book. For example, the e - book 2700 is composed of two housings, a housing 2701 and a housing 2703. Figure 10(C) shows an example of an e - book. For example, the e - book 2700 is composed of two housings, a housing 2701 and a housing 2703. ​​​03 is integrated with the shaft portion 2711 and can perform an opening / closing operation with the shaft portion 2711 as the axis. With such a configuration, it becomes possible to perform operations similar to those of a paper book.

[0194] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration of displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 10(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 10(C)). By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable electronic book 2700 can be obtained.

[0195] Also, FIG. 10(C) shows an example in which the housing 2701 is provided with an operation unit and the like. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, and the like are provided. The operation keys 2723 can be used to turn the page. Note that the housing may be configured to be provided with a keyboard, a pointing device, or the like on the same surface as the display unit. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion portion, or the like. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0196] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is also possible to purchase and download desired book data and the like from an electronic book server. ​

[0197] Figure 10(D) shows a mobile phone, which is composed of two casings, namely casing 2800 and casing 2801. Casing 2801 is equipped with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. In addition, casing 2800 is equipped with a solar cell 2810 for charging the portable information terminal, an external memory slot 2811, etc. Also, the antenna is built inside casing 2801. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable mobile phone can be obtained.

[0198] In addition, the display panel 2802 is equipped with a touch panel, and a plurality of operation keys 2805 shown as video displays in Figure 10(D) are indicated by dotted lines. Note that a boost circuit for boosting the voltage generated by the solar cell 2810 to the voltage required for each circuit is also implemented.

[0199] The display direction of the display panel 2802 changes appropriately according to the usage form. Also, since the camera lens 2807 is provided on the same surface as the display panel 2802, a video phone is possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, and video calls, recording, playback, etc. are possible. Furthermore, the casings 2800 and 2801 can be slid and changed from the unfolded state shown in Figure 10(D) to an overlapping state, enabling miniaturization suitable for portability.

[0200] The external connection terminal 2808 is connected to various cables such as an AC adapter and a USB cable. ​​​​​​​​It is possible and capable of charging and data communication with a personal computer or the like. Also , a recording medium can be inserted into the external memory slot 2811 to support larger amounts of data storage and transfer .

[0201] In addition to the above functions, it may be provided with an infrared communication function, a television receiving function, etc. as well.

[0202] FIG. 10(E) shows a digital video camera, which is composed of a main body 3051, a display unit (A) 3057 , an eyepiece 3053, an operation switch 3054, a display unit (B) 3055, a battery 3056 , etc. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable digital video camera can be obtained.

[0203] FIG. 10(F) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display images. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable television device can be obtained.

[0204] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control operation device. Also, the remote control operation device may be configured to be provided with a display unit for displaying information output from the remote control operation device itself.

[0205] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver It can receive general TV broadcasts, and can also be connected to a communication network via a modem, either wired or wireless, to enable one-way (sender to receiver) or two-way information communication (between the sender and the receiver, or between receivers, etc.).

[0206] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Explanation of Reference Numerals

[0207] 310 Transistor 320 Transistor 330 Transistor 340 Transistor 350 Transistor 360 Transistor 370 Transistor 380 Transistor 390 Transistor 400 Substrate 401 Gate Electrode 402 Gate Insulating Film 403 Oxide Semiconductor Film 404 Metal Oxide Film 405a Source Electrode 405b Drain Electrode 407 Metal Oxide Film 409 Insulating Film 410 Conductive Film 419 Protective Insulating Film 427 Metal Oxide Film 500 Transistor 2700 E-book 2701 Housing 2703 Housing 2705 Display Unit 2707 Display Unit 2711 Shaft Portion 2721 Power Supply 2723 Operation Key 2725 Speaker​​​ 2800 housing 2801 housing 2802 display panel 2803 speaker 2804 microphone 2805 operation key 2806 pointing device 2807 camera lens 2808 external connection terminal 2810 solar cell 2811 external memory slot 3001 main body 3002 housing 3003 display unit 3004 keyboard 3021 main body 3022 stylus 3023 display unit 3024 operation button 3025 external interface 3051 main body 3053 eyepiece 3054 operation switch 3055 display unit (B) 3056 battery 3057 display unit (A) 4001 substrate 4002 pixel section 4003 signal line drive circuit 4004 scanning line drive circuit 4005 sealing material 4006 substrate 4008 liquid crystal layer 4010 transistor 4011 transistor 4013 liquid crystal element 4015 connection terminal electrode 4016 terminal electrode 4018 FPC 4018a FPC 4018b FPC 4019 anisotropic conductive film 4021 insulating layer 4030 electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4035 Spacer 4510 Partition wall 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 4612 Cavity 4613 Spherical particle 4614 Filling material 4615a Black region 4615b White region 9600 Television device 9601 Housing 9603 Display unit 9605 Stand

Claims

1. a first transistor; and a second transistor having a top gate structure, the semiconductor device comprising: a first conductive layer; a first insulating layer on the first conductive layer; a first oxide semiconductor layer having a channel formation region of the first transistor on the first insulating layer; a second oxide semiconductor layer having a channel formation region of the second transistor on the first insulating layer; an oxide layer having a region in contact with the upper surface of the first oxide semiconductor layer and a region in contact with the upper surface of the second oxide semiconductor layer; a second conductive layer having a region functioning as a gate electrode of the second transistor; a third conductive layer having a region overlapping the second oxide semiconductor layer; a fourth conductive layer having a region overlapping the first oxide semiconductor layer; a fifth conductive layer having a region overlapping the first oxide semiconductor layer, the semiconductor device comprising: the oxide layer having a region in contact with the channel formation region of the first transistor; the first conductive layer having a region overlapping the channel formation region of the first transistor; the second conductive layer having a region overlapping the channel formation region of the second transistor via a second insulating layer; the region of the third conductive layer overlapping the second oxide semiconductor layer having a first region in contact with the upper surface of the second oxide semiconductor layer and a second region not in contact with the upper surface of the second oxide semiconductor layer; the first region having a region overlapping the first conductive layer; the region of the fourth conductive layer overlapping the first oxide semiconductor layer having a third region in contact with the upper surface of the first oxide semiconductor layer and a fourth region not in contact with the upper surface of the first oxide semiconductor layer; the third region having a region overlapping the first conductive layer; the fifth conductive layer having a region overlapping the channel formation region of the first transistor.

2. a first transistor; and a second transistor having a top gate structure, the semiconductor device comprising: a first conductive layer; a first insulating layer on the first conductive layer; a first oxide semiconductor layer having a channel formation region of the first transistor on the first insulating layer; a second oxide semiconductor layer having a channel formation region of the second transistor on the first insulating layer; an oxide layer having a region in contact with the upper surface of the first oxide semiconductor layer and a region in contact with the upper surface of the second oxide semiconductor layer; A second conductive layer having a region that functions as a gate electrode of the second transistor; A third conductive layer having a region overlapping with the second oxide semiconductor layer; A fourth conductive layer having a region overlapping with the first oxide semiconductor layer; A fifth conductive layer having a region overlapping with the first oxide semiconductor layer, and The oxide layer has a region in contact with a channel formation region of the first transistor; The first conductive layer has a region overlapping with a channel formation region of the first transistor; The second conductive layer has a region overlapping with a channel formation region of the second transistor via a second insulating layer; The region of the third conductive layer overlapping with the second oxide semiconductor layer has a first region in contact with the upper surface of the second oxide semiconductor layer and a second region not in contact with the upper surface of the second oxide semiconductor layer; The first region has a region overlapping with the first conductive layer; The region of the fourth conductive layer overlapping with the first oxide semiconductor layer has a third region in contact with the upper surface of the first oxide semiconductor layer and a fourth region not in contact with the upper surface of the first oxide semiconductor layer; The third region has a region overlapping with the first conductive layer; The fifth conductive layer has a region overlapping with a channel formation region of the first transistor; The first oxide semiconductor layer is In-O; The second oxide semiconductor layer is In-O, a semiconductor device.

3. In claim 1 or claim 2, The third conductive layer has a region in contact with the upper surface of the oxide layer; The third conductive layer does not have a region in contact with a side surface of the second oxide semiconductor layer, a semiconductor device.

Images