Printed wiring board

The printed wiring board design with a solder resist groove and metal protruding member addresses the issue of large substrate size and warpage by minimizing dam area and underfill outflow, improving component mounting and reliability.

JP2025110131APending Publication Date: 2025-07-28IBIDEN CO LTD
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
JP2024003890
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-01-15
Publication Date
2025-07-28

AI Technical Summary

Technical Problem

Existing printed wiring boards with multiple dams along the chip side surfaces require larger substrate sizes, leading to increased warpage and decreased connection reliability, making it difficult to mount electronic components effectively.

Method used

A printed wiring board design featuring a solder resist layer with a groove and a metal protruding member in the groove, which reduces the need for extensive dam formation, thereby minimizing the board's size and suppressing warpage while preventing underfill outflow.

Benefits of technology

The design effectively reduces the printed wiring board's size, suppresses warpage, and enhances connection reliability by preventing underfill outflow, ensuring stable mounting of electronic components.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 2025110131000001_ABST
    Figure 2025110131000001_ABST
Patent Text Reader

Abstract

To provide a printed wiring board of high quality.SOLUTION: A printed wiring board has: a top resin insulation layer; a top conductor layer formed on the top resin insulation layer and including an electrode group formed of a plurality of electrodes for mounting an electronic component; a soler resist layer formed on the top resin insulation layer and the top conductor layer, and having a groove substantially surrounding the electrode group; and a metallic projection member formed in the groove. The projection member has a top part, which protrudes upward from a top surface of the solder resist layer.SELECTED DRAWING: Figure 2
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The technology disclosed by this specification relates to a printed wiring board.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having a rectangular chip provided in a mounting area on a substrate and a plurality of dams.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] The plurality of dams in Patent Document 1 are formed along the side surface of the chip, and a predetermined interval is provided between adjacent dams. In Patent Document 1, since a plurality of dams are formed, it is considered that the size of the substrate has to be increased. If the size of the substrate is large, it is considered that the warpage of the substrate is likely to increase. It is considered difficult to mount electronic components on the substrate. It is considered that the connection reliability between the substrate and the electronic components on the substrate is likely to decrease.

Means for Solving the Problems

[0005] The printed wiring board of the present invention includes a top resin insulating layer, a top conductor layer formed on the top resin insulating layer and including a group of electrodes formed of a plurality of electrodes for mounting electronic components, a solder resist layer formed on the top resin insulating layer and the top conductor layer and having a groove substantially surrounding the group of electrodes, and a metal protruding member formed in the groove. The protruding member has a top, and the top protrudes above the upper surface of the solder resist layer.

[0006] The printed wiring board according to an embodiment of the present invention includes a solder resist layer having a groove and a protruding member in the groove. Both the protruding member and the groove can prevent the outflow of underfill. The embodiment can further prevent the outflow of underfill. Since the protruding member is located in the groove, the embodiment can reduce the area for forming a dam. As a result, the embodiment can reduce the size of the printed wiring board. The warpage of the printed wiring board is suppressed.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Embodiments for Carrying Out the Invention

[0008] [Embodiment] FIG. 1 is a plan view showing a printed wiring board 2 according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. As shown in FIGS. 1 and 2, the printed wiring board 2 has a top resin insulating layer 20, a top conductor layer 30, a solder resist layer 60, and a dam 80. The dam 80 is formed of a groove 70 formed in the solder resist layer 60 and a metal protruding member 50 formed in the groove 70. The printed wiring board 2 may have a build-up layer. In that case, the top resin insulating layer 20 and the top conductor layer 30 form part of the build-up layer.

[0009] As shown in FIG. 1, the top conductor layer 30 has electrodes 32, 34, 36 for mounting electronic components. An electrode group is formed by a plurality of electrodes 34. A first electronic component is mounted on the printed wiring board 2 via the electrode 34. A second electronic component is mounted on the printed wiring board 2 via the electrode 32. A third electronic component is mounted on the printed wiring board 2 via the electrode 36. Each of the electrodes 32, 34, 36 is exposed by openings 62, 64, 66 formed in the solder resist layer 60. The electrode group formed by the plurality of electrodes (electrodes for mounting the first electronic component) 34 is surrounded by the dam 80. The electrodes 32, 36 are disposed outside the dam 80.

[0010] The top resin insulating layer 20 is formed using a thermosetting resin. The material of the top resin insulating layer 20 may be a photocurable resin. The top resin insulating layer 20 may contain inorganic particles such as silica. The top resin insulating layer 20 may contain a reinforcing material such as glass cloth.

[0011] The uppermost conductor layer 30 is formed on the uppermost resin insulating layer 20. The uppermost conductor layer 30 has electrodes 32, 34, 36 and connection wirings 33, 37. The electrode (electrode for the second electronic component) 32 is connected to one end of the connection wiring 33. The electrode (first electrode for the first electronic component) 34 is connected to the other end of the connection wiring 33. The electrode (second electrode for the first electronic component) 34 is connected to one end of the connection wiring 37. The electrode (electrode for the third electronic component) 36 is connected to the other end of the connection wiring 37. The electrodes 32, 34 are electrically connected via the connection wiring 33. The electrodes 34, 36 are electrically connected via the connection wiring 37. The uppermost conductor layer 30 is mainly formed of copper. The uppermost conductor layer 30 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a.

[0012] Data is sent from one electronic component to another via the connection wirings 33, 37. The connection wiring 33 is a wiring for sending data from the first electronic component to the second electronic component. The connection wiring 37 is a wiring for sending data from the first electronic component to the third electronic component.

[0013] The solder resist layer 60 is formed on the uppermost conductor layer 30 and the uppermost resin insulating layer 20. The solder resist layer 60 is formed using, for example, a photocurable resin. The solder resist layer 60 has openings 62, 64, 66 that expose the respective electrodes 32, 34, 36. The opening 62 exposes the electrode (electrode for the second electronic component) 32. The opening 64 exposes the electrode (electrode for the first electronic component) 34. The opening 66 exposes the electrode (electrode for the third electronic component) 36. The solder resist layer 60 has a first layer 60a on the uppermost resin insulating layer 20 and the uppermost conductor layer 30 and a second layer 60b on the first layer 60a. The solder resist layer 60 has a groove 70 that substantially surrounds an electrode group formed by the plurality of electrodes 34. The groove 70 surrounds all the electrodes (electrodes for the first electronic component) 34. The groove 70 penetrates the second layer 60b. The bottom of the groove 70 exposes the first layer 60a.

[0014] The protruding member 50 is formed in the groove 70. The protruding member 50 is formed on the first layer 60a that is exposed from the groove 70. The top 52 of the protruding member 50 protrudes above the upper surface 61 of the solder resist layer 60. The cross-sectional shape of the protruding member 50 is substantially rectangular or substantially trapezoidal. When the cross-sectional shape is trapezoidal, the protruding member 50 becomes thinner toward the top 52. The protruding member 50 is formed of metal. The protruding member 50 is mainly formed of copper. The protruding member 50 is formed of a seed layer 50a and an electrolytic plating layer 50b on the seed layer 50a. The width W1 of the groove 70 is larger than the width W2 of the protruding member 50. The width W2 is measured on the first layer 60a. A dam 80 is formed by the groove 70 and the protruding member 50. The dam 80 prevents the outflow of the underfill.

[0015] [Method for manufacturing the printed wiring board 2 of the embodiment] Figs. 3A to 3D show a method for manufacturing the printed wiring board 2 of the embodiment. Figs. 3A to 3D are cross-sectional views. The uppermost conductor layer 30 is formed on the upper surface of the uppermost resin insulating layer 20 by the semi-additive method. The uppermost conductor layer 30 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The uppermost conductor layer 30 has electrodes 32, 34, 36 and connection wirings 33, 37. A dry film for the first layer 60a is laminated on the uppermost resin insulating layer 20 and the uppermost conductor layer 30. The dry film is cured. The first layer 60a is formed. The intermediate substrate 3 shown in Fig. 3A is obtained. The dry film for forming the first layer 60a may be of a photocuring type or a thermosetting type. The first layer 60a may be formed by applying a resin.

[0016] As shown in Fig. 3B, a dry film 60D for the second layer 60b is laminated on the first layer 60a. For example, the dry film 60D is of a photocuring type.

[0017] As shown in FIG. 3C, by exposure and development, a groove 70 is formed that penetrates the dry film 60D for the second layer 60b and reaches the first layer 60a. At this time, since the first layer 60a is cured, the bottom of the groove 70 is formed by the first layer 60a. Then, the dry film 60D is cured. The second layer 60b is formed. A solder resist layer 60 having the groove 70 is formed. The planar shape of the groove 70 is substantially frame-shaped. The groove 70 may be a cavity within the second layer 60b. In that case, the bottom of the groove 70 is formed by the second layer 60b. The groove 70 may be a cavity within the solder resist layer 60. In that case, the groove 70 completely penetrates the second layer 60b and penetrates a part of the first layer 60a. Further, the bottom of the groove 70 is formed by the first layer 60a. The dry film 60D for forming the second layer 60b may be of a thermosetting type. When the dry film 60D is of a thermosetting type, for example, the groove 70 is formed by a laser. An example of a method for controlling the bottom of the groove 70 (a method for controlling the depth of the groove 70) is the number of laser shots. The second layer 60b may be formed by applying a resin.

[0018] A seed layer 50a is formed on the solder resist layer 60. The seed layer 50a is formed on the second layer 60b and the groove 70. The seed layer 50a on the groove 70 includes a seed layer on the side wall of the groove 70 and a seed layer on the bottom surface of the groove 70. A plating resist is formed on the seed layer 50a. The plating resist has an opening for forming the protruding member 50. The opening exposes the seed layer 50a on the bottom surface of the groove 70. The opening for forming the protruding member 50 is entirely within the groove 70. An electrolytic plating layer 50b is formed on the seed layer 50a exposed from the plating resist by electrolytic plating. The plating resist is removed. The seed layer 50a exposed from the electrolytic plating layer 50b is removed. A protruding member 50 having a top 52 is formed as shown in FIG. 3D. The planar shape of the protruding member 50 is substantially frame-shaped. A dam 80 is formed by the groove 70 and the protruding member 50. The planar shape of the dam 80 is substantially frame-shaped.

[0019] Openings 62, 64, 66 are formed that penetrate the solder resist layer 60 using a laser and reach the electrodes 32, 34, 36. The electrodes 32, 34, 36 are exposed by the openings 62, 64, 66. A printed wiring board 2 is obtained.

[0020] The printed wiring board 2 of the embodiment has a groove 70 and a dam 80 formed by a protruding member 50 in the groove 70. Both the protruding member 50 and the groove 70 can prevent the outflow of underfill. The embodiment can further prevent the outflow of underfill. Since the protruding member 50 is located in the groove 70, the embodiment can reduce the area for forming the dam 80. The embodiment can reduce the size of the printed wiring board 2. The warping of the printed wiring board 2 is suppressed.

[0021] In the embodiment, the electrodes 32, 34 are electrically connected via a connection wiring 33. The electrodes 34, 36 are electrically connected via a connection wiring 37. The path connecting the two electrodes does not have a via conductor and a wiring under the uppermost resin insulating layer 20. The two electrodes can be connected by a short path. The embodiment can reduce transmission loss.

[0022] In the embodiment, the protruding member 50 is formed on the first layer 60a. Therefore, even if the thickness of the electrolytic plating layer 50b forming the protruding member 50 is small, the embodiment can ensure the height of the metal member. The embodiment can reduce the variation in the height of the protruding member 50. The height of the top of the protruding member 50 does not vary greatly from place to place. The height of the dam 80 does not vary greatly from place to place.

[0023] The embodiment may have a base between the first layer 60a and the seed layer 50a forming the protruding member 50. In this case, the protruding member 50 is formed on the base on the first layer 60a.

[0024] [Modification Example] FIG. 4 is a plan view showing a printed wiring board 102 of a modified example. FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 4. As shown in FIGS. 4 and 5, the printed wiring board 102 of the modified example has a conductor layer 10, the uppermost resin insulating layer 20, the uppermost conductor layer 30, via conductors 42, 44, 46, 48, a solder resist layer 60, and a dam 80. The dam 80 is formed by a groove 70 formed in the solder resist layer 60 and a metal protruding member 50 formed in the groove 70. The protruding member 50 has a top portion 52. The top portion 52 of the protruding member 50 protrudes upward from the upper surface 61 of the solder resist layer 60.

[0025] As shown in FIG. 5, the conductor layer 10 includes pads 12, 14, 16, 18 and connection wirings 13, 17. The conductor layer 10 is mainly formed of copper. The conductor layer 10 is formed of a seed layer 10a and an electrolytic plating layer 10b on the seed layer 10a. The pad 12 is connected to one end of the connection wiring 13. The pad 14 is connected to the other end of the connection wiring 13. The pad 16 is connected to one end of the connection wiring 17. The pad 18 is connected to the other end of the connection wiring 17. The pads 12, 14 are electrically connected via the connection wiring 13. The pads 16, 18 are electrically connected via the connection wiring 17.

[0026] The uppermost resin insulating layer 20 is formed on the conductor layer 10. The uppermost resin insulating layer 20 is formed of the same material as in the embodiment. In the modified example, the uppermost resin insulating layer 20 has openings (openings for via conductors) 22, 24, 26, 28 that expose the conductor layer 10. The openings 22, 24, 26, 28 extend from the upper surface of the uppermost resin insulating layer 20 to the pads 12, 14, 16, 18. The openings 22, 24, 26, 28 expose the pads 12, 14, 16, 18.

[0027] The uppermost conductor layer 30 is formed on the upper surface of the uppermost resin insulating layer 20. The uppermost conductor layer 30 has electrodes 32, 34, 36 and a base 39. The uppermost conductor layer 30 does not have connection wirings. The base 39 does not have an electrical function. The base 39 is not connected to any of a power supply, a ground, and signal wirings. The base 39 functions only as a base for the protruding member 50. The uppermost conductor layer 30 is mainly formed of copper. The uppermost conductor layer 30 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The thickness of the base 39 is substantially equal to the thicknesses of the electrodes 32, 34, 36. The thickness of the base 39 may be larger than the thicknesses of the electrodes 32, 34, 36. The thickness of the base 39 may be smaller than the thicknesses of the electrodes 32, 34, 36.

[0028] Via conductors 42, 44, 46, 48 are formed in openings 22, 24, 26, 28. The via conductors 42, 44, 46, 48 connect the conductor layer 10 and the uppermost conductor layer 30. The via conductor 42 connects the pad 12 and the electrode 32. The via conductor 44 connects the pad 14 and the electrode 34. The via conductor 46 connects the pad 16 and the electrode 34. The via conductor 48 connects the pad 18 and the electrode 36. The electrode (electrode for the second electronic component) 32 and the electrode (first electrode for the first electronic component) 34 are electrically connected via the via conductor 42, the pad 12, the connection wiring 13, the pad 14, and the via conductor 44. The electrode (second electrode for the first electronic component) 34 and the electrode (electrode for the third electronic component) 36 are electrically connected via the via conductor 46, the pad 16, the connection wiring 17, the pad 18, and the via conductor 48. The via conductors 42, 44, 46, 48 are formed of the seed layer 30a and the electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductors 42, 44, 46, 48 and the seed layer 30a forming the uppermost conductor layer 30 are common. The electrolytic plating layer 30b forming the via conductors 42, 44, 46, 48 and the electrolytic plating layer 30b forming the uppermost conductor layer 30 are common.

[0029] Data is sent from one electronic component to another via the connection wirings 13, 17. The connection wiring 13 is a wiring for sending data from the first electronic component to the second electronic component. The connection wiring 17 is a wiring for sending data from the first electronic component to the third electronic component.

[0030] The solder resist layer 60 is formed on the uppermost conductor layer 30 and the uppermost resin insulation layer 20. The solder resist layer 60 has openings 62, 64, 66 that expose the respective electrodes 32, 34, 36. In a modified example, the solder resist layer 60 is formed in a single layer. The groove 70 penetrates the solder resist layer 60. The bottom of the groove 70 exposes the base 39. The upper surface of the base 39 is partially covered by the solder resist layer 60. The central portion of the upper surface of the base 39 is exposed by the solder resist layer 60.

[0031] The protruding member 50 is formed in the groove 70. The protruding member 50 is formed on the base 39 that is exposed from the groove 70. The protruding member 50 is mainly formed of copper. The protruding member 50 is formed of a seed layer 50a on the base 39 and an electrolytic plating layer 50b on the seed layer 50a. The protruding member 50 is joined to the base 39. The width W3 of the base 39 is larger than the width W1 of the groove 70. The width W1 of the groove 70 is larger than the width W2 of the protruding member 50.

[0032] [Manufacturing Method of the Printed Wiring Board 102 of the Modified Example] Figs. 6A to 6D show the manufacturing method of the printed wiring board 102 of the modified example. Figs. 6A to 6D are cross-sectional views. The conductor layer 10 including the pads 12, 14, 16, 18 and the connection wirings 13, 17 is formed by a semi-additive method. The uppermost resin insulation layer 20 is formed on the conductor layer 10. Openings 22, 24, 26, 28 for via conductors that penetrate the uppermost resin insulation layer 20 and reach the pads 12, 14, 16, 18 are formed in the uppermost resin insulation layer 20. The uppermost conductor layer 30 and the via conductors 42, 44, 46, 48 are formed on the upper surface of the uppermost resin insulation layer 20 by a semi-additive method. The uppermost conductor layer 30 includes the base 39 and the electrodes 32, 34, 36. A dry film 60D is laminated on the uppermost resin insulation layer 20 and the uppermost conductor layer 30. The dry film 60D is cured. The intermediate substrate 4 shown in Fig. 6A is obtained. The dry film 60D for forming the solder resist layer 60 may be of a photo-curing type or a heat-curing type. The solder resist layer 60 may be formed by applying a resin.

[0033] As shown in FIG. 6B, a groove 70 is formed. A solder resist layer 60 having the groove 70 is formed. The groove 70 is formed by a laser. Alternatively, the groove 70 is formed by exposure and development.

[0034] A seed layer 50a is formed on the solder resist layer 60. The seed layer 50a is also formed on the base 39 exposed from the groove 70 and on the side walls of the groove 70. As shown in FIG. 6C, a plating resist 90 is formed on the seed layer 50a. The plating resist 90 has an opening 92 for forming the protruding member 50. The opening 92 exposes the seed layer 50a on the base 39.

[0035] An electrolytic plating layer 50b is formed on the seed layer 50a exposed from the plating resist 90 by electrolytic plating. A protruding member 50 is formed on the base 39 exposed from the plating resist 90. The protruding member 50 joins to the upper surface of the base 39. As shown in FIG. 6D, the plating resist 90 is removed. The seed layer 50a exposed from the electrolytic plating layer 50b is removed. A dam 80 is formed.

[0036] Openings 62, 64, 66 that penetrate the solder resist layer 60 and reach the electrodes 32, 34, 36 are formed using a laser. The electrodes 32, 34, 36 are exposed by the openings 62, 64, 66. A printed wiring board 102 is obtained.

[0037] The protruding member 50 of the modified example is joined to the base 39. The adhesion strength between the protruding member 50 and the base 39 is high. The dam 80 is difficult to peel off from the printed wiring board 102. The dam 80 is difficult to deform. The base 39 surrounds an electrode group formed by a plurality of electrodes (electrodes for the first electronic component) 34. The planar shape of the base 39 and the planar shape of the dam 80 are substantially equal. The planar shape of the groove 70, the planar shape of the base 39, and the planar shape of the dam 80 are substantially frame-shaped.

[0038] In the modified example, the base 39 and the protruding member 50 are formed in separate processes. Therefore, the modified example can reduce the variations in the thickness of the base 39 and the height of the protruding member 50. The height of the top 52 of the protruding member 50 does not vary significantly from place to place. The height of the dam 80 does not vary significantly from place to place.

Explanation of Reference Numerals

[0039] 2, 102: Printed Wiring Board 20: Top Resin Insulation Layer 30: Top Conductor Layer 32, 34, 36: Electrodes 39: Base 50: Protruding Member 52: Top 60: Solder Resist Layer 60a: First Layer 60b: Second Layer 61: Top Surface 70: Groove 80: Dam

Claims

1. The uppermost resin insulating layer, The uppermost conductor layer formed on the uppermost resin insulating layer and including an electrode group formed of a plurality of electrodes for mounting electronic components, A solder resist layer formed on the uppermost resin insulating layer and the uppermost conductor layer and having a groove substantially surrounding the electrode group, A printed wiring board having a metal protruding member formed in the groove, The protruding member has a top, and the top protrudes above the upper surface of the solder resist layer.

2. The printed wiring board according to Claim 1, wherein a dam is formed by the groove and the protruding member.

3. The printed wiring board according to Claim 1, wherein the width of the groove is larger than the width of the protruding member.

4. The printed wiring board according to Claim 1, wherein the solder resist layer has a first layer on the uppermost resin insulating layer and the uppermost conductor layer and a second layer on the first layer, the groove penetrates the second layer, the bottom of the groove exposes the first layer, and the protruding member is formed on the first layer exposed from the groove.

5. The printed wiring board according to Claim 1, wherein the uppermost conductor layer has a base, the groove penetrates the solder resist layer, the bottom of the groove exposes the base, and the protruding member is formed on the base exposed from the groove.

6. The printed wiring board according to Claim 5, wherein the width of the base is larger than the width of the groove, and the width of the groove is larger than the width of the protruding member.

7. The printed wiring board according to Claim 5, wherein the thickness of the base is substantially equal to the thickness of the electrode.

8. The printed wiring board according to Claim 5, wherein the thickness of the base is larger than the thickness of the electrode.

9. The printed wiring board according to Claim 5, wherein the thickness of the base is smaller than the thickness of the electrode.

Citation Information

Patent Citations

  • Semiconductor device

    JP2008252026A