Nitride semiconductor device

Abstract

To mitigate local electric field concentration.SOLUTION: A nitride semiconductor device 10 includes a first passivation layer 32 covering an electron supply layer 18, a gate layer 22 and a gate electrode 24, and a first field plate electrode 40 provided on the first passivation layer 32. The first field plate electrode 40 includes a plate main body part 42 and a connection part 44 electrically connecting the plate main body part 42 and a source electrode 52. The plate main body part 42 is provided at least partially in a region between the gate layer 22 and a drain electrode 54 in a planar view and extends in a Y axis direction orthogonal with an X axis direction in the planar view. The connection part 44 is disposed at an upper side of the gate electrode 24 between the plate main body part 42 and the source electrode 52, extends in the X axis direction with the Y axis direction defined as a width direction, and connects the plate main body part 42 and the source electrode 52.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing (see, for example, Patent Document 1). A nitride semiconductor device having such a configuration includes, for example, an electron traveling layer, an electron supply layer formed on the electron traveling layer and having a larger bandgap than the electron traveling layer, a gate layer formed on the electron traveling layer and containing acceptor-type impurities, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode. Further, this nitride semiconductor device includes a field plate electrode integrated with the source electrode and extending from the source electrode across the gate layer and the gate electrode toward the drain electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In a nitride semiconductor device, for example, when a positive voltage is applied to the gate electrode, an electric field may locally concentrate at the end of the gate layer.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transport layer composed of a nitride semiconductor, an electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a larger bandgap than the electron transport layer, a gate layer provided on the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity, a gate electrode provided on the gate layer, a first passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and including a first source opening and a first drain opening that are spaced apart from each other in a first direction and sandwich the gate layer in the first direction, a source electrode in contact with the electron supply layer through the first source opening, a drain electrode in contact with the electron supply layer through the first drain opening, a first field plate electrode provided on the first passivation layer, and a second passivation layer covering the first passivation layer and the first field plate electrode. The first field plate electrode includes a plate main body portion provided spaced apart from the source electrode in the first direction, and a connection portion that electrically connects the plate main body portion and the source electrode. The plate main body portion is at least partially provided in a region between the gate layer and the drain electrode in a plan view, extends in a second direction orthogonal to the first direction in the plan view, the connection portion is disposed above the gate electrode between the plate main body portion and the source electrode, extends in the first direction with the second direction as a width direction to connect the plate main body portion and the source electrode, and the width of the connection portion is shorter than the length of the plate main body portion in the second direction.

Brief Description of the Drawings

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[0007] [Detailed Description] Hereinafter, some embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Further, for ease of understanding, in the cross-sectional views, the hatching lines may be omitted. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure. The terms "first", "second", "third", etc. in the present disclosure are merely used to distinguish objects and do not rank the objects.

[0008] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] (Embodiment) (Schematic Structure of Nitride Semiconductor Device) FIG. 1 is an exemplary schematic plan view of a nitride semiconductor device 10 according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10 cut along the line F2-F2 in FIG. 1. FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 cut along the line F3-F3 in FIG. 1. FIG. 4 is an enlarged schematic plan view showing a part of the nitride semiconductor device 10 in FIG. 1. FIG. 5 is an enlarged schematic cross-sectional view showing a part of the nitride semiconductor device 10 in FIG. 3. In FIGS. 1 to 5, unless otherwise explicitly stated, "plan view" means viewing the object along the Z-axis direction of the nitride semiconductor device 10. FIGS. 2 and 3 show the cross-sectional structure along the XZ plane.

[0010] In one example, the nitride semiconductor device 10 may be a HEMT using GaN. Hereinafter, with reference to FIGS. 2 to 5, the cross-sectional structure of the nitride semiconductor device 10 will be described, and then with reference to FIG. 1, the planar structure of the nitride semiconductor device 10 will be described.

[0011] As shown in FIG. 2, the nitride semiconductor device 10 may include a semiconductor substrate 12 and a buffer layer 14 provided on the semiconductor substrate 12. The nitride semiconductor device 10 further includes an electron traveling layer 16 and an electron supply layer 18 provided on the electron traveling layer 16.

[0012] The semiconductor substrate 12 can be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 may be a Si substrate. The thickness of the semiconductor substrate 12 can be, for example, 100 μm or more and 1500 μm or less.

[0013] The buffer layer 14 may include one or more nitride semiconductor layers. The electron traveling layer 16 is provided on the buffer layer 14. In one example, the buffer layer 14 can be composed of any material that can facilitate the epitaxial growth of the electron traveling layer 16. The buffer layer 14 may include one or more nitride semiconductor layers.

[0014] For example, the buffer layer 14 can include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In order to suppress the leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make the buffer layer 14 semi-insulating. In that case, the impurity is, for example, carbon (C) or iron (Fe), and the concentration of the impurity is, for example, 4×10 16cm -3 It can be set as above.

[0015] The electron transport layer 16 is composed of a nitride semiconductor. The electron transport layer 16 may be, for example, a GaN layer. The thickness of the electron transport layer 16 can be, for example, 0.5 μm or more and 2 μm or less. In addition, in order to suppress the leakage current in the electron transport layer 16, by introducing impurities into a part of the electron transport layer 16, the region other than the surface layer region of the electron transport layer 16 may be made semi-insulating. In this case, the impurity may be, for example, C. The impurity concentration in the electron transport layer 16 is, for example, 1×10 16 cm -3 It can be set as above.

[0016] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the bandgap becomes larger as the Al composition increases, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al X Ga (1-X) N, the Al composition ratio X is 0.1 < X < 0.4, and more preferably, 0.1 < X < 0.3. The electron supply layer 18 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 18 may have a thickness of 8 nm or more.

[0017] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface). Note that by increasing at least one of the Al composition and the thickness of the electron supply layer 18, the sheet carrier density of the 2DEG 20 generated in the electron transport layer 16 can be increased.

[0018] (Gate layer and gate electrode) The nitride semiconductor device 10 further includes a gate layer 22 formed on the electron supply layer 18 and a gate electrode 24 formed on the gate layer 22. The gate layer 22 may be formed on a part of the electron supply layer 18.

[0019] The gate layer 22 has a rectangular shape in a cross section along the XZ plane of FIGS. 2 and 3. The gate layer 22 may have a trapezoidal shape in a cross section along the XZ plane. The thickness T22 of the gate layer 22 may be, for example, 60 nm or more and 200 nm or less.

[0020] The gate layer 22 is composed of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 may have a smaller bandgap than the electron supply layer 18. The gate layer 22 may be composed of any material having a smaller bandgap than the electron supply layer 18, for example, an AlGaN layer. The gate layer 22 may be a gallium nitride layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of acceptor-type impurities in the gate layer 22 is 7×10 18 cm -3 or more and 1×10 20 cm -3 or less. In one example, the gate layer 22 may be GaN containing at least one of Mg and Zn as an impurity.

[0021] As described above, when the gate layer 22 contains acceptor-type impurities, the energy levels of the electron traveling layer 16 and the electron supply layer 18 are raised. Therefore, in the region directly below the gate layer 22, the energy level of the conduction band of the electron traveling layer 16 near the hetero-junction interface between the electron traveling layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 24, a 2DEG 20 is not formed in the electron traveling layer 16 in the region directly below the gate layer 22. On the other hand, a 2DEG 20 is formed in the electron traveling layer 16 in a region other than the region directly below the gate layer 22.

[0022] Thus, due to the presence of the gate layer 22 doped with acceptor-type impurities, the 2DEG 20 disappears in the region directly below the gate layer 22. As a result, the normally-off operation of the transistor is realized. When an appropriate on-voltage is applied to the gate electrode 24, a channel due to the 2DEG 20 is formed in the electron traveling layer 16 in the region directly below the gate electrode 24, so that conduction occurs between the source and the drain.

[0023] The gate electrode 24 may be composed of one or more metal layers. In one example, the gate electrode 24 may be composed of a titanium nitride (TiN) layer. In another example, the gate electrode 24 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 may be formed in a region smaller than the gate layer 22 in plan view. The thickness of the gate electrode 24 may be, for example, 50 nm or more and 200 nm or less.

[0024] The nitride semiconductor device 10 further includes a passivation layer 30 that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 30 may be formed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 30 may be, for example, 80 nm or more and 150 nm or less.

[0025] The passivation layer 30 has a source opening 30A and a drain opening 30B spaced apart in the X-axis direction. In this specification, the X-axis direction is also referred to as the first direction, and the Y-axis direction is also referred to as the second direction. Therefore, the second direction is orthogonal to the first direction in plan view. The gate layer 22 is located between the source opening 30A and the drain opening 30B. More specifically, the gate layer 22 may be between the source opening 30A and the drain opening 30B and closer to the source opening 30A than the drain opening 30B.

[0026] (Source and Drain Electrodes) The nitride semiconductor device 10 includes a source electrode 52 and a drain electrode 54. The source electrode 52 is in contact with the electron supply layer 18 through the source opening 30A. The source opening 30A of the passivation layer 30 exposes a part of the electron supply layer 18. The source electrode 52 is in contact with the electron supply layer 18 exposed by the source opening 30A. The source electrode 52 is in ohmic contact with the 2DEG directly under the electron supply layer 18.

[0027] The drain electrode 54 is in contact with the electron supply layer 18 through the drain opening 30B. The drain opening 30B of the passivation layer 30 exposes a part of the electron supply layer 18. The drain electrode 54 is in contact with the electron supply layer 18 exposed by the drain opening 30B. The drain electrode 54 is in ohmic contact with the 2DEG directly under the electron supply layer 18.

[0028] The source electrode 52 and the drain electrode 54 are arranged on the upper surface of the electron supply layer 18 so as to sandwich the gate layer 22. The source electrode 52 and the drain electrode 54 may be composed of one or more metal layers. For example, the source electrode 52 and the drain electrode 54 can be composed of any combination of two or more layers such as a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

[0029] The source electrode 52 includes a contact portion 52A filled in the source opening 30A and an extension portion 52B formed integrally with the contact portion 52A and located around the source opening 30A in plan view. The extension portion 52B is located on the passivation layer 30.

[0030] The drain electrode 54 includes a contact portion 54A filled in the drain opening 30B and an extension portion 54B formed integrally with the contact portion 54A and located around the drain opening 30B in plan view. The extension portion 54B is located on the passivation layer 30. The thickness T52 of the extension portion 52B of the source electrode 52 may be, for example, 350 nm. The thickness T52 of the extension portion 54B of the drain electrode 54 may be, for example, 350 nm.

[0031] (Passivation layer) The passivation layer 30 includes a first passivation layer 32 and a second passivation layer 34. The first passivation layer 32 is disposed on the electron supply layer 18. The first passivation layer 32 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. In one example, the first passivation layer 32 is in contact with the electron supply layer 18, the gate layer 22, and the gate electrode 24.

[0032] The second passivation layer 34 is disposed on the first passivation layer 32. The second passivation layer 34 covers the first passivation layer 32. The second passivation layer 34 is in contact with the first passivation layer 32.

[0033] The first passivation layer 32 and the second passivation layer 34 may be made of the same material as each other. The first passivation layer 32 and the second passivation layer 34 may be made of different materials from each other.

[0034] The thickness T32 of the first passivation layer 32 may be, for example, 30 nm or more and 60 nm or less. In one example, the thickness T32 of the first passivation layer 32 may be 40 nm. The second passivation layer 34 may be thicker than the first passivation layer 32. The thickness T34 of the second passivation layer 34 may be, for example, 50 nm or more and 100 nm or less. In one example, the thickness T34 of the second passivation layer 34 may be 80 nm.

[0035] The source opening 30A of the passivation layer 30 penetrates through the first passivation layer 32 and the second passivation layer 34. It can be said that the source opening 30A is composed of a first source opening 32A of the first passivation layer 32 and a second source opening 34A of the second passivation layer 34.

[0036] In one example, the source opening 30A may be formed such that the opening width of the source opening 30A increases from the electron supply layer 18 toward the upper surface 30S of the passivation layer 30. The passivation layer 30 includes an inner wall surface 31A that constitutes the source opening 30A. The inner wall surface 31A constitutes the source opening 30A.

[0037] As shown in FIG. 5, the inner wall surface 31A of the source opening 30A includes an inclined surface that is inclined with respect to the XY plane along the Z-axis direction, which is the thickness direction of the first passivation layer 32 and the second passivation layer 34. It can be said that the inner wall surface 31A of the source opening 30A is inclined with respect to the Z-axis direction. The inclination angle θ1 of the inner wall surface 31A of the source opening 30A with respect to the Z-axis direction may be 20 degrees or more and 60 degrees or less. In one example, the inclination angle θ1 may be 30 degrees or more.

[0038] As shown in FIGS. 2 and 3, the drain opening 30B of the passivation layer 30 penetrates through the first passivation layer 32 and the second passivation layer 34. It can be said that the drain opening 30B is constituted by the first drain opening 32B of the first passivation layer 32 and the second drain opening 34B of the second passivation layer 34. In one example, the drain opening 30B may be formed such that the opening width of the drain opening 30B is equal from the electron supply layer 18 toward the upper surface 30S of the passivation layer 30.

[0039] (Field plate electrode) As shown in FIGS. 1 to 5, the nitride semiconductor device 10 includes a first field plate electrode 40.

[0040] As shown in FIGS. 2, 3, and 5, the first field plate electrode 40 is embedded in the passivation layer 30. The passivation layer 30 includes a first passivation layer 32 and a second passivation layer 34 on the first passivation layer 32. The first field plate electrode 40 is disposed between the first passivation layer 32 and the second passivation layer 34. It can be said that the first field plate electrode 40 is provided on the first passivation layer 32 and covered by the second passivation layer 34.

[0041] As shown in FIGS. 1 to 5, the first field plate electrode 40 includes a plate main body portion 42 and a connection portion 44. In FIG. 3, the connection portion 44 is shown by a broken line. The plate main body portion 42 is provided at a distance from the source electrode 52 in the X-axis direction. The plate main body portion 42 is at least partially provided in a region between the gate layer 22 and the drain electrode 54 in a plan view. Further, the plate main body portion 42 extends in the Y-axis direction orthogonal to the X-axis direction in a plan view. In one example, the plate main body portion 42 has a rectangular shape that is long in the Y-axis direction with respect to the X-axis direction in a plan view. In one example, in the Y-axis direction, the plate main body portion 42 may be longer than the length of the source opening 30A. Also, in one example, in the Y-axis direction, the length of the plate main body portion 42 may be longer than the length of the drain opening 30B. As shown in FIG. 4, the length L1 of the plate main body portion 42 in the Y-axis direction may be 400 μm or more and 1000 μm or less.

[0042] As shown in FIGS. 2, 3, and 5, it can be said that the plate main body portion 42 is at least partially provided in a region between the gate layer 22 and the drain electrode 54 in a plan view and extends in the Y-axis direction orthogonal to the X-axis direction in a plan view. As shown in FIG. 2, the distance D1 between the source opening 30A in which the source electrode 52 is formed and the plate main body portion 42 is about 1 μm in one example.

[0043] The connection part 44 is provided between the plate main body part 42 and the source electrode 52. The connection part 44 electrically connects the plate main body part 42 and the source electrode 52. The connection part 44 extends from the plate main body part 42 to the source electrode 52 through above the gate electrode 24. It can be said that the plate main body part 42 is disposed above the gate electrode 24 and extends in the X-axis direction. In plan view, the area of the connection part 44 is smaller than the area of the plate main body part 42. The area of the connection part 44 may be 1 / 10 or less of the area of the plate main body part 42. The width W2 of the connection part 44 is the length of the connection part 44 in the Y-axis direction. The width W2 of the connection part 44 is shorter than the length L1 of the plate main body part 42. The width W2 of the connection part 44 may be 1 / 50 or less with respect to the length L1 of the plate main body part 42. The width W2 of the connection part 44 may be 5 μm or more and 10 μm or less.

[0044] As shown in FIG. 5, the connection part 44 is exposed at the source opening 30A of the passivation layer 30. The passivation layer 30 includes the inner wall surface 31A that constitutes the source opening 30A. The connection part 44 is exposed from the inner wall surface 31A. It can be said that the passivation layer 30 includes the inner wall surface 31A where the connection part 44 is exposed. The inner wall surface 31A constitutes the source opening 30A. It can be said that the source opening 30A includes the inner wall surface 31A where the connection part 44 is exposed. The inner wall surface 31A of the source opening 30A includes an inclined surface inclined with respect to the XY plane along the Z-axis direction which is the thickness direction of the first passivation layer 32 and the second passivation layer 34. The connection part 44 includes a connection end surface 44A connected to the source electrode 52. The connection end surface 44A is inclined corresponding to the inner wall surface 31A of the source opening 30A of the passivation layer 30.

[0045] As shown in FIGS. 4 and 5, the plate main body part 42 includes a first end part 42A which is an end part in the X-axis direction, and a second end part 42B on the opposite side of the first end part 42A. The first end part 42A is the end part on the side of the plate main body part 42 closer to the source electrode 52. The second end part 42B is the end part on the side of the plate main body part 42 closer to the drain electrode 54.

[0046] The first end portion 42A of the plate main body 42 may be located above the gate layer 22. The second end portion 42B of the plate main body 42 may be located between the gate layer 22 and the drain electrode 54 in a plan view. It can be said that the plate main body 42 overlaps a part of the gate layer 22. In a plan view, it can be said that the plate main body 42 covers the second end portion 22B of the gate layer 22. In a plan view, it can be said that the first end portion 22A of the gate layer 22 is not covered by the plate main body 42.

[0047] The first end portion 42A of the plate main body 42 may be located above the gate electrode 24. It can be said that the plate main body 42 overlaps a part of the gate layer 22. It can be said that the plate main body 42 overlaps a part of the gate electrode 24. In a plan view, the area of the region where the plate main body 42 and the gate electrode 24 overlap may be smaller than the area of the region where the plate main body 42 and the gate electrode 24 do not overlap.

[0048] As shown in FIG. 4, the nitride semiconductor device 10 may include a plurality of connection portions 44 with respect to one plate main body 42. That is, a plurality of connection portions 44 may be connected to one plate main body 42. The connection portion 44 is connected to the first end portion 42A of the plate main body 42. It can be said that one plate main body 42 is electrically connected to the source electrode 52 by a plurality of connection portions 44. In one example, one plate main body 42 is electrically connected to the source electrode 52 by two connection portions 44. By the two connection portions 44, the plate main body 42 has the same potential as the source electrode 52.

[0049] As shown in FIG. 5, the plate main body 42 includes a third end portion 42C in the Y-axis direction and a fourth end portion 42D on the side opposite to the third end portion 42C. The plate main body 42 also includes a first connection portion 42AA and a second connection portion 42AB to which two connection portions 44 are connected. In one example, the two connection portions 44 are connected to the plate main body 42 such that the length L11 between the third end portion 42C and the first connection portion 42AA, the length L12 between the first connection portion 42AA and the second connection portion 42AB, and the length L13 between the second connection portion 42AB and the fourth end portion 42D are equal.

[0050] As shown in FIG. 5, the gate layer 22 includes a first end portion 22A which is an end portion in the X-axis direction and a second end portion 22B on the side opposite to the first end portion 22A. The first end portion 22A is the end portion on the source electrode 52 side in the gate layer 22. The second end portion 22B is the end portion on the drain electrode 54 side in the gate layer 22. The distance D2 between the first end portion 22A of the gate layer 22 and the source opening 30A in the X-axis direction may be 0.3 μm or more and 0.6 μm or less. As shown in FIG. 2, the minimum width W3 of the source opening 30A in the X-axis direction may be 1 μm or less.

[0051] (Planar layout of nitride semiconductor device) Next, with reference to FIG. 1, an example of the planar layout of the nitride semiconductor device 10 will be described. In FIG. 1, the gate electrode 24 and the first field plate electrode 40 are drawn with solid lines, and the source electrode 52 and the drain electrode 54 are drawn with dashed lines. For the passivation layer 30, the source opening 30A and the drain opening 30B are drawn with solid lines, and the other portions are shown transparently.

[0052] As shown in FIG. 1, the nitride semiconductor device 10 includes a plurality of transistor elements each having the HEMT structure of the nitride semiconductor device 10 in the element region. Note that FIG. 1 shows only a plurality of transistor elements arranged in the X-axis direction. The transistor elements may be arranged side by side in both the X-axis direction and the Y-axis direction.

[0053] The drain electrode 54 is provided for each transistor element. The drain electrode 54 extends in the Y-axis direction in a plan view. The source electrode 52 is provided, for example, so as to surround each drain electrode 54 in a plan view. In the example shown in FIG. 1, the source electrode 52 is continuously formed in the X-axis direction across a plurality of transistor elements adjacent in the X-axis direction, but it may be separated into a plurality of portions in the X-axis direction.

[0054] The gate layer 22 and the gate electrode 24 are provided for each transistor element. Each gate layer 22 and each gate electrode 24 are formed in an annular shape so as to surround one of the drain electrodes 54 in a plan view.

[0055] The first field plate electrode 40 is provided for each transistor element. The first field plate electrode 40 includes a plate main body portion 42 provided at a distance from the source electrode 52 in the X-axis direction, and a connection portion 44 that electrically connects the plate main body portion 42 and the source electrode 52. The plate main body portion 42 is at least partially provided in a region between the gate layer 22 and the drain electrode 54 in a plan view and extends in the Y-axis direction. The plate main body portion 42 may be formed in an annular shape so as to surround the drain electrode 54.

[0056] The nitride semiconductor device 10 may include a gate wiring 72, a source wiring 74, and a drain wiring 76. In FIG. 1, the gate wiring 72, the source wiring 74, and the drain wiring 76 are drawn with a dashed line. The gate wiring 72, the source wiring 74, and the drain wiring 76 are located above the source electrode 52 and the drain electrode 54 in the Z-axis direction. The gate wiring 72, the source wiring 74, and the drain wiring 76 extend in the X-axis direction. The gate wiring 72, the source wiring 74, and the drain wiring 76 are arranged at intervals from each other in the Y-axis direction.

[0057] The gate wiring 72 may be arranged at a position different from the drain electrode 54, the source opening 30A, and the drain opening 30B in the Y-axis direction. The gate wiring 72 may be electrically connected to the gate electrode 24 by the via wiring 73. The source wiring 74 and the drain wiring 76 may be arranged at positions overlapping with the drain electrode 54, the source opening 30A, and the drain opening 30B in a plan view in the Y-axis direction. The source wiring 74 may be electrically connected to the source electrode 52 by the via wiring 75. The drain wiring 76 may be electrically connected to the drain electrode 54 by the via wiring 77. In FIG. 1, the via wirings 73, 75, and 77 are drawn with broken lines. The planar layout of the nitride semiconductor device 10 is not limited to the example shown in FIG. 1. Any other planar layout can be applied to the nitride semiconductor device 10.

[0058] (Operation of the Embodiment) (Comparative Example) FIG. 6 is a schematic cross-sectional view showing a nitride semiconductor device 10X of a comparative example with respect to the nitride semiconductor device 10 of the above embodiment. The structure of FIG. 6 is shown as a comparative example with the structures of FIGS. 2 and 3. For the nitride semiconductor device 10X of the comparative example, the same reference numerals are given to the components similar to those of the nitride semiconductor device 10 of the embodiment.

[0059] The nitride semiconductor device 10X of the comparative example includes an electron supply layer 18, a gate layer 22, and a passivation layer 30X that covers the gate electrode 24. The nitride semiconductor device 10X of the comparative example includes a source field plate electrode 52X formed integrally with the source electrode 52. The source field plate electrode 52X is provided on the passivation layer 30X so as to cover the entire gate electrode 24 and the gate layer 22. The source field plate electrode 52X includes an end portion 52XB on the drain electrode 54 side. This end portion 52XB is located between the drain electrode 54 and the gate layer 22 in a plan view. When a high voltage is applied between the source and drain while the gate-source voltage is 0V, the source field plate electrode 52X extends the depletion layer toward the 2DEG20 directly below the source field plate electrode 52X, thereby playing a role of alleviating the electric field concentration in the vicinity of the second end portion 22B of the gate layer 22.

[0060] In the nitride semiconductor device 10X of the comparative example, in order to reduce the on-resistance, for example, it is conceivable that a design is made to shorten the distance between the source electrode 52 and the drain electrode 54. In this case, in order to alleviate the electric field concentration accompanying the shortening of the distance between the source electrode 52 and the drain electrode 54, it is necessary to thin the passivation layer 30X between the source field plate electrode 52X and the gate layer 22 and the gate electrode 24. The source field plate electrode 52X and the gate electrode 24 face each other with the passivation layer 30X interposed therebetween, constituting a parasitic capacitance C1X. When the passivation layer 30X is thinned, the capacitance value of the parasitic capacitance C1X increases. This increase in the parasitic capacitance C1X lengthens the charging and discharging time with respect to the parasitic capacitance C1X, that is, the time (transition period) required for the rise and fall of the gate voltage at the gate electrode 24, and consequently leads to an increase in energy loss.

[0061] The source electrode 52 and the drain electrode 54 are formed by selectively etching a metal layer formed on the passivation layer 30X. The film thickness of the metal layer forming the source electrode 52 and the drain electrode 54 is, for example, 350 nm. Also, in the manufacturing process, over-etching for etching the passivation layer 30X is performed to electrically isolate the source electrode 52 and the drain electrode 54. Therefore, due to variations in the manufacturing process, there is a risk that the passivation layer 30X may become too thin by etching the thick metal layer. In this case, when the passivation layer 30X becomes thinner than the desired thickness, the insulation property of the passivation layer 30X cannot be ensured.

[0062] (Nitride semiconductor device of this embodiment) The nitride semiconductor device 10 of this embodiment includes an electron transport layer 16 composed of a nitride semiconductor, an electron supply layer 18 provided on the electron transport layer 16 and composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16, a gate layer 22 provided on the electron supply layer 18 and composed of a nitride semiconductor containing an acceptor-type impurity, a gate electrode 24 provided on the gate layer 22, a first passivation layer 32 that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24 and includes a first source opening 32A and a first drain opening 32B that are spaced apart from each other in the X-axis direction and sandwich the gate layer 22 in the X-axis direction, a source electrode 52 in contact with the electron supply layer 18 through the first source opening 32A, a drain electrode 54 in contact with the electron supply layer 18 through the first drain opening 32B, a first field plate electrode 40 provided on the first passivation layer 32, and a second passivation layer 34 that covers the first passivation layer 32 and the first field plate electrode 40.

[0063] The first field plate electrode 40 includes a plate main body portion 42 provided at a distance from the source electrode 52 in the X-axis direction, and a connection portion 44 that electrically connects the plate main body portion 42 and the source electrode 52. The plate main body portion 42 is at least partially provided in a region between the gate layer 22 and the drain electrode 54 in a plan view, and extends in the Y-axis direction orthogonal to the X-axis direction in the plan view. The plate main body portion 42 of the first field plate electrode 40 provided on the first passivation layer 32 covers the second end portion 22B of the gate layer 22 closer to the drain electrode 54. Therefore, the plate main body portion 42 can relieve the electric field concentration near the end portion of the gate layer 22.

[0064] In the nitride semiconductor device 10 of the embodiment, the on-resistance can be reduced by shortening the distance between the source electrode 52 and the drain electrode 54. The plate main body portion 42 of the first field plate electrode 40 is provided on the first passivation layer 32 that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. This first passivation layer 32 is thinner than the second passivation layer 34 that constitutes the passivation layer 30 together with the first passivation layer 32. Therefore, the electric field concentration associated with the shortening of the distance between the source electrode 52 and the drain electrode 54 can be relieved.

[0065] As shown in FIG. 5, the thickness T40 of the first field plate electrode 40 is smaller than the thickness T32 of the first passivation layer 32. Also, the thickness T40 of the first field plate electrode 40 is thinner than the thickness T52 of the source electrode 52. Therefore, the decrease in the film thickness of the first passivation layer 32 due to overetching when forming the first field plate electrode 40 is extremely smaller than the decrease in the film thickness of the passivation layer 30X when forming the source electrode 52 in the nitride semiconductor device 10X of the comparative example. Therefore, the insulating property of the first passivation layer 32, that is, the passivation layer 30 can be ensured.

[0066] The first field plate electrode 40 includes a connection portion 44. The connection portion 44 is disposed between the plate main body portion 42 and the source electrode 52 and above the gate electrode 24, extends in the X-axis direction with the Y-axis direction as the width direction, and connects the plate main body portion 42 and the source electrode 52. The width of the connection portion 44 is shorter than the length of the plate main body portion 42 in the Y-axis direction. Therefore, compared with the case of connecting the plate main body portion 42 to the source electrode 52 in the same manner as the nitride semiconductor device 10X of the comparative example, the area of the first field plate electrode 40 facing the gate electrode 24 is small. The capacitance value of the parasitic capacitance C2 is the area of the connection portion 44 facing the gate electrode 24. Also, the capacitance value of the parasitic capacitance C1 formed between the gate electrode 24 and the source electrode 52 is smaller than the capacitance value of the parasitic capacitance C1X in the nitride semiconductor device 10X of the comparative example by increasing the thickness of the passivation layer 30. And the combined capacitance value of the parasitic capacitances C1 and C2 can be made smaller than the capacitance value of the parasitic capacitance C1X of the nitride semiconductor device 10X of the comparative example. For this reason, the capacitance values of the parasitic capacitances C1 and C2 can be reduced. Therefore, when switching the nitride semiconductor device 10 of the embodiment, high-speed charging and discharging of the parasitic capacitances C1 and C2 are possible by the gate voltage applied to the gate electrode 24, and the nitride semiconductor device 10 can be switched at high speed.

[0067] (Method of manufacturing a nitride semiconductor device) With reference to FIGS. 7 to 18, an exemplary manufacturing method of the nitride semiconductor device 10 will be described. In FIGS. 7 to 18, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals.

[0068] As shown in FIG. 7, a method for manufacturing a nitride semiconductor device 10 includes sequentially forming a buffer layer 14, an electron transport layer 16, an electron supply layer 18, and a nitride semiconductor layer 82 on a semiconductor substrate 12. The semiconductor substrate 12 is, for example, a Si substrate. The nitride semiconductor layer 82 is, for example, a gallium nitride (GaN) layer. The buffer layer 14, the electron transport layer 16, the electron supply layer 18, and the nitride semiconductor layer 82 can be epitaxially grown, for example, by using a metal organic chemical vapor deposition (MOCVD) method.

[0069] The buffer layer 14 may be a multilayer buffer layer. In the multilayer buffer layer, an AlN layer (first buffer layer) is formed on the semiconductor substrate 12, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by laminating three AlGaN layers having Al compositions of 75%, 50%, and 25% in order from the side closer to the AlN layer.

[0070] The electron transport layer 16 formed on the buffer layer 14 may be a GaN layer. The electron supply layer 18 formed on the electron transport layer 16 may be an AlGaN layer. Therefore, the electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16.

[0071] The nitride semiconductor layer 82 formed on the electron supply layer 18 may contain magnesium as an acceptor-type impurity. By doping magnesium during the growth of the nitride semiconductor layer 82 on the electron supply layer 18, a nitride semiconductor layer 82 containing acceptor-type impurities can be formed. In one example, the nitride semiconductor layer 82 may contain Mg (magnesium) as an impurity at a concentration of 1×10 18 cm -3 or more and less than 1×10 20 cm -3

[0072] ​As shown in FIG. 8, the method for manufacturing the nitride semiconductor device 10 includes forming a first metal layer 84. In one example, the first metal layer 84 can be formed on the nitride semiconductor layer 82 by sputtering. The first metal layer 84 may be, for example, a TiN layer.

[0073] As shown in FIG. 9, the method for manufacturing the nitride semiconductor device 10 includes forming a gate electrode 24. In one example, the gate electrode 24 is formed by selectively removing the first metal layer 84 shown in FIG. 8 by lithography and etching.

[0074] As shown in FIG. 10, the method for manufacturing the nitride semiconductor device 10 includes forming a gate layer 22. In one example, the gate layer 22 is formed by selectively removing the nitride semiconductor layer 82 shown in FIG. 9 by lithography and etching.

[0075] As shown in FIG. 11, the method for manufacturing the nitride semiconductor device 10 includes forming a first passivation layer 32. In one example, the first passivation layer 32 may be a SiN layer formed by a low-pressure chemical vapor deposition (LPCVD) method. The first passivation layer 32 is formed so as to cover the electron supply layer 18, the gate layer 22, and the gate electrode 24.

[0076] As shown in FIG. 12, the method for manufacturing the nitride semiconductor device 10 includes forming a second metal layer 86. In one example, the second metal layer 86 can be formed on the first passivation layer 32 by sputtering. The second metal layer 86 may be, for example, a TiN layer.

[0077] As shown in FIGS. 13 and 14, the method for manufacturing the nitride semiconductor device 10 includes forming a first field plate electrode 40. In one example, the first field plate electrode 40 is formed by selectively removing the second metal layer 86 shown in FIG. 12 by lithography and etching. As shown in FIG. 14, the first field plate electrode 40 includes a plurality of plate main body portions 42 extending in the Y-axis direction and a connection portion 44 connecting the plate main body portions 42 adjacent to each other in the X-axis direction.

[0078] As shown in FIG. 15, the method for manufacturing the nitride semiconductor device 10 includes forming a second passivation layer 34. In one example, the second passivation layer 34 may be a SiN layer formed by a low-pressure CVD (LPCVD) method. The second passivation layer 34 is formed so as to cover the first passivation layer 32 and the first field plate electrode 40.

[0079] As shown in FIG. 16, the method for manufacturing the nitride semiconductor device 10 includes forming a source opening 30A and a drain opening 30B in the passivation layer 30. In one example, the source opening 30A and the drain opening 30B are formed by selectively removing the passivation layer 30 by lithography and etching. The source opening 30A is formed such that the inner wall surface 31A is an inclined surface inclined with respect to the Z-axis direction which is the lamination direction of the first passivation layer 32 and the second passivation layer 34. By forming the source opening 30A, a connection end surface 44A of the connection portion 44 exposed on the inner wall surface 31A of the source opening 30A is formed.

[0080] As shown in FIG. 17, the method for manufacturing the nitride semiconductor device 10 includes forming a third metal layer 88. In one example, the third metal layer 88 can be formed on the passivation layer 30 by a sputtering method. The third metal layer 88 is formed so as to fill the source opening 30A and the drain opening 30B of the passivation layer 30. The third metal layer 88 may be, for example, a TiN layer. The third metal layer 88 is electrically connected to the connection end face 44A of the connection portion 44 exposed on the inner wall surface 31A of the source opening 30A.

[0081] As shown in FIG. 18, the method for manufacturing the nitride semiconductor device 10 includes forming a source electrode 52 and a drain electrode 54. In one example, it is formed by selectively removing the third metal layer 88 shown in FIG. 14 by lithography and etching. Through the above steps, the nitride semiconductor device 10 shown in FIG. 2 is obtained.

[0082] (Effects of the Embodiment) As described above, the nitride semiconductor device 10 of the embodiment has the following effects.

[0083] (1) The nitride semiconductor device 10 includes a first passivation layer 32 covering the electron supply layer 18, the gate layer 22, and the gate electrode 24, and a first field plate electrode 40 provided on the first passivation layer 32. The first field plate electrode 40 includes a plate main body portion 42 and a connection portion 44 that electrically connects the plate main body portion 42 and the source electrode 52. The plate main body portion 42 is at least partially provided in a region between the gate electrode 24 and the drain electrode 54 in a plan view and extends in a Y-axis direction orthogonal to the X-axis direction in the plan view. The connection portion 44 is disposed between the plate main body portion 42 and the source electrode 52 and above the gate electrode 24, and extends in the X-axis direction with the Y-axis direction as the width direction to connect the plate main body portion 42 and the source electrode 52.

[0084] The plate main body portion 42 of the first field plate electrode 40 provided on the first passivation layer 32 covers the second end portion 22B of the gate layer 22 near the drain electrode 54. Therefore, the plate main body portion 42 can relieve the electric field concentration near the end portion of the gate layer 22.

[0085] (2) In the nitride semiconductor device 10 of the embodiment, in order to reduce the on-resistance, for example, the distance between the source electrode 52 and the drain electrode 54 is shortened. The plate main body portion 42 of the first field plate electrode 40 is provided on the first passivation layer 32 that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. This first passivation layer 32 is thinner than the second passivation layer 34 that constitutes the passivation layer 30 together with the first passivation layer 32. Therefore, the electric field concentration associated with the shortening of the distance between the source electrode 52 and the drain electrode 54 can be relieved.

[0086] (3) The thickness T40 of the first field plate electrode 40 is smaller than the thickness T32 of the first passivation layer 32. Also, the thickness T40 of the first field plate electrode 40 is thinner than the thickness T52 of the source electrode 52. Therefore, the decrease in the film thickness of the first passivation layer 32 due to overetching when forming the first field plate electrode 40 is extremely smaller than the decrease in the film thickness of the passivation layer 30X when forming the source electrode 52 in the nitride semiconductor device 10X of the comparative example. Therefore, the insulating property of the first passivation layer 32, that is, the passivation layer 30 can be ensured.

[0087] (4) The first field plate electrode 40 includes a connection portion 44. The connection portion 44 is located between the plate main body portion 42 and the source electrode 52 and above the gate electrode 24. With the Y-axis direction as the width direction, it extends in the X-axis direction to connect the plate main body portion 42 and the source electrode 52. The width of the connection portion 44 is shorter than the length of the plate main body portion 42 in the Y-axis direction. Therefore, compared with the case of connecting the plate main body portion 42 to the source electrode 52 in the same manner as the nitride semiconductor device 10X of the comparative example, the area of the first field plate electrode 40 facing the gate electrode 24 is small. The capacitance value of the parasitic capacitance C2 is the area of the connection portion 44 facing the gate electrode 24. Also, the capacitance value of the parasitic capacitance C1 formed between the gate electrode 24 and the source electrode 52 is smaller than the capacitance value of the parasitic capacitance C1X in the nitride semiconductor device 10X of the comparative example by thickening the passivation layer 30. And the combined capacitance value of the parasitic capacitances C1 and C2 can be made smaller than the capacitance value of the parasitic capacitance C1X of the nitride semiconductor device 10X of the comparative example. For this reason, the capacitance values of the parasitic capacitances C1 and C2 can be reduced. Therefore, when switching the nitride semiconductor device 10 of the embodiment, high-speed charging and discharging of the parasitic capacitances C1 and C2 can be achieved by the gate voltage applied to the gate electrode 24, and the nitride semiconductor device 10 can be switched at high speed.

[0088] (Modification example) The above embodiment can be modified as follows, for example. The above embodiment and each of the following modification examples can be combined with each other as long as no technical contradiction occurs. In the following modification examples, for the parts common to the above embodiment, the same reference numerals as those in the above embodiment are given and the description thereof is omitted.

[0089] · The configuration of the nitride semiconductor device 10 may be appropriately changed. As shown in FIG. 19, the nitride semiconductor device 110 of the modified example may include a source electrode 152. The source electrode 152 includes a field plate portion 52C. The field plate portion 52C extends toward the drain electrode 54. Specifically, the source electrode 152 includes a contact portion 52A embedded in the source opening 30A and an extension portion 52B located around the source opening 30A. The field plate portion 52C extends from the extension portion 52B toward the drain electrode 54.

[0090] The field plate portion 52C covers the gate layer 22 and the gate electrode 24 in plan view. An end portion 52D of the field plate portion 52C closer to the drain electrode 54 is located closer to the drain electrode 54 than a second end portion 42B of a plate main body portion 42 which is an end portion of the first field plate electrode 40 closer to the drain electrode 54.

[0091] In the nitride semiconductor device 110 of the modified example, the first field plate electrode 40 can relieve the electric field concentration in the vicinity of the ends of the gate electrode 24 and the gate layer 22. Then, the nitride semiconductor device 110 can further relieve the electric field concentration in the vicinity of the ends of the gate electrode 24 and the gate layer 22 by the field plate portion 52C. Therefore, the breakdown voltage of the nitride semiconductor device 110 of the modified example can be improved. The nitride semiconductor device 110 of the modified example can reduce the on-resistance by shortening the distance between the source electrode 152 and the drain electrode 54. The field plate portion 52C extends from the extension portion 52B of the source electrode 152 toward the drain electrode 54. Therefore, the capacitance value of the parasitic capacitance with the gate electrode 24 does not increase. Accordingly, the nitride semiconductor device 110 can perform high-speed switching.

[0092] In the nitride semiconductor device 110 of the modification example, the passivation layer 30 covering the gate layer 22 and the gate electrode 24 does not have to be thinned. Specifically, the second passivation layer 34 covering the first passivation layer 32 can be formed thick. Therefore, even if the second passivation layer 34 is over-etched when forming the field plate portion 52C of the source electrode 152, the insulation of the passivation layer 30 can be ensured. For this reason, a decrease in breakdown voltage can be suppressed.

[0093] As shown in FIG. 20, the nitride semiconductor device 210 of the modification example may further include a third passivation layer 62 covering the source electrode 52 and a second field plate electrode 64 provided on the third passivation layer 62. The third passivation layer 62 covers the source electrode 52, the drain electrode 54, and the second passivation layer 34 of the passivation layer 30. The second field plate electrode 64 extends from directly above the source electrode 52 toward the drain electrode 54.

[0094] The second field plate electrode 64 is electrically connected to the source electrode 52. Specifically, the second field plate electrode 64 is electrically connected to a via wiring 75 connected to the source electrode 52. In one example, the via wiring 75 penetrates the second field plate electrode 64 and is connected to the source electrode 52. The second field plate electrode 64 is at least partially provided in a region between the gate layer 22 and the drain electrode 54 in a plan view. The end portion 64c of the second field plate electrode 64 closer to the drain electrode 54 is located closer to the drain electrode 54 than the second end portion 42B of the plate main body portion 42, which is the end portion of the first field plate electrode 40 closer to the drain electrode 54. The thickness of the second field plate electrode 64 is thinner than the thickness of the source electrode 52. In one example, the thickness of the second field plate electrode 64 is equal to the thickness of the first field plate electrode 40. The thickness of the second field plate electrode 64 may be thicker than the thickness of the first field plate electrode 40 or may be thinner than the thickness of the first field plate electrode 40.

[0095] In the nitride semiconductor device 210 of this modification example, the first field plate electrode 40 and the second field plate electrode 64 can further mitigate the electric field concentration near the ends of the gate electrode 24 and the gate layer 22. Therefore, the breakdown voltage of the nitride semiconductor device 210 of the modification example can be improved. The nitride semiconductor device 210 of the modification example can reduce the on-resistance by shortening the distance between the source electrode 52 and the drain electrode 54. Since the second field plate electrode 64 is disposed on the third passivation layer 62 that covers the source electrode 52, the capacitance value of the parasitic capacitance between the second field plate electrode 64 and the gate electrode 24 does not increase. Therefore, the nitride semiconductor device 210 can perform high-speed switching.

[0096] As shown in FIGS. 21 and 22, the nitride semiconductor device 310 of the modification example includes a gate layer 322. The gate layer 322 may include a ridge portion 331, a first extending portion 341 and a second extending portion 351 that extend in opposite directions from both ends of the ridge portion 331. These ridge portion 331, first extending portion 341, and second extending portion 351 constitute a step structure of the gate layer 322.

[0097] The ridge portion 331 corresponds to a relatively thick portion of the gate layer 322. The gate electrode 24 is in contact with the entire upper surface 332 of the ridge portion 331. The ridge portion 331 may have a rectangular shape or a trapezoidal shape in a cross section along the XZ plane of FIG. 21. The thickness of the ridge portion 331 may be, for example, 100 nm or more and 200 nm or less. The thickness of the ridge portion 331 refers to the distance from the upper surface 332 of the ridge portion 331 to the lower surface (the lower surface of the gate layer 322 in contact with the electron supply layer 18). The thickness of the ridge portion 331 (gate layer 322) may be determined in consideration of various parameters such as gate breakdown voltage.

[0098] The first extending portion 341 extends from the source-side side surface 333 of the ridge portion 331 toward the source opening 30A of the passivation layer 30. The second extending portion 351 extends from the drain-side side surface 334 of the ridge portion 331 toward the drain opening 30B of the passivation layer 30. In the examples of FIGS. 21 and 22, the second extending portion 351 extends longer from the ridge portion 331 than the first extending portion 341. However, the first extending portion 341 and the second extending portion 351 may have the same length. The first extending portion 341 may have a thickness of, for example, 10 nm or more and 30 nm or less. The first extending portion 341 may have a width of, for example, 0.2 μm or more and 0.3 μm or less in the direction from the ridge portion 331 toward the source opening 30A. The second extending portion 351 may have a thickness of, for example, 10 nm or more and 30 nm or less. The second extending portion 351 may have a width of, for example, 0.2 μm or more and 0.6 μm or less in the direction from the ridge portion 331 toward the drain opening 30B. The thickness of the first extending portion 341 and the thickness of the second extending portion 351 are equal to each other. Here, if the difference between the thickness of the first extending portion 341 and the thickness of the second extending portion 351 is, for example, within 10% of the thickness of the first extending portion 341, it can be said that the thickness of the first extending portion 341 and the thickness of the second extending portion 351 are equal to each other.

[0099] The plate main body portion 42 of the first field plate electrode 40 covers the end portion 352 near the drain electrode 54 of the second extending portion 351 that extends toward the drain electrode 54. The first end portion 42A of the plate main body portion 42 may overlap the second extending portion 351 in plan view. The second end portion 42B of the plate main body portion 42 may be located between the end portion 352 of the second extending portion 351 and the drain electrode 54 in plan view.

[0100] In the nitride semiconductor device 310 of this modified example, the first extending portion 341 and the second extending portion 351 can reduce the hole density accumulated at the interface between the gate layer 322 and the electron supply layer 18. Therefore, the band bending of the electron supply layer 18 caused by hole accumulation can be suppressed, and an increase in the gate leakage current can be suppressed. The plate main body portion 42 of the first field plate electrode 40 covers the end portion 352 near the drain electrode 54 of the second extending portion 351. Therefore, the electric field concentration near the end portion 352 of the gate layer 322 can be suppressed.

[0101] As in the nitride semiconductor device 410 of the modified example shown in FIG. 23, the source electrode 52 may be formed so as not to overlap the gate layer 22 and the gate electrode 24 in a plan view. The contact between the source electrode 52 and the drain electrode 54 and the electron supply layer 18 is not limited to the above embodiment. For example, the electron supply layer 18 may include a source opening and a drain opening. The contact portion 52A of the source electrode 52 is disposed at the source opening 30A of the passivation layer 30 and the source opening of the electron supply layer 18. Therefore, it can be said that the source electrode 52 is in contact with the electron supply layer 18. The contact portion 54A of the drain electrode 54 is disposed at the drain opening 30B of the passivation layer 30 and the drain opening of the electron supply layer 18. Therefore, it can be said that the drain electrode 54 is in contact with the electron supply layer 18. The source opening and the drain opening of the electron supply layer 18 may be formed so as to be interposed between the source electrode 52 and the drain electrode 54 and the electron traveling layer 16.

[0102] As used in this disclosure, the term "on" includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Therefore, the expression "the first layer is formed on the second layer" may mean that in some embodiments, the first layer can be directly disposed on the second layer in contact with the second layer, while in other embodiments, the first layer can be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which other layers are formed between the first layer and the second layer.

[0103] The Z-axis direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to exactly coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 2) are not limited to the "upper" and "lower" in the Z-axis direction described in this specification being the "upper" and "lower" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0104] (Supplementary Note) The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than limiting, the components described in the supplementary note are assigned the reference signs of the corresponding components in the embodiments. The reference signs are shown as examples for assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference signs.

[0105] (Supplementary Note 1) An electron traveling layer (16) composed of a nitride semiconductor, An electron supply layer (18) provided on the electron traveling layer (16) and composed of a nitride semiconductor having a larger bandgap than the electron traveling layer (16), A gate layer (22, 322) provided on the electron supply layer (18) and composed of a nitride semiconductor containing acceptor-type impurities, A gate electrode provided on the gate layer (22, 322), A first passivation layer (32) that covers the electron supply layer (18), the gate layer (22, 322), and the gate electrode, is spaced apart from each other in a first direction (X), and includes a first source opening (32A) and a first drain opening (32B) disposed with the gate layer (22, 322) sandwiched therebetween in the first direction (X), A source electrode (52, 152) in contact with the electron supply layer (18) through the first source opening (32A), A drain electrode (54) in contact with the electron supply layer (18) through the first drain opening (32B), A first field plate electrode (40) provided on the first passivation layer (32); A second passivation layer (34) covering the first passivation layer (32) and the first field plate electrode (40); comprising The first field plate electrode (40) includes a plate main body portion (42) provided at a distance from the source electrode (52, 152) in the first direction (X), and a connection portion (44) that electrically connects the plate main body portion (42) and the source electrode (52, 152). The plate main body portion (42) is at least partially provided in a region between the gate electrode and the drain electrode (54) in a plan view, and extends in a second direction (Y) orthogonal to the first direction (X) in the plan view. The connection portion (44) is disposed between the plate main body portion (42) and the source electrode (52, 152) and above the gate electrode, and extends in the first direction (X) with the second direction (Y) as the width direction to connect the plate main body portion (42) and the source electrode (52, 152). The width of the connection portion (44) is shorter than the length of the plate main body portion (42) in the second direction (Y). A nitride semiconductor device.

[0106] (Appendix 2) The film thickness of the first field plate electrode (40) is thinner than the film thickness of the source electrode (52). The nitride semiconductor device according to Appendix 1.

[0107] (Appendix 3) The film thickness of the first passivation layer (32) is thinner than the film thickness of the second passivation layer (34). The nitride semiconductor device according to Appendix 1 or Appendix 2.

[0108] (Appendix 4) The film thickness of the first field plate electrode (40) is thinner than that of the second passivation layer (34). The nitride semiconductor device according to Appendix 1 or Appendix 2.

[0109] (Appendix 5) The area of the connection part (44) is 1 / 10 or less of the area of the plate main body part (42). The nitride semiconductor device according to any one of Appendices 1 to 4.

[0110] (Appendix 6) The width of the connection part (44) is 1 / 50 or less of the length of the plate main body part (42) in the second direction (Y). The nitride semiconductor device according to any one of Appendices 1 to 5.

[0111] (Appendix 7) The width of the connection part (44) is 5 μm or more and 10 μm or less. The nitride semiconductor device according to any one of Appendices 1 to 6.

[0112] (Appendix 8) The source electrode (152) is provided on the second passivation layer (34) and includes a field plate part (52C) extending toward the drain electrode (54). The field plate part (52C) covers the gate electrode in plan view. The end part (52D) of the field plate part (52C) closer to the drain electrode (54) is located closer to the drain electrode (54) than the end part of the first field plate electrode (40) closer to the drain electrode (54). The nitride semiconductor device according to any one of Appendices 1 to 7.

[0113] (Appendix 9) A third passivation layer (62) covering the source electrode (52), A second field plate electrode (64) provided on the third passivation layer (62) and electrically connected to the source electrode (52), and The second field plate electrode (64) is provided at least partially in a region between the gate layer (22) and the drain electrode (54) in a plan view. An end portion (62C) of the second field plate electrode closer to the drain electrode (54) is located closer to the drain electrode (54) than an end portion (42B) of the first field plate electrode (40) closer to the drain electrode (54). The nitride semiconductor device according to any one of Appendices 1 to 8.

[0114] (Appendix 10) A second source opening (34A) communicating with the first source opening (32A) is formed in the second passivation layer (34). A source opening (30A) constituted by the first source opening (32A) and the second source opening (34A) has an inner wall surface (31A) on which the connection portion (44) is exposed. The inner wall surface (31A) of the source opening (30A) includes an inclined surface inclined with respect to the thickness direction of the first passivation layer (32) and the second passivation layer (34). The connection portion (44) includes a connection end surface (44A) connected to the source electrode (52). The connection end surface (44A) is inclined corresponding to the inclined surface. The nitride semiconductor device according to any one of Appendices 1 to 9.

[0115] (Appendix 11) The plate main body portion (42) overlaps a part of the gate electrode (24). The nitride semiconductor device according to any one of Appendices 1 to 10.

[0116] (Appendix 12) The area of a region where the plate main body portion (42) and the gate electrode (24) overlap is smaller than the area of a non-overlapping region. The nitride semiconductor device according to any one of Appendices 1 to 11.

[0117] (Appended Note 13) A plurality of the connection portions (44) are provided at intervals in the second direction (Y). The nitride semiconductor device according to any one of Appended Notes 1 to 12.

[0118] (Appended Note 14) The gate layer (322) includes a ridge portion (331) where the gate electrode is disposed, a first extending portion (341) extending from the ridge portion toward the source electrode (52), a second extending portion (351) extending from the ridge portion toward the drain electrode (54), and the plate main body portion (42) covers an end portion (352) of the second extending portion closer to the drain electrode (54). The nitride semiconductor device according to any one of Appended Notes 1 to 13.

[0119] (Appended Note 15) The source electrode (52) includes a contact portion (52A) filled in the first source opening (32A) and an extending portion (52B) extending to the second passivation layer (34). The field plate portion (52C) extends from the extending portion (52B) toward the drain electrode (54). The nitride semiconductor device according to Appended Note 8.

[0120] The above description is merely illustrative. Those skilled in the art can recognize that there are more conceivable combinations and substitutions other than the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to include all alternatives, modifications, and changes included within the scope of the present disclosure including the claims.

Description of Reference Numerals

[0121] 10 Nitride semiconductor device 12 Semiconductor substrate 14 Buffer layer 16 Electron traveling layer 18 Electron supply layer 20 Two-dimensional electron gas 22 Gate layer 22A First end 22B Second end 24 Gate electrode 30 Passivation layer 30A Source opening 30B Drain opening 30S Upper surface 31A Inner wall surface 32 First passivation layer 32A First source opening 32B First drain opening 34 Second passivation layer 34A Second source opening 34B Second drain opening 40 First field plate electrode 42 Plate main body 42A First end 42AA First connection part 42AB Second connection part 42B Second end 42C Third end 42D Fourth end 44 Connection part 44A Connection end face 52 Source electrode 52A Contact part 52B Extension part 52C Field plate part 52D End 54 Drain electrode 54A Contact part 54B Extension part 62 Third passivation layer 64 Second field plate electrode 64c End 72 Gate wiring 73 Via wiring 74 Source wiring 75 Via wiring 76 Drain wiring 77 via wiring 82 nitride semiconductor layer 84 first metal layer 86 second metal layer 88 third metal layer 110 nitride semiconductor device 152 source electrode 210 nitride semiconductor device 310 nitride semiconductor device 322 gate layer 331 ridge portion 332 upper surface 333 source side surface 334 drain side surface 341 first extending portion 351 second extending portion 352 end portion 410 nitride semiconductor device

Claims

1. An electron transport layer composed of a nitride semiconductor, an electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a larger bandgap than the electron transport layer, a gate layer provided on the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity, a gate electrode provided on the gate layer, a first passivation layer covering the electron supply layer, the gate layer, and the gate electrode, including a first source opening and a first drain opening that are spaced apart from each other in a first direction and sandwich the gate layer in the first direction, a source electrode in contact with the electron supply layer through the first source opening, a drain electrode in contact with the electron supply layer through the first drain opening, a first field plate electrode provided on the first passivation layer, a second passivation layer covering the first passivation layer and the first field plate electrode, comprising, the first field plate electrode includes a plate main body portion provided spaced apart from the source electrode in the first direction, and a connection portion that electrically connects the plate main body portion and the source electrode, the plate main body portion is at least partially provided in a region between the gate electrode and the drain electrode in a plan view, and extends in a second direction orthogonal to the first direction in the plan view, the connection portion is between the plate main body portion and the source electrode and is disposed above the gate electrode, and extends in the first direction with the second direction as a width direction to connect the plate main body portion and the source electrode, the width of the connection portion is shorter than the length of the plate main body portion in the second direction, a nitride semiconductor device.

2. The film thickness of the first field plate electrode is thinner than the film thickness of the source electrode. The nitride semiconductor device according to Claim 1.

3. The film thickness of the first passivation layer is thinner than the film thickness of the second passivation layer. The nitride semiconductor device according to Claim 1 or Claim 2.

4. The film thickness of the first field plate electrode is thinner than the second passivation layer. The nitride semiconductor device according to Claim 1 or Claim 2.

5. The area of the connection portion is 1 / 10 or less of the area of the plate main body portion. The nitride semiconductor device according to Claim 1.

6. The width of the connection part is 1 / 50 or less with respect to the length of the plate main body part in the second direction. The nitride semiconductor device according to claim 1.

7. The width of the connection part is 5 μm or more and 10 μm or less. The nitride semiconductor device according to claim 1.

8. The source electrode is provided on the second passivation layer and includes a field plate portion extending toward the drain electrode. The field plate portion covers the gate electrode in plan view. The end portion of the field plate portion closer to the drain electrode is located closer to the drain electrode than the end portion of the first field plate electrode closer to the drain electrode. The nitride semiconductor device according to claim 1.

9. A third passivation layer covering the source electrode, A second field plate electrode provided on the third passivation layer and electrically connected to the source electrode, and includes The second field plate electrode is provided at least partially in a region between the gate layer and the drain electrode in plan view. The end portion of the second field plate electrode closer to the drain electrode is located closer to the drain electrode than the end portion of the first field plate electrode closer to the drain electrode. The nitride semiconductor device according to claim 1.

10. A second source opening communicating with the first source opening is formed in the second passivation layer. The source opening formed by the first source opening and the second source opening has an inner wall surface on which the connection part is exposed. The inner wall surface of the source opening includes an inclined surface inclined with respect to the thickness direction of the first passivation layer and the second passivation layer. The connection part includes a connection end surface connected to the source electrode. The connection end surface is inclined corresponding to the inclined surface. The nitride semiconductor device according to claim 1.

11. The plate main body part overlaps a part of the gate electrode. The nitride semiconductor device according to claim 1.

12. The area of the region where the plate main body part and the gate electrode overlap is smaller than the area of the non-overlapping region. The nitride semiconductor device according to claim 1.

13. A plurality of the connection parts are provided spaced apart in the second direction. The nitride semiconductor device according to claim 1.

14. The gate layer is a ridge part where the gate electrode is disposed, a first extending portion extending from the ridge portion toward the source electrode; a second extending portion extending from the ridge portion toward the drain electrode; and the plate main body portion covers an end portion of the second extending portion closer to the drain electrode. The nitride semiconductor device according to claim 1.

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