Semiconductor device

Abstract

To provide a semiconductor device having high withstand voltage.SOLUTION: A semiconductor device includes a semiconductor substrate 11, an embedded semiconductor layer 13 provided over the semiconductor substrate 11, an epithelial semiconductor layer 14 provided over the embedded semiconductor layer 13, a first element region 50A that is provided in the epithelial semiconductor layer 14, and a first isolation structure that surrounds the first element region 50A in a plan view. The first isolation structure TA includes a first trench arranged to extend from a surface of the epithelial semiconductor layer 14 to a position where the first trench penetrates the embedded semiconductor layer 13, a first conductive region 17A provided inside of the first trench through a first isolation layer 16A1, and a first isolation region 16A2 provided inside of the first trench and at an area deeper than the first conductive region 17A inside of the first trench. The depth of the first conductive region 17A is shallower than the depth of an upper surface position of the embedded semiconductor layer 13.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a deep trench isolation (DTI) structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The present disclosure provides a semiconductor device capable of improving breakdown voltage.

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, an embedded semiconductor layer provided on the semiconductor substrate, an epitaxial semiconductor layer provided on the embedded semiconductor layer, a first element region provided in the epitaxial semiconductor layer, and a first isolation structure surrounding the first element region in a plan view. The first isolation structure includes a first trench extending from the surface of the epitaxial semiconductor layer to a position penetrating the embedded semiconductor layer, a first conductive region provided inside the first trench via a first insulating layer, and a first insulating region provided in a region deeper than the first conductive region inside the first trench. The depth of the first conductive region is shallower than the upper surface position of the embedded semiconductor layer.

Brief Description of Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0007] [Detailed Description]

[0008] Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0009] FIG. 1 is a plan view of a semiconductor chip 100 (semiconductor device). First, an XYZ three-dimensional orthogonal coordinate system is set. The thickness direction (depth direction) of the semiconductor chip 100 is defined as the Z-axis direction. A direction perpendicular to the Z-axis is defined as the X-axis, and a direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis.

[0010] The semiconductor chip 100 in this example includes a bipolar transistor region 100B, a CMOS circuit region 100C, and a DMOS transistor region 100D. The bipolar transistor region 100B includes one or more bipolar transistors and is an analog block to which analog signals such as signals from various sensors are input. The CMOS circuit region 100C includes a plurality of field-effect transistors constituting one or more CMOS (complementary metal oxide semiconductor) circuits and is a digital block to which digital signals are input. The DMOS transistor region 100D includes one or more DMOS (double-diffused metal oxide semiconductor - FET (field-effect transistor)) and is a power block capable of processing high-voltage signals. The semiconductor chip 100 in this example is a BCD (BIPOLAR - CMOS - DMOS) chip. In a BCD chip, for example, a sensor signal can be input to the analog block, a control signal can be input to the digital block, and based on these outputs, the output signal of the power block can be controlled.

[0011] Each block includes one or more device regions. For example, within the DMOS transistor region 100D, a plurality of device regions are set, and each device region includes a transistor surrounded by an isolation structure. The semiconductor chip 100 in this example is a BCD chip, but the isolation structure can also be applied to semiconductor chips of types other than BCD chips.

[0012] FIG. 2 is a plan view of a device region in a semiconductor device.

[0013] The figure shows a plurality of device regions. The first device region 10A and the second device region 10B are shown. These device regions are for convenience of explanation and there is no physical boundary line in the actual device regions.

[0014] Within the first device region 10A, a first element region 50A (device) is formed. In a plan view seen from the Z-axis direction, the first element region 50A is surrounded by a first isolation structure TA. The first element region 50A in this example constitutes a transistor. The first isolation structure TA includes a trench having a first width WA and constitutes deep trench isolation (DTI). Note that the first device region 10A is adjacent to the second device region 10B. An exemplary depth of the trench is about 10 μm to 30 μm.

[0015] Within the second device region 10B, a second element region 50B (device) is formed. In a plan view seen from the Z-axis direction, the second element region 50B is surrounded by a second isolation structure TB. The second element region 50B in this example constitutes a transistor. The second isolation structure TB includes a trench having a second width WB and constitutes deep trench isolation (DTI). An exemplary depth of the trench is about 10 μm to 30 μm.

[0016] The first width WA of the trench surrounding the first element region 50A is set relatively narrow so that the second width WB > the first width WA is satisfied. The first width WA (X-axis direction width) is, for example, 1.25 μm. The second width WB (X-axis direction width) is, for example, 3 μm. Each width can be defined by the opening width of the trench formed in the semiconductor material. When an insulating layer is formed on the surface of the semiconductor material, the interface position between the semiconductor material and the insulating layer can be used as the reference position for defining the width. The exemplary range of the first width WA is 1 μm ≤ WA ≤ 7 μm. The exemplary range of the second width WB is 0.5 μm ≤ WB ≤ 5 μm. Note that the Y-axis direction width of the trench is the same as the X-axis direction width.

[0017] FIG. 3 is a diagram showing a cross-sectional configuration of a device region in a semiconductor device. This figure shows the cross-sectional configuration of the device region along the X1-X1 arrow line in FIG. 2.

[0018] The semiconductor device includes a P-type (first conductivity type) semiconductor substrate 11, a P-type first epitaxial semiconductor layer 12, an N-type (second conductivity type) buried semiconductor layer 13, an N-type second epitaxial semiconductor layer 14, and an insulating region 18 on the substrate surface side. The first epitaxial semiconductor layer 12 is formed on the semiconductor substrate 11. The buried semiconductor layer 13 is formed on the first epitaxial semiconductor layer 12. The second epitaxial semiconductor layer 14 is formed on the buried semiconductor layer 13.

[0019] The semiconductor device includes a first isolation structure TA and a second isolation structure TB. Inside the first isolation structure TA, the first element region 50A is located. Inside the second isolation structure TB, the second element region 50B is located. The first epitaxial semiconductor layer 12 may be omitted. The first element region 50A and the second element region 50B are, for example, transistors, respectively, but may be other devices.

[0020] A specific example of the first element region 50A is a DMOS-FET. The first element region 50A includes a first N-type well region 51 A1 and the first N-type well region 51A1 The first drain region 52 formed therein A1 and the first P-type well region 53 A and the first P-type well region 53 A The first source region 54 formed therein A is provided. On the first P-type well region 53 A a first gate insulating film 55 A1 is provided via which a first gate electrode 56 A1 is provided. When a positive potential is applied to the first gate electrode 56 A1 an N-type channel is formed in the surface layer of the first P-type well region 53 directly below the first gate electrode 56 A1 . Electrons in the first source region 54 A can reach the first drain region 52 through this N-type channel and the drift region in the first N-type well region 51 located below the left insulating region 18 A . A1 A1 A A2

[0021] The first element region 50A has a structure that is symmetric with respect to the YZ plane passing through the first source region 54. That is, the first element region 50A includes a second N-type well region 51 A and a second drain region 52 formed therein A2 and the second N-type well region 51 A2 . On the first P-type well region 53 A2 a second gate insulating film 55 A is provided via which a second gate electrode 56 A2 is provided. When a positive potential is applied to the second gate electrode 56 A2 an N-type channel is formed in the surface layer of the first P-type well region 53 directly below the second gate electrode 56 A2 . Electrons in the first source region 54 A2 can reach the second drain region 52 through this N-type channel and the drift region in the second N-type well region 51 located below the right insulating region 18 A . A A2 A2

[0022] ​​​ A specific example of the second element region 50B is a DMOS-FET, which has a structure with a lower breakdown voltage requirement than the DMOS-FET in the first element region 50A. The second element region 50B includes a third N-type well region 51 B1 and the third N-type well region 51 B1 and a third drain region 52 formed therein B1 and a second P-type well region 53 B and the second P-type well region 53 B and a second source region 54 formed therein B . On the second P-type well region 53 B a third gate insulating film 55 B1 is provided, and via this, a third gate electrode 56 B1 is provided. When a positive potential is applied to the third gate electrode 56 B1 , an N-type channel is formed in the surface layer of the second P-type well region 53 B1 directly below the third gate electrode 56. Electrons in the second source region 54 B can reach the third drain region 52 B through this N-type channel and the drift region in the third N-type well region 51 B1 located at the lower part of the left insulating region 18 B1 .

[0023] The second element region 50B has a plane-symmetric structure with respect to the YZ plane passing through the second source region 54 B . That is, the second element region 50B includes a fourth N-type well region 51 B2 and the fourth N-type well region 51 B2 and a fourth drain region 52 formed therein B2 . On the second P-type well region 53 B a fourth gate insulating film 55 B2 is provided, and via this, a fourth gate electrode 56 B2 is provided. When a positive potential is applied to the fourth gate electrode 56 B2 , an N-type channel is formed in the surface layer of the second P-type well region 53 B2 directly below the fourth gate electrode 56. Electrons in the second source region 54 B can reach the fourth drain region 52 BThe electrons inside reach the fourth drain region 52 through the drift region inside this N-type channel and the fourth N-type well region 51 located at the lower part of the right insulating region 18. B2 B2

[0024] The first isolation structure TA is a deep trench isolation (DTI), which extends in the direction from the substrate surface to the deep part (Z-axis direction), and has a trench that penetrates the embedded semiconductor layer 13 and reaches a position above the semiconductor substrate 11. The depth of the trench of the first isolation structure TA is smaller than the depth of the trench of the second isolation structure TB. A first sinker region 15A doped with N-type impurities is formed on the inner wall surface of this trench. A first insulating region 16A is formed on the inner surface of the trench. The first insulating region 16A includes a first insulating layer 16A1 that constitutes the upper region and a first insulating region 16A2 that constitutes the lower region and fills the internal space of the trench. A first conductive region 17A is formed inside the first insulating layer 16A1 in the trench. Note that the sinker region extends from the surface side of the inner surface of the trench to the deep part and applies a potential to the embedded semiconductor layer 13.

[0025] Let the distance (the shortest distance in the Z-axis direction) between the deepest part of the first conductive region 17A and the embedded semiconductor layer 13 be the first distance DZ. The deepest part of the first conductive region 17A is located above the embedded semiconductor layer 13 by the first distance DZ.

[0026] The second isolation structure TB is a deep trench isolation (DTI), which extends in the direction from the substrate surface to the deep part (Z-axis direction), and has a trench that penetrates the embedded semiconductor layer 13 and reaches the inside of the semiconductor substrate 11. A second sinker region 15B doped with N-type impurities is formed on the inner wall surface of this trench. A second insulating layer 16B is formed on the inner surface of the trench. A second conductive region 17B is formed inside the second insulating layer 16B in the trench. The deepest part of the second conductive region 17B penetrates the second insulating layer 16B and reaches the semiconductor substrate 11. At the upper end of the second conductive region 17B, a second bias application electrode E B (bias potential application terminal) is electrically connected.

[0027] In the second isolation structure TB, the second conductive region 17B is located adjacent to the embedded semiconductor layer 13 in the X-axis direction. In many cases, the potential of the embedded semiconductor layer 13 is high, and the potential of the second conductive region 17B is set low like the ground potential. In this case, a large potential difference is generated between the embedded semiconductor layer 13 and the second conductive region 17B, and the electric field strength becomes high in this region. When this electric field strength is equal to or higher than the threshold value at which a leakage current to the deep part of the substrate occurs, a leakage current is generated. Therefore, as an element in the second isolation structure TB, a transistor with relatively low breakdown voltage and low operating voltage can be used compared to the elements in the first isolation structure TA so that the electric field strength does not exceed the threshold value.

[0028] On one hand, in the first isolation structure TA, the first conductive region 17A is not located adjacent to the embedded semiconductor layer 13 in the X-axis direction. That is, the embedded semiconductor layer 13 and the first conductive region 17A are separated along the Z-axis direction. The electric field strength is inversely proportional to the distance. Therefore, the electric field strength between the embedded semiconductor layer 13 and the first conductive region 17A can be reduced according to the distance. An example of the first distance DZ between the deepest part of the first conductive region 17A and the embedded semiconductor layer 13 can be set to be 0.1 μm or more and 10 μm or less. In other words, the first distance DZ between the first conductive region 17A and the upper surface position of the embedded semiconductor layer 13 satisfies the following relationship: 0.1 μm ≤ DZ ≤ 10 μm. When the first distance DZ is smaller than the lower limit value, the electric field strength between them becomes high. When this electric field strength is a value equal to or higher than the threshold value, the electric field strength between the embedded semiconductor layer 13 and the first conductive region inside the first trench becomes high, and there is a risk of generating a leakage current deep into the substrate. Therefore, the first distance DZ is set to a value that can suppress the substrate leakage current. The upper limit value of the first distance DZ can be set to be smaller than the thickness of the second epitaxial semiconductor layer 14. This is because the first conductive region 17A is embedded in the second epitaxial semiconductor layer 14. In other words, the upper limit value of the first distance DZ can also be set to the thickness of the second epitaxial semiconductor layer 14. From the perspective of relaxing the above-mentioned electric field strength, the lower limit value of the first distance DZ can be set to, for example, 0.2 μm, 0.5 μm, 1 μm, or 2 μm. The greater the value of the first distance DZ, the greater the effect of relaxing the electric field strength.

[0029] In the first isolation structure TA, since the first conductive region 17A does not reach the embedded semiconductor layer 13, it can withstand use in a higher voltage environment than the second isolation structure TB. For example, the element region (device) in the first isolation structure TA is a FET used in the range of 100V to 200V, and the element region (device) in the second isolation structure TB is a FET used in the range of 1.5V to 5V. The operating voltages of these devices correlate with the potentials of the second epitaxial semiconductor layers 14 corresponding to the respective devices. In other words, the first element region 50A and the second element region 50B have a structure in which the potential of the second epitaxial semiconductor layer 14 corresponding to the first element region 50A is set to be higher than the potential of the second epitaxial semiconductor layer 14 corresponding to the second element region 50B. In the first element region 50A used at a relatively high voltage, the potential of the second epitaxial semiconductor layer 14 becomes high, and in the second element region 50B used at a relatively low voltage, the potential of the second epitaxial semiconductor layer 14 becomes low.

[0030] The second distance DX is the X-axis direction distance (the shortest distance in the X-axis direction) between the first sinker region 15A and the first N-type well region 51 A1 (or the second N-type well region 51 A2 ). In this example, the second distance DX is also the X-axis direction distance (the shortest distance in the X-axis direction) between the second sinker region 15B and the third N-type well region 51 B1 (or the fourth N-type well region 51 B2 ), but these values may be different. In this example, the first drain region 52 A1 , the second drain region 52 A2、 the third drain region 52 B1 , and the fourth drain region 52 B2A positive potential for attracting N-channel electrons is applied. The potential of each drain region provides a potential to the N-type well region containing it. The second distance DX determines the electric field between the N-type well region and the sinker region. That is, the larger the second distance DX, the smaller the electric field strength. When the second distance DX is small, the electric field strength becomes higher than the threshold value, which causes a leakage current. Also, if the second distance DX is too large, the element size becomes large. From the viewpoint of suppressing such problems, an example of the second distance DX can be set to be 1 μm or more and 5 μm or less.

[0031] FIG. 4 is a diagram showing a cross-sectional configuration of a device region.

[0032] The difference in the structure shown in FIG. 3 of this structure is that a first bias application electrode E A (bias potential application terminal) for bias application is connected to the first conductive region 17A. Other configurations are the same as those shown in FIG. 3. The first bias application electrode E A can be given a low fixed potential such as a ground potential (0V). The first bias application electrode E A can be given an intermediate potential that is higher than 0V and lower than the potential of the second bias application electrode E B on the second isolation structure side. The first conductive region 17A can stabilize the potential around the first element region 50A and suppress the intrusion of noise, but by giving a fixed potential, these effects can be increased. When an intermediate potential is given to the first bias application electrode E A , the potential difference between the first conductive region 17A and the embedded semiconductor layer 13 becomes small, and the electric field strength decreases. That is, the above-mentioned leakage current is less likely to occur, and the breakdown voltage increases.

[0033] FIG. 5 is a diagram showing a cross-sectional configuration of a device for explaining a manufacturing method.

[0034] When manufacturing the above structure, first, a semiconductor substrate 11 is prepared (Fig. 5(A)). Next, a P-type first epitaxial semiconductor layer 12, an N-type buried semiconductor layer 13, and an N-type second epitaxial semiconductor layer 14 are sequentially formed on the semiconductor substrate 11 (Fig. 5(B)). The buried semiconductor layer 13 can be formed using an ion implantation method or the like. For the formation of the epitaxial layer, a chemical vapor deposition (CVD) method using a source gas (e.g., SiH4) containing a raw material constituting the semiconductor can be used.

[0035] Next, a resist is applied to the surface of the N-type second epitaxial semiconductor layer 14, exposed by an exposure apparatus, and developed to form a mask MSK having a pattern with an annular opening in plan view (Fig. 5(C)). Through the opening of the mask MSK, the substrate including the second epitaxial semiconductor layer 14 is etched to form a first trench 20A and a second trench 20B. The first trench 20A penetrates the second epitaxial semiconductor layer 14 and the buried semiconductor layer 13 and reaches the inside of the first epitaxial semiconductor layer 12. The second trench 20B penetrates the second epitaxial semiconductor layer 14, the buried semiconductor layer 13, and the first epitaxial semiconductor layer 12 and reaches the inside of the semiconductor substrate 11. The width of the first trench 20A (the width in the X-axis direction in the figure) is narrower than the width of the second trench 20B (the width in the X-axis direction in the figure), and has a shape in which it is relatively difficult for the conductive material to enter the inside. The depth of the second trench 20B is larger than the depth of the first trench 20A.

[0036] Next, N-type impurities are added to the inner wall surfaces of the first trench 20A and the second trench 20B to form N-type first sinker regions 15A and second sinker regions 15B (FIG. 5(D)). Thereafter, in an oxygen (O2) atmosphere, the inner surface of the trench is thermally oxidized to form an oxide film (thermal oxide film). Thereafter, an additional oxide film is formed on the thermal oxide film by a CVD method using TEOS (tetraethyl orthosilicate) or the like. Through these steps, first insulating regions 16A and second insulating layers 16B made of these oxide films are formed on the inner surfaces of the first trench 20A and the second trench 20B. The first insulating region 16A includes not only the first insulating layer 16A1 but also a first insulating region 16A2 filled in the lower region on the bottom surface side of the first trench 20A.

[0037] Next, anisotropic etching is performed in the depth direction of the second trench 20B to remove the second insulating layer 16B located on the trench bottom surface. Anisotropic etching of the first trench 20A may be performed, but the first insulating region 16A2 located at the bottom of the first trench 20A is not removed. As the anisotropic etching, dry etching can be used, and SiO2 can be physically or chemically removed using plasma or an ion beam. As the dry etching, reactive ion etching (RIE) or the like can be used.

[0038] Next, a conductive material is embedded inside the first trench 20A and the second trench 20B whose inner surfaces are covered with an insulating layer to form a first conductive region 17A and a second conductive region 17B. An exemplary conductive material is polysilicon doped with impurities, and as the embedding method, a sputtering method or a CVD method can be used. After the formation of the first conductive region 17A and the second conductive region 17B, the masks used in these steps are removed, and if necessary, the exposed surface of the substrate is chemically mechanically polished (CMP).

[0039] Thereafter, a mask is formed again on the exposed surface of the substrate, and using this mask, etching is performed to form recesses in the substrate surface, and the inside of the recesses is filled with an insulating material (such as SiO2) to form the insulating region 18 shown in FIG. 3 or FIG. 4. The insulating region 18 may be formed by thermal oxidation of the substrate surface. The insulating region 18 can be a field oxide film or shallow trench isolation (STI), etc.

[0040] In a plan view, a first element region 50A and a second element region 50B are formed in a region surrounded by the first and second isolation structures. That is, N-type impurities are added using a mask for forming an N-type well region to form an N-type well, P-type impurities are added using a mask for forming a P-type well to form a P-type well region, and a source region and a drain region are formed in each well region. When the source region and the drain region are N-type, N-type impurities are added to these regions. As a method for adding impurities, an ion implantation method can be used, but a diffusion method may also be used.

[0041] The materials of the semiconductor device described above will be explained.

[0042] The semiconductor substrate 11, the first epitaxial semiconductor layer 12, the buried semiconductor layer 13, the second epitaxial semiconductor layer 14, the well region, the drain region, and the source region constituting the transistor can be formed using silicon (Si). As the semiconductor material, in addition to silicon, compound semiconductors such as SiC (silicon carbide) and gallium nitride (GaN) may be used. The insulating region 18, the first insulating region 16A, the second insulating layer 16B, and the gate oxide film are composed of silicon dioxide (SiO2), but insulating materials such as silicon nitride may also be used. The first conductive region 17A, the second conductive region 17B, and the gate electrode can be composed of polysilicon, but metals such as copper (Cu) or aluminum (Al), silicides, or alloys may also be used.

[0043] Assuming that the conductivity type of the semiconductor substrate 11 is P-type, an exemplary range of the impurity concentration is 1×10 16 / cm3 ~1×10 20 / cm 3 can be set to

[0044] Taking the conductivity type of the first epitaxial semiconductor layer 12 as P-type, an exemplary range of the impurity concentration is 1×10 14 / cm 3 ~1×10 17 / cm 3 can be set to. An exemplary thickness of the first epitaxial semiconductor layer 12 can be set to 0.5 μm or more and 20 μm or less.

[0045] Taking the conductivity type of the buried semiconductor layer 13 as N-type, an exemplary range of the impurity concentration is 1×10 16 / cm 3 ~1×10 21 / cm 3 can be set to. The impurity concentration of the phosphorus (N-type) addition region located deeper than the As distribution region in the buried semiconductor layer 13 is 1×10 14 / cm 3 ~1×10 18 / cm 3 can be set to. The thickness of the buried semiconductor layer 13 with high impurity concentration where As is added is 0.1 μm or more and 5 μm or less. The thickness of the region with low impurity concentration where phosphorus is added can also be set to 0.1 μm or more and 5 μm or less.

[0046] Taking the conductivity type of the second epitaxial semiconductor layer 14 as N-type, an exemplary range of the impurity concentration is 1×10 14 / cm 3 ~1×10 17 / cm 3 can be set to. An exemplary thickness of the second epitaxial semiconductor layer 14 can be set to 0.5 μm or more and 20 μm or less.

[0047] The impurity concentrations in the N-type well region and the P-type well region constituting the transistor are set higher than the impurity concentration of the second epitaxial semiconductor layer 14. The impurity concentrations in the drain region and the source region constituting the transistor are set higher than the impurity concentration of the well region, and an exemplary range is 1×10 15 / cm 3 ~5×10 19 / cm 3 and can be set to this.

[0048] The buried semiconductor layer 13 is formed by implanting N-type arsenic ions (As + ). At a position deeper than the buried semiconductor layer 13, by implanting N-type phosphorus ions (P + ), the change in impurity concentration in the thickness direction can be moderated. The exemplary implantation energy of the arsenic ions is 70 keV, and the doping amount is 1×10 15 / cm 2 . The exemplary implantation energy of the phosphorus ions is 1900 keV, and the doping amounts are 1×10 12 / cm 2 , 3×10 12 / cm 2 , 7×10 12 / cm 2 .

[0049] The isolation structure of the semiconductor device under these conditions was also examined using a simulator. The semiconductor device is composed of silicon. The depth of the trench in each isolation structure is 27 μm. Also, the ion implantation is performed after the formation of the first epitaxial semiconductor layer 12, and after the growth of the second epitaxial semiconductor layer 14, it is set so that the depth of the impurity concentration peak in the buried semiconductor layer 13 is about 10 μm from the substrate surface.

[0050] The width of the first trench (first width WA) of the first isolation structure TA was set to 1.25 μm. The depth position on the surface side of the As ion implantation region constituting the embedded semiconductor layer 13 is 9 μm from the substrate surface. The depth position of the deepest part of the first conductive region 17A (polysilicon) in the trench is 7 μm from the substrate surface, which is about 2 μm shallower than the depth position on the surface side of the embedded semiconductor layer 13.

[0051] When the voltage at which the substrate leakage current flows is defined as the breakdown voltage, the breakdown voltage in the case of the above P ion addition amount (1×10 12 / cm 2 ) is 102 V. The breakdown voltage in the case of the P ion addition amount (3×10 12 / cm 2 ) is 114 V. The breakdown voltage in the case of the P ion addition amount (7×10 12 / cm 2 ) is 96 V.

[0052] From the viewpoint of increasing the breakdown voltage (voltage withstand), when the embedded semiconductor layer 13 is formed by As ion implantation and P ion implantation, the N-type impurity concentration C N (peak concentration) in the embedded semiconductor layer 13 is as follows. That is, 1×10 16 / cm 3 ≦C N ≦1×10 21 / cm 3 . It is also possible to set it as 1×10 17 / cm 3 ≦C N ≦1×10 20 / cm 3 . Further, it is also possible to set it as 1×10 18 / cm 3 ≦C N ≦5×10 19 / cm 3 .

[0053] When the width of the second trench (second width WB) of the second isolation structure TB is 1.5 μm, in this example, only the depth position of the deepest part of the second conductive region 17B (polysilicon) in the trench is different from that of the first isolation structure TA. The deepest position of the second conductive region 17B is 13 μm from the substrate surface, which is about 4 μm deeper than the depth position on the surface side of the buried semiconductor layer 13. The breakdown voltage in the case of the above-mentioned P ion addition amount (1×10 12 / cm 2 ) is 78V. The breakdown voltage in the case of the P ion addition amount (7×10 12 / cm 2 ) is 96V.

[0054] As described above, in the case of the first isolation structure TA, when the first conductive region 17A (ground potential (or intermediate potential)) moves away from the buried semiconductor layer 13, the breakdown voltage (voltage withstand) is improved more than in the case of the second isolation structure TB. Phosphorus is added to the deep part side of the buried semiconductor layer 13, and the voltage withstand can be further increased by adjusting the P ion addition amount (impurity concentration on the deep part side of the buried semiconductor layer 13).

[0055] In addition, when the device formed in the element region is an N-channel DMOS-FET, a P-type contact region is provided adjacent to the N-type source region. Here, one or two or more P-type contact regions and one or two or more N-type source regions may be arranged alternately. Also, when forming a P-channel FET, the configuration is such that the N-type region and the P-type region are interchanged. When forming an FET, a gate oxide film and a gate electrode are formed on the channel formation planned region. Also, the first element region 50A and the second element region 50B are not limited to DMOS-FETs, and can also be other active devices or passive devices.

[0056] In the case of using N-type well regions and P-type well regions in bipolar transistors or CMOS circuits constituting the BCD chip, these regions can be formed in the same process as the formation process of the N-type well region and P-type well region of the DMOS-FET. Also, the impurities added to the first and second conductive regions in the trench can be P-type, and it is also possible to add P-type impurities in the semiconductor region at a position deeper than the bottom of the trench.

[0057] (Supplementary Note) As described above, the above semiconductor device can improve the breakdown voltage. Various embodiments in the present disclosure can be defined as the following supplementary notes.

[0058] [A1] A semiconductor device comprising: a semiconductor substrate (11); a buried semiconductor layer (13) provided on the semiconductor substrate (11); an epitaxial semiconductor layer (14) provided on the buried semiconductor layer (13); a first element region (50A) provided in the epitaxial semiconductor layer (14); and a first isolation structure (TA) surrounding the first element region (50A) in a plan view. The first isolation structure (TA) includes a first trench extending from the surface of the epitaxial semiconductor layer (14) to a position penetrating the buried semiconductor layer (13); a first conductive region (17A) provided inside the first trench via a first insulating layer (16A1); and a first insulating region (16A2) provided in a region inside the first trench at a position deeper than the first conductive region (17A). The depth of the first conductive region (17A) is shallower than the upper surface position of the buried semiconductor layer (13). Since the depth of the first conductive region 17A is shallower than the upper surface position of the buried semiconductor layer 13, the electric field strength caused by the potential difference between them becomes small. When the electric field strength becomes high, problems such as element breakdown or leakage current flowing occur, but in this structure, the electric field strength can be reduced, so the breakdown voltage can be improved.

[0059] [A2] In the semiconductor device according to A1, the first distance DZ between the first conductive region (17A) and the upper surface position of the embedded semiconductor layer (13) satisfies 0.1 μm ≤ DZ ≤ 10 μm. When the first distance DZ is smaller than the lower limit value, the electric field strength between them becomes high. If this electric field strength is a value equal to or higher than the threshold value, the electric field strength between the embedded semiconductor layer 13 and the first conductive region inside the first trench becomes high, and there is a possibility of generating a leakage current deep into the substrate. Therefore, the first distance DZ is set to a value that can suppress the substrate leakage current. The upper limit value of the first distance DZ can be set to the thickness of the second epitaxial semiconductor layer 14.

[0060] [A3] In the semiconductor device according to A1, the first conductive region (17A) is connected to a bias potential application terminal (E A ). By controlling the potential of the first conductive region 17A, the electric field strength between the first conductive region 17A and the embedded semiconductor layer 13 can be controlled, the generation of leakage current can be suppressed, and the breakdown voltage can be improved.

[0061] [A4] The semiconductor device according to A1 includes a second element region (50B) provided in the epitaxial semiconductor layer (14) and, in a plan view, a second isolation structure (TB) surrounding the second element region (50B). The second isolation structure (TB) includes a second trench extending from the surface of the epitaxial semiconductor layer (14) to a position penetrating the embedded semiconductor layer (13), and a second conductive region (17B) provided inside the second trench via an insulating layer (16B). The depth of the second conductive region (17B) is deeper than the lower surface position of the embedded semiconductor layer (13). When using a device that can be used at a breakdown voltage lower than that of the first isolation structure (TA), the second isolation structure (TB) can be used.

[0062] [A5] The semiconductor device according to A4, wherein the first element region (50A) and the second element region (50B) have a structure in which the potential of the epitaxial semiconductor layer (14) corresponding to the first element region (50A) is set to be higher than the potential of the epitaxial semiconductor layer (14) corresponding to the second element region (50B). In the first element region (50A) that is used at a relatively high voltage, the potential of the epitaxial semiconductor layer (14) becomes high, and in the second element region (50B) that is used at a relatively low voltage, the potential of the epitaxial semiconductor layer (14) becomes low. For example, as the first element region (50A), an FET operating at 200V is adopted, and as the second element region (50B), an FET operating at 5V is adopted.

[0063] Although various exemplary embodiments have been described above, various omissions, substitutions, and changes may be made without being limited to the above-described exemplary embodiments. Also, it is possible to form other embodiments by combining elements in different embodiments. Further, from the above description, it will be understood that various embodiments of the present disclosure are described in this specification for the purpose of explanation, and various changes can be made without departing from the scope and gist of the present disclosure. Therefore, the various embodiments disclosed in this specification are not intended to be limiting, and the true scope and gist are indicated by the claims.

Description of Reference Numerals

[0064] 10A... First device region, 10B... Second device region, 11... Semiconductor substrate, 12... First epitaxial semiconductor layer, 13... Embedded semiconductor layer, 14... Second epitaxial semiconductor layer, 15A... First sinker region, 15B... Second sinker region, 16A... First insulating region, 16A1... First insulating layer, 16A2... First insulating region, 16B... Second insulating layer, 17A... First conductive region, 17B... Second conductive region, 18... Insulating region, 20A... First trench, 20B... Second trench, 50A... First element region, 50B... Second element region, 51 A1 ,51 A2 ,51 B1 ,51 B2 …N-type well region, 52A1 …the first drain region, 52 A2 …the second drain region, 52 B1 …the third drain region, 52 B2 …the fourth drain region, 53 A ,53 B …P-type well region, 54 A …the first source region, 54 B …the second source region, 55 A1 …the first gate insulating film, 55 A2 …the second gate insulating film, 55 B1 …the third gate insulating film, 55 B2 …the fourth gate insulating film, 56 A1 …the first gate electrode, 56 A2 …the second gate electrode, 56 B1 …the third gate electrode, 56 B2 …the fourth gate electrode, 100... semiconductor device, 100B... bipolar transistor region, 100C... CMOS circuit region, 100D... DMOS transistor region, E A …the first bias application electrode, E B …the second bias application electrode, TA... the first isolation structure, TB... the second isolation structure, DZ... the first distance, DX... the second distance, MSK... mask, WA... the first width, WB... the second width.

Claims

1. A semiconductor substrate, An embedded semiconductor layer provided on the semiconductor substrate, An epitaxial semiconductor layer provided on the embedded semiconductor layer, A first element region provided in the epitaxial semiconductor layer, In a plan view, a first isolation structure surrounding the first element region, Comprising, The first isolation structure is, A first trench extending from the surface of the epitaxial semiconductor layer to a position penetrating the embedded semiconductor layer, A first conductive region provided inside the first trench via a first insulating layer, A first insulating region provided in a region deeper than the first conductive region inside the first trench, Comprising, The depth of the first conductive region is shallower than the upper surface position of the embedded semiconductor layer, A semiconductor device.

2. A first distance DZ between the first conductive region and the upper surface position of the embedded semiconductor layer is, 0.1 μm ≤ DZ ≤ 10 μm, Satisfying, The semiconductor device according to Claim 1.

3. The first conductive region is connected to a bias potential application terminal, The semiconductor device according to Claim 1.

4. A second element region provided in the epitaxial semiconductor layer, In a plan view, a second isolation structure surrounding the second element region, Comprising, The second isolation structure is, A second trench extending from the surface of the epitaxial semiconductor layer to a position penetrating the embedded semiconductor layer, A second conductive region provided inside the second trench via a second insulating layer, Comprising, The depth of the second conductive region is deeper than the lower surface position of the embedded semiconductor layer, The semiconductor device according to Claim 1.

5. The first element region and the second element region have a structure in which the potential of the epitaxial semiconductor layer corresponding to the first element region is set to be higher than the potential of the epitaxial semiconductor layer corresponding to the second element region, The semiconductor device according to Claim 4.

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