Semiconductor device and equipment

Abstract

To provide an advantageous technique for suppressing an increase in a chip area while providing power domains for individual clock lines.SOLUTION: A semiconductor device has a first region, a second region, and a third region. The third region extends in a first direction, and is disposed between the first region and the second region in a second direction orthogonal to the first direction, and a first clock line for transmitting a first clock and a second clock line for transmitting a second clock are disposed in the third region. A plurality of first power domains for the first clock line and a plurality of second power domains for the second clock line are disposed in the third region. A first buffer for buffering the first clock is disposed in each of the plurality of first power domains. A second buffer for buffering the second clock is disposed in each of the plurality of second power domains.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to semiconductor devices and equipment.

Background Art

[0002] In a semiconductor device, noise generated by a signal processing circuit may be transmitted through a power supply line to a clock line arranged in another location, thereby degrading the quality of the clock. Therefore, a plurality of power domains (power supply regions) may be arranged so as to separate the power supply of the signal processing circuit from the clock line. Although the relevance to the present application is low, Patent Document 1 describes a layout pattern in which a plurality of power domains and a plurality of hard macro cells are arranged.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] If the entire clock line is arranged within one power domain, a large amount of area resources are required, which may compress the area for other circuits. In particular, when each of a plurality of clock lines is arranged within an individual power domain, area resources corresponding to the number of clock lines are required, and the chip area may increase.

[0005] An object of the present invention is to provide an advantageous technique for suppressing an increase in chip area while providing a power domain for each individual clock line.

Means for Solving the Problems

[0006] One aspect of the present invention relates to a semiconductor device, the semiconductor device having a first region, a second region, and a third region, the third region extending in a first direction and being disposed between the first region and the second region in a second direction orthogonal to the first direction, a first clock line for transmitting a first clock and a second clock line for transmitting a second clock being disposed in the third region. A plurality of first power domains for the first clock line and a plurality of second power domains for the second clock line are disposed in the third region, a first buffer for buffering the first clock being disposed in each of the plurality of first power domains, and a second buffer for buffering the second clock being disposed in each of the plurality of second power domains.

Advantages of the Invention

[0007] According to the present invention, an advantageous technique is provided for suppressing an increase in chip area while providing power domains for individual clock lines.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] Hereinafter, a semiconductor device 100 according to an embodiment will be described. FIG. 1 is a diagram showing a schematic configuration of the semiconductor device 100. FIG. 2 is a diagram showing an example in which a plurality of clock lines and a plurality of power supply lines of the semiconductor device 100 are embodied. FIGS. 3, 4, and 5 are diagrams each enlarging a part of FIG. 2. The semiconductor device 100 has a first clock line and a second clock line as a plurality of clock lines in which power domains (power supply regions) are individually provided for power noise countermeasures. The semiconductor device 100 is, as an example, a photoelectric conversion device that generates a signal obtained by photoelectrically converting incident light. As an example of the photoelectric conversion device, there is an imaging device that generates an image. As other examples of the photoelectric conversion device, for example, there are a distance measuring device (a device for distance measurement using focus detection or TOF (Time Of Flight)), a photometric device (a device for measuring the amount of incident light), and the like. Further, the semiconductor device 100 may be a memory. Examples of the memory include a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a flash memory, and the like.

[0011] The semiconductor device 100 may have a first region R1, a second region R2, and a third region R3. The third region R1 may extend in a first direction and be disposed between the first region R1 and the second region R2 in a second direction orthogonal to the first direction. The third region R1 has a dimension in the first direction larger than that in the second direction. In other words, the longitudinal direction of the third region R1 coincides with the first direction. In the third region R3, a first clock line for transmitting a first clock and a second clock line for transmitting a second clock are disposed.

[0012] The first clock is input to a first clock terminal 101. The first clock input to the first clock terminal 101 is supplied to a first buffer 103 disposed in a first power domain 137 via a first conductive path 102 extending parallel to the first direction. The first buffer 103 buffers the received first clock and outputs it to a first conductive path 104 extending parallel to the first direction. The first clock output to the first conductive path 104 is supplied to a first buffer 105 disposed in a first power domain 138. The first buffer 105 buffers the received first clock and outputs it to a first conductive path 106 extending parallel to the second direction. The first conductive path 106 is connected to a first receiving portion 107 that receives the first clock. That is, in the third region R3, a first clock line including the first clock terminal 101, the first conductive path 102, the first buffer 103, the first conductive path 104, the first buffer 105, and the first conductive path 106 is disposed. Also, a plurality of first power domains 137 and 138 for the first clock line are disposed in the third region R3, and the first buffers 103 and 105 are respectively disposed in the plurality of first power domains 137 and 138. Thereby, the first clock input to the first clock terminal 101 is transmitted to the first receiving portion 107 while being buffered. The first receiving portion 107 is an example of at least one of the circuits disposed in the first region R1 and the circuits disposed in the second region R2.

[0013] The first power supply voltage terminal 112 for the first clock is connected to a plurality of first power domains 137, 138 via a first power supply voltage line 110 extending parallel to the first direction. The first power supply voltage line 110 is connected to the first receiving unit 107 via a first power supply voltage line 108 extending parallel to the second direction. The first ground voltage terminal 113 for the first clock is connected to the first power domains 137, 138 via a first ground voltage line 111 extending parallel to the first direction. The first ground voltage line 111 is connected to the first receiving unit 107 via a first ground voltage line 109 extending parallel to the second direction. The first power supply voltage line 110 and the first ground voltage line 111 constitute a first power line that supplies the first power to the plurality of first power domains 137, 138. Also, the first power supply voltage lines 110, 108 and the first ground voltage lines 111, 109 constitute a first power line that supplies the first power to the first receiving unit 107.

[0014] The second clock is input to the second clock terminal 114. The second clock input to the second clock terminal 114 is supplied to a second buffer 116 disposed in the second power domain 139 via a second conductive path 115 extending parallel to the first direction. The second buffer 116 buffers the received second clock and outputs it to a second conductive path 117 extending parallel to the first direction. The second clock output to the second conductive path 117 is supplied to a second buffer 118 disposed in the second power domain 140. The second buffer 118 buffers the received second clock and supplies it to a second buffer 120 disposed in the second power domain 141 via a second conductive path 119 extending parallel to the first direction. The second buffer 120 buffers the received second clock and outputs it to a second conductive path 121 extending parallel to the second direction. The second conductive path 121 is connected to a second receiving unit 122 that receives the second clock. That is, in the third region R3, a second clock line composed of a second clock terminal 114, a second conductive path 115, a second buffer 116, a second conductive path 117, a second buffer 118, a second conductive path 119, a second buffer 120, and a second conductive path 121 is disposed. Also, in the third region R3, a plurality of second power domains 139, 140, 141 for the second clock line are disposed, and second buffers 116, 118, 120 are respectively disposed in the plurality of second power domains 139, 140, 141. Thereby, the second clock input to the second clock terminal 114 is transmitted to the second receiving unit 122 while being buffered. The second receiving unit 122 is an example of at least one of the circuits disposed in the first region R1 and the circuits disposed in the second region R2.

[0015] The second power supply voltage terminal 127 for the second clock is connected to a plurality of second power domains 139, 140, 141 via a second power supply voltage line 125 extending parallel to the first direction. The second power supply voltage line 125 is connected to the second receiving unit 122 via a second power supply voltage line 123 extending parallel to the second direction. The second ground voltage terminal 128 for the second clock is connected to the second power domains 139, 140, 141 via a second ground voltage line 126 extending parallel to the first direction. The second ground voltage line 126 is connected to the second receiving unit 122 via a second ground voltage line 124 extending parallel to the second direction. The second power supply voltage line 125 and the second ground voltage line 126 constitute a second power line that supplies second power to a plurality of second power domains 139, 140, 141. Also, the second power supply voltage lines 125, 123 and the first ground voltage lines 126, 124 constitute a second power line that supplies second power to the second receiving unit 122.

[0016] The third power supply voltage terminal 129 is connected to the processing unit 142 via a third power supply voltage line 130 extending parallel to the first direction and a third power supply voltage line 144 extending parallel to the second direction. The third ground voltage terminal 131 is connected to the processing unit 142 via a third ground voltage line 132 extending parallel to the first direction and a third ground voltage line 143 extending parallel to the second direction. The power line constituted by the third power supply voltage lines 130, 144 and the third ground voltage lines 132, 143 is an example of a third power line that supplies third power to at least one of the circuits arranged in the first region R1 and the circuits arranged in the second region R2.

[0017] The third power supply voltage terminal 133 is connected to the processing unit 145 via a third power supply voltage line 134 extending parallel to the first direction and a third power supply voltage line 146 extending parallel to the second direction. The third ground voltage terminal 135 is connected to the processing unit 145 via a third ground voltage line 136 extending parallel to the first direction and a third ground voltage line 147 extending parallel to the second direction. The power lines composed of the third power supply voltage lines 134, 146 and the third ground voltage lines 136, 147 are an example of a third power line that supplies third power to at least one of the circuits arranged in the first region R1 and the circuits arranged in the second region R2.

[0018] In the first direction, the plurality of first power domains 137, 138 and the plurality of second power domains 139, 140, 141 can be arranged alternately. For example, a first power domain can be arranged between adjacent second power domains, and a second power domain can be arranged between adjacent first power domains. The first power line can be arranged to pass through at least one of the plurality of first power domains 137, 138 and at least one of the plurality of second power domains 139, 140, 141. Similarly, the second power line can be arranged to pass through at least one of the plurality of first power domains 137, 138 and at least one of the plurality of second power domains 139, 140, 141.

[0019] Also, for at least one of the circuits arranged in the first region R1 and the circuits arranged in the second region R2, first power can be supplied from the first power line, and first clock can be supplied from a first buffer arranged in at least one of the plurality of first power domains 137, 138. Similarly, for at least one of the circuits arranged in the first region R1 and the circuits arranged in the second region R2, second power can be supplied from the second power line, and second clock can be supplied from a second buffer arranged in at least one of the plurality of second power domains 139, 140, 141.

[0020] According to the above configuration, the clock and power are supplied from the supply source to the processing unit which is the supply destination through individual conductive paths, and it is possible to reduce the influence of power noise generated in a clock line other than the target clock line or in other clock lines on the clock of the target clock line.

[0021] Hereinafter, the structure of the power domain will be exemplarily described. FIGS. 6 and 7 are cross-sectional views showing configuration examples of the second power domains 139, 140, and 141. As illustrated in FIG. 6, the first power domains 137 and 138 may also have a similar configuration. The second ground voltage line 126 is connected to the ground terminal 206 of the second buffer (116, 118, or 120) via the stack via 202. Further, the second ground voltage line 126 is connected to the well isolation region 205 disposed in the semiconductor substrate 204 via the stack vias 201 and 203, respectively. Thereby, the ground terminal 206 of the second buffer (116, 118, or 120) and the well isolation region 205 are grounded. Also, the well isolation regions 205 of the plurality of second power domains are electrically separated from each other.

[0022] As illustrated in FIG. 7, the second power voltage line 125 is connected to the power terminal 304 of the second buffer (116, 118, or 120) via the stack via 301. Further, the second power voltage line 125 is connected to the well region 303 disposed in the semiconductor substrate 204 via the stack via 302. As illustrated in FIGS. 6 and 7, by electrically separating the target power domain from other power domains by the well isolation region 205, it is possible to suppress the transmission of power noise to the target power domain through the semiconductor substrate 204.

[0023] Hereinafter, a preferred arrangement example of the first power domain and the second power domain will be described with reference to FIGS. 8, 9, and 10. Here, as an example, the first power domain 137 and the second power domain 139 will be described as an example, but the same applies to other first power domains and other second power domains.

[0024] The first direction is parallel to the first axis 405, and the second direction is parallel to the second axis 406. Among the four vertices of the first power domain 1367, the lower left vertex closest to the intersection 407 of the first axis 405 and the second axis 406 is set as the starting point (A11) 401, and the lower right vertex among the four vertices of the first power domain 137 is set as the ending point (A12) 402. Also, among the four vertices of the second power domain 139, the lower left vertex closest to the intersection 407 is set as the starting point (A21) 403, and the lower right vertex among the four vertices of the second power domain 139 is set as the ending point (A22) 404.

[0025] In the above definitions, it is preferable that the arrangements of the first power domain 137 and the second power domain 139 satisfy at least one of the following condition 2 and condition 3 while satisfying the following condition 1. (Condition 1) The first power domain and the second power domain do not overlap. (Condition 2) The coordinate of A11 on the second axis 406 <= the coordinate of A21 on the second axis 406 <= the coordinate of A12 on the second axis 406 (Condition 3) The coordinate of A11 on the second axis 406 <= the coordinate of A22 on the second axis 406 <= the coordinate of A12 on the second axis 406 The example in FIG. 8 satisfies all of conditions 1, 2, and 3. The example in FIG. 8 is most advantageous for reducing the chip area of the semiconductor device. In the example of FIG. 9, conditions 1 and 2 are satisfied. The example in FIG. 10 satisfies conditions 1 and 3. The examples in FIGS. 9 and 10 are inferior to the example in FIG. 8, but are advantageous for reducing the chip area of the semiconductor device 100.

[0026] In another aspect, it is preferable that a plurality of first power domains and a plurality of second power domains are arranged such that there is a virtual straight line VSL passing in a direction parallel to the first direction (the first axis 405). Such an arrangement enables the first region R1 and the second region R2 to be arranged closer to each other, and thus is advantageous for reducing the chip area of the semiconductor device 100.

[0027] As described above, the semiconductor device 100 can be applied to, for example, a photoelectric conversion device that generates a signal by photoelectrically converting incident light. Hereinafter, a configuration example of a device in which the semiconductor device 100 is incorporated will be described with reference to FIG. 11. The device 1000 can include at least any one of an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090, in addition to the semiconductor device 100 configured as a photoelectric conversion device. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls the semiconductor chip 210. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0028] The processing device 1060 processes a signal output from the semiconductor device 100, for example, an image signal. The processing device 1060 is a semiconductor device such as a CPU or an ASIC for configuring an analog front end (AFE) or a digital front end (DFE). The display device 1070 is an EL display device or a liquid crystal display device that displays information obtained by processing a signal output from the semiconductor device 100, for example, an image. The storage device 1080 is a magnetic device or a semiconductor device that stores a signal output from the semiconductor device 100 or information obtained by processing it, for example, an image. The storage device 1080 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0029] The mechanical device 1090 has a movable part or a propulsion part such as a motor or an engine. In the device 1000, information obtained by processing a signal output from the semiconductor device 100 is displayed on the display device 1070 or transmitted to the outside by a communication device (not shown) provided in the device 1000. For this purpose, the device 1000 may further include a storage device 1080 and a processing device 1060 separately from the storage circuit and the arithmetic circuit included in the semiconductor device 100. The mechanical device 1090 may be controlled based on a signal output from the semiconductor device 100.

[0030] In addition, the device 1000 is suitable for electronic devices such as an information terminal having a photographing function (e.g., a smartphone or a wearable terminal) or a camera (e.g., a single-lens reflex camera, a compact camera, a video camera, a surveillance camera). The mechanical device 1090 in the camera can drive the components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in the camera can move the semiconductor device 100 for anti-vibration operation.

[0031] In addition, the device 1000 can be a transportation device such as a vehicle, a ship, or an aircraft. The mechanical device 1090 in the transportation device can be used as a moving device. The device 1000 as a transportation device is suitable for transporting the semiconductor chip 210 or for assisting and / or automating driving (operation) by means of a photographing function. The processing device 1060 for assisting and / or automating driving (operation) can perform processing for operating the mechanical device 1090 as a moving device based on the information obtained by the semiconductor chip 210. Alternatively, the device 1000 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analysis device such as an electron microscope, an office device such as a copying machine, or an industrial device such as a robot.

[0032] This specification and the drawings include the following disclosures. (Document name) Claims (Item 1) A semiconductor device having a first region, a second region, and a third region, wherein the third region extends in a first direction and is disposed between the first region and the second region in a second direction orthogonal to the first direction, and a first clock line for transmitting a first clock and a second clock line for transmitting a second clock are disposed in the third region, a plurality of first power domains for the first clock line and a plurality of second power domains for the second clock line are disposed in the third region, a first buffer for buffering the first clock is disposed in each of the plurality of first power domains, A second buffer for buffering the second clock is disposed in each of the plurality of second power domains. A semiconductor device characterized by the above. (Item 2) In the first direction, the plurality of first power domains and the plurality of second power domains are alternately arranged. The semiconductor device according to Item 1, characterized by the above. (Item 3) The first buffer disposed in at least one of the plurality of first power domains supplies the first clock to at least one of the circuit disposed in the first region and the circuit disposed in the second region. The semiconductor device according to Item 1 or 2, characterized by the above. (Item 4) In the third region, a first power line for supplying first power to the plurality of first power domains extends along the first direction. The semiconductor device according to Item 1 or 2, characterized by the above. (Item 5) For at least one of the circuit disposed in the first region and the circuit disposed in the second region, the first power is supplied from the first power line, and the first clock is supplied from a first buffer disposed in at least one of the plurality of first power domains. The semiconductor device according to Item 4, characterized by the above. (Item 6) The second buffer disposed in at least one of the plurality of second power domains supplies the second clock to at least one of the circuit disposed in the first region and the circuit disposed in the second region. The semiconductor device according to Item 3, characterized by the above. (Item 7) In the third region, a second power line for supplying second power to the plurality of second power domains extends along the first direction. The semiconductor device according to Item 5, characterized by the above. (Item 8) For at least one of the circuit disposed in the first region and the circuit disposed in the second region, the second power is supplied from the second power line, and the second clock is supplied from a second buffer disposed in at least one of the plurality of second power domains. The semiconductor device according to item 7, characterized in that. (Item 9) The first power line is arranged to pass through at least one of the plurality of first power domains and at least one of the plurality of second power domains. The second power line is arranged to pass through at least one of the plurality of first power domains and at least one of the plurality of second power domains. The semiconductor device according to item 8, characterized in that. (Item 10) In the third region, a third power line for supplying a third power to at least one of the circuit disposed in the first region and the circuit disposed in the second region is arranged. The semiconductor device according to item 9, characterized in that. (Item 11) The plurality of first power domains and the plurality of second power domains are arranged such that there is a virtual straight line passing in a direction parallel to the first direction. The semiconductor device according to any one of items 1 to 10, characterized in that. (Item 12) The plurality of first power domains and the plurality of second power domains are arranged on a semiconductor substrate and are electrically separated from each other. The semiconductor device according to any one of items 1 to 11, characterized in that. (Item 13) The semiconductor device according to any one of items 1 to 12, A processing device that processes a signal output from the semiconductor device, An apparatus characterized by comprising.

[0033] The invention is not limited to the above embodiments, and various changes and modifications are possible without departing from the spirit and scope of the invention. Therefore, the claims are appended to disclose the scope of the invention.

Explanation of Reference Numerals

[0034] R1: First region, R2: Second region, R3: Third region, 100: Semiconductor device, 137, 138: First power domain, 139, 140, 141: Second power domain, 103, 105: First buffer, 116, 118, 120: Second buffer

Claims

1. A semiconductor device having a first region, a second region, and a third region, wherein the third region extends in a first direction and is disposed between the first region and the second region in a second direction orthogonal to the first direction, and a first clock line for transmitting a first clock and a second clock line for transmitting a second clock are disposed in the third region, a plurality of first power domains for the first clock line and a plurality of second power domains for the second clock line are disposed in the third region, a first buffer for buffering the first clock is disposed in each of the plurality of first power domains, a second buffer for buffering the second clock is disposed in each of the plurality of second power domains. A semiconductor device characterized by the above.

2. In the first direction, the plurality of first power domains and the plurality of second power domains are alternately disposed. The semiconductor device according to claim 1, characterized by the above.

3. The first buffer disposed in at least one of the plurality of first power domains supplies the first clock to at least one of the circuit disposed in the first region and the circuit disposed in the second region. The semiconductor device according to claim 1, characterized by the above.

4. In the third region, a first power line for supplying first power to the plurality of first power domains extends along the first direction. The semiconductor device according to claim 1, characterized by the above.

5. For at least one of the circuit disposed in the first region and the circuit disposed in the second region, the first power is supplied from the first power line, and the first clock is supplied from the first buffer disposed in at least one of the plurality of first power domains. The semiconductor device according to claim 4, characterized by the above.

6. The second buffer disposed in at least one of the plurality of second power domains supplies the second clock to at least one of the circuit disposed in the first region and the circuit disposed in the second region. The semiconductor device according to claim 3, characterized by the above.

7. In the third region, a second power line for supplying second power to the plurality of second power domains extends along the first direction. The semiconductor device according to claim 5, characterized by the above.

8. For at least one of the circuit disposed in the first region and the circuit disposed in the second region, the second power is supplied from the second power line, and the second clock is supplied from a second buffer disposed in at least one of the plurality of second power domains. The semiconductor device according to claim 7, characterized in that.

9. The first power line is arranged to pass through at least one of the plurality of first power domains and at least one of the plurality of second power domains. The second power line is arranged to pass through at least one of the plurality of first power domains and at least one of the plurality of second power domains. The semiconductor device according to claim 8, characterized in that.

10. In the third region, a third power line for supplying a third power to at least one of the circuit disposed in the first region and the circuit disposed in the second region is arranged. The semiconductor device according to claim 9, characterized in that.

11. The plurality of first power domains and the plurality of second power domains are arranged such that there is a virtual straight line passing through the plurality of first power domains and the plurality of second power domains in a direction parallel to the first direction. The semiconductor device according to claim 1, characterized in that.

12. The plurality of first power domains and the plurality of second power domains are disposed on a semiconductor substrate and are electrically separated from each other. The semiconductor device according to claim 1, characterized in that.

13. A semiconductor device according to any one of claims 1 to 12; A processing device for processing a signal output from the semiconductor device; An apparatus, characterized in that it comprises.

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