Control substrate

Abstract

To suppress breakage due to cracks of a semiconductor element or developing cracking of a joint part of the semiconductor element and a wiring board at extremely low temperatures, and improve joint reliability of a control substrate.SOLUTION: A control substrate 10 includes: a wiring board 1 with a first main surface 1a and a second main surface 1b opposed to each other; an electrode 4 on the first main surface 1a of the wiring board 1; and a semiconductor element 2 joined to the electrode 4 by a conductive joint part 6. The conductive particles in the joint part 6 are silver, and the joint part 6 includes a conductive adhesive 5a and a conductive adhesive 5b surrounding the conductive adhesive 5a in planer view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a control board of a quantum computer realized using a dilution refrigerator or the like, and particularly relates to a bonding structure between a quantum chip or a quantum control chip mounted at an extremely low temperature near absolute zero and a wiring board.

Background Art

[0002] In recent years, the progress of quantum computer technology has been remarkable, and expectations for realizing a practical quantum computer have also been increasing in conjunction with it.

[0003] A quantum computer uses a superconducting logic-based device and is typically cooled to an extremely low temperature to function in a superconducting state. Patent Document 1 (Japanese Patent Translation of PCT International Publication No. 2021-523572) discloses a system including at least two sets of superconducting logic devices, a cooling device adapted to cool the logic devices to a first operating temperature, and an interconnection that couples the superconducting logic devices. Patent Document 2 (Japanese Patent Translation of PCT International Publication No. 2019-537239) discloses a quantum computing device in which a quantum device die and a control circuit die for controlling the operation of the quantum device die are arranged on a substrate. In both patent documents, the quantum device and the substrate are connected to each other by solder bumps or the like.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] A quantum computer operates at an extremely low temperature near absolute zero. In a control board that implements a quantum chip or a quantum control chip, various electronic components such as LSI (Large Scale Integration) are mounted on a wiring board via a joint (adhesive). The structural material of the joint has a problem of brittle fracture at extremely low temperatures, and it is necessary to prevent the occurrence of even a small crack. In addition, although semiconductor elements are connected to the electrodes of the wiring board using a conductive adhesive, at extremely low temperatures, the respective structural materials of the adhesive and the wiring board contract, and cracks occur between the members due to the difference in the linear expansion coefficients of the respective structural materials, resulting in a problem that the control board fails. Patent Documents 1 and 2 mention the reliability of the joints of electronic components at extremely low temperatures, but do not mention the joint structure.

[0006] An object of the present invention is to improve the bonding reliability in a control board.

Means for Solving the Problems

[0007] Among the embodiments disclosed in the present application, the outline of a representative one will be briefly described as follows.

[0008] A control board according to an embodiment includes a wiring board having a first main surface and a second main surface opposite to the first main surface, an electrode formed on the first main surface of the wiring board, and a semiconductor element adhered on the electrode via a conductive joint. Here, the conductive particles contained in the joint are silver, and the joint has a first conductive adhesive and a second conductive adhesive disposed so as to surround the outer periphery of the first conductive adhesive in a plan view.

Effects of the Invention

[0009] Among the inventions disclosed in the present application, the effects obtained by a representative one will be briefly described as follows.

[0010] According to the present invention, the bonding reliability in a control board can be improved.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, unless particularly necessary, explanations of the same or similar parts are not repeated in principle. In the drawings for explaining the embodiments, hatching may be added even in a plan view or a perspective view in order to make the configuration easier to understand. Furthermore, in the drawings for explaining the embodiments, hatching may be omitted in the cross-sectional view in order to make the configuration easier to understand.

[0013] <Details of Room for Improvement> Hereinafter, the technical room for improvement in the control board of the quantum computer will be described.

[0014] In a quantum computer, a control board is arranged on a stage cooled to an extremely low temperature such as 4K or 100mK. The control board includes a wiring board and semiconductor elements mounted on the wiring board. In the structure where the semiconductor elements are joined to the wiring board, the mounting of the semiconductor elements is performed by applying a conductive adhesive to the electrode portions on the wiring board and heating and curing the conductive adhesive to form a joint portion. As the conductive particles of the conductive adhesive, silver particles may be considered to be used, but copper particles may also be used.

[0015] For the wiring board, for example, an FR-4 (Flame Retardant Type 4) board may be considered to be used. This is a board formed by impregnating an epoxy resin into a glass woven fabric in which glass fibers are woven in a cloth shape, but since it has a large coefficient of linear expansion, it has the characteristic of being easily bent by temperature changes. On the other hand, a semiconductor element (semiconductor chip) has a small coefficient of linear expansion and is difficult to deform even when the temperature changes extremely.

[0016] In the control board, the semiconductor elements are connected to the wiring board via a conductive adhesive, but due to the difference in the coefficient of linear expansion between each component such as between the semiconductor element and the wiring board, or between the conductive adhesive and the wiring board, each member deforms at an extremely low temperature, and there is a risk of cracks occurring in each member and between each member. Specifically, there is a risk of cracks occurring in the semiconductor elements and the conductive adhesive. Also, brittle fracture is likely to occur at extremely low temperatures, and this becomes a factor in reducing the life of the control board, so the reliability of the control board is further impaired. Therefore, in the control board, there is room for improvement in that the bonding reliability between the wiring board and the semiconductor elements is low.

[0017] Therefore, in the following embodiments, a device is provided to solve the above-mentioned room for improvement. Hereinafter, the technical idea in this embodiment provided with this device will be described.

[0018] (Embodiment) This embodiment relates to an adhesive for connecting a semiconductor element (chip) mounted on a wiring board constituting a control board of a quantum computer and the wiring board. Hereinafter, by using materials with different properties for the base resin of the adhesive at the central part and the peripheral part of the chip, the stress generated in the adhesive and the chip in a control board that moves at extremely low temperatures will be described for suppression.

[0019] This embodiment will be described with reference to FIGS. 1 to 4. Among the directions shown in each figure, the X direction and the Y direction are directions along the upper surface of the flat wiring board 1 (see FIG. 1) without warping, and are directions orthogonal to each other in a plan view. The Z direction is a direction orthogonal to the X direction and the Y direction, and is also called the height direction or the thickness direction. The plan view referred to here means looking at the control board or the constituent members of the control board in the Z direction.

[0020] As shown in FIGS. 1 and 2, the control board 10 of this embodiment has a wiring board 1 and a semiconductor element 2. The wiring board 1 has a first main surface 1a and a second main surface 1b on the opposite side of the first main surface 1a in the Z direction. An electrode 4 is provided on the first main surface which is the upper surface of the wiring board 1. That is, the wiring board 1 is a printed board in which wiring patterns such as the electrode 4 are provided on the upper surface of an insulating board. An organic board such as an FR-4 board is used for the wiring board 1.

[0021] The semiconductor element 2 is mounted facing the wiring board 1 via the conductive joint 6 provided on the electrode 4. In other words, the semiconductor element 2 is adhered via the joint 6 on the electrode 4 provided on the first main surface 1a of the wiring board 1. The joint 6 is composed of a conductive adhesive 5a and a conductive adhesive 5b. In plan view, the conductive adhesive 5a is surrounded by the conductive adhesive 5b. That is, in plan view, the joint 6 has its central portion composed of the conductive adhesive 5a, and the periphery of the conductive adhesive 5a is covered with the conductive adhesive 5b. That is, the conductive adhesive 5b has an annular structure in plan view. The shapes of the semiconductor element 2 and the joint 6 in plan view are rectangular, and both the conductive adhesives 5a and 5b overlap the semiconductor element 2 in plan view. In other words, both the conductive adhesives 5a and 5b are covered by the back surface of the semiconductor element 2. However, unlike FIG. 1, as shown in FIG. 2, in plan view, a part of the conductive adhesive 5a may protrude outside the semiconductor element 2. In FIG. 2, the contour of the semiconductor element 2 is shown by a dashed line.

[0022] The conductive adhesive 5a has a higher adhesive strength than the conductive adhesive 5b, and the conductive adhesive 5b has a smaller curing shrinkage rate than the conductive adhesive 5a. In order to realize such a difference in characteristics between the conductive adhesives 5a and 5b, for example, it is preferable that the base resin of the conductive adhesive 5a is epoxy-based and the base resin of the conductive adhesive 5b is silicone-based.

[0023] The semiconductor element 2 preferably has a metallization 3 on the back surface on the side of the wiring board 1. When a back surface electrode (not shown) of the semiconductor element 2 is provided, by providing the metallization 3 covering the back surface of the semiconductor element 2, the conductive performance between the back surface electrode and the joint 6 can be enhanced. Also, by providing the metallization 3, the thermal conductivity between the semiconductor element 2 and the electrode 4 can be enhanced.

[0024] FIG. 3 shows a schematic diagram of a quantum computer. The quantum computer 20 shown in FIG. 3 includes a plurality of cooling stages (base plates, flanges) 11 to 15 that are vertically spaced apart from each other and arranged in a hierarchical manner. A stage 16 is provided above the cooling stage 11. Each of the cooling stages 11 to 15 is made of, for example, copper plated with gold, and is cooled to a lower temperature as it goes downward by a dilution refrigerator system. For example, in order from the top, the cooling stage 11 is cooled to 50K, the cooling stage 12 is cooled to 4K, the cooling stage 13 is cooled to 1K, and the cooling stage 11 is cooled to 100mK. The cooling stages are connected to each other by a plurality of wirings (control wirings, readout wirings, etc.) 19 made of an alloy containing copper. The temperature on the stage 16 is 300K (room temperature).

[0025] A quantum control chip 23 is mounted on the cooling stage 12 cooled to 4K. Also, a quantum chip 22 is mounted on the cooling stage 15 cooled to 100mK. The quantum chip 22 is a qubit array chip that performs quantum information processing using qubits. The quantum control chip 23 is an extremely low temperature analog chip that controls the quantum chip 22, and includes an extremely low temperature DA converter and an extremely low temperature AD converter. The quantum chip 22 is electrically connected to the quantum control chip 23, and the quantum control chip 23 is electrically connected to a comprehensive control chip (measurer) 24 provided on the stage 16.

[0026] The semiconductor element 2 shown in FIGS. 1 and 2 is used for the quantum chip 22 or the quantum control chip 23 shown in FIG. 3. That is, the control board 10 is installed on the cooling stage 12 or the cooling stage 15 and operates at an extremely low temperature of 77K or lower. Specifically, it is conceivable that the quantum control chip 23 is arranged between the cooling stage 12 and the cooling stage 11, and the quantum chip 22 is arranged below the cooling stage 15. When the semiconductor element 2 is the quantum control chip 23, the wiring board 1 is fixed to the cooling stage 12 by bolts or the like that penetrate the wiring board 1. Also, when the semiconductor element 2 is the quantum control chip 23, the wiring board 1 may be mounted on another wiring board that is the parent board as a daughter board, and the parent board may be fixed to the cooling stage 12 by bolts.

[0027] <Effects of the Embodiment> FIG. 4 shows how the wiring board 1 deforms at extremely low temperatures. When the wiring board 1 is an organic substrate, in an environment of 4K, which is the temperature of the area where the quantum control chip 23 is mounted in the dilution refrigerator, the central portion of the wiring board 1 bulges upward (toward the first main surface 1a), and stress is applied to the central portion. The semiconductor element 2 is affected by the deformation of the wiring board 1, and the stress applied to the central portion of the semiconductor element 2 becomes greater than that applied to the peripheral portion. The joint portion 6 is affected by the deformation of the wiring board 1, and the stress applied to the peripheral portion of the joint portion 6, particularly the corner portion, becomes greater than that applied to the central portion. The joint portion 6 is preferably formed of a conductive adhesive having a high adhesive strength and being less likely to generate voids. However, at extremely low temperatures, there is a concern that even a small crack may impair the connection reliability. Therefore, it is preferable that the peripheral portion of the joint portion 6 is formed of a conductive adhesive having a small curing shrinkage rate at low temperatures. Thus, in the present embodiment, the central portion of the joint portion 6 covered by the semiconductor element 2 is constituted by a conductive adhesive 5a having a high adhesive strength and being less likely to generate voids, and the periphery of the conductive adhesive 5a is constituted by a conductive adhesive 5b having a small curing shrinkage rate.

[0028] Specifically, the control board 10 of the present embodiment includes a wiring board 1 having a first main surface 1a and a second main surface 1b opposite to the first main surface 1a, an electrode 4 formed on the first main surface 1a of the wiring board 1, and a semiconductor element 2 adhesively bonded onto the electrode 4 via a conductive joint portion 6. Here, the conductive particles contained in the joint portion 6 are silver, and the joint portion 6 has a conductive adhesive 5a and a conductive adhesive 5b disposed so as to surround the outer periphery of the conductive adhesive 5a in a plan view.

[0029] Figure 5 shows in a table the evaluation results of an element sample in which the inventors repeated the heating and cooling cycle between 77K and 289K 500 times. When all of the joints 6 were joined with an epoxy-based conductive adhesive (Comparative Example 1), cracks occurred in 4 out of 6 semiconductor elements, and cracks occurred in 3 out of 6 joints 6. When all of the joints 6 were joined with a silicon-based conductive adhesive (Comparative Example 2), cracks occurred in 2 out of 6 semiconductor elements, and cracks occurred in 3 out of 6 joints 6. When the central portion of the joint 6 was joined with an epoxy-based conductive adhesive and the peripheral portion thereof was joined with a silicon-based conductive adhesive (Example 1), no cracks occurred in any of the 6 semiconductor elements, and cracks occurred in 1 out of 6 joints 6. When the central portion of the joint 6 was joined with a silicon-based conductive adhesive and the peripheral portion thereof was joined with an epoxy-based conductive adhesive (Comparative Example 3), cracks occurred in 3 out of 6 semiconductor elements, and cracks occurred in 2 out of 6 joints 6.

[0030] In the evaluations of Comparative Example 2 and Comparative Example 3, a large number of voids occurred, and they were connected to the cracks that occurred, impairing the reliability. This is because the base of the central portion mainly constituting the joint 6 was made of a silicon-based resin in which voids are more likely to occur than in an epoxy-based resin. From this result, it is necessary that after the conductive adhesive is heat-cured, the joint 6 has few voids and is in a good joint state. It can be seen that when only an adhesive with a small curing shrinkage rate at low temperature is used (Comparative Example 2), or when the joining is performed with a large joining area ratio (Comparative Example 3), the joint reliability is impaired when operating at extremely low temperatures. When using a conductive adhesive based on a silicon-based resin, as in Example 1, it is desirable to apply the silicon-based resin-based conductive adhesive only to an area where it is easy to discharge the voids to the outside of the joint 6, that is, the peripheral portion of the joint 6.

[0031] From the evaluation results shown in FIG. 5, as in the present embodiment, the central portion of the joint 6 covered by the semiconductor element 2 is formed of the conductive adhesive 5a having a high adhesive strength and hardly generating voids, and the periphery of the conductive adhesive 5a is formed of the conductive adhesive 5b having a small curing shrinkage rate. It can be seen that the generation and remaining of cracks and voids can be reduced. Therefore, by using the control board 10 of the present embodiment, brittle fracture in the semiconductor element 2 and the joint 6 can be suppressed even at an extremely low temperature of 77K or lower. Therefore, the bonding reliability of the control board 10 can be improved.

[0032] <Modification Example 1> The control board of this modification example will be described with reference to FIG. 6. In FIG. 6, the outline of the semiconductor element 2 is shown by a broken line.

[0033] As shown in FIG. 6, the shape of the conductive adhesive 5a in plan view may be substantially circular. That is, here, in the joint 6, the epoxy-based conductive adhesive 5a is formed so as to reach the center of the side surface of the semiconductor element 2 in plan view, and the silicon-based conductive adhesive 5b is formed so as to cover only the corners of the semiconductor element 2. Thereby, the stress load applied to the joint 6 under the corner of the semiconductor element 2 can be reduced. The portion where the stress is particularly large on the semiconductor element 2 and the joint 6 at an extremely low temperature is near the corners of the semiconductor element 2 in plan view. For this reason, by disposing the silicon-based conductive adhesive 5b directly below the corners (four corners) of the semiconductor element 2, a decrease in bonding reliability due to stress can be prevented, a high adhesive strength can be realized, and the generation of voids can also be prevented.

[0034] Note that the side surface of the joint 6 may be along the end surface of the semiconductor element 2 or may be gently inclined toward the electrode 4 (see FIG. 1). The joint 6 is preferably formed according to the size of the electrode 4 designed due to the constraints when wire-bonding the semiconductor element 2.

[0035] <Modification Example 2> The control board of this modification example will be described with reference to FIG. 7.

[0036] As shown in FIG. 7, here, the formation area of the silicon-based conductive adhesive 5b in the planar direction is formed to be equal to or less than the thickness of the joint portion 6 so that the voids 25 are discharged. That is, in the direction along the X-Y plane along the X direction and the Y direction (the direction along the first main surface 1a of the wiring board 1, the horizontal direction, the lateral direction), the size of the width of the conductive adhesive 5b at one end of the joint portion 6 is equal to or less than the thickness of the joint portion 6 (the thickness of the conductive adhesive 5b).

[0037] The conductive adhesive 5b containing a silicon-based resin is more likely to generate voids than the conductive adhesive 5a containing an epoxy-based resin. The upper limit of the size of the voids 25 generated in the joint portion 6 is determined by the thickness of the joint portion 6. As shown in FIG. 8, when a conductive adhesive 5b having a width equal to or greater than the thickness of the joint portion 6 is provided, if voids 25 are generated in the conductive adhesive 5b near the central portion of the semiconductor element 2, it is difficult to discharge the voids 25, and the voids 25 may remain in the joint portion 6. When the size of the voids 25 is large, it causes a decrease in the adhesive strength in the joint portion 6, joint failure, and further inhibits the heat conduction performance. Due to the ease of generation of the voids 25 in the conductive adhesive 5b, it is necessary to appropriately consider the formation area, that is, the width of the conductive adhesive 5b.

[0038] Here, the width of the conductive adhesive 5b at one end of the joint portion 6 in the lateral direction is set to be equal to or less than the thickness of the joint portion 6. However, the width of the conductive adhesive 5b here may be considered as the width directly under the semiconductor element 2 (the width in the region covered by the semiconductor element 2). That is, as shown in FIG. 2, when a part of the conductive adhesive 5b is provided outside the semiconductor element 2 in a plan view, even if the width of the conductive adhesive 5b is larger than the thickness of the joint portion 6, if the width of the conductive adhesive 5b directly under the semiconductor element 2 is equal to or less than the thickness of the joint portion 6, the voids twenty-five can be effectively discharged.

[0039] In addition, as a result of the analysis by the present inventors, if the formation ratio of the conductive adhesive 5a and the conductive adhesive 5b in a predetermined direction (any direction along the X-Y plane) in plan view is 5:1 on the diagonal line of the joint portion 6, or if the formation ratio of the second conductive adhesive is smaller than that, the void 25 generated in the joint portion 6 can be effectively discharged. In other words, in the lateral direction, if the width of the conductive adhesive 5b adjacent to one side surface of the conductive adhesive 5a is 1 / 5 or less of the width of the conductive adhesive 5a, the void 25 can be effectively discharged.

[0040] As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof.

[0041] In the conductive adhesive for joining the wiring board and the semiconductor element according to the present invention, the conductive particles are mainly composed of silver. In the joint portion formed of the conductive adhesive, the central portion is joined with a conductive adhesive having a high adhesive strength and good joinability, and the periphery thereof may be covered with a conductive adhesive having a small curing shrinkage rate. Each dimension, its ratio, and shape are not limited to the configuration of the figure, and the constituent members such as the semiconductor element and the wiring board to be used are arbitrary.

Explanation of Reference Numerals

[0042] 1 Wiring board 1a First main surface 1b Second main surface 2 Semiconductor element 3 Metallization 4 Electrode 5a, 5b Conductive adhesives 6 Joint portion 10 Control board

Claims

1. A wiring board having a first main surface and a second main surface on the opposite side of the first main surface; An electrode formed on the first main surface of the wiring board; A semiconductor element bonded onto the electrode via a conductive bonding portion; Characterized by comprising: The conductive particles contained in the bonding portion are silver; The bonding portion has a first conductive adhesive and a second conductive adhesive disposed so as to surround the outer periphery of the first conductive adhesive in a plan view, a control board.

2. In the control board according to Claim 1, The first conductive adhesive contains an epoxy resin; The second conductive adhesive contains a silicone resin, a control board.

3. In the control board according to Claim 1, The first conductive adhesive has a higher adhesive strength than the second conductive adhesive; The second conductive adhesive has a smaller curing shrinkage rate than the first conductive adhesive, a control board.

4. In the control board according to Claim 1, In a direction along the first main surface, the width of the second conductive adhesive adjacent to one side surface of the first conductive adhesive is 1 / 5 or less of the width of the first conductive adhesive, a control board.

5. In the control board according to Claim 1, In a direction along the first main surface, the width of the second conductive adhesive is equal to or less than the thickness of the second conductive adhesive, a control board.

6. In the control board according to Claim 1, Operating at 77 K or less, a control board.

7. In the control board according to Claim 1, The semiconductor element is a quantum chip or a quantum control chip, a control board.

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