MIM capacitor and method for manufacturing MIM capacitor

Abstract

To provide an MIM capacitor that reduces short-circuit defects caused by hillocks.SOLUTION: An MIM capacitor comprises a plurality of first electrodes that are provided on a substrate separate from each other in a specific direction, and a plurality of insulating parts that are provided on an opposite surface opposite to the adjacent plurality of first electrodes. A part of the substrate is exposed from a gap between the adjacent plurality of first electrodes.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a MIM capacitor and a method for manufacturing a MIM capacitor.

Background Art

[0002] FIG. 1 of Patent Document 1 discloses a technique for simultaneously forming electrodes and wiring that constitute a MIM (Metal Insulator Metal) capacitor without losing the degree of freedom in the design of the MIM capacitor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, when manufacturing a MIM capacitor, a raised portion called a hillock may occur due to thermal expansion of a part of the electrode. In the etching process of the electrode where the hillock occurs, if the position of the hillock portion and the gap (metal-free portion) formed in the electrode is the same, etching residue may occur at the bottom of the gap depending on the thickness of the hillock, and a short circuit failure may occur.

[0005] Based on the above circumstances, an object of the present disclosure is to provide a MIM capacitor and a method for manufacturing a MIM capacitor that reduce short circuit failures caused by hillocks.

Means for Solving the Problems

[0006] To solve the above problems, the MIM capacitor according to the present disclosure includes a plurality of first electrodes provided on a substrate so as to be separated from each other in a specific direction, and a plurality of insulating portions provided on an opposing surface where adjacent ones of the plurality of first electrodes face each other. A part of the substrate is exposed in a gap between adjacent ones of the plurality of first electrodes.

[0007] The method for manufacturing an MIM capacitor according to the present disclosure includes a first electrode forming step of forming a first electrode on a substrate, a first resist step of forming a first resist having a specific pattern on a surface of the first electrode opposite to the substrate side, a first etching step of etching the first electrode using the first resist to form a plurality of gaps in the first electrode and dividing the first electrode into a plurality of first electrodes provided on the substrate so as to be separated from each other in a specific direction, an insulating portion forming step of forming an insulating portion on an opposing surface where adjacent ones of the first electrodes face each other through the gaps, a second electrode forming step of forming a second electrode on a surface of the insulating portion opposite to the first electrode side, a second resist step of forming a second resist having a specific pattern on the second electrode, and a removing step of removing, by etching the second electrode and the insulating portion using the second resist, a portion of the second electrode and the insulating portion formed in the gaps that faces the substrate to expose a part of the substrate in the gaps.

[0008] The manufacturing method of the MIM capacitor according to the present disclosure includes a first electrode forming step of forming a first electrode on a substrate, a first resist step of forming a first resist with a specific pattern on a surface of the first electrode opposite to the substrate side, a first etching step of etching the first electrode using the first resist to form a plurality of gaps in the first electrode and dividing the first electrode into a plurality of first electrodes provided on the substrate away from each other in a specific direction, an insulating portion forming step of forming an insulating portion on an opposing surface where the adjacent first electrodes face each other through the gaps, a second electrode forming step of forming a second electrode on a surface of the insulating portion opposite to the first electrode side, a second resist step of forming a second resist with a specific pattern on the second electrode, a step of removing the second electrode formed in the gaps by etching the second electrode using the second resist, and a step of exposing a part of the substrate from the gaps by etching a part of the insulating portion formed in the gaps.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 3F

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 5H

Figure 5I

Embodiment for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are assigned to the same functions and configurations, and the description thereof will be omitted as appropriate.

[0011] (Embodiment) FIG. 1 is a cross-sectional view of the MIM capacitor 100 according to an embodiment of the present disclosure. The MIM capacitor 100 may include a plurality of first electrodes 1, a plurality of insulating portions 2, a plurality of second electrodes 3, a first Via (via) 4, a second Via 5, an interlayer insulating film 6, a third electrode 7, and a fourth electrode 8.

[0012] (First Electrode 1) The plurality of first electrodes 1 may be interpreted as an aluminum alloy (Al-Cu) provided on the substrate 20 so as to be separated from each other in a specific direction D. A gap GP may be formed between the first electrodes 1 adjacent to each other in the specific direction D. Note that transistors, contacts, metal wirings, vias, etc. may be provided between the MIM capacitor 100 and the substrate 20, and the substrate 20 may include transistors, contacts, metal wirings, vias, etc.

[0013] (Insulating Portion 2) Each of the plurality of insulating portions 2 may be interpreted as a silicon nitride film (SiN) that covers the surface of the first electrode 1. A part of the plurality of insulating portions 2 may be provided on the opposing surface OS where the adjacent plurality of first electrodes 1 face each other. A part of the plurality of insulating portions 2 may be provided on the tip surface 1a of a specific first electrode 1 among the plurality of first electrodes 1.

[0014] The opposing surface OS may be interpreted as a surface where the adjacent first electrodes 1 face each other through the plurality of gaps GP. The tip surface 1a may be interpreted as a surface on the side opposite to the substrate 20 side of each of the plurality of first electrodes 1.

[0015] (Second Electrode 3) The second electrode 3 may be interpreted as a titanium nitride film (TiN) covering the surface of the first electrode 1.

[0016] A part of the second electrode 3 may be provided on a surface 2a of the insulating portion 2 provided on the opposite side of the first electrode 1 side of the opposing surface OS. Specifically, a part of the second electrode 3 may be provided on the surface 2a of the insulating portion 2 on the opposite side of the first electrode 1 side of the insulating portion 2 located on the opposing surfaces OS of the first two of the plurality of first electrodes 1 shown in FIG. 1. The same applies to the second electrodes 3 of the second and third first electrodes 1 from the left and the second electrodes 3 of the third and fourth first electrodes 1 from the left. The second electrodes 3 adjacent in the specific direction D are not electrically connected to each other and are insulated by an interlayer insulating film 6 (for example, SiO) located in the gap GP. Since the adjacent second electrodes 3 are not electrically connected to each other, it can be said that a part of the upper surface 20a of the substrate 20 is exposed in the gap GP in a state where the interlayer insulating film 6 is not provided. The interlayer insulating film 6 located in the gap GP may be in contact with the upper surface 20a of the substrate 20. Thereby, insulation between the adjacent second electrodes 3 is ensured.

[0017] A part of the second electrode 3 may be provided on the insulating portion 2 provided on the remaining portion excluding a part of the surface (tip surface 1a) on the opposite side of the specific first electrode 1 from the substrate 20 side. Specifically, an insulating portion 2 is provided in a partial region of the tip surface 1a on the leftmost specific first electrode 1 among the plurality of first electrodes 1 shown in FIG. 1, and a part of the second electrode 3 may be provided on the surface 2a on the opposite side of the insulating portion 2 from the first electrode 1 side.

[0018] (First Via 4, Second Via 5) The first Via 4 and the second Via 5 may each be interpreted as a connection region that electrically connects the lower layer wiring and the upper layer wiring.

[0019] For the first Via 4, the first end 41 may be connected to the surface (tip surface 1a) on the opposite side of the first electrode 1 from the substrate 20 side. Also, for the first Via 4, the second end 42 on the opposite side of the first end 41 may be connected to the third electrode 7.

[0020] The second Via5 may have its third terminal 53 connected to the second electrode 3 provided on the side of the substrate 20 opposite to the first electrode 1. Specifically, the third terminal 53 may be connected to the second electrode 3 on the insulating portion 2 provided on the remaining portion of the surface of a specific first electrode, excluding a part of the surface on the side opposite to the substrate 20 side among the plurality of first electrodes 1. Also, for the second Via5, the fourth terminal 54 on the side opposite to the third terminal 53 may be connected to the fourth electrode 8.

[0021] Next, a method for manufacturing the MIM capacitor 100 will be described with reference to FIGS. 2A to 2H. FIGS. 2A to 2H are diagrams for explaining the method for manufacturing the MIM capacitor 100.

[0022] The method for manufacturing the MIM capacitor 100 may include a first electrode forming step shown in FIG. 2A, a first resist step shown in FIG. 2B, a first etching step shown in FIG. 2C, an insulating portion forming step shown in FIG. 2D, a second electrode forming step shown in FIG. 2D, a second resist step shown in FIG. 2E, two removing steps from FIGS. 2F to 2G, and a Via forming step shown in FIG. 2H.

[0023] In the first electrode forming step shown in FIG. 2A, the first electrode 1 is formed on the substrate 20 by sputtering.

[0024] In the first resist step shown in FIG. 2B, a first resist 30 with a specific pattern is formed on the surface (front end surface 1a) on the side of the substrate 20 opposite to the first electrode 1 by photolithography.

[0025] In the first etching step shown in FIG. 2C, by etching the first electrode 1 using the first resist 30, a plurality of first electrodes 1 are formed on the substrate 20 spaced apart from each other in a specific direction D, and a gap GP is formed between adjacent first electrodes 1.

[0026] After removing the first resist 30, the insulating portion forming step shown in FIG. 2D forms the insulating portion 2 by sputtering. Specifically, a part of the insulating portion 2 is formed on the surface (front end surface 1a) opposite to the substrate 20 side of a specific first electrode 1 among the plurality of first electrodes 1, and further formed on the opposing surface OS where the adjacent first electrodes 1 face each other through the gap GP.

[0027] The second electrode forming step shown in FIG. 2D forms the second electrode 3 on the surface 2a opposite to the first electrode 1 side of the insulating portion 2 by sputtering.

[0028] The second resist step shown in FIG. 2E forms the second resist 31 with a specific pattern on a part of the second electrode 3 by photolithography. Specifically, the second resist 31 is formed so as to cover a partial region of the second electrode 3 on a specific first electrode 1 located at the leftmost among the plurality of first electrodes 1.

[0029] The removing step shown in FIG. 2F etches a part of the insulating portion 2 and the second electrode 3 using the second resist 31. At this time, among the second electrode 3 and the insulating portion 2 formed in the gap GP, the portion facing the substrate 20 (see FIG. 2E) is removed. As a result, a part of the substrate 20 is exposed in the gap GP. That is, the second electrodes 3 adjacent to each other in the specific direction D are insulated from each other without being electrically connected.

[0030] Also, the removing step shown in FIG. 2F exposes a part of the tip of the first electrode 1 by etching a part of the insulating portion 2 and the second electrode 3.

[0031] After removing the second resist 31 in the removing step shown in FIG. 2G, the Via forming step shown in FIG. 2H is performed. The Via forming step may include an interlayer insulating film step and a forming step.

[0032] The interlayer insulating film step forms the interlayer insulating film 6 so as to cover the gap GP, the first electrode 1, and the second electrode 3.

[0033] The forming process forms a first via 4 that electrically connects the first electrode 1 to the third electrode 7 and a second via 5 that electrically connects the second electrode 3 to the fourth electrode 8 in the interlayer insulating film 6.

[0034] Hereinafter, with reference to FIGS. 3A to 3F, a method for manufacturing a MIM capacitor according to a comparative example will be described. FIGS. 3A to 3F are diagrams for explaining a method for manufacturing a MIM capacitor according to a comparative example.

[0035] The process shown in FIG. 3A forms the first electrode 1 on the substrate 20 by sputtering.

[0036] The process shown in FIG. 3B forms the insulating portion 2 so as to cover the first electrode 1, for example, by CVD (chemical vapor deposition) sputtering. At this time, when the first electrode 1 becomes high temperature (for example, 400° C. or higher) by sputtering, a raised portion called a hillock 1A is generated on its surface. For this reason, a raised portion also occurs in the insulating portion 2 that covers the first electrode 1.

[0037] In the process shown in FIG. 3C with the hillock 1A generated, when the second electrode 3 is formed by sputtering, a raised portion also occurs in the second electrode 3 that covers the insulating portion 2.

[0038] The process shown in FIG. 3D exposes a part of the first electrode 1 by etching the insulating portion 2 and the second electrode 3 using a resist 33. At this time, the hillock 1A remains in the first electrode 1.

[0039] The process shown in FIG. 3E forms a resist 34 with a specific pattern on the portion where the first electrode 1 is exposed by photolithography.

[0040] The process shown in FIG. 3F removes a part of the first electrode 1 by etching the resist 33 and the resist 34, thereby forming a gap GP in the first electrode 1. At this time, since the hillock 1A shown in FIG. 3E obstructs the etching of the first electrode 1, an etching deficiency occurs. Therefore, as shown in FIG. 3F, the electrode 1B remains in a part of the gap GP, and the electrode 1B shorts the adjacent first electrode 1. As a result, the adjacent first electrodes 1 are electrically connected, that is, a short-circuit defect occurs, so that the insulation performance of the completed MIM capacitor can be significantly reduced.

[0041] (Modification example) FIG. 4 is a cross-sectional view of an MIM capacitor 100A according to a modification example. The difference between the MIM capacitor 100A according to the modification example and the MIM capacitor 100 shown in FIG. 1 is that a part of the second electrode 3 shown in FIG. 1 is omitted in the MIM capacitor 100A.

[0042] Specifically, a part of the second electrode 3 may be provided on the insulating portion 2 provided on the remaining portion except a part of the surface (front end surface 1a) on the side opposite to the substrate 20 side of the specific first electrode 1.

[0043] And the second electrode 3 is not provided on the insulating portion 2 provided on the opposing surface OS of the first electrode 1. More specifically, the second electrode 3 is not provided on the surface 2a on the side opposite to the first electrode 1 side of the insulating portion 2 located on the opposing surface OS of each of the first two first electrodes 1 from the left among the plurality of first electrodes 1 shown in FIG. 4. Similarly, the second electrode 3 is not provided on the surface 2a on the side opposite to the first electrode 1 side of the insulating portion 2 located on the opposing surface OS of each of the second and third first electrodes 1 from the left. Also, the second electrode 3 is not provided on the surface 2a on the side opposite to the first electrode 1 side of the insulating portion 2 located on the opposing surface OS of each of the third and fourth first electrodes 1 from the left.

[0044] That is, the second electrode 3, which is the upper layer metal, does not remain on the side surfaces of the adjacent first electrodes 1, and only the insulating portion 2, which is a nitride film, remains.

[0045] And the first electrodes 1 adjacent to the specific direction D are not electrically connected to each other and are insulated by the interlayer insulating film 6 located in the gap GP.

[0046] In a state where the interlayer insulating film 6 is not provided, it can be said that a part of the upper surface 20a of the substrate 20 is exposed in the gap GP. The interlayer insulating film 6 located in the gap GP may be in contact with the upper surface 20a of the substrate 20. Thereby, insulation between the adjacent first electrodes 1 is ensured.

[0047] Next, a method for manufacturing the MIM capacitor 100A will be described with reference to FIGS. 5A to 5I. FIGS. 5A to 5I are diagrams for explaining the method for manufacturing the MIM capacitor 100A.

[0048] The method for manufacturing the MIM capacitor 100A may include the first electrode formation step of FIG. 5A, the first resist step of FIG. 5B, the first etching step of FIG. 5C, the insulating portion formation step of FIG. 5D, the second electrode formation step of FIG. 5D, the second resist step of FIG. 5E, three removal steps from FIGS. 5F to 5H, and the Via formation step of FIG. 5I. Since the steps shown in FIGS. 5A to 5E are the same as the steps shown in FIGS. 2A to 2E, the description of these steps will be omitted below, and the steps after FIG. 5F will be described.

[0049] The removal step shown in FIG. 5F etches a part of the second electrode 3 using the second resist 31. At this time, the second electrode 3 formed in the gap GP and the second electrode 3 located at the tip of the first electrode 1 are etched. Specifically, using the insulating portion 2, which is an insulating film, as a stopper, the second electrode 3, which is the upper layer metal covering the insulating portion 2, is wet-etched. As a result, the second electrode 3 does not remain on the side surface of the first electrode 1, so that the insulating portion 2 formed in the gap GP and the insulating portion 2 located at the tip of the first electrode 1 are exposed. That is, the second electrode 3 no longer exists between the first electrodes 1 adjacent to the specific direction D, and the first electrodes 1 adjacent to the specific direction D are in an insulated state.

[0050] In the Via process described below, before the interlayer insulating film 6 (e.g., SiO), which is an insulating film, is formed, the second electrode 3 formed in the gap GP is etched, so that the remaining lower-layer metal due to the influence of the hillock 1A (see FIG. 3B, etc.), that is, a part of the first electrode 1 remaining in the gap GP can be suppressed, and the occurrence of a short circuit defect due to the remaining lower-layer metal can be suppressed.

[0051] The removal process shown in FIG. 5G removes a part of the insulating portion 2 formed in the gap GP and the insulating portion 2 formed at the tip of the first electrode 1. Specifically, among the insulating portions 2 formed in the gap GP, the portion facing the substrate 20 (see FIG. 5F) and the insulating portion 2 formed at the tip of the first electrode 1 are dry-etched, for example. As a result, a part of the substrate 20 is exposed in the gap GP. That is, the first electrodes 1 adjacent in the specific direction D are insulated from each other without being electrically connected.

[0052] In CM (chemical) etching, by performing the wet etching in the process shown in FIG. 5F and the dry etching shown in FIG. 5G, a structure is obtained in which the second electrode 3, which is the upper-layer metal, does not remain on the side walls of the lower-layer metal, that is, on the respective side surfaces of the adjacent first electrodes 1, and only the insulating portion 2, which is a nitride film, remains.

[0053] Since the nitride film remains on the side walls of the lower-layer metal, an increase in fringe capacitance (capacitance between metals in the same layer) can be expected. Also, since there is no upper-layer metal between the adjacent lower-layer metals, the embedding property of the interlayer insulating film 6 can be improved in the process shown in FIG. 5I described later. That is, since the width of the gap GP formed between the adjacent first electrodes 1, which are the lower-layer metals, relatively increases, the interlayer insulating film 6 can be easily embedded in the gap GP.

[0054] After removing the second resist 31 in the removal process shown in FIG. 5H, the Via formation process shown in FIG. 5I is performed. The Via formation process may include an interlayer insulating film process and a formation process.

[0055] The interlayer insulating film process forms the interlayer insulating film 6 so as to cover the gap GP, the first electrode 1, and the insulating portion 2.

[0056] In the forming process, a first via 4 for electrically connecting the first electrode 1 to the third electrode 7 and a second via 5 for electrically connecting the second electrode 3 to the fourth electrode 8 are formed in the interlayer insulating film 6.

[0057] (Function and effect) In the MIM capacitors 100 and 100A according to the embodiments of the present disclosure, by the above-described respective processes, in the second electrode 3 and the insulating portion 2 formed in the gap GP, the portion facing the substrate 20 (see FIG. 2E) is removed. For this reason, a part of the substrate 20 is exposed in the gap GP. That is, since the first electrodes 1 adjacent in the specific direction D are not electrically connected to each other and are in an insulated state, a short circuit failure of the adjacent first electrodes 1 does not occur, and thus the insulation performance of the completed MIM capacitor 100 is significantly improved.

[0058] In addition, the following supplementary notes are disclosed regarding the above description.

[0059] (Supplementary Note 1) A plurality of first electrodes provided on a substrate, separated from each other in a specific direction, a plurality of insulating portions provided on opposing surfaces where adjacent ones of the plurality of first electrodes face each other, and a MIM capacitor in which a part of the substrate is exposed in a gap between adjacent ones of the plurality of first electrodes.

[0060] (Supplementary Note 2) further comprising a plurality of second electrodes provided on surfaces on the opposite sides of the respective insulating portions from the first electrode sides, separated from each other in the specific direction, The MIM capacitor according to Supplementary Note 1, in which a part of the substrate is exposed from a gap between adjacent ones of the plurality of second electrodes.

[0061] (Supplementary Note 3) A first via having a first end connected to a part of a surface on the side opposite to the substrate side of a specific first electrode among the plurality of first electrodes and a second end opposite to the first end connected to a third electrode, The third terminal is connected to an electrode on an insulating portion provided on the remaining part of the surface of the specific first electrode opposite to the substrate side, and a fourth terminal opposite to the third terminal is a second via connected to a fourth electrode, The MIM capacitor according to claim 1 or 2, comprising

[0062] (Appendix 4) A first electrode forming step of forming a first electrode on a substrate, A first resist step of forming a first resist with a specific pattern on the surface of the first electrode opposite to the substrate side, A first etching step of forming a plurality of gaps in the first electrode by etching the first electrode using the first resist, and dividing the first electrode into a plurality of first electrodes provided on the substrate apart from each other in a specific direction, An insulating portion forming step of forming an insulating portion on the opposing surface where the adjacent first electrodes face each other through the gap, A second electrode forming step of forming a second electrode on the surface of the insulating portion opposite to the first electrode side, A second resist step of forming a second resist with a specific pattern on the second electrode, A removing step of removing, by etching the second electrode and the insulating portion using the second resist, a portion of the second electrode and the insulating portion formed in the gap that faces the substrate, and exposing a part of the substrate in the gap, A method for manufacturing an MIM capacitor, including

[0063] (Appendix 5) A first electrode forming step of forming a first electrode on a substrate, A first resist step of forming a first resist with a specific pattern on the surface of the first electrode opposite to the substrate side, A first etching step of forming a plurality of gaps in the first electrode by etching the first electrode using the first resist, and dividing the first electrode into a plurality of first electrodes provided on the substrate apart from each other in a specific direction, An insulating portion forming step of forming an insulating portion on a facing surface where the first electrodes adjacent through the gap face each other; A second electrode forming step of forming a second electrode on a surface of the insulating portion opposite to the first electrode side; A second resist step of forming a second resist of a specific pattern on the second electrode; A step of removing the second electrode formed in the gap by etching the second electrode using the second resist; A step of exposing a part of the substrate from the gap by etching a part of the insulating portion formed in the gap; A method for manufacturing a MIM capacitor, including:

[0064] (Appendix 6) An interlayer insulating film step of forming an interlayer insulating film so as to cover the gap, the first electrode, and the second electrode; A first Via having a first end connected to a part of a surface of a specific first electrode opposite to the substrate side among the plurality of first electrodes, and a second end opposite to the first end connected to a third electrode; A forming step of forming a second Via in the interlayer insulating film, wherein a third end is connected to an electrode on an insulating portion provided on a remaining part of the surface of the specific first electrode excluding a part opposite to the substrate side, and a fourth end opposite to the third end is connected to a fourth electrode; The MIM capacitor according to Appendix 4 or 5, further including:

Explanation of symbols

[0065] 1 First electrode 1A Hillock 1B Electrode 1a Front end face 2 Insulating portion 2a Surface 3 Second electrode 4 First Via 5 Second Via 6 Interlayer insulating film 7 Third electrode 8 Fourth electrode 20 Substrate 20a Upper surface 30 Resist 31 Resist 33 Resist 34 Resist 41 End 42 End 53 End 54 End 100 MIM Capacitor 100A MIM Capacitor D Specific Direction GP Gap OS Opposite Surface

Claims

1. A plurality of first electrodes provided on a substrate, spaced apart from each other in a specific direction, A plurality of insulating portions provided on a facing surface where adjacent ones of the plurality of first electrodes face each other, Comprising, A MIM (Metal Insulator Metal) capacitor in which a part of the substrate is exposed from a gap between adjacent ones of the plurality of first electrodes.

2. Further comprising a plurality of second electrodes provided on surfaces of the plurality of insulating portions on sides opposite to the first electrode sides respectively, spaced apart from each other in the specific direction, The MIM capacitor according to claim 1, wherein a part of the substrate is exposed from a gap between adjacent ones of the plurality of second electrodes.

3. A first Via having a first end connected to a part of a surface of a specific first electrode among the plurality of first electrodes, on a side opposite to the substrate side, and a second end opposite to the first end connected to a third electrode, A second Via having a third end connected to an electrode on an insulating portion provided on a remaining part of the surface of the specific first electrode, excluding a part on a side opposite to the substrate side, and a fourth end opposite to the third end connected to a fourth electrode, The MIM capacitor according to claim 1, comprising.

4. A first electrode forming step of forming a first electrode on a substrate, A first resist step of forming a first resist with a specific pattern on a surface of the first electrode on a side opposite to the substrate side, A first etching step of forming a plurality of gaps in the first electrode by etching the first electrode using the first resist, and dividing the first electrode into a plurality of first electrodes provided on the substrate, spaced apart from each other in a specific direction, An insulating portion forming step of forming an insulating portion on a facing surface where adjacent ones of the first electrodes face each other through the gaps, A second electrode forming step of forming a second electrode on a surface of the insulating portion on a side opposite to the first electrode side, A second resist step of forming a second resist with a specific pattern on the second electrode, A removing step of removing a portion of the second electrode and the insulating portion formed in the gap, which faces the substrate, by etching the second electrode and the insulating portion using the second resist, and exposing a part of the substrate from the gap, A method for manufacturing a MIM capacitor, including.

5. A first electrode forming step of forming a first electrode on a substrate, A first resist step of forming a first resist with a specific pattern on a surface of the first electrode on a side opposite to the substrate side, A first etching step of forming a plurality of gaps in the first electrode by etching the first electrode using the first resist, and dividing the first electrode into a plurality of first electrodes provided on the substrate while being separated from each other in a specific direction; An insulating portion forming step of forming an insulating portion on a facing surface where the adjacent first electrodes face each other through the gap; A second electrode forming step of forming a second electrode on a surface of the insulating portion opposite to the first electrode side; A second resist step of forming a second resist with a specific pattern on the second electrode; A step of removing the second electrode formed in the gap by etching the second electrode using the second resist; A step of exposing a part of the substrate from the gap by etching a part of the insulating portion formed in the gap; A method for manufacturing a MIM capacitor, comprising:

6. An interlayer insulating film step of forming an interlayer insulating film so as to cover the gap, the first electrode, and the second electrode; A first Via having a first end connected to a part of a surface of a specific first electrode among the plurality of first electrodes, which is opposite to the substrate side, and a second end opposite to the first end connected to a third electrode; A forming step of forming a second Via in the interlayer insulating film, wherein a third end is connected to an electrode on an insulating portion provided on a remaining portion of a surface of the specific first electrode excluding a part opposite to the substrate side, and a fourth end opposite to the third end is connected to a fourth electrode; The method for manufacturing a MIM capacitor according to claim 4 or 5, further comprising:

Images