Semiconductor device

Abstract

To improve the field effect mobility and improve the reliability in a transistor including an oxide semiconductor film.SOLUTION: A transistor includes an oxide semiconductor film. The transistor includes a region where the maximum value of the field effect mobility in the range in which the gate voltage of the transistor is more than 0 V and 10 V or less is 40 cm2 / Vs or more and less than 150 cm2 / Vs, a region where the threshold voltage is -1 V or more and 1 V or less, a region where the S value is less than 0.3 V / decade, and a region where the off current is less than 1×10-12 A / cm2. When the maximum value of the field effect mobility of the transistor is represented as μFE(max) and the value of the field effect mobility at which the gate voltage of the transistor is 2 V is represented as μFE(Vg=2 V), μFE(max) / μFE(Vg=2 V) is 1 or more and less than 1.5.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device having an oxide semiconductor film and a display device having the semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one aspect of the present invention relates to an oxide semiconductor or a method for manufacturing the oxide semiconductor. Or, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor devices include semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including thin-film solar cells, organic thin-film solar cells, etc.), and an electronic device may have a semiconductor device.

Background Art

[0004] Techniques for constructing a transistor (also referred to as a field-effect transistor (FET) or a thin-film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). As a semiconductor thin film applicable to a transistor, silicon ​​​​​​​​​​​​​Semiconductor materials typified by [material name] are widely known, but oxide semiconductors are attracting attention as other materials. For example, a technique for manufacturing a transistor using an In-Ga-Zn-based oxide semiconductor has been disclosed (see Patent Document 1).

[0005] In addition, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer serving as a channel contains indium and gallium, and the ratio of indium is made larger than the ratio of gallium, thereby increasing the field-effect mobility (sometimes simply referred to as mobility or μFE). A semiconductor device has been disclosed (see Patent Document 1).

[0006] In addition, in Non-Patent Document 1, it is described that a homologous phase represented by In 1-x Ga 1+x O3(ZnO) m (where x is a number satisfying -1 ≤ x ≤ 1, and m is a natural number) exists. In addition, Non-Patent Document 1 describes the solid solution range of the homologous phase. For example, it is described that the solid solution range of the homologous phase when m = 1 is that x is in the range of -0.33 to 0.08, and the solid solution range of the homologous phase when m = 2 is that x is in the range of -0.68 to 0.32.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0008] ​​​​​​​​

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] As for a transistor using an oxide semiconductor film in a channel region, it is preferable that the field-effect mobility is high. However, when the field-effect mobility of the transistor is increased, there is a problem that the characteristics of the transistor tend to be normal-on characteristics. Note that normal-on means a state in which a channel exists even without applying a voltage to the gate electrode, and a current flows through the transistor. Moreover, in a transistor using an oxide semiconductor film in a channel region, oxygen deficiency formed in the oxide semiconductor film becomes a problem because it affects the transistor characteristics. For example, when oxygen deficiency is formed in the oxide semiconductor film, hydrogen binds to the oxygen deficiency and becomes a carrier supply source. When a carrier supply source is generated in the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film, typically a shift in the threshold voltage, occur. For example, if there is too much oxygen deficiency in the oxide semiconductor film, the threshold voltage of the transistor shifts to the negative side and becomes normal-on characteristics. Therefore, in the oxide semiconductor film, especially in the channel region, there is little oxygen deficiency or it does not become normal-on characteristics. For example, when oxygen deficiency is formed in the oxide semiconductor film, hydrogen binds to the oxygen deficiency and becomes a carrier supply source. When a carrier supply source is generated in the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film, typically a shift in the threshold voltage, occur. Note that normal-on means a state in which a channel exists even without applying a voltage to the gate electrode, and a current flows through the transistor.

[0010] Moreover, in a transistor using an oxide semiconductor film in a channel region, oxygen deficiency formed in the oxide semiconductor film becomes a problem because it affects the transistor characteristics. For example, when oxygen deficiency is formed in the oxide semiconductor film, hydrogen binds to the oxygen deficiency and becomes a carrier supply source. When a carrier supply source is generated in the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film, typically a shift in the threshold voltage, occur. When a carrier supply source is generated in the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film, typically a shift in the threshold voltage, occur. When a carrier supply source is generated in the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film, typically a shift in the threshold voltage, occur.

[0011] For example, if there is too much oxygen deficiency in the oxide semiconductor film, the threshold voltage of the transistor shifts to the negative side and becomes normal-on characteristics. Therefore, in the oxide semiconductor film, especially in the channel region, there is little oxygen deficiency or it does not become normal-on characteristics. Therefore, in the oxide semiconductor film, especially in the channel region, there is little oxygen deficiency or it does not become normal-on characteristics. It is preferably an oxygen deficiency amount that is not such.

[0012] Also, in Non-Patent Document 1, In x Zn y Ga z O w is shown as an example, and x, y, and z are compositions near ZnGa2O4, that is, when x, y, and z have values close to (x, y, z) = (0, 1, 2), it is described that a spinel-type crystal structure is likely to be formed or mixed. Compounds represented by AB2O4 (A and B are metals) are known as compounds having a spinel-type crystal structure. However, when a spinel-type crystal structure is formed or mixed in an In-Ga-Zn-based oxide semiconductor, it may have an adverse effect on the electrical characteristics or reliability of a semiconductor device (for example, a transistor) having the In-Ga-Zn-based oxide semiconductor.

[0013] In view of the above problems, one aspect of the present invention is, in a transistor having an oxide semiconductor film, to improve the field-effect mobility and improve the reliability as one of the problems. Or

[0014] In view of the above problems, one aspect of the present invention is, in a transistor having an oxide semiconductor film, to suppress fluctuations in electrical characteristics and improve the reliability as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with reduced power consumption as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or is to provide a novel oxide semiconductor as one of the problems. Or, One aspect of the disclosure aims to provide a novel display device as one of the problems.

[0015] Note that the description of the above problems does not prevent the existence of other problems. One aspect of the present invention does not necessarily need to solve all of these problems. Other problems will be apparent from the description in the specification and the like, and it is possible to extract other problems from the description in the specification and the like.

Means for Solving the Problems

[0016] One aspect of the present invention is a semiconductor device having a transistor, the transistor including an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film, the first conductive film having a region in contact with the oxide semiconductor film, the second conductive film having a region in contact with the oxide semiconductor film, the third conductive film having a region where the oxide semiconductor film and the third conductive film overlap each other with an insulating film therebetween, the transistor 2 having a region where the maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0 V and less than or equal to 10 V is 40 cm 2 / Vs or more and less than 150 cm 2 / Vs, a region where the threshold voltage is -1 V or more and 1 V or less, a region where the S -12 value is less than 0.3 V / decade, and a region where the off-current is less than 1×10 A / cm 2 When the maximum value of the field-effect mobility of the transistor is represented as μFE(max ) and the value of the field-effect mobility when the gate voltage of the transistor is 2 V is represented as μFE(Vg = 2 V), the semiconductor device is such that μFE(max) / μFE(Vg = 2 V) is 1 or more and less than 1.5.

[0017] Another aspect of the present invention is a semiconductor device having a transistor, where the transist or has a first gate electrode, a first insulating film on the first gate electrode, an acid ide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate elec trode on the second insulating film, a third insulating film on the oxide semiconductor film and the second gate electrode, the oxide semi conductor film has a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film, the first gate electrode and the second gate electrode are electrically connected, the transistor has a maximum value of the field-effect mobility in a range where the gate voltage of the transistor is greater than 0 V and less than or equal to 10 V of 40 cm / Vs or more and less than 150 cm / Vs, a region where the threshold voltage is -1 V or more and 1 V or less, a region where the S value is less than 0.3 V / decade, and a region where the off-current is less than 1×10 2 A / cm 2 , representing the maximum value of the field-effect mobility of the transistor as μFE(max), and when representing the value of the field-effect mobility when the gate voltage of the transistor is 2 V as μFE(Vg = 2V), μFE(max) / μFE(Vg = 2V) is 1 or more and less than 1.5, the semiconductor device. -12 A / cm 2 The region is less than, and has a region, and represents the maximum value of the field-effect mobility of the transistor as μFE(max), and when representing the value of the field-effect mobility when the gate voltage of the transistor is 2 V as μFE(Vg = 2V), μFE(max) / μFE(Vg = 2V) is 1 or more and less than 1.5, the semiconductor device. device. device.

[0018] In the above aspect, it is preferable that the oxide semiconductor film has a region where the density of shallow defect energy levels is less than 1.0×10 -12 cm -2 .

[0019] Another aspect of the present invention is a semiconductor device having a transistor, where the transist The transistor has an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film. , and the first conductive film has a region in contact with the oxide semiconductor film, and the second conductive film has a region in contact with the oxide semiconductor film. The third conductive film has a region where the oxide semiconductor film and the third conductive film overlap each other with the insulating film interposed therebetween. The transistor has a maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0 V and less than or equal to 10 V of 40 cm 2 / Vs or more and less than 150 cm 2 / Vs, a threshold voltage in the range of -1 V or more and 1 V or less, an S value of less than 0.3 V / decade, and an off-current of less than 1×10 -1 2 A / cm 2 The semiconductor device has a region where the maximum value of the field-effect mobility of the transistor is represented as μF E(max), and when the value of the field-effect mobility when the gate voltage of the transistor is 2 V is represented as μF E(Vg = 2V), μFE(max) / μFE(Vg = 2V) is 1.5 or more and less than 3.

[0020] Another aspect of the present invention is a semiconductor device having a transistor, where the transistor has a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film has a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode have a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode ​electrically connected, the transistor has a gate voltage of the transistor greater than 0V and less than 10V The maximum value of the field-effect mobility in the following range is 40 cm 2 / Vs or more and 150 cm 2 / Vs less than full region, the threshold voltage is in the range of -1V or more and 1V or less, and the S value is 0.3V / decade or less, and the off-current is 1×10 -12 A / cm 2 less than the region region, and represents the maximum value of the field-effect mobility of the transistor as μFE(max), When the value of the field-effect mobility at a gate voltage of 2V of the transistor is represented as μFE(Vg = 2V) When expressed, μFE(max) / μFE(Vg = 2V) is 1.5 or more and less than 3, a semiconductor device.

[0021] In the above aspect, the oxide semiconductor film has a shallow defect level density of 1.0×10 -12 cm -2 or more and 2.0×10 -12 cm -2 less than the region is preferably provided.

[0022] Another aspect of the present invention is a semiconductor device having a transistor, the transistor has an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film , the first conductive film has a region in contact with the oxide semiconductor film, and the second conductive film has an oxide a region in contact with the semiconductor film, and the third conductive film has a region where the oxide semiconductor film and the third conductive film overlap each other with an insulating film interposed therebetween, and the transistor has a gate voltage of the transistor The maximum value of the field-effect mobility in the range greater than 0V and less than or equal to 10V is 10 cm 2 / Vs or more and 100 cm 2a region less than / Vs, a threshold voltage of -1V or more and 1V or less a region, an S value of less than 0.3V / decade, an off-current of 1×10 -1 2 A / cm 2 a region less than, and has a maximum value of the field-effect mobility of the transistor represented as μF E(max), and when the value of the field-effect mobility at a gate voltage of 2V of the transistor is represented as μF E(Vg=2V), μFE(max) / μFE(Vg=2V) is 3 or more and less than 10, which is a semiconductor device.

[0023] Another aspect of the present invention is a semiconductor device having a transistor, and the transistor has a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film has a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected. The transistor has a maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0V and less than or equal to 10V of 10 cm / Vs or more and 100 cm / Vs less than a region, a threshold voltage of -1V or more and 1V or less, an S value of less than 0.3V / decade, an off-current of 1×10 A / cm less than, and has a maximum value of the field-effect mobility of the transistor represented as μFE(max) 2 / Vs or more and 100 cm 2 / Vs less a region, a threshold voltage of -1V or more and 1V or less, an S value of less than 0.3V / decade, an off-current of 1×10 -12 A / cm 2 less than the region and has, and represents the maximum value of the field-effect mobility of the transistor as μFE(max) The value of the field-effect mobility when the gate voltage of the transistor is 2V is expressed as μFE(Vg = 2V). When μFE(max) / μFE(Vg = 2V) is 3 or more and less than 10, it is a semiconductor device.

[0024] In the above aspect, the oxide semiconductor film preferably has a region where the density of shallow defect energy levels is 2.0×10 -12 cm -2 or more and less than 3.0×10 -12 cm -2 .

[0025] Also, in the above aspect, the oxide semiconductor film has a composite oxide semiconductor in which a first region and a second region are mixed. The first region has a plurality of first clusters mainly composed of any one or more selected from indium, zinc, and oxygen. The second region has a plurality of second clusters mainly composed of any one or more selected from indium, element M (M is Al, Ga, Y, or Sn), zinc, and oxygen. The first region preferably has a portion where the plurality of first clusters are connected to each other, and the second region preferably has a portion where the plurality of second clusters are connected to each other.

[0026] Also, in the above aspect, the atomic ratio of indium, element M, and zinc is preferably in the vicinity of In:M:Zn = 4:2:3. When In is 4, element M is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less. Or, in the above aspect, the atomic ratio of indium, element M, and zinc is preferably in the vicinity of In:M:Zn = 5:1:6. When In is 5, element M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less.

[0027] ​​​​​​​​​​​Also, in the above aspect, the first cluster has electrical conductivity, and the second cluster preferably has electrical semiconductor properties.

[0028] Also, in the above aspect, the first cluster preferably has a portion that is 0.5 nm or more and 1.5 nm or less.

[0029] Another aspect of the present invention is a display device having the semiconductor device and a display element described in any one of the above aspects. Another aspect of the present invention is a display module having the display device and a touch sensor. Another aspect of the present invention is an electronic device having the semiconductor device, the display device, or the display module described in any one of the above aspects, and an operation key or a battery. Another aspect of the present invention is an electronic device having the semiconductor device described in any one of the above aspects, an inverter, or a converter.

Advantages of the Invention

[0030] According to one aspect of the present invention, in a transistor having an oxide semiconductor film, the field-effect mobility can be improved and the reliability can be improved. Or, according to one aspect of the present invention, in a transistor having an oxide semiconductor film, the variation in electrical characteristics can be suppressed and the reliability can be improved. Or, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Or, according to one aspect of the present invention, good electrical characteristics can be imparted to a semiconductor device. Or, according to one aspect of the present invention, a novel oxide semiconductor can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided. ​​​​​​​​​​​​​It is possible. Or, according to one aspect of the present invention, a novel display device can be provided. It is.

[0031] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc. will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of Drawings

[0032]

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[0033] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. It should not be construed as being limited to the description of the following embodiments.

[0034] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic illustrations of ideal examples and are not limited to the shapes or values shown in the drawings.

[0035] Also, the ordinal numbers "first", "second", "third", etc. used in this specification are attached to avoid confusion of components, and it should be noted that they are not numerically limiting.

[0036] In this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0037] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel region. In this specification and the like, the channel region refers to the region through which current mainly flows.

[0038] Also, the functions of the source and the drain may vary depending on the type of transistor with different polarities or in a circuit ​​​​​​​​​​In cases where the direction of the current changes during operation, etc., it may be reversed. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0039] Also, in this specification and the like, "electrically connected" includes cases where connection is made through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0040] Also, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included.

[0041] Also, in this specification and the like, the term "film" and the term "layer" are interchangeable. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0042] Also, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as a non-conductive state or a cut-off state). The off state and​​​​​​​​​ In the case of an n-channel transistor, unless otherwise specified, the voltage V between the gate and the source, Vgs, is lower than the threshold voltage Vth. In the case of a p-channel transistor, the voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth. The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, the off-state at Vgs within a predetermined range, or the off-state at Vgs where a sufficiently reduced off-current is obtained, etc.

[0043] The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, the off-state at Vgs within a predetermined range, or the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, the off-state at Vgs within a predetermined range, or the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, the off-state at Vgs within a predetermined range, or the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, the off-state at Vgs within a predetermined range, or the off-state at Vgs where a sufficiently reduced off-current is obtained, etc. The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, the off-state at Vgs within a predetermined range, or the off-state at Vgs where a sufficiently reduced off-current is obtained, etc.

[0044] As an example, assume an n-channel transistor with a threshold voltage Vth of 0.5 V, a drain current of 1×10 A at Vgs = 0.5 V, a drain current of 1×10 -9 A at Vgs = 0.1 V, a drain current of 1×10 -1 3 A at Vgs = -0.5 V, and a drain current of 1×10 -19 A at Vgs = -0.8 V. Since the drain current of this transistor is 1×10 A or less at Vgs = -0.5 V or in the range of Vgs from -0.5 V to -0.8 V, it may be said that the off-current of this transistor is 1×10 -22 A or less. The drain current of this transistor is 1×10 A or less at Vgs = -0.5 V or in the range of Vgs from -0.5 V to -0.8 V. Therefore, it may be said that the off-current of this transistor is 1×10 -19 A or less. A or less. -19 A or less.​ exists. There is a Vgs at which the drain current of the transistor becomes 1×10 -22 A or less, so the off-current of the transistor may be said to be 1×10 A or less. -22

[0045] Also, in this specification and the like, the off-current of a transistor having a channel width W may be represented by the current value flowing per channel width W. Also, it may be represented by the current value flowing per a predetermined channel width (for example, 1 μm). In the latter case, the unit of the off-current may be represented by a unit having a unit of current / length (for example, A / μm).

[0046] The off-current of a transistor may depend on temperature. In this specification, unless otherwise specified, the off-current may represent the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, the temperature at which the reliability of the semiconductor device or the like including the transistor is guaranteed, or the temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature from 5 °C to 35 °C), may represent the off-current. That the off-current of a transistor is I or less means that there exists a value of Vgs at which the off-current of the transistor becomes I or less at room temperature, 60 °C, 85 °C, 95 °C, 125 °C, the temperature at which the reliability of the semiconductor device or the like including the transistor is guaranteed, or the temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature from 5 °C to 35 °C). [[ID=3২]]

[0047] The off-current of a transistor may depend on the voltage Vds between the drain and the source. . In this specification, unless otherwise specified, the off-current refers to the off-current at Vds = 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or it may represent the off-current at 20V. Or, it may represent the off-current at Vds where the reliability of the semiconductor device containing the transistor is guaranteed, or the off-current at Vds used in the semiconductor device containing the transistor. When it is stated that the off-current of the transistor is I or less, it may mean that there exists a value of Vgs such that the off-current of the transistor at Vds = 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds where the reliability of the semiconductor device containing the transistor is guaranteed, or the Vds used in the semiconductor device containing the transistor, is I or less. In the description of the off-current above, the drain and source may be read as swapped. That is, the off-current may also refer to the current flowing through the source when the transistor is in the off state.

[0048] In the above description of the off-current, the drain and source may be read as swapped. That is, the off-current may also refer to the current flowing through the source when the transistor is in the off state. That is, the off-current may also refer to the current flowing through the source when the transistor is in the off state.

[0049] Also, in this specification etc., the leakage current may be described with the same meaning as the off-current. Further, in this specification etc., the off-current may, for example, refer to the current flowing between the source and the drain when the transistor is in the off state.

[0050] Also, in this specification etc., the threshold voltage of the transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of the transistor is such that, with the gate voltage (Vg) on the horizontal axis and the square root of the drain current (Id) on the vertical axis, a plot is made. In the drawn curve (Vg-√Id characteristic), the gate voltage (Vg ) at the intersection with the straight line obtained by extrapolating the tangent line with the maximum slope and the square root of the drain current (Id) being 0 (Id being 0 A) may be referred to. Alternatively, the threshold voltage of a transistor is the gate voltage (Vg) when the channel length is L, the channel width is W, and the value of Id [A] × L [μm] / W [μm] becomes 1 × 10 -9 [A].

[0051] Also, in this specification and the like, even when referred to as "semiconductor", for example, when the conductivity is sufficiently low, it may have the characteristics of an "insulator". Also, the boundary between "semiconductor" and " insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification and the like may be convertible to "insulator". Similarly, the "insulator" described in this specification and the like may be convertible to "semiconductor". Also the "insulator" described in this specification and the like may be convertible to "semi-insulator".

[0052] Also, in this specification and the like, even when referred to as "semiconductor", for example, when the conductivity is sufficiently high, it may have the characteristics of a "conductor". Also, the boundary between "semiconductor" and " conductor" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification and the like may be convertible to "conductor". Similarly, the "conductor" described in this specification and the like may be convertible to "semiconductor".

[0053] Also, in this specification and the like, the impurities of a semiconductor refer to components other than the main components constituting the semiconductor. ​​For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of impurities may cause the formation of DOS (Density of States) in the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, etc. When the semiconductor has an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, there are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, for example, the mixing of impurities such as hydrogen may form oxygen vacancies. When the semiconductor has silicon, examples of impurities that change the characteristics of the semiconductor include

[0054] (Embodiment 1) In this embodiment, a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 1 to 35.

[0055] One aspect of the present invention is a semiconductor device having a transistor, the transistor including a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film has a channel region overlapping the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first

[0056] Further, in the transistor, the maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0 V and equal to or less than 10 V is 40 cm 2 / Vs or more and less than 150 cm 2 / Vs. It has a first region, a second region where the threshold voltage is -1 V or more and 1 V or less, a third region where the S value is less than 0 .3 V / decade, and a fourth region where the off-current is less than 1×10 -12 A / cm 2 When the maximum value of the field-effect mobility of the transistor is represented as μFE(max), and the value of the field-effect mobility when the gate voltage of the transistor is 2 V is represented as μFE(V g = 2 V), μFE(max) / μFE(Vg = 2 V) is 1 or more and less than 1.5 . Also, the transistor is not limited to this, and μFE(max) / μFE(Vg = 2 V

[0057] ) may be 1.5 or more and less than 3. In other words, the semiconductor device according to one aspect of the present invention is a transistor having an oxide semiconductor film in the channel region, and the field-effect mobility, threshold voltage

[0058] of the transistor, the off-current, and the S value are very excellent transistors. Such a semiconductor device can be suitably used for, for example, a transistor of a pixel of an organic EL display or a transistor of a driving circuit of an organic EL display. Further, the transistor is not limited to this, and the maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0 V and less than or equal to 10 V is 10 cm / Vs or more and 100 cm / Vs or less.

[0059] 2 / Vs or more and less than 100 cm 2A first region where it is less than / Vs, a second region where the threshold voltage is not less than -1V and not more than 1V, a third region where the S value is less than 0.3V / decade, and an off current is 1×10 A fourth region that is less than A / cm -12 A / cm 2 It has, and when the maximum value of the field-effect mobility of the transistor is represented as μFE(max) and the value of the field-effect mobility when the gate voltage of the transistor is 2V is represented as μFE(Vg = 2V), μFE(max) / μFE(Vg = 2V ) may be not less than 3 and less than 10. In other words, the semiconductor device according to one aspect of the present invention is a transistor having an oxide semiconductor film in a channel region, and the transistor has high heat resistance and physical Since the characteristics are stable, it is a highly reliable transistor. Such a semiconductor device can be suitably used as a power device. For example, it can be suitably used as a semiconductor device used in a power converter such as an inverter or a converter. Also, for example,

[0060] It can be used for inverter control of electric vehicles, hybrid vehicles, air conditioners, etc., and various general-purpose motors. In the present embodiment, an oxide semiconductor which is one aspect of the present invention will be described.

[0061]

[0062] <1-1. Oxide Semiconductor Film> First, the oxide semiconductor film that can be used for the transistor according to one aspect of the present invention will be described with reference to FIGS. 4 to 13.

[0062] The oxide semiconductor film preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to those, aluminum, gallium, yttrium ​​It is preferable that it contains lithium or tin, etc. Further, boron, silicon, titanium , iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neo dymium, hafnium, tantalum, tungsten, or magnesium, etc., and one kind selected therefrom, or a plurality of kinds may be contained.

[0063] Here, consider the case where the oxide semiconductor film has indium, element M, and zinc. Note that , element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, silicon, titanium, iron, nickel, germani um, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantal um, tungsten, magnesium, etc. However, as element M, a plurality of the aforementioned elements may be combined. Note that the respective terms of the atomic ratios of indium, element M, and zinc contained in the oxide semiconductor film are denoted as [In], [M], and [Zn].

[0064] <1-2. Structure of Oxide Semiconductor Film> A conceptual diagram of the oxide semiconductor film in one aspect of the present invention is shown in FIG. 4.

[0065] FIG. 4(A) is a conceptual diagram of the upper surface of the oxide semiconductor film (here, referred to as the a-b plane direction), and FIG. 4(B) is a conceptual diagram of a cross section (here, referred to as the c-axis direction) in which the oxide semiconductor film is formed on the substrate Sub. [[ID=3⑧]]

[0066] Note that in FIG. 4, the case where the oxide semiconductor film is formed on the substrate is illustrated, but it is not limited thereto, and an insulating film such as an underlayer film or an interlayer film, or another semiconductor film such as an oxide semiconductor film may be formed between the substrate and the oxide semiconductor film.

[0067] As shown in FIGS. 4A and 4B, the oxide semiconductor film of one embodiment of the present invention has a region A1 and region B1 are mixed to form a composite oxide semiconductor. In the following description, the oxide semiconductor film may be referred to as a composite oxide semiconductor. .

[0068] The region A1 shown in FIG. 4(A)(B) is [In]:[M]:[Zn]=x:y:z (x> 0, y ≥ 0, z ≥ 0). On the other hand, region B1 is a region where [In]:[M This is the region where there is little In such that ]:[Zn]=a:b:c (a>0, b>0, c>0).

[0069] In this specification, the atomic ratio of In to element M in region A1 is The atomic ratio of In to M in region A1 is larger than that in region B1. Therefore, in this specification, the region A1 is referred to as an in-rich region. The area B1 is also called an in-poor area.

[0070] For example, the concentration of In in the region A1 is 1.1 times or more, preferably 2 times or more, than that in the region B1. The region A1 is preferably an oxide containing at least In. However, the elements M and Zn do not necessarily have to be included.

[0071] Here, the atomic ratio of elements contained in the complex oxide semiconductor of one embodiment of the present invention will be described. .

[0072] In the composite oxide semiconductor, for example, the region A1 has In, the element M, and Zn. In this case, the atomic ratio of each element can be shown using the phase diagram shown in Figure 8. The atomic number ratios of In, M, and Zn are represented as x:y:z using x, y, and z. Here, the atomic number ratios can be represented in the figure as coordinates (x:y:z). Note that Fig. 8 does not show the atomic number ratio of oxygen.

[0073] In Fig. 8, the dashed lines represent the lines with the atomic number ratios of [In]:[M]:[Zn] = (1 + α):(1 - α):1 (-1 ≤ α ≤ 1), [In]:[M]:[Zn] = (1 + α):(1 - α):2, [In]:[M]:[Zn] = (1 + α):(1 - α):3, [In]:[M]:[Zn] = (1 + α):(1 - α):4, and [In]:[M]:[Zn] = (1 + α):(1 - α):5.

[0074] Also, the dashed-dotted lines represent the lines with the atomic number ratios of [In]:[M]:[Zn] = 1:1:β (β ≥ 0), [In]:[M]:[Zn] = 1:2:β, [In :[M]:[Zn] = 1:3:β, [In]:[M]:[Zn =1:4:β, [In]:[M]:[Zn]=1:7:β, [In]:[M]:[Zn] = 2:1:β, and [In]:[M]:[Zn] = 5:1:β.

[0075] Also, the oxide semiconductor with the atomic number ratio of [In]:[M]:[Zn] = 0:2:1 or values near it shown in Fig. 8 tends to have a spinel-type crystal structure.

[0076] Region A2 shown in Fig. 8 has the atomic number ratios of indium, element M, and zinc that region A1 has. An example of a preferable range is shown. Region A2 includes the line where the atomic ratio of [In]:[M]:[Zn =(1+γ):0:(1-γ) (-1≦γ≦1). Let it be so.

[0077] Region B2 shown in FIG. 8 shows an example of the preferable range of the atomic ratio of indium, element M, and zinc that region B1 has. Note that region B2 includes [In]:[M]:[Zn =4:2:3 to 4.1 and nearby values. The nearby values include, for example, the atomic ratio of [In]:[M]:[Zn]=5:3:4. Region B2 also includes [In]: M]:[Zn]=5:1:6 and nearby values.

[0078] Since the concentration of In in region A2 is high, the conductivity is higher than that of region B2, and it has a function of increasing the carrier mobility (field-effect mobility). Therefore, the on-current and carrier mobility of a transistor using the oxide semiconductor film having region A1 can be increased. <\

[0079] On the other hand, since the concentration of In in region B \alpha is low, the conductivity is lower than that of region A2, and it has a function of reducing the leakage current. Therefore, the off-current of a transistor using the oxide semiconductor film having region B1 can be lowered.

[0080] In the oxide semiconductor film of one aspect of the present invention, region A1 and region B1 form a composite. That is, carrier movement easily occurs in region A1, and carrier movement hardly occurs in region B1. Therefore, the oxide semiconductor of one aspect of the present invention can be used as a material having high carrier mobility, high switching characteristics, and good semiconductor characteristics. ​​​​​​​

[0081] As an example, as shown in FIG. 4(A), in the a-b plane direction and the c-axis direction, there are a plurality of granular (also referred to as cluster-like) ones present. Note that the clusters may be irregularly distributed. Also, when multiple clusters are in a superimposed or continuous state, for example, one cluster may be connected in a superimposed shape with another cluster, and region A1 may be observed to spread in a cloud-like manner.

[0082] However, when all regions A1 are connected in the a-b plane direction, the switching characteristics of the transistor deteriorate. For example, since the off-current of the transistor increases, as shown in FIGS. 4(A) and 4(B), it is preferable that region A1 is scattered within region B1. Therefore, region A1 can exist in a state of being three-dimensionally enclosed by region B1. That is, region A1 has a structure of being enclosed by region B1.

[0083]

[0084] It is possible to form a composite oxide semiconductor with a large proportion of region A1. For example, a composite oxide semiconductor with a smaller proportion of region A1 than the composite oxide semiconductors shown in FIGS. 4(A) and 4(B) can be shown as in FIGS. 5(A) and 5(B). Here, FIG. 5(A) is a conceptual diagram corresponding to FIG. 4(A ), and FIG. 5(B) is a conceptual diagram corresponding to FIG. 4(B). Also, in the composite oxide semiconductor according to one aspect of the present invention, the proportion of region A1 is not necessarily small with respect to region B1. In a composite oxide semiconductor with a very large proportion of region A1, depending on the observed range, region B1 may be formed within region A1. Further, for example, the size of the region of the granular formed by region A1 can be appropriately adjusted according to the production conditions or composition of the composite oxide semiconductor.

[0085] Also, there may be cases where a clear boundary cannot be observed between region A1 and region B1. Note that the sizes of region A1 and region B1 can be evaluated by EDX mapping using energy dispersive X-ray spectroscopy (EDX). For example, in the EDX mapping of a cross-sectional photograph or a planar photograph of the cluster of region A1, the diameter of the cluster may be observed to be 0.1 nm or more and 2.5 nm or less. Preferably, the diameter of the cluster is 0.5 nm or more and 1.5 nm or less.

[0086] Thus, the oxide semiconductor according to one aspect of the present invention is a composite oxide semiconductor in which region A1 and region B1 are mixed, and the functions of region A1 and region B1 are different from each other, and region A1 and region B1 function complementarily. For example, when element M is Ga, In-Ga ​​​​​​​​- In the case of a zinc oxide (hereinafter referred to as IGZO), the oxide semiconductor of one embodiment of the present invention is Co It can be called complementary IGZO (abbreviation: C / IGZO).

[0087] On the other hand, for example, in the case of a configuration in which region A1 and region B1 are laminated in layers, since there is no interaction or the interaction is unlikely to occur between region A1 and region region B1, the functions of region A1 and the function of region B1 may function independently. In this case, even if the carrier mobility can be increased by region A1, the off-current of the transistor may increase. Therefore, by using the above-described composite oxide semiconductor or C / IGZO, it is possible to simultaneously have a function of high carrier mobility and a function of good switching characteristics. This is an excellent effect obtained by the composite oxide semiconductor of one embodiment of the present invention. There is.

[0088] When forming a film of an oxide semiconductor using a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of the target is formed. In particular, depending on the substrate temperature during film formation, in the case of [Zn], the atomic ratio of the film may be smaller than the atomic ratio of the target. There is.

[0089] In addition, the characteristics of the composite oxide semiconductor which is one embodiment of the present invention are not uniquely determined by the atomic ratio. Therefore, the illustrated regions are regions showing the preferred atomic ratios of region A1 included in the composite oxide semiconductor and region B 1, and the boundaries are not strict. There is.

[0090] In addition, the oxide semiconductor according to the present invention is not limited to the above. Conceptual diagrams of oxide semiconductor films having structures different from the above are shown in FIGS. 6 and 7. FIGS. 6(A) and 7(A) are shown. Conceptual diagram of the upper surface of the composite oxide semiconductor (hereafter referred to as the a-b plane direction), FIG. 6(B) , and FIG. 7(B) are conceptual diagrams of a cross-section (hereafter referred to as the c-axis direction) in which a composite oxide semiconductor is formed on a substrate Sub. . Note that the structure of the oxide semiconductor film shown in FIGS. 6 and 7 can refer to the structure of the oxide semiconductor film shown in FIG. 4, except for the following points.

[0091] Here, the oxide semiconductor is divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors . Examples of the non-single-crystalline oxide semiconductor include CAAC-OS (c-axis al igned crystalline oxide semiconductor), poly crystalline oxide semiconductor, nc-OS (nanocrystalline oxide sem iconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorph ous-like oxide semiconductor), and amorphous oxide semiconduct or, etc.

[0092] CAAC-OS has c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the a-b plane direction and have strain. Note that the strain means that the CAAC-OS has a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned, and the direction of the lattice arrangement changes between these regions . The place where the direction of the lattice arrangement changes is referred to as a location . .

[0093] Here, FIGS. 6(A) and 7(A) schematically show a plurality of nanocrystals with broken lines . The nanocrystals are based on hexagons, but are not necessarily regular hexagons and may be non-regular hexagons . Also, in the strain, there may be cases where there are polygonal nanocrystals such as pentagons and heptagons .

[0094] In addition, in CAAC-OS, clear grain boundaries were observed even near the strain. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is not dense in the ab-plane direction. The substitution of metal elements causes changes in the bond distance between atoms, resulting in distortion. This is thought to be because it can tolerate the

[0095] In addition, in Fig. 6(B) and Fig. 7(B), the nanocrystals have a c-axis orientation, and the c-axis is CAA. The surface on which the C-OS film is to be formed (also called the surface on which the film is to be formed) or the upper surface of the C-OS film is to be formed. The CAAC-OS has a layered crystal structure with a c-axis orientation. It has a layered structure (also called a layered structure) and a layer containing indium and oxygen (hereinafter referred to as the In layer). and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M, Zn) layer). do.

[0096] Indium and element M may be substituted for each other. Therefore, the (M, Zn) layer A part of the element M is replaced with indium, and it can also be expressed as an (In, M, Zn) layer. In this case, a layered structure is formed in which an In layer and an (In, M, Zn) layer are stacked.

[0097] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0098] The a-like OS is an oxide having a structure between nc-OS and an amorphous oxide semiconductor. The semiconductor is an a-like OS. The a-like OS has a loose or low-density region. That is, the a-lik e OS has an unstable structure compared with nc-OS and CAAC-OS.

[0099] Oxide semiconductors have various structures, each having various characteristics. The oxide semiconductor of the present invention may be a composite oxide semiconductor having two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS , and CAAC-OS. Also, region A1 and region B1 may have different crystallinities.

[0100] For example, region A1 is preferably non-single crystal. When region A1 has crystallinity, when region A1 is composed of indium, it tends to have a tetragonal crystal system. Also, the region When A1 is composed of indium oxide ([In]:[M]:[Zn]=x:0:0 (x>0)), it tends to have a bixbyite-type crystal structure. Also, when region A1 is composed of In- Zn oxide ([In]:[M]:[Zn]=x:0:z (x>0, z>0)), it tends to have a layered crystal structure.

[0101] On the other hand, region B1 has CAAC-OS. However, region B1 does not necessarily consist only of CAAC-OS, and may have regions such as a polycrystalline oxide semiconductor and nc-OS.

[0102] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, since CAAC-OS does not have a clear crystalline grain boundary, a decrease in electron mobility due to the crystalline grain boundary does not occur. It can be said to be difficult. Also, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, by having CAAC-OS, the physical properties of the composite oxide semiconductor are stabilized, so that a composite oxide semiconductor that is heat-resistant and highly reliable can be provided.

[0103] In addition, in the above, the ratio at which region A1 is scattered can be adjusted according to the production conditions of the composite oxide semiconductor and also the composition. For example, as shown in FIGS. 7(A) and 7(B), a composite oxide semiconductor with a small ratio of region A1 can be formed. Or, a composite oxide semiconductor with a large ratio of region A1 can be formed.

[0104] <1-3. Transistor having an oxide semiconductor film> Subsequently, the case where the above oxide semiconductor film is used for a transistor will be described.

[0105] In addition, by using the above composite oxide semiconductor for a transistor, a transistor with high carrier mobility and high switching characteristics can be realized. Also, a highly reliable transistor can be realized.

[0106] Also, for a transistor, it is preferable to use an oxide semiconductor film with a low carrier density. For example, the oxide semiconductor film has a carrier density of less than 8×10 11 / cm 3 , preferably less than 1 ×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 and less than 1×10 ​​​​​-9 / cm 3 This is all that is required.

[0107] When reducing the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced, and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. An oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, and thus the carrier density can be reduced. In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0108] In addition, the charge trapped in the trap levels of the oxide semiconductor film may take a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0109] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor film. In addition, in order to reduce the impurity concentration in the oxide semiconductor film it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0110] Here, the influence of each impurity in the oxide semiconductor film will be described.

[0111] In an oxide semiconductor film, when silicon or carbon, which is one of the Group 14 elements, is contained, the acid ​Defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry)) shall be 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0112] In addition, when the oxide semiconductor film contains an alkali metal or an alkaline earth metal, defect levels may be formed to generate carriers. Therefore, a transistor using an oxide semiconductor film containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film obtained by SIMS shall be 1×10 atoms / cm or less, preferably 18 2×10 3 atoms / cm or less. 16 atoms / cm 3 or less.

[0113] In addition, in the oxide semiconductor film, when nitrogen is contained, electrons as carriers are generated, and the carrier density increases, making it easy to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor shall be 5×10 atoms / cm or less in SIMS, 19 atoms / cm 3Less than, preferably 5×1 0 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, Even more preferably 5×10 17 atoms / cm 3 Shall be below.

[0114] In addition, hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water Therefore, oxygen vacancies (V o ) may be formed. When hydrogen enters the oxygen vacancies (V o ), electrons, which are carriers, may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 atoms / cm Below, preferably less than 1×10 atoms / cm 20 Below, more preferably less than 5×10 3 Less than Preferably less than 1×10 19 atoms / cm 3 Below, even more preferably less than 5×10 18 at oms / cm 3 Below, even more preferably less than 1×10 18 atoms / cm 3 Shall be below.

[0115] Incidentally, oxygen vacancies (V o ) in the oxide semiconductor film can be reduced by introducing oxygen into the oxide semiconductor film. That is, when oxygen fills the oxygen vacancies (V ) in the oxide semiconductor film, the oxygen vacancies (V o ) are filled, and the oxygen vacancies (V o) disappears. Therefore, by diffusing oxygen into the oxide semiconductor film, oxygen vacancies (V ) in the transistor can be reduced, and the reliability can be improved. o ) can be reduced, and the reliability can be improved. It is possible.

[0116] As a method of introducing oxygen into the oxide semiconductor film, for example, an oxide containing more oxygen than oxygen satisfying the stoichiometric composition can be provided in contact with the oxide semiconductor. That is, it is preferable that the oxide has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, when an oxide semiconductor film is used for a transistor, by providing an oxide having an excess oxygen region in the underlying film or the interlayer film near the transistor, the oxygen vacancies in the transistor can be reduced, and the reliability can be improved. [[ID=;13]] it is preferable that the oxide has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, when an oxide semiconductor film is used for a transistor, by providing an oxide having an excess oxygen region in the underlying film or the interlayer film near the transistor, the oxygen vacancies in the transistor can be reduced, and the reliability can be improved. it is preferable that the oxide has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, when an oxide semiconductor film is used for a transistor, by providing an oxide having an excess oxygen region in the underlying film or the interlayer film near the transistor, the oxygen vacancies in the transistor can be reduced, and the reliability can be improved. it is preferable that the oxide has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, when an oxide semiconductor film is used for a transistor, by providing an oxide having an excess oxygen region in the underlying film or the interlayer film near the transistor, the oxygen vacancies in the transistor can be reduced, and the reliability can be improved. it is preferable that the oxide has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, when an oxide semiconductor film is used for a transistor, by providing an oxide having an excess oxygen region in the underlying film or the interlayer film near the transistor, the oxygen vacancies in the transistor can be reduced, and the reliability can be improved.

[0117] By using an oxide semiconductor film with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted. By using an oxide semiconductor film with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0118] <1-4. Method for manufacturing a composite oxide semiconductor> Here, an example of a method for manufacturing a composite oxide semiconductor shown in FIGS. 4(A) and 4(B) will be described with reference to FIGS. 9 to 13. The composite oxide semiconductor according to one aspect of the present invention can be formed using a sputtering apparatus. Here, an example of a method for manufacturing a composite oxide semiconductor shown in FIGS. 4(A) and 4(B) will be described with reference to FIGS. 9 to 13. The composite oxide semiconductor according to one aspect of the present invention can be formed using a sputtering apparatus. Here, an example of a method for manufacturing a composite oxide semiconductor shown in FIGS. 4(A) and 4(B) will be described with reference to FIGS. 9 to 13. The composite oxide semiconductor according to one aspect of the present invention can be formed using a sputtering apparatus.

[0119] <1-5. Sputtering apparatus> FIG. 9(A) is a cross-sectional view for explaining the film formation chamber 2501 of the sputtering apparatus, and FIG. 9(B) is a plan view of the magnet unit 2530a and the magnet unit 2530b of the sputtering apparatus. FIG. 9(B) is a plan view of the magnet unit 2530a and the magnet unit 2530b of the sputtering apparatus.

[0120] The film deposition chamber 2501 shown in Fig. 9(A) includes a target holder 2520a, a target holder 2520b, a backing plate 2510a, a backing plate 2510b, a target 2500a, a target 2500b, a member 2542, and a substrate holder 257 0. The target 2500a is disposed on the backing plate 2510a. The backing plate 2510a is disposed on the target holder 2520a. The magnet unit 2530a is disposed under the target 2500a through the backing plate 2510a. The target 2500b is disposed on the backing plate 2510b. The backing plate 2510b is disposed on the target holder 2520b. The magnet unit 2530b is disposed under the target 2500b through the backing plate 2510b.

[0121] As shown in Fig. 9(A) and Fig. 9(B), the magnet unit 2530a includes a magnet 2530N1, a magnet 2530N2, a magnet 2530S, and a magnet holder 2532. In the magnet unit 2530a, the magnet 2530N1, the magnet 2530N2, and the magnet 2530S are disposed on the magnet holder 2532. The magnet 2530N1 and the magnet 2530N 2 are disposed at intervals from the magnet 2530S. The magnet unit 25 30b has the same structure as the magnet unit 2530a. When the substrate 2560 is carried into the film deposition chamber 2501, the substrate 2560 is disposed in contact with the substrate holder 2570.

[0122] ​​​​​ Target 2500a, backing plate 2510a, and target holder 2520 a, and target 2500b, backing plate 2510b, and target holder 25 20b are separated by member 2542. Note that member 2542 is preferably an insulator. However, member 2542 may be a conductor or a semiconductor. Also it is possible that member 2542 has a surface of a conductor or a semiconductor covered with an insulator. .

[0123] Target holder 2520a and backing plate 2510a are fixed using screws (such as bolts ) and are at the same electric potential. Also, target holder 2520a has the function of supporting target 2500a via backing plate 2510a. Also target holder 2520b and backing plate 2510b are fixed using screws (such as bolts ) and are at the same electric potential. Also, target holder 2520b has the function of supporting target 2500b via backing plate 2510b.

[0124] Backing plate 2510a has the function of fixing target 2500a. Also backing plate 2510b has the function of fixing target 2500b.

[0125] Note that in Fig. 9(A), magnetic field lines 25 80a, 2580b formed by magnet unit 2530a are shown explicitly.

[0126] Also, as shown in Fig. 9(B), magnet unit 2530a includes a rectangular or substantially rectangular magnet 2530N1, a rectangular or substantially rectangular magnet 2530N2, and ​A rectangular or substantially rectangular magnet 2530S is fixed to a magnet holder 2532. It has such a configuration. And the magnet unit 2530a can be swung left and right as shown by the arrow in FIG. 9(B). For example, the magnet unit 2530a may be swung at a beat of 0.1 Hz or more and 1 kHz or less.

[0127] The magnetic field on the target 2500a changes along with the swing of the magnet unit 2530a. Since the region with a strong magnetic field becomes a high-density plasma region, the sputtering phenomenon of the target 2 500a is likely to occur in the vicinity thereof. This is the same for the magnet unit 2530b.

[0128] <1-6. Fabrication Flow of Composite Oxide Semiconductor> FIG. 10 is a process flow diagram for explaining a method of manufacturing a composite oxide semiconductor.

[0129] The composite oxide semiconductor shown in FIGS. 4(A) and (B) is manufactured through at least the first to fourth processes shown in FIG. 10.

[0130] [First Process: Process of Placing a Substrate in a Film Deposition Chamber] The first process has a process of placing a substrate in a film deposition chamber (see step S101 in FIG. 10) .

[0131] As the first process, for example, the substrate 2560 is placed on the substrate holder 2570 of the film deposition chamber 2501 shown in FIG. 9.

[0132] The temperature of the substrate 2560 may be room temperature (25°C) or higher and 200°C or lower, preferably room temperature or higher and 130°C or lower. By setting the substrate temperature within the above range, a large-area glass substrate can be used. ​​This is suitable when there is [a certain situation]. In particular, by setting the substrate temperature during the film formation of the composite oxide semiconductor to room temperature, or in other words, keeping it in a state where it is not intentionally heated, it is possible to suppress the bending or distortion of the substrate, which is suitable.

[0133] Also, a configuration in which a cooling mechanism or the like is provided in the substrate holder 2570 to cool the substrate 2560 is also good.

[0134] Also, by setting the temperature of the substrate 2560 to 100 °C or higher and 130 °C or lower, water in the composite oxide semiconductor can be removed. By removing water, which is an impurity in this way, it becomes easier to form the composite oxide semiconductors shown in FIGS. 5(A) and 5(B). As a result, while improving the field-effect mobility, the reliability can be improved.

[0135] Also, by setting the temperature of the substrate 2560 to 100 °C or higher and 130 °C or lower, it is possible to prevent the sputtering device from being distorted due to excessive heat. As a result, the productivity of the semiconductor device can be improved. Therefore, since the productivity is stabilized, it is easy to introduce a large-scale production device, and it is possible to easily manufacture a large-sized display device using a large-area substrate.

[0136] [Second step: Step of introducing gas into the film formation chamber] The second step has a step of introducing gas into the film formation chamber (see step S201 in FIG. 10).

[0137] As the second step, for example, gas is introduced into the film formation chamber 2501 shown in FIG. 9. As the gas either one or both of argon gas and oxygen gas may be introduced. Note that ​​, inert gases such as helium, xenon, and krypton may be used instead of argon gas .

[0138] When forming a composite oxide semiconductor using oxygen gas, the proportion of oxygen in the entire film-forming gas may sometimes be described as the "oxygen flow rate ratio". The oxygen flow rate ratio during the film formation of the composite oxide semiconductor is 0% or more and 30% or less, preferably 5% or more and 30% or less, and more preferably 7% or more and 15% or less.

[0139] Also, when forming the composite oxide semiconductor shown in FIGS. 5(A) and 5(B), the oxygen flow rate ratio should be greater than 30% and less than 70%, preferably greater than 30% and 50% or less, for room temperature film formation. Also, for heated film formation (for example, 70°C or more and 150°C or less) it should be 10% or more and 50% or less, preferably 30% or more and 50% or less.

[0140] Also, when forming the composite oxide semiconductor shown in FIGS. 6(A) and 6(B), or FIGS. 7(A) and 7(B), a mixed gas of a noble gas and oxygen is used, and the gas ratio of oxygen to the noble gas should be 70% or more and 100% or less.

[0141] Also, high-purity of the above gases is also necessary. For example, the oxygen gas and argon gas used as the gas should be a gas purified to a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, and even more preferably -120°C or lower. By using such a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the composite oxide semi- conductor as much as possible.

[0142] Also, the film formation chamber 2501 should remove water and the like that would be impurities for the composite oxide semiconductor as much as possible An adsorption type vacuum exhaust pump such as a cryopump should be used to evacuate to a high vacuum (from 5×10 - 7 Pa to about 1×10 -4 Pa). In particular, during the standby of the sputtering device, the partial pressure of gas molecules corresponding to H2O in the film formation chamber 2501 (gas molecules corresponding to m / z = 1 8) should be 1×10 -4 Pa or less, preferably 5×10 -5 Pa or less. It is preferably set as follows.

[0143] [Third step: Step of applying a voltage to the target] The third step has a step of applying a voltage to the target (see Figure 10, step S301). See).

[0144] As the third step, for example, a voltage is applied to the target holders 2520a and 2520b shown in Figure 9. As an example, the potential applied to the terminal V1 connected to the target holder 2520a is set to be lower than the potential applied to the terminal V2 connected to the substrate holder 2570. Also, the potential applied to the terminal V4 connected to the target holder 2520b is set to be lower than the potential of the terminal V2 connected to the substrate holder 2570. Also, the potential applied to the terminal V2 connected to the substrate holder 2570 is set to the ground potential. Also, the potential applied to the terminal V3 connected to the magnet holder 2532 is set to the ground potential. The potential applied to the terminal V1 connected to the target holder 2520a is set to be lower than the potential applied to the terminal V2 connected to the substrate holder 2570. Also, the potential applied to the terminal V4 connected to the target holder 2520b is set to be lower than the potential of the terminal V2 connected to the substrate holder 2570. Also, the potential applied to the terminal V2 connected to the substrate holder 2570 is set to the ground potential. Also, the potential applied to the terminal V3 connected to the magnet holder 2532 is set to the ground potential. the potential applied to the terminal V2 connected to the substrate holder 2570 is set to the ground potential. Also, the potential applied to the terminal V3 connected to the magnet holder 2532 is set to the ground potential. Note that the potentials applied to the terminals V1, V2, V3, and V4 are not limited to the above potentials. Also, potentials do not have to be applied to all of the target holder 2520, the substrate holder 2570, and the magnet holder 2532. For example, the substrate holder 2570 may be electrically

[0145] not applied. For example, the substrate holder 2570 may be electrically not applied. not applied. For example, the substrate holder 2570 may be electrically It may be in a floating state in terms of qi. Note that the control of the applied potential to the terminal V1 is such that a power source capable of doing so is electrically connected. As the power source, a DC power source, an AC power source, or an RF power source may be used.

[0146] Also, as the targets 2500a and 2500b, targets having indium, an element M (where M is Al, Ga, Y, or Sn), zinc, and oxygen are preferably used. As an example of the targets 2500a and 2500b, an In-G a-Zn metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]), an I n-Ga-Zn metal oxide target (In:Ga:Zn = 5:1:7 [atomic ratio]), etc. can be used. Hereinafter, the case of using an In-Ga-Zn metal oxide target (In:G a:Zn = 4:2:4.1 [atomic ratio]) will be described.

[0147] Note that when a sputtering target containing a polycrystalline oxide having a plurality of crystal grains is used for the targets 2500a and 2500b, a composite oxide semiconductor having crystallinity as shown in FIG. 4 or FIG. 8 is easily obtained.

[0148] [Fourth step: Step of depositing a composite oxide semiconductor on a substrate] The fourth step has a step of ejecting sputtered particles from the target and depositing a composite oxide semiconductor on the substrate (see step S401 in FIG. 10).

[0149] As the fourth step, for example, in the film formation chamber 2501 shown in FIG. 9, argon gas or oxygen gas is ionized and separated into cations and electrons to form a plasma. Then, in the plasma ​​​​The cations are accelerated toward the targets 2500a and 2500b by the potential applied to the target holders 2520a and 2520b. When the cations collide with the In-Ga-Zn metal oxide target, sputtered particles are generated and deposited on the substrate 2560. Sputtered particles are generated, and sputtered particles are deposited on the substrate 2560.

[0150] Note that as the targets 2500a and 2500b, an In-Ga-Zn metal oxide target with an atomic ratio of In:Ga:Zn = 4: 2:4.1 or an atomic ratio of In:Ga:Zn = 5:1:7 may have a plurality of crystal grains with different compositions in the target. For example, the plurality of crystal grains often have a diameter of 10 μm or less. Also, for example , when the In-Ga-Zn metal oxide target contains crystal grains with a high proportion of In, the proportion of the region A1 described above may increase.

[0151] <1-7. Film formation model> Next, in the fourth step, the film formation models shown in FIGS. 11(A) and FIG. 11(B) can be considered.

[0152] FIGS. 11(A) and FIG. 11(B) are cross-sectional views near the target 2500a shown in FIG. 9. Note that FIGS. 11(A) and FIG. 11(B) show the backing plate 2510a, the target 2500a, the plasma 2190, the cations 2192, the sputtered particles 2194, etc. are shown.

[0153] [First step] In FIG. 11(A), argon gas or oxygen gas is ionized and separated into cations 2192 and electrons ( (not shown)) to form a plasma 2190. Then, in the plasma 2190 ​​​The positive ions 2192 are accelerated toward the target 2500a (here, an In-Ga-Zn metal oxide target). When the positive ions 2192 collide with the In-Ga-Zn metal oxide target, sputtered particles 2194 are generated and ejected from the In-Ga-Zn metal oxide target. In the In-Ga-Zn metal oxide target, it is considered that Ga and Zn are preferentially sputtered first as the sputtered particles 2194.

[0154] More specifically, when the positive ions 2192 collide with the In-Ga-Zn metal oxide target, Ga and Zn, whose relative atomic masses are lighter than In, are preferentially ejected from the In-Ga-Zn metal oxide target. The ejected In, Ga, and Zn combine with oxygen and deposit on the substrate, forming the region B1 shown in FIGS. 4(A) and (B). [[ID=2I]]

[0155] As shown in FIG. 11(A), after Ga and Zn are preferentially sputtered as the sputtered particles 2194, In may segregate on the surface of the target 2500a, here, the surface of the In-Ga-Zn metal oxide target. In FIG. 11(A), the state where In is segregated is indicated as the cluster 2196.

[0156] [Second Step] Subsequently, as shown in FIG. 11(B), after In is segregated, that is, after the cluster 2196 is formed, the cluster 2196, here, the cluster containing In, is sputtered from the In-Ga-Zn metal oxide target.

[0157] ​​​​​More specifically, In segregated on the surface of the In-Ga-Zn metal oxide target forms a structure like a plurality of clusters and is ejected from the In-Ga-Zn metal oxide target. The segregated In that forms a structure like a plurality of clusters combines with oxygen and collides with the previously formed region B1, and a cluster-shaped (granular) region A1 is deposited. Since the segregated In is ejected, In, Ga, and Zn on the surface of the In-Ga-Zn metal oxide target are in a state close to the original atomic ratio.

[0158] Also, as shown in FIG. 11(B), in one region on the surface of the target 2500a, In segregates, and in other regions on the surface of the target 2500a, the segregated In is ejected. That is, the mechanism by which In segregates and the mechanism by which the segregated In is ejected occur simultaneously, so that the region A1 is sandwiched between the regions B1 and has an irregularly distributed structure.

[0159] By repeating the film formation models of the first step and the second step, a composite oxide semiconductor according to one aspect of the present invention shown in FIGS. 4(A) (B) can be obtained.

[0160] Here, a manufacturing method by a sputtering method has been described, but the present invention is not limited thereto. Other methods such as a pulsed laser deposition (PLD) method, a plasma chemical vapor deposition (PECVD) method, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, and a vacuum evaporation method may be used. As an example of the thermal CVD method, an MOCVD (Metal Organic Chemical Vapo r Deposition) method can be mentioned.

[0161] <1-8. Verification of the film formation model> Next, in order to verify the above film formation model, a sample Z1 shown below was fabricated.

[0162] [Sample Z1] Sample Z1 is a sample in which an insulating film 82, an insulating film 84, an oxide semiconductor film 88, and an insulating film 86 are formed in this order on a glass substrate. The insulating film 82 and the insulating film 84 have the function as an underlayer film. As the insulating film 82, a silicon nitride film with a thickness of 400 nm was formed using a PECVD apparatus. Also, as the insulating film 84, a silicon oxynitride film with a thickness of 50 nm was formed using a PECVD apparatus.

[0163] The insulating film 82 and the insulating film 84 have the function as an underlayer film. As the insulating film 82, a silicon nitride film with a thickness of 400 nm was formed using a PECVD apparatus. Also, as the insulating film 84, a silicon oxynitride film with a thickness of 50 nm was formed using a PECVD apparatus. The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film. The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film.

[0164] The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film. The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film. The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film. The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film. (In:Ga:Zn = 4:2:4.1 [atomic ratio]) to form a film. The oxide semiconductor film 88 is an In-Ga-Zn oxide with a thickness of 40 nm, which was formed using a sputtering apparatus. Note that for the oxide semiconductor film 88, the substrate temperature was set to 170°C, argon gas with a flow rate of 35 sccm and oxygen gas with a flow rate of 15 sccm were introduced into the chamber, the pressure was set to 0.2 Pa, and 1500 W of AC power was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) installed in the sputtering apparatus to form a film.

[0165] Note that in this embodiment, the oxide semiconductor film 88 is assumed to be a sputtering target for forming a composite oxide semiconductor. Note that in this embodiment, the oxide semiconductor film 88 is assumed to be a sputtering target for forming a composite oxide semiconductor.

[0166] Next, after the formation of the oxide semiconductor film 88, assuming a sputtering apparatus, plasma treatment of the surface of the oxide semiconductor film 88 with argon gas was performed. For this plasma treatment, argon gas with a flow rate of 100 sccm was introduced into the chamber, and the pressure in the chamber was set to 40 Next, after the formation of the oxide semiconductor film Next, after the formation of the oxide semiconductor film 88, assuming a sputtering apparatus, plasma treatment of the surface of the oxide semiconductor film 8 with argon gas was performed. For this plasma treatment, argon gas with a flow rate of 100 sccm was introduced into the chamber, and the pressure in the chamber was set to 40 It was carried out by supplying 1000 W of power to the RF power supply (27.12 MHz) as Pa.

[0167] After the plasma treatment, an insulating film 86 was formed on the oxide semiconductor film 88. The insulating film 86 has a function as a protective insulating film. As the insulating film 86, a silicon oxynitride film with a thickness of 100 nm was formed using a PECVD apparatus.

[0168] By the above steps, a sample Z1 for verifying the film formation model was fabricated.

[0169] Next, HAADF (High-Angle Annular Dark Field)-STEM observation of the cross-section of the sample Z1 was performed. For the HAADF-STEM observation, JEM-ARM200F manufactured by JEOL Ltd. was used, and the acceleration voltage was set to 200 kV. The HAADF-STEM observation results of the sample Z1 are shown in FIG. 13.

[0170] As shown in FIG. 13, it can be seen that a structure 90 is formed on the oxide semiconductor film 88. Also, from the HAADF-STEM observation results,

[0171] the thickness of the oxide semiconductor film 88 was approximately 36 nm, and the thickness of the structure 90 was approximately 11 nm. Next, in order to evaluate the composition of the structure 90, elemental analysis was performed on point 1 shown in the oxide semiconductor film 88

[0172] and point 2 shown in the structure 90. For the elemental analysis, JED-2300T was used as the EDX analyzer. The beam diameter of the elemental analysis was set to 0.1 nmφ.

[0173] The results of the EDX analysis are shown in Table 1.

[0174]

Table 1

[0175] When the value of point 1 shown in Table 1 is normalized by the In value of the metal oxide target, it can be seen that In :Ga:Zn:O = 4:2:2.4:7.2 [atomic ratio]. Regarding the atomic ratio of Zn, although there is a slight deviation from the composition of the metal oxide target, the composition of the oxide semiconductor film 88 generally reflects the composition of the metal oxide target. On the other hand, as shown in Table 1, the structure 90 has a large proportion of In. Therefore, it can be said that the structure 90 is a precipitate of In or indium oxide precipitate.

[0176] The above-mentioned precipitate of In or indium oxide can be considered as the state where In on the surface of the In-Ga-Zn metal oxide target of the film formation model described above is segregated (cluster 2196) and can be considered. Therefore, it can be seen that the film formation model described above is sufficiently reasonable .

[0177] In addition, when forming the composite oxide semiconductor of one aspect of the present invention shown in FIG. 6, in the fourth step , the film formation models shown in FIGS. 12(A) and 12(B) can be considered.

[0178] FIGS. 12(A) and 12(B) are cross-sectional views near the target 2500a shown in FIG. 9 . Note that FIG. 12 shows the backing plate 2510a, the target 2500a, the plasma 2190, the cations 2192, the sputter particles 2194, etc. clearly .

[0179] In the film formation chamber 2501 shown in FIG. 12(A), argon gas or oxygen gas is ionized and separated into cations 2192 and electrons (not shown) to form plasma 2190. Then ​​​ The cations 2192 in the plasma 2190 are accelerated toward the target 2500a (here, an In-Ga -Zn metal oxide target). When the cations 2192 collide with the In-Ga-Zn metal oxide target, sputtered particles 2194 are generated, and the sputtered particles 2194 are ejected from the In-Ga -Zn metal oxide target.

[0180] Here, the target 2500a and the target 2500b have a polycrystalline structure having a plurality of crystal grains. The plurality of crystal grains often have a diameter of 10 μm or less. In addition, for example, in an In-Ga-Zn metal oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1 or an atomic ratio of In :Ga:Zn = 5:1:7, etc., the plurality of crystal grains may have different compositions.

[0181] For example, in FIG. 12(A), the target 2500a has at least a region 2502a where the ratio of In is less than the atomic ratio of the target, and a region 2504a where the ratio of In is more than the atomic ratio of the target.

[0182] First, the region 2502a of the target 2500a where the ratio of In is less will be described.

[0183] As shown in FIG. 12(A), the cations 2192 generated in the high-density plasma region are accelerated toward the target 2500a by the electric field, and eventually collide with the region 2 502a of the target 2500a. At this time, clusters 2198, which are flat nanocrystals, are peeled off from the region 2502a. The cluster has two M-Zn-O layers and I located therebetween. ​​​​​​​It is often composed of an n-O layer. In addition, with the detachment of cluster 2198, sputtering particles 2194 are also ejected from target 2 500a.

[0184] In addition, cluster 2198 may be in the form of a cluster having a triangular, for example, equilateral triangle plane. Or, cluster 2198 may be in the form of a cluster having a hexagonal, for example, regular hexagonal plane. However, the shape of cluster 2198 is not limited to a triangle or a hexagon. For example, it may be a shape formed by combining a plurality of triangles. For example, it may be a quadrilateral (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles).

[0185] In addition, the thickness of cluster 2198 is determined according to the type of film-forming gas and the like. For example, cluster 2198 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, cluster 2198 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less.

[0186] In addition, when sputtering particles 2194 pass through plasma 2190, their surfaces may be negatively or positively charged. For example, sputtering particles 2194 may receive a negative charge from O2 - in plasma 2190. As a result, the oxygen atoms on the surface of sputtering particles 2194 may be negatively charged. Also, when sputtering particles 2194 pass through plasma 2190, they may grow by bonding with In, element M, Zn, or oxygen in plasma 2190. Therefore, sputtering particles 2194 have atoms or aggregates of several atoms.

[0187] ​​Cluster 2198 that has passed through the plasma 2190 and sputter particles 2194 reach the substrate surface. Here, since the cluster 2198 is flat-plate shaped, it is likely to deposit with its planar side facing the surface of the substrate . Some of the sputter particles 2194 may be discharged to the outside by a vacuum pump or the like because of their small mass.

[0188] The sputter particles 2194 reach the surface of the substrate. The sputter particles 2194 tend to bond to the side surface rather than the upper surface of the cluster 21 98, and the sputter particles 2194 preferentially adhere to the side surface of the cluster 2198 so as to fill the region where the cluster 2198 is not formed. The sputter particles 2194 chemically bond to the cluster 2198 to form a lateral growth portion by the bonds becoming active. Also, the sputter particles 2194 can enter the region between one cluster and another cluster.

[0189] The lateral growth portion grows laterally (also referred to as lateral growth) so as to fill the region (also referred to as the Lateral Growth Buffer Region (LGBR)) between one cluster and another cluster. Here, the lateral direction refers to, for example, the direction perpendicular to the c-axis in the cluster.

[0190] Here, a reaction is likely to occur in which sputter particles adhere to the lateral growth portion of the cluster, oxygen diffused through the LGBR adheres to the sputter particles, and sputter particles similarly adhere again. It is presumed that lateral solid-phase growth is occurring due to this repetition. Such lateral growth of the cluster can also be called self-organization.

[0191] Furthermore, as the lateral growth parts grow laterally, they collide with each other. The protruding part is used as a connecting part to connect adjacent clusters. However, lateral growth parts are formed on the sides of the cluster, and by growing laterally, one cluster and It can be said that the clusters fill the spaces between other clusters. Lateral growth occurs until the unformed area is filled. This mechanism is similar to that of atomic layer deposition. The deposition mechanism is similar to that of the ALD (Atomic Layer Deposition) method. Similar.

[0192] Therefore, even if multiple clusters are formed facing different directions, The sputtered particles grow laterally and fill the gaps between clusters. A clear grain boundary is not formed, and a region B1 having a CAAC-OS is formed.

[0193] The layered crystal structure of CAAC-OS is stable over a wide range of compositions, and it is suitable for metals. The bond strength and equilibrium distance between the metal atom and the oxygen atom are different for each metal atom. The crystal structure of CAAC-OS is presumed to be tolerant to distortion. The sputtered particles smoothly connect (anchore) between the clusters, and at the connecting parts The resulting crystal structure is different from both single crystal and polycrystal. A strained crystal structure is formed at the connecting portion between the two. In the case where the crystal structure with a hexagonal top surface changes to a pentagonal or heptagonal shape, There are also.

[0194] Next, the region 2504a of the target 2500a where the proportion of In is high will be described. is clarified.

[0195] The cations 2192 generated in the high-density plasma region are accelerated by the electric field toward the target 2500a side and eventually collide with the region 2504a of the target 2500a. In In the Ga-Zn metal oxide target, as sputtered particles 2194, Ga and Z n are preferentially sputtered. That is, when the cations 2192 collide with the In-Ga-Zn metal oxide target, Ga and Zn, whose relative atomic mass is lighter than In, are preferentially ejected from the In-Ga-Zn metal oxide target. The ejected sp uttered particles 2194 are deposited on the substrate as described above, ejected from the region 2502a, and fill the region between the cluster 2198 deposited on the substrate and other clusters 2198, thereby forming the region B1.

[0196] Also, as shown in FIG. 12(A), after Ga and Zn are preferentially sputtered as the sputtered particles 2194, In is segregated on the surface of the region 2504a where the proportion of In is high. In FIG. 12(A), the segregated state of In is shown as the cluster 2196. The cluster 2196 preferably has a diameter of about 0.5 nm or more and 1.5 nm or less.

[0197] Subsequently, as shown in FIG. 12(B), after In is segregated, that is, after the cluster 2196 is formed, the cluster 2196 is sputtered from the region 2504a where the proportion of In is high.

[0198] More specifically, the In segregated on the surface of the In-Ga-Zn metal oxide target is in a granular state ​​It has a structure like a plurality of clusters and is ejected from an In-Ga-Zn metal oxide target. The segregated In with a structure like a plurality of clusters combines with oxygen and collides with the previously formed film region B1, and region A1 having granular clusters is deposited. Since the segregated In is ejected, on the surface of region 2504a, In, Ga, and Zn are in a state close to the original atomic ratio. The segregated In with a structure like a plurality of clusters combines with oxygen and collides with the previously formed film region B1, and region A1 having granular clusters is deposited. Since the segregated In is ejected, on the surface of region 2504a, In, Ga, and Zn are in a state close to the original atomic ratio. It has a structure like a plurality of clusters and is ejected from an In-Ga-Zn metal oxide target. Since the segregated In is ejected, on the surface of region 2504a, In, Ga, and Zn are in a state close to the original atomic ratio.

[0199] Also, as shown in FIG. 12, in region 2504a where the proportion of In in target 2500a is large, in one region on the surface, In segregates, and in other regions on the surface, the segregated In is ejected. That is, the mechanism by which In segregates and the mechanism by which the segregated In is ejected occur simultaneously. In region 2504a where the proportion of In is large, in one region on the surface, In segregates, and in other regions on the surface, the segregated In is ejected. That is, the mechanism by which In segregates and the mechanism by which the segregated In is ejected occur simultaneously. In region 2504a where the proportion of In is large, in one region on the surface, In segregates, and in other regions on the surface, the segregated In is ejected. That is, the mechanism by which In segregates and the mechanism by which the segregated In is ejected occur simultaneously. In region 2504a where the proportion of In is large, in one region on the surface, In segregates, and in other regions on the surface, the segregated In is ejected. That is, the mechanism by which In segregates and the mechanism by which the segregated In is ejected occur simultaneously.

[0200] Also, from the above, in region 2504a where the proportion of In is large, clusters 2196 are likely to be formed, and region A1 tends to be formed. On the other hand, in region 2502a where the proportion of In is small, the ejected clusters and sputtered particles combine with oxygen and are deposited on the substrate, and region B1 tends to be formed. In region 2504a where the proportion of In is large, clusters 2196 are likely to be formed, and region A1 tends to be formed. On the other hand, in region 2502a where the proportion of In is small, the ejected clusters and sputtered particles combine with oxygen and are deposited on the substrate, and region B1 tends to be formed. In region 2504a where the proportion of In is large, clusters 2196 are likely to be formed, and region A1 tends to be formed. On the other hand, in region 2502a where the proportion of In is small, the ejected clusters and sputtered particles combine with oxygen and are deposited on the substrate, and region B1 tends to be formed. In region 2504a where the proportion of In is large, clusters 2196 are likely to be formed, and region A1 tends to be formed. On the other hand, in region 2502a where the proportion of In is small, the ejected clusters and sputtered particles combine with oxygen and are deposited on the substrate, and region B1 tends to be formed.

[0201] Therefore, region A1 and region B1 spread in a cloud shape and have an irregularly distributed structure. From the above, a composite oxide semiconductor according to one aspect of the present invention shown in FIG. 6 can be obtained. Therefore, region A1 and region B1 spread in a cloud shape and have an irregularly distributed structure. From the above, a composite oxide semiconductor according to one aspect of the present invention shown in FIG. 6 can be obtained.

[0202] <1-9. Classification of Oxide Semiconductors> Next, the classification of oxide semiconductors will be described.

[0203] Oxide semiconductors are divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc- Oxide semiconductors are divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc- Examples of such a semiconductor include an OS, a pseudo-amorphous oxide semiconductor, and an amorphous oxide semiconductor.

[0204] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0205] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0206] That is, a stable oxide semiconductor is transformed into a completely amorphous In addition, it is not isotropic (for example, in a microscopic region, An oxide semiconductor having a periodic structure cannot be called a completely amorphous oxide semiconductor. -like OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is physically an amorphous oxide semiconductor. Close to.

[0207] [CAAC-OS] First, let me explain about CAAC-OS.

[0208] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0209] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0210] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0211] [nc-OS] Next, we will explain nc-OS.

[0212] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0213] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS may have a higher density of defect states than the CAAC-OS.

[0214] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0215] The a-like OS has a loose or low-density region. The a-like OS has a loose structure. Therefore, it has an unstable structure.

[0216] Also, since the a-like OS has a loose structure, compared with nc-OS and CAAC-OS, it has a lower density structure. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition. Also, the density of nc-OS and the density of CAAC- OS are 92.3% or more and less than 100% of the density of a single crystal with the same composition. An oxide semiconductor with a density of less than 78% of the density of a single crystal is difficult to form a film itself.

[0217] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm or more and less than 5.9 g / cm 3 . Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], 3 the density of nc-OS and the density of CAAC-OS are 5.9 g / cm or more and less than 6.3 g / cm 3 3

[0218] When there is no single crystal with the same composition, by combining single crystals with different compositions at an arbitrary ratio, the density corresponding to a single crystal in the desired composition can be estimated. The density corresponding to a single crystal of the desired composition is proportional to the ratio of combining single crystals with different compositions. ​​​, it may be estimated using a weighted average. However, the density is preferably estimated by combining as few types of single crystals as possible. It is preferable to estimate by combining.

[0219] As described above, the oxide semiconductor has various structures, each having various characteristics. Note that in the oxide semiconductor film of one aspect of the present invention, two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS may be mixed.

[0220] Note that the region A1 described above is preferably non-single crystal. Also, the region B1 is preferably non-single crystal. Also, the region A1 and the region B1 may have different crystallinities. It may be.

[0221] <1-10. Characteristics of the transistor> Next, general characteristics of the transistor will be described with reference to FIGS. 14 to 17.

[0222] [Id-Vg characteristics of the transistor] First, the drain current-gate voltage characteristics (Id-Vg characteristics) of the transistor will be described. FIG. 14(A) is a diagram for explaining an example of the Id-Vg characteristics of the transistor. Note that in FIG. 14(A), for simplicity of understanding, it is assumed that polycrystalline silicon is used for the active layer of the transistor. Also, in FIG. 14(A), the vertical axis represents Id and the horizontal axis represents V g, respectively.

[0223] As shown in FIG. 14(A), the Id-Vg characteristics are roughly divided into three regions. The first region is an off region, the second region is a subthreshold region, and the third region is an on region. region, and the third region is an on region (O They are respectively referred to as the N region). Also, the gate voltage at the boundary between the subthreshold region and the on region is referred to as the threshold voltage (Vth). is called the threshold voltage (Vth).

[0224] As characteristics of the transistor, it is desirable that the drain current in the off region (also called the off current or Ioff) is low and the drain current in the on region (also called the on current or Ion) is high. For the on current of the transistor, the case where the field-effect mobility is used as an index is often. Details of the field-effect mobility will be described later.

[0225] Also, in order to drive the transistor at a low voltage, it is desirable that the slope of the Id-Vg characteristic in the subthreshold region is steep. As an index representing the magnitude of the change in the Id-Vg characteristic in the subthreshold region, SS (subthreshold swing) or an S value, etc. are called. Note that the S value is represented by the following formula (1).

[0226]

Equation

[0227] The S value is the minimum value of the change amount of the gate voltage required for the drain current to change by one digit in the subthreshold region. The smaller the S value, the steeper the switching operation between on and off can be performed.

[0228] [Id-Vd Characteristics of Transistor] Next, the drain current-drain voltage characteristic (Id-Vd characteristic) of the transistor will be described. FIG. 14(B) is a diagram for explaining an example of the Id-Vd characteristic of the transistor. Also in FIG. 14(B), the vertical axis represents Id and the horizontal axis represents Vd respectively. ​​​​​​

[0229] As shown in FIG. 14(B), the on-region is further divided into two regions. The first region is called the linear region, and the second region is called the saturation region. In the linear region, the drain current increases parabolically as the drain voltage increases. On the other hand, in the saturation region, the drain current does not change significantly even when the drain voltage changes. Note that, analogous to a vacuum tube, the linear region may be referred to as the triode region and the saturation region may be referred to as the pentode region, respectively.

[0230] Also, the linear region may refer to a state where Vg is larger than Vd (Vd < Vg). Also, the saturation region may refer to a state where Vd is larger than Vg (Vg < Vd). However, in reality, it is necessary to consider the threshold voltage of the transistor. Therefore, a state where the value obtained by subtracting the threshold voltage of the transistor from Vg is larger than Vd (Vd < Vg - Vth) may be defined as the linear region. Similarly, a state where the value obtained by subtracting the threshold voltage of the transistor from Vg is smaller than Vd (Vg - Vth < Vd) may be defined as the saturation region.

[0231] In the Id-Vd characteristics of a transistor, a characteristic in which the current in the saturation region is constant may be expressed as "good saturation". The good saturation of a transistor is particularly important for applications to organic EL displays. For example, by using a transistor with good saturation as the transistor of a pixel in an organic EL display, it is possible to suppress changes in the brightness of the pixel even when the drain voltage changes.

[0232] [Analysis Model of Drain Current] Next, an analysis model of the drain current will be described. As the analysis model of the drain current there is an analytical expression of the drain current based on the Gradual channel approximation (GCA) that is known Based on GCA, the drain current of the transistor is expressed by the following equation (2). as follows.

[0233]

Equation

[0234] In Equation (2), the upper part is the equation of the drain current in the linear region, and the lower part is the equation of the drain current in the saturation region. In Equation (2), Id represents the drain current, μ represents the mobility of the active layer , L represents the channel length of the transistor, W represents the channel width of the transistor, Cox represents the gate capacitance , Vg represents the gate voltage, Vd represents the drain voltage, and Vth represents the threshold voltage of the transistor , respectively.

[0235] [Field-effect mobility] Next, the field-effect mobility will be described. As an index of the current driving force of the transistor, the field-effect mobility is used. As described above, the on region of the transistor is divided into a linear region and a saturation region. From the characteristics of each region, the field-effect mobility of the transistor can be calculated based on the analytical expression of the drain current based on GCA. When it is necessary to distinguish, they are called linear mobility and saturation mobility, respectively. The linear mobility is expressed by the following equation (3), and the saturation mobility is expressed by the following equation (4). as follows.

[0236]

Equation

[0237] [Number]

[0238] In this specification and the like, the curves calculated from Formula (3) and Formula (4) are referred to as mobility curves. FIG. 15 shows the mobility curves calculated from the analytical formula of the drain current based on GCA. In FIG. 15, the Id-Vg characteristics at Vd = 10V when GCA is effective and the mobility curves of the linear mobility and the saturation mobility are shown superimposed, respectively.

[0239] In FIG. 15, the Id-Vg characteristics are calculated from the analytical formula of the drain current based on GCA. The shape of the mobility curve serves as a clue for understanding the internal state of the transistor.

[0240] As an example, FIG. 16 shows the Id-Vg characteristics of an FET using CAAC-OS in actual measurement. In FIG. 16, the Id-Vg characteristics of the FET, the saturation mobility, and the mobility curves of the linear mobility are explicitly arranged side by side. Note that an oxide semiconductor (IGZO) film is used for the semiconductor layer of the FET, and the composition thereof is In:Ga:Zn = 1:1:1 [atomic ratio]. Also, the mobility curves of the saturation mobility and the linear mobility are both calculated from the Id-Vg characteristics at Vd = 10V.

[0241] As shown in FIG. 16, when the shape of the FET follows GCA, the curve of the saturation mobility becomes a plateau in the saturation region and has a shape that gradually decreases in the linear region.

[0242] <1-11. Fabrication of Transistor for Characteristic Evaluation> ​​Next, the structure of the transistor according to one aspect of the present invention will be described, and then the results of fabricating the transistor and evaluating the electrical characteristics of the transistor will be explained.

[0243] [Configuration Example 1 of Transistor] FIG. 17(A) is a top view of the transistor 100A, and FIG. 17(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 17(A). FIG. 17(C) is a cross-sectional view taken along the dashed line Y1- Y2 in FIG. 17(A). In FIG. 17(A), for clarity, components such as the insulating film 110 are omitted from the illustration. In the top view of the transistor, in subsequent drawings as well, similar to FIG. 17(A), some of the components may be omitted from the illustration. Also, the direction of the dashed line X1-X2 is sometimes referred to as the channel length (L) direction, and the direction of the dashed line Y1-Y2 is sometimes referred to as the channel width (W) direction.

[0244] The transistor 100A shown in FIGS. 17(A), (B), and (C) includes a conductive film 10 6 on the substrate 102, an insulating film 104 on the conductive film 106, an oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, a conductive film 112 on the insulating film 110, an insulating film 10 4, an oxide semiconductor film 108, and an insulating film 116 on the conductive film 112. The oxide semiconductor film 108 has a channel region 108i that overlaps the conductive film 112, a source region 108s that contacts the insulating film 116, and a drain region 108d that contacts the insulating film 116. .

[0245] Further, the insulating film 116 contains nitrogen or hydrogen. When the insulating film 116 contacts the source region 108 s and the drain region 108d, nitrogen or hydrogen in the insulating film 116 diffuses into the source ​​- It is added into the source region 108s and the drain region 108d. The source region 108s and the drain region 108d have a higher carrier density by adding nitrogen or hydrogen.

[0246] Also, the transistor 100A may have an insulating film 118 on the insulating film 116, and a conductive film 120a electrically connected to the source region 108s through an opening 141a provided in the insulating films 116 and 118, and a conductive film 120b electrically connected to the drain region 108d through an opening 141b provided in the insulating films 116 and 118. Further, an insulating film 122 may be provided on the insulating film 118, the conductive film 120a, and the conductive film 120b. Note that in FIGS. 17(B) and (C), a configuration in which the insulating film 122 is provided

[0247] is illustrated, but it is not limited thereto, and a configuration in which the insulating film 122 is not provided may also be used. In this specification and the like, the insulating film 104 may be referred to as the first insulating film, the insulating film 110 may be referred to as the second insulating film, the insulating film 116 may be referred to as the third insulating film, the insulating film 118 may be referred to as the fourth insulating film, and the insulating film 122 may be

[0248] referred to as the fifth insulating film, respectively. Further, the insulating film 104 has a function as the first gate insulating film, and the insulating film 110 has a function as the second gate insulating film. Also, the insulating films 116 and 118 have a function as Since it can be filled, a highly reliable semiconductor device can be provided.

[0249] In addition, in order to supply excess oxygen into the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 10 8. In this case, the excess oxygen contained in the insulating film 10 4 can also be supplied to the source region 108s and the drain region 10 8d of the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and the drain region 108d , the resistance of the source region 108s and the drain region 108d may increase.

[0250] On the other hand, by configuring the insulating film 110 formed above the oxide semiconductor film 108 to have excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 10 8d, by selectively increasing the carrier density of the source region 108s and the drain region 108d, it is possible to suppress the increase in the resistance of the source region 108s and the drain region 108d.

[0251] In addition, the source region 108s and the drain region 108d of the oxide semiconductor film 108 preferably each have an element that forms an oxygen deficiency or an element that binds to the oxygen deficiency. Typical examples of the element that forms the oxygen deficiency or the element that binds to the oxygen deficiency include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, noble gases, etc. There is xenon or the like. One or more elements that form the oxygen deficiency are included in the insulating film 116. When included, it diffuses from the insulating film 116 into the source region 108s and the drain region 108d. And / or, the element that forms the oxygen deficiency is added into the source region 108s and the drain region 108d by an impurity addition process.

[0252] When an impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and an oxygen deficiency is formed. Or, when an impurity element is added to the oxide semiconductor film, the oxygen that was bonded to the metal element in the oxide semiconductor film bonds with the impurity element, oxygen is desorbed from the metal element, and an oxygen deficiency is formed. As a result, the carrier density in the oxide semiconductor film increases and the conductivity becomes higher.

[0253] Also, the conductive film 106 has a function as a first gate electrode, the conductive film 112 has a function as a second gate electrode, the conductive film 120a has a function as a source electrode, and the conductive film 120b has a function as a drain electrode.

[0254] Also, as shown in FIG. 17(C), openings 143 are provided in the insulating films 104 and 110. Also, the conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. Note that different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. Also, the conductive film 106 may be used as a light-shielding film without providing the opening 143. For example, by forming the conductive film 106 with a light-shielding material, the light from below that irradiates the channel region 108i can be suppressed. ​

[0255] Further, as shown in FIGS. 17(B) and (C), the oxide semiconductor film 108 is located so as to face each of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode, and is sandwiched between the conductive films that function as the two gate electrodes. Also, the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire oxide semiconductor film 108 in the channel width direction is covered with the conductive film 112 with the insulating film 110 interposed therebetween. Further, since the conductive film 112 and the conductive film 106 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, one side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 interposed therebetween. That is to say, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 112 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween.

[0256] By having such a configuration, the oxide semiconductor film 108 included in the transistor 100A can be electrically surrounded by the electric fields of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. As in the case of the transistor 100A, a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by the electric fields of the first gate electrode and the second gate electrode is a Surro Also, the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire oxide semiconductor film 108 in the channel width direction is covered with the conductive film 112 with the insulating film 110 interposed therebetween. Further, since the conductive film 112 and the conductive film 106 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, one side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 interposed therebetween. Also, the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire oxide semiconductor film 108 in the channel width direction is covered with the conductive film 112 with the insulating film 110 interposed therebetween. Further, since the conductive film 112 and the conductive film 106 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, one side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 interposed therebetween. 104, and the opening 143 provided in the insulating film 110, one side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 interposed therebetween. 104, and the opening 143 provided in the insulating film 110, one side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 interposed therebetween. That is to say, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 112 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween.

[0257] That is to say, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 112 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween. 104, and the opening 143 provided in the insulating film 110, and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween. 104, and the opening 143 provided in the insulating film 110, and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween. That is to say, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 112 are connected at the insulating film 104 and the opening 143 provided in the insulating film 110, and surround the oxide semiconductor film 108 with the insulating film 104 and the insulating film 110 interposed therebetween.

[0258] By having such a configuration, the oxide semiconductor film 10 included in the transistor 100A 8 can be electrically surrounded by the electric fields of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. As in the case of the transistor 100A, a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by the electric fields of the first gate electrode and the second gate electrode is a Surro 8 can be electrically surrounded by the electric fields of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. As in the case of the transistor 100A, a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by the electric fields of the first gate electrode and the second gate electrode is a Surro 8 can be electrically surrounded by the electric fields of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. As in the case of the transistor 100A, a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by the electric fields of the first gate electrode and the second gate electrode is a Surro rounded transistor device structure It can be called an unded channel (S-channel) structure. Note that the transistor 100A can also be called a Dual Gate structure in terms of the number of gate electrodes. .

[0259] Since the transistor 100A has an S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 106 or the conductive film 112. Therefore, the current driving ability of the transistor 100A is improved, and high on current characteristics can be obtained. Also, since it is possible to increase the on-current, the transistor 100A can be miniaturized. Further, since the transistor 100A has a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100A can be increased. In addition, in the channel width direction of the transistor 100A, an opening different from the opening 143 may be formed on the side where the opening 143 of the oxide semiconductor film 108 is not formed.

[0260]

[0261] Note that the transistor 100A may be referred to as a TGSA (Top Gate Self Alig ned) type FET based on the position of the conductive film 112 with respect to the oxide semiconductor film 108 or the formation method of the conductive film 112. However, the semiconductor device according to one aspect of the present invention is not limited to this, and may be a BGTC (Bottom Gate Top Contact) type FET.

[0262] [Fabrication of Transistor] Next, a transistor corresponding to the transistor 100A described above is fabricated, and the The electrical characteristics of the transistor were evaluated. In the present embodiment, samples S1A to S1C shown below were fabricated. Samples S1A to S1C are samples in which a transistor with a channel length L of 2 μm and a channel width W of 3 μm is formed. Here, sample S1A has the composite oxide semiconductor shown in FIG. 4 as the oxide semiconductor film 108, sample S1B has the composite oxide semiconductor shown in FIG. 5 as the oxide semiconductor film 108, and sample S1C is assumed to have the composite oxide semiconductor shown in FIG. 6 as the oxide semiconductor film 108. Here, sample S1A has the composite oxide semiconductor shown in FIG. 4 as the oxide semiconductor film 108, sample S1B has the composite oxide semiconductor shown in FIG. 5 as the oxide semiconductor film 108, and sample S1C is assumed to have the composite oxide semiconductor shown in FIG. 6 as the oxide semiconductor film 108. Here, sample S1A has the composite oxide semiconductor shown in FIG. 4 as the oxide semiconductor film 108, sample S1B has the composite oxide semiconductor shown in FIG. 5 as the oxide semiconductor film 108, and sample S1C is assumed to have the composite oxide semiconductor shown in FIG. 6 as the oxide semiconductor film 108. Here, sample S1A has the composite oxide semiconductor shown in FIG. 4 as the oxide semiconductor film 108, sample S1B has the composite oxide semiconductor shown in FIG. 5 as the oxide semiconductor film 108, and sample S1C is assumed to have the composite oxide semiconductor shown in FIG. 6 as the oxide semiconductor film 108. Here, sample S1A has the composite oxide semiconductor shown in FIG. 4 as the oxide semiconductor film 108, sample S1B has the composite oxide semiconductor shown in FIG. 5 as the oxide semiconductor film 108, and sample S1C is assumed to have the composite oxide semiconductor shown in FIG. 6 as the oxide semiconductor film 108.

[0263] [Fabrication method of samples S1A to S1C] First, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by photolithography. First, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by photolithography. First, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by photolithography.

[0264] Next, four insulating films were laminated and formed on the substrate and the conductive film. The insulating films were continuously formed in a vacuum using a plasma-enhanced chemical vapor deposition (PECVD) apparatus. The insulating films used were a 50-nm-thick silicon nitride film, a 300-nm-thick silicon nitride film, a 50-nm-thick silicon nitride film, and a 50-nm-thick silicon oxynitride film from the bottom up, respectively. Next, four insulating films were laminated and formed on the substrate and the conductive film. The insulating films were continuously formed in a vacuum using a plasma-enhanced chemical vapor deposition (PECVD) apparatus. The insulating films used were a 50-nm-thick silicon nitride film, a 300-nm-thick silicon nitride film, a 50-nm-thick silicon nitride film, and a 50-nm-thick silicon oxynitride film from the bottom up, respectively. Next, four insulating films were laminated and formed on the substrate and the conductive film. The insulating films were continuously formed in a vacuum using a plasma-enhanced chemical vapor deposition (PECVD) apparatus. The insulating films used were a 50-nm-thick silicon nitride film, a 300-nm-thick silicon nitride film, a 50-nm-thick silicon nitride film, and a 50-nm-thick silicon oxynitride film from the bottom up, respectively. Next, four insulating films were laminated and formed on the substrate and the conductive film. The insulating films were continuously formed in a vacuum using a plasma-enhanced chemical vapor deposition (PECVD) apparatus. The insulating films used were a 50-nm-thick silicon nitride film, a 300-nm-thick silicon nitride film, a 50-nm-thick silicon nitride film, and a 50-nm-thick silicon oxynitride film from the bottom up, respectively.

[0265] Next, an oxide semiconductor film was formed on the insulating film, and the oxide semiconductor film was processed into an island shape to form a semiconductor layer. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was formed. The oxide semiconductor film is the composite oxide semiconductor described above or C / IGZO. Next, an oxide semiconductor film was formed on the insulating film, and the oxide semiconductor film was processed into an island shape to form a semiconductor layer. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was formed. The oxide semiconductor film is the composite oxide semiconductor described above or C / IGZO. Next, an oxide semiconductor film was formed on the insulating film, and the oxide semiconductor film was processed into an island shape to form a semiconductor layer. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was formed. The oxide semiconductor film is the composite oxide semiconductor described above or C / IGZO. Next, an oxide semiconductor film was formed on the insulating film, and the oxide semiconductor film was processed into an island shape to form a semiconductor layer. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was formed. The oxide semiconductor film is the composite oxide semiconductor described above or C / IGZO.

[0266] As the film formation conditions of the oxide semiconductor film of sample S1A, the substrate temperature was set to room temperature (25 °C). Argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm were introduced into the chamber of the sputtering device, the pressure was set to 0.6 Pa, and an alternating current power of 2.5 kw was applied to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) having indium, gallium, and zinc to form it. In sample S1A, the oxygen flow ratio during the film formation of the oxide semiconductor film was 10%.

[0267] Next, an insulating film was formed on the insulating film and the oxide semiconductor layer. As the insulating film, a silicon oxynitride film with a thickness of 15 0 nm was formed using a PECVD device.

[0268] Next, heat treatment was performed. The heat treatment was carried out at 3 50 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen.

[0269] Next, an opening was formed in a desired region of the insulating film. As a method for forming the opening, a dry etching method was used.

[0270] Next, an oxide semiconductor film with a thickness of 100 nm was formed on the insulating film so as to cover the opening, and the oxide semiconductor film was processed into an island shape to form a conductive film. Also, after forming the conductive film, subsequently, an insulating film was formed by processing the insulating film in contact with the lower side of the conductive film.

[0271] As the conductive film, an oxide semiconductor film with a thickness of 10 nm, a titanium nitride film with a thickness of 50 nm, and a copper film with a thickness of 100 nm were sequentially formed. The film formation conditions for the oxide semiconductor film were such that the substrate temperature was 170 °C, oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering device, the pressure was set to 0.6 Pa, and indium, gallium, and zinc were used as the metal ​​​​​​A 2.5 kW alternating current was applied to an oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) to form it. Also, the titanium nitride film and the copper film were formed using a sputtering device. Next, plasma treatment was performed on the oxide semiconductor film, the insulating film, and the conductive film. As the plasma treatment, a PECVD device was used, the substrate temperature was set to 220 °C, and it was performed in a mixed gas atmosphere of argon gas and nitrogen gas. Next, an insulating film was formed on the oxide semiconductor film, the insulating film, and the conductive film. As the insulating film, a 100 nm thick silicon nitride film and a 300 nm thick silicon oxynitride film were laminated and formed using a PECVD device.

[0272] Next, a mask was formed on the formed insulating film, and an opening was formed in the insulating film using the mask. Next, a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape to form a conductive film serving as a source electrode and a drain electrode. As the conductive film, a 10 nm thick titanium film and a 100 nm thick copper film were respectively formed using a sputtering device. Next, an insulating film was formed on the insulating film and the conductive film. As the insulating film, an acrylic-based photosensitive resin with a thickness of 1.5 μm was used.

[0273] In the above manner, sample S1A was fabricated. Sample S1B was fabricated using the same method as sample S1A except for the film formation conditions of the oxide semiconductor film.

[0274]

[0275]

[0276]

[0277]

[0278] ​​​​​​​​​​​It was fabricated. As the film formation conditions of the oxide semiconductor film of Sample S1B, the substrate temperature was room temperature (25 °C) and argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber of the sputtering apparatus, the pressure was set to 0.6 Pa, and indium, gallium and zinc were applied with 2.5 kW of AC power to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic number ratio]) to form it. In Sample S1B, the oxygen flow rate ratio during the film formation of the oxide semiconductor film was 50%.

[0279] Sample S1C was also fabricated in the same manner as Sample S1A except for the film formation conditions of the oxide semiconductor film. As the film formation conditions of the oxide semiconductor film of Sample S1C, the substrate temperature was room temperature (25 °C) and oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering apparatus, the pressure was set to 0.6 Pa, and indium, gallium, and zinc were applied with 2.5 kW of AC power to a metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic number ratio]) to form it. In Sample S1C, the oxygen flow rate ratio during the film formation of the oxide semiconductor film was 10 0%.

[0280] [Id-Vg Characteristics of Transistor] Next, the Id-Vg characteristics of the transistors of Samples S1A to S1C fabricated above were measured. As the measurement conditions of the Id-Vg characteristics of the transistors, the voltage applied to the conductive film functioning as the first gate electrode (hereinafter also referred to as the gate voltage (Vg)), and the voltage applied to the conductive film functioning as the second gate electrode (hereinafter also referred to as the back gate voltage (Vbg)) were applied in steps of 0.25 V from -10 V to +10 V. Also, the source voltage ​​​​​​​​The voltage applied to the conductive film functioning as a source (hereinafter also referred to as the source voltage (Vs)) is set to 0 V( comm), and the voltage applied to the conductive film functioning as a drain electrode (hereinafter also referred to as the drain voltage (Vd)) is set to 0.1 V and 20 V.

[0281] The Id-Vg characteristic results of sample S1A are shown in FIG. 1, the Id-Vg characteristic results of sample S1B are shown in FIG. 2, and the Id-Vg characteristic results of sample S1C are shown in FIG. 3. In FIGS. 1 to 3, the first vertical axis represents Id (A), the second vertical axis represents the field-effect mobility (μFE (cm 2 / Vs)), and the horizontal axis represents Vg (V). The field-effect mobility is the value measured at Vd = 20 V.

[0282] As shown in FIG. 1, the transistor, which is a semiconductor device according to one aspect of the present invention, has good electrical characteristics. Here, the characteristics of the transistor shown in FIG. 1 are shown in Table 2.

[0283]

Table 2

[0284] As shown in Table 2, sample S1A has a first region where the maximum value of the field-effect mobility is 40 cm / Vs or more and less than 150 cm 2 / Vs in the range where the gate voltage of the transistor is greater than 0 V and 10 V 2 or less, a second region where the threshold voltage is -1 V or more and 1 V or less, a third region where the S value is less than 0.3 V / decade, and a fourth region where the off-current is less than 1×10 A / -12 A / cm 2 / cm ​Represented as E(max), the value of the field-effect mobility when the gate voltage of the transistor is 2V is μF When represented as E(Vg = 2V), μFE(max) / μFE(Vg = 2V) is 1 or more and less than 1.5.

[0285] As shown in FIG. 2, the transistor, which is a semiconductor device according to an aspect of the present invention, has good electrical characteristics. Here, the characteristics of the transistor shown in FIG. 2 are shown in Table 3. As shown in Table 3, for sample S1B, the maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0V and 10V or less is 40 cm

[0286] [Table 3]

[0287] / Vs or more and less than 150 cm / Vs, a first region where the threshold voltage is -1V or more and 1V or less, a second region where the S value is less than 0.3 V / decade, and an off-current of 1 × 10 2 A / 2 less than cm 2 , and has a fourth region. Represented as μFE(max) for the maximum value of the field-effect mobility of the transistor, and when the value of the field-effect mobility when the gate voltage of the transistor is 2V is represented as μFE(Vg = 2V), μFE(max) / μFE(Vg = 2V) is 1.5 or more and less than 3. -12 A / cm 2 E(Vg = 2V), when μFE(max) / μFE(Vg = 2V) is 1.5 or more and less than 3.

[0288] As shown in FIG. 3, the transistor, which is a semiconductor device according to an aspect of the present invention, has good electrical characteristics. Here, the characteristics of the transistor shown in FIG. 3 are shown in Table 4. As shown in Table 4, for sample S1B, the maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0V and 10V or less is 40 cm

[0289] [Table 4]

[0290] As shown in Table 4, for sample S1C, the maximum value of the field-effect mobility in the following range where the gate voltage of the transistor is greater than 0 V and less than 10 V is 10 cm 2 / Vs or more and less than 100 cm 2 / Vs, a first region that is satisfied, a second region where the threshold voltage is -1 V or more and 1 V or less, and an S value is less than 0.3 V / decade, a third region where the off-current is 1×10 -12 A / cm 2 less than, and a fourth region. Represent the maximum value of the field-effect mobility of the transistor as μF E(max), and represent the value of the field-effect mobility when the gate voltage of the transistor is 2 V as μF E(Vg = 2V). When expressed in this way, μFE(max) / μFE(Vg = 2V) is 3 or more and less than 10.

[0291] The characteristics of the above transistor can be obtained by using the composite oxide semiconductor described above, or C / IGZ O. By using the composite oxide semiconductor or C / IGZO for the semiconductor layer of the transistor, it is possible to simultaneously have both the function of high carrier mobility and the function of good switching characteristics.

[0292] <1-12. Evaluation of the Shape of the Mobility Curve by Device Simulation> Next, device simulation was performed on the shape of the mobility curve of the field-effect mobility of the transistor shown in FIG. 1, and the shape of the mobility curve was considered from various aspects.

[0293] In device simulation, as factors determining the shape of the mobility curve, 1. The temperature dependence of mobility, 2. The donor density distribution in the channel region, 3. Shallow in the oxide semiconductor film Three factors of the defect level density (also referred to as sDOS) were assumed.

[0294] [1. Temperature dependence of mobility] In a transistor using an oxide semiconductor film, the field-effect mobility rapidly increases due to self-heating. The temperature dependence of the electron mobility (μ n ) of the oxide semiconductor film is expressed by the following mathematical formula (5). It is as follows.

[0295] [Equation]

[0296] In Equation (5), μ n 300 represents the electron mobility of the oxide semiconductor film at room temperature, and T L represents the lattice temperature, respectively. As shown in Equation (5), the field-effect mobility of the transistor using the oxide semiconductor film increases in proportion to approximately the 1.5th power of the temperature T. It rises in proportion to approximately the 1.5th power of the temperature T.

[0297] [2. Donor density distribution in the channel region] Next, the effective channel length of the transistors from sample S1A to sample S1C will be described with reference to FIG. 18. It will be described with reference to FIG. 18.

[0298] FIG. 18 is a schematic diagram for explaining the concept of the effective channel length of a transistor.

[0299] In FIG. 18, GE represents the gate electrode, GI represents the gate insulating film, and OS represents the oxide semiconductor film , respectively. Also, an n-type region is formed in the oxide semiconductor film. The effective channel length (L eff ) of the transistor is expressed by the following Equation (6).

[0300] [Equation]

[0301] In formula (6), L g represents the gate length, and ΔL represents the reduction amount of the channel length, respectively. .

[0302] Note that the effective channel length of the transistor can be obtained, for example, from TLM (Transmission Line Model) analysis.

[0303] In the following description, based on the above-described effective channel length, a model is assumed in which the donor density gradually decreases from the n-type region to the channel region. That is, the donors decrease according to a Gaussian distribution toward the channel region. Schematic diagrams for explaining the donor density in the channel region are shown in FIGS. 19(A), (B), and (C).

[0304] Here, FIG. 19(A) is a diagram for explaining the donor density of sample S1A, FIG. 19(B) is a diagram for explaining the donor density of sample S1B, and FIG. 19(C) is a diagram for explaining the donor density of sample S1C.

[0305] In FIGS. 19(A), (B), and (C), GE represents the gate electrode, GI represents the gate insulating film, and O S represents the oxide semiconductor film, respectively. Further, in the oxide semiconductor films shown in FIGS. 19(A), (B), and (C), the region where the donor density is 5×10 is represented in gray, and the region where the donor density is 1×10 18 cm -3 or less is represented in black. 16 cm -3

[0306] From the results shown in FIGS. 19(A), (B), and (C), the effective channel of the transistor shown in FIG. 19(A) The channel length is estimated to be 2.0 μm, and the effective channel length of the transistor shown in Fig. 19(B) is estimated to be 1.2 μm, and the effective channel length of the transistor shown in Fig. 19(C) is 0.8 μm. In other words, the ΔL of the transistor in Fig. 19(A) is estimated to be 0 μm, the ΔL of the transistor in Fig. 19(B) is estimated to be 0.4 μm, and the ΔL of the transistor in Fig. 19(C) is estimated to be 0.6 μm.

[0307] [3. Density of Shallow Defect Levels in Oxide Semiconductor Film] Next, the density of shallow defect levels (also referred to as sDOS) in the oxide semiconductor film will be described. The sDOS of the oxide semiconductor film can be estimated from the electrical characteristics of the transistor using the oxide semiconductor film. Hereinafter, the density of interface states of the transistor will be evaluated, and in addition to the density of the interface states, the number of electrons N trapped in the interface states will be considered, and a method for predicting the subthreshold leakage current will be described. trap

[0308] The number of electrons N trap trapped in the interface states can be evaluated, for example, by comparing the measured drain current -gate voltage (Id-Vg) of the transistor with the calculated value of the drain current-gate voltage (Id-Vg) characteristics.

[0309] Fig. 20 shows the ideal Id-Vg characteristics obtained by calculation and the measured Id-Vg characteristics in the transistor at a source voltage Vs = 0 V and a drain voltage Vd = 0.1 V. Note that among the measurement results of the transistor, only values of 1×10 0 A or more, for which the measurement of the drain current Id is easy, are plotted. -13

[0310] Compared with the ideal Id-Vg characteristics obtained by calculation, the measured Id-Vg characteristics show a gradual change in the drain current Id with respect to the gate voltage V g. This is considered to be due to electrons being trapped in shallow interface levels located near the energy of the lower end of the conduction band ( denoted as Ec). Here, by considering the number of electrons N trapped in the shallow interface levels (per unit area and per unit energy) using the Fermi distribution function, the density N trap of the interface levels can be estimated more accurately. of the interface levels can be estimated more accurately. it First, the method for evaluating the number of electrons N

[0311] trapped in the interface trap levels will be explained using the schematic Id-Vg characteristics shown in Fig. 21. The dashed line represents the ideal Id-Vg characteristics without trap levels obtained by calculation. Also, in the dashed line, the change in the gate voltage Vg when the drain current changes from Id1 trap to Id2 is denoted as ΔV . Also, the solid line represents the measured Id-Vg characteristics. In the solid line, the change in the gate voltage Vg when the drain current changes from Id1 to Id2 id is denoted as ΔV . The potentials at the interface of interest when the drain current is Id1 and Id2 are denoted as φ respectively, and the change amount is denoted as Δφ ex . it1 it2 it ex id ex id In Fig. 21, since the measured slope is smaller than the calculated slope, it can be seen that ΔV

[0312] is always larger than ΔV ex . At this time, the difference between ΔV id and ΔV is due to electrons being trapped in the shallow interface levels. ex id ​​Represents the potential difference required for trapping. Therefore, the change in charge due to the trapped electrons amount ΔQ trap can be expressed by the following equation (7).

[0313]

Equation

[0314] C tg is the combined capacitance of the insulator and the semiconductor per unit area. Also, ΔQ trap is the number of electrons N trapped (per unit area and per unit energy), and can also be expressed by Equation (8) trap using q, where q is the elementary charge.

[0315]

Equation

[0316] Equation (9) can be obtained by simultaneously solving Equation (7) and Equation (8).

[0317]

Equation

[0318] Next, by taking the limit of zero for Δφ in Equation (9) it Equation (10) can be obtained.

[0319]

Equation

[0320] That is, using the ideal Id-Vg characteristics, the measured Id-Vg characteristics, and Equation (10), the number of electrons N trapped at the interface can be estimated. Note that the drain current trap ​​​Regarding the relationship of the potential at the interface with the current, it can be obtained by the above-described calculation using the device simulator. It can be obtained by the above-described calculation using the device simulator.

[0321] Also, the number of electrons N per unit area and per unit energy trap and the density N of the interface level it are in the relationship as shown in Equation (11).

[0322]

Equation

[0323] Here, f(E) is the Fermi distribution function. By fitting the N obtained from Equation (10) to Equation trap with Equation (11), N it is determined. By using the device simulator with this N it set, it is possible to obtain transfer characteristics including Id < 0.1 pA. It is possible to obtain transfer characteristics including Id < 0.1 pA. It is possible.

[0324] Next, applying Equation (10) to the measured Id-Vg characteristics shown in Figure 20 and extracting N trap results are shown as white circles in Figure 22. Here, the vertical axis in Figure 22 is the Fermi energy Ef from the lower end Ec of the conduction band of the semiconductor. Looking at the dashed line, there is a maximum value just below Ec. results are shown as white circles in Figure 22. Here, the vertical axis in Figure 22 is the Fermi energy Ef from the lower end Ec of the conduction band of the semiconductor. Looking at the dashed line, there is a maximum value just below Ec. Looking at the dashed line, there is a maximum value just below Ec. Assuming the tail distribution of Equation (12) as N it in Equation (11), it can be very well fitted to N as shown by the dashed line in Figure 22, and as fitting parameters, the peak value N trap ta ta ta = 1.67×10 13 cm -2 eV -1 and the characteristic width W ta = 0.105 eV are obtained. are obtained.

[0325]

Number

[0326] Next, the fitting curve of the obtained interface level is fed back to the calculation using a device simulator, and the result of inverse calculation of the Id-Vg characteristics is shown in Fig. 23. Fig. 2 3(A) shows the Id-Vg characteristics obtained by calculation when the drain voltage Vd is 0.1 V and 1.8 V, and the measured Id-Vg characteristics in the transistor when the drain voltage Vd is 0.1 V and 1.8 V. Fig. 23(B) is a graph with the drain current Id in Fig. 23(A) as the logarithm. 3(A) shows the Id-Vg characteristics obtained by calculation when the drain voltage Vd is 0.1 V and 1.8 V, and the measured Id-Vg characteristics in the transistor when the drain voltage Vd is 0.1 V and 1.8 V. Fig. 23(B) is a graph with the drain current Id in Fig. 23(A) as the logarithm. Id-Vg characteristics, and the measured Id-Vg characteristics in the transistor when the drain voltage Vd is 0.1 V and 1.8 V. Also, Fig. 23(B) is a graph with the drain current Id in Fig. 23(A) as the logarithm. It can be seen that the calculated curve and the plot of the measured values almost coincide, indicating high reproducibility between the calculated values and the measured values. Therefore, it can be seen that the above method is sufficiently reasonable as a method for calculating the density of shallow defect levels.

[0327] It can be seen that the calculated curve and the plot of the measured values almost coincide, indicating high reproducibility between the calculated values and the measured values. Therefore, it can be seen that the above method is sufficiently reasonable as a method for calculating the density of shallow defect levels. It can be seen that the calculated curve and the plot of the measured values almost coincide, indicating high reproducibility between the calculated values and the measured values. Therefore, it can be seen that the above method is sufficiently reasonable as a method for calculating the density of shallow defect levels. It can be seen that the calculated curve and the plot of the measured values almost coincide, indicating high reproducibility between the calculated values and the measured values. Therefore, it can be seen that the above method is sufficiently reasonable as a method for calculating the density of shallow defect levels.

[0328] [4. Calculation Results of Mobility Curve] The sDOS in the above-described oxide semiconductor film affects the mobility curve of the field-effect mobility. In particular, near the threshold voltage, electrons are trapped by the sDOS and the shape of the mobility curve changes. The sDOS in the oxide semiconductor film is represented by the product of N ta and W ta and t OS in Equation (12). Therefore, based on Equation (12) described above, the mobility curve was calculated. The parameters used in the calculation are shown in Table 5. in Equation (12). Therefore, based on Equation (12) described above, the mobility curve was calculated. The parameters used in the calculation are shown in Table 5. The parameters used in the calculation are shown in Table 5.

[0329]

Table 5

[0330] In addition, in this embodiment, the mobility curves when the value of W ta is changed were calculated W ta . The shape of the mobility curve when the value of W is changed is shown in FIG. 24. In FIG. 24 , N ta = 2.5×10 19 cm -3 eV -1 is set, and ΔL = 0 is set. Also, W ta is set to 0 .015 eV, 0.02 eV, 0.025 eV, 0.03 eV, 0.035 eV, 0.0 4 eV, and 0.045 eV under seven conditions.

[0331] As shown in FIG. 24, it can be seen that the smaller the value of Wta, that is, the narrower the energy width of sDOS, the steeper the rise of the mobility curve. Also, it can be seen that the narrower the energy width of sDOS, the more the peak value of the mobility curve shifts from the high Vg side to the low Vg side, and the peak value decreases.

[0332] [5. Influence of Diffusion Current on Mobility Curve] Next, the influence of the diffusion current on the mobility curve will be described. The drain current of the FET is represented by the following mathematical formula (13).

[0333]

Equation

[0334] As shown in mathematical formula (13), the drain current is the sum of the drift current component and the diffusion current component . In mathematical formula (13), the first term represents the drift current and the second term represents the diffusion current . Also, a conceptual diagram explaining the contributions of the diffusion current and the drift current components in the Id-Vg characteristics is shown in FIG. 25.

[0335] Next, the influence of the diffusion current component on the mobility curve (saturation) was estimated by device simulation. As the FET, a Dual-Gate structure was assumed, where the active layer is an oxide semiconductor, the source region and the drain region are n+ regions, and the channel region is intrinsic. The calculation conditions are shown in Table 6. Note that the interface between the GI and the active layer and trap levels ( for example, sDOS) in the active layer are not assumed.

Table 6

[0336]

[0337] Fig. 26 shows the Id-Vg characteristics and the saturation mobility curve obtained by simulation. In Fig. 26, the Id-Vg characteristics and the saturation mobility curve are shown superimposed. As shown in Fig. 26, the mobility curve shows a peak near Vth of the Id-Vg characteristics.

[0338] Next, a schematic diagram of the band diagram in the film thickness direction of the FET with a Dual Gate structure is shown in Fig. 27.

[0339] As can be seen from Fig. 27, due to the gate electric field, the band is relatively linear in the film thickness direction of the semiconductor, and current flows through the entire semiconductor film. In the FET with such a Dual Gate structure, the drain current in the subthreshold region is expressed by the following formula (14).

[0340]

Equation

[0341] In formula (14), k is the Boltzmann constant, T is the temperature, and n i is the intrinsic carrier Let the density be \(t\). s Let \(t\) be the film thickness of the active layer, and \(\Delta\varphi\) be the difference between the true Fermi level and the work function of the gate. These are represented respectively. Equation (14) means that the diffusion current is proportional to the difference between the diffusion current density at the end of the source region and the diffusion current density at the end of the drain region.

[0342] Substituting Equation (14) into the definition of the saturation mobility, Equation (15) can be obtained.

[0343]

Equation

[0344] Equation (15) shows a behavior with a peak near \(V_{th}\). That is, the peak near \(V_{th}\) in the saturation mobility curve seen in an ideal simulation without assuming any trap levels in sDOS is considered to be due to the diffusion current flowing through the entire active layer. However, in the mobility curve of an actual IGZO - FET, such a sharp peak near \(V_{th}\) is not observed. By assuming that there are shallow electron trap levels (i.e., sDOS) in the OS film or at the interface between the OS film and the gate insulating film, the shape of the measured mobility curve can be approximated. Figure 28 shows the device simulation results when sDOS is assumed in the OS film.

[0345] However, in the actual mobility curve of the IGZO - FET, such a sharp peak near \(V_{th}\) is not observed. This is because by assuming that there are shallow electron trap levels (i.e., sDOS) in the OS film or at the interface between the OS film and the gate insulating film, the shape of the measured mobility curve can be approximated. Figure 28 shows the device simulation results when sDOS is assumed in the OS film. This sharp peak near \(V_{th}\) is not observed. By assuming that there are shallow electron trap levels (i.e., sDOS) in the OS film or at the interface between the OS film and the gate insulating film, the shape of the measured mobility curve can be approximated. Figure 28 shows the device simulation results when sDOS is assumed in the OS film. That is, by assuming that there are shallow electron trap levels (i.e., sDOS) in the OS film or at the interface between the OS film and the gate insulating film, the shape of the measured mobility curve can be approximated. Figure 28 shows the device simulation results when sDOS is assumed in the OS film. As shown in Figure 28, it is suggested that sDOS in the OS film affects the mobility curve. The amount of sDOS in the OS film increases as the film thickness of the OS increases. Therefore, as the film thickness of the OS increases, the field - effect mobility decreases. Figure 29 shows the field - effect mobility of the FET.

[0346] As shown in Figure 28, it is suggested that sDOS in the OS film affects the mobility curve. The amount of sDOS in the OS film increases as the film thickness of the OS increases. Therefore, as the film thickness of the OS increases, the field - effect mobility decreases. Figure 29 shows the field - effect mobility of the FET. As shown in Figure 28, it is suggested that sDOS in the OS film affects the mobility curve. The amount of sDOS in the OS film increases as the film thickness of the OS increases. Therefore, as the film thickness of the OS increases, the field - effect mobility decreases. Figure 29 shows the field - effect mobility of the FET. ​​​​Fig. showing the relationship between the degree (maximum value) and the OS film thickness is presented.

[0347] In Fig. 29, the vertical axis represents the field-effect mobility (maximum value), and the horizontal axis represents the OS film thickness. Also, in Fig. 29, the results of four types of transistors with different channel lengths (L = 2 μm, 3 μm, 6 μm, and 10 μm) are superimposed and shown respectively. As shown in Fig. 2 9, it can be seen that as the OS film thickness increases, the field-effect mobility decreases.

[0348] In addition, the saturation mobility curves calculated by changing the distribution of sDOS are shown in Figs. 30(A) and (B). Fig. 30(A) represents the distribution of sDOS in the OS film, and Fig. 30(B) represents the shape of the mobility curve. As shown by the arrows in Figs. 30(A) and (B), it is suggested that the shape of the saturation mobility curve changes depending on the amount of energy levels of sDOS or the distribution of sDOS.

[0349] [6. Influence of Parasitic Resistance in Source Region and Drain Region] Next, the influence of the parasitic resistance in the source region and drain region (also referred to as the SD region) of the TGSA-type OS-FET will be explained. One of the characteristics of the TGSA-type OS-FET is that there are source regions and drain regions with reduced resistance in the active layer on both sides of the channel region. The source region and drain region sometimes act as parasitic resistances in FET characteristics. In this case, when the TGSA-type OS-FET is drawn as a circuit diagram, it can be shown as in Fig. 31(A). In the case of the circuit diagram shown in Fig. 31(A), as shown in Equation (16), Vd is divided into the voltage across the two parasitic resistances and the voltage across the FET.

[0350]

[0351] [Number]

[0352] In the mathematical formula (16), R is the parasitic resistance, and V FET is the potential difference applied across both ends of the FET channel. In the GCA formula, considering the region above V =Vg - Vth as the linear region, when there is a parasitic resistance as shown in Fig. 31(A), the Vg at which the linear region is formed, that is, the V FET =Vg - Vth, becomes smaller than that in the case without a parasitic resistance. As shown in Fig. 15, the saturation mobility decreases when entering the linear region. Considering this, it can be thought that the larger the resistance value of the parasitic resistance, the smaller the Vg at the lower limit of the linear region. Therefore, by device simulation, the relationship between the electric field effect mobility and Vg was obtained by changing the sizes of the source region and the drain region. The device simulation FET results are shown in Fig. 31(B). As shown in Fig. 31(B), as the source region and the drain region with a lower resistance active layer become larger and the parasitic resistance becomes larger, the Vg at the lower limit of the linear region, that is, the Vg at which the saturation mobility curve begins to decrease, becomes smaller, which is confirmed.

[0353] [7. Influence of Self-Heating] Next, the influence of the self-heating of the FET will be explained. The FET generates heat when current flows. Also, the larger the current amount, the larger the heat generation amount. This is obvious from Joule's law. Also, in the FET, the larger Vg is, the larger the current amount increases, and from Joule's law, the larger Vg is, the larger the self-heating of the FET becomes.

[0354]

[0355] ​​​​​​​​​ According to the GCA approximation described above, the drain current in the saturation region is, as shown in Equation (2), (Vg - Vth) 2 proportional to. Therefore, when the square root of the drain current is plotted, it becomes a straight line in the saturation region. The saturation mobility is obtained by calculating the slope of this straight line part by differentiation and converting it to mobility by normalizing with the channel length, channel width, and gate capacitance.

[0356] The GCA approximation formula does not contain an explicit temperature variable, and the saturation mobility does not seem to depend on temperature. However, in an OS-FET, some of the parameters included in the GCA approximation have temperature dependence. Therefore, due to the influence of the self-heating of the FET, the shape of the saturation mobility curve changes.

[0357] The first parameter that changes depending on temperature is the temperature dependence of the electron mobility of IGZO. The electron mobility of IGZO improves as the temperature rises. That is, if the amount of current flowing through the FET increases and the temperature of the FET rises, the electron mobility of IGZO increases. Therefore, under the condition that Vg or Vd is high, when the FET becomes hot due to self-heating, the electron mobility increases and the drain current increases. As a result, the slope of the √Id-Vg characteristic in the saturation region increases, showing a behavior where the saturation mobility increases. The influence of the self-heating of the FET was evaluated by device simulation. The device simulation results are shown in Fig. 32. Fig. 32 shows the calculation results of the Id-Vg characteristics and the saturation mobility curve of the TGSA-type CAAC-OS-FET.

[0358] The influence of the self-heating of the FET is particularly significant in the TGSA type. The reason is that the BGTC type This is because, compared with the FET of [[ID=]], the TGSA type FET has a structure that makes it difficult to dissipate heat.

[0359] In the BGTC type FET, the source electrode and the drain electrode are near the channel region which is the heat generation location, and it has excellent heat dissipation performance. On the other hand, in the TGSA type FET, the electrodes that serve as the heat dissipation path are far from the channel region, so the heat dissipation performance is poor. As a result, in the TGSA type FET, the temperature of the FET tends to become high due to self-heating, and the influence of self-heating appears easily in the mobility curve.

[0360] The second parameter that changes depending on the temperature is the number of carrier electrons. Cox(Vg - Vth) represents the number of electrons per unit area accumulated in the gate capacitance. However, when there are electron traps, some of these accumulated electrons are trapped, so the number of carrier electrons decreases accordingly. As described above, since the OS has an electron trap called sDOS, a part of the electrons accumulated in the gate capacitance does not act as carriers.

[0361] Since the level of sDOS is lower than the lower end of the conduction band, considering the Boltzmann distribution, the higher the temperature, the larger the ratio of carrier electrons to trapped electrons. As described above, the higher Vg is, the higher the temperature of the FET rises. Therefore, the larger Vg is, the larger the ratio of carrier electrons becomes. Thus, the saturation mobility also shows a behavior of increasing as Vg increases.

[0362] Using device simulation, considering sDOS and assuming that the electron mobility of CAAC-OS does not depend on temperature, regarding the temperature dependence of the saturation mobility of the FET, ​​​​​​Calculations were performed. The calculation results are shown in FIG. 33. As shown in FIG. 33, when there is no temperature dependence, even when there is temperature dependence, as Vg increases, an increase in mobility is clearly observed.

[0363] [8. Influence of Reduction in Effective Channel Length] The channel length of the CAAC-OS FET is the distance between the source electrode and the drain electrode in the BGTC type FET, and the length of the gate electrode in the TGSA type FET. However, in actual FET characteristics, the distance between the n+ regions of the source region and the drain region becomes the effective channel length. Depending on the process conditions, the n+ region and the channel region may not be separated at the gate electrode end, and the n+ region may progress in the channel direction beyond the gate electrode end. In this case , since the effective channel length becomes shorter, it brings about an effect of seemingly improving the field-effect mobility. FIG. 34 shows the relationship between the field-effect mobility and Vg. In FIG. 34, the vertical axis represents the field-effect mobility and the horizontal axis represents Vg, respectively.

[0364] Assuming the previous explanations, the shapes of the saturation mobility curves of three types of TGSA type OS-FETs can be obtained. FIGS. 35(A)(B)(C) show the calculation results of the saturation mobility of the TGSA type OS-FET. Here, FIG. 35(A) corresponds to sample S1A, FIG. 35(B) corresponds to sample S1B and FIG. 35(C) corresponds to sample S1C. As shown in FIGS. 35(A)(B)(C), it can be seen that by setting the parameter of sDOS to an appropriate value, saturation mobility curves of various shapes can be obtained. In the semiconductor

[0365] device corresponding to sample S1A, since the shape of the saturation mobility curve is as shown in FIG. 35(A), the sDOS ​​It is suggested that the value is low. Similarly, in the semiconductor device corresponding to the sample S1B, since the shape of the saturation mobility curve is as shown in FIG. 35(B ), it is suggested that the value of sDOS is low. Also, in the semiconductor device corresponding to the sample S1C, the shape of the saturation mobility curve is as shown in FIG. 35(C).

[0366] Here, using the Id-Vg characteristics of the transistor shown in FIG. 1, the value of sDOS of the oxide semiconductor film of the sample S1A was measured. As a result of the measurement, the sDOS of the oxide semiconductor film of the sample S1A was 6.4×10 -12 cm -2 . Thus, the oxide semiconductor film of one aspect of the present invention has a region where the value of sDOS is small, in other words, the density of shallow defect levels is less than 1.0×10 -12 cm -2 .

[0367] ... Also, using the Id-Vg characteristics of the transistor shown in FIG. 2, the value of sDOS of the oxide semiconductor film of the sample S1B was measured. As a result of the measurement, the sDOS of the oxide semiconductor film of the sample S1B was 1.7×10 -12 cm -2 . Thus, the oxide semiconductor film of one aspect of the present invention has a region where the value of sDOS is small, in other words, the density of shallow defect levels is 1.0×10 -12 cm - 2 or more and less than 2.0×10 -12 cm -2 .

[0368] Also, using the Id-Vg characteristics of the transistor shown in FIG. 3, the value of sDOS of the oxide semiconductor film of the sample S1C was measured. As a result of the measurement, the sDOS of the oxide semiconductor film of the sample S1C was 2.4×10 -12 cm-2 was. Thus, the oxide semiconductor film of one aspect of the present invention has a region where the value of sDOS is small, in other words, the density of shallow defect levels is 2.0×10 -12 cm - 2 or more and less than 3.0×10 -12 cm -2 below.

[0369] <1-13. Components of the Transistor> Next, the details of the components of the transistor shown in FIGS. 17(A), (B), and (C) will be described. will be described.

[0370] [Substrate] As the substrate 102, a material having heat resistance enough to withstand heat treatment during the manufacturing process can be used. can be used.

[0371] Specifically, alkali-free glass, soda-lime glass, alkali glass, crystal glass, quartz, or sapphire can be used. Also, an inorganic insulating film may be used. Examples of the inorganic insulating film include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and the like.

[0372] Also, as the alkali-free glass, for example, a thickness of 0.2 mm or more and 0.7 mm or less may be used. Alternatively, the alkali-free glass may be polished to have the above thickness.

[0373] Also, as the alkali-free glass, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation (2950 mm × 3400 mm), etc. A large glass substrate can be used. Thereby, a large-sized display device can be manufactured. It is possible.

[0374] Further, as the substrate 102, a single-crystalline semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. may be used. .

[0375] Further, as the substrate 102, an inorganic material such as metal may be used. Examples of the inorganic material such as metal include stainless steel or aluminum.

[0376] Further, as the substrate 102, an organic material such as resin, resin film or plastic may be used. Examples of the resin film include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or a resin having a siloxane bond. etc. may be mentioned. Further, as the substrate 102, a composite material combining an inorganic material and an organic material may be used. Examples of the composite material include a material obtained by laminating a metal plate or a thin glass plate and a resin film, fibrous metal, particulate metal, fibrous glass, or a material in which particulate glass is dispersed in a resin film, or a material in which fibrous resin or particulate resin is dispersed in an inorganic material. etc. may be mentioned.

[0377] Further, as the substrate 102, a composite material combining an inorganic material and an organic material may be used. Examples of the composite material include a material obtained by laminating a metal plate or a thin glass plate and a resin film, fibrous metal, particulate metal, fibrous glass, or a material in which particulate glass is dispersed in a resin film, or a material in which fibrous resin or particulate resin is dispersed in an inorganic material. Examples of the composite material include a material obtained by laminating a metal plate or a thin glass plate and a resin film, fibrous metal, particulate metal, fibrous glass, or a material in which particulate glass is dispersed in a resin film, or a material in which fibrous resin or particulate resin is dispersed in an inorganic material. Examples of the composite material include a material obtained by laminating a metal plate or a thin glass plate and a resin film, fibrous metal, particulate metal, fibrous glass, or a material in which particulate glass is dispersed in a resin film, or a material in which fibrous resin or particulate resin is dispersed in an inorganic material. etc. may be mentioned.

[0378] Note that as the substrate 102, at least a film or layer formed on the upper or lower side can be supported. It suffices as long as it is any one or more of an insulating film, a semiconductor film, and a conductive film .

[0379] [First Insulating Film] As the insulating film 104, it can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition ( PLD) method, a printing method, a coating method, or the like. Further, as the insulating film 104 , for example, an oxide insulating film or a nitride insulating film can be formed by a single layer or a laminate . In addition, in order to improve the interface characteristics with the oxide semiconductor film 108, at least the region of the insulating film 104 in contact with the oxide semiconductor film 108 is preferably formed of an oxide insulating film . Further, an oxide insulating film that releases oxygen by heating can be used as the insulating film 104 , and it is possible to move the oxygen contained in the insulating film 104 to the oxide semiconductor film 108 by heat treatment .

[0380] The thickness of the insulating film 104 can be 50 nm or more, or 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By increasing the thickness of the insulating film 104 , it is possible to increase the oxygen release amount of the insulating film 104, and to reduce the interface levels at the interface between the insulating film 104 and the oxide semiconductor film 108, as well as the oxygen deficiency contained in the channel region 1 08i of the oxide semiconductor film 108 .

[0381] As the insulating film 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, nitride silicon, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide etc. can be used, and it can be provided in a single layer or a laminate. In the present embodiment, the insulating film As 104, a stacked structure of a silicon nitride film and a silicon oxynitride film is used. In this way the insulating film 104 is formed in a stacked structure, with a silicon nitride film used on the lower layer side and a silicon oxynitride film used on the upper layer side, so that oxygen can be efficiently introduced into the oxide semiconductor film 108. It is possible.

[0382] [Oxide semiconductor film] As the oxide semiconductor film 108, it is preferable to use the composite oxide semiconductor or C / IGZO described above.

[0383] [Second insulating film] The insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly to the channel region 108i. For example, as the insulating film 110, a single layer or a stack of an oxide insulating film or a nitride insulating film can be formed. In addition, in order to improve the interface characteristics with the oxide semiconductor film 108, in the insulating film 110, the region in contact with the oxide semiconductor film 108 is preferably formed using at least an oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, etc. can be used.

[0384] Also, the thickness of the insulating film 110 can be 5 nm or more and 400 nm or less, or 5 nm or more and 300 n m or less, or 10 nm or more and 250 nm or less.

[0385] Also, the insulating film 110 preferably has few defects. Typically, the signal observed by the electron spin resonance method (ESR: Electron Spin Resonance) is preferably less. For example, as the above-mentioned signal, a g value of 2.001 is observed The E’ center can be mentioned. The E’ center is caused by the dangling bonds of silicon. For the insulating film 110, the spin density caused by the E’ center is 3×10 17 spi ns / cm 3 or less, preferably 5×10 16 spins / cm 3 or less of a silicon oxide film or a silicon oxynitride film may be used.

[0386] In addition, signals caused by nitrogen dioxide (NO2) may be observed in the insulating film 110 in addition to the above-mentioned signals. The signal is split into three signals by the nuclear spin of N, and the g value of each is 2.037 or more and 2.039 or less (referred to as the first signal) , the g value is 2.001 or more and 2.003 or less (referred to as the second signal), and the g value is 1.96 4 or more and 1.966 or less (referred to as the third signal).

[0387] For example, it is preferable to use an insulating film in which the spin density caused by nitrogen dioxide (NO2) is 1×10 1 7 spins / cm 3 or more and 1×10 18 spins / cm 3 less than.

[0388] Note that nitrogen oxides (NO x ) containing nitrogen dioxide (NO2) form energy levels in the insulating film 110. The energy levels are located within the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxides (NOx) diffuse to the interface between the insulating film 110 and the oxide semiconductor film 108, the energy levels may trap electrons on the insulating film 110 side. As a result, the trap The trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108. Therefore, the insulating film 11 When a film containing a small amount of nitrogen oxide is used, the threshold voltage of the transistor is The shift can be reduced.

[0389] Nitrogen oxides (NO x ) is released in a small amount, for example, a silicon oxynitride film. The silicon oxynitride film can be analyzed by thermal desorption spectroscopy (TDS). Thermal Desorption Spectroscopy (DSS) revealed that nitrogen oxides (NO x ) is a membrane that releases more ammonia than water, and typically Output is 1 x 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The above is as follows. The amount of ammonia released is determined by the temperature of the heat treatment in TDS being between 50°C and 650°C, or The total amount is in the range of 50°C to 550°C.

[0390] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating film that releases a large amount of monoxide, x ) is reduced.

[0391] When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6×10 20 ato ms / cm 3 It is preferable that the following is true:

[0392] The insulating film 110 is made of hafnium silicate (HfSiO x ), nitrogen is added doped hafnium silicate (HfSi x O y N z ), hafnium aluminate (HfAl with nitrogen added (HfAl x O y N z ), or other high-k materials such as hafnium oxide may be used. Using such high-k materials can reduce the gate leakage of transistors.

[0393] [Third Insulating Film] The insulating film 116 contains nitrogen or hydrogen. Also, the insulating film 116 may contain fluorine. Examples of the insulating film 116 include nitride insulating films. The nitride insulating film can be formed using, for example, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon nitride fluoride, fluorosilicon nitride, etc. The hydrogen concentration contained in the insulating film 116 is preferably 1×10 atoms / cm 22 or more. Also, the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Therefore, 3 the concentration of impurities (nitrogen or hydrogen) in the source region 108s and the drain region 108d in contact with the insulating film 116 increases, and the carrier density of the source region 108s and the drain region 108d can be increased. (nitrogen or hydrogen) can be increased, and the carrier density of the source region 108s and the drain region 108d can be increased.

[0394] [Fourth Insulating Film] As the insulating film 118, an oxide insulating film can be used. Also, as the insulating film 118, a laminated film of an oxide insulating film and a nitride insulating film can be used. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, You may use hafnium oxide, gallium oxide, Ga-Zn oxide, or the like.

[0395] Further, the insulating film 118 is preferably a film that functions as a barrier film against hydrogen, water, etc. from the outside. It is preferable.

[0396] The thickness of the insulating film 118 can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. It can be.

[0397] [Fifth Insulating Film] The insulating film 122 may be insulating and can be formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, etc. Examples of the organic material include photosensitive resin materials such as acrylic resin or polyimide resin. As the inorganic material, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, etc. may be mentioned. As the organic material, photosensitive resin materials such as acrylic resin or polyimide resin may be mentioned. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, etc. Examples of the organic material include photosensitive resin materials such as acrylic resin or polyimide resin. Examples of the organic material include photosensitive resin materials such as acrylic resin or polyimide resin. It may be mentioned.

[0398] [Conductive Film] The conductive films 106, 112, 120a, and 120b can be formed using sputtering, vacuum evaporation, pulsed laser deposition (PLD), thermal CVD, or the like. Further, as the conductive films 106, 112, 120a, and 120b, a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used. As the conductive films 106, 112, 120a, and 120b, a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used. As the conductive films 106, 112, 120a, and 120b, a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used. As the conductive films 106, 112, 120a, and 120b, a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used. It may be.

[0399] As the conductive metal film, a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese can be used. Alternatively, an alloy containing the above-mentioned metal elements may be used. As the conductive metal film, a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese can be used. Alternatively, an alloy containing the above-mentioned metal elements may be used. As the conductive metal film, a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese can be used. Alternatively, an alloy containing the above-mentioned metal elements may be used. It may be.

[0400] As the above-mentioned metal film having conductivity, specifically, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a titanium nitride film, a two-layer structure in which a copper film is laminated on a tantalum nitride film, a three-layer structure in which a copper film is laminated on a titanium film and a titanium film is further formed thereon, etc. may be used. In particular, by using a conductive film containing a copper element, the resistance can be lowered, which is preferable. Further, examples of the conductive film containing a copper element include an alloy film containing copper and manganese. Since the alloy film can be processed by a wet etching method, it is preferable.

[0401] Note that as the conductive films 106, 112, 120a, and 120b, it is preferable to use a tantalum nitride film. The tantalum nitride film has conductivity and high barrier properties against copper or hydrogen. Further, since the tantalum nitride film emits little hydrogen from itself, it can be most preferably used as the metal film in contact with the oxide semiconductor film 108 or the metal film near the oxide semiconductor film 108.

[0402] Also, as the above-mentioned conductive film having conductivity, a conductive polymer or a conductive polymer may be used.

[0403] Also, as the above-mentioned conductive film having a function of reflecting visible light, a material containing a metal element selected from gold, silver, copper, or palladium can be used. In particular, by using a conductive film containing a silver element, the reflectance in visible light can be increased, which is preferable.

[0404] Also, as the above-mentioned conductive film having a function of transmitting visible light, indium, tin, zinc, Materials containing elements selected from gallium or silicon can be used. Specifically include indium oxide, zinc oxide, indium-tin oxide (also referred to as ITO), indium-tin-silicon oxide (also referred to as ITSO), indium-zinc oxide, indium-gallium-zinc oxide, etc. can be mentioned.

[0405] In addition, as the conductive film having the function of transmitting the above-mentioned visible light, a film containing graphene or grapheme ite may be used. As the film containing graphene, a film containing graphene oxide is formed, and by reducing the film containing graphene oxide, a film containing graphene can be formed. Examples of the reduction method include a method of applying heat and a method of using a reducing agent. can be mentioned.

[0406] In addition, the conductive films 112, 120a, and 120b can be formed by electroless plating. Examples of the materials that can be formed by the electroless plating method include any one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd. In particular, using Cu or Ag can reduce the resistance of the conductive film, which is preferable. Therefore, it is suitable.

[0407] In addition, when the conductive film is formed by the electroless plating method, a diffusion prevention film may be formed under the conductive film so that the constituent elements of the conductive film do not diffuse to the outside. Also, a seed layer on which the conductive film can grow may be formed between the diffusion prevention film and the conductive film. As the diffusion prevention film, for example, it can be formed using a sputtering method. In addition, as the diffusion prevention film, for example, a tantalum nitride film or a titanium nitride film can be used. can be used. In addition, as the diffusion prevention film, for example, a tantalum nitride film or a titanium nitride film can be used. It is possible. Further, the seed layer can be formed by electroless plating. Further, as the seed layer, a material similar to that of a conductive film that can be formed by electroless plating can be used.

[0408] Note that, as the conductive film 112, an oxide semiconductor typified by In-Ga-Zn oxide can be used. When nitrogen or hydrogen is supplied to the oxide semiconductor from the insulating film 116, the carrier density increases. In other words, the oxide semiconductor functions as an oxide conductor (OC: Oxide Conductor). Therefore, the oxide semiconductor can be used as a gate electrode.

[0409] For example, as the conductive film 112, a single-layer structure of an oxide conductor (OC), a single-layer structure of a metal film, or a laminated structure of an oxide conductor (OC) and a metal film can be mentioned.

[0410] Note that when a single-layer structure of a metal film having light-shielding properties or a laminated structure of an oxide conductor (OC) and a metal film having light-shielding properties is used as the conductive film 112, it is preferable because the channel region 108i formed below the conductive film 112 can be shielded from light. Further, when a laminated structure of an oxide semiconductor or an oxide conductor (OC) and a metal film having light-shielding properties is used as the conductive film 112, by forming a metal film (for example, a titanium film, a tungsten film, etc.) on the oxide semiconductor or the oxide conductor (OC), the constituent elements in the metal film diffuse to the oxide semiconductor or the oxide conductor (OC) side and the resistance is reduced, the resistance is reduced due to damage during film formation of the metal film (for example, sputtering damage, etc.), or the oxide semiconductor is present in the metal film. Alternatively, oxygen in the oxide conductor (OC) diffuses to form oxygen vacancies and reduce the resistance. It becomes.

[0411] The thicknesses of the conductive films 106, 112, 120a, and 120b can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

[0412] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. It can be implemented in combination.

[0413] (Embodiment 2) In this embodiment, a transistor having a different aspect from the transistor shown in Embodiment 1 will be described with reference to FIGS. 36 to 51. It will be described with reference to FIGS. 36 to 51.

[0414] <2-1. Configuration Example 2 of Transistor> FIGS. 36(A) and 36(B) are cross-sectional views of the transistor 100B, and FIGS. 37(A) and 37(B) are cross-sectional views of the transistor 100C, and FIGS. 38(A) and 38(B) are cross-sectional views of the transistor 100D. Note that the top views of the transistor 100B, the transistor 100C, and the transistor 100D are the same as those of the transistor 100A shown in FIG. 17(A), so the description here is omitted. Therefore, the description here is omitted.

[0415] The transistor 100B shown in FIGS. 36(A) and 36(B) has a laminated structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110 that are different from those of the transistor 100A.

[0416] The conductive film 112 of the transistor 100B has a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. For example, as the conductive film 112_1, an acid By using an oxide conductive film, excess oxygen can be added to the insulating film 110. The above As the oxide conductive film, it can be formed by a sputtering method in an atmosphere containing oxygen gas Moreover, examples of the oxide conductive film include an oxide having indium and tin, an oxide having tungsten and indium, an oxide having tungsten, indium, and zinc, an oxide having titanium and indium, an oxide having titanium, indium, and tin, an oxide having indium and zinc, an oxide having silicon, indium, and tin, an oxide having indium, gallium, and zinc, etc.

[0417] Also, as shown in FIG. 36(B), in the opening 143, the conductive film 112_2 and the conductive film 106 are connected. When forming the opening 143, after forming the conductive film that becomes the conductive film 112_1, by forming the opening 143, the shape shown in FIG. 36(B) can be obtained. When an oxide conductive film is applied to the conductive film 112_1, by configuring the conductive film 112_2 and the conductive film 106 to be connected, the contact resistance between the conductive film 112 and the conductive film 106 can be lowered.

[0418] Also, the conductive film 112 and the insulating film 110 of the transistor 100B are in a tapered shape. More specifically, the lower end portion of the conductive film 112 is formed outside the upper end portion of the conductive film 112. Also, the lower end portion of the insulating film 110 is formed outside the upper end portion of the insulating film 110. Also, the lower end portion of the conductive film 112 is formed at approximately the same position as the upper end portion of the insulating film 110.

[0419] By forming the conductive film 112 and the insulating film 110 of the transistor 100B in a tapered shape, ​​​​​​​​​​​​Compared with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular, it is preferable because the covering property of the insulating film 1 16 can be enhanced.

[0420] Note that other configurations of the transistor 100B are the same as those of the transistor 100A shown above and exhibit the same effects.

[0421] The transistor 100C shown in FIGS. 37(A) and (B) differs from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.

[0422] The conductive film 112 of the transistor 100C has a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. Also, the lower end portion of the conductive film 112_1 is formed outside the upper end portion of the conductive film 112_2. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with the same mask, and the conductive film 112_2 is wet etched, and the conductive film 112_1 and the insulating film 110 are dry-etched, respectively to obtain the above structure.

[0423] Also, by adopting the structure of the transistor 100C, a region 1 08f may be formed in the oxide semiconductor film 108. The region 108f is formed between the channel region 108i and the source region 1 08s, and between the channel region 108i and the drain region 108d.

[0424] The region 108f functions as either a high-resistance region or a low-resistance region. The high-resistance region has the same resistance as the channel region 108i and is a region where the conductive film 112 functioning as a gate electrode does not overlap. When the region 108f is a high-resistance region, the region 108f functions as an offset region. When region 108f functions as an offset region , in order to suppress the decrease in the on-current of transistor 100C, the channel length (L ) in the direction may be set to 1 μm or less for region 108f.

[0425] Further, the low-resistance region has a lower resistance than the channel region 108i and a higher resistance than the source region 10 8s and the drain region 108d. When region 108f is a low-resistance region , region 108f functions as a so-called LDD (Lightly Doped Drain) region . When region 108f functions as an LDD region, the electric field in the drain region can be relaxed, so that the variation in the threshold voltage of the transistor due to the electric field in the drain region can be reduced.

[0426] When region 108f is an LDD region, for example, one or more of nitrogen, hydrogen, and fluorine are supplied from the insulating film 116 to region 10 8f, or an impurity element is added from above the conductive film 112_1 using the insulating film 110 and the conductive film 11 2_1 as a mask, so that the impurity passes through the conductive film 112_1 and the insulating film 110 and is added to the oxide semiconductor film 108 to form it.

[0427] Further, as shown in FIG. 37(B), in the opening 143, the conductive film 112_2 and the conductive film 106 are connected.

[0428] The other configurations of transistor 100C are the same as those of transistor 100A shown above and have the same effects.

[0429] The transistor 100D shown in FIGS. 38(A) and (B) has a laminated structure of a conductive film 112, a shape of the conductive film 112, and a shape of the insulating film 110 different from those of the transistor 100A.

[0430] The conductive film 112 of the transistor 100D has a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. Also, the lower end portion of the conductive film 112_1 is formed outside the lower end portion of the conductive film 112_2. Further, the lower end portion of the insulating film 110 is formed outside the lower end portion of the conductive film 112_1. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with the same mask, and the conductive film 112_2 and the conductive film 112_1 are wet-etched, and the insulating film 110 is dry-etched, respectively, to obtain the above structure.

[0431] Also, similar to the transistor 100C, a region 108f may be formed in the oxide semiconductor film 1 08 in the transistor 100D. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d formed.

[0432] Also, as shown in FIG. 38(B), in the opening 143, the conductive film 112_2 and the conductive film 106 are connected.

[0433] Note that the other configurations of the transistor 100D are the same as those of the transistor 100A shown above and exhibit the same effects.

[0434] <2-2. Configuration Example 3 of Transistor>

[0435] FIG. 39(A)(B) is a cross-sectional view of transistor 100E, and FIG. 40(A)(B) is , a cross-sectional view of transistor 100F, and FIG. 41(A)(B) is a cross-sectional view of transistor 100G . FIG. 42(A)(B) is a cross-sectional view of transistor 100H, and FIG. 43 (A)(B) is a cross-sectional view of transistor 100J. Note that the top views of transistor 100E, transistor 100F, transistor 100G, transistor 100H, and transistor 100J are the same as those of transistor 100A shown in FIG. 17(A), so the description here is omitted.

[0436] Transistor 100E, transistor 100F, transistor 100G, transistor 100H, and transistor 100J have a different structure of the oxide semiconductor film 108 from that of transistor 100A shown above. For other configurations, they are the same as those of transistor 100A shown above and have the same effects.

[0437] The oxide semiconductor film 108 of transistor 100E shown in FIG. 39(A)(B) has an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. Also, the channel region 108i, the source region 108s, and the drain region 108d are each a three-layer stacked structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.

[0438] The oxide semiconductor film 108 of transistor 100F shown in FIG. 40(A)(B) has an oxide semiconductor film 108_2 on the insulating film 104 and an oxide semiconductor film on the oxide semiconductor film 108_2​​ It has the body film 108_3. Also, the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 1 08_3.

[0439] The oxide semiconductor film 108 of the transistor 100G shown in FIGS. 41(A) and (B) has the oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_2 on the oxide semiconductor film 108_1. Also, the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 1 08_2. the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 1 08_2.

[0440] The oxide semiconductor film 108 of the transistor 100H shown in FIGS. 42(A) and (B) has the oxide semiconductor film 108_1 on the insulating film 104, the oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and the oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. Also, the channel region 108i has a three-layer stacked structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108 _2, and the oxide semiconductor film 108_3, and the source region 108s and the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2. Note that in the cross-section of the transistor 100H in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2. and the drain region 108d each have a two-layer stacked structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2. The channel width (W) of the transistor 100H In the cross-section in the direction, the oxide semiconductor film 108_3 covers the side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

[0441] The oxide semiconductor film 108 of the transistor 100J shown in FIGS. 43(A) and (B) has the insulating It has an oxide semiconductor film 108_2 on the edge film 104 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. Further, the channel region 108i has a two-layer stacked structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3, and the source region 108s and the drain region 108d each have a single-layer structure of the oxide semiconductor film 108_2. In the cross-section of the transistor 100J in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2. In the vicinity of or on the side surface of the channel region 108i in the channel width (W) direction, defects (for example, oxygen deficiency) are likely to be formed due to damage during processing, or contamination is likely to occur due to the adhesion of impurities. Therefore, even if the channel region 108i is substantially intrinsic, when stress such as an electric field is applied, the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof is activated and likely to become a low-resistance (n-type) region. Also, when the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof is an n-type region, since the n-type region becomes a carrier path, a parasitic channel may be formed. Therefore, in the transistor 100H and the transistor 100J, the channel region 108i has a stacked structure, and the side surface of the channel region 108i in the channel width (W) direction is covered with one layer of the stacked structure. By adopting such a configuration, it is possible to suppress defects in the side surface of the channel region 108i or the vicinity thereof, or to reduce the adhesion of impurities to the side surface of the channel region 108i or the vicinity thereof.

[0442]

[0443]

[0444] [Band structure] Here, the band structures of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110, the band structures of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110, and the band structures of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and the insulating film 110 will be described with reference to FIGS. 44(A), (B), and (C). Note that FIGS. 44(A), (B), and (C) show the band structures in the channel region 108i.

[0445] FIG. 44(A) is an example of the band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110. Further, FIG. 44(B) is an example of the band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110. Further, FIG. 44(C) is an example of the band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and the insulating film 110. Note that the band structures show the energy levels (Ec) of the lower ends of the conduction bands of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110 for easy understanding.

[0446] Further, in FIG. 44(A), a silicon oxide film is used as the insulating films 104 and 110, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn = 1:3:2 of metal elements is used as the oxide semiconductor film 108_1, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1 of metal elements is used as the oxide semiconductor film 108_2, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1 of metal elements is used as the oxide semiconductor film 108_3. ​​​​​​​​​​​​​​​​ Oxide formed using a metal oxide target with a numerical ratio of In:Ga:Zn=1:3:2 FIG. 1 is a band diagram of a configuration using a semiconductor film.

[0447] FIG. 44(B) shows a case where silicon oxide films are used as the insulating films 104 and 110, and oxide semiconductor films are used as the insulating films 104 and 110. The conductor film 108_2 is made of a metal having an atomic ratio of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108_3 is formed using an oxide semiconductor film formed using an oxide target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 was used. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed by

[0448] FIG. 44(C) shows a case where silicon oxide films are used as the insulating films 104 and 110, and oxide semiconductor films are used as the insulating films 104 and 110. The metal oxide film 108_1 has an atomic ratio of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using a metal target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed by

[0449] As shown in FIG. 44A, in the oxide semiconductor films 108_1, 108_2, and 108_3, The energy level at the bottom of the conduction band changes gradually as shown in Figure 44(B). As shown, the energy level of the conduction band minimum in the oxide semiconductor films 108_2 and 108_3 is As shown in FIG. 44C, the oxide semiconductor films 108_1 and 1 In O8_2, the energy level at the bottom of the conduction band changes smoothly. It can be said that the band structure changes continuously or is a continuous junction. For this purpose, it is assumed that there are no impurities that form defect energy levels such as trap centers or recombination centers at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. At the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3, it is assumed that there are no impurities that form defect energy levels such as trap centers or recombination centers. It is assumed that there are no impurities that form defect energy levels such as trap centers or recombination centers.

[0450] In order to form a continuous junction in the oxide semiconductor films 108_1, 108_2, and 108_3, it is necessary to use a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber to continuously stack each film without exposing it to the atmosphere. By using a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber, it is necessary to continuously stack each film without exposing it to the atmosphere. By using a multi-chamber film-forming apparatus (sputtering apparatus) equipped with a load lock chamber, it is necessary to continuously stack each film without exposing it to the atmosphere.

[0451] By adopting the configuration shown in FIGS. 44(A), (B), and (C), the oxide semiconductor film 108_2 becomes a well (pit), and it can be seen that in the transistor using the above stacking structure, the channel region is formed in the oxide semiconductor film 108_2. In the transistor using the above stacking structure, it can be seen that the channel region is formed in the oxide semiconductor film 108_2. In the transistor using the above stacking structure, it can be seen that the channel region is formed in the oxide semiconductor film 108_2.

[0452] Note that by providing the oxide semiconductor films 108_1 and 108_3, defect energy levels can be moved away from the oxide semiconductor film 108_2. Note that by providing the oxide semiconductor films 108_1 and 108_3, defect energy levels can be moved away from the oxide semiconductor film 108_2.

[0453] In addition, the defect energy level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 that functions as the channel region, and electrons may easily accumulate in the defect energy level. When electrons accumulate in the defect energy level, it becomes a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable to adopt a configuration such that the defect energy level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. By doing so, it becomes difficult for electrons to accumulate in the defect energy level, and it is possible to increase the on-current of the transistor and the field-effect mobility. In addition, the defect energy level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 that functions as the channel region, and electrons may easily accumulate in the defect energy level. When electrons accumulate in the defect energy level, it becomes a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. When electrons accumulate in the defect energy level, it becomes a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable to adopt a configuration such that the defect energy level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. Therefore, it is preferable to adopt a configuration such that the defect energy level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. By doing so, it becomes difficult for electrons to accumulate in the defect energy level, and it is possible to increase the on-current of the transistor and the field-effect mobility. can be enhanced.

[0454] In addition, the oxide semiconductor films 108_1 and 108_3 have a conduction band lower energy level closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the difference between the conduction band lower energy level of the oxide semiconductor film 108_2 and the conduction band lower energy levels of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less. That is, the electron affinity of the oxide semiconductor film 108_2 is greater than that of the oxide semiconductor films 108_1 and 108_3, and the difference between the electron affinities of the oxide semiconductor films 108_1 and 108_3 and the oxide semiconductor film 108_2 is 0.15 eV or more, or 0.5 eV or more and 2 eV or less,

[0455] By having such a configuration, the oxide semiconductor film 108_2 becomes the main current path. That is, the oxide semiconductor film 108_2 has a function as a channel region, and the oxide semiconductor films 108_1 and 108_3 have a function as an oxide insulating film. In addition, it is preferable to use an oxide semiconductor film composed of one or more of the metal elements constituting the oxide semiconductor film 108_2 in which the channel region is formed. With such a configuration, at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3, interface scattering is less likely to occur. Therefore, carrier movement is not inhibited at the interface, and

[0456] the field-effect mobility of the transistor is increased.In addition, the oxide semiconductor films 108_1 and 108_3 function as part of the channel region. To prevent this, a material with a sufficiently low conductivity is used. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be called oxide insulating films in terms of their physical properties and / or functions. Or, materials are used for the oxide semiconductor films 108_1 and 108_3 that have an electron affinity (the difference between the vacuum level and the energy level at the lower end of the conduction band) smaller than that of the oxide semiconductor film 108_2, and the energy level at the lower end of the conduction band has a difference (band offset) from the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. In addition, to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, it is preferable to use a material in which the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is closer to the vacuum level than the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. For example, the difference between the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2 and the energy levels at the lower end of the conduction bands of the oxide semiconductor films 108_1 and 108_3 is preferably 0.2 eV or more, more preferably 0.5 eV or more.

[0457]

[0457] In addition, it is preferable that the oxide semiconductor films 108_1 and 108_3 do not contain a spinel-type crystal structure in the film. When the oxide semiconductor films 108_1 and 108_3 contain a spinel-type crystal structure in the film, the constituent elements of the conductive films 120a and 120b may diffuse into the oxide semiconductor film 108_2 at the interface between the spinel-type crystal structure and other regions. When the oxide semiconductor films 108_1 and 108_3 are CAAC-OS described later, it is preferable that the blocking property of the constituent elements of the conductive films 120a and 120b, for example, the copper element, is increased.

[0458] Also, in the present embodiment, as the oxide semiconductor films 108_1 and 108_3, a metal oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:3:2 was exemplified, but the present invention is not limited thereto. For example, as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn = 1:1:1 [atomic ratio , In:Ga:Zn = 1:1:1.2 [atomic ratio], In:Ga:Zn = 1:3:4 atomic ratio], In:Ga:Zn = 1:3:6 [atomic ratio], In:Ga:Zn = 1:4: 5 [atomic ratio], In:Ga:Zn = 1:5:6 [atomic ratio], or an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In:Ga:Zn = 1:10:1 [atomic ratio] may be used. Alternatively, as the oxide semiconductor films 108_1 and 108_3, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of Ga:Zn = 10:1 may be used. In this case, as the oxide semiconductor film 108_2, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1 is used, and as the oxide semiconductor films 108_1 and 108_3, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of Ga:Z n = 10:1 is used. Then, the difference between the energy level of the lower end of the conduction band of the oxide semiconductor film 108_2 and the energy level of the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 can be made 0.6 eV or more, which is preferable. Note that, as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn = 1:1:1 is used. As the oxide semiconductor film 108_2, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1 is used, and as the oxide semiconductor films 108_1 and 108_3, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of Ga:Z n = 10:1 is used. Then, the difference between the energy level of the lower end of the conduction band of the oxide semiconductor film 108_2 and the energy level of the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 can be made 0.6 eV or more, which is preferable. n = 10:1 is used. Then, the difference between the energy level of the lower end of the conduction band of the oxide semiconductor film 108_2 and the energy level of the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 can be made 0.6 eV or more, which is preferable. 108_3 can be made 0.6 eV or more, which is preferable. Therefore, it is suitable.

[0459] Note that, as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn = 1:1:1 When using a metal oxide target with an [atomic ratio], the oxide semiconductor films 108_1 and 108 _3 may have a case where In:Ga:Zn = 1:β1 (0 < β1 ≤ 2):β2 (0 < β2 ≤ 2). Also, as the oxide semiconductor films 108_1 and 108_3, when using a metal oxide target with an atomic ratio of In:Ga:Zn = 1 :3:4, the oxide semiconductor films 108_1 and 108_3 may have a case where In:Ga:Zn = 1:β3 (1 ≤ β3 ≤ 5):β4 (2 ≤ β4 ≤ 6). Also, as the oxide semiconductor films 108_1 and 108_3, when using a metal oxide target with an atomic ratio of In:Ga: Zn = 1:3:6, the oxide semiconductor films 1 08_1 and 108_3 may have a case where In:Ga:Zn = 1:β5 (1 ≤ β5 ≤ 5):β6 (4 ≤ β 6 ≤ 8).

[0460] <2-3. Configuration Example 4 of Transistor> FIG. 45(A) is a top view of the transistor 300A, FIG. 45(B) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line X1-X2 shown in FIG. 45(A ), and FIG. 45(C) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line Y1-Y2 shown in FIG. 4 5(A). In FIG. 45 (A), in order to avoid complexity, some of the components of the transistor 300A (such as the insulating film that functions as the gate insulating film) are omitted in the illustration. Also, when the direction of the dashed-dotted line X1 -X2 is called the channel length direction and the direction of the dashed-dotted line Y1-Y2 is called the channel width direction . In the top view of the transistor, as in FIG. 45(A) in the subsequent drawings

[0461] , some of the components may be omitted in the illustration. The transistor 300A shown in FIG. 45 includes a conductive film 304 on a substrate 302, and the substrate 302 and and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and above the insulating film 307 an oxide semiconductor film 308, a conductive film 312a on the oxide semiconductor film 308, and a conductive film 312b on the oxide semiconductor film 308. Further, on the transistor 300A, more specifically insulating films 314, 316, and an insulating film 318 are provided on the conductive films 312a, 312b and the oxide semiconductor film 308.

[0462] Note that in the transistor 300A, the insulating films 306 and 307 function as a gate insulating film of the transistor 300 A, and the insulating films 314, 316, and 318 function as a protective insulating film of the transistor 300A. Further, in the transistor 300A, the conductive film 304 functions as a gate electrode, the conductive film 312a functions as a source electrode and the conductive film 312b functions as a drain electrode.

[0463] Note that in this specification and the like, the insulating films 306 and 307 may be referred to as the first insulating film, the insulating films 314, 316 as the second insulating film, and the insulating film 318 as the third insulating film, respectively. .

[0464] The transistor 300A shown in FIG. 45 has a channel etch type transistor structure. The oxide semiconductor film according to one aspect of the present invention can be suitably used for a channel etch type transistor.

[0465] <2-4. Configuration Example 5 of Transistor> FIG. 46(A) is a top view of the transistor 300B, FIG. 46(B) corresponds to a cross-sectional view of a cut surface between the dashed-dotted line X1-X2 shown in FIG. 46(A ), and FIG. 46(C) is FIG. 4 ​It corresponds to a cross-sectional view of a cross-section between the dashed-dotted lines Y1 - Y2 shown in 6(A).

[0466] The transistor 300B shown in FIG. 46 includes a conductive film 304 on a substrate 302, the substrate 302 and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and on the insulating film 307 an oxide semiconductor film 308, an insulating film 314 on the oxide semiconductor film 308, and on the insulating film 314 an insulating film 316, and a conductive film 312a electrically connected to the oxide semiconductor film 308 through an opening 341a provided in the insulating film 314 and the insulating film 316, and a conductive film 312b electrically connected to the oxide semiconductor film 308 through an opening 341b provided in the insulating film 314 and the insulating film 316. Further, on the transistor 300B, more specifically, on the conductive films 31 2a, 312b, and the insulating film 316, an insulating film 318 is provided. In the transistor 300B, the insulating films 306 and 307 function as a gate insulating film of the transistor 300

[0467] B, the insulating films 314 and 316 function as a protective insulating film of the oxide semiconductor film 308 and the insulating film 318 functions as a protective insulating film of the transistor 300B . Also, in the transistor 300B, the conductive film 304 functions as a gate electrode, the conductive film 312a functions as a source electrode, and the conductive film 3 12b functions as a drain electrode. In the transistor 300A shown in FIG. 45, it had a channel etch type structure, whereas the transistor 300B shown in FIGS. 46(A), (B), and (C) has a channel protection type structure

[0468] . The oxide semiconductor film according to one aspect of the present invention is also suitably used for a channel protection type transistor . ​It can be used.

[0469] <2-5. Configuration Example 6 of Transistor> FIG. 47(A) is a top view of the transistor 300C, and FIG. 47(B) corresponds to a cross-sectional view of the cutting plane between the dashed-dotted lines X1-X2 shown in FIG. 47(A), and FIG. 47(C) corresponds to a cross-sectional view of the cutting plane between the dashed-dotted lines Y1-Y2 shown in FIG. 47(A). ) and FIG. 47(C) corresponds to a cross-sectional view of the cutting plane between the dashed-dotted lines Y1-Y2 shown in FIG. 47(A).

[0470] The transistor 300C shown in FIG. 47 has different shapes of the insulating films 314 and 316 from those of the transistor 300B shown in FIGS. 46(A), (B), and (C). Specifically, the insulating films 314 and 316 of the transistor 300C are provided in an island shape on the channel region of the oxide semiconductor film 308. Other configurations are the same as those of the transistor 300B.

[0471] <2-6. Configuration Example 7 of Transistor> FIG. 48(A) is a top view of the transistor 300D, and FIG. 48(B) corresponds to a cross-sectional view of the cutting plane between the dashed-dotted lines X1-X2 shown in FIG. 48(A), and FIG. 48(C) corresponds to a cross-sectional view of the cutting plane between the dashed-dotted lines Y1-Y2 shown in FIG. 48(A). ) and FIG. 48(C) corresponds to a cross-sectional view of the cutting plane between the dashed-dotted lines Y1-Y2 shown in FIG. 48(A).

[0472] The transistor 300D shown in FIG. 48 includes a conductive film 304 on the substrate 302, an insulating film 306 on the substrate 302 and the conductive film 304, an insulating film 307 on the insulating film 306, an oxide semiconductor film 308 on the insulating film 307, a conductive film 312a on the oxide semiconductor film 308, a conductive film 312b on the oxide semiconductor film 308, an insulating film 314 on the oxide semiconductor film 308 and the conductive films 312a and 312b, an insulating film 316 on the insulating film 314, an insulating film 318 on the insulating film 316, and conductive films 320a and 320b on the insulating film 318. ​​​​​​​​​​

[0473] In the transistor 300D, the insulating films 306 and 307 function as the first gate insulating film of the transistor 300 D, and the insulating films 314, 316, and 318 function as the second gate insulating film of the transistor 300 D. Also, in the transistor 300 D, the conductive film 304 functions as the first gate electrode, and the conductive film 320a functions as the second gate electrode, and the conductive film 320b functions as the pixel electrode used in the display device . Also, the conductive film 312a functions as the source electrode, and the conductive film 312b functions as the drain electrode.

[0474] Also, as shown in FIG. 48(C), the conductive film 320a is connected to the conductive film 304 at the openings 342b and 342c provided in the insulating films 306, 307, 314, 316, and 318. Therefore, the same potential is applied to the conductive film 320a and the conductive film 304.

[0475] In the transistor 300D, the openings 342b and 342c are provided and the configuration of connecting the conductive film 3 20a and the conductive film 304 is illustrated, but it is not limited thereto. For example , only one of the openings 342b or 342c may be formed to connect the conductive film 3 20a and the conductive film 304, or the openings 342b and 342c may be provided without connecting the conductive film 320a and the conductive film 304. Note that in the case of a configuration where the conductive film 32 0a and the conductive film 304 are not connected, different potentials can be applied to the conductive film 320a and the conductive film 304, respectively.

[0476] Also, the conductive film 320b is at the opening 342a provided in the insulating films 314, 316, and 318 It is connected to the conductive film 312b via

[0477] Note that the transistor 300D has the S-channel structure described above.

[0478] <2-7. Configuration Example 8 of Transistor> In addition, the oxide semiconductor film 308 included in the transistor 300A shown in FIGS. 45(A), (B), and (C) may have a plurality of stacked structures. An example in that case is shown in FIGS. 49(A), (B) and FIGS. 50 (A), (B).

[0479] FIGS. 49(A) and (B) are cross-sectional views of the transistor 300E, and FIGS. 50(A) and (B) are cross-sectional views of the transistor 300F. Note that the upper surfaces of the transistors 300E and 300F are the same as those of the transistor 300A shown in FIG. 45(A).

[0480] The oxide semiconductor film 308 included in the transistor 300E shown in FIGS. 49(A) and (B) is an acid oxide semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3 and so on. Further, the oxide semiconductor film 308 included in the transistor 300F shown in FIGS. 50(A) and (B) is an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.

[0481] Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the oxide semi- conductor film 308_1, the oxide semiconductor film 308_2, the oxide semiconductor film 308_3, the conductive film 31 2a, 312b, the insulating film 314, the insulating film 316, the insulating film 318, and the conductive films 320a, 3 20b are the conductive film 106, the insulating film 116, the oxide semiconductor film 10 8, the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3 described above, respectively. , the same materials as those of the conductive films 120a and 120b, the insulating film 104, the insulating film 118, the insulating film 116, and the conductive film 112 can be used.

[0482] <2-8. Configuration Example 9 of Transistor> FIG. 51(A) is a top view of the transistor 300G, and FIG. 51(B) corresponds to a cross-sectional view of a cut surface between the dashed-dotted line X1-X2 shown in FIG. 51(A ), and FIG. 51(C) corresponds to a cross-sectional view of a cut surface between the dashed-dotted line Y1-Y2 shown in FIG. 5 1(A).

[0483] The transistor 300G shown in FIG. 51 includes a conductive film 304 on a substrate 302, the substrate 302 and an insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, an insulating film 307 on the oxide semiconductor film 308, a conductive film 312a on the oxide semiconductor film 308, and an oxide semiconductor film 308, a conductive film 312b on the oxide semiconductor film 308, and an oxide semiconductor film 308, a conductive film 312a, and a conductive film 3 12b, an insulating film 314 on the oxide semiconductor film 308, a conductive film 314, an insulating film 316 on the insulating film 314, and a conductive film on the insulating film 316 320a, and a conductive film 320b on the insulating film 316.

[0484] Further, the insulating films 306 and 307 have an opening 351, and a conductive film 312 is electrically connected to the conductive film 304 through the opening 351 on the insulating films 306 and 307 c is formed. Further, the insulating films 314 and 316 have an opening 352a reaching the conductive film 312b and an opening 352b reaching the conductive film 312c.

[0485]

[0485] Further, the oxide semiconductor film 308 includes an oxide semiconductor film 308_2 on the conductive film 304 side and an oxide semiconductor film 308_3 on the oxide semiconductor film 308_2.

[0486] Also, an insulating film 318 is provided on the transistor 300G. The insulating film 318 is formed so as to cover the insulating film 316, the conductive film 320a, and the conductive film 320b.

[0487] In the transistor 300G, the insulating films 306 and 307 have the function of the first gate insulating film of the transistor 300 G, the insulating films 314 and 316 have the function of the second gate insulating film of the transistor 3 00G, and the insulating film 318 has the function of the protective insulating film of the transistor 300 G. Also, in the transistor 300G, the conductive film 3 04 has the function of the first gate electrode, the conductive film 320a has the function as the second gate electrode and the conductive film 320b has the function as the pixel electrode used in the display device. Also, in the transistor 300G, the conductive film 312a has the function as the source electrode and the conductive film 312b has the function as the drain electrode. Also, in the transistor 30 0G, the conductive film 312c has the function as the connection electrode.

[0488] Note that the transistor 300G has the S-channel structure described above.

[0489] Also, the structures of the transistors 300A to 300G may be freely combined and used.

[0490] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0491] (Embodiment 3) In this embodiment, a display device having the semiconductor device exemplified in the previous embodiment ​​An example will be described below with reference to FIGS. 52 to 59.

[0492] FIG. 52 is a top view showing an example of a display device. The display device 700 shown in FIG. 52 includes a pixel portion 702 provided on a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701, a sealant 712 disposed so as to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. Moreover, the display device 700 has an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Signal lines 710 are connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708, respectively. Various signals supplied by the FPC 716 are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. Moreover, the display device 700 has an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Signal lines 710 are connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708, respectively. Various signals supplied by the FPC 716 are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705.

[0493] Moreover, the display device 700 has an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Signal lines 710 are connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708, respectively. Various signals supplied by the FPC 716 are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. Moreover, the display device 700 has an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Signal lines 710 are connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708, respectively. Various signals supplied by the FPC 716 are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. Moreover, the display device 700 has an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Signal lines 710 are connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708, respectively. Various signals supplied by the FPC 716 are provided between the first substrate 701 and the second substrate 705. Although not shown in FIG. 52, a display element is provided between the first substrate 701 and the second substrate 705. Numbers etc. are supplied to the pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, and the FPC terminal section 708 via the signal line 710.

[0494] Also, a plurality of gate driver circuit sections 706 may be provided in the display device 700. Also, as the display device 700, an example in which the source driver circuit section 704 and the gate driver circuit section 706 are formed on the same first substrate 701 as the pixel section 702 is shown, but is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701, or only the source driver circuit section 704 may be formed on the first substrate 701. In this case, a substrate (for example, a drive circuit substrate formed of a single crystalline semiconductor film or a polycrystalline semiconductor film) on which a source driver circuit or a gate driver circuit or the like is formed may be formed on the first substrate 701. Note that the connection method of the separately formed drive circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

[0495] Also, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 included in the display device 700 have a plurality of transistors.

[0496] Also, the display device 700 can have various elements. As an example of the element, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, etc.), a light-emitting transistor element (a transistor that emits light according to current), an electron-emitting element, Low-temperature element, plasma display panel (PDP), MEMS (Micro Electro-Mechanical System) display (e.g., grating light valve (GLV), digital micromirror device (DMD), digital microshutter (DMS) element, interferometric modulation (IMOD) element, etc.), piezoelectric ceramic display, etc.

[0497] Also, as an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron emission element, there is a field emission display (FED) or a SED type flat panel display (SED: Surface-conduction n Electron-emitter Display), etc. As an example of a display device using a liquid crystal element, there is a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display) etc. As an example of a display device using an electronic ink element or an electrophoretic element, there is electronic paper, etc. When realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may function as reflective electrodes. For example, part or all of the pixel electrodes may contain aluminum, silver, etc. Further, in that case, it is also possible to provide a memory circuit such as SRAM under the reflective electrode. This can further reduce power consumption.

[0498] Note that the display method in the display device 700 may be a progressive method or an interlace method. ​​​etc. can be used. Also, as color elements for controlling pixels during color display, R is not limited to the three colors of RGB (where R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Or, like a pentile arrangement one color element may be composed of two of the RGB colors, and different two colors may be selected and composed by the color element. Or, one or more colors such as yellow, cyan, and magenta may be added to RGB . Note that the size of the display area may be different for each dot of the color element . However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device.

[0499] Also, in order to perform full-color display of a display device using a white light-emitting (W) backlight (such as an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp), a coloring layer (also called a color filter .) may be used. The coloring layer can be used, for example, by appropriately combining red (R), green (G), blue (B ), yellow (Y), etc. By using the coloring layer , the color reproducibility can be made higher than when the coloring layer is not used. At this time, by arranging the area with the coloring layer and the area without the coloring layer , the white light in the area without the coloring layer can be directly used for display. By arranging an area without the coloring layer in part , the reduction in luminance due to the coloring layer can be reduced during bright display, and the power consumption may be reduced by about 2 to 30%. However, when performing full-color display using a self-luminous element such as an organic EL element or an inorganic EL element , R, G, B, Y, and W may be made to emit light from elements having their respective emission colors . By using a self-luminous element, compared to the case of using a coloring layer ​ In some cases, power consumption can be further reduced.

[0500] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts red, green, and blue by filtering, A method that uses each color of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method of converting to green (color conversion method, quantum dot method) may also be applied.

[0501] In this embodiment, a liquid crystal element and an EL element are used as display elements. 53 to 55. Note that FIGS. 53 and 54 are diagrams showing the chained dotted line shown in FIG. This is a cross-sectional view taken along line QR, and shows a configuration in which a liquid crystal element is used as a display element. 55 is a cross-sectional view taken along the dashed line QR in FIG. 52, and shows a display device using an EL element as a display element. This is the configuration used.

[0502] First, the common parts shown in Figures 53 to 55 will be explained, and then the different parts will be explained. This will be explained below.

[0503] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIGS. 53 to 55 includes a wiring portion 711, a pixel portion 702, and a , a source driver circuit section 704, and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Has.

[0504] Transistor 750 and transistor 752 are similar to transistor 100A shown above. It has the following configuration. Regarding the configurations of the transistors 750 and 752, other transistors shown in the previous embodiment may be used.

[0505] The transistor used in this embodiment has an oxide semiconductor film with high purity and suppression of the formation of oxygen vacancies. This transistor can reduce the off-current. Therefore, the holding time of electrical signals such as image signals can be extended, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, resulting in an effect of suppressing power consumption.

[0506] Also, the transistor used in this embodiment can obtain a relatively high field-effect mobility, so it can be driven at high speed. For example, by using such a high-speed drivable transistor in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed on the same substrate. That is, since there is no need to use a semiconductor device formed by a separate driver circuit such as a silicon wafer, the number of components of the semiconductor device can be reduced. Also, in the pixel portion, by using a transistor that can be driven at high speed, a high-quality image can be provided.

[0507] The capacitive element 790 has a lower electrode formed through a process of processing the same conductive film that functions as the first gate electrode of the transistor 750, and an upper electrode formed through a process of processing the same conductive film that functions as the source electrode and drain electrode of the transistor 750 or the same conductive film that functions as the second gate electrode. Also, between the lower electrode and the upper electrode, an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the first gate insulating film of the transistor 750, and an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the protective insulating film on the transistor 750 are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. and an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the protective insulating film on the transistor 750 are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. and an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the protective insulating film on the transistor 750 are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. Also, between the lower electrode and the upper electrode, an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the first gate insulating film of the transistor 750, and an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the protective insulating film on the transistor 750 are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. and an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the protective insulating film on the transistor 750 are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes.

[0508] Also, in FIGS. 53 to 55, a planarization insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitor element 790. Also, in FIGS. 53 to 55, a planarization insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitor element 790.

[0509] Also, in FIGS. 53 to 55, the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion. and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but the present invention is not limited thereto. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top gate type transistor is used for the pixel portion 702 and a bottom gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom gate type transistor is used for the pixel portion 702 and a top gate type transistor is used for the source driver circuit portion 704 may be mentioned. Note that the source driver circuit portion 704 described above may be read as a gate driver circuit portion.

[0510] Also, the signal line 710 is formed through the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. As the signal line 710, for example, a copper element and the drain electrode of the transistors 750 and 752. As the signal line 710, for example, a copper element When a material including [it] is used, signal delay and the like due to wiring resistance are small, and display on a large screen becomes possible. It becomes possible.

[0511] Further, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 71 6. Note that the connection electrode 760 is formed through the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780.

[0512] Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, as the first substrate 701 and the second substrate 705, a flexible substrate may be used. Examples of the flexible substrate include a plastic substrate and the like.

[0513] Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure 778.

[0514] Further, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 that contacts the light-shielding film 738 and the colored film 736 are provided.

[0515] <3-2. Configuration example of a display device using a liquid crystal element> The display device 700 shown in FIG. 53 has a liquid crystal element 775. The liquid crystal element 775 is a conductive film It has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display device 700 shown in FIG. 53 changes the alignment state of the liquid crystal layer 776 by the voltage applied to the conductive film 772 and the conductive film 774, and controls the transmission and non-transmission of light to display an image.

[0516] Also, the conductive film 772 is electrically connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element.

[0517] As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is transparent to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film that is reflective to visible light, for example, aluminum or a material containing silver may be used.

[0518] When a conductive film that is reflective to visible light is used for the conductive film 772, the display device 700 becomes a reflective liquid crystal display device. Also, when a conductive film that is transparent to visible light is used for the conductive film 772 the display device 700 becomes a transmissive liquid crystal display device.

[0519] Also, by changing the configuration on the conductive film 772, the driving method of the liquid crystal element can be changed. An example in this case is shown in FIG. 54. Also, the display device 700 shown in FIG. 54 is an example of a configuration using a horizontal electric field method (for example, FFS mode) as the driving method of the liquid crystal element. FIG. 54 ​​​​​​​ In the case of the configuration shown, an insulating film 773 is provided on the conductive film 772, and a conductive film 774 is provided on the insulating film 773. In this case, the conductive film 774 functions as a common electrode (also referred to as a common electrode), and through the insulating film 773, the electric field generated between the conductive film 772 and the conductive film 774 can control the alignment state of the liquid crystal layer 776.

[0520] Also, although not shown in FIGS. 53 and 54, a configuration may be adopted in which alignment films are provided on either one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776. Also, although not shown in FIGS. 53 and 54, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, or the like may be used as the light source. When using a liquid crystal element as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

[0521] Also, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the cholesteric liquid crystal is heated, it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used to improve the temperature range.

[0522] ​​​​​​​​​​​The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational speed and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is eliminated. This can prevent defects and damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0523] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0524] Furthermore, normally black type liquid crystal display devices, such as those using vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0525] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 55 has a light-emitting element 782. The light-emitting element 782 has a conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 55 can display an image by the light emission of the EL layer 786 included in the light-emitting element 782. Note that the EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

[0526] Examples of materials that can be used for the organic compound include a fluorescent material or a phosphorescent material. Examples of materials that can be used for the quantum dot include a colloidal quantum dot material, an alloy-type quantum dot material, a core-shell-type quantum dot material, and a core-type quantum dot material. In addition, materials containing an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, a quantum dot material containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), aluminum (Al), etc. may be used.

[0527] In addition, as the above-described organic compound and inorganic compound, for example, methods such as a vapor deposition method (including a vacuum vapor deposition method), a droplet discharge method (also referred to as an inkjet method), a coating method, and a gravure printing method can be used to form them. Further, the EL layer 786 may include a low molecular material, a medium molecular material (including an oligomer and a dendrimer), or a high molecular material.

[0528] Here, a method of forming the EL layer 786 using the droplet discharge method will be described with reference to FIG. 58. FIGS. 58(A) to 58(D) are cross-sectional views for explaining a method of manufacturing the EL layer 786. ​​

[0529] First, a conductive film 772 is formed on the planarized insulating film 770, and an insulating film 730 is formed so as to cover a part of the conductive film 772 (see Fig. 58(A)). (See Fig. 58(A)).

[0530] Next, droplets 784 are ejected from the droplet ejection device 783 onto the exposed portion of the conductive film 772, which is an opening in the insulating film 730, to form a layer 785 containing the composition. The droplets 784 are a composition containing a solvent and adhere to the conductive film 772 (see Fig. 58(B)). The droplets 784 are a composition containing a solvent and adhere to the conductive film 772 (see Fig. 58(B)). (See Fig. 58(B)).

[0531] Note that the step of ejecting the droplets 784 may be performed under reduced pressure.

[0532] Next, the solvent is removed from the layer 785 containing the composition and solidified to form an EL layer 786 (see Fig. 58(C)). (See Fig. 58(C)).

[0533] Note that as a method for removing the solvent, a drying process or a heating process may be performed.

[0534] Next, a conductive film 788 is formed on the EL layer 786 to form a light-emitting element 782 (see Fig. 58( D)).

[0535] When the EL layer 786 is formed by the droplet ejection method in this way, the composition can be selectively ejected, so that material loss can be reduced. In addition, since a lithography process for processing the shape is not required, the process can be simplified and cost reduction can be achieved. When the EL layer 786 is formed by the droplet ejection method in this way, the composition can be selectively ejected, so that material loss can be reduced. In addition, since a lithography process for processing the shape is not required, the process can be simplified and cost reduction can be achieved. (See Fig. 58(D)).

[0536] Note that the droplet ejection method described above is a general term for means for ejecting droplets such as a nozzle having a composition discharge port or a head having one or a plurality of nozzles.

[0537] Next, a droplet ejection apparatus used in the droplet ejection method will be described with reference to FIG. 59. FIG. 59 is a conceptual diagram for explaining the droplet ejection apparatus 1400.

[0538] The droplet ejection apparatus 1400 includes droplet ejection means 1403. Further, the droplet ejection means 140 3 includes a head 1405 and a head 1412.

[0539] The head 1405 and the head 1412 are connected to the control means 1407, and can be drawn in a pattern pre-programmed by being controlled by the computer 1410.

[0540] Also, as the timing for drawing, for example, it may be based on the marker 1 411 formed on the substrate 1402. Alternatively, a reference point may be determined based on the outer edge of the substrate 1402. Here, the marker 1411 is detected by the imaging means 1404, and the signal converted into a digital signal by the image processing means 1 409 is recognized by the computer 1410 to generate a control signal and send it to the control means 1407.

[0541] As the imaging means 1404, an image sensor using a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor ( CMOS) can be used. Note that the information on the pattern to be formed on the substrate 1402 is stored in the storage medium 1408, and based on this information, a control signal is sent to the control means 1407 to individually control the individual heads 1 405 and the head 1412 of the droplet ejection means 1403. The material to be ejected is supplied from the material supply source 1 413 and the material supply source 1414 to the head 1405 and the head 1412 through pipes, respectively.

[0542] Inside the head 1405, as indicated by the dotted line 1406, there is a space filled with a liquid material and a structure having a nozzle which is a discharge port. Although not shown, the head 1412 also has an internal structure similar to that of the head 1405. If the nozzles of the head 1405 and the head 1412 are provided with different sizes, different materials can be simultaneously drawn with different widths. With one head, a plurality of types of light-emitting materials and the like can be respectively discharged and drawn. When drawing over a wide area, in order to improve the throughput, the same material can be simultaneously discharged and drawn from a plurality of nozzles. When using a large substrate, the heads 1405 and 1412 can freely scan on the substrate in the directions of the arrows X, Y, and Z shown in FIG. 59, and the area to be drawn can be freely set, and the same pattern can be drawn a plurality of times on one substrate. Also, the step of discharging the composition may be performed under reduced pressure. The substrate may be heated during discharge. After discharging the composition, one or both of the steps of drying and firing are performed. The steps of drying and firing are both heat treatment steps, but their purposes, temperatures, and times are different. The steps of drying and firing are performed under normal pressure or reduced pressure by irradiation with laser light, instant thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of times of heat treatment are not particularly limited. In order to perform the steps of drying and firing well, the temperature at that time depends on the material of the substrate and the properties of the composition. As described above, the EL layer 786 can be manufactured using the droplet discharge device.

[0543] Returning again to the description of the display device 700 shown in FIG. 55.

[0544]

[0545]

[0546] ​​​​​​​​ In the display device 700 shown in FIG. 55, an insulating film 730 is provided on a planarizing insulating film 770 and a conductive film 772. The insulating film 730 covers a part of the conductive film 772. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency and transmits light emitted from the EL layer 7 86. Note that in this embodiment, a top emission structure is exemplified, but the present invention is not limited to this. For example, it can also be applied to a bottom emission structure that emits light from the side of the conductive film 772, or a dual emission structure that emits light from both the conductive film 772 and the conductive film 788.

[0547] In addition, a colored film 736 is provided at a position overlapping with the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping with the insulating film 730, at a routing wiring portion 711...

Claims

Claim 1 A semiconductor device having a transistor, wherein the transistor includes an insulating film, a first conductive film, a second conductive film, a third conductive film, and an oxide semiconductor film, the first conductive film has a region in contact with the oxide semiconductor film, the second conductive film has a region in contact with the oxide semiconductor film, the third conductive film has a region where the oxide semiconductor film and the third conductive film overlap each other with the insulating film therebetween, the transistor has The maximum value of the field-effect mobility in the range where the gate voltage of the transistor is greater than 0 V and less than or equal to 10 V is 40 cm ２ / Vs or more and less than 150 cm ２ / Vs, and the region where a region where the threshold voltage is −1 V or more and 1 V or less, a region where the S value is less than 0.3 V / decade, The off-current has a region where it is less than 1×10 －１２ A / cm ２ and has a region where it is less than 1×10 when the maximum value of the field-effect mobility of the transistor is represented as μFE(max) and the value of the field-effect mobility at a gate voltage of 2 V of the transistor is represented as μFE(Vg = 2V), a semiconductor device in which μFE(max) / μFE(Vg = 2V) is 1 or more and less than 1.5.

Images