Display device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A semiconductor device has a drive circuit part and a display part (also referred to as a pixel part) on the same substrate. The drive circuit part and the display part have a thin-film transistor whose semiconductor layer is configured by an oxide semiconductor, and have first wiring and second wiring. The thin-film transistor has a source electrode layer or a drain electrode layer. The thin-film transistor of the drive circuit part is configured by sandwiching the semiconductor layer between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected with each other via an oxide conductive layer at an opening provided on a gate insulating film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. This includes electro-optical devices such as liquid crystal display devices, semiconductor circuits, and electronic devices, all of which are semiconductor devices.

Background Art

[0003] In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. The thin film transistor is widely applied to electronic devices such as integrated circuits (ICs) and electro-optical devices, and in particular, development as a switching element for image display devices has been urgently required. Metal oxides exist in various forms and are used in various applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like. Some metal oxides exhibit semiconductor characteristics. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. A thin film transistor having such a metal oxide exhibiting semiconductor characteristics as a channel formation region is already known (Patent Document 1 and Patent Document 2).

[0004]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] Thin film transistors that use oxide semiconductor films have high operating speeds and are relatively easy to manufacture. Therefore, sufficient reliability is required.

[0007] To improve the operating characteristics and reliability of a thin film transistor using an oxide semiconductor film This is one of the challenges.

[0008] In particular, it is preferable that the operating speed of the thin film transistors used in the drive circuits is fast.

[0009] For example, the channel length (L) of a thin film transistor can be shortened or the channel width (W) can be widened. However, shortening the channel length (L) reduces the switching speed. There is a problem that the switching characteristics, for example, the on-off ratio, becomes smaller. This increases the capacitance load of the thin film transistor itself.

[0010] In addition, a semiconductor device having a thin film transistor with stable electrical characteristics even if the channel length is short is also provided. It is also an object of the present invention to provide a body device.

[0011] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required for thin film transistors used in drive circuits. High operating speed is required. In particular, the higher the resolution of the display device, Since the writing time of the display image is to be shortened, the thin film transistor used in the driving circuit preferably has a fast operation speed.

[0012] Reducing the variation in the electrical characteristics of the thin film transistor using the oxide semiconductor film is also one of the problems.

Means for Solving the Problem

[0013] One aspect of the present invention has a driving circuit section and a display section (also referred to as a pixel section) on the same substrate. The driving circuit section and the display section have a thin film transistor, a first wiring (also referred to as a terminal or a connection electrode), and a second wiring (also referred to as a terminal or a connection electrode). The thin film transistor has a gate electrode formed of a metal, a gate insulating film on the gate electrode, an oxide semiconductor layer on the gate insulating film, a source electrode (also referred to as a source electrode layer) and a drain electrode (also referred to as a drain electrode layer) formed of a metal on the oxide semiconductor layer, and a protective insulating layer on the oxide semiconductor layer, the source electrode, and the drain electrode. The thin film transistor in the driving circuit section has a conductive layer at a position overlapping the oxide semiconductor layer on the protective insulating layer. The thin film transistor in the display section is electrically connected to a pixel electrode (also referred to as a pixel electrode layer). The first wiring is formed of the same material as the gate electrode, the second wiring is formed of the same material as the source electrode or the drain electrode, and the first wiring and the second wiring in the driving circuit section are electrically connected through an opening (contact hole) provided in the gate insulating film and the protective insulating layer.

[0014] One aspect of the present invention has a driving circuit section and a display section (also referred to as a pixel section) on the same substrate. The driving circuit section and the display section have a thin film transistor, a first wiring, and a second wiring. ​​​​​​​​​​​​​​ The transistor includes a gate electrode made of metal, a gate insulating film on the gate electrode, an oxide semiconductor layer on the gate insulating film, a source electrode and a drain electrode made of metal on the oxide semiconductor layer, and a protective insulating layer on the oxide semiconductor layer and the source electrode and the drain electrode. The thin film transistor in the driving circuit section has a conductive layer at a position overlapping with the oxide semiconductor layer on the protective insulating layer. The thin film transistor in the display section is electrically connected to the pixel electrode. The first wiring is formed of the same material as the gate electrode, the second wiring is formed of the same material as the source electrode or the drain electrode, and the first wiring and the second wiring in the driving circuit section are electrically connected through an opening formed in the gate insulating film. As the thin film transistor for pixels and the thin film transistor for the driving circuit, a reverse staggered type thin film transistor having a bottom gate structure is used. The thin film transistor for pixels and the thin film transistor for the driving circuit are channel etch type thin film transistors provided with an oxide insulating film in contact with the oxide semiconductor layer exposed between the source electrode layer and the drain electrode layer. The thin film transistor for the driving circuit is configured to sandwich the oxide semiconductor layer between the gate electrode and the conductive layer. Thereby, it is possible to reduce the threshold variation of the thin film transistor and provide a semiconductor device including a thin film transistor having stable electrical characteristics. The conductive layer may have the same potential as the gate electrode layer, a floating potential, or a fixed potential, for example, a GND potential or 0V. Further, by applying an arbitrary potential to the conductive layer, the threshold of the thin film transistor can be controlled.

[0015]

[0016]

[0017] ​​​​​​​​​​​​​​ One aspect of the present invention for realizing the above structure is that in a first region where a drive circuit portion is formed on the same substrate and a second region where a display portion is formed, a first electrode that functions as a gate electrode and a first wiring made of the same material as the first electrode are formed by a first photolithography process. Then, a first insulating film that functions as a gate insulating film is formed on the first electrode and the first wiring. On the first insulating film, an oxide semiconductor layer is formed by a second photolithography process. A heat treatment for dehydrating or dehydrogenating the oxide semiconductor layer is performed. On the oxide semiconductor layer, a second electrode that functions as a source electrode and a third electrode that functions as a drain electrode are formed by a third photolithography process. A second wiring made of the same material as the source electrode or the drain electrode is formed. A second insulating film that functions as a protective insulating layer is formed on the second electrode, the third electrode, and the oxide semiconductor layer. By a fourth photolithography process, the first insulating film and the second insulating film that overlap the first wiring are selectively removed to form a first opening. The second insulating film that overlaps the second wiring is selectively removed to form a second opening. In the second region, at a position overlapping either the second electrode or the third electrode, the second insulating film is selectively removed to form a third opening. By a fifth photolithography process, a first conductive layer that electrically connects the first wiring and the second wiring through the first opening and the second opening is formed. In the first region, a fourth electrode made of the same material as the first conductive layer is formed at a position overlapping the oxide semiconductor layer through the second insulating film. In the second region, a fifth electrode made of the same material as the first conductive layer that electrically connects to the thin film transistor through the third opening and functions as a pixel electrode is formed. This is a method for manufacturing a semiconductor device. ​

[0018] The first opening to the third opening are simultaneously formed in the same photolithography process, and the pixel electrode and The first conductive layer and the fourth electrode are simultaneously formed in the same photolithography process. The above configuration can be realized without increasing the number of photolithography steps.

[0019] A semiconductor in which the drive circuit and display sections are formed on the same substrate through five photolithography processes An apparatus can be provided.

[0020] One aspect of the present invention for realizing the above structure is to provide a first substrate on which a drive circuit section is formed. A gate electrode is formed in the first region and a second region where a display portion is to be formed by a first photolithography process. A first electrode that functions as a light-transmitting electrode and a first wiring made of the same material as the first electrode are formed. a first insulating film that functions as a gate insulating film is formed on the first electrode and the first wiring; An oxide semiconductor layer is formed on the insulating film of the first insulating film by a second photolithography process. A heat treatment is performed to dehydrate or dehydrogenate the compound semiconductor layer, and a third photolithography is performed. The first insulating film on the first wiring is selectively removed to form a fourth opening, and an oxide A second electrode serving as a source electrode is formed on the semiconductor layer by a fourth photolithography process. a first electrode, a third electrode acting as a drain electrode, and a second electrode made of the same material as the second or third electrode. A second wiring made of a material is formed on the second electrode, the third electrode, and the oxide semiconductor layer. A second insulating film that functions as an insulating layer is formed, and a fifth photolithography step is performed to form a first insulating film. In the second region, a second electrode is provided at a position overlapping either the second electrode or the third electrode. The insulating film is selectively removed to form a third opening, and a sixth photolithography step is performed. In a first region, a fourth electrode is formed at a position overlapping an oxide semiconductor layer with a second insulating film interposed therebetween. In a second region, a fourth electrode is formed which is made of the same material as the fourth electrode that is electrically connected to the thin film transistor through a third opening and functions as a pixel electrode. This is a method for manufacturing a semiconductor device. The formation of the fourth opening by the third photolithography process may be performed after the formation of the first insulating film and before the formation of the oxide semiconductor layer by the second photolithography process.

[0021] Compared with the above-described aspect, since a photolithography process for providing an opening on the first wiring is added after the formation of the oxide semiconductor layer, a driving circuit portion and a display portion are formed on the same substrate in a total of six photolithography processes. However, since the step of the opening for connecting the first wiring and the second wiring can be only the thickness of the first insulating film, the first wiring and the second wiring can be surely connected with good coverage, and the reliability of the semiconductor device can be improved. In the photolithography process described above, the etching process may be performed using a mask layer formed by a multi-tone mask which is an exposure mask in which the transmitted light has a plurality of intensities.

[0022] The mask layer formed using the multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching on the mask layer. Therefore, it can be used for a plurality of etching processes for processing into different patterns. Thus, with a single multi-tone mask, a driving circuit portion and a display portion can be formed on the same substrate in a total of six photolithography processes. However, since the step of the opening for connecting the first wiring and the second wiring can be only the thickness of the first insulating film, the first wiring and the second wiring can be surely connected with good coverage, and the reliability of the semiconductor device can be improved. The mask layer formed using the multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching on the mask layer. Therefore, it can be used for a plurality of etching processes for processing into different patterns. Thus, with a single multi-tone mask, a driving circuit portion and a display portion can be formed on the same substrate in a total of six photolithography processes. However, since the step of the opening for connecting the first wiring and the second wiring can be only the thickness of the first insulating film, the first wiring and the second wiring can be surely connected with good coverage, and the reliability of the semiconductor device can be improved.

[0023] In the photolithography process described above, the etching process may be performed using a mask layer formed by a multi-tone mask which is an exposure mask in which the transmitted light has a plurality of intensities. The mask layer formed using the multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching on the mask layer. Therefore, it can be used for a plurality of etching processes for processing into different patterns. Thus, with a single multi-tone mask, a driving circuit portion and a display portion can be formed on the same substrate in a total of six photolithography processes.

[0024] The mask layer formed using the multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching on the mask layer. Therefore, it can be used for a plurality of etching processes for processing into different patterns. Thus, with a single multi-tone mask, a driving circuit portion and a display portion can be formed on the same substrate in a total of six photolithography processes. Therefore, it can be used for a plurality of etching processes for processing into different patterns. Thus, with a single multi-tone mask, Thus, a mask layer corresponding to at least two or more different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced. As a result, the process can be simplified.

[0025] The above configuration solves at least one of the above problems.

[0026] In addition, the oxide semiconductor used in this specification is InMO3(ZnO) m (m > 0), and a thin film transistor is fabricated by forming a thin film represented by this and using the thin film as an oxide semiconductor layer. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where M contains the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. Further, in the above oxide semiconductor, in addition to the metal elements contained as M, there are those containing Fe, Ni, and other transition metal elements or oxides of the transition metals as impurity elements. In this specification, among the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m > 0), the oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O-based non-single crystal film. In addition to the above, as the metal oxide applied to the oxide semiconductor layer, metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In- O system, Sn-O system, and Zn-O system can be applied. Also, the above metal oxide In addition to the above, as the metal oxide applied to the oxide semiconductor layer, metal oxides of In-Sn-Zn-O m (m > 0), the oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O-based non-single crystal film. In addition to the above, as the metal oxide applied to the oxide semiconductor layer, metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn

[0027] In addition to the above, as the metal oxide applied to the oxide semiconductor layer, metal oxides of In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In- O system, Sn-O system, Zn-O system can be applied. Also, the above metal oxide The oxide semiconductor layer made of the material may contain silicon oxide.

[0028] Heat treatment is carried out under an inert gas atmosphere such as nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment, resulting in low resistance, that is, N-type ( N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer, and a process for forming the oxide insulating film is performed. By performing heat treatment, the oxide semiconductor layer is made into an oxygen-excess state, which increases the resistance, i.e., I In addition, solid-phase oxidation is performed to place the oxide semiconductor layer in an oxygen-excess state. This allows us to obtain thin film transistors with good electrical characteristics and high reliability. Therefore, it is possible to manufacture and provide a semiconductor device that can achieve this.

[0029] Dehydration or dehydrogenation is carried out using an inert gas such as nitrogen or a noble gas (argon, helium, etc.). Heating in an atmosphere at 400°C or higher but lower than the strain point of the substrate, preferably 420°C or higher and 570°C or lower Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer. This prevents re-impregnation of the sintered body with water (H2O).

[0030] The heat treatment for dehydration or dehydrogenation is preferably carried out in a nitrogen atmosphere with an H2O concentration of 20 ppm or less. It is also possible to carry out the treatment in ultra-dry air with an H2O concentration of 20 ppm or less.

[0031] The oxide semiconductor layer that has been dehydrated or dehydrogenated is Even when TDS measurements were performed on the body layer up to 450°C, two peaks of water were observed, and at least 300 The heat treatment conditions should be such that a peak that appears around 100°C is not detected. Thin film transistors using oxide semiconductor layers that have been hydrogenated or dehydrogenated are 45% or less in TDS. Even if the measurement is carried out up to 0 °C, the peak of water appearing at around at least 300 °C is not detected.

[0032] And when the temperature is lowered after dehydration or dehydrogenation of the oxide semiconductor layer at a heating temperature T, by not exposing to the atmosphere using the same furnace in which dehydration or dehydrogenation has been carried out, it is important not to allow water or hydrogen to be mixed in again. After performing dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (N etc.), and then increasing the resistance to make it an I-type, when a thin-film transistor is fabricated using the oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. - It is desirable for the semiconductor device (display device) that the channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin-film transistor. Note that if the threshold voltage of the thin-film transistor is negative, current flows between the source electrode and the drain electrode even when the gate voltage is 0 V, and it tends to be a so-called normally-on. In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and this electrical characteristic affects the performance of the display device. In particular, among the electrical characteristics of the thin-film transistor, the threshold voltage is important. Even if the field-effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin-film transistor with a large absolute value of the threshold voltage, in a state where the drive voltage is low, the switching function as a TFT cannot be achieved, and there is a risk of becoming a load. In the case of an n-channel type thin-film transistor, a channel is formed only when a positive voltage is applied to the gate voltage, and a drain current flows. In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and this electrical characteristic affects the performance of the display device. In particular, among the electrical characteristics of the thin-film transistor, the threshold voltage is important. Even if the field-effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. If the absolute value of the threshold voltage is large for a thin-film transistor, in a state where the drive voltage is low, the switching function as a TFT cannot be achieved, and there is a risk of becoming a load. In the case of an n-channel type thin-film transistor, a channel is formed only when a positive voltage is applied to the gate voltage, and a drain current flows. A transistor in which a channel does not form unless the driving voltage is high is desirable. A transistor in which a channel is formed and drain current flows even under negative voltage conditions, However, they are not suitable for use as thin film transistors in circuits.

[0033] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. It is also possible to switch to a gas atmosphere, for example, by switching to air in the same furnace where dehydration or dehydrogenation was performed. The furnace is filled with high-purity oxygen gas, N2O gas, or ultra-dry air (dew point Cooling is carried out by filling the container with a temperature of -40°C or less, preferably -60°C or less.

[0034] The moisture content in the film is reduced by heat treatment for dehydration or dehydrogenation, and then the film containing moisture is Cool slowly (or cool) in an atmosphere that is free from dew (dew point is -40°C or less, preferably -60°C or less). By using the oxide semiconductor film, the electrical characteristics of the thin film transistor can be improved and mass production can be achieved. This will realize thin-film transistors that are both reliable and high-performance.

[0035] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). This heat treatment is called a heat treatment for dehydration or dehydrogenation. Dehydrogenation does not only mean that hydrogen is released as H2 by the hydrogenation process, but also means that hydrogen is released as H For convenience, this term is used to refer to the elimination of OH and other groups.

[0036] Heat treatment is carried out under an inert gas atmosphere such as nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment, resulting in low resistance, that is, N-type ( N - To make something (such as a product).

[0037] Also, a high-resistance drain region (also referred to as an HRD (High Resistance Drain) region) that is oxygen-deficient and overlaps with the drain electrode layer is formed. Also, a high-resistance source region (also referred to as an HRS (High Resistance e Source) region) that is oxygen-deficient and overlaps with the source electrode layer is formed.

[0038] Specifically, the carrier concentration of the high-resistance drain region is in the range of 1×10 18 / cm 3 or higher, and is higher than at least the carrier concentration (less than 1×10 / cm 18 / cm 3 less) of the channel formation region. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0039] Then, by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excessive state, further high resistance, that is, type-I conversion, is achieved to form a channel formation region. Note that, as the process of making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excessive state, film formation by sputtering of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer, or heat treatment after oxide insulating film formation, or heat treatment in an atmosphere containing oxygen, or cooling in an oxygen atmosphere after heating in an inert gas atmosphere, cooling with ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower), etc. are performed.

[0040] Also, in order to make at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer into a channel formation region, by selectively making it in an oxygen-excessive state, high resistance It can also be converted, i.e., made into type I. In contact with the dehydrated or dehydrogenated oxide semiconductor layer a source electrode layer and a drain electrode layer made of a metal electrode such as Ti are formed, and an exposed region that does not overlap with the source electrode layer and the drain electrode layer is selectively made into an oxygen-excessive state to form a channel formation region can be formed. When selectively making it into an oxygen-excessive state, a first high-resistance source region overlapping with the source electrode layer and a second high-resistance drain region overlapping with the drain electrode layer are formed, and the region between the first high-resistance source region and the second high-resistance drain region becomes the channel formation region That is, the channel formation region is self-alignedly formed between the source electrode layer and the drain electrode layer.

[0041] Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability.

[0042] In addition, by forming a high-resistance drain region in the oxide semiconductor layer overlapping with the drain electrode layer, it is possible to improve the reliability when forming a drive circuit. Specifically, by forming a high- resistance drain region, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region becomes a buffer and a local high electric field is not applied, and a configuration can be obtained in which the breakdown voltage of the thin-film transistor is improved.

[0043] Also, in the oxide semiconductor layer overlapping with the drain electrode layer and the source electrode layer, a high-resistance drain ​​​​By forming an in-region and a high-resistance source region, it is possible to reduce the leakage current in the channel formation region when forming a drive circuit. Specifically, by forming a high-resistance drain region, the path of the leakage current flowing between the drain electrode layer and the source electrode layer is the drain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the high-resistance source region on the source electrode layer side, and the source electrode layer in that order. At this time, in the channel formation region, the leakage current flowing into the channel formation region from the high-resistance drain region on the drain electrode layer side can be concentrated near the interface between the gate insulating layer, which becomes high resistance when the transistor is off, and the channel formation region, and the leakage current in the back channel portion (a part of the surface of the channel formation region away from the gate electrode layer) can be reduced. Moreover, the high-resistance source region overlapping the source electrode layer and the high-resistance drain region overlapping the drain electrode layer overlap with a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer, thereby more effectively relaxing the electric field strength near the end of the drain electrode layer. In addition, an oxide conductive layer may be formed between the oxide semiconductor layer and the source and drain electrodes. The oxide conductive layer preferably contains zinc oxide as a component and preferably does not contain indium oxide. For example, zinc oxide, aluminum zinc oxide, aluminum gallium zinc oxynitride, zinc gallium oxide, etc. can be used. The oxide conductive layer is also called a low-resistance drain region (LRN (Low Resistance N-type conductivity) region, LRD (Low Resistance Drain) region).

[0044]

[0045] ​​​​​​​​​​​​​​​​ also functions as. Specifically, the carrier concentration in the low-resistance drain region is higher than that in the high-resistance drain region (HRD region), for example, 1×10 20 / cm 3 or more and 1×10 21 / c m 3 or less is preferable. By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode and the drain electrode, the contact resistance between the electrode and the oxide semiconductor layer can be reduced, and the high-speed operation of the transistor can be realized. Therefore, the frequency characteristics of the peripheral circuit (driving circuit) can be improved .

[0046] The metal layer for forming the oxide conductive layer, the source electrode, and the drain electrode enables continuous film formation .

[0047] In addition, the above-described first wiring and second wiring may be formed as a laminated wiring composed of the same material as the oxide conductive layer that functions as LRN or LRD and a metal material. By forming a laminate of the metal and the oxide conductive layer, the covering property against steps such as overstepping and opening of the lower-layer wiring can be improved , and the wiring resistance can be reduced. Also, since an effect of preventing local high resistance or disconnection of the wiring due to migration or the like can be expected, a highly reliable semiconductor device can be provided . .

[0048] Also, when connecting the above-described first wiring and second wiring, by sandwiching the oxide conductive layer and connecting them, it can be expected to prevent an increase in the contact resistance (contact resistance) due to the formation of an insulating oxide on the metal surface of the connection portion (contact portion), and a highly reliable semiconductor device can be provided . .

[0049] ​In addition, since thin film transistors are easily damaged by static electricity or the like, a protection circuit for protecting the thin film transistors in the pixel portion is provided on the same substrate with respect to the gate line or the source line. It is preferable. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer.

[0050] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, the specific names used as matters for specifying the invention in this specification do not indicate anything.

Advantages of the Invention

[0051] A semiconductor device including a thin film transistor using an oxide semiconductor layer and having excellent electrical characteristics and reliability can be realized.

Brief Description of the Drawings

[0052]

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[0053] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiments. In the configuration described below, parts that have the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for corresponding parts, and repeated explanations thereof will be omitted.

[0054] (Embodiment 1) A manufacturing process of a semiconductor device including a thin film transistor will be described with reference to FIGS. .

[0055] A liquid crystal display device as a semiconductor device according to one embodiment of the present invention is shown in FIG. The pixel portion includes a thin film transistor 170 and a capacitor 147, and the thin film transistor 180 a pixel electrode layer 110, and an insulating layer 191 that functions as an alignment film. A substrate 100, an insulating layer 193 that functions as an alignment film, a counter electrode layer 194, a color filter A liquid crystal layer 192 is sandwiched between an opposing substrate 190 on which a colored layer 195 is provided, which functions as a liquid crystal layer. In addition, on the opposite side of the liquid crystal layer 192 of the substrate 100 and the counter substrate 190, A polarizing plate (a layer having a polarizer, also simply referred to as a polarizer) 196a, 196b is provided, and a gate A first terminal 121, a connection electrode 120, and a terminal electrode 128 for connection are provided at the terminal portion of the gate wiring A second terminal 122 and a terminal electrode 129 for connection are provided at the terminal portion of the source wiring. It is.

[0056] In the drive circuit portion, a conductive layer 111 is provided above the gate electrode layer and the semiconductor layer of the thin film transistor 180, and the drain electrode layer 165b is electrically connected to a conductive layer 162 formed in the same process as the gate electrode layer. Also, in the pixel portion, the drain electrode layer of the thin film transistor 170 is electrically connected to the pixel electrode layer 110. The drain electrode layer is electrically connected to the conductive layer 162 formed in the same process as the gate electrode layer. In the pixel portion, the drain electrode layer of the thin film transistor 170 is electrically connected to the pixel electrode layer 110. It is.

[0057] Hereinafter, the manufacturing method will be described in detail with reference to FIGS. 2 to 5 and FIG. 11. FIG. 5 is a plan view of the pixel portion of the liquid crystal display device, and FIGS. 1 to 4 correspond to cross-sectional views taken along lines A1 - A2 and B1 - B2 in FIG. 5. FIG. 5 is a plan view of the pixel portion of the liquid crystal display device, and FIGS. 1 to 4 correspond to cross-sectional views taken along lines A1 - A2 and B1 - B2 in FIG. 5. It corresponds to.

[0058] After forming a conductive layer on the entire surface of the substrate 100, which is a substrate having an insulating surface, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring 108 (also referred to as a capacitive wiring layer), and first terminal 121). As shown in FIG. 2(A), etching is performed so that a tapered shape is formed at the ends of the wirings and electrodes, which is preferable because the coating property of the laminated film is improved. Note that the gate electrode layer 101 and the gate electrode layer 161 are each included in the gate wiring. A first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring 108 (also referred to as a capacitive wiring layer), and first terminal 121). A first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring 108 (also referred to as a capacitive wiring layer), and first terminal 121). Capacitive wiring 108 (also referred to as a capacitive wiring layer), and first terminal 121). As shown in FIG. 2(A), etching is performed so that a tapered shape is formed at the ends of the wirings and electrodes, which is preferable because the coating property of the laminated film is improved. As shown in FIG. 2(A), etching is performed so that a tapered shape is formed at the ends of the wirings and electrodes, which is preferable because the coating property of the laminated film is improved. Note that the gate electrode layer 101 and the gate electrode layer 161 are each included in the gate wiring.

[0059] There are no major restrictions on the substrate that can be used for the substrate 100 having an insulating surface, but at least It is also necessary to have heat resistance to withstand subsequent heat treatment. For the insulating surface A glass substrate can be used for the substrate 100 having.

[0060] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, the strain point is 730 °C or higher It is good to use the one. Also, for the glass substrate, for example, glass materials such as aluminosilicate glass, al Luminosilicate glass, barium silicate glass, etc. are used . Note that by including more barium oxide (BaO) compared to boric acid, a more practical Heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3 .

[0061] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. Since the liquid crystal display device shown in this embodiment is a transmissive type, a substrate having translucency is used as the substrate 100. However, in the case of a reflective type, a substrate such as a non-translucent metal substrate may be used as the substrate 100 . . For a reflective type, a substrate such as a non-translucent metal substrate may be used as the substrate 100 .

[0062] An insulating film serving as an underlayer film may be provided between the substrate 100 and the gate electrode layer 101, the gate electrode layer 161, the conductive layer 1 62, the capacitive wiring 108, and the first terminal 121. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 1 00, and is formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film . It can be.

[0063] The gate electrode layer 101, the gate electrode layer 161, the conductive layer 162, the capacitive wiring 108, and the first The material of the terminal 121 can be a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these, and can be formed in a single layer or by lamination. For example, in the case of a two-layer laminated structure of the gate electrode layer 101, the gate electrode layer 161, the conductive layer 162, the capacitive wiring 108, and the first terminal 121, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to form a laminate of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer. Subsequently, a gate insulating layer 102 is formed on the gate electrode layer 101, the gate electrode layer 161, the conductive layer 162, the capacitive wiring 108, and the first terminal 121 (see Fig. 2(A)).

[0064] The gate insulating layer 102 can be formed as a single layer or by lamination of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer using, for example, a plasma CVD method or a sputtering method. For example, a silicon oxynitride layer can be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 102 is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, the film thickness is 50 nm or more and 2

[0065]

[0066] ​​​​​​​​​​​​​a first gate insulating layer having a thickness of 500 nm or less and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer; The second gate insulating layer is laminated to a thickness of 1 m or less.

[0067] In this embodiment, the gate insulating layer 102 is formed by plasma CVD to a thickness of 200 nm or more. A bottom silicon nitride layer is formed.

[0068] Next, an oxide semiconductor film 13 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 102. 0 (see Figure 2(B)).

[0069] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and the surface of the gate insulating layer 102 is It is preferable to remove the dust particles that are on the substrate side under an argon atmosphere. This is a method of modifying the surface by applying voltage using an RF power source to form plasma near the substrate. It should be noted that nitrogen, helium, etc. may be used instead of the argon atmosphere. It may be performed in an atmosphere containing oxygen, N2O, etc. Also, in an argon atmosphere, Cl 2. It may be carried out in an atmosphere containing CF4 or the like.

[0070] Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 130, the oxide semiconductor film 130 is not oxidized. In order to make the compound semiconductor film amorphous, it is preferable to make the film thickness as thin as 50 nm or less. When the thickness of the oxide semiconductor film is reduced, the oxide semiconductor layer is subjected to heat treatment after being formed. Crystallization can be suppressed.

[0071] The oxide semiconductor film 130 is an In—Ga—Zn—O based non-single crystal film, an In—Sn—Zn—O based , Oxide semiconductor films of In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al-Z n-O system, In-O system, Sn-O system, Zn-O system are used. In this embodiment state, a film is formed by sputtering using an In-Ga-Zn-O system oxide semiconductor target. Also, the oxide semiconductor film 130 is formed by sputtering in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a rare gas (typically argon) and oxygen atmosphere. Also, when using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (x>0) that inhibits crystallization is included in the oxide semiconductor film 130, and it is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process.

[0072] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mol%], In:Ga:Zn = 1:1:0.5 [at%]) is used, and the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, the direct current (DC) power supply is 0.5 kW, and film formation is performed in an atmosphere of argon and oxygen (argon:oxygen = 30 sccm:20 sccm, oxygen flow rate ratio 40%). Note that when using a pulsed direct current (DC) power supply, the visibility can be reduced and the film thickness distribution becomes uniform, which is preferable. The film thickness of the In-Ga-Zn-O system non-single crystal film is set to 5 nm or more and 200 nm or less. In this embodiment, as the oxide semiconductor film an In-Ga-Zn-O system non-single crystal film with a film thickness of 20 nm is formed by sputtering using an In-Ga-Zn-O system oxide semiconductor target. ​

[0073] Among sputtering methods, there are an RF sputtering method that uses a high-frequency power source as a sputtering power source and a DC sputtering method. There is also a pulsed DC sputtering method that applies a bias pulsewise . The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0074] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can laminate and form different material films in the same chamber, or can also discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0075] There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber, and a sputtering apparatus that uses a plasma generated using microwaves without using glow discharge, which is an E CR sputtering method. There is also a reactive sputtering method that forms a compound thin film by chemically reacting a target substance and a sputtering gas component during film formation, and a bias sputtering method that applies a voltage to a substrate during film formation.

[0076] Next, a resist mask 137 is formed by performing a second photolithography process on the oxide semiconductor film 130, and unnecessary portions of the oxide semiconductor film 130 and the gate insulating layer 1 02 are removed by etching, and a contact hole 119 reaching the first terminal 121 and a contact hole 118 reaching the conductive layer 162 are formed in the gate insulating layer 102 (FIG. 2( ).

[0077] Next, a resist mask 137 is formed by performing a second photolithography process on the oxide semiconductor film 130, and unnecessary portions of the oxide semiconductor film 130 and the gate insulating layer 102 are removed by etching to form a contact hole 119 reaching the first terminal 121 and a contact hole 118 reaching the conductive layer 162 in the gate insulating layer 102 (FIG. 2( ). 02 are removed by etching, and a contact hole 119 reaching the first terminal 121 and a contact hole 118 reaching the conductive layer 162 are formed in the gate insulating layer 102 (FIG. 2( ). See C). ).

[0078] In this way, in a state where the oxide semiconductor film 130 is laminated on the entire surface of the gate insulating layer 102, When a step of forming a contact hole in the insulating layer 102 is performed, a laser is formed on the surface of the gate insulating layer 102. Since the resist mask does not come into direct contact with the gate insulating layer 102, contamination (such as adhesion of impurities) on the surface of the gate insulating layer 102 can be prevented. ) can be prevented. This improves the condition of the device, leading to improved reliability.

[0079] A resist pattern may be formed directly on the gate insulating layer to open the contact holes. In that case, after the resist is removed, heat treatment is performed to dehydrate and decompose the surface of the gate insulating film. It is preferable to carry out the hydrogenation and dehydroxylation treatments. For example, the treatments are carried out in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) and oxygen atmosphere. (below the strain point of the substrate) to remove impurities such as hydrogen and water contained in the gate insulating layer. That's fine.

[0080] Next, the resist mask 137 is removed, and the oxide semiconductor film 130 is subjected to a third photolithography. The resist masks 135a and 135b formed by the etching process are used to form the islands. The oxide semiconductor layers 131 and 132 are formed in an island shape (see FIG. 3A). Resist masks 135a and 135b for forming the compound semiconductor layer are formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0081] Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated. Form hydrogenated oxide semiconductor layers 133 and 134 (see Fig. 3(B)). Before dehydration or dehydrogenation, the temperature of the first heat treatment is 400 °C or higher and lower than the strain point of the substrate, preferably 425 °C or higher. If it is 425 °C or higher, the heat treatment time may be 1 hour or less. However, if it is less than 425 °C, the heat treatment time will be longer than 1 hour. Here, Introduce the substrate into an electric furnace, which is one of the heat treatment apparatuses, and perform heat treatment on the oxide semiconductor layer in a nitrogen atmosphere. After that, without exposing it to the atmosphere, prevent the re - mixing of water and hydrogen into the oxide semiconductor layer to obtain the oxide semiconductor layer. In this embodiment, from the heating temperature T for dehydrating or dehydrogenating the oxide semiconductor layer, use the same furnace to cool it slowly in a nitrogen atmosphere until it reaches a sufficient temperature where water will not enter again. Specifically, cool it slowly until the temperature drops by 100 °C or more from the heating temperature T. Also, it is not limited to a nitrogen atmosphere, and dehydration or dehydrogenation is performed in an inert gas atmosphere such as helium, neon, or argon. By heat - treating the oxide semiconductor layer at a temperature of 400 °C to 700 °C, dehydration and dehydrogenation of the oxide semiconductor layer can be achieved, and subsequent re - impregnation of water (H2O) can be prevented.

[0082]

[0083] Regarding an example of the mechanism of water desorption in the oxide semiconductor film, the following reaction pathway was analyzed (in the oxide semiconductor film, reactions not only as water but also as OH or H). An In - Ga - Zn - O - based amorphous film was used as the oxide semiconductor film.

[0084] Also, the optimal molecular structure in the ground state of the calculation model was calculated using the density functional theory (DFT). The total energy of DFT is the potential energy, the electrostatic energy between electrons, and the electronic It is expressed as the sum of the kinetic energy of the particles and the exchange-correlation energy that includes all the complex electron-electron interactions. In DFT, since the exchange-correlation interaction is approximated by a functional (function of a function) of the one-electron potential expressed by the electron density, the calculation is fast and highly accurate. Here, using the hybrid functional B3LYP, the weights of the parameters related to the exchange and correlation energies were defined. Also, as the basis functions, for indium atoms, gallium atoms, and zinc atoms, La nL2DZ (basis function obtained by adding a split valence basis system to the effective core potential of the Ne shell), and for other atoms, 6-311 (basis function of the triple split valence basis system using three contracted functions for each valence orbital) were applied. With the above-mentioned basis functions, for example, for a hydrogen atom, the 1s to 3s orbitals are considered, and for an oxygen atom, the 1s to 4s, 2p to 4p orbitals are considered. Furthermore, to improve the calculation accuracy, as a polarized basis system, a p function was added to the hydrogen atom and a d function was added to the oxygen atom. It is noted that Gaussian03 was used as the quantum chemistry calculation program. The calculation was performed using a high-performance computer (Altix4700 manufactured by SGI).

[0085] By heat treatment for dehydration or dehydrogenation, it is considered that -OHs contained in the oxide semiconductor film react with each other to generate H2O. Therefore, the water generation / desorption mechanism as shown in Fig. 39 was analyzed. In Fig. 39, since Zn is divalent, when both M1 and M2 or either one of them is Zn, one M'-O bond bonded to Zn is removed.

[0086]

[0087] ​​​​​​​​​​​ In Figure 39, M represents a metal atom, and the three types of In, Ga, and Zn apply. Initial state 1 In the initial state 1, -OH forms a coordination bond so as to crosslink M1 and M2. In the transition state 2, the H of -O H migrates to another -OH. In the intermediate state 3, the generated H2O molecule forms a coordination bond with the metal atom In the final state 4, the H2O molecule desorbs and moves away to infinity.

[0088] All combinations of (M1 - M2) are: 1. In - In, 2. Ga - Ga, 3. Zn - Zn, 4. In - Ga, 5. In - Zn, 6. Ga - Zn, and there are six such combinations. Therefore, calculations were performed for all combinations In this calculation, a cluster calculation using a calculation model in which M' was replaced with H was performed for the sake of simplifying the calculation.

[0089] In the calculation, an energy diagram corresponding to the reaction path in Figure 39 was obtained. Representing from all six combinations of ( M1 - M2), the calculation results for the case of 1. In - In are shown in Figure 40.

[0090] From Figure 40, it was found that the activation energy for water generation is 1.16 eV. When the generated water molecule desorbs, it becomes unstable by about 1.58 eV.

[0091] Conversely, when considering the reaction in Figure 40 from right to left, it can be regarded as a reaction in which water enters the oxide semiconductor film. Then, the water coordinated to the metal hydrolyzes to form two OH groups, and the activation energy of the reaction is 0.47 eV.

[0092] Similarly, for other combinations of (M1 - M2), the reaction paths were also analyzed. For cases 1 to 6 the activation energy (Ea [eV]) of the water generation reaction is shown in Table 1.

[0093]

Table 1

[0094] From Table 1, it can be seen that in the case of 1.In-In and 4.In-Ga, the water generation reaction is likely to occur. . On the other hand, in the case of 3.Zn-Zn, the water generation reaction is less likely to occur. From this, it is inferred that the water generation reaction mediated by Zn atoms tends to be less likely to occur.

[0095] Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Th ermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. In addition, the LRTA apparatus may be equipped with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element as well as a lamp. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be processed by heat treatment are used. Using the RTA method, heat treatment may be performed at 600 °C to 750 °C for several minutes. In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. In particular, for the oxide semiconductor layer, 400 °C

[0096] ​​​​​The heat treatment for dehydration and dehydrogenation carried out at ~700 °C is preferably performed in a nitrogen atmosphere with H2O of 20 ppm or less. Alternatively, the purity of nitrogen, or rare gases such as helium, neon, argon, etc. introduced into the heat treatment apparatus should be 6N (99.9999%) or higher, preferably 7N (9 9.99999%) or higher (i.e., the impurity concentration should be 1 ppm or less, preferably 0.1 ppm or less).

[0097] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur, resulting in microcrystals or polycrystals. For example, it may become an oxide semiconductor layer of microcrystals with a crystallization rate of 90% or more, or 80% or more. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor without a crystalline component.

[0098] The first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film 130 before it is processed into island-shaped oxide semiconductor layers 131 and 132. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus and a photolithography process is carried out.

[0099] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer can be carried out either after forming the oxide semiconductor layer, or after laminating the source electrode and the drain electrode on the oxide semiconductor layer, or after forming a passivation film on the source electrode and the drain electrode.

[0100] Also, the process of forming contact holes 118 and 119 in the gate insulating layer 102 as shown in Fig. 2(C) can be carried out after performing a dehydration or dehydrogenation treatment on the oxide semiconductor film 130.

[0101] Note that the etching of the oxide semiconductor film here is not limited to wet etching, and dry etching may be used.

[0102] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.) is preferable.

[0103] In addition, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0104] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that etching can be performed into a desired processed shape.

[0105] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0106] In addition, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material is purified, and the contained material is It may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0107] Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate according to the material so that etching can be performed into a desired processed shape.

[0108] Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layers 133 and 134 by sputtering or vacuum evaporation.

[0109] Examples of the material of the metal conductive film include elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or an alloy containing the above-described elements as components, or an alloy film formed by combining the above-described elements. The metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a Ti film, an aluminum film is laminated on the Ti film, and a Ti film is further formed thereon, etc. may be mentioned. Also, an alloy film in which a single or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc) are combined with Al, or a nitride film may be used.

[0110] When performing a heat treatment after forming the metal conductive film, it is preferable to endow the metal conductive film with heat resistance that can withstand this heat treatment.

[0111] Next, a fourth photolithography process is performed, and resist masks 136a, 136b, 13 Form 6c, 136d, 136e, and 136f, and remove unnecessary parts by etching the metal conductive film to form the source electrode layer 105a, drain electrode layer 105b, source electrode layer 165a, drain electrode layer 165b, connection electrode 120, and second terminal 122 (see Fig. 3(C ).). )

[0112] Note that when etching the metal conductive film, the oxide semiconductor layers 133 and 134 are not removed. Appropriately adjust the respective materials and etching conditions accordingly.

[0113] In this embodiment, a Ti film is used as the metal conductive film, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layers 133 and 134, and aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0114] In this fourth photolithography process, the connection electrode 120 and the second terminal 122, which are made of the same material as the source electrode layers 105a and 165a and the drain electrode layers 105b and 165b, are respectively formed at the terminal portions. Note that the second terminal 122 is electrically connected to the source wiring (the source wiring including the source electrode layers 105a and 165a). Also, the connection electrode 120 is formed in contact with the first terminal 121 at the contact hole 119 and is electrically connected.

[0115] Note that the resist masks 136a, 136b, 136c, 136d, 136e, and 136f for forming the source electrode layer and the drain electrode layer may be formed by the inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0116] ​​​​​​​​​Next, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f are removed, and an oxide insulating film 107 serving as a protective insulating film in contact with the oxide semiconductor layers 133 and 134 is formed.

[0117] At this stage, regions where the oxide semiconductor layers 133 and 134 are in contact with the oxide insulating film are formed, and among these regions, a region that overlaps with the gate electrode layer via the gate insulating layer and also overlaps with the oxide insulating film 107 becomes the channel formation region.

[0118] The oxide insulating film 107 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating film 107. If hydrogen is contained in the oxide insulating film 107, the intrusion of hydrogen into the oxide semiconductor layer or the extraction of oxygen in the oxide semiconductor layer by hydrogen occurs, resulting in a low-resistance (N-type) back channel in the oxide semiconductor layer and the formation of a parasitic channel. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating film 107 becomes a film that contains as little hydrogen as possible.

[0119] In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 107 by sputtering. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to room temperature. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon) or an oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide is formed by sputtering in an oxygen atmosphere using a silicon target. It is possible. The oxide insulator formed in contact with the oxide semiconductor layer whose resistance has been reduced by the first heat treatment film does not contain impurities such as moisture, hydrogen ions, and OH - and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum gallium oxide film, an aluminum oxide film, or an aluminum oxynitride film is used.

[0120] Next, a second heat treatment (preferably 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 4(A). ). For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 that overlap with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107.

[0121] By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer after film formation to reduce the resistance, a part of the oxide semiconductor layer is selectively made into an oxygen-excessive state.

[0122] As a result, in the oxide semiconductor layer 133, the channel formation region 166 that overlaps with the gate electrode layer 161 becomes of type I, and a high-resistance source region 167a that overlaps with the source electrode layer 165a and a high-resistance drain region 167b that overlaps with the drain electrode layer 165b are self-alignedly formed, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel formation region 116 that overlaps with the gate electrode layer 101 becomes of type I, and a high-resistance source region 117a that overlaps with the source electrode layer 105a and a high-resistance drain region 117b that overlaps with the drain electrode layer 105b are formed, and a high-resistance drain region that overlaps with the drain electrode layer 105b ​​​The region 117b is self-alignedly formed, and the oxide semiconductor layer 103 is formed.

[0123] Note that in the stacked oxide semiconductor layers 103 and 163 overlapping with the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a), by forming the high-resistance drain regions 117b and 167b ( or the high-resistance source regions 117a and 167a), the reliability when forming a circuit can be improved. Specifically, by forming the high-resistance drain regions 117b and 167b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layers 105b and 165b to the high-resistance drain regions 117b , 167b, and the channel formation regions 116 and 166. Therefore, when operating by connecting to a wiring for supplying the high power supply potential VDD to the drain electrode layers 105b and 165b, even if a high electric field is applied between the gate electrode layers 101 and 161 and the drain electrode layers 105b and 165b, the high-resistance drain region serves as a buffer and no local high electric field is applied, and a configuration can be obtained in which the breakdown voltage of the transistor is improved.

[0124] Also, in the oxide semiconductor layer stacked with the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a), by forming the high-resistance drain regions 117b and 167b (or the high-resistance source regions 117a and 167a), the leakage current in the channel formation regions 116 and 166 when forming a circuit can be reduced.

[0125] In this embodiment, after forming a silicon oxide film as the oxide insulating film 107 by a sputtering method, heat treatment is performed at 250°C to 350°C, and the oxide between the source region and the drain region From the exposed portion of the semiconductor layer (channel formation region), oxygen is infiltrated and diffused into the oxide semiconductor layer. This is done. By forming a silicon oxide film by sputtering, excess oxygen can be included in the silicon oxide film, and this oxygen can be infiltrated and diffused into the oxide semiconductor layer by heat treatment. By the infiltration and diffusion of oxygen into the oxide semiconductor layer, the channel formation region can be made highly resistive (i-type). Thereby, a normally-off thin film transistor can be obtained.

[0126] Through the above steps, on the same substrate, thin film transistor 180 can be fabricated in the drive circuit section, and thin film transistor 170 can be fabricated in the pixel section. Thin film transistors 170 and 180 are bottom gate type thin film transistors including an oxide semiconductor layer including a high-resistance source region, a high-resistance drain region, and a channel formation region. Therefore, thin film transistors 170 and 18 0 have a configuration in which the high-resistance drain region or the high-resistance source region serves as a buffer even when a high electric field is applied, so that a local high electric field is not applied, and the breakdown voltage of the transistor is improved. By forming the drive circuit section and the pixel section on the same substrate, the connection wiring between the drive circuit and the external signal can be shortened, and the semiconductor device can be miniaturized and the cost can be reduced.

[0127] By forming the drive circuit section and the pixel section on the same substrate, the connection wiring between the drive circuit and the external signal can be shortened, and the semiconductor device can be miniaturized and the cost can be reduced.

[0128] A protective insulating layer may be further formed on the oxide insulating film 107. For example, a silicon nitride film is formed using the RF sputtering method. Since the RF sputtering method has good mass productivity, it is preferable as a film formation method for the protective insulating layer. The protective insulating layer uses an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH and blocks these from entering from the outside. - etc. impurities, and uses an inorganic insulating film that blocks these from entering from the outside. Use silicon films, aluminum nitride films, silicon oxynitride films, aluminum oxynitride films, etc.

[0129] Next, perform a fifth photolithography process to form a resist mask, and form a contact hole 125 reaching the drain electrode layer 105b by etching of oxide insulating film 1 07, and remove the resist mask (see Fig. 4(B)). Also, by the etching here, a contact hole 127 reaching the second terminal 122 and a contact hole 126 reaching the connection electrode 120 are also formed. Further, the resist mask for forming the contact hole may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0130] Next, form a conductive film having translucency. As the material of the conductive film having translucency, indium oxide (In2O3), indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO), etc. are formed using a sputtering method, a vacuum evaporation method, or the like. As other materials of the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film, a Zn-O-based non-single crystal film containing nitrogen, or a Sn-Zn-O-based non-single crystal film containing nitrogen may be used. The composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, larger than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the non-single crystal film is larger than the composition ratio (atomic%) of nitrogen in the non-single crystal film. The etching treatment of such materials is performed with a hydrochloric acid-based solution. However, particularly for the etching of ITO, residues are likely to occur, so the etching Even indium oxide-zinc oxide alloy (In2O3-ZnO) can be used to improve processability. This is acceptable.

[0131] Note that the unit of the composition ratio of the conductive film having translucency is atomic %, and it shall be evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0132] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions of the conductive film having translucency are removed by etching to form the pixel electrode layer 110, the conductive layer 111, and the terminal electrodes 128 and 129, and the resist mask is removed. A cross-sectional view at this stage is shown in FIG. 4( C). Note that the plan view at this stage corresponds to FIG. 5.

[0133] Also, in this sixth photolithography process, a holding capacitance is formed by the capacitance wiring 108 and the pixel electrode layer 110, using the gate insulating layer 102 and the oxide insulating film 107 in the capacitance portion as dielectrics.

[0134] A holding capacitance 147, which is a holding capacitance formed by using the gate insulating layer 102 as a dielectric and formed by the capacitance wiring and the capacitance electrode (also referred to as the capacitance electrode layer), can also be formed on the same substrate. Also, without providing the capacitance wiring, a holding capacitance may be formed by overlapping the pixel electrodes with the gate wiring of adjacent pixels via the protective insulating film and the gate insulating layer.

[0135] The terminal electrodes 128 and 129 formed in the terminal portion serve as electrodes or wirings for connection to the FPC. The terminal electrode 128 formed on the first terminal 121 via the connection electrode 120 serves as a terminal electrode for connection that functions as an input terminal of the gate wiring. The second terminal 122 has a shape formed thereon​​​​ The formed terminal electrode 129 is a connection terminal electrode that functions as an input terminal of the source wiring. It is.

[0136] In addition, FIGS. 11(A1) and 11(A2) respectively show a top view and a cross-sectional view of the gate wiring terminal portion at this stage. FIG. 11(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 11(A2). In FIG. 11(A1), the conductive film 155 formed on the oxide insulating film 107 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 11(A1), in the terminal portion, a first terminal 151 formed of the same material as the gate wiring and a connection electrode 153 formed of the same material as the source wiring overlap and are directly connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. connected in conduction through a contact hole provided in the oxide insulating film 107. In FIG. 11(A1), in the terminal portion, a first terminal 151 formed of the same material as the gate wiring and a connection electrode 153 formed of the same material as the source wiring overlap and are directly connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. In FIG. 11(A1), in the terminal portion, a first terminal 151 formed of the same material as the gate wiring and a connection electrode 153 formed of the same material as the source wiring overlap and are directly connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107.

[0137] In addition, FIGS. 11(B1) and 11(B2) respectively show a top view and a cross-sectional view of the source wiring terminal portion. Also, FIG. 11(B1) corresponds to a cross-sectional view taken along line D1-D2 in FIG. 11(B2). In FIG. 11(B1), the conductive film 155 formed on the oxide insulating film 107 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 11(B1), in the terminal portion, an electrode 156 formed of the same material as the gate wiring overlaps via the gate insulating layer 102 below a second terminal 150 that is electrically connected to the source wiring. The electrode 1 connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. In FIG. 11(B1), in the terminal portion, an electrode 156 formed of the same material as the gate wiring overlaps via the gate insulating layer 102 below a second terminal 150 that is electrically connected to the source wiring. The electrode 1 connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. 56 is not electrically connected to the second terminal 150. If the electrode 156 is set to a potential different from that of the second terminal 150, such as floating, GND, 0V, etc., for noise countermeasures connected in conduction through the gate insulating layer 102. Further, the connection electrode 153 and the conductive film 155 are directly connected in conduction through a contact hole provided in the oxide insulating film 107. It is possible to form a capacitor for the purpose of capacitance or electrostatic countermeasures. Also, the second terminal 150 is electrically connected to the conductive film 155 via the oxide insulating film 107.

[0138] A plurality of gate wirings, source wirings, and capacitor wirings are arranged according to the pixel density. Also, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal may be set to any number, and the implementer may appropriately determine it.

[0139] In this way, through six photolithography processes, using six photomasks, a driving circuit portion having thin film transistors 180, a pixel portion having thin film transistors 170, a capacitor 147 having a holding capacitance, and an external extraction terminal portion can be completed. The thin film transistors and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and it can be used as one substrate for manufacturing an active matrix type display device. In this specification, such a substrate is referred to as an active matrix substrate for convenience. When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the

[0140] counter substrate are fixed. A common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. [[ID=3?]]

[0141] ​​​​ An insulating layer functioning as an alignment film is formed on the oxide insulating film 107, the conductive layer 111, and the pixel electrode layer 110. Form 191.

[0142] A colored layer 195, a counter electrode layer 194, and an insulating layer 19 functioning as an alignment film are formed on the counter substrate 190. The substrate 100 and the counter substrate 190 are connected to each other to adjust the cell gap of the liquid crystal display device. The liquid crystal layer 192 is sandwiched between the spacers and bonded together with a sealing material (not shown). The lamination step may be carried out under reduced pressure.

[0143] The sealing material typically uses visible light curing, ultraviolet curing or thermosetting resin. It is preferable to use an acrylic resin, an epoxy resin, an amine resin, or the like. In addition, photopolymerization initiators (typically ultraviolet light), heat curing agents, fillers, and coupling agents can be used. The composition may also contain a stimulating agent.

[0144] The liquid crystal layer 192 is formed by sealing a liquid crystal material in the gap. A dispenser method (dropping method) may be used in which the adhesive is dropped before bonding the adhesive to the facing substrate 190. After bonding the substrate 100 and the opposing substrate 190 together, liquid crystal is injected using capillary action. The liquid crystal material is not particularly limited, and various materials can be used. In addition, if a material exhibiting a blue phase is used as the liquid crystal material, the alignment film becomes unnecessary. This can be done.

[0145] A polarizing plate 196a is provided on the outer side of the substrate 100, and a polarizing plate 196b is provided on the outer side of the counter substrate 190. Thus, the transmissive liquid crystal display device of this embodiment mode can be manufactured (see FIG. 1).

[0146] In addition, although not shown in this embodiment, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a phase difference member, an antireflection member, etc. are provided as appropriate. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light emitting diode, etc. may be used as the light source.

[0147] In an active matrix type liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, whereby optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by the observer as the display pattern .

[0148] In video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there is a problem that afterimages occur, and also, blurring of the video occurs. To improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion in which full-screen black display is performed every other frame.

[0149] Also, there is a driving technique called so-called double-speed driving in which the video characteristics are improved by setting the vertical synchronization frequency to 1.5 times the normal value, preferably 2 times or more.

[0150] Also, to improve the video characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light-emitting diode) light sources or a plurality of EL light sources, etc., and there is also a driving technique in which each light source constituting the surface light source is driven to blink intermittently within one frame period. As the surface light source three or more types of LEDs may be used, or white light-emitting LEDs may be used. Independently Since a plurality of LEDs can be controlled, it is also possible to synchronize the light emission timing of the LEDs in accordance with the switching timing of the optical modulation of the liquid crystal layer. This driving technique can partially turn off the LEDs, so that particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. By combining these driving techniques, it is possible to improve display characteristics such as the video characteristics of the liquid crystal display device more than before. By forming a thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, by forming an oxide insulating film in contact with the oxide semiconductor layer by the above method, it is possible to fabricate and provide a thin film transistor having stable electrical characteristics. Therefore, it is possible to provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0151] Since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are arranged. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0152] Since a plurality of LEDs can be controlled, it is also possible to synchronize the light emission timing of the LEDs in accordance with the switching timing of the optical modulation of the liquid crystal layer. This driving technique can partially turn off the LEDs, so that particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. By forming a thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, by forming an oxide insulating film in contact with the oxide semiconductor layer by the above method, it is possible to fabricate and provide a thin film transistor having stable electrical characteristics. Therefore, it is possible to provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are arranged. Since a plurality of LEDs can be controlled, it is also possible to synchronize the light emission timing of the LEDs in accordance with the switching timing of the optical modulation of the liquid crystal layer. This driving technique can partially turn off the LEDs, so that particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved.

[0153] Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are arranged. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0154] Since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are arranged. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are arranged. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Provided that a surge voltage is applied to a scanning line, a signal line, and a capacitance bus line due to static electricity or the like, so that a pixel transistor or the like is configured not to be damaged. Therefore, the protection circuit is configured to release charge to a common wiring when a surge voltage is applied. Further, the protection circuit is composed of a non-linear element arranged in parallel between the scanning line and the common wiring. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can be formed in the same process as the thin film transistor 170 in the pixel portion. For example, by connecting the gate terminal and the drain terminal of the transistor, the same characteristics as those of a diode can be obtained. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0155]

[0156] (Embodiment 2) In this embodiment, in Embodiment 1, an example in which an oxide conductive layer is provided as a source region and a drain region between an oxide semiconductor layer and a source electrode layer or a drain electrode layer is shown in FIGS. 6 and 7. Therefore, the rest can be performed in the same manner as in Embodiment 1, and the description of the same parts or parts having the same functions as those in Embodiment 1, and the repetition of the steps is omitted. Further, FIGS. 6 and 7 are the same as FIGS. 1 to 5 except that some of the steps are different, so the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0157] First, according to Embodiment 1, the steps up to FIG. 3(B) in Embodiment 1 are performed. FIG. 6( A) is the same as FIG. 3(B).

[0158] An oxide conductive film 140 is formed on the dehydrated or dehydrogenated oxide semiconductor layers 133 and 134, and a metal conductive film made of a metal conductive material is laminated on the oxide conductive film 140. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process.

[0159] The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X > 0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X > 0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X > 0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X > 0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. The method of forming the oxide conductive film 140 uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method. As the material of the oxide conductive film 140, those containing zinc oxide as a component are preferred, and those not containing indium oxide are preferably used. As such an oxide conductive film 140, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X > 0) that inhibits crystallization is included in the oxide conductive film to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process.

[0160] Next, a fourth photolithography process is performed to form resist masks 136a, 136b, 136c, 136d, 136e, and 136f, and unnecessary portions of the metal conductive film are removed by etching to form source electrode layers 105a, drain electrode layers 105b, source electrode layers 165a, drain electrode layers 165b, connection electrodes 120, and second terminals 122 (see Fig. 6(B)). Next, a fourth photolithography process is performed to form resist masks 136a, 136b, 136c, 136d, 136e, and 136f, and unnecessary portions of the metal conductive film are removed by etching to form source electrode layers 105a, drain electrode layers 105b, source electrode layers 165a, drain electrode layers 165b, connection electrodes 120, and second terminals 122 (see Fig. 6(B)). Next, a fourth photolithography process is performed to form resist masks 136a, 136b, 136c, 136d, 136e, and 136f, and unnecessary portions of the metal conductive film are removed by etching to form source electrode layers 105a, drain electrode layers 105b, source electrode layers 165a, drain electrode layers 165b, connection electrodes 120, and second terminals 122 (see Fig. 6(B)). Next, a fourth photolithography process is performed to form resist masks 136a, 136b, 136c, 136d, 136e, and 136f, and unnecessary portions of the metal conductive film are removed by etching to form source electrode layers 105a, drain electrode layers 105b, source electrode layers 165a, drain electrode layers 165b, connection electrodes 120, and second terminals 122 (see Fig. 6(B)). Next, a fourth photolithography process is performed to form resist masks 136a, 136b, 136c, 136d, 136e, and 136f, and unnecessary portions of the metal conductive film are removed by etching to form source electrode layers 105a, drain electrode layers 105b, source electrode layers 165a, drain electrode layers 165b, connection electrodes 120, and second terminals 122 (see Fig. 6(B)).

[0161] During the etching of the metal conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide conductive film 140 and the oxide semiconductor layers 133 and 134 are not removed. During the etching of the metal conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide conductive film 140 and the oxide semiconductor layers 133 and 134 are not removed.

[0162] Next, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f are removed, and using the source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, and the drain electrode layer 165b as masks, the oxide conductive film 140 is etched to form the oxide conductive layers 164a, 164b, the oxide conductive layers 104a, 104b (see Fig. 6(C)). The oxide conductive film 140 containing zinc oxide can be easily etched using an alkaline solution such as a resist stripper. Also, in the same process, the oxide conductive layers 138 and 139 are formed at the terminal portions.

[0163] An etching process is performed to divide the oxide conductive film in order to form the channel formation region by utilizing the difference in the etching rate between the oxide semiconductor layer and the oxide conductive film. By utilizing the fact that the etching rate of the oxide conductive film is faster than that of the oxide semiconductor layer, the oxide conductive film on the oxide semiconductor layer is selectively etched. Therefore, it is preferable to remove the resist masks 136a, 136b, 136c, 136d, 136e, and 136f by an ashing process. In the case of etching using a stripper, the etching conditions (type of etchant, concentration, etching time) are appropriately adjusted so that the oxide conductive film 140 and the oxide semiconductor layers 133 and 134 are not over-etched.

[0164] As in this embodiment, after etching the oxide semiconductor layer into an island shape, the oxide conductive film and the metal conductive film are laminated, and a wiring pattern including the source electrode layer and the drain electrode layer is formed using the same mask.

[0165] ​​​​​​By etching, an oxide conductive film can be left under the wiring pattern of the metal conductive film. This is possible.

[0166] Even in the contact between the gate wiring (conductive layer 162) and the source wiring (drain electrode layer 165b), since the oxide conductive layer 164b is formed under the source wiring, the oxide conductive layer 164b serves as a buffer, which is preferable. Further, it is preferable not to form an oxide that is insulating from the metal. This is preferable. This is preferable.

[0167] An oxide insulating film 107 serving as a protective insulating film in contact with the oxide semiconductor layers 133 and 134 is formed. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 107 by sputtering. This is done using the sputtering method.

[0168] Next, a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107. This is done. This is done. This is done.

[0169] By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer after film formation to reduce the resistance, a part of the oxide semiconductor layer is selectively made to be in an oxygen-excessive state. This is done. This is done.

[0170] As a result, in the oxide semiconductor layer 133, the channel formation region 166 overlapping with the gate electrode layer 161 becomes of type I, and the high-resistance region overlapping with the source electrode layer 165a and the oxide conductive layer 164a This is done. The anti-source region 167a and the high-resistance drain region 167b overlapping the drain electrode layer 165b and the oxide conductive layer 164b are self-alignedly formed, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel formation region 116 becomes of type I, and the high-resistance source region 117a overlapping the source electrode layer 105a and the oxide conductive layer 104a and the high-resistance drain region 117b overlapping the drain electrode layer 105b and the oxide conductive layer 104b are self-alignedly formed, and the oxide semiconductor layer 103 is formed. The oxide conductive layers 104b and 164b disposed between the oxide semiconductor layers 163 and 103 and the drain electrode layers 105b and 165b made of a metal material function also as a low-resistance drain region (also referred to as an LRN (Low Resistance N-type conductivity) region, an LRD (Low Resistance Drain) region). Similarly, the oxide conductive layers 104a and 164a disposed between the oxide semiconductor layers 163 and 103 and the source electrode layers 105a and 165a made of a metal material function also as a low-resistance source region (also referred to as an LRN (Low Resistance N-type conductivity) region, an LRS (Low Resistance Source) region). By configuring the oxide semiconductor layer, the low-resistance drain region, and the drain electrode layer made of a metal material, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration of the low-resistance drain region is larger than that of the high-resistance drain region (HRD region), for example, 1×10

[0171] / cm or more and 1×10 / cm or less. The oxide conductive layers 104b and 164b disposed between the oxide semiconductor layers 163 and 103 and the drain electrode layers 105b and 165b made of a metal material function also as a low-resistance drain region (also referred to as an LRN (Low Resistance N-type conductivity) region, an LRD (Low Resistance Drain) region). Similarly, the oxide conductive layers 104a and 164a disposed between the oxide semiconductor layers 163 and 103 and the source electrode layers 105a and 165a made of a metal material function also as a low-resistance source region (also referred to as an LRN (Low Resistance N-type conductivity) region, an LRS (Low Resistance Source) region). By configuring the oxide semiconductor layer, the low-resistance drain region, and the drain electrode layer made of a metal material, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration of the low-resistance drain region is larger than that of the high-resistance drain region (HRD region), for example, 1×10 / cm or more and 1×10 / cm or less. 20 / cm 3 or more and 1×10 21 / cm 3It is preferable that it is within the following range. It is preferable.

[0172] Through the above steps, on the same substrate, a thin-film transistor 181 can be formed in the drive circuit section, and a thin-film transistor 171 can be formed in the pixel section. The thin-film transistors 171 and 181 are bottom-gate type thin-film transistors including an oxide semiconductor layer containing a high-resistance source region, a high-resistance drain region, and a channel formation region. Therefore, the thin-film transistors 171 and 181 are configured such that even when a high electric field is applied, the high-resistance drain region or the high-resistance source region serves as a buffer so that a local high electric field is not applied, improving the breakdown voltage of the transistor.

[0173] In the capacitor section, a capacitor 146 is formed by laminating a capacitor wiring 108, a gate insulating layer 102, an oxide conductive layer 104b, an oxide conductive layer formed in the same process, a metal conductive layer formed in the same process as the drain electrode layer 105b, and an oxide insulating film 107.

[0174] Next, a planarization insulating layer 109 is formed on the oxide insulating film 107. In this embodiment, the planarization insulating layer 109 is formed only in the pixel section. As the planarization insulating layer 109, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the planarization insulating layer 109 may be formed by laminating a plurality of insulating films formed of these materials. ), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used.

[0175] Note that the siloxane-based resin is Si-O-S formed using a siloxane-based material as a starting material. It corresponds to a resin containing i-bonds. As substituents for the siloxane resin, organic groups (e.g., alkyl groups and aryl groups) or fluoro groups may be used. Further, the organic group may have a fluoro group in it.

[0176] The method for forming the planarization insulating layer 109 is not particularly limited, and depending on the material, sputtering method , SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater , knife coater, etc. can be used. In this embodiment, the planarization insulating layer 109 is formed using photosensitive acrylic.

[0177] Next, a fifth photolithography process is performed to form a resist mask, and contact holes 125 that reach the drain electrode layer 105b are formed by etching the planarization insulating layer 109 and the oxide insulating film 107, and the resist mask is removed (see Fig. 6(D)). Also, contact holes 127 that reach the second terminal 122 and contact holes 126 that reach the connection electrode 120 are also formed by the etching here.

[0178] Next, a conductive film having translucency is formed, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 110, the conductive layer 11 1, the terminal electrodes 128, 129, and the resist mask is removed (see Fig. 7(A)). .

[0179] Similar to Embodiment 1, the counter substrate 190 is bonded with the liquid crystal layer 192 sandwiched therebetween to fabricate the liquid crystal display device of this embodiment (see Fig. 7(B)).

[0180] As a source region and a drain region, by providing an oxide conductive layer between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, the resistance of the source region and the drain region can be reduced, and the transistor can operate at high speed. Using an oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (driver circuit). This is because the contact between a metal electrode (such as Ti) and an oxide conductive layer can reduce the contact resistance compared to the contact between a metal electrode (such as Ti

[0181] ) and an oxide semiconductor layer. In addition, molybdenum (Mo) used as part of the wiring material in a liquid crystal panel (for example, Mo / Al / Mo) has a high contact resistance with the oxide semiconductor layer, which has been a problem. This is because Mo is less likely to be oxidized compared to Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer does not become n-type. However, even in such a case, by interposing an oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer,

[0182] the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (driver circuit) can be improved. Since the channel length of the thin film transistor is determined during the etching of the oxide conductive layer, shorter channel formation can be achieved. For example, by shortening the channel length to 0.1 μm or more and 2 μm or less,

[0183] (Embodiment 3) In this embodiment, in Embodiment 1 or Embodiment 2, an oxide conductive layer is provided as a source region and a drain region between the oxide semiconductor layer and the source electrode layer or the drain electrode layer. Other examples thereof are shown in FIGS. 8 and 9. Therefore, others can be carried out in the same manner as in Embodiment 1 or Embodiment 2, and the description of the same parts or parts having the same functions as in Embodiment 1 or Embodiment 2 and the repeated description of the process is omitted. Also, FIGS. 8 and 9 are the same as FIGS. 1 to 7 except that the processes are partially different, so the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0184] First, according to Embodiment 1, a metal conductive film is formed on the substrate 100, and the metal conductive film is etched using a resist mask formed by a first photolithography process to form a first terminal 121, a gate electrode layer 161, a conductive layer 162, a gate electrode layer 101, and a capacitor wiring 108.

[0185] Next, a gate insulating layer 102 is formed on the first terminal 121, the gate electrode layer 161, the conductive layer 162, the gate electrode layer 101, and the capacitor wiring 108, and an oxide semiconductor film and an oxide conductive film are laminated. The gate insulating layer, the oxide semiconductor film, and the oxide conductive film can be continuously formed without being exposed to the atmosphere.

[0186] A resist mask is formed on the oxide conductive film by a second photolithography process. Using the resist mask, the gate insulating layer, the oxide semiconductor film, and the oxide conductive film are etched to form a contact hole 119 reaching the first terminal 121 and a contact hole 118 reaching the conductive layer 162.

[0187] The resist mask formed by the second photolithography process is removed, and then a resist mask is formed on the oxide conductive film by a third photolithography process. The third photolithography process An island-shaped oxide semiconductor layer and an island-shaped oxide conductive layer are formed using a resist mask in a deposition process.

[0188] In this way, in a state where the oxide semiconductor film and the oxide conductive film are stacked on the entire surface of the gate insulating layer, When a step of forming a contact hole in the gate insulating layer is performed, a resist mask is formed on the surface of the gate insulating layer. Since the mask does not come into direct contact with the gate insulating layer, contamination of the surface (such as adhesion of impurities) can be prevented. Therefore, the state of the interfaces between the gate insulating layer and the oxide semiconductor film and between the gate insulating layer and the oxide conductive film can be improved. This leads to improved reliability.

[0189] Next, the oxide semiconductor layer and the oxide conductive layer are stacked together, and then subjected to heat treatment for dehydration and dehydrogenation. By performing heat treatment at a temperature of 400 to 700°C, the oxide semiconductor layer is dehydrated and dehydrated. This hydrogenates the material and prevents subsequent re-impregnation with water (H2O).

[0190] This heat treatment allows the oxide conductive layer to be crystallized as long as it does not contain a crystallization inhibitor such as silicon oxide. The oxide conductive layer is crystallized by this process, and the crystals of the oxide conductive layer grow in a columnar shape relative to the underlying surface. As a result, in order to form the source electrode layer and the drain electrode layer, the gold layer on the oxide conductive layer is When etching a metal conductive film, the formation of undercuts can be prevented.

[0191] In addition, the conductivity of the oxide conductive layer is improved by heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer. Note that only the oxide conductive layer can be heat-treated at a lower temperature than the oxide semiconductor layer. It's okay to understand that.

[0192] In addition, the first heat treatment of the oxide semiconductor layer and the oxide conductive layer is performed to form an island-shaped oxide semiconductor layer and This can also be performed on the oxide semiconductor film and the oxide conductive film before processing into the oxide conductive layer. In this case, after the first heat treatment, the substrate is taken out of the heating device, and a photolithography process is performed.

[0193] In the above process, the oxide semiconductor layers 133 and 134 and the oxide conductive layers 142 and 143 are obtained (see Fig. 8(A)). The oxide semiconductor layer 133 and the oxide conductive layer 142, and the oxide semiconductor layer 134 and the oxide conductive layer 143 are each an island-like stack formed using the same mask .

[0194] Next, a fourth photolithography process is performed to form resist masks 136a, 136b, 13 6c, 136d, 136e, and 136f, and unnecessary portions of the metal conductive film are removed by etching to form the source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, the drain electrode layer 165b, the connection electrode 120, and the second terminal 122 (see Fig. 8(B ). )

[0195] Note that during the etching of the metal conductive film, the materials and etching conditions are appropriately adjusted so that the oxide conductive layers 142 and 143 and the oxide semiconductor layers 133 and 134 are not removed. .

[0196] Next, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f are removed, and the oxide conductive layers 142 and 143 are etched using the source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, and the drain electrode layer 165b as masks to form the oxide conductive layers 164a and 164b and the oxide conductive layers 104a and 104b (Fig. 8(C) ). The oxide conductive layers 142 and 143 containing zinc oxide are formed by, for example, removing the resist. It can be easily etched using alkaline solutions such as ethyl alcohol.

[0197] Therefore, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f The removal of the film is preferably performed by an ashing process. In this case, the oxide conductive layers 142 and 143 and the oxide semiconductor layers 133 and 134 are excessively etched. To prevent chipping, the etching conditions (type of etchant, concentration, etching time) Adjust as appropriate.

[0198] The oxide insulating film 107 serving as a protective insulating film in contact with the oxide semiconductor layers 133 and 134 is formed. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating film 107. The film is formed using a deposition method.

[0199] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. The oxide semiconductor layers 133 and 134 are in contact with the oxide insulating film 107. It is heated in this state.

[0200] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor layer is selectively treated with an oxygen-excess This is the state.

[0201] As a result, in the oxide semiconductor layer 133, a channel formation region overlapping with the gate electrode layer 161 is formed. Region 166 becomes of type I, and a high-resistance source region 167a overlapping with the source electrode layer 165a and the oxide conductive layer 164a, and a high-resistance drain region 167b overlapping with the drain electrode layer 165b and the oxide conductive layer 164b are self-alignedly formed, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, a channel formation region 116 overlapping with the gate electrode layer 101 becomes of type I, and a high-resistance source region 117a overlapping with the source electrode layer 105a and the oxide conductive layer 104a, and a high-resistance drain region 117b overlapping with the drain electrode layer 105b and the oxide conductive layer 104b are self-alignedly formed, and the oxide semiconductor layer 103 is formed.

[0202] The oxide conductive layers 104b, 164b disposed between the oxide semiconductor layers 163, 103 and the drain electrode layers 105b, 165b made of a metal material also function as low-resistance drain regions (also referred to as LRN regions, LRD regions). Similarly, the oxide conductive layers 104a, 164a disposed between the oxide semiconductor layers 163, 103 and the source electrode layers 105a, 165a made of a metal material also function as low-resistance source regions (also referred to as LRN regions, LRS regions). By configuring the oxide semiconductor layer, the low-resistance drain region, and the drain electrode layer made of a metal material, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration of the low-resistance drain region is larger than that of the high-resistance drain region (HRD region), and is preferably in the range of 1×10 20 / cm 3 or more and 1×10 21 / cm 3 or less.

[0203] Through the above steps, on the same substrate, a thin film transistor 182 and a pixel portion are formed in the driving circuit portion a thin film transistor 172 can be fabricated. The thin film transistors 172 and 182 are bottom gate type thin film transistors including an oxide semiconductor layer containing a high resistance source region, a high resistance drain region, and a channel formation region . Therefore, the thin film transistors 172 and 18 2 are configured such that even when a high electric field is applied, the high resistance drain region or the high resistance source region serves as a buffer and a local high electric field is not applied, improving the breakdown voltage of the transistor.

[0204] Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 125 reaching the drain electrode layer 105b is formed by etching the oxide insulating film 1 07, and the resist mask is removed (see Fig. 8(D)). Also, by the etching here, a contact hole 127 reaching the second terminal 122 and a contact hole 126 reaching the connection electrode 120 are also formed.

[0205] Next, a conductive film having translucency is formed, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 110, the conductive layer 11 1, the terminal electrodes 128 and 129, and the resist mask is removed (see Fig. 9(A)). .

[0206] Similar to Embodiment 1, the counter substrate 190 is bonded with the liquid crystal layer 192 interposed therebetween to fabricate the liquid crystal display device of this embodiment (see Fig. 9(B)).

[0207] As the source region and the drain region, an oxide conductive layer is formed by using an oxide semiconductor layer, a source electrode layer, and By disposing it between the drain electrode layer, the resistance of the source region and the drain region can be reduced. This enables high-speed operation of the transistor. Using an oxide conductive layer as the source region and the drain region is effective for improving the frequency characteristics of the peripheral circuit (driver circuit). Compared with the contact between a metal electrode (such as Ti) and an oxide semiconductor layer, the contact between a metal electrode (such as Ti) and an oxide conductive layer can reduce the contact resistance.

[0208] Interposing an oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer can reduce the contact resistance and improve the frequency characteristics of the peripheral circuit (driver circuit).

[0209] Since the channel length of the thin-film transistor is determined during the etching of the oxide conductive layer, the channel length can be made shorter. For example, the channel length L can be shortened to 0.1 μm or more and 2 μm or less to increase the operating speed.

[0210] (Embodiment 4) Here, in a liquid crystal display device in which a liquid crystal layer is enclosed between a first substrate and a second substrate, an example of forming a common connection portion on the first substrate for electrically connecting to a counter electrode provided on the second substrate is shown. Note that a thin-film transistor is formed as a switching element on the first substrate, and the manufacturing process of the common connection portion is made common with the manufacturing process of the switching element in the pixel portion so as to be formed without complicating the process.

[0211] The common connection portion is disposed at a position overlapping with a sealing material for adhering the first substrate and the second substrate, and electrical connection with the counter electrode is performed through conductive particles contained in the sealing material. Alternatively A common connection portion is provided at a location that does not overlap with the sealing material (excluding the pixel portion), and a paste containing conductive particles is separately provided so as to overlap with the common connection portion to make an electrical connection with the counter electrode.

[0212] FIG. 36(A) is a cross-sectional structure diagram of a semiconductor device in which a thin film transistor and a common connection portion are formed on the same substrate.

[0213] In FIG. 36(A), the thin film transistor 220 that is electrically connected to the pixel electrode layer 227 is a channel-etch type thin film transistor disposed in the pixel portion. In the present embodiment, the same structure as the thin film transistor 170 of Embodiment 1 is used.

[0214] Further, FIG. 36(B) is a diagram showing an example of a top view of the common connection portion, and a cross-sectional view of the common connection portion along the chain line C3-C4 in the figure corresponds to FIG. 36(A). In FIG. 36(B), the same parts as those in FIG. 36(A) are denoted by the same reference numerals for explanation.

[0215] The common potential line 210 is provided on the gate insulating layer 202 and is formed of the same material and in the same process as the source electrode layer and the drain electrode layer of the thin film transistor 220.

[0216] Further, the common potential line 210 is covered with the protective insulating layer 203, and the protective insulating layer 203 has a plurality of openings at positions overlapping the common potential line 210. These openings are formed in the same process as the contact holes that connect the drain electrode layer of the thin film transistor 2 20 and the pixel electrode layer 227.

[0217] Here, since the area sizes are greatly different, the contact holes in the pixel portion and the common ​​​​​​In addition, in FIG. 36(A), the opening of the pixel portion is also called the opening of the connection portion. The connection parts are not shown to the same scale. For example, the length of the chain line C3-C4 of the common connection part is 50 0 μm, whereas the width of a thin film transistor is less than 50 μm, and in reality, 36(A) shows the area of the pixel section and the common connection section for ease of understanding. The following parts are shown at different scales.

[0218] The common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made of the same materials and in the same process as

[0219] In this way, the manufacturing process of the common connection portion is common to the manufacturing process of the switching element of the pixel portion. It is preferable that the common potential line be made of metal wiring to reduce wiring resistance.

[0220] A first substrate on which a pixel section and a common connection section are provided and a second substrate having an opposing electrode are then Secure it in place using a sealant.

[0221] When the sealing material contains conductive particles, the sealing material and the common connection part are overlapped with each other. For example, in a small LCD panel, the diagonal corners of the pixel area are aligned. Two common connection parts are placed over the sealing material. In addition, in large LCD panels, Four or more common connections are arranged overlapping the sealant.

[0222] The common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material. The electrode is electrically connected to the counter electrode of the substrate.

[0223] When using the liquid crystal injection method, a pair of substrates are fixed together with a sealant, and then liquid crystal is injected between the pair of substrates. Inject. When using the liquid crystal droplet method, a sealing material is applied on the second substrate or the first substrate and the liquid crystal is dropped, and then the pair of substrates are bonded together under reduced pressure.

[0224] In addition, in this embodiment, an example of a common connection portion electrically connected to the counter electrode is shown, but particularly it is not limited, and it can be used for a connection portion connected to other wirings or a connection portion connected to an external connection terminal or the like. It can be.

[0225] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0226] (Embodiment 5) In this embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of Embodiment 1 is shown in FIG. 10. Since FIG. 10 is the same as FIGS. 1 to 5 except for the part where the process is partially different, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0227] First, according to Embodiment 1, a gate electrode layer, a gate insulating layer, and an oxide semiconductor film 130 are formed on the substrate, and the oxide semiconductor film 130 is processed into island-shaped oxide semiconductor layers 131 and 132 by a second photolithography process.

[0228] Next, dehydration or dehydrogenation of the oxide semiconductor layers 131 and 132 is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400 ° C or higher and lower than the distortion point of the substrate, preferably 42 5 ° C or higher. Note that if it is 425 ° C or higher, the heat treatment time may be 1 hour or less, but if it is less than 425 ° C, the heat treatment time will be longer than 1 hour. Here, the substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and the oxide semiconductor layer is placed in a nitrogen atmosphere.​​​​ After performing the heat treatment, without exposing to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer. Then, high-purity oxygen gas, high-purity N2O gas , or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) is introduced into the same furnace for cooling . It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Or, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower).

[0229] Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Th ermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. An LRTA apparatus is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Also, an LR TA apparatus may be equipped with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be processed by heat treatment are used. Using the RTA method, heat treatment may be performed at 600 °C to 750°C for several minutes. The LRTA apparatus may be equipped with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be processed by heat treatment are used. Using the RTA method, heat treatment may be performed at 600 °C to 750°C for several minutes. Heat treatment is a method of performing heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be processed by heat treatment are used. Using the RTA method, heat treatment may be performed at 600 °C to 750°C for several minutes.

[0230] Also, after the first heat treatment for dehydration or dehydrogenation, heating treatment may be performed at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower in an oxygen gas or N2O gas atmosphere.

[0231] Also, the first heat treatment of the oxide semiconductor layers 131 and 132 can be performed on the oxide semiconductor film 130 before being processed into island-shaped oxide semiconductor layers. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

[0232] By going through the above steps, the entire oxide semiconductor film is made in an oxygen-excessive state, thereby high resistivity, that is, type-I conversion is achieved. Thus, oxide semiconductor layers 168 and 118 that are entirely type-I converted are obtained.

[0233] Next, a resist mask is formed on the oxide semiconductor layers 168 and 118 by a third photolithography process, and selective etching is performed to form a source electrode layer and a drain electrode layer, and an oxide insulating film 107 is formed by a sputtering method.

[0234] Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, heat treatment (preferably 150°C or higher and less than 350°C) may be performed in an inert gas atmosphere or in a nitrogen gas atmosphere. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0235] A resist mask is formed by a fourth photolithography process, and selective etching is performed to form contact holes reaching the first terminal 121, the conductive layer 162, the drain electrode layer 105b, and the second terminal 122 in the gate insulating layer and the oxide insulating film. A conductive ​​​​​​​After forming the film, a resist mask is formed by a fifth photolithography process. The pixel electrode layer 110, the conductive layer 111, the terminal electrode 128, and the terminal electrode 12 9. Form the wiring layer 145.

[0236] In this embodiment, the first terminal 121 and the terminal electrode 128 are connected via the connection electrode 120. In this example, the drain electrode layer 165b and the conductive layer 162 are directly connected without wiring. This is done via the line layer 145.

[0237] In the capacitance section, the capacitance wiring 108, the gate insulating layer 102, the source electrode layer and the drain electrode The metal conductive layer, the oxide insulating film 107, and the pixel electrode layer 110 are formed in the same process as the pixel electrode layer. A capacitor 148 is formed from a laminated layer.

[0238] By the above process, the thin film transistor 183 is formed in the driver circuit portion and the thin film transistor 184 is formed in the pixel portion on the same substrate. A thin film transistor 173 can be fabricated on the substrate.

[0239] As in the first embodiment, the liquid crystal layer 192 is sandwiched between the opposing substrates 190, and the liquid crystal layer 192 is bonded to the opposing substrates 190. A liquid crystal display device having the above structure is fabricated (see FIG. 10).

[0240] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0241] (Sixth embodiment) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0242] The thin film transistors disposed in the pixel portion are formed according to any one of Embodiments 1 to 5. Since the thin film transistors shown in Embodiments 1 to 5 are n-channel TFTs, a part of the drive circuit that can be composed of n-channel TFTs is formed on the same substrate as the thin film transistors in the pixel portion. Of these, a part of the drive circuit that can be configured with n-channel TFTs is formed on the same substrate as the thin film transistors in the pixel portion. Form on the same substrate as the thin film transistors in the pixel portion.

[0243] An example of a block diagram of an active matrix display device is shown in FIG. 12(A). On the substrate 5300 of the display device, there are a pixel portion 5301, a first scan line drive circuit 5302, a second scan line drive circuit 5303, and a signal line drive circuit 5304. In the pixel portion 5301, a plurality of signal lines extend from the signal line drive circuit 5304 and are arranged, and a plurality of scan lines extend from the first scan line drive circuit 5302 and the scan line drive circuit 5303. Note that in the intersection region of the scan line and the signal line, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit). In FIG. 12(A), the first scan line drive circuit 5302, the second scan line drive circuit 5303, and the signal line drive circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of components such as drive circuits provided externally is reduced, so that cost reduction can be achieved. Also, the number of connections at the connection portion due to extending the wiring when a drive circuit is provided outside the substrate 5300 can be reduced, and reliability improvement or yield improvement can be achieved. Note that the timing control circuit 5305, for example,

[0244] In FIG. 12(A), the first scan line drive circuit 5302, the second scan line drive circuit 5303, and the signal line drive circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of components such as drive circuits provided externally is reduced, so that cost reduction can be achieved. Also, the number of connections at the connection portion due to extending the wiring when a drive circuit is provided outside the substrate 5300 can be reduced, and reliability improvement or yield improvement can be achieved. Note that the timing control circuit 5305, for example, In FIG. 12(A), the first scan line drive circuit 5302, the second scan line drive circuit 5303, and the signal line drive circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301.

[0245] Note that the timing control circuit 5305, for example, The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal The timing control circuit 5305 also supplies the second scanning line driving circuit (GCLK1). For example, a start signal for the second scanning line driving circuit (GSP2) (S It supplies a clock signal (GCLK2) for the scanning line driver circuit. The timing control circuit 5305 supplies a start signal for the signal line driver circuit to the signal line driver circuit 5304. (SSP), signal line driver circuit clock signal (SCLK), video signal data (DAT A) (also called simply video signal), latch signal (LAT) are supplied. The clock signal may be a plurality of clock signals with different periods, or may be an inverted clock signal. The first scanning line driving circuit may be supplied together with the signal (CKB). It is possible to omit either the second scanning line driver circuit 5302 or the second scanning line driver circuit 5303.

[0246] In FIG. 12B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, thin-film transistors have lower field-effect mobility than transistors using single-crystal semiconductors. The driving circuit formed on the substrate 5300 can be configured by the film transistor. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yields. do.

[0247] The thin film transistors described in Embodiments 1 to 5 are n-channel TFTs. 3(A) and 3(B) show and explain an example of the configuration and operation of a signal line driving circuit composed of n-channel type TFTs. An example will be shown and explained.

[0248] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of circuits such as switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors such as thin film transistors 5603_1 to 5603_k (k is a natural number). An example where the thin film transistors 5603_1 to 5603_k are n-channel type TFTs will be explained. 、have a plurality of transistors such as thin film transistors 5603_1 to 5603_k (k is a natural number). The thin film transistors 5603_1 to 5603_k are n-channel type TFTs. An example will be explained.

[0249] Regarding the connection relationship of the signal line driving circuit, an example of the switching circuit 5602_1 will be used for explanation. The first terminals of the thin film transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gates of the thin film transistors 5603_1 to 5603_ k are connected to the wiring 5605_1.

[0250] The shift register 5601 outputs signals of H level (also called H signal, high power supply potential level) to the wirings 5605_1 to 5605_N in order, and has a function of selecting the switching circuits 5602_1 to 56 02_N in order. The shift register 5601 has a function of outputting signals of H level (also referred to as H signal, high power supply potential level) to the wirings 5605_1 to 5605_N in sequence and selecting the switching circuits 5602_1 to 5602_N in sequence.

[0251] The switching circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of controlling whether to supply the potentials of the wirings 5604_ 1 to 5604_k to the signal lines S1 to Sk. The switching circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of controlling whether to supply the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0252] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0253] Next, the operation of the signal line driver circuit of FIG. 13(A) will be explained with reference to the timing chart of FIG. 13(B). 13B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0254] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. It may be exaggeratedly represented for the purpose. Therefore, it is noted that it is not necessarily limited to that scale. is appended.

[0255] During periods T1 to TN, the shift register 5601 outputs signals of the H level to wirings 560 5_1 to 5605_N in order. For example, during period T1, the shift register 5 601 outputs a high-level signal to wiring 5605_1. Then, since the thin-film transistors 5603_1 to 5603_k turn on, wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into a conductive state. At this time, Data(S1) to Data(Sk ) are input to wirings 5604_1 to 5604_k respectively. Data(S1) to Data(Sk ) are written to the pixels in columns 1 to k among the pixels belonging to the selected row via the thin-film transistors 5603_1 to 5603_k respectively. In this way, during periods T1 to TN , video signal data (DATA) is written to the pixels belonging to the selected row in units of k columns in order. Thus, by writing video signal data (DATA) to pixels in units of a plurality of columns, the number of video signal data (DATA) or the number of wirings can be reduced.

[0256] As described above, by writing video signal data (DATA) to pixels in units of a plurality of columns, the number of video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, by writing the video signal to pixels in units of a plurality of columns, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

[0257] Note that as the shift register 5601 and the switching circuit 5602, a circuit composed of the thin-film transistors shown in Embodiments 1 to 5 can be used. In this case, the Configure all transistors in the futo register 5601 to be of only N-channel type This can be done.

[0258] A form of the shift register used in part of the scanning line drive circuit and / or the signal line drive circuit will be described with reference to FIGS. 14 and 15. This will be described with reference to FIGS. 14 and 15.

[0259] The scanning line drive circuit has a shift register. In some cases, it may also have a level shifter and / or a buffer. In the scanning line drive circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. And since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. And since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. And since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used. [[ID=2H]]The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line.

[0260] The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 14(A)). To the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 14(A), a first clock signal CK1 is supplied from a first wiring 11, a second clock signal CK2 is supplied from a second wiring 12, a third clock signal CK3 is supplied from a third wiring 13, and a fourth clock signal CK4 is supplied from a fourth wiring 14. In the first pulse output circuit 10_1 of the shift register shown in FIG. 14(A), a start pulse SP1 (the first start pulse) from a fifth wiring 15 is input. In the first pulse output circuit 10_1 of the shift register shown in FIG. 14(A), a start pulse SP1 (the first start pulse) from a fifth wiring 15 is input. In the first pulse output circuit 10_1 of the shift register shown in FIG. 14(A), a start pulse SP1 (the first start pulse) from a fifth wiring 15 is input. In the first pulse output circuit 10_1 of the shift register shown in FIG. 14(A), a start pulse SP, (the first start pulse) from a fifth wiring 15 is input. In the first pulse output circuit 10_1 of the shift register shown in FIG. 14(A), a start pulse SP1 (the first start pulse) from a fifth wiring 15 is input. In the first pulse output circuit 10_1 of the shift register shown in FIG. 14(A), a start pulse SP1 (the first start pulse) from a fifth wiring 15 is input. In the pulse output circuit 10_n (where n is a natural number from 2 to N), a signal from the pulse output circuit one stage ahead (referred to as the previous stage signal OUT(n - 1)) (n is a natural number from 2 to N) is input. Also, in the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages behind is input. Similarly, in the nth pulse output circuit 10_n from the second stage onwards, a signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages behind (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, from each stage of the pulse output circuit, a first output signal OUT(1)(SR)~OUT(N)(SR) for input to the subsequent stage and / or the pulse output circuit two stages ahead, and a second output signal (OUT(1)~OUT(N)) electrically connected to another wiring or the like are output. As shown in FIG. 14(A), since the subsequent stage signal OUT(n + 2) is not input to the two stages at the final stage of the shift register, as an example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. A signal from the previous stage pulse output circuit (referred to as the previous stage signal OUT(n - 1)) (n is a natural number from 2 to N) is input. In the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages behind is input. Similarly, in the nth pulse output circuit 10_n from the second stage onwards, a signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages behind (referred to as the subsequent stage signal OUT(n + 2)) is input. A signal from the (n + 2)th pulse output circuit 10_(n + 2) two stages behind (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, from each stage of the pulse output circuit, a first output signal OUT(1)(SR)~OUT(N)(SR) for input to the subsequent stage and / or the pulse output circuit two stages ahead, and a second output signal (OUT(1)~OUT(N)) electrically connected to another wiring or the like are output. / Also, a first output signal OUT(1)(SR)~OUT(N)(SR) for input to the subsequent stage and / or the pulse output circuit two stages ahead, and a second output signal (OUT(1)~OUT(N)) electrically connected to another wiring or the like are output. As shown in FIG. 14(A), since the subsequent stage signal OUT(n + 2) is not input to the two stages at the final stage of the shift register, as an example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. As shown in FIG. 14(A), since the subsequent stage signal OUT(n + 2) is not input to the two stages at the final stage of the shift register, as an example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. Since the subsequent stage signal OUT(n + 2) is not input to the two stages at the final stage of the shift register, as an example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. For example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. For example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input.

[0261] The clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. The clock signal may also be referred to as GCLK, SCLK depending on the input driving circuit, but here it will be described as CK. The clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. The clock signal may also be referred to as GCLK, SCLK depending on the input driving circuit, but here it will be described as CK.

[0262] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 14(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11 and the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14 .

[0263] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 14(B)). In the first pulse output circuit 10_1, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, a third clock signal CK3 is input to the third input terminal 23, a start pulse is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, a first output signal OUT(1)(SR) is output from the first output terminal 26, and a second output signal OUT(1) is output from the second output terminal 27.

[0264] Note that the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N, in addition to a three-terminal thin film transistor (also referred to as a TFT: Thin Film Transistor), above The four-terminal thin film transistor described in the embodiments can be used. FIG. 14(C) shows an equivalent circuit of the four-terminal thin film transistor 28 described in the above embodiments. Note that in this specification, when a thin film transistor has two gate electrodes via a semiconductor layer the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode.

[0265] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, the threshold voltage may shift to the negative side or the positive side during the manufacturing process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, a configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the four-terminal thin film transistor 2 8 can be controlled to a desired value by controlling the potentials of the upper and / or lower gate electrodes.

[0266] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 14(B) will be described with reference to FIG. 14 (D).

[0267] The pulse output circuit shown in FIG. 14(D) includes transistors 31 to 43 of the first to thirteenth . Also, in addition to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which a first high power supply potential VDD is supplied, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied supply signals to the transistors 31 to 43 of the first to thirteenth . ​​​A power supply potential is supplied. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 14(D) is such that the first power supply potential VDD is at a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VC C is at a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) ~ the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals but are assumed to be VDD when at the H level and VSS when at the L level. By setting the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, without affecting the operation the potential applied to the gate electrode of the transistor can be kept low, reducing the shift in the threshold value of the transistor and suppressing degradation. Among the first transistor 31 to the thirteenth transistor 43, it is preferable to use four-terminal thin-film transistors for the first transistor 31, the sixth transistor 36 to the ninth transistor 39. The operations of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 are transistors for which it is required to switch the potential of a node to which one of the electrodes serving as the source or drain is connected, by means of a control signal applied to the gate electrode, and are transistors for which a faster response to the control signal input to the gate electrode (a steep rise in the on-current) can reduce the malfunction of the pulse output circuit. Therefore, by using four-terminal thin-film transistors, the threshold voltage can be controlled and a pulse output circuit with even lower malfunction can be achieved . . .

[0268] In FIG. 14(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (The lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24 and are. The second transistor 32 has its first terminal electrically connected to the power supply line 53 and its second terminal electrically connected to the first terminal of the ninth transistor 39, and its gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has its first terminal electrically connected to the first input terminal 21 and its second terminal electrically connected to the first output terminal 26 and is continued. The fourth transistor 34 has its first terminal electrically connected to the power supply line 53, and its second terminal electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and its gate electrode electrically connected to the fourth input terminal 24. The sixth transistor 36 has its first terminal electrically connected to the power supply line 52, its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power supply line 52, its second terminal electrically connected to the second terminal of the eighth transistor 38, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the second input terminal is electrically connected to 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and the gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power line 52 . The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 . The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 37 . The thirteenth transistor 43 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the first output terminal 26, and its gate electrode electrically connected to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 37 . In FIG. 14(D), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is defined as node A . Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, .

[0269] In FIG. 14(D), let the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 be node A . Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, ​​​​​​The connection points of the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 are defined as node B.

[0270] Fig. 15(A) shows the signals input to or output from the first input terminal 21 to the fifth input terminal 25, the first output terminal 26, and the second output terminal 27 when the pulse output circuit described in Fig. 14(D) is applied to the first pulse output circuit 10_1. Specifically, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, a third clock signal CK3 is input to the third input terminal 23, a start pulse is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, a first output signal OUT(1)(SR) is output from the first output terminal 26, and a second output signal OUT(1) is output from the second output terminal 27.

[0271] Here, a thin film transistor is an element having at least three terminals including a gate, a drain, and a source. Further, it has a semiconductor in which a channel formation region is formed in a region overlapping with the gate, and by controlling the potential of the gate, the current flowing between the drain and the source through the channel formation region can be controlled. Here, since the source and the drain vary depending on the structure and operating conditions of the thin film transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the regions functioning as the source and the drain may not be called the source or the drain. In that case, as an example, respectively

[0272] ​​​​​​​​​​​​​​​ These may be denoted as the first terminal and the second terminal.

[0273] In FIGS. 14(D) and 15(A), by making node A in a floating state, a boot strap operation may be performed by separately providing a capacitive element. Also, in order to hold the potential of node B, a capacitive element having one electrode electrically connected to node B may be separately provided.

[0274] Here, a timing chart of a shift register including a plurality of pulse output circuits shown in FIG. 15(A) is shown in FIG. 15(B). When the shift register is a scanning line driving circuit, in FIG. 15(B), period 61 is a vertical blanking period, and period 62 corresponds to a gate selection period.

[0275] As shown in FIG. 15(A), by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate, the following advantages exist before and after the bootstrap operation.

[0276] When there is no ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, when the potential of node A increases due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, increases and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied both between the gate and the source and between the gate and the drain, resulting in a large stress being applied, which may cause deterioration of the transistor. Therefore, a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode By providing the transistor 39, the potential of node A rises due to the bootstrap operation, but the potential rise of the second terminal of the first transistor 31 can be prevented. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. Although the potential of node A rises by the bootstrap operation by providing the transistor 39, the potential rise of the second terminal of the first transistor 31 can be prevented. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. By providing the transistor 39, the potential of node A rises due to the bootstrap operation, but the potential rise of the second terminal of the first transistor 31 can be prevented. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed.

[0277] Regarding the location where the ninth transistor 39 is provided, it may be configured to be connected via the first terminal and the second terminal between the second terminal of the first transistor 31 and the gate of the third transistor 33. In the case of a shift register having a plurality of pulse output circuits in the present embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, which has the advantage of reducing the number of transistors. Regarding the location where the ninth transistor 39 is provided, it may be configured to be connected via the first terminal and the second terminal between the second terminal of the first transistor 31 and the gate of the third transistor 33. In the case of a shift register having a plurality of pulse output circuits in the present embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, which has the advantage of reducing the number of transistors. Regarding the location where the ninth transistor 39 is provided, it may be configured to be connected via the first terminal and the second terminal between the second terminal of the first transistor 31 and the gate of the third transistor 33. In the case of a shift register having a plurality of pulse output circuits in the present embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0278] By using an oxide semiconductor as the semiconductor layer of the first transistor to the thirteenth transistor 43, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of degradation can be reduced. Therefore, malfunction in the circuit can be reduced. Further, compared with a transistor using amorphous silicon, a transistor using an oxide semiconductor has a smaller degree of degradation of the transistor due to the application of a high potential to the gate electrode. Therefore, the second power supply potential VCC is supplied. By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of degradation can be reduced. Therefore, malfunction in the circuit can be reduced. Further, compared with a transistor using amorphous silicon, a transistor using an oxide semiconductor has a smaller degree of degradation of the transistor due to the application of a high potential to the gate electrode. By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of degradation can be reduced. Therefore, malfunction in the circuit can be reduced. Further, compared with a transistor using amorphous silicon, a transistor using an oxide semiconductor has a smaller degree of degradation of the transistor due to the application of a high potential to the gate electrode. Therefore, the second power supply potential VCC is supplied. The same operation can be obtained by supplying the first power potential VDD to the power supply line, and the number of power supply lines routed between circuits can be reduced, so that the circuit can be miniaturized. Since the number of power supply lines can be reduced, the circuit can be miniaturized.

[0279] Note that the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) are supplied with the clock signal supplied by the third input terminal 23, and the gate electrodes of the eighth transistor 38 (the lower gate electrode and the upper gate electrode) are supplied with the clock signal supplied by the second input terminal 22. The clock signal supplied to the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) by the second input terminal 22, and the clock signal supplied to the gate electrodes of the eighth transistor 38 (the lower gate electrode and the upper gate electrode) by the third input terminal 23. Even if the connection relationship is swapped so that the clock signal supplied to the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) by the second input terminal 22, and the clock signal supplied to the gate electrodes of the eighth transistor 38 (the lower gate electrode and the upper gate electrode) by the third input terminal 23, the same effect can be obtained. In the shift register shown in FIG. 15(A), when both the seventh transistor 37 and the eighth transistor 38 are in the on state, the seventh transistor 37 is turned off, the eighth transistor 38 is turned on, then the seventh transistor 37 is turned off, and the eighth transistor 38 is turned off. By doing so, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. Note that in the shift register shown in FIG. 15(A), when both the seventh transistor 37 and the eighth transistor 38 are in the on state, the seventh transistor 37 is turned on, the eighth transistor 38 is turned off, then the seventh transistor 37 is turned off. When the eighth transistor 38 is in the on state, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. 15(A), when both the seventh transistor 37 and the eighth transistor 38 are in the on state, the seventh transistor 37 is turned on, the eighth transistor 38 is turned off, then the seventh transistor 37 is turned off. When the eighth transistor 38 is in the on state, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. 15(A), when both the seventh transistor 37 and the eighth transistor 38 are in the on state, the seventh transistor 37 is turned on, the eighth transistor 38 is turned off, then the seventh transistor 37 is turned off. When the eighth transistor 38 is in the on state, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. , by setting the eighth transistor 38 to the off state, the potential drop of node B caused by the potential drop of the second input terminal 22 and the potential drop of the third input terminal 23 can be reduced at once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, a clock signal is supplied from the third input terminal 23 to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrodes (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. It is preferable to have such a connection relationship. This is because the number of fluctuations in the potential of node B is reduced, and noise can be reduced.

[0280] In this way, by configuring such that a signal of H level is periodically supplied to node B during the period when the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, malfunctions of the pulse output circuit can be suppressed.

[0281] (Embodiment 7) A thin film transistor can be fabricated, and a semiconductor device (also referred to as a display device) having the functions shown by using the thin film transistor in a pixel portion and further in a driving circuit can be fabricated. In addition, a part or all of the driving circuit can be integrally formed on the same substrate as the pixel portion with the thin film transistor to form a system on panel.

[0282] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) can be used. In addition, a display medium such as electronic ink, whose contrast changes by an electrical action, can also be applied.

[0283] ​​​​In addition, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC or the like including a controller is mounted on the panel. Further, regarding the element substrate corresponding to a form before the completion of the display element in the process of manufacturing the display device, the element substrate is provided with means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrode and before etching to form the pixel electrode, and any form is applicable.

[0284] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module to which a connector, for example, an FPC (Flexible pr inted circuit) or a TAB (Tape Automated Bon ding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device.

[0285] The appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 16. FIGS. 16(A1) and (A2) show thin film transistors 4010, 4011, and a liquid crystal element 4013 sealed between a first substrate 4001 and a second substrate 4006 by a sealing material 4005, and are a plan view of the panel. FIG. 16(B) corresponds to a cross-sectional view taken along M -N in FIGS. 16(A1) and (A2).

[0286] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0287] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 16(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0288] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 16B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The protective insulating layer 4020 is formed on the thin film transistors 4010 and 4011. 021 is provided.

[0289] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 5. A highly reliable thin film transistor can be applied. As the thin film transistor 4011 for the driving circuit, the thin film transistors 180, 181, 182, 183 shown in Embodiments 1 to 5 can be used. As the thin film transistor 4010 for the pixel, the thin film transistors 170 171, 172, 173 can be used. In this embodiment, the thin film transistors 4010 , 4011 are n-channel thin film transistors. On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. Also,

[0290] the potential of the conductive layer 4040 may be the same as that of the gate electrode layer of the thin film transistor 4011, or different, and it can also function as a second gate electrode layer. Also, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032, 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032, 4033.

[0291] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032, 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032, 4033. The insulating layers 4032, 4033 are provided respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032, 4033. The insulating layers 4032, 4033 sandwich the liquid crystal layer 4008.

[0292] Note that as the first substrate 4001 and the second substrate 4006, a translucent substrate can be used, and glass, ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used.

[0293] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Further, the counter electrode layer 4031 is electrically connected to a common potential line disposed on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005.

[0294] Also, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5 wt% or more of a chiral agent is mixed is used for the liquid crystal layer 4008 in order to improve the temperature range. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence.

[0295] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0296] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer (color The polarizing plate is placed in the order of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be provided on the polarizing side. The setting can be made appropriately depending on the materials of the plate and colored layer and the manufacturing process conditions. A light-shielding film that functions as a black matrix may be provided.

[0297] In addition, an insulating layer 4020 is formed on the thin film transistors 4010 and 4011 . The insulating layer 4020 is formed using a material and a method similar to those of the oxide insulating film 107 described in Embodiment 1. However, in this example, the insulating layer 4020 is formed by sputtering silicon oxide. A bare film is formed.

[0298] A protective insulating layer may be formed over the insulating layer 4020. Then, a silicon nitride film is formed by RF sputtering (not shown).

[0299] An insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 109 may be formed using the same material and method as the planarization insulating layer 109 shown in the second embodiment. Heat-resistant organic materials such as polyimide, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low dielectric constant materials (low-k materials), silicon Use fluororesin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by laminating a plurality of insulating films made of these materials, the insulating layer 40 21 may be formed.

[0300] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, sputtering method, S OG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater , knife coater, etc. can be used. By combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0301] The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and other light-transmitting conductive materials can be used.

[0302] Further, as the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive composition containing a conductive polymer (also referred to as a conductive polymer ) can be used for formation. The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a light transmittance at a wavelength of 550 nm of 70% or more, which is preferable. Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less. As the conductive polymer, so-called π-electron conjugated system conductive polymers can be used. For example

[0303] polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives can be used. Examples include a derivative thereof, or a copolymer of two or more of these.

[0304] Also, a separately formed signal line driving circuit 4003, a scanning line driving circuit 4004, or a pixel portion 4 The various signals and potentials supplied to 002 are supplied from the FPC 4018.

[0305] The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistor 4011.

[0306] Also, in FIG. 16, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the configuration is not limited to this. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0307] FIG. 17 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by the manufacturing method disclosed in this specification.

[0308] FIG. 17 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are disposed therebetween to form a display area. The coloring layer 2605 is necessary for performing color display. In the case of the RGB method, coloring layers corresponding to each color of red, green, and blue are disposed corresponding to each pixel. Polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is cold ​ It is composed of a cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit part 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, it may be laminated with a retardation plate between the polarizing plate and the liquid crystal layer. It is connected to the wiring circuit part 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. It is connected to the wiring circuit part 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, it may be laminated with a retardation plate between the polarizing plate and the liquid crystal layer. It may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer.

[0309] The liquid crystal display module can use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. In-Plane-Switching) mode, an FFS (Fringe Field S witching) mode, an MVA (Multi-domain Vertical A lignment) mode, a PVA (Patterned Vertical Alig nment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated B irefringence) mode, an FLC (Ferroelectric Liqui d Crystal) mode, an AFLC (AntiFerroelectric Liq uid Crystal) mode, etc.

[0310] Through the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. It can be manufactured.

[0311] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. (Embodiment 8)

[0312] The semiconductor device disclosed in this specification has flexibility, and thus can be used for an electronic book (e-book). child books), posters, advertisements on trains and other vehicles, various cards such as credit cards An example of the electronic device is shown in FIG.

[0313] 18 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and a The housing 2701 and the housing 2703 are The shaft 2711 serves as an axis for opening and closing. This configuration allows the device to operate like a paper book.

[0314] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 18) and An image can be displayed on the display unit 2707 in FIG.

[0315] 18 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. It may also be possible.

[0316] In addition, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to configure it to purchase and download desired book data and the like from an electronic book server. It is also possible.

[0317] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. These are examples. These include, for example, large game machines such as pachinko machines. These are examples.

[0318] FIG. 19(A) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display video. Here, a configuration is shown in which the housing 9601 is supported by a stand 9605. This is the shown configuration.

[0319] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation device 9610. The operation keys 9609 provided on the remote control operation device 9610 can be used to operate the channels and volume, and can also be used to operate the video displayed on the display unit 9603. In addition, the remote control operation device 9610 may be configured to include a display unit 9607 for displaying information output from the remote control operation device 9610. This is the shown configuration. This is also a possible configuration.

[0320] The television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can also be connected to a communication network by wire or wirelessly via the modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0321] FIG. 19(B) shows an example of a digital photo frame. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 970 3 can display various images, and can function in the same way as a normal photo stand by displaying image data taken with, for example, a digital camera.

[0322] The digital photo frame 9700 has a configuration including an operation unit, external connection terminals (terminals connectable to various cables such as USB cables, USB B cables, etc.), a recording medium insertion part, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface as it improves the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion part of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0323] The digital photo frame 9700 may also be configured to be able to transmit and receive information wirelessly. It can also be configured to capture and display desired image data wirelessly.

[0324] Figure 20(A) shows a portable gaming machine, which is composed of two casings, a casing 9881 and a casing 9891, and is connected by a connecting part 9893 so as to be openable and closable. A display part 9882 is incorporated in the casing 9881, and a display part 9883 is incorporated in the casing 9891. In addition, the portable gaming machine shown in Figure 20(A) also includes, among other things, a speaker part 9884, a recording medium insertion part 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it is sufficient that it has at least the semiconductor device disclosed in this specification, and other accessory equipment can be provided as appropriate. The portable gaming machine shown in Figure 20(A) has functions such as reading out a program or data recorded on a recording medium and displaying it on the display part, and wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Figure 20(A) are not limited to this, and it can have various functions. It is composed of, and is connected by a connecting part so as to be openable and closable. A display part is incorporated in the casing, and a display part is incorporated in the other casing. In addition, the portable gaming machine shown in Figure also includes, among other things, a speaker part, a recording medium insertion part, an LED lamp, input means (operation keys, connection terminals, a sensor (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it is sufficient that it has at least the semiconductor device disclosed in this specification, and other accessory equipment can be provided as appropriate. The portable gaming machine shown in Figure has functions such as reading out a program or data recorded on a recording medium and displaying it on the display part, and wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Figure are not limited to this, and it can have various functions. chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it is sufficient that it has at least the semiconductor device disclosed in this specification, and other accessory equipment can be provided as appropriate. The portable gaming machine shown in Figure has functions such as reading out a program or data recorded on a recording medium and displaying it on the display part, and wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Figure are not limited to this, and it can have various functions. It is not limited to the above, and it is sufficient that it has at least the semiconductor device disclosed in this specification, and other accessory equipment can be provided as appropriate. It is sufficient that it has at least the semiconductor device disclosed in this specification, and other accessory equipment can be provided as appropriate. The portable gaming machine shown in Figure reads out a program or data recorded on a recording medium and displays it on the display part, and has a function of wirelessly communicating with other portable gaming machines to share information. reads out a program or data recorded on a recording medium and displays it on the display part, and has a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Figure are not limited to this, and it can have various functions. Note that the functions of the portable gaming machine shown in Figure are not limited to this, and it can have various functions.

[0325] Figure 20(B) shows an example of a slot machine, which is a large gaming machine. The slot machine 9900 has a display part 9903 incorporated in a casing 9901. In addition, the slot machine 9900 also includes, among other things, operation means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above. In addition, the slot machine also includes, among other things, operation means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above. It is not specified, and it may be any configuration as long as it includes at least the semiconductor device disclosed in this specification, and other ancillary equipment can be appropriately provided.

[0326] FIG. 21(A) is a perspective view showing an example of a portable computer.

[0327] The portable computer in FIG. 21(A) can be in a state where the upper housing 9301 having a display unit 9303 and the lower housing 9302 are overlapped with the hinge unit connecting them in a closed state, which is convenient for carrying. When the user inputs via the keyboard, the hinge unit can be opened so that the input operation can be performed while looking at the display unit 9303. In addition, the lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. Also, if the display unit 9303 is a touch input panel, an input operation can be performed by touching a part of the display unit. Further, the lower housing 9302 has arithmetic function units such as a CPU and a hard disk. Also, the lower housing 9302 has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, is inserted.

[0328]

[0329] The upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, and a wide display screen can be realized. Also, the user can adjust the orientation of the screen of the storage display unit 9307. Also, if the storage display unit 9307 is a touch input panel, an input operation can be performed by touching a part of the storage display unit.

[0330] ​​​​​​​​​​​ The display unit 9303 or the retractable display unit 9307 uses a video display device such as a liquid crystal display panel.

[0331] In addition, the portable computer shown in Fig. 21(A) is configured with a receiver and the like, and can receive television broadcasts and display the video on the display unit 9303 or the display unit 9307. Also, with the hinge unit connecting the upper housing 9301 and the lower housing 9302 in the closed state, slide the display unit 9307 to expose the entire screen, adjust the screen angle, and allow the user to watch television broadcasts. In this case, with the hinge unit in the open state, the display unit 9 303 is not displayed, and only the circuit for displaying only the television broadcast is activated, so that the minimum power consumption can be achieved, which is useful for a portable computer with a limited battery capacity.

[0332] Fig. 21(B) is a perspective view showing an example of a mobile phone that can be worn on the user's wrist like a wristwatch.

[0333] This mobile phone includes a communication device having at least a telephone function, a main body having a battery, a band portion 9204 for attaching the main body to the wrist, an adjustment portion 9205 for adjusting the fixed state of the band portion with respect to the wrist, a display portion 9201, a speaker 9207, and a microphone 9208.

[0334] The main body also has an operation switch 9203, and can associate each function such as a power input switch, a display switching switch, an imaging start instruction switch, and for example, a program for the Internet is started when a button is pressed.

[0335] ​​​​​​​​ Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 21(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0336] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0337] The mobile phone shown in FIG. 21(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. The system is configured with a storage device and the like, so that television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 1 may have a function for collecting location information such as GPS.

[0338] The display portion 9201 is an image display device such as a liquid crystal display panel. Since mobile phones are small and lightweight, their battery capacity is limited. The display device used in 1 preferably uses a panel that can be driven with low power consumption.

[0339] Although FIG. 21B illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape.

[0340] (Embodiment 10) In this embodiment mode, the thin film transistor shown in any of Embodiments 1 to 5 is used as one mode of a semiconductor device. An example of a display device having a stud will be described with reference to FIGS. 22 to 35. In the present embodiment, the display An example of a liquid crystal display device using a liquid crystal element as a device will be described with reference to FIGS. 22 to 35. FIG The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. 22 to 35 can be applied with the thin film transistors shown in Embodiments 1 to 5, and are thin film transistors with high electrical characteristics and reliability that can be manufactured in the same manner as in the processes shown in Embodiments 1 to 5. First, a VA (Vertical Alignment) type liquid crystal display device will be described.

[0341] The VA type is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel, and is a method in which the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. In the present embodiment, in particular, pixels are divided into several regions (sub-pixels), and the molecules are tilted in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

[0342] FIGS. 23 and 24 show a pixel electrode and a counter electrode, respectively. Note that FIG. 23 is a plan view of the substrate side on which the pixel electrode is formed, and the cross-sectional structure corresponding to the cutting line E-F shown in the figure is shown in FIG. 22. FIG. 24 is a plan view of the substrate side on which the counter electrode is formed. In the following description, these figures will be referred to for description.

[0343] FIG. 22 shows a substrate 600 on which a TFT 628, a pixel electrode layer 624 connected thereto, and a holding capacitor portion 630 are formed, and a counter substrate 601 on which a counter electrode layer 640 and the like are formed, superimposed, and shows a state in which liquid crystal is injected.

[0344] Although not shown, a first colored film, a second colored film, and a third colored film are formed on the opposing substrate 601 at positions where spacers are to be formed. The second colored film, the third colored film, and the counter electrode layer 640 are formed. The height of the protrusion 644 for controlling the crystal orientation and the spacer are made different. An alignment film 648 is formed on the counter electrode layer 640. A liquid crystal layer 650 is formed between them.

[0345] The spacers may be formed as columnar spacers or dispersed bead spacers. In the case of an optical element, it may be formed on the pixel electrode layer 624 formed on the substrate 600 .

[0346] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 6 The contacts penetrate the insulating film 620 covering the insulating film 30 and the third insulating film 622 covering the insulating film 620. The TFT 628 is connected to the wiring 618 through a contact hole 623. A thin film transistor can be used as appropriate.

[0347] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0348] 23 shows a structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment Mode 1. The pixel electrode layer 624 is provided with a slit 625. The slit 625 is formed by It is for controlling the orientation.

[0349] The TFT629 shown in FIG. 23, the pixel electrode layer 626 connected thereto, and the storage capacitor portion 631 can be formed in the same manner as the TFT628, the pixel electrode layer 624, and the storage capacitor portion 630, respectively. Both the TFT628 and the TFT629 are connected to the wiring 616. The pixel of this liquid crystal display panel is composed of the pixel electrode layer 624 and the pixel electrode layer 626. The pixel electrode layers 624 and 626 are sub-pixels.

[0350] FIG. 24 shows the structure on the counter substrate side. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. Protrusions 644 for controlling the alignment of liquid crystal are formed on the counter electrode layer 640.

[0351] The equivalent circuit of this pixel structure is shown in FIG. 25. Both the TFT628 and the TFT629 are connected to the gate wiring 602 and the wiring 616. In this case, by making the potentials of the capacitance wiring 604 and the capacitance wiring 605 different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, the alignment of the liquid crystal is precisely controlled to widen the viewing angle.

[0352] When a voltage is applied to the pixel electrode layer 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side to alternately mesh with each other, an oblique electric field is effectively generated to control the alignment of the liquid crystal, so that the direction in which the liquid crystal aligns varies depending on the location. That is, the liquid crystal is multi-domainized to widen the viewing angle of the liquid crystal display panel.

[0353] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 26 to 29. .

[0354] FIGS. 26 and 27 show the pixel structure of a VA type liquid crystal display panel. FIG. 27 is a plan view of the substrate 600, and the cross-sectional structure corresponding to the cutting line Y-Z shown in the figure is shown in FIG. 26. .

[0355] This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed with a multi-domain, the signal applied to each pixel electrode has a configuration that is independently controlled. . That is, in a pixel designed with a multi-domain, the signal applied to each pixel electrode has a configuration that is independently controlled. .

[0356] The pixel electrode layer 624 is connected to the TFT 628 by the wiring 618 at the contact hole 623. Also, the pixel electrode layer 626 is connected to the TFT 629 by the wiring 619 at the contact hole 627. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be applied. On the other hand, the wiring 616 that functions as a data line is commonly used by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 can appropriately use the thin film transistors shown in Embodiments 1, 2, 5, and 6. . The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be applied. On the other hand, the wiring 616 that functions as a data line is commonly used by the TFT 628 and the TFT 629. . The wiring 616 that functions as a data line is commonly used by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 can appropriately use the thin film transistors shown in Embodiments 1, 2, 5, and 6. .

[0357] The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different and are separated by the slit 625. The pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. The voltages applied to the pixel electrode layer 624 and the pixel electrode layer 626 are applied by the TFT 628. . . And by varying them with TFT629, the alignment of the liquid crystal is controlled. In this pixel structure The equivalent circuit is shown in FIG. 29. TFT628 is connected to the gate wiring 602, and TFT629 is connected to the gate wiring 603. Also, both TFT628 and TFT629 are connected to the wiring 616 By applying different gate signals to the gate wiring 602 and the gate wiring 603, the operations of the liquid crystal elements 651 and 652 can be made different. That is, by individually controlling the operations of TF T628 and TFT629, the alignment of the liquid crystal in the liquid crystal elements 651 and the liquid crystal elements 652 can be precisely controlled to widen the viewing angle.

[0358] On the counter substrate 601, a colored film 636 and a counter electrode layer 640 are formed. Also, between the colored film 636 and the counter electrode layer 640, a planarization film 637 is formed to prevent the alignment disorder of the liquid crystal and is shown in FIG. 28. The counter electrode layer 640 is an electrode that is shared among different pixels, but a slit 641 is formed. By arranging this slit 641 and the slit 625 on the side of the pixel electrode layer 624 and the pixel electrode layer 626 to alternately mesh with each other effectively generate an oblique electric field to control the alignment of the liquid crystal. Thereby the direction in which the liquid crystal aligns can be made different depending on the location, widening the viewing angle. Note that in FIG. 28, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 shown in FIG. 26 are shown by dashed lines, and the state where the counter electrode layer 640 and the pixel electrode layer 624 and the pixel electrode layer 626 are arranged overlapping each other is shown. On the pixel electrode layer 624 and the pixel electrode layer 626, an alignment film 648 is formed, and similarly on the counter electrode layer 640, an alignment film 648 is formed. are arranged overlapping each other is shown.

[0359] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626, and similarly on the counter electrode An alignment film 646 is also formed on the layer 640. Liquid crystal is between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed. Also, a first liquid crystal element is formed by the overlapping of the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640. Also, a second liquid crystal element is formed by the overlapping of the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640. The pixel structure of the display panel described in FIGS. 26 to 29 has a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel. 26 to 29 has a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel. Next, a horizontal electric field type liquid crystal display device will be described. The horizontal electric field type is a method of driving liquid crystal to perform gradation display by applying an electric field in the horizontal direction to the liquid crystal molecules in the cell. By this method,

[0360] Next, a horizontal electric field type liquid crystal display device will be described. The horizontal electric field type is a method of driving liquid crystal to perform gradation display by applying an electric field in the horizontal direction to the liquid crystal molecules in the cell. By this method, the viewing angle can be expanded to about 180 degrees. In the following description, a liquid crystal display device adopting the horizontal electric field type will be described. the viewing angle can be expanded to about 180 degrees. In the following description, a liquid crystal display device adopting the horizontal electric field type will be described. FIG. 30 shows a state in which the substrate 600 on which the electrode layer 607, the pixel electrode layer 624 connected to the TFTs 628, and the TFTs 628 are formed is overlapped with the counter substrate 601 and liquid crystal is injected.

[0361] FIG. 30 shows a state in which the substrate 600 on which the electrode layer 607, the pixel electrode layer 624 connected to the TFTs 628, and the TFTs 628 are formed is overlapped with the counter substrate 601 and liquid crystal is injected. On the counter substrate 601, a colored film 636, a planarization film 637, etc. are formed. Note that no counter electrode is disposed on the counter substrate 601 side. Also, a liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601 via the alignment films 646 and 648. On the counter substrate 601, a colored film 636, a planarization film 637, etc. are formed. Note that no counter electrode is disposed on the counter substrate 601 side. Also, a liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601 via the alignment films 646 and 648. On the substrate 600, the electrode layer 607, the capacitance wiring 604 connected to the electrode layer 607, and the TFTs 628 are formed. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFTs 628. As the TFTs 628, the thin film transistors shown in Embodiments 1 to 5 On the substrate 600, the electrode layer 607, the capacitance wiring 604 connected to the electrode layer 607, and the TFTs 628 are formed. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFTs 628. As the TFTs 628, the thin film transistors shown in Embodiments 1 to 5

[0362] On the substrate 600, the electrode layer 607, the capacitance wiring 604 connected to the electrode layer 607, and the TFTs 628 are formed. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFTs 628. As the TFTs 628, the thin film transistors shown in Embodiments 1 to 5 On the substrate 600, the electrode layer 607, the capacitance wiring 604 connected to the electrode layer 607, and the TFTs 628 are formed. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFTs 628. As the TFTs 628, the thin film transistors shown in Embodiments 1 to 5 On the substrate 600, the electrode layer 607, the capacitance wiring 604 connected to the electrode layer 607, and the TFTs 628 are formed. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFTs 628. As the TFTs 628, the thin film transistors shown in Embodiments 1 to 5 The studs can be applied. The electrode layer 607 can use the same materials as the pixel electrode layers shown in Embodiments 1 to 5. Also, the electrode layer 607 is formed in a shape partitioned into substantially pixel shapes. A gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. The wiring 616 is a data line for carrying a video signal in the liquid crystal display panel, and is a wiring extending in one direction. At the same time, it is connected to the source region or the drain region of the TFT 628, and becomes one electrode of the source and the drain. The wiring 618 becomes the other electrode of the source and the drain, and is a wiring connected to the pixel electrode layer 624. An insulating film 620 is formed on the wiring 616 and the wiring 618. Also, on the insulating film 620, a pixel electrode layer 624 connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed using the same materials as the pixel electrode layers shown in Embodiments 1 to 5.

[0363] In this way, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The holding capacitance is formed by providing the gate insulating film 606 between the electrode layer 607 and the pixel electrode layer 624. FIG. 31 is a plan view showing the configuration of the pixel electrode. The cross-sectional structure corresponding to the cut line O - P shown in FIG. 31 is shown in FIG. 30. A slit 625 is arranged in the pixel electrode layer 624. The slit 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is between the electrode layer 607 and... ... ... ...

[0364] ... ... ... ...

[0365] ... ... ...

[0366] ... ... ... The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. a film 606 is disposed, and the thickness of the gate insulating film 606 is 50 nm or more and 200 nm or less; Since the thickness of the liquid crystal layer is sufficiently thin compared to the thickness of the liquid crystal layer, which is 2 μm or more and 10 μm or less, the thickness of the substrate 60 An electric field is generated in the direction parallel to 0 (horizontal direction). This electric field controls the alignment of the liquid crystal. The liquid crystal molecules are rotated horizontally by using an electric field in a direction approximately parallel to the substrate. The crystal molecules are horizontal in any state, so the influence of the viewing angle on contrast is minimal. In addition, the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes. Since it is a polar, the aperture ratio can be improved.

[0367] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0368] Figures 32 and 33 show the pixel structure of an IPS type liquid crystal display device. Figure 33 is a plan view. FIG. 32 shows a cross-sectional structure corresponding to the cutting line VW shown in the figure.

[0369] FIG. 32 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlaid and liquid crystal is injected. A coloring film 636, a planarizing film 637, etc. are formed. The pixel electrodes are disposed on the substrate 600 side. Therefore, no counter electrode is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the first and second alignment films 646 and 648 .

[0370] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. As for the TFT 628, the thin film transistors shown in Embodiments 1 to 5 can be applied.

[0371] The wirings 616 and 618 of the TFT 628 are formed on the gate insulating film 606. The wiring 61 6 is a data line on which a video signal is placed in the liquid crystal display panel and is a wiring extending in one direction. At the same time, it is connected to the source region or the drain region of the TFT 628 and serves as one electrode of the source and the drain. The wiring 618 serves as the other electrode of the source and the drain and is a wiring connected to the pixel electrode layer 624.

[0372] An insulating film 620 is formed on the wirings 616 and 618. Further, on the insulating film 620, a pixel electrode layer 624 connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed using the same material as the pixel electrode layer shown in Embodiments 1 to 5. As shown in FIG. 33, the pixel electrode layer 624 is formed so that a horizontal electric field is generated with the comb-shaped electrode formed simultaneously with the common potential line 609. Further, the comb teeth portion of the pixel electrode layer 624 is formed to alternately engage with the comb-shaped electrode formed simultaneously with the common potential line 609. When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, the alignment of the liquid crystal is controlled by this electric field. Using the electric field in a direction substantially parallel to this substrate, the liquid crystal

[0373] molecules are rotated horizontally. In this case, since the liquid crystal molecules are horizontal in any state, the influence of factors such as contrast depending on the viewing angle is small, and the viewing angle is widened.

[0374] ​​​In this way, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between the common potential line 609 and the capacitor electrode 615. The capacitor electrode 615 and the pixel electrode layer 624 are connected via the contact hole 633.

[0375] Next, the form of the TN type liquid crystal display device will be described.

[0376] FIGS. 34 and 35 show the pixel structure of the TN type liquid crystal display device. FIG. 35 is a plan view, and the cross-sectional structure corresponding to the cutting line K-L shown in the figure is shown in FIG. 34. In the following description, both of these figures will be referred to for explanation.

[0377] The pixel electrode layer 624 is connected to the TFT 628 via the contact hole 623 and the wiring 618 formed in the insulating film 620. The wiring 616 that functions as a data line is connected to the TFT 628. The TFT 628 can apply any of the TFTs shown in Embodiments 1 to 5.

[0378] The pixel electrode layer 624 is formed using the pixel electrode layers shown in Embodiments 1 to 5. The capacitance wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the gate wiring 602 and the capacitance wiring 604. The storage capacitor is formed between the capacitance wiring 604 and the capacitor electrode 615 with the gate insulating film 606 interposed therebetween. The capacitor electrode 615 and the pixel electrode layer 624 are connected via the contact hole 623.

[0379] On the counter substrate 601, a colored film 636 and a counter electrode layer 640 are formed. Also, the colored film A planarization film 637 is formed between the 636 and the counter electrode layer 640 to prevent the alignment disorder of the liquid crystal. The liquid crystal layer 650 is formed between the pixel electrode layer 624 and the counter electrode layer 640 through the alignment film 648 and the alignment film 646.

[0380] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap each other to form a liquid crystal element. formed.

[0381] In addition, the coloring film 636 may be formed on the substrate 600 side. Also, a polarizing plate is bonded to the surface of the substrate 600 opposite to the surface on which the thin film transistor is formed, and a polarizing plate is bonded to the surface of the counter substrate 601 opposite to the surface on which the counter electrode layer 640 is formed.

[0382] Through the above steps, a liquid crystal display device can be manufactured as a display device.

[0383] (Embodiment 11) In this embodiment, another example of the manufacturing method of a semiconductor device, which is one form of the present invention, will be described with reference to FIG. 37. explain.

[0384] A gate electrode layer is formed on a substrate having an insulating surface (S101 in FIG. 37). The gate electrode layer materials include metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., or alloy materials mainly composed of these, and can be formed in a single layer or by stacking.

[0385] A gate insulating layer is formed on the gate electrode layer (S102 in FIG. 37). The gate insulating layer is formed by using a plasma CVD method or a sputtering method, etc., and a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed in a single layer or by stacking. In this embodiment, a silicon nitride layer with a film thickness of 200 nm or less is formed as the gate insulating layer by plasma CVD method.

[0386] Next, an oxide semiconductor film with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer (S103 in Fig. 37). In this embodiment, an In-Ga-Zn-O-based oxide semiconductor film is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. (S103 in Fig. 37). In this embodiment, an In-Ga-Zn-O-based oxide semiconductor film is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target.

[0387] Next, the oxide semiconductor film is etched using the resist mask formed by the photolithography process to form an island-shaped oxide semiconductor layer (S104 in Fig. 37).

[0388] Next, a heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the heat treatment for dehydration or dehydrogenation is set to be 400 °C or higher and less than 700 °C of the substrate (S105 in Fig. 37). In this embodiment, a heat treatment at 450 °C is performed in a nitrogen atmosphere. Here, the substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and after performing the heat treatment on the oxide semiconductor layer in a nitrogen atmosphere, without touching the atmosphere, the re-mixing of water and hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer. In this embodiment, using the same furnace from the heating temperature T for dehydration or dehydrogenation of the oxide semiconductor layer to a sufficient temperature where water does not enter again, specifically, it is slowly cooled in a nitrogen atmosphere until it drops by 100 °C or more from the heating temperature T. Also, it is not limited to a nitrogen atmosphere, and dehydration or dehydrogenation is performed in an inert gas atmosphere such as helium, neon, or argon.

[0389] By heat-treating the oxide semiconductor layer at a temperature of 400°C to 700°C, dehydration and dehydrogenation of the oxide semiconductor layer can be achieved, and subsequent re-impregnation with water (H2O) can be prevented.

[0390] Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. An LRTA apparatus is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be equipped with a device that heats an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA is a method of performing heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases that do not react with the object to be processed by heat treatment, such as nitrogen, are used. Heat treatment may be performed at 600 °C to 750°C for several minutes using the RTA method.

[0391] Note that in the heat treatment for dehydration or dehydrogenation, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. In particular, for the oxide semiconductor layer, the heat treatment for dehydration and dehydrogenation performed at 400°C to 700°C is preferably performed in a nitrogen atmosphere with H2O of 20 ppm or less. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably ​​​​​​​​​​​Preferably, it is 7N (99.99999%) or more, that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0392] Next, using the resist mask formed by the photolithography process, unnecessary parts of the gate insulating layer are removed to form an opening (contact hole) in the gate insulating layer (S 106 in FIG. 37). 106).

[0393] Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layer by sputtering or vacuum evaporation method.

[0394] Examples of the material of the metal conductive film include elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W , alloys containing the above-described elements as components, alloy films obtained by combining the above-described elements, and the like can be mentioned. Further, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example , a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film , a three-layer structure in which a Ti film is formed, an aluminum film is laminated on the Ti film, and a Ti film is formed thereon. Further, a film, an alloy film, or a nitride film obtained by combining one or more elements selected from titanium (Ti), tantalum (T a), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc) with Al may be used. Further, a nitride film may be used.

[0395] When heat treatment is performed after the metal conductive film, it is preferable to give the metal conductive film heat resistance to withstand this heat treatment .

[0396] Next, a photolithography process is performed to form a resist mask and etch the metal conductive film Remove unnecessary portions by G to form a source electrode layer and a drain electrode layer (S in FIG. 37 107).

[0397] Note that when etching the metal conductive film, appropriate adjustments are made to the respective materials and etching conditions so that the oxide semiconductor layer is not removed.

[0398] In this embodiment, a laminated film of a Ti film, an Al film, and a Ti film is used as the metal conductive film, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer, and aqueous hydrogen peroxide ammonia water (a mixed solution of ammonia, water, and hydrogen peroxide water) is used as the etchant.

[0399] Next, the target and the substrate are heat-treated in a chamber for forming an oxide insulating film (S in FIG. 3 7, S108). After the heat treatment, the target and the substrate are cooled (S109 in FIG. 37), and an oxide insulating film is formed at room temperature (S110 in FIG. 37). The heating temperature may be 100°C or higher and 250°C or lower.

[0400] The oxide insulating film should have a film thickness of at least 1 nm or more, (preferably 100 nm or more and 500 nm or less), and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating film. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed by sputtering as the oxide insulating film. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and is set to room temperature in this embodiment. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon Using a target, silicon oxide can be formed by a sputtering method in an oxygen atmosphere. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and blocks the intrusion of these from the outside. An inorganic insulating film is used, and typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or - an aluminum oxynitride film is used. etc. Further, a protective insulating layer may be formed on the oxide insulating film. For example, a silicon nitride film is formed using an RF sputtering

[0401] [[ID=……This part seems to be incomplete or has some issues. The following translation is based on the existing text.]] method. Since the RF sputtering method has good mass productivity, it is preferable as a method for forming the protective insulating layer. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH and blocks the intrusion of these from the outside. An inorganic insulating film is used, and a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. are used. - etc. In this embodiment, it is formed using a silicon nitride film as the protective insulating layer. The oxide insulating film is formed as a silicon oxide film with a thickness of 100 nm by a sputtering method (in an oxygen atmosphere, room temperature), and the laminated protective insulating layer is formed with a thickness of 100 nm by a sputtering method (in a nitrogen and argon atmosphere, room temperature)

[0402] This configuration may also be adopted.

[0403] Further, after the formation of the oxide insulating film, heat treatment may be performed in an inert gas atmosphere or a nitrogen gas atmosphere (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower). For example, heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0404] ​​Next, the oxide insulating film and the protective insulating layer are selectively etched to form an opening (S1 in FIG. 37 11). A planarizing insulating layer may be formed on the protective insulating layer. Depending on the material and formation method of the planarizing insulating layer, heat treatment at about 250 °C may be performed during formation. In this case, after the formation of the aforementioned oxide insulating film, the heat treatment may be omitted under an inert gas atmosphere or a nitrogen gas atmosphere as well.

[0405] Next, a conductive film having translucency is formed. As materials for the conductive film having translucency, indium oxide (In2O3), indium oxide - tin oxide alloy (In2O3 - SnO2, abbreviated as ITO ) etc. are formed using a sputtering method, a vacuum evaporation method or the like. As other materials for the conductive film having translucency, an Al - Zn - O - based non - single - crystal film containing nitrogen, that is, an Al - Zn - O - N - based non - single - crystal film, a Zn - O - based non - single - crystal film containing nitrogen, or a Sn - Zn - O - based non - single - crystal film containing nitrogen may be used. Note that the composition ratio (atomic %) of zinc in the Al - Zn - O - N - based non - single - crystal film is 47 atomic % or less, larger than the composition ratio (atomic %) of aluminum in the non - single - crystal film, and the composition ratio (atomic %) of aluminum in the non - single - crystal film is larger than the composition ratio (atomic %) of nitrogen in the non - single - crystal film. The etching treatment of such materials is performed with a hydrochloric acid - based solution. However, especially for the etching of ITO, residues are likely to occur, so an indium oxide - zinc oxide alloy (In2O3 - ZnO) may be used to improve the etching processability as well.

[0406] Next, a photolithography process is performed to form a resist mask, and unnecessary portions of the conductive film having translucency are removed by etching to form a pixel electrode layer and a conductive layer, and the resist mask is removed (S112 in FIG. 37). ​

[0407] Next, heat treatment is performed in the atmosphere at a temperature of 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter ( S113 in FIG. 37). In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be repeated multiple times by raising the temperature from room temperature to a heating temperature of 100°C or higher and 200°C, and then lowering the temperature from the heating temperature to room temperature. Also, this heat treatment may be performed under reduced pressure before forming the oxide insulating film. Performing heat treatment under reduced pressure can shorten the heating time. By this heat treatment, hydrogen is incorporated into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved. Through the above steps, thin film transistors can be fabricated for the drive circuit section and the pixel section on the same substrate.

[0408]

[0409] Similar to Embodiment 1, a counter substrate is bonded with a liquid crystal layer sandwiched therebetween, and the display device of this embodiment can be fabricated.

[0410] (Embodiment 12) In this embodiment, an example in which the oxide semiconductor layer is surrounded by a nitride insulating film as viewed in cross section is shown in FIG. 38. Since FIG. 38 is the same as FIG. 1 except that the upper surface shape and the position of the end portion of the oxide insulating layer are different, and the configuration of the gate insulating layer is different, the same reference numerals are used for the same portions, and detailed description of the same portions is omitted.

[0411] The thin film transistor 180 disposed in the drive circuit is a channel etch type thin film transistor. Yes, on a substrate 100 having an insulating surface, there are provided a gate electrode layer 161, a first gate insulating layer 188 made of a nitride insulating film, a second gate insulating layer 187a made of an oxide insulating film, an oxide semiconductor layer 163, a source electrode layer 165a, and a drain electrode layer 165b. Further, an oxide insulating layer 177a is provided which covers the thin film transistor 180 and is in contact with the channel formation region of the oxide semiconductor layer 163. A protective insulating layer 178 is further formed on the oxide insulating layer 177a, and a conductive layer 111 is provided at a position overlapping the gate electrode layer 161 and the oxide semiconductor layer 163 on the oxide insulating layer 177a. The first gate insulating layer 188, a second gate insulating layer 187a made of an oxide insulating film, an oxide semiconductor layer 163, a source electrode layer 165a, and a drain electrode layer 165b. Also, an oxide insulating layer 177a is provided which covers the thin film transistor 180 and is in contact with the channel formation region of the oxide semiconductor layer 163. A protective insulating layer 178 is further formed on the oxide insulating layer 177a, and a conductive layer 111 is provided at a position overlapping the gate electrode layer 161 and the oxide semiconductor layer 163 on the oxide insulating layer 177a.

[0412] The thin film transistor 170 disposed in the pixel portion is a channel etch type thin film transistor, and on a substrate 100 having an insulating surface, there are provided a gate electrode layer 101, a first gate insulating layer 188 made of a nitride insulating film, a second gate insulating layer 187b made of an oxide insulating film, an oxide semiconductor layer 103, a source electrode layer 105a, and a drain electrode layer 105b. Also, an oxide insulating layer 177b is provided which covers the thin film transistor 170 and is in contact with the channel formation region of the oxide semiconductor layer 103. A protective insulating layer 178 is further formed on the oxide insulating layer 177b, and a pixel electrode layer 110 in contact with the drain electrode layer 105b is provided on the protective insulating layer 178. formed, and a pixel electrode layer 110 in contact with the drain electrode layer 105b is provided on the protective insulating layer 178.

[0413] In this embodiment, in the thin film transistors 170 and 180, the gate insulating layer has a laminated structure of a nitride insulating film and an oxide insulating film from the gate electrode layer side. Also, when forming an opening in the oxide insulating layer, the oxide insulating film of the second gate insulating layer is also selectively removed, and the nitride insulating film is processed so as to be exposed.

[0414] ​​​​​ At least the oxide insulating layers 177a and 177b and the second gate insulating layers 187a and 187b have an upper surface shape that is wider than the upper surface shape of the oxide semiconductor layers 163 and 103, and it is preferable that the upper surface shape covers the thin film transistors 180 and 170.

[0415] Furthermore, a protective insulating layer 178 made of a nitride insulating film is formed to cover the upper surface and side surfaces of the oxide insulating layers 177a and 177b and to be in contact with the nitride insulating film of the first gate insulating layer.

[0416] The protective insulating layer 178 made of a nitride insulating film and the first gate insulating layer 188 are inorganic insulating films that do not contain impurities such as moisture, hydrogen ions, and OH in a silicon nitride film, silicon oxynitride film, aluminum nitride film, aluminum oxynitride film, etc. obtained by sputtering or plasma CVD, and block these from entering from the outside. -

[0417] In this embodiment, as the protective insulating layer 178 made of a nitride insulating film, an RF sputtering method is used to surround the upper surface and side surfaces of the oxide semiconductor layers 163 and 103, and a silicon nitride film with a film thickness of 100 nm is provided. Also, the protective insulating layer 178 is configured to be in contact with the first gate insulating layer 188 made of a nitride insulating film.

[0418] By adopting the structure shown in FIG. 38, it is possible to prevent the intrusion of moisture from the outside during the manufacturing process after the formation of the protective insulating layer 178 made of a nitride insulating film. Also, even after the device is completed as a semiconductor device, for example, a liquid crystal display device, it is possible to prevent the intrusion of moisture from the outside in the long term and improve the long-term reliability of the device.

[0419] In addition, in this embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film has been shown, but it is not particularly limited thereto, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may be employed, or a configuration in which a plurality of thin film transistors in the pixel portion are collectively surrounded by a nitride insulating film may be used. At least a region where the protective insulating layer 178 and the first gate insulating layer 188 are in contact may be provided so as to surround the periphery of the pixel portion of the active matrix substrate.

[0420] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

Explanation of Reference Numerals

[0421] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input Terminal 22 Input Terminal 23 Input Terminal 24 Input Terminal 25 Input Terminal 26 Output Terminal 27 Output Terminal 28 Thin Film Transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power Supply Line 52 Power Supply Line 53 Power Supply Line 100 Substrate 101 Electrode 102 Gate insulating layer 103 Oxide semiconductor layer 107 Oxide insulating film 108 Capacitor wiring 109 Planarization insulating layer 110 Pixel electrode layer 111 Conductive layer 116 Channel formation region 118 Contact hole 119 Contact hole 120 Connection electrode 121 Terminal 122 Terminal 125 Contact hole 126 Contact hole 127 Contact hole 128 Terminal electrode 129 Terminal electrode 130 Oxide semiconductor film 131 Oxide semiconductor layer 133 Oxide semiconductor layer 134 Oxide semiconductor layer 137 Resist mask 138 Oxide conductive layer 140 Oxide conductive film 142 Oxide conductive layer 143 Oxide conductive layer 145 Wiring layer 146 Capacitor 147 Capacitor 148 Capacitor 150 Terminal 151 Terminal 153 Connection electrode 155 Conductive film 156 Electrode 161 Gate electrode layer 162 Conductive layer 163 Oxide semiconductor layer 166 Channel formation region 168 Oxide semiconductor layer 170 Thin film transistor 171 Thin film transistor 172 Thin film transistor 173 Thin film transistor 178 Protective insulating layer 180 Thin film transistor 181 Thin film transistor 182 Thin film transistor 183 Thin film transistor 188 Gate insulating layer 190 Counter substrate 191 Insulating layer 192 Liquid crystal layer 193 Insulating layer 194 Counter electrode layer 195 Coloring layer 202 Gate insulating layer 203 Protective insulating layer 206 Common electrode layer 210 Common potential line 220 Thin film transistor 227 Pixel electrode layer 402 Gate insulating layer 600 Substrate 601 Counter substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 607 Electrode layer 609 Common potential line 615 Capacitance electrode 616 Wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact hole 628 TFT 629 TFT 630 Holding capacitance section 631 Holding capacitance section 633 Contact Hole 636 Colored Film 637 Planarization Film 640 Counter Electrode Layer 641 Slit 644 Protrusion 646 Alignment Film 648 Alignment Film 650 Liquid Crystal Layer 651 Liquid Crystal Element 652 Liquid Crystal Element 104a Oxide Conductive Layer 104b Oxide Conductive Layer 105a Source Electrode Layer 105b Drain Electrode Layer 117a High-Resistance Source Region 117b High-Resistance Drain Region 135a Resist Mask 136a Resist Mask 164a Oxide Conductive Layer 164b Oxide Conductive Layer 165a Source Electrode Layer 165b Drain Electrode Layer 167a High-Resistance Source Region 167b High-Resistance Drain Region 177a Oxide Insulating Layer 177b Oxide Insulating Layer 187a Gate Insulating Layer 187b Gate Insulating Layer 196a Polarizer 2600 TFT Substrate 2601 Counter Substrate 2602 Sealant 2603 Pixel Portion 2604 Display Element 2605 Colored Layer 2606 Polarizer 2607 Polarizer 2608 Wiring Circuit Portion 2609 Flexible Wiring Substrate 2610 Cold Cathode Tube 2611 Reflector 2612 Circuit Substrate 2613 Diffuser 2700 E-books 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft part 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel part 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4020 Protective insulating layer 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4035 Spacer 4040 Conductive layer 5300 Substrate 5301 Pixel part 5302 Scanning line drive circuit 5303 Scanning line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 9201 Display unit 9202 Display button 9203 Operation switch Adjustment Unit Camera Unit Speaker Microphone Upper Housing Lower Housing Display Unit Keyboard External Connection Port Pointing Device Display Unit Television Device Housing Display Unit Stand Display Unit Operation Key Remote Control Unit Digital Photo Frame Housing Display Unit Housing Display Unit Display Unit Speaker Unit Operation Key Recording Medium Insertion Part Connection Terminal Sensor Microphone LED Lamp Housing Connection Part Slot Machine Housing Display Unit

Claims

【Claim 1】 On the same substrate, a driving circuit portion having a first thin-film transistor, a pixel portion having a second thin-film transistor, a first wiring, and a second wiring, wherein the first and second thin-film transistors have a gate electrode layer on the substrate, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer on the oxide semiconductor layer, and an oxide conductive layer in contact with the source electrode layer or the drain electrode layer and the oxide semiconductor layer, have an oxide insulating layer, a pixel electrode layer, and a liquid crystal layer on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein the first wiring is formed of the same material as the gate electrode layer, the second wiring is formed of a laminate of the same material as the source electrode or drain electrode layer and the same material as the oxide conductive layer, the first wiring is connected to the second wiring through an opening provided in the gate insulating layer on the first wiring, the first thin-film transistor has a conductive layer at a position overlapping the oxide semiconductor layer on the oxide insulating layer, and the second thin-film transistor is electrically connected to the pixel electrode layer. A semiconductor device characterized by this.

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