Three-dimensional memory device and manufacturing method thereof, and three-dimensional memory

Abstract

To provide a three-dimensional memory device and a manufacturing method thereof.SOLUTION: A three-dimensional memory device 1000 includes a first memory cell 100 and at least one second memory cell 200. Each memory cell includes a first set of contacts 40, a memory array device 10, and a CMOS device 20. The first set of contacts is disposed on a side of the memory array device facing a direction away from the CMOS device and electrically connected with the CMOS device. The second memory cell further includes a second set of contacts 50. The second set of contacts is disposed on a side of the CMOS device facing a direction away from the memory array device and electrically connected with the CMOS device. The memory array device of the first memory cell is bonded with the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is electrically connected with the second set of contacts of the adjacent second memory cell.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of Chinese Patent Application No. 202110330026.2, filed on March 27, 2021, entitled "THREE - DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF AND THREE - DIMENSIONAL MEMORY", and the entire disclosure of this Chinese patent application is incorporated herein by reference in its entirety.

[0002] Technical Field The present disclosure relates to the technical field of semiconductor devices, and more particularly, to three - dimensional memory devices, manufacturing methods of three - dimensional memory devices, and three - dimensional memories including such three - dimensional memory devices.

Background Art

[0003] 3D NAND memory is a new type of three - dimensional memory that addresses the storage capacity limitation problem of 2D NAND memory or planar NAND memory by vertically stacking multiple data memory layers within a memory chip. This memory chip includes a CMOS device and a memory array device having a step structure. The CMOS device and the memory array device are separately formed on a substrate, and the surfaces of the CMOS device and the memory array device, which are far from each other from each substrate, are electrically connected to each other.

[0004] With the increasing demand for high-density designs in 3D NAND memories, the number of memory layers in the memory array devices of memory chips is gradually increasing. However, in the prior art, with the increase in the number of stacked layers of the memory layer, both the number of step layers and the footprint of the step structure of the memory array device increase, thereby increasing the substrate area of the memory array device. Therefore, this results in an area mismatch between the substrate of the memory array device and the substrate of the CMOS device, creating unused space in the memory chip, which is not favorable for the development and volume miniaturization of next-generation 3D NAND memories. Summary of the Invention Means for Solving the Problems

[0005] One aspect of the present disclosure provides a three-dimensional memory device including at least two memory cells stacked continuously. These at least two memory cells include a first memory cell and at least one second memory cell stacked on the first memory cell, and each memory cell a memory array device and a CMOS device stacked and electrically connected to each other, a first set of contacts disposed on a surface facing away from the CMOS device of the memory array device and electrically connected to the CMOS device and comprising, The second memory cell further includes a second set of contacts. The second set of contacts is disposed on a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell and is electrically connected to the CMOS device of the second memory cell. The memory array device of the first memory cell is bonded to the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is electrically connected corresponding to the second set of contacts of the adjacent second memory cell. When there is one second memory cell, the second memory cell is an outer second memory cell stacked on the first memory cell, and a first set of contacts of the outer second memory cell is used to connect to an external device. When there are a plurality of second memory cells, the plurality of second memory cells are continuously stacked on the first memory cell. For two adjacent second memory cells among the second memory cells, a first set of contacts of the second memory cell closer to the first memory cell is electrically connected corresponding to a second set of contacts of the second memory cell farther from the first memory cell. The second memory cell farthest from the first memory cell along the stacking direction is defined as the outer second memory cell, and a first set of contacts of the outer second memory cell is used to connect to an external device.

[0006] Another aspect of the present disclosure further provides a method for manufacturing a three-dimensional memory device. This manufacturing method includes the following steps, that is A step of preparing a first memory cell and a second memory cell, each including a first set of contacts, a memory array device and a CMOS device stacked and electrically connected to each other, wherein the first set of contacts is disposed on a surface facing away from the CMOS device of the memory array device and is electrically connected to the CMOS device. A step of thinning a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell. A step of forming a second set of contacts on a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts is electrically connected to the CMOS device of the second memory cell. Stacking a second memory cell on a surface of a memory array device of a first memory cell facing away from a CMOS device of the first memory cell, and bonding the memory array device of the first memory cell to the CMOS device of the second memory cell, such that a first set of contacts of the first memory cell is electrically connected corresponding to a second set of contacts of the second memory cell, the step of including.

[0007] Still other aspects of the present disclosure further provide a three-dimensional memory including the three-dimensional memory device described above.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] The present disclosure will be further described in the following detailed description in combination with the above-described drawings.

[0010] Hereinafter, in combination with the drawings of the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and fully described. Although it goes without saying, the described embodiments are only a part of the embodiments of the present disclosure, not all of them. All other embodiments that can be realized by those skilled in the art based on the embodiments of the present disclosure without creative efforts are also included in the protection scope of the present disclosure.

[0011] In the description of the present disclosure, terms such as "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. This is only for the purpose of facilitating and simplifying the description of the present disclosure, and does not indicate or suggest that the device or element pointed out must have a specific orientation and be configured and operated in a specific orientation. Therefore, it should be noted that it should not be understood as limiting the present disclosure. Further, terms such as "first", "second", etc. are only for the purpose of description and should not be construed as indicating or suggesting relative importance.

[0012] Referring to FIGS. 1 and 2, the present disclosure provides a three-dimensional memory device comprising at least two memory cells stacked continuously. These at least two memory cells consist of a first memory cell 100 and at least one second memory cell 200 stacked on the first memory cell 100. As shown in FIG. 1, in one embodiment of the present disclosure, the number of the second memory cells 200 is one, and the first memory cell 100 and one second memory cell 200 are stacked to form a three-dimensional memory device 1000. As shown in FIG. 2, in another embodiment of the present disclosure, the number of the second memory cells 200 is plural (two or more), and a plurality of second memory cells 200 are continuously stacked on the first memory cell 100, and the first memory cell 100 and the plurality of second memory cells 200 are stacked to form a three-dimensional memory device 1000b. The three-dimensional memory device provided by the present disclosure is formed by stacking at least two memory cells, and thus has a high storage density.

[0013] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, each memory cell includes a memory array device 10 and a CMOS device 20 that are stacked and electrically connected to each other, and a first set 40 of contacts disposed on a surface of the memory array device 10 facing away from the CMOS device 20 and electrically connected to the CMOS device 20. In some embodiments of the present disclosure, the memory array device 10 and the CMOS device 20 of each memory cell can establish an electrical connection between each other by being connected by bonding. Of course, in other embodiments, the memory array device 10 and the CMOS device 20 of each memory cell may establish an electrical connection by other means including, but not limited to, wired connection, conductive contact connection, plug-in connection, etc.

[0014] The memory array device 10 includes an array substrate 11 and a memory array disposed on a surface of the array substrate 11 close to the CMOS device 20. This memory array has a data storage function and includes a plurality of memory layers 13 and a plurality of memory strings that penetrate the plurality of memory layers 13 and are connected to each other. The first set 40 of contacts of each memory cell is disposed on a surface of the array substrate 11 facing away from the CMOS device 20. The CMOS device 20 includes a CMOS substrate 21 and a CMOS circuit disposed on a surface of the CMOS substrate 21 close to the memory array device 10. This CMOS circuit is used to perform logical control on the memory array device 10, read stored data, etc.

[0015] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, each memory cell further includes an interconnect channel 30, and this interconnect channel 30 is electrically connected to a first set 40 of contacts of the memory cell where the interconnect channel 30 is located and the CMOS device 20, respectively. Thereby, the first set 40 of contacts is electrically connected to the CMOS device 20 via the interconnect channel 30. In some embodiments of the present disclosure, the interconnect channel 30 is disposed within the memory array device 10 of the memory cell where the interconnect channel 30 is located and the CMOS device 20, and is perpendicular to the array substrate 11 and the CMOS substrate 21. Of course, in other embodiments, the interconnect channel 30 may not be perpendicular to the array substrate 11 and the CMOS substrate 21, and may be perpendicular to the array substrate 11 or perpendicular to the CMOS substrate 21.

[0016] In some embodiments of the present disclosure, each second memory cell 200 further includes a second set 50 of contacts. In some embodiments, the second set 50 of contacts is disposed on the surface of the CMOS device 20 of the second memory cell 200 facing away from the memory array device 10 of the second memory cell 200 and is electrically connected to the CMOS device 20 of the second memory cell 200.

[0017] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, the memory array device 10 of the first memory cell 100 is bonded to the CMOS device 20 of the adjacent second memory cell 200. Correspondingly, the first set 40 of contacts of the first memory cell 100 is electrically connected to the second set 50 of contacts of the adjacent second memory cell 200, and the first memory cell 100 is electrically connected to the adjacent second memory cell 200 via the first set 40 of contacts and the second set 50 of contacts.

[0018] As shown in FIG. 1, in one embodiment of the present disclosure, when there is only one second memory cell 200 in the three-dimensional memory device 1000, this second memory cell 200 becomes an outer second memory cell 200 stacked on the first memory cell 100, and the first set 40 of contacts of this outer second memory cell 200 is used to connect to an external device (such as a control device or a drive circuit, etc.) for performing functions such as driving and controlling the three-dimensional memory device 1000.

[0019] As shown in FIG. 2, in another embodiment of the present disclosure, when there are a plurality of second memory cells 200 in the three-dimensional memory device 1000b, these plurality of second memory cells 200 are continuously stacked on the first memory cell 100. Regarding two adjacent second memory cells 200 among these second memory cells 200, the first set 40 of contacts of the second memory cell 200 located near the first memory cell 100 is electrically connected to the second set 50 of contacts of the second memory cell 200 located far from the first memory cell 100, so that these two adjacent second memory cells 200 establish an electrical connection through the first set 40 of corresponding contacts and the second set 50 of contacts, and further, the first memory cell 100 and the plurality of second memory cells 200 continuously stacked on the first memory cell 100 establish an electrical connection. The second memory cell 200 located farthest from the first memory cell 100 along the stacking direction is the outer second memory cell 200 stacked on the first memory cell 100, and the first set 40 of contacts of this outer second memory cell 200 is used to connect to an external device (such as a control device or a drive circuit, etc.) for performing functions such as driving and controlling the three-dimensional memory device 1000b. The number of memory cells stacked in the three-dimensional memory device 1000b is larger compared to the three-dimensional memory device 1000, and thus it will be understood that the storage density of the three-dimensional memory device 1000b is higher.

[0020] In these embodiments of the present disclosure, at least two memory cells are continuously stacked, and by establishing an electrical connection between these at least two memory cells via a first set 40 of corresponding contacts and a second set 50 of contacts, a three-dimensional memory device with a high storage density can be configured without the need to stack an excessive number of memory layers 13 within the memory array device 10 of each memory cell. As a result, the area of the array substrate 11 of each memory cell does not become overly large, which is preferable for arranging the array substrate 11 and the CMOS substrate 21 of each memory cell in an appropriate area ratio. It becomes possible to further reduce the unused space within each memory cell and increase the space utilization rate of the three-dimensional memory device.

[0021] Both the array substrate 11 and the CMOS substrate 21 can be made of a semiconductor material or a non-conductive material. Here, semiconductor materials include, but are not limited to, silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, germanium on insulator, or any suitable combination thereof. Non-conductive materials include, but are not limited to, glass, plastic, or sapphire. In these embodiments of the present disclosure, both the array substrate 11 and the CMOS substrate 21 are silicon substrates. Except for the CMOS substrate 21 of the first memory cell 100, the array substrate 11 and the CMOS substrate 21 of any memory cell within the three-dimensional memory device can be thinned to be advantageous in reducing the volume of the three-dimensional memory device. Thinning means include, but are not limited to, mechanical polishing, wet / dry etching, chemical mechanical polishing, or any combination thereof.

[0022] As shown in FIGS. 1 and 2, in each memory array device 10, a plurality of memory layers 13 are stacked in a stepped structure on one side surface of the array substrate 11, and a plurality of memory strings (for example, NAND strings) penetrate through the plurality of memory layers 13 and connect these memory layers 13 to each other. Thus, the plurality of memory strings and the plurality of memory layers 13 together constitute a memory array having a storage function.

[0023] In some embodiments, each memory layer 13 extends along a lateral direction parallel to the surface of the array substrate 11. In a direction away from the array substrate 11 gradually and perpendicular to the array substrate 11, two adjacent memory layers 13 among the plurality of memory layers 13 are each offset by the same distance and reduced by the same distance in the lateral direction. It will be understood that the two adjacent memory layers 13 may each be located in the same plane at one end and reduced by the same distance at the other end in the lateral direction, and may further be reduced by the same distance at each of the two ends in the lateral direction. As shown in FIGS. 1 and  2, in some embodiments of the present disclosure, the two adjacent memory layers 13 are each reduced by the same distance at each of the two ends in the lateral direction. Each memory layer 13 may include one or a plurality of pairs of conductive layers / dielectric layers each composed of a conductive layer and a dielectric layer, and the specific structures, functions, and materials of these conductive layers and dielectric layers are the same as those of the conductive layers and dielectric layers generally used in the prior art. Therefore, this will not be described again in this specification.

[0024] Each memory string includes a channel structure portion that extends in a direction perpendicular to the array substrate 11 and penetrates a plurality of memory layers 13. This channel structure portion includes a channel hole filled with a semiconductor material (as a semiconductor channel) and a channel hole filled with a dielectric material (as a memory film). The memory film may include a tunnel layer, a charge trap / memory layer, and a barrier layer. The semiconductor channel, the tunnel layer, the charge trap / memory layer, and the barrier layer are continuously arranged outward from the center of the memory string. Note that the specific structure, function, and material of the memory string are the same as those of the memory strings generally used in the prior art, and thus, they will not be described again in this specification.

[0025] In the three-dimensional memory device provided by the present disclosure, each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 includes a plurality of memory layers 13. As described above, in order to avoid the area of the array substrate 11 from becoming excessively large, it is not necessary to stack an excessively large number of memory layers 13 in the memory array device 10 of each memory cell. In the three-dimensional memory device realized according to the embodiment of the present disclosure, each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 includes a preset number of memory layers 13, and the numerical value of the preset number of layers is an integer greater than 0 and less than 500, for example, 32 layers, 64 layers, 96 layers, or 128 layers. The number of memory layers 13 in each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 may be the same or different. In some implementation forms, the number of memory layers 13 in each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 may be the same, which is convenient for mass-producing the first memory cell 100 and the second memory cell 200 in the same process step.

[0026] In each memory cell, the memory array device 10 and the CMOS device 20 may each further include several other elements. For example, a stack layer covering the memory array or the CMOS circuit, a bonding structure disposed on the inner side surface of the stack layer (including, but not limited to, conductive structures such as wires, plugs, solder bumps, or pads), and a plurality of interconnect conductive channels that penetrate the stack layer and are electrically connected to the bonding structure and the memory array or the CMOS circuit, respectively. It will be understood that the stack layer includes at least one insulating layer covering the memory array or the CMOS circuit. The specific structures and functions of the memory array device 10 and the CMOS device 20 are substantially the same as the structures and functions of the memory array devices and CMOS devices in the prior art and are not related to the improvements and innovations of the present disclosure, so they will not be described again in this specification.

[0027] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, the interconnect channel 30 includes a first interconnect sub-channel 31, a second interconnect sub-channel 32, and an interconnect structure 33 electrically connected between the first interconnect sub-channel 31 and the second interconnect sub-channel 32.

[0028] In some embodiments, the first interconnect sub-channel 31 is disposed within the memory array device 10, located on the surface of the memory array device 10 that includes the memory array, and penetrates the stack layer of the memory array device 10. The second interconnect sub-channel 32 is disposed within the CMOS device 20, located on the surface of the CMOS device 20 that includes the CMOS circuit, and penetrates the stack layer of the CMOS device 20. The second interconnect sub-channel 32 is located at a position corresponding to the first interconnect sub-channel 31, and the second interconnect sub-channel 32 is electrically connected to the CMOS circuit at one end far from the first interconnect sub-channel 31. It should be noted that the first interconnect sub-channel 31 and the second interconnect sub-channel 32 can be formed using conventional means of the prior art. For example, in some embodiments of the present disclosure, deep etching may be performed on the respective stack layers of the memory array device 10 and the CMOS device 20 to form a filled channel penetrating the stack layer, and then a conductive material may be filled into this filled channel to form the first interconnect sub-channel 31 and the second interconnect sub-channel 32, respectively. Here, the conductive material includes, but is not limited to, tungsten, cobalt, copper, polysilicon, silicide, or any combination thereof. The number of the first interconnect sub-channel 31 and the second interconnect sub-channel 32 can be set as one or more as long as the numbers of both of them correspond and are the same, but it is not limited thereto.

[0029] The interconnection structure part 33 includes a first interconnection contact and a second interconnection contact. The first interconnection contact is disposed on the inner (i.e., the side closer to the CMOS device) surface of the stack layer of the memory array device 10 and is electrically connected to the first interconnection sub-channel 31 correspondingly. The second interconnection contact is disposed on the inner (i.e., the side closer to the memory array device) surface of the stack layer of the CMOS device 20 and is electrically connected to the second interconnection sub-channel 32 correspondingly. The first interconnection contact and the second interconnection contact include, but are not limited to, conductive structure parts such as wires, plugs, solder bumps, or pads. The structural shapes of the first interconnection contact and the second interconnection contact may be the same or different. As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, the first interconnection contact is a plurality of solder bumps having the same number as the number of the first interconnection sub-channels 31 and is electrically connected to the first interconnection sub-channels 31 in a one-to-one correspondence. The second interconnection contact is a pad. These pads are electrically connected on one side surface so as to correspond to the second interconnection sub-channels 32, and include a plurality of pins on the other side surface. These pins are in a one-to-one correspondence with the plurality of solder bumps of the first interconnection contact. When the memory array device 10 and the CMOS device 20 of each memory cell are bonded in a face-to-face configuration, the first interconnection contact and the second interconnection contact are bonded simultaneously to form the interconnection structure part 33, whereby the first interconnection sub-channel 31 is electrically connected through the interconnection structure part 33 so as to correspond to the second interconnection sub-channel 32, and it can be understood that the interconnection channel 30 of the memory cell is formed.

[0030] Referring back to FIGS. 1 and 2, in some embodiments of the present disclosure, a first set 40 of contacts is disposed on an outer side surface of the array substrate 11 (i.e., the surface facing away from the memory array). The array substrate 11 includes a plurality of first conductive channels 41 at positions corresponding to first interconnect sub-channels 31 within the memory array device 10 where the array substrate 11 is located. Each of these first conductive channels 41 penetrates through the surfaces located on two opposite sides of the array substrate 11 and is electrically connected to the corresponding first interconnect sub-channel 31. Thereby, the first set 40 of contacts is electrically connected to the first interconnect sub-channel 31 via the first conductive channels 41.

[0031] The first set 40 of contacts includes, but is not limited to, conductive structures such as wires, plugs, solder bumps, or pads. In some embodiments of the present disclosure, the first set 40 of contacts is a pad that is electrically connected to the first conductive channels 41.

[0032] The outer side surface of the array substrate 11 is covered with a first bonding layer 42. The end of the first conductive channel 41 far from the first interconnect sub-channel 31 and the first set 40 of contacts are both embedded within the first bonding layer 42. The first bonding layer 42 can be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The first bonding layer 42 includes at least one dielectric layer made of a dielectric material including, but not limited to, silicon oxide or silicon nitride, but is not limited thereto.

[0033] In some embodiments of the present disclosure, the first conductive channel 41 can be formed using conventional means such as, for example, Si through electrode technology. In some implementation forms, deep etching is performed at the positions of the first bonding layer 42 and the array substrate 11 corresponding to the plurality of first interconnect sub-channels 31 to form a plurality of first vertical channels penetrating the first bonding layer 42 and the array substrate 11. Each of the first vertical channels exposes at least a part of the corresponding first interconnect sub-channel 31, and then a conductive material is filled into the first vertical channels until it exceeds the outer side surface of the array substrate 11, thereby forming the first conductive channel 41 in contact with the first interconnect sub-channel 31. The end of the first conductive channel 41 far from the first interconnect sub-channel 31 is located within the first bonding layer 42. Leakage of the conductive material in the first vertical channels can be avoided in the manufacturing process of the first conductive channel 41 by covering the outer side surface of the array substrate 11 with the first bonding layer 42 to avoid contamination of other manufacturing processes.

[0034] In some embodiments of the present disclosure, after the formation of the first conductive channel 41, when the position of the first bonding layer 42 corresponding to the first conductive channel 41 is etched, an opening is formed that exposes the end portions of a plurality of first conductive channels 41 that are far from the first interconnect sub-channel 31. Then, a first set 40 of contacts (i.e., pads) is disposed within these openings, whereby the first set 40 of contacts is electrically connected to correspond to the plurality of first conductive channels 41. In some embodiments of the present disclosure, after the first set 40 of contacts is disposed within the openings of the first bonding layer 42, the dielectric material of the first bonding layer 42 is refilled within these openings to cover the first set 40 of contacts, thereby avoiding the exposure of the first set 40 of contacts, and thereby preventing damage to the first set 40 of contacts prior to the bonding connection with the second set 50 of corresponding contacts. This is preferable to improve the certainty of the bonding connection of the first set 40 of contacts with the second set 50 of corresponding contacts. Of course, in other embodiments, the first set 40 of contacts may also be exposed. It will be understood that when the first set 40 of contacts within the openings of the first bonding layer 42 is covered with a dielectric material, the first bonding layer 42 needs to be thinned or etched prior to the bonding connection of the first set 40 of contacts with the second set 50 of corresponding contacts in order to remove the dielectric material and expose the first set 40 of contacts within the openings.

[0035] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, a second set 50 of contacts of the second memory cell is disposed on an outer side surface of the CMOS substrate 21 of the second memory cell 200 (i.e., a surface facing away from the CMOS circuit). The CMOS substrate 21 includes a plurality of second conductive channels 60 at positions corresponding to the second interconnect sub-channels 32 within the CMOS device 20 where the CMOS substrate 21 is located. Each of the second conductive channels 60 penetrates through the surfaces located on two opposite sides of the CMOS substrate 21 and is electrically connected to each of the second set 50 of contacts of the CMOS device 20 and the CMOS circuit, whereby the second set 50 of contacts is electrically connected to the CMOS circuit of the CMOS device 20 via the second conductive channels 60. Of course, in other embodiments, the second conductive channels 60 do not have to correspond to the second interconnect sub-channels 32 as long as they are electrically connected to the CMOS circuit of the CMOS device 20.

[0036] The second set 50 of contacts includes, but is not limited to, conductive structures such as wires, plugs, solder bumps, or pads. In some embodiments of the present disclosure, the second set 50 of contacts is a plurality of solder bumps that are electrically connected to the plurality of second conductive channels 60 in a one-to-one correspondence.

[0037] The outer side surface of the CMOS substrate 21 of the second memory cell 200 is covered with a second bonding layer 52, and both the end of the second conductive channel 60 far from the second interconnect sub-channel 32 and the second set 50 of contacts are embedded within the second bonding layer 52. Similar to the first bonding layer 42, the second bonding layer 52 can also be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. Similarly, the second bonding layer 52 includes, but is not limited to, at least one dielectric layer made of a dielectric material including silicon oxide or silicon nitride.

[0038] In some embodiments of the present disclosure, the formation processes of the second conductive channel 60 and the first conductive channel 41 are substantially the same. In some implementations, deep etching is first performed at the positions of the second bonding layer 52 and the CMOS substrate 21 corresponding to the plurality of second interconnect sub-channels 32 to form a plurality of second vertical channels penetrating the second bonding layer 52 and the CMOS substrate 21. Each second vertical channel exposes at least a portion of the corresponding second interconnect sub-channel 32. Then, a conductive material is filled into the second vertical channels until the outer side surface of the CMOS substrate 21 is exposed, thereby forming a second conductive channel 60 in contact with the second interconnect sub-channel 32, whereby the second conductive channel 60 is electrically connected to the CMOS circuit, and the end of the second conductive channel 60 far from the second interconnect sub-channel 32 is located within the second bonding layer 52. Leakage of the conductive material in the second vertical channels can be avoided in the manufacturing process of the second conductive channel 60 by covering the outer side surface of the CMOS substrate 21 with the second bonding layer 52 to avoid contamination of other manufacturing processes. The conductive material filled into the second vertical channels and the aforementioned first vertical channels includes, but is not limited to, tungsten, copper, aluminum, polysilicon, silicide, or any combination thereof, and may be the same or different.

[0039] In some embodiments of the present disclosure, the manufacturing process of the second set 50 of contacts is different from that of the first set 40 of contacts in that, after the formation of the second conductive channels 60, one solder bump is disposed directly within each second vertical channel of the second bonding layer 52, and the plurality of solder bumps within the plurality of second vertical channels constitute the second set 50 of contacts. Further, similar to the first set 40 of contacts, the second set 50 of contacts may be covered or exposed in some embodiments of the present disclosure. In some implementation forms, the second set 50 of contacts may be covered prior to bonding connection with the corresponding first set 40 of contacts to prevent damage to the second set 50 of contacts, which is also preferably done to improve the certainty of the bonding connection of the first set 40 of contacts with the corresponding second set 50 of contacts. If the solder bumps within each second vertical channel of the second bonding layer 52 are covered by the dielectric material of the second bonding layer 52 (i.e., the second set 50 of contacts is covered), it should be understood that the second bonding layer 52 needs to be thinned or etched to remove the dielectric material within each second dielectric channel to expose the solder bumps within each second vertical channel, i.e., to expose the second set 50 of contacts for bonding with the corresponding first set 40 of contacts.

[0040] As shown in FIGS. 1 and 2, for any two adjacent memory cells, after the first set 40 of contacts of the lower memory cell is bonded corresponding to the second set 50 of contacts of the other upper memory cell, the respective CMOS circuits of the two adjacent memory cells are connected together, and it can be understood that the first bonding layer 42 of the lower memory cell is integrally attached to the second bonding layer 52 of the other upper memory cell.

[0041] Referring to FIGS. 1 and 2, in some embodiments of the present disclosure, the three-dimensional memory device further includes an insulating layer 300 and an array pad 400 embedded in the insulating layer 300. In some implementations, the insulating layer 300 covers a surface facing away from the first memory cell 100 of the outer second memory cell 200 and a first set 40 of contacts of the outer second memory cell 200. The insulating layer 300 includes a receiving cavity at a position corresponding to the first set 40 of contacts of the outer second memory cell 200, and the receiving cavity corresponds to at least a portion of the first set 40 of contacts. The array pad 400 is disposed in the receiving cavity of the insulating layer 300 and is electrically connected to the first set 40 of contacts of the outer second memory cell 200, and the three-dimensional memory device is electrically connected to the aforementioned external device via the array pad 400.

[0042] The receiving cavity of the insulating layer 300 may be formed by conventional means such as etching, for example, and this means will not be described again. The array pad 400, as well as the aforementioned solder bumps and pads, etc., may be fabricated by conventional means of the prior art, and this will not be described again.

[0043] It should be noted that, similar to the first bonding layer 42 and the second bonding layer 52, the insulating layer 300 can also be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. Further, the insulating layer 300 may include at least one dielectric layer made of a dielectric material including, but not limited to, silicon oxide or silicon nitride, but is not limited thereto.

[0044] The receiving cavity of the insulating layer 300 may be a cavity with one end opening to the outer second memory cell. Therefore, the array pad 400 is preferably covered by the insulating layer 300 before connection to an external device to protect the array pad 400. However, when the array pad 400 is electrically connected to an external device, the position of the insulating layer 300 corresponding to the receiving cavity needs to be thinned or etched to expose the array pad 400. Naturally, the receiving cavity of the insulating layer 300 may be a cavity structure having openings at both ends, whereby the array pad 400 is exposed so as to facilitate direct electrical connection with an external device.

[0045] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, the insulating layer 300 covers the outer side surface of the first bonding layer 42 of the second memory cell 200 at the outermost position. It will be understood that both the insulating layer 300 and the first bonding layer 42 are formed of a dielectric material, and thus the materials of the insulating layer 300 and the first bonding layer 42 may be the same or different. That is, the insulating layer 300 and the first bonding layer 42 may be formed in different thin film deposition processes or in the same thin film deposition process. In some implementations, the insulating layer 300 and the first bonding layer 42 are formed in different thin film deposition processes, so that the first set of contacts 40 and the array pad 400 may be disposed at different times in different thin film deposition processes. This is convenient in practice. Further, the first bonding layer 42 and the insulating layer 300 are formed at different times. When the first bonding layer 42 and the insulating layer 300 are etched separately, the etching depth is small, which is preferable for improving etching efficiency and etching accuracy.

[0046] As shown in FIGS. 1 and 2, in some embodiments of the present disclosure, the three-dimensional memory device further includes a protective layer 500 laminated on the outer side surface of the insulating layer 300. This protective layer 500 covers the insulating layer 300 and has an opening at a position corresponding to the array pad 400. At least a part of the array pad 400 is exposed through this opening for connection to an external device. Of course, in other embodiments, the protective layer 500 may also protect the array pad 400 by covering the array pad 400, but when electrically connecting the array pad 400 to an external device, the position of the protective layer 500 corresponding to the array pad 400 needs to be thinned or etched to expose the array pad 400.

[0047] By covering the insulating layer 300 with the protective layer 500, the insulating layer 300 can be protected from damage, thereby preventing the array pad 400 from loosening due to damage to the insulating layer 300 and ensuring the reliability of the connection of the array pad 400.

[0048] The protective layer 500 may be made of a material such as silicon nitride or silicon oxide, and the opening may be formed by conventional means such as etching. These will not be described again in this specification.

[0049] Referring to FIG. 3, the present disclosure further provides a method for manufacturing the three-dimensional memory device described above. This method includes the following steps.

[0050] Step S1. Prepare a first memory cell and a second memory cell each having a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected to each other. The first set of contacts is disposed on a surface facing away from the CMOS device of the memory array device and is electrically connected to the CMOS device.

[0051] Referring to FIGS. 4 to 7 together, in some implementation forms, the manufacturing process of the memory cell is as follows.

[0052] First step: Prepare a memory array device 10 and a CMOS device 20. As shown in FIG. 4, the memory array device 10 includes an array substrate 11, a memory array disposed on the inner side surface of the array substrate 11 (i.e., the surface close to the CMOS device 20), a first interconnect sub-channel 31 disposed in the memory array, and a first interconnect contact 331 disposed on the inner side surface of the memory array device 10 and electrically connected to the first interconnect sub-channel 31. The memory array includes a plurality of memory layers 13 having a step structure and a plurality of memory strings penetrating through and connecting the plurality of memory layers 13. As shown in FIG. 4, the CMOS device 20 includes a CMOS substrate 21, a CMOS circuit disposed on the inner side surface of the CMOS substrate 21 (i.e., the surface close to the memory array device 10), a second interconnect sub-channel 32 disposed on one surface of the CMOS circuit and electrically connected to the CMOS circuit, and a second interconnect contact 332 disposed on the inner side surface of the CMOS device 20 and electrically connected to the second interconnect sub-channel 32. Note that since the specific features, functions, and formation processes of the array substrate 11, the plurality of memory layers 13, the plurality of memory strings, the CMOS substrate 21, the first interconnect sub-channel 31, the second interconnect sub-channel 32, the first interconnect contact 331, and the second interconnect contact 332 can refer to the corresponding content in the three-dimensional memory device described above, they will not be described again here. Further, the memory array device 10 and the CMOS device 20 each further include some other elements, and the specific structures and functions of the memory array device 10 and the CMOS device 20 are substantially the same as the structures and functions of existing memory array devices and CMOS devices and are not related to the improvement and innovation of the present disclosure, so they will not be described again in this specification.

[0053] Second step. Face-bonding the memory array device 10 and the CMOS device 20. As shown in FIG. 5, after the alignment bonding of the memory array device 10 and the CMOS device 20, the aforementioned first interconnect contact 331 and the second interconnect contact 332 (as shown in FIG. 4) are further bonded to form an interconnect structure 33. Thereby, the aforementioned first interconnect sub-channel 31 is electrically connected corresponding to the second interconnect sub-channel 32 via the interconnect structure 33, thereby forming an interconnect channel 30 of the memory cell. This interconnect channel 30 is electrically connected to a first set 40 of contacts of the memory cell where the interconnect channel 30 is located and the CMOS device 20. Thereby, the first set 40 of contacts is electrically connected to the CMOS device 20 via the interconnect channel 30.

[0054] Third step. As shown in FIG. 6, thinning the outer side surface of the array substrate 11 of the memory array device 10 (i.e., the surface facing away from the memory array). Thinning means include, but are not limited to, mechanical polishing, wet / dry etching, chemical mechanical polishing, or any combination thereof.

[0055] Step 4. Form a first set 40 of contacts on the outer side surface of the memory array device 10, whereby the first set 40 of contacts is electrically connected to the first interconnect sub-channel 31. As shown in FIG. 7, in some embodiments of the present disclosure, the outer side surface of the array substrate 11 is covered with a first bonding layer 42. The first conductive channel 41 that penetrates the array substrate 11 and is electrically connected to the first interconnect sub-channel 31 can be formed by conventional technical means. Both the end of the first conductive channel 41 far from the first interconnect sub-channel 31 and the first set 40 of contacts are embedded in the first bonding layer 42, and the first set 40 of contacts is electrically connected to the first interconnect sub-channel 31 via the first conductive channel 41. Similarly, the specific features, functions, or formation processes of the first bonding layer 42 and the first conductive channel 41 may refer to the corresponding content in the three-dimensional memory device described above and will not be described again here.

[0056] The first memory cell 100 and the part of the second memory cell 200 that is the same as the first memory cell 100 can be manufactured in the above-described first step to fourth step.

[0057] Step S2. Thinning the surface of the CMOS device of the second memory cell that faces away from the memory array device of the second memory cell. That is, the surface of the CMOS substrate of the second memory cell that faces away from the CMOS circuit is thinned, and the thinning means includes, but is not limited to, mechanical polishing, wet / dry etching, chemical mechanical polishing, or any combination thereof.

[0058] Referring to both FIGS. 8 and 9, in some embodiments of the present disclosure, before step S2, the method for manufacturing a three-dimensional memory device includes preparing a carrier and attaching the carrier to a surface of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell, whereby the carrier covers the surface of the memory array device of the second memory cell to which the carrier is attached and facing away from the CMOS device of the second memory cell and the first set of contacts of the second memory cell.

[0059] In some implementations, as shown in FIGS. 8 and 9, first, the second memory cell 200 is inverted upside down so that the memory array device 10 of the second memory cell 200 is positioned below, and then the carrier 600 is attached to the outer side surface of the memory array device 10 of the second memory cell 200 (i.e., the surface facing away from the CMOS device 20 of the second memory cell 200), whereby the carrier 600 covers the outer side surface of the memory array device 10 of the second memory cell to which the carrier is attached and the first set of contacts 40. Finally, the CMOS substrate 21 of the second memory cell 200 is thinned. By attaching the carrier 600 to the outer side surface of the memory array device 10 of the second memory cell 200, the carrier 600 can play a role in supporting the second memory cell 200, which is thus preferable for reducing and even avoiding deformation of the second memory cell 200 in the transport process or the thinning process of the CMOS substrate 21.

[0060] The carrier 600 may be made of glass, sapphire, or a semiconductor material, but is not limited thereto.

[0061] Attaching the carrier 600 to the outer side surface of the memory array device 10 of the second memory cell 200 includes the following steps.

[0062] First, the surface of the carrier 600 facing the second memory cell 200 and / or the outer side surface of the memory array device 10 of the second memory cell 200 are coated with any bonding adhesive selected from the group consisting of a heat-curable adhesive, an ultraviolet radiation-curable adhesive, a heat-decomposable adhesive, and a laser-decomposable adhesive. In some implementations, both the surface of the carrier 600 facing the second memory cell 200 and the outer side surface of the memory array device 10 of the second memory cell 200 are coated with the bonding adhesive, thereby strengthening the adhesion between the carrier 600 and the outer side surface of the memory array device 10 of the second memory cell 200.

[0063] Next, the carrier 600 is bonded to the outer side surface of the memory array device 10 of the second memory cell 200 by a temporary bonding process or a permanent bonding process. The temporary bonding process refers to a process means used to bond the carrier 600 to the outer side surface of the memory array device 10 of the second memory cell 200, which allows the carrier 600 to be easily removed from the outer side surface of the memory array device 10 as needed. In this case, the carrier 600 can be easily removed. The permanent bonding process refers to a process means used to bond the carrier 600 to the outer side surface of the memory array device 10 of the second memory cell 200, which allows the carrier 600 to be removed from the outer side surface of the memory array device 10 by additionally applying a large external force. Here, the bonding connection between the carrier 600 and the memory array device 10 of the second memory cell 200 is firm.

[0064] It will be appreciated that in some embodiments of the present disclosure, the outer side of the memory array device 10 of the second memory cell 200 is covered with the first bonding layer 42, and therefore in some implementations, the carrier 600 can be bonded to the outer side of the first bonding layer 42.

[0065] Step S3. Forming a second set of contacts on a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell. The second set of contacts is electrically connected to the CMOS device of the second memory cell.

[0066] Referring to both FIGS. 10 and 11, in some embodiments of the present disclosure, step S3 of the method for manufacturing a three-dimensional memory device includes the following steps, namely Forming a via (i.e., the aforementioned second vertical direction channel) penetrating the CMOS substrate 21 on the CMOS substrate 21 of the second memory cell 200, wherein the via exposes at least a part of the interconnect channel 30 of the second memory cell 200 (i.e., at least a part of the aforementioned second interconnect sub-channel 32), the step of Filling the via with a conductive medium to form a conductive channel (i.e., the aforementioned second conductive channel 60) electrically connected to the interconnect channel 30 of the second memory cell 200, the step of Forming a second set of contacts 50 of the second memory cell 200 from the ends of these conductive channels facing away from the interconnect channel 30 of the second memory cell 200 (i.e., the ends of the second conductive channel 60 far from the second interconnect sub-channel 32), whereby the second set of contacts 50 is electrically connected to the interconnect channel 30 of the second memory cell 200 through these conductive channels, the step of including.

[0067] As shown in FIGS. 10 and 11, before the step of forming the second set 50 of contacts, the outer side surface of the CMOS substrate 21 of the second memory cell 200 (i.e., the surface facing away from the CMOS circuit) is first coated with the second bonding layer 52, and then a second conductive channel 60 that penetrates the CMOS substrate 21 and is electrically connected to the second interconnect sub-channel 32 can be formed by conventional technical means. Both the end of the second conductive channel 60 far from the second interconnect sub-channel 32 and the second set 50 of contacts are embedded in the second bonding layer 52, and the second set 50 of contacts is electrically connected to the CMOS circuit of the CMOS device 20 via the second conductive channel 60 and is simultaneously electrically connected to the second interconnect sub-channel 32 of the interconnect channel 30. Similarly, the specific features, functions, or formation processes of the second bonding layer 52 and the second conductive channel 60 may refer to the corresponding content in the three-dimensional memory device described above and will not be described again here.

[0068] After the step of forming the second set 50 of contacts on the outer side surface of the CMOS device 20 of the second memory cell 200 (i.e., the surface facing away from the memory array device 10 of the first memory cell, i.e., the outer side surface of the CMOS substrate), the method for manufacturing a three-dimensional memory device further includes step S4, i.e., stacking a second memory cell on the surface of the memory array device of the first memory cell facing away from the CMOS device of the first memory cell, bonding the memory array device of the first memory cell to the CMOS device of the second memory cell, whereby the first set of contacts of the first memory cell is electrically connected corresponding to the second set of contacts of the second memory cell.

[0069] In some embodiments, referring to FIG. 12, after the carrier 600 is bonded to the outer side surface of the memory array device 10 of the second memory cell 200, the second memory cell 200 is turned upside down, whereby the CMOS device 20 of the second memory cell 200 faces the memory array device 10 of the first memory cell 100. Next, the CMOS device 20 of the second memory cell 200 is bonded face-to-face to the memory array device 10 of the first memory cell 100, whereby the first set 40 of contacts of the first memory cell 100 is electrically connected corresponding to the second set 50 of contacts of the second memory cell 200, and then the first memory cell 100 is electrically connected to the second memory cell 200 via the first set 40 of corresponding contacts, the second set 50 of contacts, and the respective interconnect channels 30 of each memory cell. At this point, the first bonding layer 42 of the first memory cell 100 is attached to the second bonding layer 52 of the second memory cell 200.

[0070] Referring to FIG. 13, in some embodiments of the present disclosure, when the carrier 600 is bonded to the outer side surface of the memory array device 10 of the second memory cell 200, the method of manufacturing a three-dimensional memory device further includes stacking the second memory cell 200 on the first memory cell 100, bonding the CMOS device 20 of the second memory cell 200 to the memory array device 10 of the first memory cell 100, and then removing the carrier 600 to expose the first set 40 of contacts of the second memory cell 200.

[0071] Referring to FIG. 1, in some embodiments of the present disclosure, after bonding the CMOS device 20 of the second memory cell 200 to the memory array device 10 of the first memory cell 100 and exposing the first set 40 of contacts of the second memory cell 200, the method of manufacturing a three-dimensional memory device includes the following steps, namely Forming an insulating layer 300 on a surface of the memory array device 10 of the second external memory cell 200 facing away from the CMOS device 20 of the second external memory cell 200, wherein the insulating layer 300 covers the surface of the memory array device 10 of the second external memory cell 200 facing away from the CMOS device 20 of the second external memory cell 200 and the first set 40 of contacts of the second external memory cell 200, and the second external memory cell 200 is the second memory cell 200 stacked on the first memory cell 100 and located farthest from the first memory cell 100 along the stacking direction. Disposing an array pad 400 in the insulating layer 300 and electrically connecting the array pad 400 to the first set 40 of contacts of the second external memory cell so as to correspond. Forming a protective layer 500 having an opening on a surface of the insulating layer 300 facing away from the second external memory cell 200, whereby the protective layer 500 covers the insulating layer 300 and the opening exposes the array pad 400. Further comprising The insulating layer 300 covers the surface of the first bonding layer 42 of the second external memory cell 200 facing away from the array substrate 11. The exposed array pad 400 is used for connection to an external device (such as a control device or a driving circuit, etc.). The protective layer 500 is used to ensure the reliability of the connection of the array pad 400 by protecting the insulating layer 300 from damage. The specific features, functions, or formation processes of the insulating layer 300, the array pad 400, and the protective layer 500 may refer to the corresponding content in the three-dimensional memory device described above and will not be described again here.

[0072] In some embodiments of the present disclosure, by the above steps, the first memory cell 100 and the second memory cell 200 are stacked, so that a three-dimensional memory device 1000 (as shown in FIG. 1) having a high storage density can be configured without the need to stack an excessive number of memory layers 13 in the memory array device 10 of each memory cell. As a result, the area of the array substrate 11 of each memory cell does not become overly large, which is preferable for arranging the array substrate 11 of each memory cell and the CMOS substrate 21 in an appropriate area ratio. It is possible to further reduce the unused space in each memory cell, and it is possible to increase the space utilization rate of the three-dimensional memory device.

[0073] In some implementation forms, in the three-dimensional memory device 1000, each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 includes a preset number of memory layers 13, and the numerical value of the preset number of layers is an integer greater than 0 and less than 500, for example, 32 layers, 64 layers, 96 layers, or 128 layers. The number of memory layers 13 in each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 may be the same or may not be the same. In some implementation forms, the number of memory layers 13 in each of the memory array devices 10 of the first memory cell 100 and the second memory cell 200 may be the same for the mass production of the first memory cell 100 and the second memory cell 200 in the same process step.

[0074] Referring to FIG. 2, in some other embodiments of the present disclosure, the number of the second memory cells 200 may be set as a plurality, and the manufacturing method of the three-dimensional memory device includes the following steps, that is Stacking one of the second memory cells 200 on a surface of the memory array device 10 of the first memory cell 100 facing away from the CMOS device 20 of the first memory cell 100, bonding the CMOS device 20 of one of the second memory cells 200 to the memory array device 10 of the first memory cell 100, whereby a second set 50 of contacts of one of the second memory cells 200 is electrically connected corresponding to a first set 40 of contacts of the first memory cell 100, a step; Stacking another one of the second memory cells 200 on a surface of the memory array device 10 of the outermost second memory cell 200 facing away from the CMOS device 20 of the outermost second memory cell 200, and bonding the CMOS device 20 of another one of the second memory cells 200 to the memory array device 10 of the outermost second memory cell 200, whereby a first set 40 of contacts of the outermost second memory cell 200 is electrically connected corresponding to a second set 50 of contacts of another one of the second memory cells 200, and repeating this step until a plurality of second memory cells 200 are continuously stacked on the first memory cell 100, the step being that the outermost second memory cell 200 is the second memory cell 200 stacked on the first memory cell 100 and located farthest away from the first memory cell 100 along the stacking direction, a step including.

[0075] To avoid deformation of the second memory cells 200, the surface of each second memory cell 200 facing away from the CMOS device 20 of the memory array device 10 may be bonded to the carrier 600. Thus, it should be noted that the step of removing the carrier 600 needs to be performed before bonding each second memory cell 200 to the other memory cell (the first memory cell 100 or another second memory cell 200). The carriers 600 bonded to these surfaces of the memory array device 10 of the plurality of second memory cells 200 may be the same carrier 600, that is, after the carrier 600 is removed from the memory array device 10 of one second memory cell 200, the carrier 600 is bonded again to the outer side surface of the memory array device 10 of the next second memory cell 200 to be stacked, and the carrier 600 is used repeatedly. Thereby, the number of carriers 600 can be reduced and the cost is lowered. Of course, the outer side surface of the memory array device 10 of each second memory cell 200 may be bonded to other carriers 600.

[0076] In some other embodiments of the present disclosure, by the above steps, a three-dimensional memory device 1000b (as shown in FIG. 2) can be constructed by continuously stacking the first memory cells 100 and the plurality of second memory cells 200. The number of memory cells of this three-dimensional memory device 1000b is larger than that of the three-dimensional memory device 1000. Therefore, the three-dimensional memory device 1000b has a higher storage density, and since it is not necessary to stack an excessive number of memory layers 13 in the memory array device 10 of each memory cell of the three-dimensional memory device 1000b, the space utilization rate of the three-dimensional memory device 1000b is increased thereby.

[0077] In these embodiments of the present disclosure, in the manufacturing process of a three-dimensional memory device, bonding is performed between the memory array device 10 of the first memory cell 100 and its CMOS device 20, between the memory array device 10 of the second memory cell 200 and its CMOS device 20, between the memory array device 10 of the first memory cell 100 and the CMOS device 20 of the second memory cell 200, and between the memory array device 10 of the second memory cell 200 and the CMOS device 20 of another second memory cell 200. The method used for this bonding includes an Xtacking bonding process. This Xtacking bonding process is called alignment bonding of the bonding structure parts between different devices in the same process step, thereby establishing electrical connection between the two devices. The use of the Xtacking bonding process is preferable for manufacturing each of the memory array device and the CMOS device and selecting a more advanced manufacturing process to reduce the complexity of the manufacturing procedure. Thereby, the three-dimensional memory device realizes a higher input / output transmission speed, a higher density, and a smaller volume.

[0078] Furthermore, the present disclosure provides a three-dimensional memory including any one of the above-described three-dimensional memory devices. This three-dimensional memory has advantages such as the high storage density and high space utilization rate of the above-described three-dimensional memory device, and also has other structural features and functions of the above-described three-dimensional memory device, which will not be described again here.

[0079] Although the embodiments of the present disclosure have been illustrated and described, various changes, modifications, alternatives, and variations may be made to these embodiments without departing from the principles and purposes of the present disclosure. It will be understood by those skilled in the art that the scope of the present disclosure is defined by the claims and their equivalents.

Description of Reference Numerals

[0080] 100 First memory cell 200 Second memory cell 10 Memory array device 11 Array substrate 13 Memory layer 20 CMOS device 21 CMOS substrate 30 Interconnection channel 31 First interconnection sub-channel 32 Second interconnection sub-channel 33 Interconnection structure part 331 First interconnection contact 332 Second interconnection contact 40 First set of contacts 41 First conductive channel 42 First bonding layer 50 Second set of contacts 52 Second bonding layer 300 Insulating layer 400 Array pad 500 Protective layer 60 Second conductive channel

Claims

1. A three-dimensional memory device comprising at least two memory cells stacked continuously, wherein the at least two memory cells include a first memory cell and at least one second memory cell stacked on the first memory cell, and each memory cell A memory array device and a CMOS device stacked and electrically connected to each other, A first set of contacts disposed on a surface of the memory array device facing away from the CMOS device and electrically connected to the CMOS device Comprising, The second memory cell further includes a second set of contacts, and the second set of contacts is disposed on a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell and is electrically connected to the CMOS device of the second memory cell, The memory array device of the first memory cell is bonded to the CMOS device of an adjacent second memory cell, and the first set of contacts of the first memory cell is electrically connected corresponding to the second set of contacts of the adjacent second memory cell, When there is one second memory cell, the second memory cell is an outer second memory cell stacked on the first memory cell, and the first set of contacts of the outer second memory cell is used for connection to an external device, When there are a plurality of second memory cells, the plurality of second memory cells are continuously stacked on the first memory cell. For two adjacent second memory cells among the second memory cells, the first set of contacts of the second memory cell closer to the first memory cell is electrically connected corresponding to the second set of contacts of the second memory cell farther from the first memory cell. The second memory cell farthest from the first memory cell along the stacking direction is defined as an outer second memory cell, and the first set of contacts of the outer second memory cell is used for connection to an external device. A three-dimensional memory device.

2. Further comprising an insulating layer and array pads embedded in the insulating layer, the insulating layer covering a surface facing away from the first memory cell of the second memory cell on the outside and a first set of contacts of the second memory cell on the outside, the array pads being electrically connected corresponding to the first set of contacts of the second memory cell on the outside and being used for connection to the external device, the three-dimensional memory device according to claim 1.

3. Further comprising a protective layer covering a surface facing away from the second memory cell on the outside of the insulating layer, The protective layer has an opening at a position corresponding to the array pad, and the array pad is exposed through the opening for connection to the external device, the three-dimensional memory device according to claim 2.

4. The memory array device comprises an array substrate, and the first set of contacts of each memory cell is disposed on a surface of the array substrate of the corresponding memory array device facing away from the corresponding CMOS device. The CMOS device comprises a CMOS substrate, and the second set of contacts of the second memory cell is disposed on a surface of the CMOS substrate of the second memory cell facing away from the memory array device of the second memory cell, the three-dimensional memory device according to any one of claims 1 to 3.

5. Each memory cell further comprises an interconnect channel, the interconnect channel being disposed within the memory array device and the CMOS device of the memory cell in which the interconnect channel is located. The interconnect channel is electrically connected to the first set of contacts of the memory cell in which the interconnect channel is located and the CMOS device respectively, whereby the first set of contacts is electrically connected to the CMOS device through the interconnect channel, the three-dimensional memory device according to claim 4.

6. The second memory cell further includes a conductive channel, the conductive channel penetrates the CMOS substrate of the second memory cell, and is electrically connected to a second set of the contacts of the second memory cell and the CMOS device respectively, whereby the second set of the contacts is electrically connected to the CMOS device of the second memory cell where the conductive channel is located via the conductive channel. The three-dimensional memory device according to claim 5.

7. Each of the memory array devices of the first memory cell and the memory array devices of the second memory cell includes memory layers with a preset number of layers, and the numerical value of the preset number of layers is an integer greater than 0 and less than 500. The three-dimensional memory device according to any one of claims 1 to 3.

8. A method for manufacturing a three-dimensional memory device, A step of preparing a first memory cell and a second memory cell, each including a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected to each other, wherein the first set of contacts is disposed on a surface facing away from the CMOS device of the memory array device and is electrically connected to the CMOS device. A step of thinning a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell. A step of forming a second set of contacts on the surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, wherein the second set of contacts is electrically connected to the CMOS device of the second memory cell. A step of stacking the second memory cell on a surface of the memory array device of the first memory cell facing away from the CMOS device of the first memory cell, and bonding the memory array device of the first memory cell to the CMOS device of the second memory cell, whereby the first set of contacts of the first memory cell is electrically connected corresponding to the second set of contacts of the second memory cell. A method for manufacturing a three-dimensional memory device, including the above steps.

9. There are a plurality of second memory cells, and the following steps, namely stacking one of the second memory cells on a surface of the memory array device of the first memory cell facing away from the CMOS device of the first memory cell, and bonding the CMOS device of one of the second memory cells to the memory array device of the first memory cell, whereby a second set of contacts of one of the second memory cells is electrically connected corresponding to the first set of contacts of the first memory cell; stacking another one of the second memory cells on a surface of the memory array device of the outer second memory cell facing away from the CMOS device of the outer second memory cell, and bonding the CMOS device of the other one of the second memory cells to the memory array device of the outer second memory cell, whereby a first set of contacts of the outer second memory cell is electrically connected corresponding to a second set of contacts of the other one of the second memory cells, and repeating this step until a plurality of second memory cells are continuously stacked on the first memory cell, wherein the outer second memory cell is the second memory cell stacked on the first memory cell and located farthest from the first memory cell along the stacking direction; The method for manufacturing a three-dimensional memory device according to claim 8, comprising the above steps.

10. Before the step of thinning a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell, the following steps, namely preparing a carrier, and mounting the carrier on a surface of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell, whereby the carrier covers the surface of the memory array device of the second memory cell with the carrier mounted thereon facing away from the CMOS device of the second memory cell and the first set of contacts of the second memory cell; The method for manufacturing a three-dimensional memory device according to claim 8 or 9, further comprising the above steps.

11. Stack the second memory cell on top of another memory cell, and after bonding the CMOS device of the second memory cell to the memory array device of the other memory cell, perform the following steps, namely The step of removing the carrier to expose a first set of contacts of the second memory cell further comprises The method for manufacturing a three-dimensional memory device according to claim 10, wherein the other memory cell is the remaining one of the first memory cell or the second memory cell.

12. A step of forming an insulating layer on a surface of the memory array device of the outer second memory cell facing away from the CMOS device of the outer second memory cell, wherein the insulating layer covers the surface of the memory array device of the outer second memory cell facing away from the CMOS device of the outer second memory cell and a first set of contacts of the outer second memory cell, and the outer second memory cell is a second memory cell stacked on the first memory cell and located farthest from the first memory cell along the stacking direction. A step of embedding array pads in the insulating layer and electrically connecting the array pads corresponding to the first set of contacts of the outer second memory cell The method for manufacturing a three-dimensional memory device according to claim 8 or 9, further comprising.

13. The method for manufacturing a three-dimensional memory device according to claim 12, further comprising a step of forming a protective layer having an opening on a surface of the insulating layer facing away from the outer second memory cell, so that the protective layer covers the insulating layer and the opening exposes the array pads.

14. The step of mounting the carrier on the surface of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell specifically comprises Coating a surface of the carrier facing the second memory cell and / or a surface of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell with any bonding adhesive among a thermosetting adhesive, an ultraviolet irradiation curable adhesive, a thermal decomposable adhesive, or a laser decomposable adhesive. Bonding the carrier to a surface of the memory array device of the second memory cell facing away from the CMOS device of the second memory cell by a temporary bonding process or a permanent bonding process The method of manufacturing a three-dimensional memory device according to claim 10, comprising:

15. Each memory cell further comprises an interconnect channel, the interconnect channel is disposed in the memory array device and the CMOS device of the memory cell where the interconnect channel is located, and is electrically connected to each of a first set of contacts of the memory cell where the interconnect channel is located and the CMOS device. The first set of contacts is electrically connected to the CMOS device via the interconnect channel, and the CMOS device comprises a CMOS substrate. The step of forming a second set of contacts on a surface of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell specifically comprises: Forming vias penetrating the CMOS substrate on the CMOS substrate of the second memory cell, the vias exposing at least a part of the interconnect channel of the second memory cell; Forming a conductive channel electrically connected to the interconnect channel of the second memory cell by filling a conductive medium in the vias; Forming a second set of contacts of the second memory cell from an end of the conductive channel far from the interconnect channel of the second memory cell, so that the second set of contacts is electrically connected to the interconnect channel of the second memory cell via the conductive channel. The method of manufacturing a three-dimensional memory device according to claim 8, comprising:

16. The method used for bonding between the memory array device of the first memory cell and the CMOS device, bonding between the memory array device of the second memory cell and the CMOS device, bonding between the memory array device of the first memory cell and the CMOS device of the second memory cell, and bonding between the memory array device of the second memory cell and the CMOS device of the other second memory cell includes an exstacking bonding process, the method for manufacturing a three-dimensional memory device according to claim 9.

17. A three-dimensional memory comprising the three-dimensional memory device according to any one of claims 1 to 7.

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