Semiconductor device

Abstract

To provide a semiconductor device in which the cell size is small in a diode region of RC-IGBT, the voltage in a conduction state at low voltage application time is low, the recovery time after the conduction of large current is short, and the breakdown voltage is high.SOLUTION: A semiconductor device 1 includes an IGBT region 2 and a diode region 3 in the same chip. A diode 30 includes a first semiconductor layer 31 of a second conductivity type held between third trenches 13 and a second semiconductor layer 32 of the second conductivity type whose impurity concentration is lower than that in the first semiconductor layer 31, a third semiconductor layer 33 of a first conductivity type, a fourth trench 14 that penetrates the first semiconductor layer 31 and the second semiconductor layer 32 and reaches the third semiconductor layer 33, and a first electrode 51 provided inside the fourth trench 14. A side surface of the fourth trench 14 is in contact with the first semiconductor layer 31 and the second semiconductor layer 32. In at least a bottom surface of the fourth trench 14, the first electrode 51 is subjected to Schottky junction with the third semiconductor layer 33.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] An RC-IGBT (RC: Reverse-Conducting, reverse-conducting IGBT) incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode in the same chip has the advantage of reducing the chip size because the termination regions of the IGBT and the diode can be shared. Also, since the timings at which the IGBT and the diode operate are different, heat generated by losses occurring in one of the IGBT region and the diode region is dispersed to the other, and heat can be dissipated throughout the chip, so there is also an advantage of reducing the thermal resistance.

[0003] On the other hand, since an RC-IGBT fabricates an IGBT and a diode in the same chip, there is a problem that it is difficult to optimize the IGBT and the diode simultaneously.

[0004] As a technique for shortening the recovery time of a diode or a diode built in an RC-IGBT, for example, there is Patent Document 1. In FIGS. 1 to 3 and paragraphs 0009 to 0038 of Patent Document 1, a pin diode is formed by a p+ semiconductor region (31), an n- semiconductor region (21), and an n+ semiconductor region (22), and a connection region (16) connected to a second electrode (11) which is an anode electrode penetrates the p+ semiconductor region (31) and reaches the n- semiconductor region (21), and an SBD (Schottky barrier diode) is formed by the connection region (16) and the n- semiconductor region (21). In a low current conduction state, the SBD operates preferentially over the pin diode, increasing the current when a low voltage is applied compared to the pin diode, reducing the voltage in the conduction state, and in a high current conduction state, the pin diode operates preferentially over the SBD. By reducing the width of the p+ semiconductor region (31) in the Y-axis direction or the contact area between the p+ semiconductor region (31) and the second electrode (11), the amount of hole injection from the anode side is suppressed, and a technique for shortening the recovery time is described. And in FIG. 12 of Patent Document 1, an application of the above-described technique to a diode region (7D) built in an RC-IGBT is described.

[0005] Also, as another technique for forming an SBD in a diode built in an RC-IGBT, for example, there is Patent Document 2. In FIG. 1 of Patent Document 2, a Schottky barrier diode (10) is formed between the side wall of a Si etch region (7) (second trench) provided in a diode portion of an RC-IGBT and an n drift layer (n- layer) (3), and a p+ layer (16) and a p layer (17) are formed below the Si etch region (7), and a technique for forming a pn diode between the p+ layer (16) and the p layer (17) and the n drift layer (n- layer) (3) is described.

[0006] As another technology in which an SBD is formed in the diode built into the RC-IGBT, for example, there is Patent Document 3. In FIG. 35 and paragraph 132 of Patent Document 3, in the diode region (108) of the RC-IGBT, a metal pillar electrode (142a) is in conduction with the emitter / anode electrode (148), penetrates the p anode region (124), and forms a Schottky junction with the n barrier region (122) via a Schottky interface (152a).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0008] However, in the technology described in FIG. 12 of Patent Document 1, since there is no p-type semiconductor region with a lower concentration than the p+-type semiconductor region (31) around the connection region (16), when the breakdown voltage is maintained (when a reverse bias is applied and the diode is off), the electric field concentrates at the corners of the connection region (16), and there are concerns about a decrease in breakdown voltage and an increase in leakage current.

[0009] Note that in FIG. 11 of Patent Document 1, a p-type semiconductor region (30) having an impurity concentration lower than that of the p-type base region (32) of the IGBT in the p+-type semiconductor region (31) and the IGBT region (7RI) is provided in the diode region (7D) incorporated in the RC-IGBT, covering the bottom surface and the side surface of the connection region (16). Here, in FIGS. 8 and paragraph 0064 of Patent Document 1, since a low-concentration p-type semiconductor region (30) is provided between the n−-type semiconductor region (21) and the p+-type semiconductor region (31), in the semiconductor device (4), a depletion layer also extends from the junction between the p-type semiconductor region (30) and the n−-type semiconductor region (21) in the off state, whereby the breakdown voltage in the off state further increases, and since the p-type semiconductor region (30) is a low-concentration region, it does not affect the current rise in the low-current conduction state, so that in the semiconductor device (4), the on-voltage is reduced is described.

[0010] However, in the configurations of FIGS. 8 and 11 of Patent Document 1, since the SBD is not formed, although Patent Document 1 describes that the p-type semiconductor region (30) is a low-concentration region and thus does not affect the current rise in the low-current conduction state, in reality, since it becomes a pn junction, a built-in voltage for the rise occurs to some extent compared to the Schottky junction, and there is a problem that the current rise in the low-current conduction state is affected to some extent. Note that the built-in voltage becomes less noticeable as the p-type semiconductor region (30) is made lower in concentration, but if the p-type semiconductor region (30) is made too low in concentration so that the built-in voltage is not noticeable, there is a trade-off problem that the breakdown voltage cannot be obtained.

[0011] Further, in the technique of FIG. 1 of Patent Document 2, since the Schottky barrier diode (10) is formed between the side wall of the Si etch region (7) (second trench) and the n-drift layer (n−-layer) (3), the Si etch region (7) (second trench) cannot be sufficiently covered with the p-layer (17) around it, so there is a possibility that a sufficient breakdown voltage cannot be ensured during breakdown voltage retention (when a reverse bias is applied and the diode is off).

[0012] Also, in the technology of FIG. 35 of Patent Document 3, there is a problem that the cell size increases because there is a gap between the p+ contact region (144) and the pillar electrode (142a), and a p anode region (124) exists therebetween. Further, since the cell size is large, the distance between the gate electrode (140) of the diode region (108) and the pillar electrode (142a) also becomes long, so that the electric field relaxation at the bottom of the pillar electrode (142a) becomes insufficient, and there is a problem that it is difficult to ensure the breakdown voltage.

[0013] The problem to be solved by the present invention is to provide a semiconductor device having a small cell size, a low voltage in the conduction state when a low voltage is applied, a short recovery time after large current conduction, and a high breakdown voltage in the diode region of an RC-IGBT.

Means for Solving the Problem

[0014] To solve the above problems, a semiconductor device according to the present invention is a semiconductor device having an IGBT region and a diode region within the same chip, wherein the IGBT in the IGBT region includes a plurality of first trenches each having a gate electrode provided therein, an emitter layer of a first conductivity type sandwiched between the first trenches, a body layer of a second conductivity type sandwiched between the first trenches and provided in a layer lower than the emitter layer, a second trench penetrating the emitter layer and provided up to the middle of the body layer, and an emitter electrode electrically connected to the emitter layer and the body layer via the second trench; and the diode in the diode region includes a plurality of third trenches each having an in-trench electrode to which an emitter potential is applied, a first semiconductor layer of a second conductivity type sandwiched between the third trenches, a second semiconductor layer of a second conductivity type sandwiched between the third trenches and provided in a layer lower than the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer, a third semiconductor layer of a first conductivity type provided in a layer lower than the second semiconductor layer, a fourth trench penetrating the first semiconductor layer and the second semiconductor layer and reaching the third semiconductor layer, and a first electrode electrically connected to the emitter electrode and provided in a layer upper than the first semiconductor layer and inside the fourth trench. The side surface of the fourth trench is in contact with the first semiconductor layer and the second semiconductor layer, and at least at the bottom surface of the fourth trench, the first electrode is in Schottky contact with the third semiconductor layer.

Advantages of the Invention

[0015] According to the present invention, in the diode region of an RC-IGBT, a semiconductor device with a small cell size, a low voltage in the conduction state when a low voltage is applied, a short recovery time after large-current conduction, and a high breakdown voltage can be realized.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Best Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

Embodiment

[0018] FIG. 1 is a cross-sectional view of the semiconductor device of Embodiment 1.

[0019] The semiconductor device 1 of this embodiment is an RC-IGBT having an IGBT region 2 and a diode region 3 in the same chip. As the semiconductor, for example, silicon can be used.

[0020] In this embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type. When the first conductivity type is p-type and the second conductivity type is n-type, holes and electrons of carriers are interchanged, and the anode and the cathode are interchanged. Also, regarding the impurity concentration, although an example is shown in the embodiment, the present invention is not limited to this, and it may be appropriately changed within the range where the intended operation in the embodiment can be realized.

[0021] The IGBT 20 in the IGBT region 2 includes a plurality of first trenches 11 in which a gate electrode 43 is provided inside, an emitter layer 21 of the first conductivity type sandwiched between the first trenches 11, a body layer 22 of the second conductivity type sandwiched between the first trenches 11 and provided in a lower layer than the emitter layer 21, a second trench 12 penetrating the emitter layer 21 and provided up to the middle of the body layer 22, and an emitter electrode 41 electrically connected to the emitter layer 21 and the body layer 22 via the second trench 12.

[0022] The impurity concentration of each semiconductor layer is, for example, the emitter layer 21 is high-concentration n+, and the body layer 22 is medium-concentration p. The gate electrode 43 is formed of, for example, polysilicon. The emitter electrode 41 is formed of, for example, metal.

[0023] The IGBT 20 also has, among other things, a contact layer 25 of the second conductivity type provided between the second trench 12 and the body layer 22. The impurity concentration of the contact layer 25 is, for example, a high concentration of p+. The contact layer 25 is provided to reduce the contact resistance between the emitter electrode 41 and the body layer 22.

[0024] The IGBT 20 also has, among other things, a gate insulating film 61 and an interlayer insulating film 63. The gate insulating film 61 is provided inside the first trench 11 and is provided between the gate electrode 43 and other semiconductor layers. The interlayer insulating film 63 is provided, for example, between the emitter electrode 41 and the gate electrode 43 and between the emitter electrode 41 and the emitter layer 21.

[0025] The IGBT 20 also has, among other things, a drift layer 23 of the first conductivity type provided below the body layer 22, a collector layer 24 of the second conductivity type provided below the drift layer 23, and a collector electrode 42 electrically connected to the collector layer 24. The impurity concentration of each semiconductor layer is such that the drift layer 23 is, for example, a low concentration of n−, and the collector layer 24 is, for example, a medium concentration of p. The collector electrode 42 is formed of, for example, metal.

[0026] The IGBT 20 also desirably has, among other things, a buffer layer 26 provided between the drift layer 23 and the collector layer 24 and having an impurity concentration higher than that of the drift layer 23. The impurity concentration of the buffer layer 26 is, for example, a medium concentration of n.

[0027] The diode 30 in the diode region 3 has a plurality of third trenches 13 having an in-trench electrode 53 to which an emitter potential is applied inside, a first semiconductor layer 31 of a second conductivity type sandwiched between the third trenches 13, a second semiconductor layer 32 of a second conductivity type which is sandwiched between the third trenches 13 and provided in a layer lower than the first semiconductor layer 31 and has a lower impurity concentration than the first semiconductor layer 31, a third semiconductor layer 33 of a first conductivity type provided in a layer lower than the second semiconductor layer 32, a fourth trench 14 which penetrates the first semiconductor layer 31 and the second semiconductor layer 32 and reaches the third semiconductor layer 33, and a first electrode 51 which is electrically connected to the emitter electrode 41 and provided in a layer upper than the first semiconductor layer 31 and inside the fourth trench 14.

[0028] The impurity concentration of each semiconductor layer is such that the first semiconductor layer 31 is, for example, high-concentration p+, the second semiconductor layer 32 is, for example, medium-concentration p, and the third semiconductor layer 33 is, for example, low-concentration n-. The second semiconductor layer 32 is desirably formed simultaneously with the body layer 22 in order to share the manufacturing process, and it is desirable that the impurity concentration of the second semiconductor layer 32 is substantially the same as the impurity concentration of the body layer 22. The third semiconductor layer 33 can be formed simultaneously with the drift layer 23, and it is desirable that the impurity concentration of the third semiconductor layer 33 is substantially the same as the impurity concentration of the drift layer 23. The in-trench electrode 53 can be formed simultaneously with the gate electrode 43 using the same material, and is formed of, for example, polysilicon. The first electrode 51 is formed integrally with the emitter electrode 41 and is formed of, for example, metal.

[0029] The diode 30 further has an in-trench insulating film 62 and an interlayer insulating film 63. The in-trench insulating film 62 is provided inside the third trench 13 and is provided between the in-trench electrode 53 and other semiconductor layers. The interlayer insulating film 63 is provided, for example, between the first electrode 51 and the in-trench electrode 53 and between the first electrode 51 and the first semiconductor layer 31.

[0030] The diode 30 also has, among other things, a fourth semiconductor layer 34 of the first conductivity type provided below the third semiconductor layer 33 and having a higher impurity concentration than the third semiconductor layer 33, and a second electrode 52 electrically connected to the fourth semiconductor layer 34 and the collector electrode 42. The impurity concentration of the fourth semiconductor layer 34 is, for example, a high concentration of n+. The second electrode 52 is integrally formed with the collector electrode 42 and is made of, for example, metal.

[0031] The diode 30 preferably also has a buffer layer 26 provided between the third semiconductor layer 33 and the fourth semiconductor layer 34 and having a higher impurity concentration than the third semiconductor layer 33.

[0032] In the diode 30 of this embodiment, the side surface of the fourth trench 14 is in contact with the first semiconductor layer 31 and the second semiconductor layer 32. Since there is no gap between the first semiconductor layer 31 and the fourth trench 14, the cell size can be reduced.

[0033] Also, at least at the bottom surface of the fourth trench 14, the first electrode 51 forms a Schottky junction with the third semiconductor layer 33. Thereby, a Schottky barrier diode is formed between the bottom surface of the first electrode 51 and the third semiconductor layer 33. Further, it is desirable that the first electrode 51 also forms a Schottky junction with the third semiconductor layer 33 at a part of the side surface of the fourth trench 14 (the side surface near the bottom). Thereby, the area where the Schottky barrier diode is formed can be increased.

[0034] Furthermore, a pn diode is formed between the second semiconductor layer 32 and the third semiconductor layer 33. Note that the first electrode 51 functions as an anode electrode, the second electrode 52 functions as a cathode electrode, the first semiconductor layer 31 and the second semiconductor layer 32, which are semiconductor layers of the second conductivity type, function as anode layers, and the third semiconductor layer 33, the buffer layer 26, and the fourth semiconductor layer 34, which are semiconductor layers of the first conductivity type, function as cathode layers.

[0035] Next, the operation of the diode 30 of this embodiment will be described.

[0036] In the low current conduction state, since the Schottky barrier diode operates preferentially over the pn diode, the current when a low voltage is applied can be increased compared to the pn diode. In the Schottky barrier diode, the built-in voltage at the rising edge generated in the pn diode does not occur, so the voltage in the low current conduction state when a low voltage is applied can be reduced.

[0037] In the high current conduction state, the pn diode operates preferentially over the Schottky barrier diode. At this time, since the width of the first semiconductor layer 31 which is a high concentration p+ is reduced by the fourth trench 14, the amount of hole injection from the anode side can be suppressed. As a result, the recovery time during subsequent reverse recovery can be shortened.

[0038] Furthermore, since the second semiconductor layer 32 having an impurity concentration lower than that of the first semiconductor layer 31 exists around the fourth trench 14, the concentration of the electric field at the corner of the fourth trench 14 can be relaxed when the breakdown voltage is maintained (when a reverse bias is applied and the diode 30 is off), and a high breakdown voltage can be achieved.

[0039] Note that since the first semiconductor layer 31 is a high concentration p+, it is difficult for a depletion layer to spread in the first semiconductor layer 31. Since the electric field = voltage / depletion layer width, if the depletion layer does not spread, the electric field becomes strong and the breakdown voltage cannot be obtained. Therefore, it is important to have the second semiconductor layer 32 having an impurity concentration lower than that of the first semiconductor layer 31 in order to ensure the breakdown voltage. However, if the impurity concentration is too low, conversely, the breakdown voltage cannot be obtained, so it is desirable that the impurity concentration of the second semiconductor layer 32 be substantially the same as that of the body layer 22.

[0040] Furthermore, it is desirable that the depth of the fourth trench 14 is deeper than the depth of the second trench 12 and shallower than the depth of the third trench 13. Since the depth of the fourth trench 14 is shallower than the depth of the third trench 13, the electric field at the corner of the fourth trench 14 can be relaxed by the depletion layer spreading from the third trench 13. Furthermore, the side surface of the fourth trench 14 is not separated from the first semiconductor layer 31, the cell size is small, and the distance between the third trench 13 and the fourth trench 14 is close, so that the electric field at the corner of the fourth trench 14 can be easily relaxed by the depletion layer spreading from the third trench 13. Furthermore, since the depth of the fourth trench 14 is deeper than the depth of the second trench 12, a Schottky barrier diode can be formed between the bottom surface of the first electrode 51 and the third semiconductor layer 33. The second trench 12 and the fourth trench 14 are formed in separate processes. Note that the first trench 11 and the third trench 13 can be formed simultaneously. Therefore, it is desirable that the first trench 11 and the third trench 13 have the same depth.

[0041] According to this embodiment, in the diode region 3 of the RC-IGBT, a semiconductor device 1 with a small cell size, a low voltage in the conduction state when a low voltage is applied, a short recovery time after large current conduction, and a high breakdown voltage can be realized.

Embodiment

[0042] FIG. 2 is a cross-sectional view of the semiconductor device of Embodiment 2.

[0043] Embodiment 2 is a modification of Embodiment 1, in which a barrier layer 27 is added, and the configurations of the third semiconductor layer 33, the fourth semiconductor layer 34, and the fifth semiconductor layer 35 are different from those of Embodiment 1.

[0044] The IGBT 20 of this embodiment further has a barrier layer 27 of the first conductivity type provided between the drift layer 23 and the body layer 22 and having a higher impurity concentration than the drift layer 23. The impurity concentration of the barrier layer 27 is, for example, medium concentration n.

[0045] When the IGBT20 is on, holes flow from the p-type collector layer 24 on the back side. However, since the n-type barrier layer 27 acts as a barrier, holes accumulate around the barrier layer 27. Then, electrons enter from the front side by the amount of the accumulated holes. Compared with the case where there is no barrier layer 27, the carriers around the barrier layer 27 increase, and the higher the carrier concentration, the lower the resistance. Therefore, the on-voltage of the IGBT20 can be lowered.

[0046] The diode 30 of this embodiment includes an n-type fourth semiconductor layer 34 provided below the third semiconductor layer 33 and having an impurity concentration lower than that of the third semiconductor layer 33, an n-type fifth semiconductor layer 35 provided below the fourth semiconductor layer 34 and having an impurity concentration higher than that of the fourth semiconductor layer 34, and a second electrode 52 electrically connected to the fifth semiconductor layer and the collector electrode 42. The impurity concentration of the third semiconductor layer 33 is substantially the same as the impurity concentration of the barrier layer 27, and the impurity concentration of the fourth semiconductor layer 34 is substantially the same as the impurity concentration of the drift layer 23.

[0047] That is, the third semiconductor layer 33 that forms a Schottky junction with the first electrode 51 corresponds to the drift layer 23 of the IGBT20 in the first embodiment, but corresponds to the barrier layer 27 of the IGBT20 in the second embodiment. Also, the fourth semiconductor layer 34 of the second embodiment corresponds to the third semiconductor layer 33 of the first embodiment, and the fifth semiconductor layer 35 of the second embodiment corresponds to the fourth semiconductor layer 34 of the first embodiment.

[0048] The impurity concentration of each semiconductor layer is, for example, medium-concentration n for the third semiconductor layer 33, low-concentration n- for the fourth semiconductor layer 34, and high-concentration n+ for the fifth semiconductor layer 35. The third semiconductor layer 33 can be formed simultaneously with the barrier layer 27.

[0049] In the high-current conduction state of the diode 30, holes are injected from the first semiconductor layer 31 and the second semiconductor layer 32 of the second conductivity type on the surface side, but are blocked by the third semiconductor layer 33 of the first conductivity type. Electrons enter from the back side and conductivity modulation occurs. However, since holes are blocked by the third semiconductor layer 33, conductivity fluctuations are less likely to occur. As a result, the carriers are in low injection, and it becomes difficult for current to flow. Also, as a result of the carriers being in low injection, the recovery time during subsequent reverse recovery can be shortened.

[0050] Since the others are the same as those in the first embodiment, the description thereof is omitted.

[0051] As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Also, a part or all of the configurations described in each embodiment may be combined and applied.

Description of Reference Numerals

[0052] 1: Semiconductor device 2: IGBT region 3: Diode region 11: First trench 12: Second trench 13: Third trench 14: Fourth trench 20: IGBT 21: Emitter layer 22: Body layer 23: Drift layer 24: Collector layer 25: Contact layer 26: Buffer layer 27: Barrier layer 30: Diode 31: First semiconductor layer 32: Second semiconductor layer 33: Third semiconductor layer 34: Fourth semiconductor layer 35: Fifth semiconductor layer 41: Emitter electrode 42: Collector electrode 43: Gate electrode 51: First electrode (anode electrode) 52: Second electrode (cathode electrode) 53: Electrode in trench 61: Gate insulating film 62: Insulating film in trench 63: Interlayer insulating film

Claims

1. A semiconductor device having an IGBT region and a diode region within the same chip, wherein the IGBT in the IGBT region has a plurality of first trenches each having a gate electrode provided therein, an emitter layer of a first conductivity type sandwiched between the first trenches, a body layer of a second conductivity type sandwiched between the first trenches and provided in a layer lower than the emitter layer, a second trench penetrating the emitter layer and provided up to the middle of the body layer, and an emitter electrode electrically connected to the emitter layer and the body layer via the second trench, wherein the diode in the diode region has a plurality of third trenches each having an in-trench electrode to which an emitter potential is applied, a first semiconductor layer of a second conductivity type sandwiched between the third trenches, a second semiconductor layer of a second conductivity type sandwiched between the third trenches, provided in a layer lower than the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer, a third semiconductor layer of a first conductivity type provided in a layer lower than the second semiconductor layer, a fourth trench penetrating the first semiconductor layer and the second semiconductor layer and reaching the third semiconductor layer, and a first electrode electrically connected to the emitter electrode and provided in a layer higher than the first semiconductor layer and inside the fourth trench, wherein a side surface of the fourth trench is in contact with the first semiconductor layer and the second semiconductor layer, and wherein the first electrode forms a Schottky junction with the third semiconductor layer at least at a bottom surface of the fourth trench. A semiconductor device characterized by this.

2. In claim 1, wherein the first electrode forms a Schottky junction with the third semiconductor layer at a part of a side surface of the fourth trench. A semiconductor device characterized by this.

3. In claim 1, wherein an impurity concentration of the second semiconductor layer of the diode is substantially the same as an impurity concentration of the body layer of the IGBT. A semiconductor device characterized by this.

4. In claim 1, wherein a depth of the fourth trench is deeper than a depth of the second trench and shallower than a depth of the third trench. A semiconductor device characterized by this.

5. In claim 1, wherein the IGBT has a drift layer of a first conductivity type provided in a layer lower than the body layer, a collector layer of a second conductivity type provided in a layer lower than the drift layer, and a collector electrode electrically connected to the collector layer. The diode has a fourth semiconductor layer of a first conductivity type provided below the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer, and a second electrode electrically connected to the fourth semiconductor layer and the collector electrode. A semiconductor device, wherein an impurity concentration of the third semiconductor layer of the diode is substantially the same as an impurity concentration of a drift layer of the IGBT.

6. In claim 1, the IGBT has a drift layer of a first conductivity type provided below the body layer, a collector layer of a second conductivity type provided below the drift layer, a collector electrode electrically connected to the collector layer, and a first conductivity type barrier layer provided between the drift layer and the body layer and having a higher impurity concentration than the drift layer. The diode has a fourth semiconductor layer of a first conductivity type provided below the third semiconductor layer and having a lower impurity concentration than the third semiconductor layer, a fifth semiconductor layer of a first conductivity type provided below the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer, and a second electrode electrically connected to the fifth semiconductor layer and the collector electrode. An impurity concentration of the third semiconductor layer of the diode is substantially the same as an impurity concentration of the barrier layer of the IGBT. A semiconductor device, wherein an impurity concentration of the fourth semiconductor layer of the diode is substantially the same as an impurity concentration of a drift layer of the IGBT.

7. In claim 1, a semiconductor device, wherein the first conductivity type is an n-type, the second conductivity type is a p-type, and the first electrode is an anode electrode.

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