Semiconductor element, semiconductor device, and manufacturing method for semiconductor element

Abstract

To provide a semiconductor element whose reliability can be improved.SOLUTION: A semiconductor element 30 includes an electrode 40 provided on an element surface 301, an insulating layer 50 covering the electrode 40 and including an opening part 51 for exposing a part of the electrode 40, and an electrode terminal 60 that is in contact with an exposed part 40A of the electrode 40 exposed by the opening part 51 and that overlaps partially with the insulating layer 50. The electrode terminal 60 includes a base layer 61, a conductive layer 65, and a wall part 66. The base layer 61 is provided linking between the exposed part 40A and a peripheral edge part 52 of the opening part 51 in the insulating layer 50, and is in contact with both the exposed part 40A and the peripheral edge part 52. The conductive layer 65 is bonded to a first region 621 on an upper surface 611 of the base layer 61. The wall part 66 is bonded to a second region 622 on the upper surface 611 of the base layer 61. The second region 622 is disposed outside the first region 621. The wall part 66 rises from the second region 622.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor device, and a method for manufacturing a semiconductor element.

Background Art

[0002] Patent Document 1 discloses a semiconductor package including a conductive member, a semiconductor device flip-chip bonded to the conductive member using Cu columnar bodies on a Cu conductive layer, and a sealing resin covering a part of the conductive member and the semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] By the way, in semiconductor elements, improvement in reliability is desired.

[0005] A semiconductor element according to one aspect of the present disclosure includes an electrode provided on an element surface facing the thickness direction, an insulating layer covering the electrode and including an opening exposing a part of the electrode, and an electrode terminal in contact with an exposed portion of the electrode exposed by the opening and partially overlapping the insulating layer when viewed from the thickness direction. The electrode terminal is provided across both the exposed portion and a peripheral portion of the opening in the insulating layer, is in contact with both the exposed portion and the peripheral portion, and includes a base layer having an upper surface including a first region and a second region, a conductive layer joined to the first region of the upper surface of the base layer, and a wall portion joined to the second region of the upper surface of the base layer. The second region is disposed outward with respect to the first region, and the wall portion stands up from the second region.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, for ease of understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure. Terms such as "first", "second", "third", etc. in the present disclosure are merely used to distinguish objects and do not rank the objects.

[0008] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] (Embodiment) With reference to FIGS. 1 to 7, the semiconductor device 10 of the embodiment will be described. FIG. 1 is a schematic perspective view showing an example of the semiconductor device 10. FIG. 2 is a schematic plan view seen from the back surface of the semiconductor device 10 of FIG. 1. FIG. 3 is a schematic plan view showing the internal structure of the semiconductor device 10 of FIG. 1. FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 cut along the line F4 - F4 of FIG. 3. FIG. 5 is a schematic cross-sectional view showing an enlarged view of the electrode terminal in the F5 region of FIG. 4 and members around it. FIG. 6 is a schematic cross-sectional view of the electrode terminal 60 and members around it cut along the line F6 - F6 of FIG. 5. FIG. 7 is a schematic cross-sectional view showing the configuration of the electrode terminal 60 of the semiconductor element 30 shown in FIG. 5. The term "plan view" used in the present disclosure means viewing the semiconductor device 10 in the Z direction of the XYZ axes orthogonal to each other shown in FIG. 1.

[0010] In FIG. 3, in order to show the states of the semiconductor element 30 and the connection terminals 20, the encapsulation resin 70 is indicated by a two-dot chain line. FIGS. 4 and 5 show the state in which the element surface 301 of the semiconductor element 30 faces downward. FIG. 7 shows the state in which the element surface 301 of the semiconductor element 30 faces upward. Further, FIG. 7 shows the state of the bonding layer 68 before being bonded to the connection terminals 20.

[0011] (Schematic Configuration of Semiconductor Device) As shown in FIG. 1, the semiconductor device 10 has a rectangular flat plate shape with the Z direction as the thickness direction. The semiconductor device 10 includes a device surface 11 facing the Z direction and a device back surface 12 on the side opposite to the device surface 11. The semiconductor device 10 includes four device side surfaces 13 to 16 that connect the device surface 11 and the device back surface 12 in the Z direction. The device side surfaces 13 and 14 constitute both end faces of the semiconductor device 10 in the X direction, and the device side surfaces 15 and 16 constitute both end faces of the semiconductor device 10 in the Y direction. In the example shown in FIG. 1, the semiconductor device 10 has a square shape in plan view. The semiconductor device 10 is a surface mount type package in which the device back surface 12 becomes the mounting surface when mounted on, for example, a circuit board (not shown). In the example shown in FIG. 1, the package type of the semiconductor device 10 is a QFN (Quad Flat Non-leaded Package) type. Note that the shape of the semiconductor device 10 in plan view is not limited to a square shape and can be arbitrarily changed. The dimensions of the semiconductor device 10 in the X direction, Y direction, and Z direction can be arbitrarily changed. Also, the package type of the semiconductor device 10 is not limited to QFN and can be arbitrarily changed.

[0012] As shown in FIGS. 1 to 4, the semiconductor device 10 includes connection terminals 20. The semiconductor device 10 may include a plurality of connection terminals 20. The connection terminal 20 includes a connection terminal surface 201, a connection terminal surface 201 facing the Z direction, and a connection terminal back surface 202 on the side opposite to the connection terminal surface 201. In one example, the connection terminal back surface 202 is exposed from the device back surface 12.

[0013] The connection terminal 20 may include a lead portion 21, a pad portion 22, and a finger portion 23. In one example, the semiconductor device 10 includes a plurality of lead portions 21. The number of lead portions 21 can be arbitrarily changed. In one example, the semiconductor device 10 includes one pad portion 22. The number of pad portions 22 can be arbitrarily changed. In one example, the semiconductor device 10 includes a plurality of finger portions 23. The number of finger portions 23 can be arbitrarily changed. The semiconductor device 10 may not include the pad portion 22. The semiconductor device 10 may not include the finger portion 23.

[0014] The plurality of lead portions 21 are arranged at the peripheral portion of the semiconductor device 10. The plurality of lead portions 21 are exposed from the device back surface 12. The plurality of lead portions 21 may be arranged along at least one of the device side surfaces 13 to 16. In one example, the plurality of lead portions 21 are arranged along each of the device side surfaces 13 to 16. The plurality of lead portions 21 may be exposed from the corresponding device side surfaces 13 to 16.

[0015] Each of the plurality of lead portions 21, in one example, has a strip shape extending in a direction orthogonal to the corresponding device side surfaces 13 to 16 in a plan view. The planar shape of the plurality of lead portions 21 can be arbitrarily changed. In one example, each of the plurality of lead portions 21 includes a protruding portion 211 that protrudes toward the center of the semiconductor device 10 on the connection terminal surface 201 side.

[0016] The pad portion 22 is arranged so as to be exposed from the device back surface 12 of the semiconductor device 10. In one example, the pad portion 22 is arranged at the center of the device back surface 12. In one example, the pad portion 22 has a rectangular flat plate shape in a plan view. In one example, the pad portion 22 has four sides parallel to the device side surfaces 13 to 16 in a plan view. In one example, the pad portion 22 includes a protruding portion 221 that protrudes toward the device side surfaces 13 to 16 at the peripheral edge portion on the connection terminal surface 201 side.

[0017] The plurality of finger portions 23 are each drawn out from the pad portion 22 toward the device side surfaces 13 to 16 of the semiconductor device 10 in a plan view. In one example, the plurality of finger portions 23 are each drawn out from the four corner portions of the rectangular pad portion 22 toward the four corner portions of the semiconductor device 10. The plurality of finger portions 23 may be exposed from the device side surfaces 13 to 16.

[0018] The connection terminal 20 is made of a conductive material. As the conductive material, for example, a material including one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), and W (tungsten) is used. The connection terminal 20 is formed, for example, by subjecting a plate material made of a conductive material to an etching process. Note that the formation method of the connection terminal 20 can be arbitrarily changed. In one example, the connection terminal 20 may be formed by subjecting a plate material to a punching process, a bending process, or the like.

[0019] The semiconductor device 10 includes a semiconductor element 30. The semiconductor element 30 is disposed inside the semiconductor device 10. The semiconductor element 30 is disposed at the center of the semiconductor device 10 in a plan view. The semiconductor element 30 is disposed inside the semiconductor device 10 so as to overlap the entire pad portion 22 and the inner ends of the plurality of lead portions 21 in a plan view.

[0020] The semiconductor element 30 has a rectangular flat plate shape with the Z direction as the thickness direction. The semiconductor element 30 includes an element front surface 301 facing the Z direction and an element back surface 302 on the side opposite to the element front surface 301. The semiconductor element 30 includes element side surfaces 303 to 306 that connect the element front surface 301 and the element back surface 302 in the Z direction. The element side surfaces 303 and 304 constitute both end faces of the semiconductor element 30 in the X direction, and the element side surfaces 305 and 306 constitute both end faces of the semiconductor element 30 in the Y direction.

[0021] The semiconductor element 30 includes a plurality of electrode terminals 60 on the element surface 301. The semiconductor element 30 is arranged with the plurality of electrode terminals 60 facing the connection terminal 20. It can be said that the semiconductor element 30 is arranged with the element surface 301 facing the connection terminal 20. The plurality of connection terminals 20 are mechanically and electrically connected to the connection terminal 20 by the bonding layer 68. It can be said that the semiconductor element 30 is flip-chip mounted on the connection terminal 20.

[0022] The semiconductor device 10 includes a sealing resin 70. The sealing resin 70 constitutes the external structure of the semiconductor device 10. More specifically, the sealing resin 70 has a rectangular flat plate shape with the Z direction as the thickness direction. The sealing resin 70 has a sealing surface 701, a sealing back surface 702 on the side opposite to the sealing surface 701 in the Z direction, and four sealing side surfaces 703 to 706 connecting the sealing surface 701 and the sealing back surface 702 in the Z direction. The sealing surface 701 constitutes the device surface 11, and the sealing back surface 702 constitutes the device back surface 12. The sealing side surface 703 constitutes the device side surface 13, the sealing side surface 704 constitutes the device side surface 14, the sealing side surface 705 constitutes the device side surface 15, and the sealing side surface 706 constitutes the device side surface 16.

[0023] As shown in FIG. 4, the sealing resin 70 covers the semiconductor element 30. The sealing resin 70 is made of an insulating material such as an epoxy resin, etc. The sealing resin 70 may be colored black or the like. The sealing resin 70 covers the entire semiconductor element 30 and a part of the connection terminal 20. It can be said that the sealing resin 70 seals the semiconductor element 30 and a part of the connection terminal 20. It can be said that the sealing resin 70 supports the connection terminal 20.

[0024] A conductive film 75 shown by a two-dot chain line in FIG. 4 may be provided on the surface of the connection terminal 20 exposed from the sealing resin 70. In one example, the conductive film 75 may be a plating film containing Sn (tin). Note that the conductive film 75 may include a plurality of plating films. In one example, the conductive film 75 may include a plurality of plating films laminated in the order of Ni (nickel), Pd (palladium), and Au.

[0025] (Schematic Configuration of Semiconductor Element) As shown in FIG. 4, the semiconductor element 30 includes a substrate 31. The substrate 31 is constituted by, for example, a semiconductor substrate. In one example, the substrate 31 is a semiconductor substrate made of a material containing Si (silicon). Note that the substrate 31 may be constituted by a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap exceeding that of Si. GaN (gallium nitride), SiC (silicon carbide), etc. are exemplified as wide bandgap semiconductors. In this form, the substrate 31 is made of a Si silicon chip. The substrate 31 may have a stacked structure including a semiconductor substrate and an epitaxial layer. The substrate 31 may be constituted by an epitaxial layer.

[0026] The substrate 31 has a rectangular flat plate shape with the Z direction as the thickness direction. The substrate 31 includes a substrate surface 311 and a substrate back surface 312 on the side opposite to the substrate surface 311. The substrate 31 is arranged with the substrate surface 311 facing the connection terminal surface 201 of the connection terminal 20. In one example, the substrate back surface 312 constitutes the element back surface 302.

[0027] The semiconductor element 30 includes one or a plurality of device regions 32 partitioned on the substrate surface 311 of the substrate 31. In FIG. 4, a plurality of device regions 32 are indicated by broken lines. The substrate surface 311 of the substrate 31 can be referred to as a device surface. In one example, a plurality of device regions 32 are partitioned on the substrate 31.

[0028] The number and arrangement of the device regions 32 may be arbitrarily changed. The device region 32 may include a functional device formed using regions inside and outside the substrate 31. The functional device may include at least one of, for example, a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0029] The semiconductor switching device may include at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0030] The semiconductor element 30 includes an insulating film 33 disposed on the substrate surface 311. The insulating film 33 is interposed between the connection terminal 20 and the substrate 31. In one example, the insulating film 33 covers the entire substrate surface 311 in plan view and is in contact with the substrate surface 311.

[0031] The insulating film 33 may include a plurality of interlayer insulating films 34 and a top insulating film 35. The number of layers of the plurality of interlayer insulating films 34 is arbitrary. In one example, the number of layers of the interlayer insulating film 34 may be 2 or more and 25 or less. Each of the plurality of interlayer insulating films 34 may have a single-layer structure or a laminated structure including at least one of a SiO2 (silicon oxide) film and a SiN (silicon nitride) film. In one example, each of the plurality of interlayer insulating films 34 has a single-layer structure made of a SiO2 film.

[0032] The top insulating film 35 constitutes the terminal insulating film of the insulating film 33 and covers the uppermost interlayer insulating film 34. The top insulating film 35 may be referred to as an "inorganic insulating film" or a "passivation film". The top insulating film 35 may have a single-layer structure including at least one of a SiO2 film and a SiN film.

[0033] The top insulating film 35 may be made of an insulating material that is at least different from the uppermost interlayer insulating film 34. In one example, the top insulating film 35 has a single-layer structure made of a SiN film. The top insulating film 35 has a flat surface extending along the substrate surface 311. In one example, the top insulating film 35 may have a thickness that is at least less than the thickness of the uppermost interlayer insulating film 34. The top insulating film 35 may be composed of a laminated structure of a SiO2 film and a SiN film. In one example, the surface of the top insulating film 35 opposite to the substrate 31 may constitute the element surface 301 of the semiconductor element 30.

[0034] The semiconductor element 30 may include a plurality of interlayer wirings 36 disposed in the insulating film 33. The plurality of interlayer wirings 36 are wiring films disposed on an arbitrary interlayer insulating film 34 below the top insulating film 35. The routing pattern of the plurality of interlayer wirings 36 is arbitrary. The semiconductor element 30 may include a plurality of via wirings 37 connected to the plurality of interlayer wirings 36. The plurality of via wirings 37 penetrate the interlayer insulating film 34. The plurality of interlayer wirings 36 and the plurality of via wirings 37 constitute a multilayer wiring structure 38 together with the plurality of interlayer insulating films 34. The plurality of interlayer wirings 36 are made of a material containing at least one of Al, Cu, Ti, and W.

[0035] The semiconductor element 30 includes a plurality of electrodes 40 disposed on the element surface 301. The element surface 301 is constituted by the surface of the insulating film 33, specifically, the top insulating film 35. Therefore, it can be said that the semiconductor element 30 includes a plurality of electrodes 40 disposed on the surface of the insulating film 33. The plurality of electrodes 40 each constitute a terminal wiring of the multilayer wiring structure 38. The routing pattern of the plurality of electrodes 40 is arbitrary. The plurality of electrodes 40 may be routed in a line shape in plan view, or may be formed in an island shape. Of course, the plurality of electrodes 40 may have a relatively wide island portion in plan view and a relatively narrow line portion drawn linearly from the island portion.

[0036] The plurality of electrodes 40 each have a thickness exceeding the thickness of the top insulating film 35. The plurality of electrodes 40 may each have a thickness exceeding the thickness of each interlayer wiring 36. The plurality of wiring layers have the same configuration except for the placement location and routing pattern.

[0037] The semiconductor element 30 includes an insulating layer 50 disposed on the element surface 301. The insulating layer 50 covers the surface 351 of the top insulating film 35 and a part of the electrode 40. The insulating layer 50 may be made of an insulating material such as an epoxy resin, a phenolic resin, a polyimide resin, or the like. The insulating layer 50 includes an opening 51 that exposes a part of the electrode 40. The opening 51 may have a circular shape in plan view in one example.

[0038] The semiconductor element 30 includes a plurality of electrode terminals 60. The plurality of electrode terminals 60 are provided corresponding to the plurality of electrodes 40. The electrode terminal 60 is in contact with the exposed portion of the electrode 40. Also, the electrode terminal 60 partially overlaps the insulating layer 50 in plan view. It can be said that the semiconductor element 30 includes the electrode terminal 60 that is in contact with the exposed portion of the electrode 40 and partially overlaps the insulating layer 50 in plan view. The electrode terminal 60 is electrically connected to the electrode 40. It can be said that the semiconductor element 30 includes the electrode terminal 60 that is electrically connected to the electrode 40.

[0039] The plurality of electrode terminals 60 protrude in the Z direction from the electrode upper surface 401 of the electrode 40. The plurality of electrode terminals 60 have a columnar shape. In one example, the electrode terminal 60 has a cylindrical shape. The plurality of electrode terminals 60 are interposed between the electrode 40 and the connection terminal 20.

[0040] The semiconductor element 30 includes a bonding layer 68 provided on the terminal surface 601 of the electrode terminal 60. The bonding layer 68 is interposed between the electrode terminal 60 and the connection terminal 20. The electrode terminal 60 is mechanically and electrically connected to the connection terminal 20 by the bonding layer 68.

[0041] (Details of the electrode terminal and its surroundings) Referring to FIGS. 5 to 7, the electrode terminal 60 and the surrounding configuration will be described in detail.

[0042] (Electrode) An example of the electrode 40 shown in FIGS. 5 and 7 will be described. Note that each of the shape, configuration, and material of the electrode 40 can be arbitrarily changed.

[0043] The electrode 40 includes an electrode upper surface 401 and an electrode lower surface 402 on the side opposite to the electrode upper surface 401. The electrode lower surface 402 is in contact with the surface 351 of the top insulating film 35. As shown in FIG. 6, the electrode 40 may have a rectangular shape in plan view in one example.

[0044] The electrode 40 includes a wiring barrier film 41 disposed on the surface 351 of the top insulating film 35. The wiring barrier film 41 selectively covers the top insulating film 35. The wiring barrier film 41 may be made of a material containing at least one of Ti, TiN, Ta (tantalum), W, Mo (molybdenum), and Cr (chromium). The wiring barrier film 41 may have a laminated structure or a single-layer structure including at least one of a Ti film and a TiN film. The wiring barrier film 41 has a single-layer structure made of a material containing Ti in one example.

[0045] The electrode 40 includes a wiring electrode 42 covering the wiring barrier film 41. The wiring electrode 42 constitutes the main body of the electrode 40. The wiring electrode 42 may cover the entire area of the wiring barrier film 41 in cross-sectional view and plan view. The wiring electrode 42 may be made of a material containing at least one of Al and Cu.

[0046] The wiring electrode 42 includes a wiring upper surface 421, a wiring lower surface 422 on the side opposite to the wiring upper surface 421, and a wiring side surface 423 connecting the wiring upper surface 421 and the wiring lower surface 422. The wiring lower surface 422 faces the surface of the top insulating film 35. The wiring electrode 42 has a wiring upper end corner portion 424 formed in a round shape in one example. The wiring upper end corner portion 424 slopes obliquely downward in an arc shape from the wiring upper surface 421 toward the wiring side surface 423 at the peripheral edge of the wiring upper surface 421.

[0047] The electrode 40 includes a cover electrode 43 that covers the wiring electrode 42. The cover electrode 43 has a film shape that covers the entire wiring electrode 42. The cover electrode 43 includes a cover upper surface 431 and a cover lower surface 432 on the side opposite to the cover upper surface 431. The cover lower surface 432 is in contact with the wiring upper surface 421 of the wiring electrode 42. The cover electrode 43 includes a round portion 434 that covers the wiring upper end corner portion 424 in a film shape so as to curve along the wiring upper end corner portion 424.

[0048] In this form, the cover electrode 43 may have a laminated structure in which a plurality of metal films are laminated. The cover electrode 43 may include a first metal film 441 and a second metal film 442 laminated in this order from the side of the wiring electrode 42. The first metal film 441 covers the entire wiring upper surface 421 in a film shape. The first metal film 441 forms the cover lower surface 432 of the cover electrode 43. In one example, the first metal film 441 is made of a material containing Ni. The second metal film 442 covers the entire area of the first metal film 441 in a film shape. The second metal film 442 forms the cover upper surface 431 of the cover electrode 43. In one example, the second metal film 442 is made of a material containing Pd.

[0049] The electrode 40 is electrically connected to the interlayer wiring 36 by the via wiring 37. The via wiring 37 is embedded in a via hole 375 formed in the insulating film 33. In FIGS. 5 and 7, the via hole 375 penetrates the top insulating film 35 and the interlayer insulating film 34. The via wiring 37 has a laminated structure including a barrier film 371 and a via body 372. The barrier film 371 covers the inner surface of the via hole 375 in a film shape. In one example, the barrier film 371 is made of a material containing Ti. The via body 372 is embedded in the via hole 375 with the barrier film 371 interposed therebetween. In one example, the via body 372 is made of a material containing W.

[0050] (Insulating layer) As shown in FIGS. 5 and 7, the insulating layer 50 covers the surface 351 of the top insulating film 35 and a part of the electrode 40.

[0051] The insulating layer 50 includes an opening 51 that exposes a part of the electrode 40. In one example, the opening 51 is formed in a circular shape in plan view. The electrode 40 includes an exposed portion 40A exposed by the opening 51 of the insulating layer 50 and a non-exposed portion 40B covered by the insulating layer 50.

[0052] The insulating layer 50 includes a peripheral edge portion 52 outside the opening 51. The peripheral edge portion 52 overlaps the electrode 40 in plan view. The peripheral edge portion 52 may be a portion that covers the electrode 40. The surface 53 of the peripheral edge portion 52 includes a first surface 531 and a second surface 532. The second surface 532 is a surface outside the first surface 531.

[0053] The peripheral edge portion 52 includes an opening end portion 541 that forms the opening 51 for exposing a part of the electrode 40. The opening end portion 541 is an annular region that surrounds the exposed portion 40A of the electrode 40 by the circular opening 51 in plan view.

[0054] The peripheral edge portion 52 includes a flat portion 542 that is outside the opening end portion 541 and has a flat surface. In one example, the second surface 532 includes the surface of the flat portion 542. The first surface 531 includes a surface that slopes obliquely downward in an arc shape from the second surface 532 toward the opening 51. The first surface 531 can be said to be the surface of the opening end portion 541. That is, the surface of the opening end portion 541 can be said to be a surface that slopes obliquely downward in an arc shape from the surface of the flat portion 542 toward the opening 51. It can be said that the surface 53 of the peripheral edge portion 52 includes the flat second surface 532 and the first surface 531 that is inside the second surface 532 and slopes toward the exposed portion of the electrode 40.

[0055] (Electrode terminal) As shown in FIGS. 5 to 7, the electrode terminal 60 is electrically connected to the electrode 40 exposed from the opening 51 of the insulating layer 50.

[0056] The electrode terminal 60 protrudes in the Z direction from the upper electrode surface 401 of the electrode 40. The electrode terminal 60 is formed in a columnar shape. In one example, the electrode terminal 60 has a cylindrical shape. The electrode terminal 60 includes a terminal back surface 602 facing the electrode 40 and a terminal front surface 601 on the side opposite to the terminal back surface 602. The electrode terminal 60 includes a terminal side surface 603 connecting the terminal back surface 602 and the terminal front surface 601.

[0057] The electrode terminal 60 includes a base layer 61. The base layer 61 is provided so as to straddle both the exposed portion 40A of the electrode 40 and the peripheral portion 52 of the opening 51 in the insulating layer 50. The base layer 61 is in contact with both the exposed portion 40A of the electrode 40 and the peripheral portion 52 of the insulating layer 50. The base layer 61 includes an upper surface 611 and a lower surface 612 on the side opposite to the upper surface 611. The lower surface 612 of the base layer 61 is in contact with both the exposed portion 40A of the electrode 40 and the surface 53 of the peripheral portion 52 of the insulating layer 50.

[0058] The upper surface 611 of the base layer 61 includes a first region 621 and a second region 622. It can be said that the base layer 61 has an upper surface 611 including the first region 621 and the second region 622. The first region 621 overlaps with the exposed portion 40A of the electrode 40 in plan view. Also, the first region 621 overlaps with a part of the peripheral portion 52 of the opening 51 in the insulating layer 50. In one example, the first region 621 overlaps with the first surface 531 of the insulating layer 50. The first region 621 overlaps with the exposed portion 40A of the electrode 40 and the first surface 531 of the insulating layer 50 in plan view. The second region 622 is disposed outward with respect to the first region 621. The second region 622 is an annular region surrounding the first region 621. The second region 622 overlaps with the flat portion 542 of the insulating layer 50 in plan view. That is, the second region 622 overlaps with the second surface 532 of the insulating layer 50 in plan view. It can be said that the second region 622 is a flat surface. In plan view, the area of the first region 621 is larger than the area of the second region 622.

[0059] The base layer 61 may have a laminated structure or a single-layer structure. In one example, the base layer 61 has a laminated structure including a barrier layer 63 and a seed layer 64. The layer configuration of the base layer 61 can be arbitrarily changed.

[0060] The barrier layer 63 is in contact with both the exposed portion 40A of the electrode 40 and the surface 53 of the peripheral portion 52 of the insulating layer 50. In one example, the barrier layer 63 constitutes the lower surface 612 of the base layer 61. The barrier layer 63 may be formed of a material containing at least one of Ti, TiN, Ta, W, Mo, Cr, and Ru (ruthenium). In one example, the barrier layer 63 is formed of a material containing Ti. The barrier layer 63 may have a single-layer structure or a laminated structure. In one example, the film thickness of the barrier layer 63 may be 0.15 μm.

[0061] The seed layer 64 covers the barrier layer 63. The seed layer 64 covers the entire barrier layer 63. In one example, the seed layer 64 constitutes the upper surface 611 of the base layer 61. The seed layer 64 is formed of a material containing Cu. The seed layer 64 may have a single-layer structure or a laminated structure. In one example, the film thickness of the seed layer 64 may be 0.25 μm.

[0062] In one example, the barrier layer 63 and the seed layer 64 are sputtered layers. The barrier layer 63 and the seed layer 64 are formed by sputtering. That is, in one example, the base layer 61 is a sputtered layer. The base layer 61 is formed by sputtering. In one example, in plan view, the size of the barrier layer 63 and the size of the seed layer 64 are equal. For this reason, the side surfaces of the barrier layer 63 and the seed layer 64 are flush. In plan view, the barrier layer 63 may be larger than the seed layer 64. In plan view, the barrier layer 63 may be smaller than the seed layer 64.

[0063] The electrode terminal 60 includes a conductive layer 65 and a wall portion 66 joined to the upper surface of the base layer 61. The conductive layer 65 is joined to the first region 621 of the upper surface 611 of the base layer 61. The wall portion 66 is joined to the second region 622 of the upper surface 611 of the base layer 61. It can be said that the electrode terminal 60 includes the conductive layer 65 joined to the first region 621 of the upper surface 611 of the base layer 61 and the wall portion 66 joined to the second region 622 of the upper surface 611 of the base layer 61. The second region 622 is disposed outside the first region 621. The wall portion 66 stands up from the second region 622.

[0064] The bonding strength between the wall portion 66 and the base layer 61 is higher than the bonding strength between the conductive layer 65 and the base layer 61. The conductive layer 65 is joined to the first region 621 of the upper surface 611 of the base layer 61, and the wall portion 66 is joined to the second region 622 of the upper surface 611 of the base layer 61. Therefore, it can be said that the bonding strength between the wall portion 66 and the second region 622 is higher than the bonding strength between the conductive layer 65 and the first region 621.

[0065] The conductive layer 65 and the wall portion 66 are made of different materials. In one example, the conductive layer 65 is made of a material containing Cu, and the wall portion 66 is made of a material containing Ti. The conductive layer 65 and the wall portion 66 may be formed by different methods. In one example, the conductive layer 65 is a plating layer. The conductive layer 65 is formed using a plating method. In one example, the wall portion 66 is a sputter layer. The wall portion 66 is formed using sputtering.

[0066] As shown in FIG. 6, the wall portion 66 has an annular shape in plan view. The wall portion 66 includes an inner wall surface 661 and an outer wall surface 662 opposite to the inner wall surface 661. The inner wall surface 661 is a surface facing the inside of the annular wall portion 66. The outer wall surface 662 is a surface facing the outside of the annular wall portion 66. As shown in FIGS. 5 and 7, the wall portion 66 includes a lower end portion 663 on the side of the base layer 61 and an upper end portion 664 opposite to the lower end portion 663 in the Z direction. The inner wall surface 661 includes a curved surface 665 provided at the upper end portion 664. The curved surface 665 is inclined in an arc shape toward the outer wall surface 662 on the inner wall surface 661.

[0067] The conductive layer 65 stands up from the first region 621. The conductive layer 65 includes a terminal base portion 651 surrounded by the wall portion 66 and a terminal upper portion 652 disposed on the side opposite to the base layer 61 with respect to the terminal base portion 651 and protruding above the wall portion 66. The terminal upper portion 652 extends outward from the terminal base portion 651 in a plan view. Therefore, the terminal upper portion 652 is also provided on the wall portion 66. The terminal base portion 651 of the conductive layer 65 is in contact with the inner wall surface 661 of the wall portion 66. In other words, the inner wall surface 661 of the wall portion 66 is in contact with the conductive layer 65.

[0068] The terminal upper portion 652 of the conductive layer 65 includes an outer wall surface 653 facing outward of the conductive layer 65. The outer wall surface 653 of the terminal upper portion 652 and the outer wall surface 662 of the wall portion 66 constitute the terminal side surface 603 of the electrode terminal 60. It can be said that the terminal side surface 603 of the electrode terminal 60 includes the outer wall surface 662 of the conductive layer 65 and the outer wall surface 662 of the wall portion 66. In one example, the outer wall surface 662 of the conductive layer 65 and the outer wall surface 662 of the wall portion 66 are flush. The outer wall surface 653 of the conductive layer 65 may be located outside the outer wall surface 662 of the wall portion 66. The outer wall surface 653 of the conductive layer 65 may be located inside the outer wall surface 662 of the wall portion 66. That is, the terminal side surface 603 may have a stepped portion.

[0069] As shown in FIG. 6, the diameter D1 of the electrode terminal 60 as the size of the electrode terminal 60 may be shown as the distance between the outer wall surfaces 662 in a pair of portions of the wall portion 66 sandwiching the opening 51. The diameter D1 of the electrode terminal 60 is 20 μm or more and 100 μm or less.

[0070] As shown in FIG. 7, the height T1 of the wall portion 66 in the Z direction may be indicated by the length of the outer wall surface 662 of the wall portion 66 in the Z direction in one example. In the conductive layer 65, the height T2 of the upper terminal 652 may be indicated by the length of the outer wall surface 662 of the upper terminal 652 in the Z direction. The height T1 of the wall portion 66 may be 30% or more and 70% or less of the height obtained by adding the height T1 of the wall portion 66 and the height T2 of the upper terminal 652. The height T2 of the upper terminal 652 may be higher than the height T1 of the wall portion 66 in one example. It can be said that the height T2 of the upper terminal 652 is higher than the height T1 of the wall portion 66. The height T1 of the wall portion 66 may be lower than the height T2 of the upper terminal 652. It can be said that the height T1 of the wall portion 66 is lower than the height T2 of the upper terminal 652. The height T1 of the wall portion 66 may be equal to the height T2 of the upper terminal 652. The thickness W1 of the wall portion 66 may be indicated by the length between the inner wall surface 661 and the outer wall surface 662 at the lower end portion 663 in one example. The thickness W1 of the wall portion 66 may be 1.8 μm or more and 2.2 μm or less.

[0071] (Bonding layer) The semiconductor element 30 may include a bonding layer 68 provided on the terminal surface 601. The bonding layer 68 may be used for external connection. The bonding layer 68 is used, in one example, for mounting the semiconductor element 30 on the connection terminal 20.

[0072] The bonding layer 68 may include a first layer 681 and a second layer 682. The first layer 681 is provided on the terminal surface 601 of the electrode terminal 60. The first layer 681 of the bonding layer 68 covers the terminal surface 601 of the electrode terminal 60. The first layer 681 of the bonding layer 68 is in contact with the terminal surface 601 of the electrode terminal 60. The first layer 681 of the bonding layer 68 may be composed of a material containing Ni and Fe in one example. The first layer 681 may be a barrier layer.

[0073] The second layer 682 is provided on the first layer 681. The second layer 682 is in contact with the first layer 681. It can be said that the bonding layer 68 has a laminated structure including the first layer 681 and the second layer 682 formed on the first layer 681. The second layer 682 may be composed of a solder containing Sn. In one example, the second layer 682 may contain SnAg. As shown in FIG. 7, in the state before the electrode terminal 60 is bonded to the connection terminal 20, the second layer 682 has an arcuate surface.

[0074] The first layer 681 of the bonding layer 68 is interposed between the second layer 682 of the bonding layer 68 and the conductive layer 65 of the electrode terminal 60. The second layer 682 may be composed of a solder. The first layer 681 of the bonding layer 68 may be formed of a metal material that suppresses the chemical reaction between the second layer 682 of the bonding layer 68 and the conductive layer 65 of the electrode terminal 60. In one example, for the conductive layer 65 containing Cu and the second layer 682 containing Sn, the first layer 681 may be formed of a material containing Ni.

[0075] (Method for manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 10 will be described. In FIGS. 8 to 18, for the semiconductor element 30, an example of a method for manufacturing the electrode terminal 60 will be mainly described. In FIGS. 19 and 20, an example of a method for manufacturing the semiconductor device 10 including the semiconductor element 30 will be described.

[0076] FIGS. 8 to 18 are cross-sectional views showing an example of the manufacturing process of the semiconductor element 30 shown in FIGS. 5 to 7. In FIGS. 8 to 18, an example of a method for manufacturing the portion related to the electrode terminal 60 will be mainly described. FIGS. 8 to 18 are cross-sectional views corresponding to the cut surfaces of FIGS. 5 and 7. FIG. 19 is a cross-sectional view showing the bonding of the semiconductor element 30 to the connection terminal 20. FIG. 20 is a cross-sectional view showing the formation of the sealing resin 70. For ease of understanding, in FIGS. 8 to 20, the same reference numerals are assigned to the components similar to those in FIG. 5.

[0077] As shown in FIG. 8, a wafer 801 including a multilayer wiring structure 38 is prepared. The outermost surface of the multilayer wiring structure 38 is formed by a top insulating film 35 on which a plurality of via wirings 37 are exposed.

[0078] As shown in FIG. 8, a method for manufacturing the semiconductor element 30 includes forming an electrode 40. The electrode 40 is formed on the top insulating film 35. In one example, the electrode 40 includes a wiring barrier film 41, a wiring electrode 42, and a cover electrode 43. The cover electrode 43 includes a first metal film 441 and a second metal film 442.

[0079] First, a wiring barrier film 41 and a seed layer are formed on the upper surface of the top insulating film 35. The wiring barrier film 41 and the seed layer may be respectively formed using sputtering in one example. A mask is formed on the seed layer. The mask includes an opening in a region where the electrode 40 is to be formed. The mask is obtained by forming a photosensitive resist film and forming an opening in the resist film by photolithography. The resist film is obtained by attaching a sheet-like photosensitive resin or applying a liquid photosensitive resin. Next, a wiring electrode 42 and a cover electrode 43 (first metal film 441, second metal film 442) are formed in the opening of the mask. The wiring electrode 42 and the cover electrode 43 may be formed using a plating method (electrolytic plating method, electroless plating method) in one example. After removing the mask, the seed layer and the wiring barrier film 41 exposed from the wiring electrode 42 are removed. The removal of the seed layer and the wiring barrier film 41 may be performed using an etching method (for example, a wet etching method).

[0080] As shown in FIG. 9, a method for manufacturing the semiconductor element 30 includes forming an insulating layer 50. The insulating layer 50 includes an opening 51. A photosensitive resin that serves as the base of the insulating layer 50 is formed on the top insulating film 35. The photosensitive resin may be in a liquid or film form. The photosensitive resin is formed so as to cover the electrode 40. By performing photolithography and curing on the photosensitive resin, an insulating layer 50 including an opening 51 that exposes a part of the electrode 40 is formed. The electrode 40 includes an exposed portion 40A exposed by the opening 51 of the insulating layer 50.

[0081] As shown in FIG. 10, the method for manufacturing the semiconductor element 30 includes forming a base layer 61. In one example, the base layer 61 includes a barrier layer 63 and a seed layer 64. The base layer 61 is formed on the exposed portion 40A of the electrode 40 and the insulating layer 50. A barrier layer 63 is formed on the exposed portion 40A of the electrode 40 and the insulating layer 50. In one example, the barrier layer 63 is composed of a material containing Ti. In one example, the barrier layer 63 may be formed using sputtering. A seed layer 64 is formed on the barrier layer 63. In one example, the seed layer 64 is composed of a material containing Cu. In one example, the seed layer 64 may be formed using sputtering.

[0082] As shown in FIG. 11, the method for manufacturing the semiconductor element 30 includes forming a mask 802. The mask 802 is formed on the base layer 61. The mask 802 includes an opening 803 that exposes a region where the electrode terminal 60 is to be formed in the base layer 61.

[0083] In one example, the mask 802 is obtained by forming a photosensitive resist film on the base layer 61 and forming the opening 803 in the resist film by photolithography. The resist film is obtained by attaching a sheet-like photosensitive resin or applying a liquid photosensitive resin. The opening 803 of the mask 802 is formed so as to expose regions that are to become the first region 621 and the second region 622 in the base layer 61.

[0084] As shown in FIG. 12, the method for manufacturing the semiconductor element 30 includes forming a first metal layer 804. The first metal layer 804 is formed so as to cover the surface of the mask 802 and the surface of the base layer 61 exposed by the opening 803 of the mask 802. The first metal layer 804 is composed of a material containing Ti. The first metal layer 804 may be formed using sputtering.

[0085] As shown in FIG. 13, the method for manufacturing the semiconductor element 30 includes forming a wall portion 66. The wall portion 66 is formed by etching back the first metal layer 804 shown in FIG. 12. In one example, using an etching method, unnecessary portions of the first metal layer 804 are removed until the first region 621 of the base layer 61 is exposed. As the etching method for the first metal layer 804, anisotropic etching is used. By this etching, the portion of the first metal layer 804 above the second region 622 of the upper surface 611 of the base layer 61 is left as the wall portion 66, and the portion above the first region 621 of the base layer 61 is selectively removed.

[0086] As shown in FIG. 14, the method for manufacturing the semiconductor element 30 includes forming a conductive layer 65. In one example, the conductive layer 65 is formed by depositing a material constituting the conductive layer 65 on the surface of the base layer 61 exposed from the mask 802 and the wall portion 66 by a plating method (for example, an electrolytic plating method). The conductive layer 65 is formed so as to cover the wall portion 66.

[0087] As shown in FIG. 15, the method for manufacturing the semiconductor element 30 includes forming a bonding layer 68. The bonding layer 68 includes a first layer 681 and a second layer 682. The first layer 681 is formed on the conductive layer 65, and the second layer 682 is formed on the first layer 681. The first layer 681 and the second layer 682 of the bonding layer 68 are formed by depositing, in order, the material constituting the first layer 681 and the material constituting the second layer 682 into the opening 803 of the mask 802 by a plating method (for example, an electrolytic plating method).

[0088] As shown in FIG. 16, the method for manufacturing the semiconductor element 30 includes removing the mask 802 shown in FIG. 15. In one example, the mask 802 is removed using a stripping solution. As shown in FIG. 17, the method for manufacturing the semiconductor element 30 includes forming the base layer 61. The base layer 61 shown in FIG. 17 is formed by removing the portion of the base layer 61 shown in FIG. 16 that is exposed from the electrode terminal 60. The removal of the unnecessary portion of the base layer 61 is performed using an etching method (for example, wet etching).

[0089] As shown in FIG. 18, the method for manufacturing the semiconductor element 30 includes forming the second layer 682 of the bonding layer 68. In one example, the second layer 682 of the bonding layer 68 is formed into a hemispherical shape by a reflow process. The reflow process may be performed before removing the unnecessary portion of the base layer 61. Thereafter, the wafer 801 is selectively cut. Thereby, the semiconductor element 30 is manufactured.

[0090] As shown in FIG. 19, the method for manufacturing the semiconductor device 10 includes preparing the connection terminal 20. The connection terminal 20 is formed, for example, as a part of a lead frame. The method for manufacturing the semiconductor device 10 includes mounting the semiconductor element 30 on the connection terminal 20. The semiconductor element 30 is placed on the connection terminal 20 with the electrode terminal 60 and the bonding layer 68 facing the connection terminal 20, and the electrode terminal 60 of the semiconductor element 30 is electrically connected to the connection terminal 20 by the second layer 682 of the bonding layer 68.

[0091] As shown in FIG. 20, the method for manufacturing the semiconductor device 10 includes forming the encapsulation resin 70. The semiconductor element 30 and the connection terminal 20 are encapsulated with the encapsulation resin 70. Thereby, the semiconductor device 10 is manufactured.

[0092] (Operation of the Embodiment) Next, the operations of the semiconductor element 30 and the semiconductor device 10 of the embodiment will be described. The semiconductor element 30 includes an electrode 40 provided on an element surface 301 facing the Z direction, an insulating layer 50 covering the electrode 40 and including an opening 51 that exposes a part of the electrode 40, and an electrode terminal 60 that contacts an exposed portion 40A of the electrode 40 exposed by the opening 51 and partially overlaps the insulating layer 50 when viewed from the Z direction. The electrode terminal 60 includes a base layer 61, a conductive layer 65, and a wall portion 66. The base layer 61 is provided across both the exposed portion 40A and a peripheral portion 52 of the opening 51 in the insulating layer 50, contacts both the exposed portion 40A and the peripheral portion 52, and has an upper surface 611 including a first region 621 and a second region 622. The conductive layer 65 is joined to the first region 621 of the upper surface 611 of the base layer 61. The wall portion 66 is joined to the second region 622 of the upper surface 611 of the base layer 61. The second region 622 is disposed outward with respect to the first region 621. The wall portion 66 stands up from the second region 622.

[0093] In a test on the semiconductor element 30, such as a shear strength test, a force in a direction intersecting the Z direction, for example, the X direction, is applied to the electrode terminal 60. For example, in the formation of a sealing resin 70 that seals the semiconductor element 30, a force is applied to the electrode terminal 60 in a direction intersecting the Z direction. In the case of an electrode terminal not provided with the wall portion 66 of the embodiment, since the force in the X direction is directly applied to the conductive layer of the electrode terminal, the conductive layer may peel off from the base layer 61. On the other hand, the electrode terminal 60 of the embodiment includes a wall portion 66 standing up from a second region 622 disposed outside the first region 621 of the base layer 61. Therefore, when a force in the X direction is applied to the conductive layer 65, the movement of the conductive layer 65 is restricted by the wall portion 66. For this reason, peeling of the conductive layer 65 from the base layer 61 can be suppressed. Therefore, the shear strength of the electrode terminal 60 can be improved, and the reliability of the semiconductor element 30 can be improved.

[0094] The bonding strength between the wall portion 66 and the second region 622 is higher than the bonding strength between the conductive layer 65 and the first region 621. For this reason, peeling of the conductive layer 65 from the base layer 61 can be further suppressed. Therefore, the reliability of the semiconductor element 30 can be further improved.

[0095] The wall portion 66 has an inner wall surface 661 in contact with the conductive layer 65, and the inner wall surface 661 includes a curved surface 665 provided at the upper end portion 664. For example, when the inner wall surface 661 at the upper end of the wall portion 66 has a corner, stress concentration occurs inside the conductive layer 65 with respect to the corner. Due to this stress concentration, cracks may occur in the conductive layer 65. In contrast, since the inner wall surface 661 includes the curved surface 665 at the upper end portion 664, stress concentration can be suppressed. Therefore, cracks in the conductive layer 65 can be suppressed.

[0096] The peripheral portion 52 of the insulating layer 50 includes a flat portion 542, and the wall portion 66 is disposed above the flat portion 542. Therefore, the second region 622 of the upper surface 611 of the base layer 61 is a flat surface. For this reason, the wall portion 66 can be stably provided on the base layer 61.

[0097] The wall portion is in a frame shape so as to surround the opening. Therefore, peeling of the conductive layer 65 can be suppressed with respect to a force in a direction intersecting the Z direction. Therefore, the reliability of the semiconductor element 30 can be further improved.

[0098] The electrode terminal 60 is circular when viewed from the thickness direction. When the electrode terminal 60 is formed in a prismatic shape, stress due to temperature change of the sealing resin 70 or stress remaining in the manufacturing process may concentrate on the corners. Stress concentration on the corners can be a factor causing cracks in the sealing resin 70. In contrast, in the semiconductor device 10 of the embodiment, since the electrode terminal 60 of the semiconductor element 30 is circular when viewed from the Z direction, stress concentration on the electrode terminal 60 can be suppressed.

[0099] The conductive layer 65 includes a terminal base portion 651 surrounded by a wall portion 66 and a terminal upper portion 652 protruding above the wall portion 66. Thereby, the height of the electrode terminal 60 in the Z direction can be made higher than the height of the wall portion 66. The electrode terminal 60 including the conductive layer 65 is connected to a connection terminal 20 on which the semiconductor element 30 is mounted. Therefore, a gap can be ensured between the element surface 301 of the semiconductor element 30 and the connection terminal 20. A sealing resin 70 for sealing the semiconductor element 30 is interposed between the connection terminal 20 and the semiconductor element 30. Therefore, by ensuring a gap between the element surface 301 of the semiconductor element 30 and the connection terminal 20, the sealing resin 70 can easily enter between the semiconductor element 30 and the connection terminal 20.

[0100] The terminal upper portion 652 is also provided on the wall portion 66. Since the terminal surface 601 of the electrode terminal 60 is the surface of the terminal upper portion 652, the terminal surface 601 can be enlarged by providing the terminal upper portion 652 also on the wall portion 66. The electrode terminal 60 is electrically connected to the connection terminal 20 by a bonding layer 68 on the terminal surface 601. Therefore, by enlarging the terminal surface 601, the mounting strength of the electrode terminal 60 with respect to the connection terminal 20 can be ensured.

[0101] The terminal upper portion 652 is also provided on the wall portion 66. In the electrode terminal 60, the shape of the terminal surface 601 may be affected by the configuration between the terminal surface 601 and the electrode 40. Therefore, by appropriately adjusting the height T1 of the wall portion 66 and the height T2 of the terminal upper portion 652, a suitable terminal surface 601 can be obtained.

[0102] The wall portion 66 is a sputter layer, and the conductive layer 65 is a plating layer. In sputtering, a film is formed by attaching a material to a base layer with higher energy compared to the plating method. Therefore, it can be said that the sputter layer formed using sputtering has a higher adhesion energy to the base layer than the plating layer formed using the plating method. For this reason, the bonding strength between the base layer 61 and the wall portion 66 can be made higher than the bonding strength between the base layer 61 and the conductive layer 65.

[0103] The base layer 61 includes a seed layer 64 having a barrier layer 63 in contact with both the exposed portion 40A and the peripheral portion 52 of the insulating layer 50, a lower surface 642 joined to the barrier layer 63, and an upper surface 611 including a first region 621 and a second region 622. The barrier layer 63 can relieve the stress applied from the electrode terminal 60 to the insulating layer 50.

[0104] The bonding layer 68 includes a first layer 681 on the terminal surface 601 and a second layer 682 on the first layer 681. In one example, the first layer 681 is made of a material containing Ni. In one example, the second layer 682 is a solder layer made of a material containing Sn. Therefore, by melting the second layer 682, it can be easily joined to the electrode terminal 60 and the connection terminal 20. Further, by the first layer 681 being interposed between the conductive layer 65 of the electrode terminal 60 and the second layer 682 of the bonding layer 68, the chemical reaction between the Cu-containing conductive layer 65 and the Sn-containing second layer 682 can be suppressed.

[0105] (Effects of the Embodiment) As described above, according to this embodiment, the following effects can be obtained. (1) The semiconductor element 30 includes an electrode 40 provided on the element surface 301 facing the Z direction, an insulating layer 50 covering the electrode 40 and including an opening 51 that exposes a part of the electrode 40, and an electrode terminal 60 that is in contact with the exposed portion 40A of the electrode 40 exposed by the opening 51 and partially overlaps the insulating layer 50 when viewed from the Z direction. The electrode terminal 60 includes a base layer 61, a conductive layer 65, and a wall portion 66. The base layer 61 is provided across both the exposed portion 40A and the peripheral portion 52 of the opening 51 in the insulating layer 50, is in contact with both the exposed portion 40A and the peripheral portion 52, and has an upper surface 611 including a first region 621 and a second region 622. The conductive layer 65 is joined to the first region 621 of the upper surface 611 of the base layer 61. The wall portion 66 is joined to the second region 622 of the upper surface 611 of the base layer 61. The second region 622 is disposed outward with respect to the first region 621. The wall portion 66 stands up from the second region 622.

[0106] In a test on the semiconductor element 30, for example, in terms of shear strength, a force in a direction intersecting the Z direction, for example, the X direction, is applied to the electrode terminal 60. For example, in the formation of the encapsulating resin 70 that encapsulates the semiconductor element 30, a force is applied in a direction intersecting the Z direction to the electrode terminal 60. In the case of an electrode terminal without the wall portion 66 of the embodiment, since the force in the X direction is directly applied to the conductive layer of the electrode terminal, the conductive layer may peel off from the base layer 61. On the other hand, the electrode terminal 60 of the embodiment includes a wall portion 66 that stands up from a second region 622 disposed outside the first region 621 of the base layer 61. Therefore, when a force in the X direction is applied to the conductive layer 65, the movement of the conductive layer 65 is restricted by the wall portion 66. For this reason, peeling of the conductive layer 65 from the base layer 61 can be suppressed. Therefore, the shear strength of the electrode terminal 60 can be improved, and the reliability of the semiconductor element 30 can be improved.

[0107] (2) The bonding strength between the wall portion 66 and the second region 622 is higher than the bonding strength between the conductive layer 65 and the first region 621. For this reason, peeling of the conductive layer 65 from the base layer 61 can be further suppressed. Therefore, the reliability of the semiconductor element 30 can be further improved.

[0108] (3) The wall portion 66 has an inner wall surface 661 that contacts the conductive layer 65, and the inner wall surface 661 includes a curved surface 665 provided at the upper end portion 664. For example, when the inner wall surface 661 at the upper end of the wall portion 66 has a corner, stress concentration occurs inside the conductive layer 65 with respect to the corner. Due to this stress concentration, cracks may occur in the conductive layer 65. On the other hand, since the inner wall surface 661 includes the curved surface 665 at the upper end portion 664, stress concentration can be suppressed. For this reason, cracks in the conductive layer 65 can be suppressed.

[0109] (4) The peripheral portion 52 of the insulating layer 50 includes a flat portion 542, and the wall portion 66 is disposed above the flat portion 542. Therefore, the second region 622 of the upper surface 611 of the base layer 61 is a flat surface. For this reason, the wall portion 66 can be stably provided on the base layer 61.

[0110] The wall portion is in a frame shape so as to surround the opening. Therefore, peeling of the conductive layer 65 can be suppressed against forces in a direction intersecting the Z direction. Therefore, the reliability of the semiconductor element 30 can be further improved.

[0111] (5) The electrode terminal 60 is circular when viewed from the thickness direction. When the electrode terminal is formed in a prismatic shape, temperature changes in the sealing resin 70 or stress remaining in the manufacturing process may concentrate on the corners. Stress concentration on the corners can be a factor in causing cracks in the sealing resin 70. On the other hand, in the semiconductor device 10 of the embodiment, since the electrode terminal 60 of the semiconductor element 30 is circular when viewed from the Z direction, stress concentration on the electrode terminal 60 can be suppressed.

[0112] (6) The conductive layer 65 includes a terminal base portion 651 surrounded by the wall portion 66 and a terminal upper portion 652 protruding above the wall portion 66. Thereby, the height of the electrode terminal 60 in the Z direction can be made higher than the height of the wall portion 66. The electrode terminal 60 including the conductive layer 65 is connected to the connection terminal 20 on which the semiconductor element 30 is mounted. Therefore, a space can be secured between the element surface 301 of the semiconductor element 30 and the connection terminal 20. A sealing resin 70 for sealing the semiconductor element 30 is interposed between the connection terminal 20 and the semiconductor element 30. Therefore, by securing a space between the element surface 301 of the semiconductor element 30 and the connection terminal 20, the sealing resin 70 can easily enter between the semiconductor element 30 and the connection terminal 20.

[0113] (7) The terminal upper portion 652 is also provided on the wall portion 66. Since the terminal surface 601 of the electrode terminal 60 is the surface of the terminal upper portion 652, the terminal surface 601 can be enlarged by providing the terminal upper portion 652 also on the wall portion 66. The electrode terminal 60 is electrically connected to the connection terminal 20 by a bonding layer 68 on the terminal surface 601. Therefore, by enlarging the terminal surface 601, the mounting strength of the electrode terminal 60 with respect to the connection terminal 20 can be ensured.

[0114] (8) The upper part 652 of the terminal is also provided on the wall part 66. In the electrode terminal 60, the shape of the terminal surface 601 may be affected by the configuration between the terminal surface 601 and the electrode 40. Therefore, by appropriately adjusting the height T1 of the wall part 66 and the height T2 of the upper part 652 of the terminal, a suitable terminal surface 601 can be obtained.

[0115] (9) The wall part 66 is a sputter layer, and the conductive layer 65 is a plating layer. In sputtering, a film is formed by attaching a material to the underlying layer with higher energy compared to the plating method. Therefore, it can be said that the sputter layer formed using sputtering has a higher adhesion energy to the underlying layer than the plating layer formed using the plating method. For this reason, the bonding strength between the base layer 61 and the wall part 66 can be made higher than the bonding strength between the base layer 61 and the conductive layer 65.

[0116] (10) The base layer 61 includes a barrier layer 63 that is in contact with both the exposed portion 40A and the peripheral portion 52 of the insulating layer 50, a lower surface 642 that is joined to the barrier layer 63, and a seed layer 64 that includes an upper surface 611 including a first region 621 and a second region 622. The stress applied from the electrode terminal 60 to the insulating layer 50 can be relaxed by the barrier layer 63.

[0117] (11) The bonding layer 68 includes a first layer 681 on the terminal surface 601 and a second layer 682 on the first layer 681. In one example, the first layer 681 is composed of a material containing Ni. In one example, the second layer 682 is a solder layer composed of a material containing Sn. Therefore, by melting the second layer 682, the electrode terminal 60 and the connection terminal 20 can be easily joined. Further, by the first layer 681 being interposed between the conductive layer 65 of the electrode terminal 60 and the second layer 682 of the bonding layer 68, the chemical reaction between the Cu-containing conductive layer 65 and the Sn-containing second layer 682 can be suppressed.

[0118] (Modified Example) The above embodiments can be modified as follows, for example. The above embodiments and each of the following modification examples can be combined with each other as long as no technical contradiction occurs. In the following modification examples, for parts common to the above embodiments, the same reference numerals as those in the above embodiments are given and the description thereof is omitted.

[0119] · The configuration of the semiconductor device 10 may be appropriately changed. As shown in FIG. 21, the semiconductor device 10A includes a semiconductor element 30A. In this semiconductor element 30A, the base layer 61A of the electrode terminal 60 has a single-layer structure. The base layer 61A may be, for example, a seed layer. The base layer 61 may be made of a material containing at least one of Ti and Cu.

[0120] · The terminal side surface 603 of the electrode terminal 60 can be appropriately changed. As shown in FIGS. 5 and 7, the terminal side surface 603 includes the outer wall surface 662 of the wall portion 66 and the outer side surface 653 of the terminal upper portion 652 of the conductive layer 65. In one example, the outer side surface 653 of the conductive layer 65 may be flush with the outer wall surface 662 of the wall portion 66. The outer side surface 653 of the conductive layer 65 may be located outside the outer wall surface 662 of the wall portion 66. The outer side surface 653 of the conductive layer 65 may be located inside the outer wall surface 662 of the wall portion 66.

[0121] · The positional relationship between the side surface 613 of the base layer 61 and the terminal side surface 603 of the electrode terminal 60 can be appropriately changed. In one example, the side surface 613 of the base layer 61 may be flush with the terminal side surface 603. The side surface 613 of the base layer 61 may be located outside the terminal side surface 603. The side surface 613 of the base layer 61 may be located inside the terminal side surface 603.

[0122] The base layer 61 includes a barrier layer 63 and a seed layer 64. In one example, the side surface of the barrier layer 63 and the side surface of the seed layer 64 may be flush. The side surface of the barrier layer 63 may be located outside the side surface of the seed layer 64. The side surface of the barrier layer 63 may be located inside the side surface of the seed layer 64.

[0123] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0124] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0125] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0126] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0127] (Appendix 1) an electrode (40) provided on the element surface facing the thickness direction (Z); an insulating layer (50) covering the electrode (40) and including an opening (51) exposing a portion of the electrode (40); an electrode terminal (60) that contacts the exposed portion (40A) of the electrode (40) exposed by the opening (51) and partially overlaps the insulating layer (50) when viewed from the thickness direction (Z); Including, The electrode terminal (60) is a base layer (61) that is provided across both the exposed portion (40A) and a peripheral portion (52) of the opening (51) in the insulating layer (50), that is in contact with both the exposed portion (40A) and the peripheral portion (52), and that has an upper surface (611) that includes a first region (621) and a second region (622); a conductive layer (65) bonded to the first region (621) of the upper surface (611) of the base layer (61); a wall portion (66) joined to the second region (622) of the upper surface (611) of the base layer (61); Including, The second region (622) is disposed outward from the first region (621), and the wall portion (66) stands upright from the second region (622). Semiconductor element.

[0128] (Appendix 2) The bonding strength between the wall portion (66) and the second region (622) is higher than the bonding strength between the conductive layer (65) and the first region (621). 2. The semiconductor device of claim 1.

[0129] (Appendix 3) The conductive layer (65) and the wall portion (66) are made of different materials. 10. The semiconductor device according to claim 1 or 2.

[0130] (Appendix 4) the conductive layer (65) is made of a material containing Cu, The wall portion (66) is made of a material containing Ti. 4. A semiconductor device according to any one of claims 1 to 3.

[0131] (Appendix 5) The wall portion (66) has an inner wall surface (661) that contacts the conductive layer (65), The inner wall surface (661) includes a curved surface (665) provided at the upper end. 5. A semiconductor device according to any one of claims 1 to 4.

[0132] (Appendix 6) The peripheral edge (52) of the insulating layer (50) includes a flat portion (542), The wall portion (66) is disposed above the flat portion (542). 6. A semiconductor device according to any one of claims 1 to 5.

[0133] (Appendix 7) The wall portion (66) has a frame shape so as to surround the opening portion (51). 7. A semiconductor device according to any one of claims 1 to 6.

[0134] (Appendix 8) The electrode terminal (60) has a circular shape when viewed from the thickness direction (Z). 8. A semiconductor device according to any one of claims 1 to 7.

[0135] (Appendix 9) The conductive layer (65) a terminal base (651) surrounded by the wall portion (66); a terminal upper portion (652) protruding above the wall portion (66); Including, 9. A semiconductor device according to any one of claims 1 to 8.

[0136] (Appendix 10) The terminal upper portion (652) is also provided on the wall portion (66). 10. The semiconductor device of claim 9.

[0137] (Appendix 11) The height of the wall portion (66) is greater than the height of the terminal upper portion (652). 11. The semiconductor device according to claim 9 or 10.

[0138] (Appendix 12) The height of the wall portion (66) is lower than the height of the terminal upper portion (652). 11. The semiconductor device according to claim 9 or 10.

[0139] (Appendix 13) The wall portion (66) includes an outer wall surface (662) facing in the opposite direction to the inner wall surface (661), The distance between the outer wall surfaces (662) of a pair of portions of the wall portion (66) sandwiching the opening portion (51) is 20 μm or more and 100 μm or less. 6. The semiconductor device of claim 5.

[0140] (Appendix 14) In a plan view, the area of the first region (621) is larger than the area of the second region (622). 14. A semiconductor device according to any one of claims 1 to 13.

[0141] (Appendix 15) The wall portion (66) is a sputtered layer, The conductive layer (65) is a plating layer. 15. The semiconductor device of any one of claims 1 to 14.

[0142] (Appendix 16) The base layer (61) a barrier layer in contact with both the exposed portion (40A) and the peripheral edge portion (52) of the insulating layer (50); a seed layer having a lower surface in contact with the barrier layer and an upper surface including the first region (621) and the second region (622); Including, 16. A semiconductor device according to any one of claims 1 to 15.

[0143] (Appendix 17) the barrier layer is made of a material containing Ti, the seed layer is made of a material containing Cu. 17. The semiconductor device of claim 16.

[0144] (Appendix 18) The electrode terminal (60) includes a terminal back surface facing the electrode (40) and a terminal front surface opposite the terminal back surface, A bonding layer (68) is provided on the surface of the terminal. 18. A semiconductor device according to any one of claims 1 to 17.

[0145] (Appendix 19) The bonding layer (68) a first layer (681) on the terminal surface; a second layer (682) on the first layer; Including, 19. The semiconductor device of claim 18.

[0146] (Appendix 20) A semiconductor element (30) according to any one of Supplementary Note 1 to Supplementary Note 19; a connection terminal (20) electrically connected to the semiconductor element; a sealing resin (70) that seals the semiconductor element and a part of the connection terminal; 10. A semiconductor device comprising:

[0147] (Appendix 21) A semiconductor element (30); a connection terminal (20) electrically connected to the semiconductor element; a sealing resin (70) that seals the semiconductor element and a part of the connection terminal; Including, The semiconductor element (30) is an electrode (40) provided on the element surface facing the thickness direction (Z); an insulating layer (50) covering the electrode (40) and including an opening (51) exposing a portion of the electrode (40); An electrode terminal (60) that contacts an exposed portion (40A) of the electrode (40) exposed by the opening (51) and partially overlaps the insulating layer (50) when viewed from the thickness direction (Z); including The electrode terminal (60) is provided so as to straddle both the exposed portion (40A) and the peripheral edge portion (52) of the opening (51) in the insulating layer (50), is in contact with both the exposed portion (40A) and the peripheral edge portion (52), and has a base layer (61) having an upper surface (611) including a first region (621) and a second region (622); a conductive layer (65) joined to the first region (621) of the upper surface (611) of the base layer (61); a wall portion (66) joined to the second region (622) of the upper surface (611) of the base layer (61); including The second region (622) is disposed outward of the first region (621), and the wall portion (66) stands up from the second region (622), The electrode terminal (60) is electrically connected to the connection terminal. A semiconductor device.

[0148] (Appendix 22) Forming an insulating layer (50) that covers the electrode (40); Forming an opening (51) in the insulating layer (50) to expose a part of the electrode (40); Using sputtering, covering the exposed portion (40A) of the electrode (40) exposed by the opening (51) and the peripheral edge portion (52) of the opening (51) in the insulating layer (50), and forming a base layer (61) including a first region (621) that overlaps the exposed portion (40A) and a second region (622) outside the first region (621); Using sputtering to form a wall portion (66) standing up in the second region (622); Using a plating method to form a conductive layer (65) in the first region (621); A method for manufacturing a semiconductor element, including.

[0149] (Appendix 23) Forming the base layer (61) includes: forming a barrier layer in contact with both the exposed portion (40A) and the peripheral portion (52) using sputtering; forming a seed layer having a lower surface joined to the barrier layer and a surface including the first region (621) and the second region (622) using sputtering; and a method for manufacturing a semiconductor device according to Appendix 22.

[0150] (Appendix 24) Forming the wall portion (66) includes: forming a mask (802) including a mask opening (803) that covers a part of the electrode (40) exposed from the insulating layer (50) and the insulating layer (50) and exposes the first region (621) and the second region (622); forming a first metal layer (804) that covers the first region (621) and the second region (622) exposed by the mask opening (803), the inner surface of the mask opening (803), and the surface of the mask using sputtering; etching the first metal layer (804) to form the wall portion (66); and when forming the conductive layer (65), forming the conductive layer (65) inside the mask opening (803). A method for manufacturing a semiconductor device according to Appendix 22 or Appendix 23.

[0151] The above description is merely illustrative. Those skilled in the art will recognize that there are many more possible combinations and substitutions other than the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and variations included within the scope of the present disclosure, including the scope of the claims.

Description of Reference Numerals

[0152] 10, 10A Semiconductor Device 11 Device Surface 12 Device Back Side 13 - 16 Device Sides 20 Connection Terminal 201 Connection Terminal Surface 202 Connection Terminal Back Side 21 Lead Part 211 Protruding Part 22 Pad Part 221 Protruding Part 23 Finger Part 30, 30A Semiconductor Element 301 Element Surface 302 Element Back Side 303 - 306 Element Sides 31 Substrate 311 Substrate Surface 312 Substrate Back Side 32 Device Region 33 Insulating Film 34 Interlayer Insulating Film 35 Top Insulating Film 351 Surface 36 Interlayer Wiring 37 Via Wiring 371 Barrier Film 372 Via Body 375 Via Hole 38 Multilayer Wiring Structure 40 Electrode 40A Exposed Part 40B Non - Exposed Part 401 Electrode Top Surface 402 Electrode Bottom Surface 41 Wiring Barrier Film 42 Wiring Electrode 421 Wiring Top Surface 422 Wiring Bottom Surface 423 Wiring Side Surface 424 Wiring Upper End Corner 43 Cover Electrode 431 Cover Top Surface 432 Cover Bottom Surface 434 Round Part 441 First Metal Film 442 Second metal film 50 Insulating layer 51 Opening 52 Peripheral part 53 Surface 531 First surface 532 Second surface 541 Opening end 542 Flat part 60 Electrode terminal 601 Terminal surface 602 Terminal inner surface 603 Terminal side surface 61, 61A Base layer 611 Upper surface 612 Lower surface 613 Side surface 621 First region 622 Second region 63 Barrier layer 64 Seed layer 642 Lower surface 65 Conductive layer 651 Terminal base 652 Terminal upper part 653 Outer surface 66 Wall part 661 Inner wall surface 662 Outer wall surface 663 Lower end part 664 Upper end part 665 Curved surface 68 Bonding layer 681 First layer 682 Second layer 70 Encapsulating resin 701 Encapsulating surface 702 Encapsulating inner surface 703 - 706 Encapsulating side surfaces 75 Conductive film

Claims

1. An electrode provided on an element surface facing the thickness direction, an insulating layer covering the electrode and including an opening that exposes a part of the electrode, an electrode terminal that contacts an exposed portion of the electrode exposed by the opening and partially overlaps the insulating layer when viewed from the thickness direction, comprising: the electrode terminal is provided across both the exposed portion and the peripheral edge of the opening in the insulating layer, is in contact with both the exposed portion and the peripheral edge, and has an upper surface including a first region and a second region; a base layer, a conductive layer joined to the first region of the upper surface of the base layer, a wall portion joined to the second region of the upper surface of the base layer, comprising: the second region is disposed outward of the first region, and the wall portion stands up from the second region, a semiconductor element.

2. The bonding strength between the wall portion and the second region is higher than the bonding strength between the conductive layer and the first region, The semiconductor element according to claim 1.

3. The conductive layer and the wall portion are made of different materials, The semiconductor element according to claim 1 or claim 2.

4. The conductive layer is made of a material containing Cu, The wall portion is made of a material containing Ti, The semiconductor element according to claim 1.

5. The wall portion has an inner wall surface in contact with the conductive layer, The inner wall surface includes a curved surface provided at the upper end portion, The semiconductor element according to claim 1.

6. The peripheral edge of the insulating layer includes a flat portion, The wall portion is disposed above the flat portion, The semiconductor element according to claim 1.

7. The wall portion is in a frame shape so as to surround the opening, The semiconductor element according to claim 1.

8. The electrode terminal is circular when viewed from the thickness direction, The semiconductor element according to claim 1.

9. The conductive layer a portion surrounded by the wall portion, a portion protruding above the wall portion, comprising: The semiconductor element according to claim 1.

10. The protruding portion is also provided on the wall portion, The semiconductor element according to claim 1.

11. The height of the wall portion is higher than the height of the protruding portion, The semiconductor element according to claim 1.

12. The height of the wall portion is lower than the height of the protruding portion, The semiconductor element according to claim 1.

13. The wall portion includes an outer wall surface facing the opposite direction to the inner wall surface, The distance between the outer wall surfaces of a pair of portions of the wall portion that sandwich the opening is 20 μm or more and 100 μm or less. The semiconductor device according to claim 5.

14. In a plan view, the area of the first region is larger than the area of the second region. The semiconductor device according to claim 1.

15. The wall portion is a sputtered layer. The conductive layer is a plated layer. The semiconductor device according to claim 1.

16. The base layer A barrier layer that is in contact with both the exposed portion and the peripheral edge of the insulating layer, A seed layer having a lower surface joined to the barrier layer and an upper surface including the first region and the second region, including The semiconductor device according to claim 1.

17. A semiconductor device, A connection terminal electrically connected to the semiconductor device, A sealing resin that seals the semiconductor device and a part of the connection terminal, including The semiconductor device An electrode provided on the element surface facing the thickness direction, An insulating layer that covers the electrode and includes an opening that exposes a part of the electrode, An electrode terminal that is in contact with the exposed portion of the electrode exposed by the opening and partially overlaps the insulating layer when viewed from the thickness direction, including The electrode terminal A base layer that is provided across both the exposed portion and the peripheral edge of the opening in the insulating layer, is in contact with both the exposed portion and the peripheral edge, and has an upper surface including a first region and a second region, A conductive layer joined to the first region of the upper surface of the base layer, A wall portion joined to the second region of the upper surface of the base layer, including The second region is disposed outward of the first region, and the wall portion stands up from the second region. The electrode terminal is electrically connected to the connection terminal. Semiconductor device.

18. Forming an insulating layer that covers the electrode, Forming an opening in the insulating layer that exposes a part of the electrode, Using sputtering, covering the exposed portion of the electrode exposed by the opening and the peripheral edge of the opening in the insulating layer, and forming a base layer including a first region that overlaps the exposed portion and a second region outside the first region, Using sputtering, forming a wall portion that stands up in the second region, Using a plating method, forming a conductive layer in the first region, including A method for manufacturing a semiconductor device.

Images