Semiconductor device and manufacturing method for semiconductor device

Abstract

To suppress the variation in concentration and depth of junction between a carrier accumulation layer and a base layer of a semiconductor device.SOLUTION: A semiconductor device includes a source layer (13) of a first conductivity type located in a surface layer part of a semiconductor layer and defined by the concentration profile of a first impurity, a base layer (15) of a second conductivity type located on a lower side of the source layer (13) and defined by the concentration profile of a second impurity, a carrier accumulation layer (2) of the first conductivity type located on a lower side of the base layer (15) and defined by the concentration profile of a third impurity, a drift layer (1) of the first conductivity type located on a lower side of the carrier accumulation layer (2), and a CSC layer (50) of the second conductivity type defined by the concentration profile of a fourth impurity. A region of the CSC layer (50) that contains the fourth impurity includes a region where a region of the base layer (15) that contains the second impurity and a region of the carrier accumulation layer (2) that contains the third impurity overlap with each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] For example, Patent Document 1 below discloses a technique for designing each of a p-type base layer and an n-type carrier accumulation layer of an IGBT so as to have a peak of impurity concentration in order to reduce variations in the threshold voltage (Vth) of the IGBT.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the IGBT of Patent Document 1, since the peak impurity concentrations of the p-type base layer and the n-type carrier accumulation layer are stabilized, the variations in the steady-state threshold voltage become small. However, variations in depth and concentration occur at the junction between the n-type source layer and the p-type base layer, and at the junction between the p-type base layer and the n-type carrier accumulation layer. In that case, in the transient state of switching, the current cannot be interrupted at a location where the impurity concentration is low, resulting in a decrease in the breakdown withstand voltage, or current concentration occurs due to variations in the local carrier distribution, resulting in a decrease in the breakdown withstand voltage. As a result, the reverse bias safe operating area (RBSOA) of the semiconductor device decreases. + The present disclosure has been made to solve the above problems, and an object thereof is to suppress variations in the depth and concentration of the junction between the base layer and the carrier accumulation layer of the semiconductor device.

[0005]

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a source layer of a first conductivity type located in the surface layer portion of the semiconductor layer and defined by the concentration profile of a first impurity, a base layer of a second conductivity type located below the source layer and defined by the concentration profile of a second impurity, a carrier accumulation layer of the first conductivity type located below the base layer and defined by the concentration profile of a third impurity, a drift layer of the first conductivity type located below the carrier accumulation layer, and a CSC layer of the second conductivity type defined by the concentration profile of a fourth impurity, wherein the region containing the fourth impurity is located so as to include a region where the region containing the second impurity in the base layer overlaps with the region containing the third impurity in the carrier accumulation layer.

Advantages of the Invention

[0007] According to the present disclosure, by providing a CSC layer in the semiconductor device, variations in the depth and concentration of the junction between the base layer and the carrier accumulation layer of the semiconductor device can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

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Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0009] In the following description, n and p indicate the conductivity types of semiconductors. In the present disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type. However, conversely, the first conductivity type may be p-type and the second conductivity type may be n-type. Also, n - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0010] Also, the height of the impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak concentration of impurities.

[0011] <Embodiment 1> The configuration of the semiconductor device according to Embodiment 1 will be described below. The semiconductor element included in the semiconductor device is assumed to be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), RC-IGBT (Reverse Conducting IGBT), SBD (Schottky Barrier Diode), PN diode, etc. Here, the semiconductor element will be described assuming it is an RC-IGBT.

[0012] The material of the semiconductor element may be silicon (Si) or a wide bandgap semiconductor such as silicon carbide (SiC). A semiconductor device formed using a wide bandgap semiconductor is superior in operation at high voltage, high current, and high temperature compared to a semiconductor device using silicon. Examples of wide bandgap semiconductors include gallium nitride (GaN)-based materials and diamond in addition to silicon carbide.

[0013] FIG. 1 is a diagram showing the configuration of the semiconductor device according to Embodiment 1 and is a cross-sectional view of the IGBT region 10 that functions as an IGBT in the RC-IGBT. The diode region that functions as a diode in the RC-IGBT will be described in the embodiments shown later.

[0014] As shown in FIG. 1, an active trench gate 11 and a dummy trench gate 12 are provided in the IGBT region 10. The active trench gate 11 is configured by providing a gate trench electrode 11a in a trench formed in a semiconductor substrate (semiconductor layer) via a gate trench insulating film 11b. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench formed in the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to a gate pad (not shown). The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to the emitter electrode 6.

[0015] On both sides in the width direction of the active trench gate 11, n + -type source layer 13 is provided in contact with the gate trench insulating film 11b. n + The n-type source layer 13 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity. That is, n + The n-type source layer 13 is located in the surface layer portion of the semiconductor layer and is defined by the concentration profile of the n-type first impurity. n + The concentration of the n-type impurity in the n-type source layer 13 is, for example, 1.0E+17 / cm 3 ~1.0E+20 / cm 3 It is.

[0016] Between two adjacent dummy trench gates 12, p + -type contact layer 14 is provided. Also, n + The n-type source layer 13 may be provided alternately with the p + -type contact layer 14 along the extending direction of the active trench gate 11. p + The p-type contact layer 14 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. p + The concentration of the p-type impurity in the p-type contact layer 14 is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 It is.

[0017] In the example of FIG. 1, a set of three active trench gates 11 and a set of three dummy trench gates 12 are arranged alternately. However, there is no restriction on the number of active trench gates 11 included in a set of active trench gates 11 and the number of dummy trench gates 12 included in a set of dummy trench gates 12. The number of dummy trench gates 12 may be 0. That is, all the trenches provided in the IGBT region 10 may be used as active trench gates 11.

[0018] The semiconductor device has an n - -type drift layer 1 made of a semiconductor substrate. n -The n-type drift layer 1 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity. n - The concentration of the n-type impurity in the n-type drift layer 1 is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 is. The semiconductor substrate ranges from the n + type source layer 13 and the p + type contact layer 14 to the p-type collector layer 16. In FIG. 1, the n + type source layer 13 and the p + type contact layer 14's upper end on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device. The semiconductor device has an n - type drift layer 1 between the first main surface and the second main surface facing the first main surface in the IGBT region 10 which is a cell region. Hereinafter, the first main surface side of the semiconductor substrate may be referred to as "upper side", and the second main surface side may be referred to as "lower side".

[0019] n + type source layer 13 and the p + type contact layer 14, a p-type base layer 15 is provided on the second main surface side. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. That is, the p-type base layer 15 is located below the n + type source layer 13 and is defined by the concentration profile of the p-type second impurity. The concentration of the p-type impurity in the p-type base layer 15 is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 is. The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0020] On the first main surface side of the p-type base layer 15, an n + type source layer 13 is provided in contact with the gate trench insulating film 11b of the active trench gate 11, and a p + type contact layer 14 is provided in the remaining region. n + type source layer 13 and p+ The p-type contact layer 14 forms the first main surface of the semiconductor substrate. Note that the p + -type contact layer 14 is a region with a higher concentration of p-type impurities than the p-type base layer 15.

[0021] On the second main surface side of the p-type base layer 15, an n - -type carrier accumulation layer 2 with a higher concentration of n-type impurities than the n-type drift layer 1 is provided. The n-type carrier accumulation layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity. That is, the n-type carrier accumulation layer 2 is located below the p-type base layer 15 and is defined by the concentration profile of the n-type third impurity. The concentration of the n-type impurity in the n-type carrier accumulation layer 2 is, for example, 1.0E+13 / cm 3 ~1.0E+17 / cm 3 . By providing the n-type carrier accumulation layer 2, the conduction loss when current flows through the IGBT region 10 can be reduced.

[0022] The n - -type drift layer 1 is located on the second main surface side of the n-type carrier accumulation layer 2. Further, on the second main surface side of the n - -type drift layer 1, an n - -type buffer layer 3 with a higher concentration of n-type impurities than the n-type drift layer 1 is provided. The n-type buffer layer 3 is provided to suppress the punch-through of the depletion layer extending from the p-type base layer 15 to the second main surface side when the semiconductor device is in the off state. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) or protons (H + ), or may be formed by implanting both phosphorus (P) and protons (H + ). The concentration of the n-type impurity in the n-type buffer layer 3 is, for example, 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0023] Note that even if the n-type buffer layer 3 is not provided, an n - -type drift layer 1 may be provided in the region of the n-type buffer layer 3 shown in FIG. 1. The n-type buffer layer 3 and the n -The drift layer may be called by combining the type drift layer 1.

[0024] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. That is, between the n - type drift layer 1 and the second main surface, a p-type collector layer 16 is provided. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type collector layer 16 is, for example, 1.0E+16 / cm 3 ~1.0E+20 / cm 3 . The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate.

[0025] As shown in FIG. 1, the active trench gate 11 and the dummy trench gate 12 penetrate the p-type base layer 15 and the n-type carrier accumulation layer 2 from the first main surface of the semiconductor substrate and reach the n - type drift layer 1. The gate trench electrode 11a of the active trench gate 11 faces the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the n - type drift layer 1 via the gate trench insulating film 11b. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b.

[0026] An interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region where the interlayer insulating film 4 is not provided on the first main surface of the semiconductor substrate and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), may be, for example, titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si). The barrier metal 5 makes an ohmic contact with the n + type source layer 13, p + type contact layer 14, and the dummy trench electrode 12a, and the n + type source layer 13, p +The type contact layer 14 is electrically connected to the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or may be an electrode composed of a plurality of metal films formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film.

[0027] In a fine region such as between adjacent interlayer insulating films 4, if there is a region where good embedding cannot be obtained with the emitter electrode 6, tungsten having better embedding properties than the emitter electrode 6 may be arranged in the fine region, and the emitter electrode 6 may be provided on the tungsten. Without providing the barrier metal 5, n + type source layer 13, p + The emitter electrode 6 may be provided on the type contact layer 14 and the dummy trench electrode 12a. Also, n + The barrier metal 5 may be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode.

[0028] In FIG. 1, a diagram is shown in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0029] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be composed of an aluminum alloy or a combination of an aluminum alloy and a plating film, similar to the emitter electrode 6. Also, the collector electrode 7 may have a configuration different from that of the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0030] In addition to the above configuration, the semiconductor device according to Embodiment 1 includes an n + type source layer 13, a p-type base layer 15, and a p-type CSC (Carrier Storage Control) layer 50 that overlaps with the n-type carrier accumulation layer 2. The p-type CSC layer 50 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. That is, the p-type CSC layer 50 is defined by the concentration profile of the p-type fourth impurity. In the present embodiment, boron is used as the p-type impurity that constitutes the p-type base layer 15.

[0031] FIG. 2 shows the impurity concentration profiles of the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, the n - type drift layer 1, and the p-type CSC layer 50 in the semiconductor device according to Embodiment 1. FIG. 2 shows the impurity concentration profile in the depth direction from the first main surface of the semiconductor substrate in the portion along the dashed line D1-D2 in FIG. 1.

[0032] As shown in FIG. 2, the concentration profile of the fourth impurity (B) that defines the p-type CSC layer 50 has a gently sloping concentration distribution in the depth direction of the semiconductor substrate. Also, the position (depth) at which the p-type CSC layer 50 is formed is set such that the region containing the fourth impurity that defines the p-type CSC layer 50 includes a region where the region containing the second impurity (B) that defines the p-type base layer 15 and the region containing the third impurity (P) that defines the n-type carrier accumulation layer 2 overlap.

[0033] In this way, by forming the p-type CSC layer 50 so as to overlap the portion where the p-type base layer 15 and the n-type carrier accumulation layer 2 are joined, the variation in the depth and concentration of the junction between the p-type base layer 15 and the n-type carrier accumulation layer 2 is reduced. Thereby, the reduction of the RBSOA of the semiconductor device is suppressed.

[0034] Also, the region containing the fourth impurity that defines the p-type CSC layer 50 is, as shown in FIG. 2, n +The region may include an area where the region containing the first impurity (P or As) defining the n-type source layer 13 overlaps with the region containing the second impurity defining the p-type base layer 15. In that case, the n + variations in the depth and concentration of the junction between the n-type source layer 13 and the p-type base layer 15 are also reduced, and a further decrease in the RBSOA of the semiconductor device is suppressed.

[0035] Here, a method for manufacturing a semiconductor device according to Embodiment 1 will be described. The method for manufacturing a semiconductor device according to Embodiment 1 may be the same as a general method for manufacturing an RC-IGBT, except for the steps of forming the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the p-type CSC layer 50. Therefore, here, with reference to the flowchart of FIG. 3, the steps of forming the n + type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the p-type CSC layer 50 will be described.

[0036] First, an n - type drift layer 1 is formed, and from the first main surface side of the n - type drift layer 1, a p-type fourth impurity defining the p-type CSC layer 50 is ion-implanted, and the fourth impurity is diffused into the semiconductor substrate by heat treatment to form the p-type CSC layer 50 (step S1). By diffusing the fourth impurity, a p-type CSC layer 50 having a gently sloping concentration distribution in the depth direction of the semiconductor substrate can be formed.

[0037] Next, from the first main surface side, an n-type first impurity defining the n-type source layer 13 is ion-implanted into the semiconductor substrate, so that an n + type source layer 13 having a peak of independent impurity concentration is formed in the surface layer portion of the semiconductor substrate (step S2). Subsequently, from the first main surface side, a p-type second impurity defining the p-type base layer 15 is ion-implanted into the semiconductor substrate, so that the n + type source layer 13 having a peak of independent impurity concentration is formed in the surface layer portion of the semiconductor substrate (step S2). Subsequently, from the first main surface side, a p-type second impurity defining the p-type base layer 15 is ion-implanted into the semiconductor substrate, so that the n +A p-type base layer 15 having an independent impurity concentration peak is formed below the n-type source layer 13 (step S3). Further, by ion-implanting a third impurity into the semiconductor substrate from the first main surface side, an n-type carrier accumulation layer 2 of the first conductivity type having an independent impurity concentration peak is formed below the p-type base layer 15 (step S4).

[0038] In the steps of step S2 to S4, n + The n-type source layer 13, the p-type base layer 15, and the n-type carrier accumulation layer 2 are n + The junction between the n-type source layer 13 and the p-type base layer 15 and the junction between the p-type base layer 15 and the n-type carrier accumulation layer 2 are formed so as to be included in the p-type CSC layer 50 formed in step S1. Note that the execution order of steps S2, S3, and S4 is not limited.

[0039] Thereafter, a heat treatment for activating the impurities implanted into each of the n-type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the p-type CSC layer 50 is performed (step S5). +

[0040] Through the above steps, the n-type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the p-type CSC layer of the semiconductor device according to Embodiment 1 can be formed. + 50.

[0041] <Embodiment 2> The configuration of the semiconductor device according to Embodiment 2 is basically the same as that of Embodiment 1 (FIG. 1), but the impurity concentration profile of the p-type CSC layer 50 is different from that of Embodiment 1.

[0042] FIG. 4 shows the n-type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the n-type carrier accumulation layer 2 in the semiconductor device according to Embodiment 2. + In the semiconductor device according to Embodiment 2, the n-type source layer 13, the p-type base layer 15, the n-type carrier accumulation layer 2, and the n-type carrier accumulation layer 2 are n -Shows the impurity concentration profiles of the n-type drift layer 1 and the p-type CSC layer 50. As shown in FIG. 4, in Embodiment 2, in the region where the second impurity-containing region of the p-type base layer 15 overlaps with the third impurity-containing region of the n-type carrier accumulation layer 2, the concentration of the fourth impurity in the p-type CSC layer 50 is higher than the concentration of the second impurity and the concentration of the third impurity.

[0043] According to the semiconductor device according to Embodiment 2, since the variation in the depth of the junction between the p-type base layer 15 and the n-type carrier accumulation layer 2 is further reduced, the decrease in the RBSOA of the semiconductor device is further suppressed.

[0044] Note that the semiconductor device of Embodiment 2 can be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50 in the manufacturing method of the semiconductor device according to Embodiment 1.

[0045] <Embodiment 3> The semiconductor device according to Embodiment 3 also has basically the same configuration as that of Embodiment 1 (FIG. 1), but the impurity concentration profile of the p-type CSC layer 50 is different from that of Embodiment 1.

[0046] FIG. 5 shows the impurity concentration profiles of the n + type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n - type drift layer 1 and p-type CSC layer 50 in the semiconductor device according to Embodiment 3. As shown in FIG. 5, in Embodiment 3, the fourth impurity-containing region of the p-type CSC layer 50 reaches below the third impurity-containing region of the n-type carrier accumulation layer 2. Therefore, a p-type layer composed of the p-type CSC layer 50 is formed between the n-type carrier accumulation layer 2 and the n - type drift layer 1.

[0047] According to the semiconductor device according to Embodiment 3, since the region between the n-type carrier accumulation layer 2 and the n - type drift layer 1 is separated by a p-type layer, the variation in the local carrier distribution is reduced, which can contribute to the improvement of the RBSOA of the semiconductor device.

[0048] The semiconductor device of Embodiment 3 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50 in the manufacturing method of the semiconductor device according to Embodiment 1.

[0049] <Embodiment 4> The semiconductor device according to Embodiment 4 also has basically the same configuration as that of Embodiment 1 (FIG. 1), but the impurity concentration profile of the p-type CSC layer 50 is different from that of Embodiment 1.

[0050] FIG. 6 shows the impurity concentration profiles of the n + type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n - type drift layer 1 and p-type CSC layer 50 in the semiconductor device according to Embodiment 4. As shown in FIG. 6, in Embodiment 4, the position of the concentration peak of the fourth impurity in the p-type CSC layer 50 is located below the position of the concentration peak of the third impurity in the n-type carrier accumulation layer 2.

[0051] According to the semiconductor device of Embodiment 4, the variation in the impurity concentration gradient at the junction between the n-type carrier accumulation layer 2 and the n - type drift layer 1 is reduced, and thereby an effect of reducing the variation in the saturation voltage (Vsat) (on-voltage) of the semiconductor device can be expected.

[0052] The semiconductor device of Embodiment 4 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50 in the manufacturing method of the semiconductor device according to Embodiment 1.

[0053] <Embodiment 5> The semiconductor device according to Embodiment 5 also has basically the same configuration as that of Embodiment 1 (FIG. 1), but the impurity concentration profile of the p-type CSC layer 50 is different from that of Embodiment 1.

[0054] FIG. 7 shows the n +Type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n - shows the impurity concentration profiles of the n-type drift layer 1 and the p-type CSC layer 50. Similar to Embodiment 4, the position of the concentration peak of the fourth impurity in the p-type CSC layer 50 is located below the position of the concentration peak of the third impurity in the n-type carrier accumulation layer 2. As shown in FIG. 7, in Embodiment 5, the tail portion (the trailing portion) in the concentration profile of the fourth impurity in the p-type CSC layer 50 reaches below the third impurity-containing region of the n-type carrier accumulation layer 2.

[0055] According to the semiconductor device according to Embodiment 5, both the effects of Embodiment 3 and the effects of Embodiment 4 can be obtained. That is, both the effect of improving the RBSOA of the semiconductor device and the effect of reducing the variation in the saturation voltage can be obtained.

[0056] The semiconductor device of Embodiment 5 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50 in the manufacturing method of the semiconductor device according to Embodiment 1.

[0057] <Embodiment 6> The semiconductor device according to Embodiment 6 also has basically the same configuration as that of Embodiment 1 (FIG. 1), but the impurity concentration profile of the p-type CSC layer 50 is different from that of Embodiment 1.

[0058] FIG. 8 shows the n- + type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, n - shows the impurity concentration profiles of the type drift layer 1 and the p-type CSC layer 50. As shown in FIG. 8, in Embodiment 6, the position of the concentration peak of the fourth impurity in the p-type CSC layer 50 is located below the third impurity-containing region of the n-type carrier accumulation layer 2.

[0059] Also in the semiconductor device according to Embodiment 6, both the effects of Embodiment 3 and the effects of Embodiment 4 can be obtained. Further, compared with Embodiment 6, since the peak concentration distribution of the fourth impurity in the p-type CSC layer 50 becomes constant, it can further contribute to both the improvement of the RBSOA of the semiconductor device and the reduction of the variation in the saturation voltage.

[0060] The semiconductor device according to Embodiment 6 can also be formed by changing the conditions of ion implantation and heat treatment for forming the p-type CSC layer 50 in the manufacturing method of the semiconductor device according to Embodiment 1.

[0061] <Embodiment 7> FIG. 9 is a diagram showing the configuration of a semiconductor device according to Embodiment 7, and is a cross-sectional view of the IGBT region 10 and the diode region 20 of an RC-IGBT. The configuration of the IGBT region 10 of the semiconductor device according to Embodiment 7 is the same as that of Embodiment 3. That is, the region containing the fourth impurity in the p-type CSC layer 50 reaches below the region containing the third impurity in the n-type carrier accumulation layer 2. Therefore, a p-type layer made of the p-type CSC layer 50 is formed between the n-type carrier accumulation layer 2 and the n - type drift layer 1.

[0062] Next, the diode region 20 will be described. As shown in FIG. 9, a diode trench gate 21 is provided in the diode region 20. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a faces the n - type drift layer 1 via the diode trench insulating film 21b. Between two adjacent diode trench gates 21, a p + type contact layer 24 and a p-type anode layer 25 are provided.

[0063] p + type contact layer 24 and the p-type anode layer 25 are semiconductor layers having, for example, boron or aluminum as a p-type impurity. p +The concentration of p-type impurities in the p-type contact layer 24 is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 is. The concentration of p-type impurities in the p-type anode layer 25 is set lower than that of the p + type contact layer 24, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 is. The p + type contact layer 24 and the p-type anode layer 25 may be alternately provided along the extending direction of the diode trench gate 21.

[0064] The semiconductor device also has an n - type drift layer 1 made of a semiconductor substrate in the diode region 20, similar to the IGBT region 10. The n - type drift layer 1 in the diode region 20 and the n - type drift layer 1 in the IGBT region 10 are continuously and integrally formed and are composed of the same semiconductor substrate. In FIG. 9, the semiconductor substrate is in the range from the p + type contact layer 24 to the n + type cathode layer 26. In FIG. 9, the upper end of the p + type contact layer 24 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the n + type cathode layer 26 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface.

[0065] As shown in FIG. 9, also in the diode region 20, similar to the IGBT region 10, an n - type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n -An n-type buffer layer 3 is provided on the second main surface side of the type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that it is not always necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Also, similar to the IGBT region 10, n - The type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0066] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is provided between the n - type drift layer 1 and the first main surface. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 in the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously (i.e., in the same process). Also, the p-type impurity concentration of the p-type anode layer 25 may be made lower than the p-type impurity concentration of the p-type base layer 15 in the IGBT region 10 so as to reduce the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0067] In this embodiment, it is assumed that the p-type anode layer 25 is formed simultaneously with the p-type base layer 15. Therefore, the p-type anode layer 25 is located in the surface layer portion of the semiconductor layer and has the same impurity concentration profile as the p-type base layer 15. The impurity concentration profiles being "the same" does not necessarily mean completely identical, and substantially identical is sufficient.

[0068] A p + type contact layer 24 is provided on the first main surface side of the p-type anode layer 25. p + The p-type impurity concentration of the type contact layer 24 may be the same as the p-type impurity of the p-type contact layer 14 in the IGBT region 10, or may be different. +

[0069] ​ In this embodiment, p + type contact layer 24 is formed simultaneously with p + type contact layer 14. Therefore, p + type contact layer 24 is located in the surface layer portion of the semiconductor layer and has the same impurity concentration profile as p + type contact layer 14.

[0070] p-type anode layer 25 and p + type contact layer 24 constitute the first main surface of the semiconductor substrate. Note that p + type contact layer 24 is a region with a higher concentration of p-type impurities than p-type anode layer 25. When it is necessary to distinguish between p + type contact layer 24 and p-type anode layer 25, they may be individually named. p + type contact layer 24 and p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0071] In diode region 20, an n + type cathode layer 26 is provided on the second main surface side of n-type buffer layer 3. n + type cathode layer 26 is provided between n - type drift layer 1 and the second main surface. n + type cathode layer 26 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 . n + type cathode layer 26 is provided in part or all of diode region 20. n + type cathode layer 26 constitutes the second main surface of the semiconductor substrate.

[0072] In FIG. 9, p-type collector layer 16 provided on the second main surface side of IGBT region 10 protrudes toward diode region 20 by a distance U1 from the boundary between IGBT region 10 and diode region 20. Thus, by providing p-type collector layer 16 to protrude into diode region 20, the n +The distance between the p-type cathode layer 26 and the active trench gate 11 can be increased. Even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, current flowing from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the p + -type cathode layer 26 can be suppressed. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or 101 which is an RC-IGBT, the distance U1 may be zero or less than 100 μm.

[0073] Also, although not shown, in the region where the p + -type cathode layer 26 is formed, p-type impurities may be selectively implanted further to provide a p-type cathode layer with a part of the region where the p + -type cathode layer 26 is formed as a p-type semiconductor.

[0074] The diode trench gate 21 penetrates the p-type anode layer 25 and the n-type carrier accumulation layer 2 from the first main surface of the semiconductor substrate and reaches the n - -type drift layer 1. The diode trench electrode 21a faces the p-type anode layer 25, the n-type carrier accumulation layer 2, and the n - -type drift layer 1 via the diode trench insulating film 21b.

[0075] A barrier metal 5 is provided on the diode trench electrode 21a and the p + -type contact layer 24. The barrier metal 5 makes an ohmic contact with the diode trench electrode 21a and the p + -type contact layer 24, and the diode trench electrode and the p +It is electrically connected to the type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. Note that, similar to the case of the IGBT region 10, without providing the barrier metal 5, the diode trench electrode 21a and the p + type contact layer 24 and the emitter electrode 6 may be in ohmic contact. In FIG. 9, a diagram is shown in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0076] n + A collector electrode 7 is provided on the second main surface side of the n-type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 in the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n + type cathode layer 26 and is electrically connected to the n + type cathode layer 26.

[0077] In addition to the above configuration, the semiconductor device according to Embodiment 7 has a configuration in which the p-type CSC layer 50 also extends into the diode region 20. The configuration of the IGBT region 10 is the same as that in Embodiment 3, and the fourth impurity-containing region of the p-type CSC layer 50 reaches below the third impurity-containing region of the n-type carrier accumulation layer 2. Therefore, also in the diode region 20, the fourth impurity-containing region of the p-type CSC layer 50 reaches below the third impurity-containing region of the n-type carrier accumulation layer 2.

[0078] According to the semiconductor device according to Embodiment 7, in addition to the effects of Embodiment 3, an effect that the anode injection efficiency in the diode region 20 can be adjusted by the p-type CSC layer 50 extending in the diode region 20 is obtained.

[0079] <Embodiment 8> FIG. 10 is a diagram showing the configuration of a semiconductor device according to Embodiment 8, and is a cross-sectional view of the IGBT region 10 and the diode region 20 of an RC-IGBT. The configuration of the IGBT region 10 of the semiconductor device according to Embodiment 8 is also the same as that of Embodiment 3.

[0080] In the semiconductor device according to Embodiment 8, the p-type anode layer 25 of the diode region 20 is formed simultaneously with the p-type CSC layer 50. That is, the p-type anode layer 25 is formed by ion-implanting a fourth impurity into the semiconductor substrate and then diffusing the fourth impurity by heat treatment. Therefore, the p-type anode layer 25 is located in the surface layer portion of the semiconductor layer and has the same concentration profile of the second impurity as the p-type CSC layer 50.

[0081] Further, the diode region 20 of the semiconductor device according to Embodiment 8 includes, in addition to the region where the p-type anode layer 25 is formed in the surface layer portion of the semiconductor layer, a Schottky region 60 which is a region where the emitter electrode 6 is Schottky-connected to the n - type drift layer 1. That is, the diode region 20 functions as an MPS (Merged PiN Schottky) diode having an MPS structure including a PN junction diode and a Schottky barrier diode. Hereinafter, an RC-IGBT in which the diode region 20 functions as an MPS diode is referred to as an "MPS-RC-IGBT".

[0082] According to the semiconductor device according to Embodiment 8, the p-type CSC layer 50 can be formed simultaneously with the p-type anode layer 25 of the diode region 20. Therefore, it is not necessary to increase the manufacturing process to add the p-type CSC layer 50 to the IGBT region 10.

[0083] <Embodiment 9> FIG. 10 is a diagram showing the configuration of the semiconductor device according to Embodiment 9, and is a cross-sectional view of the IGBT region 10 and the diode region 20 of the RC-IGBT. The configuration of the IGBT region 10 of the semiconductor device according to Embodiment 9 is the same as that of Embodiment 3. Further, the diode region 20 includes a Schottky region 60 and functions as an MPS diode, as in Embodiment 8.

[0084] In the semiconductor device according to Embodiment 9, the diode region 20 is provided with a Schottky adjustment layer 61 having locally different n-type impurity concentrations on the surface layer portion of the n-type drift layer 1 of the Schottky region 60. Further, the p-type CSC layer 50 extends also to the Schottky region 60. - In the semiconductor device according to Embodiment 9, the diode region 20 is provided with a Schottky adjustment layer 61 having locally different n-type impurity concentrations on the surface layer portion of the n-type drift layer 1 of the Schottky region 60. Further, the p-type CSC layer 50 extends also to the Schottky region 60.

[0085] According to the semiconductor device according to Embodiment 9, the characteristics of the Schottky region 60 of the MPS-RC-IGBT can be adjusted.

[0086] It should be noted that the respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or omitted.

[0087] <Supplementary Note> Hereinafter, aspects of the present disclosure will be collectively described as supplementary notes.

[0088] (Supplementary Note 1) A source layer of a first conductivity type located in the surface layer portion of the semiconductor layer and defined by the concentration profile of the first impurity, A base layer of a second conductivity type located below the source layer and defined by the concentration profile of the second impurity, A carrier accumulation layer of the first conductivity type located below the base layer and defined by the concentration profile of the third impurity, The drift layer of the first conductivity type located below the carrier accumulation layer, A CSC layer of the second conductivity type defined by the concentration profile of the fourth impurity, wherein the region containing the fourth impurity includes a region where the region containing the second impurity of the base layer and the region containing the third impurity of the carrier accumulation layer overlap. A semiconductor device comprising

[0089] (Appendix 2) In a region where the region containing the second impurity of the base layer overlaps with the region containing the third impurity of the carrier accumulation layer, the concentration of the fourth impurity in the CSC layer is higher than the concentration of the second impurity and the concentration of the third impurity. The semiconductor device according to Appendix 1.

[0090] (Appendix 3) The region containing the fourth impurity in the CSC layer includes a region where the region containing the first impurity in the source layer overlaps with the region containing the second impurity in the base layer. The semiconductor device according to Appendix 1 or Appendix 2.

[0091] (Appendix 4) The region containing the fourth impurity in the CSC layer reaches below the region containing the third impurity in the carrier accumulation layer. The semiconductor device according to any one of Appendices 1 to 3.

[0092] (Appendix 5) The position of the peak concentration of the fourth impurity in the CSC layer is located below the position of the peak concentration of the third impurity in the carrier accumulation layer. The semiconductor device according to any one of Appendices 1 to 3.

[0093] (Appendix 6) The tail portion in the concentration profile of the fourth impurity in the CSC layer reaches below the region containing the third impurity in the carrier accumulation layer. The semiconductor device according to Appendix 5.

[0094] (Appendix 7) The position of the peak concentration of the fourth impurity in the CSC layer is located below the region containing the third impurity in the carrier accumulation layer. The semiconductor device according to Appendix 5 or Appendix 6.

[0095] (Appendix 8) the semiconductor layer further includes a diode region that functions as a diode; the diode region is located in a surface layer portion of the semiconductor layer and includes an anode layer of the second conductivity type having the same concentration profile of the second impurity as the base layer; the carrier accumulation layer, the drift layer, and the CSC layer also extend into the diode region; 5. The semiconductor device according to claim 4.

[0096] (Appendix 9) the semiconductor layer further includes a diode region that functions as a diode; the drift layer also extends into the diode region; The diode region is a region in which the second conductivity type anode layer is formed, the region being located in a surface layer portion of the semiconductor layer and having the same concentration profile of the fourth impurity as the CSC layer; a Schottky region in which an electrode provided on the semiconductor layer is connected to the drift layer by a Schottky junction; Equipped with 5. The semiconductor device according to claim 4.

[0097] (Appendix 10) the semiconductor layer further includes a diode region that functions as a diode; the drift layer also extends into the diode region; The diode region is a region in which the second conductivity type anode layer is formed on a surface layer portion of the semiconductor layer; a Schottky region in which an electrode provided on the semiconductor layer is connected to the drift layer by a Schottky junction; Equipped with The CSC layer also extends to the Schottky region. 5. The semiconductor device according to claim 4.

[0098] (Appendix 11) (a) ion-implanting a fourth impurity into a semiconductor layer and diffusing the fourth impurity by heat treatment to form a CSC layer of a second conductivity type in the semiconductor layer; (b) forming a source layer of a first conductivity type in a surface layer portion of the semiconductor layer by ion-implanting a first impurity into the semiconductor layer; (c) ion-implanting a second impurity into the semiconductor layer to form the second conductivity type base layer located below the source layer; (d) forming a carrier accumulation layer of the first conductivity type located below the base layer by ion-implanting a third impurity into the semiconductor layer; Equipped with the steps (b), (c), and (d) are carried out after the step (a); In the steps (b), (c), and (d), the source layer, the base layer, and the carrier accumulation layer are formed such that a junction between the source layer and the base layer and a junction between the base layer and the carrier accumulation layer are included in the CSC layer formed in the step (a). A method for manufacturing a semiconductor device. [Explanation of symbols]

[0099] 1n - 1. n-type drift layer, 2. n-type carrier accumulation layer, 3. n-type buffer layer, 4. interlayer insulating film, 5. barrier metal, 6. emitter electrode, 7. collector electrode, 10. IGBT region, 11. active trench gate, 11a. gate trench electrode, 11b. gate trench insulating film, 12. dummy trench gate, 12a. dummy trench electrode, 12b. dummy trench insulating film, 13. n + Mold source layer, 14p + 16a p-type collector termination layer; 20 diode region; 21 diode trench gate; 21a diode trench electrode; 21b diode trench insulating film; 24 p + p-type contact layer, 25 p-type anode layer, 26 n +50 p-type cathode layer, 51 p-type CSC layer, 60 Schottky region, 61 Schottky adjustment layer.

Claims

1. A source layer of a first conductivity type, which is located in the surface layer portion of the semiconductor layer and is defined by the concentration profile of a first impurity; A base layer of a second conductivity type, which is located below the source layer and is defined by the concentration profile of a second impurity; A carrier accumulation layer of the first conductivity type, which is located below the base layer and is defined by the concentration profile of a third impurity; A drift layer of the first conductivity type, which is located below the carrier accumulation layer; A CSC layer of the second conductivity type, which is defined by the concentration profile of a fourth impurity, and the region containing the fourth impurity is located such that it includes the region where the region containing the second impurity in the base layer and the region containing the third impurity in the carrier accumulation layer overlap; A semiconductor device comprising the above.

2. In the region where the region containing the second impurity in the base layer and the region containing the third impurity in the carrier accumulation layer overlap, the concentration of the fourth impurity in the CSC layer is higher than the concentration of the second impurity and the concentration of the third impurity. The semiconductor device according to Claim 1.

3. The region containing the fourth impurity in the CSC layer includes the region where the region containing the first impurity in the source layer and the region containing the second impurity in the base layer overlap. The semiconductor device according to Claim 1 or Claim 2.

4. The region containing the fourth impurity in the CSC layer reaches below the region containing the third impurity in the carrier accumulation layer. The semiconductor device according to Claim 1 or Claim 2.

5. The position of the concentration peak of the fourth impurity in the CSC layer is located below the position of the concentration peak of the third impurity in the carrier accumulation layer. The semiconductor device according to Claim 1 or Claim 2.

6. The tail portion in the concentration profile of the fourth impurity in the CSC layer reaches below the region containing the third impurity in the carrier accumulation layer. The semiconductor device according to Claim 5.

7. The position of the concentration peak of the fourth impurity in the CSC layer is located below the region containing the third impurity in the carrier accumulation layer. The semiconductor device according to Claim 5.

8. The semiconductor layer further includes a diode region that functions as a diode. The diode region is located in the surface layer portion of the semiconductor layer and includes an anode layer of the second conductivity type having the same concentration profile of the second impurity as that of the base layer. The carrier accumulation layer, the drift layer, and the CSC layer also extend into the diode region. The semiconductor device according to claim 4.

9. The semiconductor layer further includes a diode region that functions as a diode. The drift layer also extends into the diode region. The diode region is a region located in the surface layer portion of the semiconductor layer, where a p-type anode layer having the same concentration profile of the fourth impurity as that of the CSC layer is formed, and a Schottky region that is a region where an electrode provided on the semiconductor layer makes a Schottky connection to the drift layer. comprises The semiconductor device according to claim 4.

10. The semiconductor layer further includes a diode region that functions as a diode. The drift layer also extends into the diode region. The diode region is a region where a p-type anode layer is formed in the surface layer portion of the semiconductor layer, and a Schottky region that is a region where an electrode provided on the semiconductor layer makes a Schottky connection to the drift layer. comprises The CSC layer also extends into the Schottky region. The semiconductor device according to claim 4.

11. (a) A step of forming a p-type CSC layer in the semiconductor layer by ion implanting a fourth impurity into the semiconductor layer and diffusing the fourth impurity by heat treatment; (b) A step of forming an n-type source layer in the surface layer portion of the semiconductor layer by ion implanting a first impurity into the semiconductor layer; (c) A step of forming a p-type base layer located below the source layer by ion implanting a second impurity into the semiconductor layer; (d) A step of forming an n-type carrier accumulation layer located below the base layer by ion implanting a third impurity into the semiconductor layer. comprises Steps (b), (c), and (d) are performed after step (a), and in steps (b), (c), and (d), the source layer, the base layer, and the carrier accumulation layer are formed such that the junction between the source layer and the base layer and the junction between the base layer and the carrier accumulation layer are included in the CSC layer formed in step (a). A method for manufacturing a semiconductor device.

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