Power mosfet having gate source ESD diode structure

Abstract

To provide a power metal oxide semiconductor field effect transistor (MOSFET) having a gate source electrostatic discharge (ESD) diode structure and a high voltage resistance and leakage prevention structure.SOLUTION: A power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, 706, a body having first and second body regions 802, 804, a source having first and second source regions 912, 914, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, 953, a gate contact plug 954, a gate source ESD diode structure 929 connected between the gate contact and the source contact, a source contact 962, a gate contact 964, a drain contact 966, and a body ring structure 820 formed under the gate source ESD diode structure, functioning as a high voltage resistance and leakage prevention structure.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001]

[0001] Embodiments of the present invention relate to a power metal-oxide-semiconductor field-effect transistor (MOSFET), and in certain embodiments, to a power MOSFET having a gate-source ESD diode structure and a high breakdown voltage and leakage prevention structure.

Background Art

[0002]

[0002] As semiconductor technology has evolved, power MOSFETs have been widely used in various industrial applications. A power MOSFET is a voltage-controlled device. When a control voltage is applied to the gate of the power MOSFET and the control voltage is greater than the threshold value of the power MOSFET, a conductive channel is established between the drain and the source of the power MOSFET. As a result, a current flows between the drain and source of the power MOSFET. On the other hand, when the control voltage is less than the threshold value of the power MOSFET, the power MOSFET turns off accordingly.

[0003]

[0003] Power MOSFETs can be included in two main categories. One is an n-channel power MOSFET. The other is a p-channel power MOSFET. Depending on the structural differences, power MOSFETs can be further divided into three subcategories: planar power MOSFETs, lateral power MOSFETs, and vertical power MOSFETs.

[0004]

[0004] Vertical power MOSFETs are widely used in high-voltage and high-current applications because they have low gate drive power, fast switching speed, and low on-resistance. In a vertical power MOSFET, the drain and source are arranged on both sides of the wafer. A trench structure may be formed between the drain and source of the vertical power MOSFET.

[0005]

[0005] The input / output terminals of a vertical power MOSFET must be protected from electrostatic discharge (ESD) voltages. For example, the gate of a vertical power MOSFET is a critical element. An excessive voltage at the gate relative to the source can cause breakdown and damage. To protect the gate of a vertical power MOSFET from ESD, a back-to-back ESD diode structure can be connected between the gate terminal and the source terminal of the vertical power MOSFET. The back-to-back ESD diode structure may be implemented as an array of alternately arranged doped p and n+ regions. For example, the array can include a first p-type region, a first n+ region, a second p-type region, a second n+ region, and a third p-type region connected in cascade. Alternatively, the array can include a first n+ region, a first p-type region, a second n+ region, a second p-type region, and a third n+ region connected in cascade. The p-n+ structure is a common configuration for ESD protection diodes. The p-n+ structure has a low breakdown voltage and helps create a structure suitable for clamping and diverting excessive voltages during an ESD event in the ESD diode structure, thereby preventing the gate of the vertical power MOSFET from being damaged.

Summary of the Invention

[0006]

[0006] By a preferred embodiment of the present disclosure that provides a power MOSFET having a gate-source ESD diode structure as well as a high breakdown voltage and leakage prevention structure, these and other problems are generally solved or avoided, and technical advantages are generally achieved.

[0007]

[0007] According to one embodiment, the device includes a drain and a source on both sides of an epitaxial layer, a plurality of gates formed within the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode structure connected between the gate contact and the source contact, and a high breakdown voltage and leakage prevention structure formed under the gate-source ESD diode structure.

[0008]

[0008] According to another embodiment, the method includes growing an epitaxial layer on a substrate, forming a plurality of gates in the epitaxial layer, forming a body region and a high-voltage-resistant and leakage-preventing structure in the epitaxial layer, forming a source in the epitaxial layer and a gate-source ESD diode structure on the epitaxial layer, and forming a source contact connected to a first terminal of the source and the gate-source ESD diode structure, and a gate contact connected to a second terminal of the plurality of gates and the gate-source ESD diode structure.

[0009]

[0009] According to yet another embodiment, the power MOSFET includes an epitaxial layer on a substrate, a plurality of gates formed in the epitaxial layer, a body region formed in the epitaxial layer, a source formed in the body region, a gate-source ESD diode structure formed on the epitaxial layer, a body ring structure formed under the gate-source ESD diode structure in the epitaxial layer, an interlayer insulating layer formed on the epitaxial layer, wherein the gate-source ESD diode structure is in the interlayer insulating layer, a plurality of source contact plugs, at least one of the plurality of source contact plugs extending through the interlayer insulating layer, the source, and partially through the body region, a gate contact plug extending partially through the interlayer insulating layer, a gate contact connected to a first terminal of the plurality of gates and the gate-source ESD diode structure through the gate contact plug, and a source contact connected to a second terminal of the source, the body region, and the gate-source ESD diode structure through the plurality of source contact plugs.

[0010]

[0010] In the above, the features and technical advantages of the present disclosure have been outlined rather broadly so that the following detailed description of the present disclosure can be better understood. Further features and advantages of the present disclosure, which form the subject of the claims of the present disclosure, are described below. It should be understood by those skilled in the art that the disclosed concepts and specific embodiments can be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Also, it should be understood by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure as set forth in the appended claims.

[0011]

[0011] To more fully understand the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0012]

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[0013]

[0043] Identical numerals and symbols in different drawings generally refer to corresponding parts, unless otherwise indicated. The drawings are drawn to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale.

[0014]

[0044] The fabrication and use of presently preferred embodiments will be described in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific situations. The specific embodiments described are merely illustrative of specific ways to make and use the present disclosure and do not limit the scope of the present disclosure.

[0015]

[0045] The present disclosure is described with respect to preferred embodiments in a particular situation, namely, a power MOSFET having a gate-source ESD diode structure and a high breakdown voltage and leakage prevention structure. However, the present disclosure can also be applied to various power transistors. Various embodiments will be described in detail hereinafter with reference to the accompanying drawings.

[0016]

[0046] FIG. 1 shows a cross-sectional view of a gate-source ESD diode structure and a power MOSFET having a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, and 706, a body including a first body region 802 and a second body region 804, a source including a first source region 912 and a second source region 914, a body ring structure 820, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, and 953, a gate contact plug 954, a gate-source ESD diode structure 929, a source contact 962, a gate contact 964, and a drain contact 966.

[0017]

[0047] As shown in FIG. 1, the epitaxial layer 104 is formed on the substrate 102. A plurality of gates 702, 704, 706 are formed in the epitaxial layer 104. The first body region 802 is formed in the epitaxial layer 104 between the gate 702 and the gate 704. The second body region 804 is formed in the epitaxial layer 104 between the gate 704 and the gate 706. It should be noted that the body regions 802 and 804 may be two separate regions from the cross-sectional view shown in FIG. 1, but the body regions 802 and 804 may also be part of a continuous body region in a top view.

[0018]

[0048] As shown in FIG. 1, the first source region 912 is formed in the first body region 802 between the gates 702 and 704. The second source region 914 is formed in the second body region 804 between the gates 704 and 706. It should be noted that the source regions 912 and 914 may be two separate regions from the cross-sectional view shown in FIG. 1, but the source regions 912 and 914 may also be part of a continuous source region in a top view.

[0019]

[0049] The interlayer insulating layer 920 is formed on the epitaxial layer 104. The gate-source ESD diode structure 929 is formed in the interlayer insulating layer 920 on the epitaxial layer. The gate-source ESD diode structure 929 includes a plurality of n+ regions and a plurality of p-type regions arranged alternately. In some embodiments, the gate-source ESD diode structure 929 includes a first p-type region 921, a first n+ region 922, a second p-type region 923, a second n+ region 924, and a third p-type region 925 connected in cascade. The first p-type region 921 is connected to the gate contact 964. The third p-type region 925 is connected to the source contact 962.

[0020]

[0050] The body ring structure 820 is formed in the epitaxial layer 104 under the gate-source ESD diode structure 929. From the cross-sectional view shown in FIG. 1, the body ring structure 820 includes four pillars 822, 824, 826, and 828. In some embodiments, the body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104 when viewed from above.

[0021]

[0051] The body ring structure 820 functions as a high-voltage-resistant and leakage-preventing structure. During operation, the body ring structure 820 is configured to disperse an electric field on the gate-source ESD diode structure 929. The body ring structure 820 provides an electric field gradient that reduces the peak electric field at the edge of the gate-source ESD diode structure 929, thereby spreading the electric field more uniformly. As a result, the breakdown voltage of the power MOSFET 100 can be improved, and the leakage of the power MOSFET 100 can be reduced.

[0022]

[0052] As shown in FIG. 1, the source contact plug 951 penetrates the interlayer insulating layer 920 and the first source region 912, and extends partially through the first body region 802. The first terminal of the source contact plug 951 is connected to the source contact 962. The second terminal of the source contact plug 951 is connected to the first p+ region 942 formed in the first body region 802.

[0023]

[0053] The source contact plug 952 penetrates the interlayer insulating layer 920 and the second source region 914, and extends partially through the second body region 804. The first terminal of the source contact plug 952 is connected to the source contact 962. The second terminal of the source contact plug 952 is connected to the second p+ region 944 formed in the second body region 804.

[0024]

[0054] The source contact plug 953 penetrates the interlayer insulating layer 920 partially and the third p-type region 925 partially, and extends. The first terminal of the source contact plug 953 is connected to the source contact 962. The second terminal of the source contact plug 953 is connected to the fourth p+ region 948 formed in the third p-type region 925.

[0025]

[0055] The gate contact plug 954 penetrates the interlayer insulating layer 920 partially and the first p-type region 921 partially, and extends. The first terminal of the gate contact plug 954 is connected to the gate contact 964. The second terminal of the gate contact plug 954 is connected to the third p+ region 946 formed in the first p-type region 921.

[0026]

[0056] In some embodiments, the power MOSFET shown in FIG. 1 can be implemented as an n-type power MOSFET. The substrate 102 is an n+ substrate. The epitaxial layer 104 is an n-type layer. The doping concentration of the epitaxial layer 104 is lower than that of the substrate 102. The body region is a p-type region. The source is an n+ region. The body ring structure 820 is a p-type body ring structure. The n-type regions in FIG. 1 (e.g., source regions 912 and 914) are formed by implanting n-type dopants such as phosphorus and arsenic. Alternatively, the n-type regions can be formed by diffusion processing. The p-type regions in FIG. 1 (e.g., body regions 802 and 804) are formed by implanting p-type doping materials such as boron, gallium, aluminum, indium, and combinations thereof. Alternatively, the p-type regions can be formed by diffusion processing.

[0027]

[0057] In an alternative embodiment, the power MOSFET shown in FIG. 1 can be implemented as a p-type power MOSFET. The substrate 102 is a p+ substrate. The epitaxial layer 104 is a p-type layer. The doping concentration of the epitaxial layer 104 is lower than that of the substrate 102. The body region is an n-type region. The source is a p+ region. The body ring structure 820 is an n-type body ring structure.

[0028]

[0058] As shown in FIG. 1, the drain contact 966 is formed under the substrate 102. In other words, the source contact 962 and the drain contact 966 of the power MOSFET 100 are fabricated on opposite sides of the wafer.

[0029]

[0059] FIGS. 2-16 show cross-sectional views of intermediate steps in manufacturing the power MOSFET shown in FIG. 1 according to various embodiments of the present disclosure.

[0030]

[0060] Figure 2 shows a cross-sectional view of a semiconductor device after growing an epitaxial layer from a substrate according to various embodiments of the present disclosure. According to one embodiment, the substrate 102 may be an n+ substrate doped with n-type impurities such as phosphorus and arsenic.

[0031]

[0061] An n-type epitaxial layer 104 is grown from the substrate 102. The epitaxial growth of the n-type epitaxial layer 104 can be carried out by using an appropriate semiconductor manufacturing process such as chemical vapor deposition (CVD) or ultra-high vacuum chemical vapor deposition (UHV-CVD).

[0032]

[0062] Figure 3 shows a cross-sectional view of the semiconductor device shown in Figure 2 after an etching process is performed on the hard mask layer to define a pattern of the hard mask layer according to various embodiments of the present disclosure. According to one embodiment, using an appropriate manufacturing technique such as CVD, the hard mask layer 106 is deposited on the epitaxial layer 104. The hard mask layer 106 can be formed of an appropriate material such as silicon nitride. The hard mask layer 106 functions as an etching mask.

[0033]

[0063] A photoresist layer 108 is formed on the hard mask layer 106 by using a spin coating method or the like. The photoresist layer 108 is patterned using an appropriate photolithography technique. Thereafter, the hard mask layer 106 is patterned in consideration of the positions of the plurality of gates 702, 704, and 706 of the power MOSFET 100 shown in Figure 1.

[0034]

[0064] Figure 4 shows a cross-sectional view of the semiconductor device shown in FIG. 3 after three trenches are formed in the epitaxial layer according to various embodiments of the present disclosure. The remaining photoresist layer 108 shown in FIG. 3 can be removed by using appropriate photoresist stripping techniques such as chemical solvent cleaning, plasma ashing, dry stripping, etc. Photoresist stripping techniques are well-known and thus will not be described in further detail herein to avoid repetition. Thereafter, an etching process such as reactive ion etching (RIE) or other dry etching, anisotropic wet etching, or any other appropriate anisotropic etching or patterning process is performed to form three trenches, namely a first trench 402, a second trench 404, and a third trench 406, in the epitaxial layer 104 as shown in FIG. 4.

[0035]

[0065] Figure 5 shows a cross-sectional view of the semiconductor device shown in FIG. 4 after a thin dielectric layer is formed in the trenches and on the epitaxial layer according to various embodiments of the present disclosure. As shown in FIG. 5, the hard mask layer 106 shown in FIG. 4 has been removed by an appropriate hard mask layer removal process such as a wet etching process. The removal process is applied to the upper surface of the semiconductor device until the epitaxial layer 104 is exposed.

[0036]

[0066] The thin dielectric layer 502 is a gate dielectric layer. As shown in FIG. 5, the thin dielectric layer 502 is formed on the bottoms and sidewalls of the trenches 402, 404, and 406. The thin dielectric layer 502 can be formed of commonly used dielectric materials such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multilayers thereof.

[0037]

[0067] According to one embodiment, the thin dielectric layer 502 is an oxide layer. The thin dielectric layer 502 can be formed by using appropriate heat treatment techniques, wet treatment techniques, or deposition techniques such as physical vapor deposition (PVD), CVD, atomic layer deposition (ALD), etc.

[0038]

[0068] FIG. 6 shows a cross-sectional view of the semiconductor device shown in FIG. 5 after the gate electrode material has been filled in the trenches, according to various embodiments of the present disclosure. The gate electrode material is filled in trenches 402, 404, 406. The gate electrode material also forms a gate electrode layer 602 over the epitaxial layer 104.

[0039]

[0069] In some embodiments, the gate electrode material is polysilicon. According to one embodiment, the polysilicon layer is doped with n-type impurity ions so as to become a gate conductive layer. Phosphorus is used as the n-type impurity ions, but other n-type conductive ions may be used if necessary or desired. The doping of the n-type impurity ions in the polysilicon layer is preferably carried out by a separate doping process of n-type impurity ions after the deposition of the polysilicon layer, or by depositing the polysilicon layer while doping with n-type impurity ions.

[0040]

[0070] An annealing process is performed on the polysilicon layer. The annealing process is used to diffuse the n-type impurity ions into the polysilicon layer. The annealing process can be carried out as a rapid thermal process.

[0041]

[0071] FIG. 7 shows a cross-sectional view of the semiconductor device shown in FIG. 6 after an etch-back process has been performed on the upper surface shown in FIG. 6, according to various embodiments of the present disclosure. A planarization process such as chemical mechanical polishing (CMP) or an etch-back process may be performed to planarize the upper surface of the gate electrode layer 602 until the thin dielectric layer is exposed. Thereafter, a polysilicon oxidation process is performed to form a dielectric layer 710 so as to cover the polysilicon material in the trenches. As shown in FIG. 7, three gates, namely a first gate 702, a second gate 704, and a third gate 706, may be formed in the epitaxial layer after the CMP process.

[0042]

[0072] FIG. 8 shows a cross-sectional view of the semiconductor device shown in FIG. 7 after a body region and a body ring structure are formed in the epitaxial layer according to various embodiments of the present disclosure. The photoresist layer 812 is formed on the upper surface of the semiconductor device using a spin coating method or the like. Considering the position of the body ring structure of the power MOSFET 100 shown in FIG. 1, the photoresist layer 812 is patterned using appropriate photolithography techniques. The body regions 802 and 804, and the body ring structure 820 may be formed on the upper part of the epitaxial layer 104. According to one embodiment, the body regions 802 and 804, and the body ring structure 820 can be formed by implanting an appropriate p-type dopant such as boron, gallium, indium, etc.

[0043]

[0073] In some embodiments, the body ring structure 820 is a concentric ring structure when viewed from above. As shown in the cross-sectional view, the body ring structure 820 has four pillars 822, 824, 826, and 828. In some embodiments, the bottommost surface of the body ring structure 820 is at the same height as the bottommost surface of the body regions 802 and 804, as shown in FIG. 8.

[0044]

[0074] During operation, the body ring structure 820 functions as a high breakdown voltage and leakage prevention structure. The functions of the high breakdown voltage and leakage prevention structure will be described below with respect to FIG. 11.

[0045]

[0075] FIG. 9 shows a cross-sectional view of the semiconductor device shown in FIG. 8 after an ESD bottom dielectric layer and an ESD layer are formed on the epitaxial layer according to various embodiments of the present disclosure. The remaining photoresist layer 812 shown in FIG. 8 can be removed by using appropriate photoresist stripping techniques. Thereafter, the ESD bottom dielectric layer 902 is deposited on the upper surface of the semiconductor device using appropriate deposition techniques such as PVD, CVD, ALD, etc. The ESD bottom dielectric layer 902 may be formed of commonly used dielectric materials such as oxides, nitrides, oxynitrides, high-k materials, combinations thereof, and multilayers thereof.

[0046]

[0076] The ESD layer 904 is deposited on the ESD bottom dielectric layer 902. The ESD layer 904 may be formed of polysilicon. According to one embodiment, the ESD layer 904 is doped with p-type impurity ions such as boron. Doping of the ESD layer 904 with p-type impurity ions is preferably carried out by a separate p-type impurity ion doping process after deposition of the ESD layer 904, or by depositing the ESD layer 904 while doping with p-type impurity ions.

[0047]

[0077] FIG. 10 shows a cross-sectional view of the semiconductor device shown in FIG. 9 after an anisotropic etching process has been applied to the ESD bottom dielectric layer and the ESD layer according to various embodiments of the present disclosure. An etching process has been applied to the semiconductor device. As shown in FIG. 10, portions of the ESD bottom dielectric layer and the ESD layer above the gates 702, 704, and 706 have been removed as a result.

[0048]

[0078] FIG. 11 shows a cross-sectional view of the semiconductor device shown in FIG. 10 after a source region has been formed over a body region and n+ regions have been formed within the ESD layer according to various embodiments of the present disclosure. As shown in FIG. 11, the n+ regions 912 and 914 are formed over the body regions 802 and 804, respectively, by a suitable manufacturing process such as an ion implantation process. According to one embodiment, the n+ regions 912 and 914 can function as the source regions of the power MOSFET 100 shown in FIG. 1. At the same time, n+ regions 922 and 924 are formed within the ESD layer 904 shown in FIG. 10. The n+ regions are formed by implanting a suitable n-type dopant such as phosphorus or arsenic.

[0049]

[0079] As described above with respect to FIG. 9, when the ESD layer 904 is doped with p-type impurity ions, the ESD layer 904 is a p-type layer. Since the n+ regions 922 and 924 are formed within the ESD layer 904, three p-type regions 921, 923, and 925 are formed within the ESD layer 904.

[0050]

[0080] As shown in FIG. 11, the first p-type region 921, the first n+ region 922, the second p-type region 923, the second n+ region 924, and the third p-type region 925 are cascade-connected. The first p-type region 921, the first n+ region 922, the second p-type region 923, the second n+ region 924, and the third p-type region 925 form a gate-source ESD diode structure 929.

[0051]

[0081] As shown in FIG. 11, the n+ regions and the p-type regions are formed alternately. The n+ regions and the p-type regions form a back-to-back ESD diode structure. The arrangement of the n+ regions and the p-type regions described above is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, the back-to-back ESD diode structure can include a first n+ region, a first p-type region, a second n+ region, a second p-type region, and a third n+ region that are cascade-connected.

[0052]

[0082] As shown in FIG. 11, the gate-source ESD diode structure 929 and the body ring structure 820 are separated by an ESD bottom dielectric layer 902. The body ring structure 820 is configured to disperse an electric field over the gate-source ESD diode structure 929. The body ring structure 820 provides an electric field gradient that reduces the peak electric field at the edge of the gate-source ESD diode structure 929, thereby spreading the electric field more uniformly. As a result, the body ring structure 820 can improve the performance of the power MOSFET 100.

[0053]

[0083] FIG. 12 shows a cross-sectional view of the semiconductor device shown in FIG. 11 after a dielectric layer is formed on the epitaxial layer according to various embodiments of the present disclosure. The dielectric layer 920 is deposited on the epitaxial layer 104. The dielectric layer 920 may alternatively be referred to as an interlayer dielectric (ILD) layer. The dielectric layer 920 may be, for example, a low-k dielectric layer having a low dielectric constant of less than about 3.5. The dielectric layer 920 may also comprise a combination of materials such as silicon nitride, silicon oxynitride, high-k dielectrics, low-k dielectrics, CVD polysilicon or other dielectrics. The dielectric layer 920 can be deposited using suitable deposition techniques such as sputtering, CVD, etc.

[0054]

[0084] FIG. 13 shows a cross-sectional view of the semiconductor device shown in FIG. 12 after an anisotropic etching process is performed on the dielectric layer to form a plurality of trenches. By etching the dielectric layer 920 and the region below the dielectric layer 920, a plurality of trenches 932, 934, 936 and 938 are formed.

[0055]

[0085] In some embodiments, trenches 932, 934 and 938 are source contact trenches. As shown in FIG. 13, trench 932 extends through the dielectric layer 920, the source region 912, and partially through the body region 802. Similarly, trench 934 extends through the dielectric layer 920, the source region 914, and partially through the body region 804. Trench 936 extends partially through the dielectric layer 920 and partially through the first p-type region 921. Trench 938 extends partially through the dielectric layer 920 and partially through the third p-type region 925.

[0056]

[0086] FIG. 14 shows a cross-sectional view of the semiconductor device shown in FIG. 13 after p+ regions are formed at the bottom of each trench according to various embodiments of the present disclosure. An appropriate implantation process such as blanket ion implantation is performed. P-type impurity ions such as boron ions are implanted into the body regions 802, 804, the first p-type region 921, and the third p-type region 925. Thus, as shown in FIG. 14, four p+ regions 942, 944, 946, and 948 are respectively formed in the trenches. The p+ regions 942, 944, 946, and 948 are specifically designed to further reduce the contact resistance.

[0057]

[0087] FIG. 15 shows a cross-sectional view of the semiconductor device shown in FIG. 14 after a metal material is filled in the trenches of the semiconductor device according to various embodiments of the present disclosure. A metal material including tungsten, titanium, aluminum, copper, any combination thereof, etc. is filled in the trenches 932, 934, 936, and 938 to form the contact plugs 951, 952, 953, and 954. The metal material on the interlayer insulating layer 920 forms the metal contact layer 950.

[0058]

[0088] FIG. 16 shows a cross-sectional view of the semiconductor device shown in FIG. 15 after source and gate contacts are formed according to various embodiments of the present disclosure. Considering the positions of the source contact and the gate contact of the power MOSFET 100 shown in FIG. 1, the metal contact layer 950 is patterned using an appropriate etching technique.

[0059]

[0089] As shown in FIG. 16, the first source contact plug 951 has a first terminal connected to the source contact 962 and a second terminal connected to the first source region 912, the p+ region 942, and the first body region 802. The second source contact plug 952 has a first terminal connected to the source contact 962 and a second terminal connected to the second source region 914, the p+ region 944, and the second body region 804. The gate contact plug 954 has a first terminal connected to the gate contact 964 and a second terminal connected to the p+ region 946 and the first terminal of the gate-source ESD diode structure 929. The third source contact plug 953 has a first terminal connected to the source contact 962 and a second terminal connected to the p+ region 948 and the second terminal of the gate-source ESD diode structure 929.

[0060]

[0090] FIG. 17 shows a cross-sectional view of a second embodiment of a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The high breakdown voltage and leakage prevention structure of the power MOSFET 200 is implemented as a body ring structure 820 as shown in FIG. 17. The body ring structure 820 shown in FIG. 17 is the same as that shown in FIG. 16 except that the body ring structure 820 shown in FIG. 17 has five pillars 822, 824, 825, 826, and 828.

[0061]

[0091] In some embodiments, one sidewall of the pillar 822 is vertically aligned with one sidewall of the first p-type region 921. One sidewall of the pillar 824 is vertically aligned with one sidewall of the first n+ region 922. One sidewall of the pillar 825 is vertically aligned with one sidewall of the second p-type region 923. One sidewall of the pillar 826 is vertically aligned with one sidewall of the second n+ region 924. One sidewall of the pillar 828 is vertically aligned with one sidewall of the third p-type region 925.

[0062]

[0092] FIG. 17 shows a high-voltage withstand and leakage prevention structure having five pillars 822, 824, 825, 826 and 828, but it should be recognized that the high-voltage withstand and leakage prevention structure can accommodate any number of pillars.

[0063]

[0093] FIG. 18 shows a cross-sectional view of a third embodiment of a high-voltage withstand and leakage prevention structure according to various embodiments of the present disclosure. The high-voltage withstand and leakage prevention structure of the power MOSFET 300 is implemented as a body ring structure 820 as shown in FIG. 18. The body ring structure 820 shown in FIG. 18 is the same as that shown in FIG. 16, except that the four pillars 822, 824, 826 and 828 of the body ring structure 820 are vertically aligned with their respective ESD diode regions.

[0064]

[0094] In some embodiments, one side wall of the pillar 822 is vertically aligned with the first side wall of the first n+ region 922. One side wall of the pillar 824 is vertically aligned with the second side wall of the first n+ region 922. One side wall of the pillar 826 is vertically aligned with the first side wall of the second n+ region 924. One side wall of the pillar 828 is vertically aligned with the second side wall of the second n+ region 924.

[0065]

[0095] FIG. 19 shows a cross-sectional view of a fourth embodiment of a high-voltage withstand and leakage prevention structure according to various embodiments of the present disclosure. The high-voltage withstand and leakage prevention structure of the power MOSFET 400 includes a plurality of n-type wells 974, 976 and a plurality of p-type wells 973, 975 arranged alternately. The plurality of n-type wells and the plurality of p-type wells are configured to disperse an electric field on the gate-source ESD diode structure 929. As shown in FIG. 19, the plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure 929 are separated by a dielectric layer.

[0066]

[0096] The p-n-p-n-p well structure shown in FIG. 19 can achieve a higher level of reliability and durability in the power MOSFET 400, thereby improving the ESD protection design.

[0067]

[0097] The above arrangements of the n-well and p-well are merely examples and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, an n-p-n-p-n well structure can be used to replace the well structure shown in FIG. 19. The n-p-n-p-n well structure completely covers the area under the gate-source ESD diode structure 929. This features a plurality of p-n diodes that improve the electrical characteristics of the power MOSFET 400 and provide stronger protection against ESD events.

[0068]

[0098] FIGS. 20-24 show cross-sectional views of intermediate steps in manufacturing the high breakdown voltage and anti-leakage structure shown in FIG. 19 according to various embodiments of the present disclosure.

[0069]

[0099] FIG. 20 shows a cross-sectional view of a semiconductor device after the gate is covered by a dielectric layer according to various embodiments of the present disclosure. The cross-sectional view shown in FIG. 20 is similar to the cross-sectional view shown in FIG. 7 and thus will not be described again herein to avoid repetition.

[0070]

[0100] FIG. 21 shows a cross-sectional view of the semiconductor device shown in FIG. 20 after body regions are formed in the epitaxial layer according to various embodiments of the present disclosure. The body regions 971, 972, 973 are p-type regions. The p-type regions 971, 972, and 973 are formed in the epitaxial layer 104 by appropriate semiconductor doping techniques such as ion implantation. In some embodiments, an appropriate p-type dopant such as boron, gallium, indium, etc. is implanted into the epitaxial layer 104 to form the body regions 971, 972, and 973. The body region 973 is also alternatively referred to as the first p-type well.

[0071]

[0101] FIG. 22 shows a cross-sectional view of the semiconductor device shown in FIG. 21 after a first n-type well is formed within a first p-type well, according to various embodiments of the present disclosure. A photoresist layer 991 is deposited on the semiconductor device using a spin coating method or the like. The photoresist layer 991 is exposed and developed such that only the portion above the first n-type well 974 is removed.

[0072]

[0102] The first n-type well 974 is formed by implanting an n-type dopant such as phosphorus or arsenic. Alternatively, the first n-type well 974 can be formed by a diffusion process. As shown in FIG. 22, the first n-type well 974 is surrounded by the first p-type well 973.

[0073]

[0103] FIG. 23 shows a cross-sectional view of the semiconductor device shown in FIG. 22 after a second p-type well is formed within the first n-type well, according to various embodiments of the present disclosure. A photoresist layer 992 is deposited on the semiconductor device using a spin coating method or the like. The photoresist layer 992 is exposed and developed such that only the portion above the second p-type well 975 is removed.

[0074]

[0104] The second p-type well 975 is formed by implanting a p-type dopant such as boron, gallium, aluminum, indium, or the like. Alternatively, the second p-type well 975 can be formed by a diffusion process. As shown in FIG. 23, the second p-type well 975 is surrounded by the first n-type well 974.

[0075]

[0105] FIG. 24 shows a cross-sectional view of the semiconductor device shown in FIG. 23 after a second n-type well is formed within the p-type well, according to various embodiments of the present disclosure. A photoresist layer 993 is deposited on the semiconductor device using a spin coating method or the like. The photoresist layer 993 is exposed and developed such that only the portion above the second n-type well 976 is removed.

[0076]

[0106] The second n-type well 976 is formed by implanting an n-type dopant such as phosphorus or arsenic. Alternatively, the second n-type well 976 can be formed by diffusion processing. As shown in FIG. 24, the second n-type well 976 is surrounded by the second p-type well 975.

[0077]

[0107] Those skilled in the art will recognize that FIG. 24 shows an ideal profile. The dimensions of the well may change after subsequent manufacturing processes.

[0078]

[0108] FIG. 25 shows a cross-sectional view of a fifth embodiment of a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The high breakdown voltage and leakage prevention structure of the power MOSFET 500 includes two n-type wells 981 and 983 and one p-type well 982 arranged alternately. The n-type well and the p-type well are configured to disperse an electric field on the gate-source ESD diode structure 929. The n-type well and the p-type well and the gate-source ESD diode structure 929 are separated by a dielectric layer.

[0079]

[0109] As shown in FIG. 25, the first n-type well 981 is formed in the epitaxial layer 104. The first p-type well 982 is formed in the first n-type well 981. The width of the first p-type well 982 is equal to the width of the first n-type well 981. The second n-type well 983 is formed in the first p-type well 982. The width of the second n-type well 983 is equal to the width of the first p-type well 982.

[0080]

[0110] Although FIG. 25 shows a high breakdown voltage and leakage prevention structure having three wells 981, 982, and 983, it should be understood that the high breakdown voltage and leakage prevention structure can accommodate any number of alternately arranged wells.

[0081]

[0111] FIG. 26 shows a cross-sectional view of a sixth embodiment of a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The high breakdown voltage and leakage prevention structure of the power MOSFET 600 is a RESURF (Reduced Surface Field) structure 990. The RESURF structure is a well-known mechanism for improving the breakdown voltage of high-voltage MOSFETs.

[0082]

[0112] As shown in FIG. 26, the RESURF structure 990 is disposed under the gate-source ESD diode structure 929. The RESURF structure 990 and the gate-source ESD diode structure 929 are separated by a dielectric layer. This RESURF structure 990 helps to disperse the electric field on the gate-source ESD diode structure 929, thereby reducing the risk of electrical breakdown and leakage.

[0083]

[0113] FIG. 27 shows a cross-sectional view of a seventh embodiment of a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The high breakdown voltage and leakage prevention structure of the power MOSFET 700 includes a RESURF structure 990 and a body ring structure 820.

[0084]

[0114] The RESURF structure 990 and the body ring structure 820 are configured to disperse the electric field on the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed in the epitaxial layer 104. The RESURF structure 990 and the gate-source ESD diode structure 929 are separated by a dielectric layer. As shown in FIG. 27, the RESURF structure 990 is between the gate-source ESD diode structure 929 and the body ring structure 820.

[0085]

[0115] FIG. 28 shows a cross-sectional view of an eighth embodiment of a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The high breakdown voltage and leakage prevention structure of the power MOSFET 800 includes a plurality of n-type wells, a plurality of p-type wells, and a body ring structure 820. The plurality of n-type wells and the plurality of p-type wells shown in FIG. 28 are the same as those shown in FIG. 19, and thus will not be described again herein.

[0086]

[0116] The plurality of n-type wells and the plurality of p-type wells are arranged alternately. The plurality of n-type wells, the plurality of p-type wells, and the body ring structure 820 are configured to disperse an electric field over the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed within the epitaxial layer 104. The plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure 929 are separated by a dielectric layer. The plurality of n-type wells and the plurality of p-type wells are between the gate-source ESD diode structure 929 and the body ring structure 820.

[0087]

[0117] FIG. 29 shows a cross-sectional view of a ninth embodiment of a high breakdown voltage and leakage prevention structure according to various embodiments of the present disclosure. The high breakdown voltage and leakage prevention structure of the power MOSFET 900 includes a plurality of n-type wells, a plurality of p-type wells, and a body ring structure 820. The plurality of n-type wells and the plurality of p-type wells shown in FIG. 29 are the same as those shown in FIG. 25 and thus will not be described again herein.

[0088]

[0118] The plurality of n-type wells and the plurality of p-type wells are arranged alternately. The plurality of n-type wells, the plurality of p-type wells, and the body ring structure 820 are configured to disperse an electric field over the gate-source ESD diode structure 929. The body ring structure 820 is a concentric ring structure formed within the epitaxial layer 104. The plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure are separated by a dielectric layer. As shown in FIG. 29, the plurality of n-type wells and the plurality of p-type wells are between the gate-source ESD diode structure 929 and the body ring structure 820.

[0089]

[0119] FIG. 30 shows a flowchart of a method for manufacturing the power MOSFET shown in FIG. 1 according to various embodiments of the present disclosure. This flowchart shown in FIG. 30 is merely an example and should not unduly limit the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, various steps shown in FIG. 30 may be added, deleted, replaced, rearranged, and repeated.

[0090]

[0120] In step 3002, an epitaxial layer is grown on a substrate.

[0091]

[0121] In step 3004, a plurality of gates are formed in the epitaxial layer.

[0092]

[0122] In step 3006, a body region and a high-voltage-resistant and leakage-preventing structure are formed in the epitaxial layer.

[0093]

[0123] In step 3008, a source is formed in the epitaxial layer, and a gate-source ESD diode structure is formed on the epitaxial layer.

[0094]

[0124] In step 3010, a source contact is formed to be connected to the source and the first terminal of the gate-source ESD diode structure, and a gate contact is formed to be connected to the plurality of gates and the second terminal of the gate-source ESD diode structure.

[0095]

[0125] The step of forming a high-voltage-resistant and leakage-preventing structure in the epitaxial layer includes a step of forming a RESURF structure by an implantation process, where the RESURF structure is in the upper part of the epitaxial layer and the RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer.

[0096]

[0126] The step of forming a high breakdown voltage and leakage prevention structure in the epitaxial layer is a step of forming a body ring structure by an implantation process, wherein the body ring structure is a concentric ring structure and the body ring structure and the gate-source ESD diode structure are separated by a dielectric layer.

[0097]

[0127] The step of forming a high breakdown voltage and leakage prevention structure in the epitaxial layer includes the step of forming a first p-type well in the epitaxial layer, the step of forming a first n-type well in the first p-type well, wherein the first n-type well is surrounded by the first p-type well, the step of forming a second p-type well in the first n-type well, wherein the second p-type well is surrounded by the first n-type well, and the step of forming a second n-type well in the second p-type well, wherein the second n-type well is surrounded by the second p-type well.

[0098]

[0128] The step of forming a high breakdown voltage and leakage prevention structure in the epitaxial layer includes the step of forming a first n-type well in the epitaxial layer, the step of forming a first p-type well in the first n-type well, wherein the width of the first p-type well is equal to the width of the first n-type well, and the step of forming a second n-type well in the first p-type well, wherein the width of the second n-type well is equal to the width of the first p-type well.

[0099]

[0129] The step of forming a gate-source ESD diode structure on the epitaxial layer includes the step of alternately forming a plurality of n-type regions and a plurality of p-type regions in the interlayer insulating layer on the epitaxial layer.

[0100]

[0130] The method further includes forming an interlayer insulating layer on the epitaxial layer, forming a plurality of trenches in the interlayer insulating layer, forming a plurality of p+ regions at the bottom of each trench, performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs and gate contact plugs, and forming source contacts and gate contacts by an etching process.

[0101]

[0131] FIG. 31 shows a cross-sectional view of the power MOSFET shown in FIG. 16 and a top view of the body ring structure according to various embodiments of the present disclosure. The cross-sectional view is along line A-A'. Since the cross-sectional view of the power MOSFET has been described above with respect to FIGS. 1 and 16, it will not be described again here. As shown in the top view of FIG. 31, the source contact 962 is surrounded by an ESD polysilicon region (for example, the gate-source ESD diode structure 929). The body ring structure 820 is a concentric ring structure. As shown in FIG. 31, the body ring structure 820 includes a first rectangle having rounded corners, a second rectangle having rounded corners, a third rectangle having rounded corners, and a fourth rectangle having rounded corners. In the cross-sectional view, the first rectangle is represented by the pillar 822. The second rectangle is represented by the pillar 824. The third rectangle is represented by the pillar 826. The fourth rectangle is represented by the pillar 828.

[0102]

[0132] As shown in FIG. 31, the body ring structure 820 includes a plurality of rectangles having rounded corners. It is within the scope and spirit of the present invention for the body ring structure 820 to include other shapes such as, but not limited to, an ellipse, a rectangle, a square, or a circle.

[0103]

[0133] Although the embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0104]

[0134] Furthermore, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, products, compositions, means, methods, and steps described herein. As will be readily understood by those skilled in the art from the disclosure of the present disclosure, processes, machines, products, compositions, means, methods, or steps that currently exist or will be developed in the future and that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include such processes, machines, products, compositions, means, methods, or steps within their scope.

Explanation of Reference Numerals

[0105] 100 Power MOSFET 102 Substrate 104 Epitaxial layer 106 Hard mask layer 108 Photoresist layer 200 Power MOSFET of the second embodiment of the high-voltage and leakage-preventing structure 300 Power MOSFET of the third embodiment of the high-voltage and leakage-preventing structure 400 Power MOSFET of the fourth embodiment of the high-voltage and leakage-preventing structure 402 First trench 404 Second trench 406 Third trench 500 Power MOSFET of the fifth embodiment of the high-voltage and leakage-preventing structure 502 Thin dielectric layer 600 Power MOSFET of the sixth embodiment of the high-voltage and leakage-preventing structure 602 Gate electrode layer 700 Power MOSFET of the seventh embodiment of the high-voltage and leakage-preventing structure 702 First gate 704 Second gate 706 Third gate 710 Dielectric layer The 8th embodiment of the high-voltage-resistant and leakage-preventing structure of the power MOSFET The first body region The second body region The photoresist layer The body ring structure The pillar The pillar The pillar The pillar The pillar The 9th embodiment of the high-voltage-resistant and leakage-preventing structure of the power MOSFET The ESD bottom dielectric layer The ESD layer The first source region The second source region The interlayer insulation layer (dielectric layer) The first p-type region The first n+ region The second p-type region The second n+ region The third p-type region The gate-source ESD diode structure The trench The trench The trench The trench The first p+ region The second p+ region The third p+ region The fourth p+ region The metal contact layer The first source contact plug The second source contact plug The third source contact plug The gate contact plug The source contact The gate contact The drain contact The body region The body region 973 Body region (first p-type well) 974 First n-type well 975 Second p-type well 976 Second n-type well 981 First n-type well 982 First p-type well 983 Second n-type well 990 Surface field relaxation (RESURF) structure 991 Photoresist layer 992 Photoresist layer 993 Photoresist layer

Claims

1. Drain and source on both sides of the epitaxial layer, A plurality of gates formed in the epitaxial layer, A source contact connected to the source, A gate contact connected to the plurality of gates, A gate-source electrostatic discharge (ESD) diode structure connected between the gate contact and the source contact, A high-voltage and leakage prevention structure formed under the gate-source ESD diode structure An apparatus comprising.

2. The high-voltage and leakage prevention structure is a surface field relaxation (RESURF) structure, The RESURF structure is configured to disperse an electric field on the gate-source ESD diode structure, The RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer, The apparatus according to claim 1.

3. The high-voltage and leakage prevention structure is a body ring structure, The body ring structure is a concentric ring structure formed in the epitaxial layer, The body ring structure is configured to disperse an electric field on the gate-source ESD diode structure, The body ring structure and the gate-source ESD diode structure are separated by a dielectric layer, The apparatus according to claim 1.

4. The high-voltage and leakage prevention structure includes a plurality of n-type wells and a plurality of p-type wells arranged alternately, The plurality of n-type wells and the plurality of p-type wells are configured to disperse an electric field on the gate-source ESD diode structure, The plurality of n-type wells, the plurality of p-type wells, and the gate-source ESD diode structure are separated by a dielectric layer, The apparatus according to claim 1.

5. In the epitaxial layer, a first p-type well among the plurality of p-type wells is formed, A first n-type well among the plurality of n-type wells is formed in the first p-type well, and the first n-type well is surrounded by the first p-type well, A second p-type well among the plurality of p-type wells is formed in the first n-type well, and the second p-type well is surrounded by the first n-type well, A second n-type well among the plurality of n-type wells is formed in the second p-type well, and the second n-type well is surrounded by the second p-type well. The device according to claim 4.

6. A first n-type well among the plurality of n-type wells is formed in the epitaxial layer, a first p-type well among the plurality of p-type wells is formed in the first n-type well, and the width of the first p-type well is equal to the width of the first n-type well, a second n-type well among the plurality of n-type wells is formed in the first p-type well, and the width of the second n-type well is equal to the width of the first p-type well, The device according to claim 4.

7. The high-voltage resistance and leakage prevention structure includes a RESURF structure and a body ring structure, the RESURF structure and the body ring structure are configured to disperse an electric field on the gate-source ESD diode structure, the body ring structure is a concentric ring structure formed in the epitaxial layer, the RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer, the RESURF structure is between the gate-source ESD diode structure and the body ring structure, The device according to claim 1.

8. The high-voltage resistance and leakage prevention structure includes a plurality of n-type wells, a plurality of p-type wells, and a body ring structure, the plurality of n-type wells and the plurality of p-type wells are alternately arranged, the plurality of n-type wells, the plurality of p-type wells, and the body ring structure are configured to disperse an electric field on the gate-source ESD diode structure, the body ring structure is a concentric ring structure formed in the epitaxial layer, the plurality of n-type wells and the plurality of p-type wells and the gate-source ESD diode structure are separated by a dielectric layer, the plurality of n-type wells and the plurality of p-type wells are between the gate-source ESD diode structure and the body ring structure, The device according to claim 1.

9. The gate-source ESD diode structure includes a first p-type region connected in cascade, a first n+ region, a second p-type region, a second n+ region, and a third p-type region, the first p-type region is connected to the gate contact, the third p-type region is connected to the source contact, The device according to claim 1.

10. The plurality of gates includes a first gate trench, a second gate trench, and a third gate trench. The source includes a first source region and a second source region. The first source region is between the first gate trench and the second gate trench. The second source region is between the second gate trench and the third gate trench. The device according to claim 1.

11. A first body region and a second body region, wherein the first body region is between the first gate trench and the second gate trench, and the second body region is between the second gate trench and the third gate trench, the first body region and the second body region; A first source contact plug having a first terminal connected to the source contact and a second terminal connected to the first source region and the first body region; A second source contact plug having a first terminal connected to the source contact and a second terminal connected to the second source region and the second body region; A gate contact plug having a first terminal connected to the gate contact and a second terminal connected to a first terminal of the gate-source ESD diode structure; A third source contact plug having a first terminal connected to the source contact and a second terminal connected to a second terminal of the gate-source ESD diode structure; An interlayer insulating layer formed on the epitaxial layer, wherein the gate-source ESD diode structure is within the interlayer insulating layer, the interlayer insulating layer The device according to claim 10, further comprising.

12. Growing an epitaxial layer on a substrate; Forming a plurality of gates in the epitaxial layer; Forming a body region and a high-voltage-resistant and leakage-preventing structure in the epitaxial layer; Forming a source in the epitaxial layer and a gate-source ESD diode structure on the epitaxial layer; Forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, and a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure A method comprising.

13. The step of forming the high breakdown voltage and leakage prevention structure in the epitaxial layer is a step of forming a RESURF structure by an implantation process, wherein the RESURF structure is located above the epitaxial layer, and the RESURF structure and the gate-source ESD diode structure are separated by a dielectric layer The method according to claim 12.

14. The step of forming the high breakdown voltage and leakage prevention structure in the epitaxial layer is a step of forming a body ring structure by an implantation process, wherein the body ring structure is a concentric ring structure, and the body ring structure and the gate-source ESD diode structure are separated by a dielectric layer The method according to claim 12.

15. The step of forming the high breakdown voltage and leakage prevention structure in the epitaxial layer is a step of forming a first p-type well in the epitaxial layer a step of forming a first n-type well in the first p-type well, wherein the first n-type well is surrounded by the first p-type well a step of forming a second p-type well in the first n-type well, wherein the second p-type well is surrounded by the first n-type well a step of forming a second n-type well in the second p-type well, wherein the second n-type well is surrounded by the second p-type well including The method according to claim 12.

16. The step of forming the high breakdown voltage and leakage prevention structure in the epitaxial layer is a step of forming a first n-type well in the epitaxial layer a step of forming a first p-type well in the first n-type well, wherein the width of the first p-type well is equal to the width of the first n-type well a step of forming a second n-type well in the first p-type well, wherein the width of the second n-type well is equal to the width of the first p-type well including The method according to claim 12.

17. The step of forming the gate-source ESD diode structure on the epitaxial layer is including a step of alternately forming a plurality of n-type regions and a plurality of p-type regions in an interlayer insulating layer on the epitaxial layer The method according to claim 12.

18. Forming an interlayer insulating layer on the epitaxial layer; Forming a plurality of trenches in the interlayer insulating layer; Forming a plurality of p+ regions at the bottom of each trench; Performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs and gate contact plugs; Forming the source contact and the gate contact by an etching process; The method according to claim 12, further comprising.

19. An epitaxial layer on a substrate; A plurality of gates formed in the epitaxial layer; A body region formed in the epitaxial layer; A source formed in the body region; A gate-source ESD diode structure formed on the epitaxial layer; A body ring structure formed in the epitaxial layer under the gate-source ESD diode structure; An interlayer insulating layer formed on the epitaxial layer, wherein the gate-source ESD diode structure is within the interlayer insulating layer; A plurality of source contact plugs, wherein at least one of the plurality of source contact plugs extends through the interlayer insulating layer, the source, and partially through the body region; A gate contact plug extending partially through the interlayer insulating layer; A gate contact connected to the plurality of gates and a first terminal of the gate-source ESD diode structure via the gate contact plug; A source contact connected to the source, the body region, and a second terminal of the gate-source ESD diode structure via the plurality of source contact plugs; A power MOSFET comprising.

20. The substrate is an n-type substrate; The epitaxial layer is an n-type layer; The body region is a p-type region; The source is an n-type region; The body ring structure is a p-type body ring structure; The body ring structure is a concentric ring structure formed in the epitaxial layer; The gate-source ESD diode structure includes a first p-type region connected in cascade, a first n+ region, a second p-type region, a second n+ region, and a third p-type region, wherein the first p-type region is connected to the gate contact and the third p-type region is connected to the source contact. The power MOSFET according to claim 19.

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