Capacitor structure and semiconductor package including the same

Abstract

To provide a capacitor structure having the improved voltage withstanding characteristic and / or the increased electrostatic capacitance, and a semiconductor package including the capacitor structure.SOLUTION: A capacitor structure according to the present invention includes: a base substrate; a penetration via penetrating the base substrate and extending in a vertical direction; a first sub-capacitor structure including a first lower electrode electrically connected to the penetration via under a lower surface of the base substrate, a first upper electrode, and a first capacitor dielectric film present between the first lower electrode and the first upper electrode; and a second sub-capacitor structure including a second lower electrode electrically connected to the penetration via over an upper surface of the base substrate, a second upper electrode, and a second capacitor dielectric film present between the second lower electrode and the second upper electrode.SELECTED DRAWING: Figure 1J

Description

Technical Field

[0001] The present invention relates to a capacitor structure and a semiconductor package including the same, and more particularly, to a capacitor structure having improved breakdown voltage characteristics and increased capacitance, and a semiconductor package including the same.

Background Art

[0002] In response to the rapid development of the electronics industry and user requirements, electronic devices are becoming more high-performance and miniaturized, and accordingly, semiconductor chips are also becoming more high-performance and miniaturized. As a result, a capacitor structure used for various purposes such as energy storage, signal coupling / decoupling, and electronic filtering is attached to a semiconductor package including a semiconductor chip.

[0003] Therefore, improvement in characteristics such as those of the capacitor structure as described above is required.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the conventional capacitor structure as described above, and an object of the present invention is to provide a capacitor structure having improved breakdown voltage characteristics and / or increased capacitance, and a semiconductor package including the same.

Means for Solving the Problems

[0005] To achieve the above object, a capacitor structure according to the present invention includes a base substrate, a through via that penetrates the base substrate and extends vertically, a first lower electrode that is electrically connected to the through via under the lower surface of the base substrate, a first upper electrode, and a first capacitor dielectric film interposed between the first lower electrode and the first upper electrode, a first sub-capacitor structure composed of the above, a second lower electrode that is electrically connected to the through via above the upper surface of the base substrate, a second upper electrode, and a second capacitor dielectric film interposed between the second lower electrode and the second upper electrode, and a second sub-capacitor structure composed of the above, and is characterized by having the above.

[0006] Also, a capacitor structure according to the present invention made to achieve the above object includes a base substrate, a first sub-capacitor structure disposed under the lower surface of the base substrate, including a first lower electrode, a first upper electrode, and a first capacitor dielectric film interposed between the first lower electrode and the first upper electrode, a first mold layer surrounding the first sub-capacitor structure under the lower surface of the base substrate, a second sub-capacitor structure disposed above the upper surface of the base substrate, including a second lower electrode, a second upper electrode, and a second capacitor dielectric film interposed between the second lower electrode and the second upper electrode, a second mold layer surrounding the second sub-capacitor structure above the upper surface of the base substrate, at least two through vias that penetrate the base substrate and extend vertically, a first bump structure disposed on the second upper electrode and electrically connected to the second upper electrode, and a second bump structure disposed on the second mold layer, and one of the at least two through vias electrically connects the first lower electrode and the second lower electrode, and is characterized by this.

[0007] To achieve the above object, a semiconductor package according to the present invention includes a package substrate including a substrate base, a plurality of upper surface pads disposed on the upper surface of the substrate base, a plurality of lower surface connection pads and at least two passive element connection pads disposed on the lower surface of the substrate base, a semiconductor chip disposed on the upper surface of the package substrate and electrically connected to the package substrate through the plurality of upper surface pads, a sealing material covering the main semiconductor chip on the upper surface of the package substrate, a plurality of external connection terminals disposed on the plurality of lower surface connection pads, and a capacitor structure disposed on the lower surface of the package substrate. The capacitor structure includes a first sub-capacitor structure including a base substrate, a first base conductive layer sequentially disposed under the lower surface of the base substrate, a plurality of first conductive pillars connected to the lower surface of the first base conductive layer and horizontally spaced apart from each other, a first capacitor dielectric film covering the first base conductive layer and the plurality of first conductive pillars, and a first upper electrode covering the first capacitor dielectric film, a second sub-capacitor structure including a second base conductive layer sequentially disposed on the upper surface of the base substrate, a plurality of second conductive pillars connected to the upper surface of the second base conductive layer and horizontally spaced apart from each other, a second capacitor dielectric film covering the second base conductive layer and the plurality of second conductive pillars, and a second upper electrode covering the second capacitor dielectric film, a through via vertically extending through the base substrate and electrically connecting the first base conductive layer and the second base conductive layer, and at least two bump structures disposed on the at least two passive element connection pads. One of the at least two bump structures is disposed on the second upper electrode and electrically connected to the second upper electrode. The first sub-capacitor structure and the second sub-capacitor structure have a symmetrical structure with respect to each other in the vertical direction.

Advantages of the Invention

[0008] According to the capacitor structure according to an embodiment of the present invention, it includes a first sub-capacitor structure and a second sub-capacitor structure connected to each other via a through-via. The first sub-capacitor structure and the second sub-capacitor structure overlap each other in the vertical direction, and the first sub-capacitor structure and the second sub-capacitor structure have a symmetrical structure with respect to each other around the base substrate and the through-via. Therefore, by the method of electrical connection between the first sub-capacitor structure and the second sub-capacitor structure, the breakdown voltage characteristics of the capacitor structure can be improved or it can have an increased capacitance.

Brief Description of the Drawings

[0009]

Figure 1A

Figure 1B

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Figure 13

[0010] Next, specific examples of embodiments for carrying out a capacitor structure and a semiconductor package including the same according to the present invention will be described with reference to the drawings.

[0011] Figures 1A to 1J are cross-sectional views for explaining a method of manufacturing a capacitor structure according to an embodiment of the present invention. Referring to FIG. 1A, a preliminary base substrate 900P is prepared. The preliminary base substrate 900P includes, for example, silicon (Si). Alternatively, the preliminary base substrate 900P may include a semiconductor material such as germanium (Ge), or may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In one embodiment, the preliminary base substrate 900P can be a silicon wafer having a thickness of 725 μm ± 25 μm.

[0012] Referring to both FIGS. 1A and 1B, a portion of the preliminary base substrate 900P is removed to form a base substrate 900. For example, the preliminary base substrate 900P is ground to reduce its thickness and form the base substrate 900. The base substrate 900 is formed to have a thickness of about 50 μm to about 70 μm, but is not limited thereto. For example, the base substrate 900 may have a thickness of about 50 μm to about 700 μm.

[0013] Referring to FIG. 1C, a through via 905 penetrating the base substrate 900 is formed. The through via 905 extends in the vertical direction from the upper surface to the lower surface of the base substrate 900. The through via 905 is formed to have a horizontal width of about 3 μm to about 20 μm. The through via 905 is formed to have a tapered shape in which the horizontal width and the horizontal area decrease from the upper surface to the lower surface of the base substrate 900. The through via 905 is made of a metal, an alloy, a conductive metal nitride, or a combination thereof. For example, the through via 905 contains Cu. The through via 905 is formed by forming a through via hole that penetrates the base substrate 900 and then filling the through via hole with a conductive material. The through via hole is formed to have a width of about 3 μm to about 20 μm. In one embodiment, the through via 905 may be composed of a barrier film covering the inner wall of the through via hole and a conductive film covering the barrier film. For example, the barrier film contains at least one substance selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

[0014] In one embodiment, a PVD (physical vapor deposition), CVD, or ALD (atomic layer deposition) process may be used to form the barrier film. For example, the barrier film is formed to have a thickness of about 40 Å to about 50 Å on the inner wall of the through via hole. The conductive film contains Cu or a Cu alloy. In one embodiment, the conductive film may be composed of Co / Cu, Ni / Cu, or Ru / Cu. A plating process is used to form the conductive film. In one embodiment, an insulating film is interposed between the inner wall of the through via hole and the through via 905. The insulating film is formed to cover the surface of the base substrate 900 exposed on the inner wall of the through via hole with a uniform thickness. In one embodiment, the insulating film may be composed of an oxide film, a nitride film, a carbide film, or a combination thereof. In one embodiment, a CVD process may be used to form the insulating film. The insulating film is formed to have a thickness of about 500 Å to about 2500 Å.

[0015] Referring to FIG. 1D, a first base conductive layer 910 is formed on the base substrate 900. The first base conductive layer 910 contains a metal. For example, the first base conductive layer 910 contains Cu, Al, W, or Ti. In one embodiment, the first base conductive layer 910 may have a stacked structure of a plurality of conductive films. Each of the plurality of conductive films is made of a metal, an alloy, or a conductive metal nitride. The first base conductive layer 910 is formed to have a thickness of about 3 μm to about 20 μm. The first base conductive layer 910 is in contact with the through-via 905 and is electrically connected to the through-via 905.

[0016] Referring to FIG. 1E, a first sub-capacitor structure 920 and a first mold layer 928 surrounding the first sub-capacitor structure 920 are formed on the first base conductive layer 910. The first sub-capacitor structure 920 is electrically connected to the first base conductive layer 910 and includes a plurality of first conductive pillars 922 spaced apart from each other, a first capacitor dielectric film 924 covering the first base conductive layer 910 and the plurality of first conductive pillars 922, and a first upper electrode 926 covering the first capacitor dielectric film 924. The first base conductive layer 910 and the plurality of first conductive pillars 922 together function as a lower electrode of the first sub-capacitor structure 920 and are referred to as a first lower electrode corresponding to the first upper electrode 926 of the first sub-capacitor structure 920. For example, the first sub-capacitor structure 920 includes a first lower electrode, a first upper electrode 926, and a first capacitor dielectric film 924 between the first lower electrode and the first upper electrode 926.

[0017] The plurality of first conductive pillars 922 are formed on the first base conductive layer 910 spaced apart from each other in the horizontal direction. For example, the plurality of first conductive pillars 922 are arranged in a matrix form forming rows and columns horizontally and vertically, or arranged in a honeycomb shape arranged in a zigzag pattern with respect to one of the horizontal and vertical directions. Each of the plurality of first conductive pillars 922 is cylindrical, but is not limited thereto. For example, each of the plurality of first conductive pillars 922 can be columnar with a closed cylindrical shape at the bottom or having various horizontal cross-sections such as a tripod shape, a cross shape, or a macaroni shape. Each of the plurality of first conductive pillars 922 is formed to have a horizontal width of about 100 nm to about 2 μm. Each of the plurality of first conductive pillars 922 is formed to have a height of about 15 μm to about 40 μm. Each of the plurality of first conductive pillars 922 contains a metal. Each of the plurality of first conductive pillars 922 is made of doped polysilicon, a metal, or a conductive metal compound containing impurities. For example, each of the plurality of first conductive pillars 922 contains Cu, W, or TiN.

[0018] The first capacitor dielectric film 924 covers the surface of the first base conductive layer 910 and each of the plurality of first conductive pillars 922. In one embodiment, the first capacitor dielectric film 924 conformally covers the surface of the first base conductive layer 910 and each of the plurality of first conductive pillars 922. For example, the first capacitor dielectric film 924 is formed so as not to completely fill the space between the plurality of first conductive pillars 922. The first capacitor dielectric film 924 contains a high-k dielectric material made of silicon oxide or a dielectric material having a relative dielectric constant higher than that of silicon oxide. The high-k dielectric material has a relative dielectric constant of about 10 to 25. The high dielectric constant material is composed of at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum oxynitride (LaON), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), titanium oxynitride (TiON), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), aluminum oxynitride (AlON), or lead scandium tantalate (PbScTaO). For example, the first capacitor dielectric film 924 is formed to have a thickness of about 10 Å to about 100 nm.

[0019] The first upper electrode 926 covers the first capacitor dielectric film 924. The first capacitor dielectric film 924 is interposed between the first upper electrode 926 and the first base conductive layer 910, and between the first upper electrode 926 and each of the plurality of first conductive pillars 922. The first upper electrode 926 is made of polysilicon doped with impurities, a metal, or a conductive metal compound. The first upper electrode 926 is formed to fill all the spaces between the plurality of first conductive pillars 922. The first mold layer 928 covers a part of the first base conductive layer 910 and surrounds the first sub-capacitor structure 920. For example, the first mold layer 928 surrounds the first sub-capacitor structure 920, but does not necessarily cover the upper surface of the first upper electrode 926. In one embodiment, the upper surface of the first mold layer 928 and the upper surface of the first upper electrode 926 are located at the same vertical level. The first mold layer 928 is made of an insulator. For example, the first mold layer 928 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In one embodiment, the first mold layer 928 may include TEOS (Tetra Ethyl Ortho Silicate) oxide, high density plasma (HDP) oxide, and the like.

[0020] Referring to FIG. 1F, a connection conductive layer 930 covering the upper surface of the first mold layer 928 and the upper surface of the first upper electrode 926, and a first protective layer 940 covering the connection conductive layer 930 are formed. The connection conductive layer 930 includes a metal. For example, the connection conductive layer 930 includes Cu, Al, W, or Ti. In one embodiment, the connection conductive layer 930 may have a stacked structure of a plurality of conductive films. Each of the plurality of conductive films is made of a metal, an alloy, or a conductive metal nitride. The connection conductive layer 930 is formed to have a thickness of about 3 μm to about 20 μm. The connection conductive layer 930 is in contact with the first upper electrode 926 and is electrically connected to the first upper electrode 926. In one embodiment, the connection conductive layer 930 may be omitted without being formed. The first protective layer 940 is made of an insulator. For example, the first protective layer 940 is formed of PSPI (photosensitive polyimide) or includes silicon nitride. The first protective layer 940 is formed to have a thickness of about 10 μm to about 30 μm.

[0021] Referring to FIG. 1G, the result of FIG. 1F is inverted up and down, and after turning the base substrate 900 and the through via 905 upward, a second base conductive layer 950 is formed on the base substrate 900 and the through via 905. The second base conductive layer 950 includes a metal. For example, the second base conductive layer 950 includes Cu, Al, W, or Ti. In one embodiment, the second base conductive layer 950 may have a stacked structure of a plurality of conductive films. Each of the plurality of conductive films is made of a metal, an alloy, or a conductive metal nitride. The second base conductive layer 950 is formed to have a thickness of about 3 μm to about 20 μm. The second base conductive layer 950 is in contact with the via 905 and is electrically connected to the via 905. The lower surface of the via 905 is in contact with the upper surface of the first base conductive layer 910, and the upper surface of the via 905 is in contact with the lower surface of the second base conductive layer 950.

[0022] Referring to FIG. 1H, a second sub-capacitor structure 960 and a second mold layer 968 surrounding the second sub-capacitor structure 960 are formed on the second base conductive layer 950. The second sub-capacitor structure 960 includes a plurality of second conductive pillars 962 connected to the second base conductive layer 950 and spaced apart from each other, a second capacitor dielectric film 964 covering the second base conductive layer 950 and the plurality of second conductive pillars 962, and a second upper electrode 966 covering the second capacitor dielectric film 964. The second base conductive layer 950 and the plurality of second conductive pillars 962 together function as the lower electrode of the second sub-capacitor structure 960, and are referred to as the second lower electrode corresponding to the second upper electrode 966 of the second sub-capacitor structure 960. For example, the second sub-capacitor structure 960 includes a second lower electrode, a second upper electrode 966, and a second capacitor dielectric film 964 between the second lower electrode and the second upper electrode 966. The plurality of second conductive pillars 962, the second capacitor dielectric film 964, the second upper electrode 966, and the second mold layer 968 formed on the second base conductive layer 950 are substantially the same as the plurality of first conductive pillars 922, the first capacitor dielectric film 924, the first upper electrode 926, and the first mold layer 928 formed on the first base conductive layer 910, and duplicate content will be omitted.

[0023] The first sub-capacitor structure 920 and the second sub-capacitor structure 960 have a symmetric structure with respect to each other in a direction perpendicular to the upper surface of the base substrate 900. The first sub-capacitor structure 920 and the second sub-capacitor structure 960 have a symmetric structure with respect to each other centered on the base substrate 900 and the through-via 905. For example, the first base conductive layer 910, the plurality of first conductive pillars 922, the first capacitor dielectric film 924, and the first upper electrode 926 are sequentially arranged from the base substrate 900 and the through-via 905, and the second base conductive layer 950, the plurality of second conductive pillars 962, the second capacitor dielectric film 964, and the second upper electrode 966 are sequentially arranged from the base substrate 900 and the through-via 905. The first sub-capacitor structure 920 and the second sub-capacitor structure 960 are electrically connected to each other via the through-via 905. For example, the plurality of first conductive pillars 922 of the first sub-capacitor structure 920 are electrically connected to the through-via 905 via the first base conductive layer 910, and the plurality of second conductive pillars 962 of the second sub-capacitor structure 960 are electrically connected to the through-via 905 via the second base conductive layer 950.

[0024] Referring to FIG. 1I, a second protective layer 970 having a bump opening 970O is formed covering the upper surface of the second mold layer 968. After forming a protective material layer covering both the upper surface of the second mold layer 968 and the upper surface of the second upper electrode 966, a part of the protective material layer covering at least a part of the second upper electrode 966 is removed to form a second protective layer 970 having a bump opening 970O. The bump opening 970O is disposed in the protective material layer covering at least a part of the second upper electrode 966. At least a part of the second upper electrode 966 is exposed through the bump opening 970O.

[0025] Referring to FIG. 1J, a bump structure 980 is formed on the second upper electrode 966 exposed through the bump opening 970O to form a capacitor structure 1000. The capacitor structure 1000 is a silicon capacitor. The bump structure 980 is disposed on the second upper electrode 966 so as to be electrically connected to the second upper electrode 966. In one embodiment, the bump structure 980 includes, but is not limited to, a connection pad layer 982, a UBM (under-bump-metallization) layer 984 on the connection pad layer 982, and a conductive cap 986 on the UBM layer 984. For example, the bump structure 980 may include the conductive cap 986, but may not include at least one of the connection pad layer 982 or the UBM layer 984. The connection pad layer 982 contains metal. For example, the connection pad layer 982 includes Cu, a copper alloy, Al, W, Au, Ni, or a combination thereof.

[0026] In one embodiment, the connection pad layer 982 may have a relatively thick pillar shape. The connection pad layer 982 is formed by a plating process such as electroplating or electroless plating. The UBM layer 984 covers at least a portion of the connection pad layer 982. In FIG. 1J, the UBM layer 984 is shown covering the entire upper surface of the connection pad layer 982, but this is exemplary and not limited thereto. For example, the UBM layer 984 covers a portion of the upper surface of the connection pad layer 982, for example, a portion adjacent to the edge of the upper surface. The UBM layer 984 is made of Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CrCu, or a combination thereof. The conductive cap 986 covers the upper surface of the UBM layer 984. The conductive cap 986 consists of a solder ball or a solder bump. For example, the conductive cap 986 includes silver (Ag), tin (Sn), gold (Au), or solder. In one embodiment, the conductive cap 986 may include SnAg.

[0027] The capacitor structure 1000 according to the present invention includes a first sub-capacitor structure 920 and a second sub-capacitor structure 960 that are connected to each other via a through-via 905. The first sub-capacitor structure 920 and the second sub-capacitor structure 960 overlap each other in the vertical direction. The first sub-capacitor structure 920 and the second sub-capacitor structure 960 have a symmetric structure with respect to each other around the base substrate 900 and the through-via 905. Therefore, depending on the method of electrically connecting the first sub-capacitor structure 920 and the second sub-capacitor structure 960, the breakdown voltage characteristics of the capacitor structure 1000 can be improved or it can have an increased capacitance.

[0028] Figures 2A to 2I are cross-sectional views for explaining a method of manufacturing a capacitor structure according to the present invention. Referring to Figure 2A, a preliminary base substrate 900P is prepared. In one embodiment, the preliminary base substrate 900P can be a silicon wafer. Referring to both Figures 2A and 2B, a part of the preliminary base substrate 900P is removed to form the base substrate 900. For example, the preliminary base substrate 900P is ground to reduce its thickness to form the base substrate 900.

[0029] Referring to Figure 2C, a through-via 905 that penetrates the base substrate 900 is formed. The through-via 905 extends from the upper surface to the lower surface of the base substrate 900. The through-via 905 is formed to have a tapered shape in which the horizontal width and the horizontal area decrease from the upper surface to the lower surface of the base substrate 900. Referring to Figure 2D, a base conductive layer 910 is formed on the base substrate 900. The base conductive layer 910 is in contact with the through-via 905 and is electrically connected to the through-via 905.

[0030] Referring to FIG. 2E, a sub-capacitor structure 920 and a mold layer 928 surrounding the sub-capacitor structure 920 are formed on the base conductive layer 910. The sub-capacitor structure 920 includes a plurality of conductive pillars 922 that are electrically connected to the base conductive layer 910 and spaced apart from each other, a capacitor dielectric film 924 covering the base conductive layer 910 and the plurality of conductive pillars 922, and an upper electrode 926 covering the capacitor dielectric film 924. The base conductive layer 910 and the plurality of conductive pillars 922 together perform the function of the lower electrode of the sub-capacitor structure 920 and are referred to as the lower electrode corresponding to the upper electrode 926 of the sub-capacitor structure 920. For example, the sub-capacitor structure 920 includes a lower electrode, an upper electrode 926, and a capacitor dielectric film 924 between the lower electrode and the upper electrode 926. The plurality of conductive pillars 922 are formed on the base conductive layer 910 spaced apart from each other in the horizontal direction. The capacitor dielectric film 924 covers the surfaces of the base conductive layer 910 and the plurality of conductive pillars 922 respectively. The upper electrode 926 covers the capacitor dielectric film 924. The upper electrode 926 is formed to fill all the spaces between the plurality of conductive pillars 922. The mold layer 928 covers a part of the base conductive layer 910 and surrounds the sub-capacitor structure 920.

[0031] Referring to FIG. 2F, a protective layer 935 covering the upper surface of the mold layer 928 and the upper surface of the upper electrode 926 is formed to form the sub-structure SUB. The protective layer 935 is made of an insulator. Referring to FIG. 2G, a first sub-structure SUB1 and a second sub-structure SUB2 are prepared. The first sub-structure SUB1 includes a first sub-capacitor structure 920a including a first base substrate 900a, a first through-via 905a, a first base conductive layer 910a, a plurality of first conductive pillars 922a, a first capacitor dielectric film 924a, and a first upper electrode 926a, a first mold layer 928a, and a first protective layer 935a. The second sub-structure SUB2 includes a second sub-capacitor structure 920b including a second base substrate 900b, a second through-via 905b, a second base conductive layer 910b, a plurality of second conductive pillars 922b, a second capacitor dielectric film 924b, and a second upper electrode 926b, a second mold layer 928b, and a second protective layer 935b.

[0032] Each of the first sub-structure SUB1 and the second sub-structure SUB2 is substantially the same as the sub-structure SUB shown in FIG. 2F. Each of the first base substrate 900a and the second base substrate 900b is substantially the same as the base substrate 900 shown in FIG. 2F. Each of the first through-via 905a and the second through-via 905b is substantially the same as the through-via 905 shown in FIG. 2F. Each of the first base conductive layer 910a and the second base conductive layer 910b is substantially the same as the base conductive layer 910 shown in FIG. 2F. Each of the plurality of first conductive pillars 922a and the plurality of second conductive pillars 922b is substantially the same as the plurality of conductive pillars 922 shown in FIG. 2F. Each of the first capacitor dielectric film 924a and the second capacitor dielectric film 924b is substantially the same as the capacitor dielectric film 924 shown in FIG. 2F. Each of the first upper electrode 926a and the second upper electrode 926b is substantially the same as the upper electrode 926 shown in FIG. 2F. Each of the first sub-capacitor structure 920a and the second sub-capacitor structure 920b is substantially the same as the sub-capacitor structure 920 shown in FIG. 2F. Each of the first mold layer 928a and the second mold layer 928b is substantially the same as the mold layer 928 shown in FIG. 2F. Each of the first protective layer 935a and the second protective layer 935b is substantially the same as the protective layer 935 shown in FIG. 2F. For example, the first sub-structure SUB1 is the sub-structure SUB shown in FIG. 2F inverted vertically, and the second sub-structure SUB2 is the sub-structure SUB shown in FIG. 2F. The first sub-structure SUB1 and the second sub-structure SUB2 are arranged such that the first base substrate 900a and the second base substrate 900b face each other, and the first through-via 905a and the second through-via 905b face each other.

[0033] Referring to FIG. 2H, the first through-via 905a and the second through-via 905b are connected to the connection bump 990. For example, the connection bump 990 includes silver (Ag), tin (Sn), gold (Au), or solder. In one embodiment, the connection bump 990 may include SnAg. An insulating adhesive layer 995 is interposed between the first sub-structure SUB1 and the second sub-structure SUB2. The insulating adhesive layer 995 surrounds the connection bump 990 and fills the space between the first sub-structure SUB1 and the second sub-structure SUB2, that is, between the first base substrate 900a and the second base substrate 900b. The insulating adhesive layer 995 includes a non-conductive film (NCF), a die attach film (DAF), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin.

[0034] Referring to FIG. 2I, after removing a part of the second protective layer 935b to form the bump opening 935O, a bump structure 980 is formed on the second upper electrode 926b exposed through the bump opening 935O to form the capacitor structure 1000a. In one embodiment, the bump structure 980 may include, but is not limited to, a connection pad layer 982, a UBM layer 984 on the connection pad layer 982, and a conductive cap 986 on the UBM layer 984.

[0035] The capacitor structure 1000a according to the present invention includes a first sub-capacitor structure 920a and a second sub-capacitor structure 920b that are electrically connected to each other through the first through-via 905a and the second through-via 905b. The first through via 905a and the second through via 905b are electrically connected via the connection bump 990. Each of the first through via 905a and the second through via 905b has a tapered shape in which the horizontal width and the horizontal area decrease as it approaches the connection bump 990 and increase as it moves away from the connection bump 990. The first through via 905a and the second through via 905b have a symmetric structure with respect to each other in the vertical direction. The first through via 905a and the second through via 905b have a symmetric structure with respect to each other centered on the connection bump 990. The first sub-capacitor structure 920a and the second sub-capacitor structure 960b overlap each other in the vertical direction. The first sub-capacitor structure 920a and the second sub-capacitor structure 960b have a symmetric structure with respect to each other in the vertical direction.

[0036] The first base substrate 900a and the second base substrate 900b are both referred to as the base substrate, and the first through via 905a and the second through via 905b are both referred to as the through via. The through via penetrates the base substrate. The first sub-capacitor structure 920a and the second sub-capacitor structure 920b have a symmetric structure with respect to each other centered on the first base substrate 900a, the second base substrate 900b, the first through via 905a, and the second through via 905b. That is, the first sub-capacitor structure 920a and the second sub-capacitor structure 920b have a symmetric structure with respect to each other centered on the base substrate and the through via. The capacitor structure 1000a according to the present invention includes a first sub-capacitor structure 920a and a second sub-capacitor structure 920b that are connected to each other via the first through via 905a and the second through via 905b. Therefore, the breakdown voltage characteristics of the capacitor structure 1000a can be improved or it can have an increased capacitance depending on the electrical connection method between the first sub-capacitor structure 920a and the second sub-capacitor structure 920b.

[0037] Figures 3A to 3I are cross-sectional views for explaining a method of manufacturing a capacitor structure according to the present invention. Referring to Figure 3A, a preliminary base substrate 900P is prepared. In one embodiment, the preliminary base substrate 900P can be a silicon wafer. Referring to both Figures 3A and 3B, a portion of the preliminary base substrate 900P is removed to form a base substrate 900. For example, the preliminary base substrate 900P is ground to reduce its thickness to form the base substrate 900.

[0038] Referring to Figure 3C, a base conductive layer 910 is formed on the base substrate 900. Referring to Figure 3D, a sub-capacitor structure 920 and a mold layer 928 surrounding the sub-capacitor structure 920 are formed on the base conductive layer 910. The sub-capacitor structure 920 includes a plurality of conductive pillars 922 connected to the base conductive layer 910 and spaced apart from each other, a capacitor dielectric film 924 covering the base conductive layer 910 and the plurality of conductive pillars 922, and an upper electrode 926 covering the capacitor dielectric film 924. The base conductive layer 910 and the plurality of conductive pillars 922 together function as the lower electrode of the sub-capacitor structure 920 and are referred to as the lower electrode corresponding to the upper electrode 926 of the sub-capacitor structure 920. For example, the sub-capacitor structure 920 includes a lower electrode, an upper electrode 926, and a capacitor dielectric film 924 between the lower electrode and the upper electrode 926.

[0039] Referring to Figure 3E, a protective layer 935 covering the upper surface of the mold layer 928 and the upper surface of the upper electrode 926 is formed. The protective layer 940 is made of an insulator. Referring to Figure 3F, a through via 907 penetrating the base substrate 900 is formed to form a sub-structure SUBa. The through via 907 extends from the lower surface to the upper surface of the base substrate 900. The through via 907 is electrically connected to the base conductive layer 910. In one embodiment, the through via 907 extends into the base conductive layer 910 after passing through the base substrate 900 from the lower surface of the base substrate 900. The through via 907 is formed to have a tapered shape in which the horizontal width and the horizontal area decrease from the lower surface to the upper surface of the base substrate 900. For example, the through via 907 is formed to have a tapered shape in which the horizontal width and the horizontal area decrease as it moves away from the lower surface of the base substrate 900 and increase as it approaches the lower surface.

[0040] Referring to FIG. 3G, a first sub-structure SUB1a and a second sub-structure SUB2a are prepared. The first sub-structure SUB1a includes a first sub-capacitor structure 920a including a first base substrate 900a, a first through via 907a, a first base conductive layer 910a, a plurality of first conductive pillars 922a, a first capacitor dielectric film 924a, and a first upper electrode 926a, a first mold layer 928a, and a first protective layer 935a. The second sub-structure SUB2a includes a second sub-capacitor structure 920b including a second base substrate 900b, a second through via 907b, a second base conductive layer 910b, a plurality of second conductive pillars 922b, a second capacitor dielectric film 924b, and a second upper electrode 926b, a second mold layer 928b, and a second protective layer 935b.

[0041] Each of the first sub-structure SUB1a and the second sub-structure SUB2a is substantially the same as the sub-structure SUBa shown in FIG. 3F. Each of the first base substrate 900a and the second base substrate 900b is substantially the same as the base substrate 900 shown in FIG. 3F. Each of the first through via 905a and the second through via 907b is substantially the same as the through via 907 shown in FIG. 3F. Each of the first base conductive layer 910a and the second base conductive layer 910b is substantially the same as the base conductive layer 910 shown in FIG. 3F. Each of the plurality of first conductive pillars 922a and the plurality of second conductive pillars 922b is substantially the same as the plurality of conductive pillars 922 shown in FIG. 3F. Each of the first capacitor dielectric film 924a and the second capacitor dielectric film 924b is substantially the same as the capacitor dielectric film 924 shown in FIG. 3F. Each of the first upper electrode 926a and the second upper electrode 926b is substantially the same as the upper electrode 926 shown in FIG. 3F. Each of the first sub-capacitor structure 920a and the second sub-capacitor structure 920b is substantially the same as the sub-capacitor structure 920 shown in FIG. 3F. Each of the first mold layer 928a and the second mold layer 928b is substantially the same as the mold layer 928 shown in FIG. 3F. Each of the first protective layer 935a and the second protective layer 935b is substantially the same as the protective layer 935 shown in FIG. 3F. For example, the first sub-structure SUB1a is the sub-structure SUBa shown in FIG. 3F inverted vertically, and the second sub-structure SUB2a is the sub-structure SUBa shown in FIG. 3F. The first sub-structure SUB1a and the second sub-structure SUB2a are arranged such that the first base substrate 900a and the second base substrate 900b face each other, and the first through via 907a and the second through via 907b face each other.

[0042] Referring to FIG. 3H, the first through via 907a and the second through via 907b are connected to the connection bump 990. An insulating adhesive layer 995 is interposed between the first sub-structure SUB1a and the second sub-structure SUB2a. The insulating adhesive layer 995 surrounds the connection bump 990 and fills the space between the first sub-structure SUB1a and the second sub-structure SUB2a, that is, between the first base substrate 900a and the second base substrate 900b. Referring to FIG. 3I, after removing a part of the second protective layer 935b to form the bump opening 935O, a bump structure 980 is formed on the second upper electrode 926b exposed through the bump opening 935O to form the capacitor structure 1000b. In one embodiment, the bump structure 980 may include, but is not limited to, a connection pad layer 982, a UBM layer 984 on the connection pad layer 982, and a conductive cap 986 on the UBM layer 984.

[0043] The capacitor structure 1000b according to the present invention includes a first sub-capacitor structure 920a and a second sub-capacitor structure 920b that are electrically connected to each other via a first through-via 907a and a second through-via 907b. The first through-via 907a and the second through-via 907b are electrically connected via a connection bump 990. Each of the first through-via 907a and the second through-via 907b has a tapered shape in which the horizontal width and the horizontal area increase as it approaches the connection bump 990 and decrease as it moves away from the connection bump 990. The first through-via 907a and the second through-via 907b have a symmetric structure with respect to each other in the vertical direction. The first through-via 907a and the second through-via 907b have a symmetric structure with respect to each other centered on the connection bump 990. The first sub-capacitor structure 920a and the second sub-capacitor structure 960b overlap each other in the vertical direction. The first sub-capacitor structure 920a and the second sub-capacitor structure 960b have a symmetric structure with respect to each other in the vertical direction.

[0044] The first base substrate 900a and the second base substrate 900b are both referred to as the base substrate, and the first through-via 907a and the second through-via 907b are both referred to as the through-via. The through-via penetrates the base substrate. The first sub-capacitor structure 920a and the second sub-capacitor structure 920b have a symmetric structure with respect to each other centered on the first base substrate 900a, the second base substrate 900b, the first through-via 907a, and the second through-via 907b. That is, the first sub-capacitor structure 920a and the second sub-capacitor structure 920b have a symmetric structure with respect to each other centered on the base substrate and the through-via. The capacitor structure 1000b according to the present invention includes a first sub-capacitor structure 920a and a second sub-capacitor structure 920b that are connected to each other via a first through-via 907a and a second through-via 907b. Therefore, depending on the method of electrically connecting the first sub-capacitor structure 920a and the second sub-capacitor structure 920b, the breakdown voltage characteristics of the capacitor structure 1000b can be improved, or it can have an increased capacitance.

[0045] FIGS. 4 to 11 are cross-sectional views showing the schematic configuration of the capacitor structure according to the present invention. Referring to FIG. 4, the capacitor structure 1002 has a structure similar to the capacitor structure 1000 shown in FIG. 1J. The capacitor structure 1002 includes a base substrate 900, a plurality of through-vias 905 penetrating the base substrate 900, a plurality of first base conductive layers 910 electrically connected to the plurality of through-vias 905 under the base substrate 900, a first sub-capacitor structure 920 connected to at least one of the plurality of first base conductive layers 910 under at least one of the plurality of first base conductive layers 910, a first mold layer 928 surrounding the first sub-capacitor structure 920 under the base substrate 900 and the plurality of first base conductive layers 910, a connection conductive layer 930 under the first mold layer 928 and the first sub-capacitor structure 920, a first protective layer 940 covering the lower surface of the first mold layer 928 and the lower surface of the connection conductive layer 930, a plurality of second base conductive layers 950 electrically connected to the through-vias 905 on the base substrate 900, a second sub-capacitor structure 960 connected to at least one of the plurality of second base conductive layers 950 on at least one of the plurality of second base conductive layers 950, a second mold layer 968 surrounding the second sub-capacitor structure 960 on the base substrate 900 and the plurality of second base conductive layers 950, a second protective layer 970 having a bump opening 970O covering the upper surface of the second mold layer 968, and at least two bump structures 980 disposed on the second upper electrode 966 exposed through the bump opening 970O.

[0046] The capacitor structure 1002 further includes a first connection via 945 that extends through the first mold layer 928 and electrically connects the connection conductive layer 930 and at least one other of the plurality of first base conductive layers 910, and a second connection via 975 that extends through the second mold layer 968 and electrically connects at least one other of the plurality of second base conductive layers 950 and any one of at least two bump structures 980. Each of the first connection via 945 and the second connection via 975 has a tapered shape in which the horizontal width and the horizontal area increase as they move away from the base substrate 900. The first connection via 945 and the second connection via 975 have a symmetric structure with respect to each other in the vertical direction. The first connection via 945 and the second connection via 975 have a symmetric structure with respect to each other centered on the base substrate 900 and the through via 905.

[0047] The first sub-capacitor structure 920 and the second sub-capacitor structure 960 are connected in series. For example, the plurality of first conductive pillars 922 of the first sub-capacitor structure 920 are electrically connected to the plurality of second conductive pillars 962 of the second sub-capacitor structure 960 via the first base conductive layer 910, the through via 905, and the second base conductive layer 950. The first upper electrode 926 of the first sub-capacitor structure 920 and the second upper electrode 966 of the second sub-capacitor structure 960 are electrically connected to different ones of the two bump structures 980. The two bump structures 980 include a first bump structure 980A1 and a second bump structure 980B1. The first bump structure 980A1 is electrically connected to the first upper electrode 926, and the second bump structure 980B1 is electrically connected to the second upper electrode 966. For example, the first upper electrode 926 is electrically connected to the first bump structure 980A1, and the second upper electrode 966 is electrically connected to the second bump structure 980B1 via the connection conductive layer 930, the first connection via 945, the first base conductive layer 910, and the second connection via 975.

[0048] In one embodiment, the first bump structure 980A1 overlaps with the second connection via 975, the second base conductive layer 950, the through via 905, the first base conductive layer 910, and the first connection via 945. For example, the first sub-capacitor structure 920 and the second sub-capacitor structure 960 are connected in series with each other between the first bump structure 980A1 and the second bump structure 980B1 that serve as two terminals of the capacitor structure 1002. Since the first sub-capacitor structure 920 and the second sub-capacitor structure 960 of the capacitor structure 1002 are connected in series, the breakdown voltage characteristics of the capacitor structure 1002 are improved.

[0049] Referring to FIG. 5, the capacitor structure 1004 is the same as or similar to the capacitor structure 1002 shown in FIG. 4, and overlapping content is omitted. The first sub-capacitor structure 920 and the second sub-capacitor structure 960 are connected in parallel. A plurality of first conductive pillars 922 of the first sub-capacitor structure 920 and a plurality of second conductive pillars 962 of the second sub-capacitor structure 960 are electrically connected to at least one of the at least two bump structures 980, and a first upper electrode 926 of the first sub-capacitor structure 920 and a second upper electrode 966 of the second sub-capacitor structure 960 are electrically connected to the other one of the at least two bump structures 980. For example, a plurality of first conductive pillars 922 of the first sub-capacitor structure 920 and a plurality of second conductive pillars 962 of the second sub-capacitor structure 960 are electrically connected via the first base conductive layer 910, the through via 905, and the second base conductive layer 950, and are electrically connected to at least one of the at least two bump structures 980 via a second connection via 975 that is electrically connected to the second base conductive layer 950.

[0050] The first upper electrode 926 of the first sub-capacitor structure 920 and the second upper electrode 966 of the second sub-capacitor structure 960 are electrically connected to another one of at least two bump structures 980 via a connection conductive layer 930, a first connection via 945, a first base conductive layer 910, a through via 905, a second base conductive layer 950, and a second connection via 975. At least two bump structures 980 include a first bump structure 980A2 electrically connected to the first upper electrode 926 and the second upper electrode 966, and a second bump structure 980B2 electrically connected to a plurality of first conductive pillars 922 and a plurality of second conductive pillars 962 among at least two bump structures 980. For example, the first sub-capacitor structure 920 and the second sub-capacitor structure 960 are connected in parallel to each other between a first bump structure 980A1 and a second bump structure 980B1 that serve as two terminals of the capacitor structure 1004. Since the first sub-capacitor structure 920 and the second sub-capacitor structure 960 are connected in parallel in the capacitor structure 1004, the capacitance of the capacitor structure 1004 is improved.

[0051] Referring to FIG. 6, the capacitor structure 1006 is the same as or similar to the capacitor structure 1002 shown in FIG. 4, and overlapping content is omitted. The capacitor structure 1006 includes a pair of first sub-capacitor structures 920 and a pair of second sub-capacitor structures 960. The pair of first sub-capacitor structures 920 and the pair of second sub-capacitor structures 960 are connected in series. For example, one of the pair of first sub-capacitor structures 920, one of the pair of second sub-capacitor structures 960, the other one of the pair of second sub-capacitor structures 960, and the other one of the pair of first sub-capacitor structures 920 are sequentially connected in series. One of the pair of second sub-capacitor structures 960 is electrically connected to one of at least two bump structures 980, and the other one of the pair of second sub-capacitor structures 960 is electrically connected to the other one of at least two bump structures 980. For example, four sub-capacitor structures including a pair of first sub-capacitor structures 920 and a pair of second sub-capacitor structures 960 are connected to each other in series between two bump structures 980. The two bump structures 980 can serve as the two terminals of the capacitor structure 1006.

[0052] Referring to FIG. 7, the capacitor structure 1008 is the same as or similar to the capacitor structure 1006 shown in FIG. 6, and the overlapping content is omitted. The capacitor structure 1006 includes a pair of first sub-capacitor structures 920 and a pair of second sub-capacitor structures 960. The pair of first sub-capacitor structures 920 and the pair of second sub-capacitor structures 960 are connected in parallel. For example, the first upper electrodes 926 of the pair of first sub-capacitor structures 920 and the second upper electrodes 966 of the pair of second sub-capacitor structures 960 are commonly and electrically connected to one of the two bump structures 980, and the plurality of first conductive pillars 922 of the pair of first sub-capacitor structures 920 and the plurality of second conductive pillars 962 of the pair of second sub-capacitor structures 960 are commonly and electrically connected to the other one of the two bump structures 980. For example, four sub-capacitor structures including a pair of first sub-capacitor structures 920 and a pair of second sub-capacitor structures 960 are connected to each other in parallel between two bump structures 980. The two bump structures 980 can serve as the two terminals of the capacitor structure 1006.

[0053] Referring to FIGS. 4 to 7 together, due to the connection relationship between the first base conductive layer 910, the second base conductive layer 950, the through via 905, the connection conductive layer 930, the first connection via 945, and the second connection via 975, the first sub-capacitor structure 920 and the second sub-capacitor structure 960 can be connected in series or in parallel, improving the breakdown voltage characteristics of the capacitor structures (1002, 1004, 1006, 1008) or increasing the capacitance.

[0054] Referring to FIG. 8, the capacitor structure 1002a has a structure similar to the capacitor structure 1000a shown in FIG. 2J. The capacitor structure 1002a includes a first base substrate 900a, a first through via 905a, a first base conductive layer 910a, a first sub-capacitor structure 920a, a first mold layer 928a, a first protective layer 935a, a second base substrate 900b, a second through via 905b, a second base conductive layer 910b, a second sub-capacitor structure 920b, a second mold layer 928b, a second protective layer 935b, a connection bump 990 connecting the first through via 905a and the second through via 905b, and an insulating adhesive layer 995 surrounding the connection bump 990 and filling the space between the first base substrate 900a and the second base substrate 900b. The capacitor structure 1002a further includes a first connection via 945a penetrating the first mold layer 928a and a second connection via 975a penetrating the second mold layer 928b. The first connection via 945a and the second connection via 975a have a symmetric structure with respect to each other in the vertical direction.

[0055] The first sub-capacitor structure 920a and the second sub-capacitor structure 920b are connected in series. For example, a plurality of first conductive pillars 922a of the first sub-capacitor structure 920a and a plurality of second conductive pillars 922b of the second sub-capacitor structure 920b are electrically connected via the first base conductive layer 910a, the first through via 905a, the connection bump 990, the second through via 905b, and the second base conductive layer 910b. The first upper electrode 926a of the first sub-capacitor structure 920a and the second upper electrode 926b of the second sub-capacitor structure 920b are electrically connected to different ones of the two bump structures 980. The two bump structures 980 include a first bump structure 980A3 electrically connected to the first upper electrode 926a and a second bump structure 980B3 electrically connected to the second upper electrode 926b. For example, the first upper electrode 926a is electrically connected to the first bump structure 980A3 via a connection conductive layer 930, a first connection via 945a, a first base conductive layer 910a, a first through via 905a, a connection bump 990, a second through via 905b, a second base conductive layer 910b, and a second connection via 975a, and the second upper electrode 926b is electrically connected to the second bump structure 980B3. For example, the first sub-capacitor structure 920a and the second sub-capacitor structure 960a are connected in series with each other between the first bump structure 980A3 and the second bump structure 980B3 that serve as two terminals of the capacitor structure 1002a. Since the capacitor structure 1002a has the first sub-capacitor structure 920a and the second sub-capacitor structure 920b connected in series, the withstand voltage characteristics of the capacitor structure 1002a are improved.

[0056] Referring to FIG. 9, the capacitor structure 1004a is the same as or similar to the capacitor structure 1002a shown in FIG. 8, and duplicate content is omitted. The first sub-capacitor structure 920a and the second sub-capacitor structure 920b are connected in parallel. A plurality of first conductive pillars 922a of the first sub-capacitor structure 920a and a plurality of second conductive pillars 922b of the second sub-capacitor structure 920 are electrically connected to one of the two bump structures 980, and the first upper electrode 926a of the first sub-capacitor structure 920a and the second upper electrode 926b of the second sub-capacitor structure 920b are electrically connected to the other one of the two bump structures 980. For example, a plurality of first conductive pillars 922a of the first sub-capacitor structure 920a and a plurality of second conductive pillars 922b of the second sub-capacitor structure 920b are electrically connected via a first base conductive layer 910a, a first through-via 905a, a connection bump 990, a second through-via 905b, and a second base conductive layer 910b, and are electrically connected to one of two bump structures 980 via a second connection via 975a that is electrically connected to the second base conductive layer 910b.

[0057] A first upper electrode 926a of the first sub-capacitor structure 920a and a second upper electrode 926b of the second sub-capacitor structure 920b are electrically connected to the other one of two bump structures 980 via a connection conductive layer 930, a first connection via 945a, a first base conductive layer 910a, a first through-via 905a, a connection bump 990, a second through-via 905b, a second base conductive layer 910b, and a second connection via 975b. The two bump structures 980 include a first bump structure 980A4 that is electrically connected to the first upper electrode 926a and the second upper electrode 926b, and a second bump structure 980B4 that is electrically connected to the plurality of first conductive pillars 922a and the plurality of second conductive pillars 922b. For example, the first sub-capacitor structure 920a and the second sub-capacitor structure 920b are connected to each other in parallel between a first bump structure 980A4 and a second bump structure 980B4 that serve as two terminals of the capacitor structure 1004a. Since the first sub-capacitor structure 920a and the second sub-capacitor structure 920b are connected in parallel in the capacitor structure 1004a, the capacitance of the capacitor structure 1004a is improved.

[0058] Referring to FIG. 10, the capacitor structure 1006a is the same as or similar to the capacitor structure 1002a shown in FIG. 8, and overlapping content is omitted. The capacitor structure 1006a includes a pair of first sub-capacitor structures 920a and a pair of second sub-capacitor structures 920b. The pair of first sub-capacitor structures 920a and the pair of second sub-capacitor structures 920b are connected in series. For example, one of the pair of first sub-capacitor structures 920a, one of the pair of second sub-capacitor structures 920b, the other one of the pair of second sub-capacitor structures 920b, and the other one of the pair of first sub-capacitor structures 920a are sequentially connected in series. One of the pair of second sub-capacitor structures 920b is electrically connected to one of the two bump structures 980, and the other one of the pair of second sub-capacitor structures 920b is electrically connected to the other one of the two bump structures 980. For example, the four sub-capacitor structures including the pair of first sub-capacitor structures 920a and the pair of second sub-capacitor structures 920b serve as the two terminals of the capacitor structure 1006a and are connected in series with each other between the two bump structures 980.

[0059] Referring to FIG. 11, the capacitor structure 1008a is the same as or similar to the capacitor structure 1006a shown in FIG. 10, and the overlapping content is omitted. The capacitor structure 1006a includes a pair of first sub-capacitor structures 920a and a pair of second sub-capacitor structures 920b. The pair of first sub-capacitor structures 920a and the pair of second sub-capacitor structures 920b are connected in parallel. For example, the first upper electrodes 926a of the pair of first sub-capacitor structures 920a and the second upper electrodes 926b of the pair of second sub-capacitor structures 920b are commonly and electrically connected to one of the two bump structures 980, and the plurality of first conductive pillars 922a of the pair of first sub-capacitor structures 920a and the plurality of second conductive pillars 922b of the pair of second sub-capacitor structures 920b are commonly and electrically connected to the other one of the two bump structures 980. For example, four sub-capacitor structures including a pair of first sub-capacitor structures 920a and a pair of second sub-capacitor structures 920b serve as the two terminals of the capacitor structure 1008a and are connected in parallel to each other between two bump structures 980.

[0060] Referring to FIGS. 8 to 11 together, the connection relationship between the first base conductive layer 910a, the second base conductive layer 910b, the first through-via 905a, the second through-via 905b, the connection conductive layer 930, the first connection via 945a, and the second connection via 975a connects the first sub-capacitor structure 920a and the second sub-capacitor structure 920b in series or in parallel, thereby improving the breakdown voltage characteristics of the capacitor structures (1002a, 1004a, 1006a, 1008a) or increasing the capacitance. Although not separately shown in the figures, it is obvious to those skilled in the art that the capacitor structure 1000b shown in FIG. 3I can also be deformed to connect the first sub-capacitor structure 920a and the second sub-capacitor structure 920b in series or in parallel with reference to FIGS. 8 to 11.

[0061] FIG. 12 is a cross-sectional view showing a schematic configuration of a semiconductor package including a capacitor structure according to the present invention. Referring to FIG. 12, the semiconductor package 1 includes a package substrate 100, a semiconductor chip 10 attached to the upper surface of the package substrate 100, a capacitor structure 1000 attached to the lower surface of the package substrate 100, and an encapsulant 50 covering and encapsulating the semiconductor chip 10.

[0062] In one embodiment, the package substrate 100 can be a printed circuit board. For example, the package substrate 100 is a double-sided printed circuit board or a multi-layer printed circuit board. The package substrate 100 includes a substrate base 110 and a wiring structure 120. The substrate base 110 can be referred to as a first substrate. The wiring structure 120 includes a plurality of wiring patterns 122 that are disposed on the upper and lower surfaces of the substrate base 110 or are disposed inside the substrate base 110 and extend horizontally, and a plurality of via wirings 124 that penetrate at least a part of the substrate base 110 and extend vertically so as to electrically connect two wiring patterns 122 located at other vertical levels among the plurality of wiring patterns 122. In one embodiment, the substrate base 110 may have a laminated structure of a plurality of base layers, and the plurality of wiring patterns 122 may be disposed on the upper and lower surfaces of each of the plurality of base layers.

[0063] The package substrate 100 further includes a solder resist layer 130 that covers the upper and lower surfaces of the substrate base 110. The solder resist layer 130 includes an upper solder resist layer 132 that covers the upper surface of the substrate base 110 and a lower solder resist layer 134 that covers the lower surface of the substrate base 110. A part of the wiring patterns 122 disposed on the upper surface of the substrate base 110 that is exposed without being covered by the upper solder resist layer 132 is referred to as a plurality of upper pads 122UP, and a part of the wiring patterns 122 disposed on the lower surface of the substrate base 110 that is exposed without being covered by the lower solder resist layer 134 is referred to as a plurality of lower connection pads 122LP and a plurality of passive element connection pads 122SP. A plurality of external connection terminals 150 are disposed on the plurality of lower connection pads 122LP. In one embodiment, the external connection terminal 150 can be a solder ball. Each of the plurality of lower connection pads 122LP and the plurality of passive element connection pads 122SP is referred to as a lower pad.

[0064] The substrate base 110 is made of at least one material selected from phenol resin, epoxy resin, and polyimide. The substrate base 110 includes at least one material selected from, for example, FR4 (Frame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanate ester, polyimide, and liquid crystal polymer. The wiring structure 120 contains copper. For example, each of the plurality of wiring patterns 122 and the plurality of wiring vias 124 is made of, for example, electrolytically deposited (ED) copper foil, rolled-annealed (RA) copper foil, ultra-thin copper foils, sputtered copper, copper alloys, and the like.

[0065] The semiconductor chip 10 includes a semiconductor substrate 12 having an active surface and an inactive surface facing each other, semiconductor elements 14 formed on the active surface of the semiconductor substrate 12, and a plurality of chip pads 16 disposed on the first surface of the semiconductor chip 10. In this specification, the first surface and the second surface of the semiconductor chip 10 face each other, and the second surface of the semiconductor chip 10 means the inactive surface of the semiconductor substrate 12. Since the active surface of the semiconductor substrate 12 is very adjacent to the first surface of the semiconductor chip 10, the illustration for separately distinguishing the active surface of the semiconductor substrate 12 and the first surface of the semiconductor chip 10 is omitted. In one embodiment, the active surface of the semiconductor substrate 12 may correspond to the first surface of the semiconductor chip 10.

[0066] In one embodiment, the semiconductor chip 10 has a face-down arrangement with the first surface facing the package substrate 100 and may be disposed on the upper surface of the package substrate 100. In this case, the first surface of the semiconductor chip 10 is referred to as the lower surface of the semiconductor chip 10, and the second surface of the semiconductor chip 10 is referred to as the upper surface of the semiconductor chip 10. For example, a plurality of chip connection members 18 are interposed between a plurality of chip pads 16 of the semiconductor chip 10 and a plurality of upper surface pads 122UP of the package substrate 100. For example, the chip connection member 18 is a solder ball or a micro bump. The semiconductor chip 10 and the package substrate 100 are electrically connected via a plurality of chip connection members 18. In one embodiment, an underfill layer 90 may be interposed between the lower surface of the semiconductor chip 10 and the upper surface of the package substrate 100. The underfill layer 90 covers and encloses the plurality of chip connection members 18. The underfill layer 90 is made of, for example, a resin material formed by a capillary underfill method. Unless otherwise specified in this specification, the upper surface means the surface facing upward in the drawing, and the lower surface refers to the surface facing downward in the drawing.

[0067] The semiconductor substrate 12 includes, for example, a semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 12 may include a compound semiconductor material such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The semiconductor substrate 12 includes a conductive region, for example, a well doped with impurities. The semiconductor substrate 12 has various element isolation structures such as a STI (shallow trench isolation) structure. On the active surface of the semiconductor substrate 12, a semiconductor element 14 including a plurality of various types of individual devices is formed. The plurality of individual elements include various microelectronic devices, such as MOSFETs (metal-oxide-semiconductor field effect transistors) such as CMOS transistors (complementary metal-insulator-semiconductor transistors), system LSIs (large scale integration), active elements, passive elements, and the like. The plurality of individual elements are electrically connected to the conductive regions of the semiconductor substrate 12. The semiconductor element 14 further includes at least two of the plurality of individual elements, or a conductive wiring or a conductive plug that electrically connects the plurality of individual elements and the conductive regions of the semiconductor substrate 12. Also, the plurality of individual elements are electrically separated from other adjacent individual elements by an insulating film, respectively.

[0068] In one embodiment, the semiconductor chip 10 includes a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, or an application processor (AP) chip. In other embodiments, the semiconductor chip 10 is, for example, a memory semiconductor chip. The memory semiconductor chip is, for example, a non-volatile memory semiconductor chip such as a flash memory, a PRAM (Phase-change Random Access Memory), an MRAM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), or an RRAM (Resistive Random Access Memory). The flash memory is, for example, a NAND (NAND) flash memory or a V-NAND flash memory. In one embodiment, the semiconductor chip 10 can be a volatile memory semiconductor chip such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory).

[0069] The encapsulant 50 covers and encloses the semiconductor chip 10 on the upper surface of the package substrate 100. The encapsulant 50 covers at least a part of the upper surface of the package substrate 100. In one embodiment, the encapsulant 50 covers the entire upper surface of the package substrate 100. In one embodiment, the encapsulant 50 may cover the entire upper surface and side surfaces of the semiconductor chip 10. In other embodiments, the encapsulant 50 may cover the side surfaces of the semiconductor chip 10, but the upper surface of the semiconductor chip 10 may be left exposed without being covered. The encapsulant 50 fills the space between the lower surface of the semiconductor chip 10 and the upper surface of the package substrate 100 and covers and encloses the plurality of chip connection members 18. For example, the encapsulant 50 is a molding member containing an epoxy molding compound (EMC).

[0070] The capacitor structure 1000 is a passive element. For example, the capacitor structure 1000 is a silicon capacitor, a ceramic capacitor, an LICC (Low Inductance Ceramic Capacitors), or an ISC (intermediate storage capacitor). FIG. 12 shows the semiconductor package 1 including the capacitor structure 1000 shown in FIG. 1J, but is not limited thereto. For example, the semiconductor package 1 may include any one of the capacitor structures 1000a shown in FIG. 2I, the capacitor structure 1000b shown in FIG. 3I, the capacitor structure 1002 shown in FIG. 4, the capacitor structure 1004 shown in FIG. 5, the capacitor structure 1006 shown in FIG. 6, the capacitor structure 1008 shown in FIG. 7, the capacitor structure 1002a shown in FIG. 8, the capacitor structure 1004a shown in FIG. 9, the capacitor structure 1006a shown in FIG. 10, and the capacitor structure 1008a shown in FIG. 11 instead of the capacitor structure 1000 shown in FIG. 1J. The base substrate of the capacitor structure 1000 is referred to as the second substrate. The capacitor structure 1000 is connected to a plurality of element connection pads 122SP of the package substrate 100 via a plurality of bump structures 980. For example, the capacitor structure 1000 has two bump structures 980.

[0071] FIG. 13 is a cross-sectional view showing a schematic configuration of a semiconductor package including a capacitor structure according to the present invention. Referring to FIG. 13, the semiconductor package 2 is a package-on-package (PoP) type semiconductor package in which an upper package UP is attached on a lower package LP. The lower package LP includes a first package substrate 100, a first semiconductor chip 10 disposed on the first package substrate 100, a second package substrate 200 covering the first semiconductor chip 10, and a capacitor structure 1000 disposed on the lower surface of the first package substrate 100. The first package substrate 100 and the first semiconductor chip 10 are substantially the same as the package substrate 100 and the semiconductor chip 10 shown in FIG. 12, and overlapping contents are omitted.

[0072] The first package substrate 100 includes a first substrate base 110 and a first wiring structure 120. The first wiring structure 120 includes a plurality of first wiring patterns 122 and a plurality of first wiring vias 124. The first package substrate 100 further includes a first solder resist layer 130. The first solder resist layer 130 includes a first top solder resist layer 132 and a first bottom solder resist layer 134. A portion of the first wiring pattern 122 disposed on the top surface of the first substrate base 110 that is exposed without being covered by the first top solder resist layer 132 is referred to as a plurality of first top pads 122UP, and a portion of the first wiring pattern 122 disposed on the bottom surface of the first substrate base 110 that is exposed without being covered by the first bottom solder resist layer 134 is referred to as a plurality of bottom connection pads 122LP and a plurality of passive element connection pads 122SP. Each of the plurality of bottom connection pads 122LP and the plurality of passive element connection pads 122SP is referred to as a first bottom pad.

[0073] The first semiconductor chip 10 includes a first semiconductor substrate 12 having an active surface and an inactive surface facing each other, a first semiconductor element 14 formed on the active surface of the first semiconductor substrate 12, and a plurality of first chip pads 16 disposed on the first surface of the first semiconductor chip 10. Each of the first semiconductor chip 10, the first semiconductor substrate 12, the first semiconductor element 14, the first chip pad 16, the first chip connection member 18, and the first underfill layer 90 is substantially the same as each of the semiconductor chip 10, the semiconductor substrate 12, the semiconductor element 14, the chip pad 16, the chip connection member 18, and the underfill layer 90 shown in FIG. 12. In one embodiment, the first package substrate 100 can be a printed circuit board. In other embodiments, the first package substrate 100 can be a redistribution structure including redistribution lines, redistribution vias, and a redistribution insulating layer covering the redistribution lines and the redistribution vias.

[0074] The second package substrate 200 covers the first semiconductor chip 10 on the first package substrate 100. The second package substrate 200 is vertically spaced apart from the first semiconductor chip 10. In one embodiment, the second package substrate 200 can be a printed circuit board. For example, the second package substrate 200 is a multilayer printed circuit board. In other embodiments, the second package substrate 200 can be a redistribution structure including redistribution lines, redistribution vias, and a redistribution insulating layer covering the redistribution lines and the redistribution vias. The second package substrate 200 includes a second wiring structure 220 including a second substrate base 210, a plurality of second wiring patterns 222 disposed on the upper and lower surfaces of the second substrate base 210, and a plurality of second substrate vias 224 penetrating at least a part of the second substrate base 210. In one embodiment, the second package substrate 200 has a stacked structure of a plurality of second substrate bases 210, and the plurality of second wiring patterns 222 are disposed on the upper and / or lower surfaces of each of the plurality of second substrate bases. Some of the plurality of second wiring patterns 222 are second upper surface pads 222UP disposed on the upper surface of the second package substrate 200, and some of the others are second lower surface pads 222LP disposed on the lower surface of the second package substrate 200. The corresponding second upper surface pads 222UP and second lower surface pads 222LP among the plurality of second upper surface pads 222UP and the plurality of second lower surface pads 222LP are electrically connected through some of the plurality of second substrate vias 224 or through some of the plurality of second wiring patterns 222 and some of the plurality of second substrate vias 224.

[0075] In one embodiment, the second package substrate 200 may further include a second solder resist layer 230 covering the upper and lower surfaces of the second substrate base 210. The second solder resist layer 230 includes a second upper surface solder resist layer 232 exposing the plurality of second upper surface pads 222UP and covering the upper surface of the second substrate base 210, and a second lower surface solder resist layer 234 exposing the plurality of second lower surface pads 222LP and covering the lower surface of the second substrate base 210. The second package substrate 200, the second substrate base 210, the second wiring structure 220, and the second solder resist layer 230 are each substantially the same as the first package substrate 100, the first substrate base 110, the first wiring structure 120, and the first solder resist layer 130, respectively, and duplicate descriptions are omitted.

[0076] In one embodiment, the horizontal width and horizontal area of the first package substrate 100 may have values equal to the horizontal width and horizontal area of the second package substrate 200. In one embodiment, the number of wiring layers of the second package substrate 200 is less than the number of wiring layers of the first package substrate 100. In this specification, the wiring layer means a place having circuit wiring that forms an electrical path on the same plane. In FIG. 13, the first package substrate 100 is shown as having three wiring layers and the second package substrate 200 is shown as having two wiring layers, but these are exemplary and not limited thereto.

[0077] The encapsulant 50 fills the space between the first package substrate 100 and the second package substrate 200 and covers and encloses the first semiconductor chip 〔10〕. The encapsulant 50 covers the upper surface of the first package substrate 100 and the lower surface of the second package substrate 200. In one embodiment, the encapsulant 50 may fill the space between the upper surface of the first semiconductor chip 10 and the lower surface of the second package substrate 200 so that the first semiconductor chip 10 and the second package substrate 200 are separated from each other. In one embodiment, the edges of the first package substrate 100, the second package substrate 200, and the encapsulant 50 are aligned with each other in the vertical direction.

[0078] A plurality of solder balls 60 are interposed between the first package substrate 100 and the second package substrate 200. In one embodiment, the encapsulant 50 may encapsulate the plurality of solder balls 60. The plurality of solder balls 60 are arranged spaced apart from the semiconductor chip 10 in the horizontal direction. The plurality of solder balls 60 connect between the plurality of first upper surface pads 122UP and the plurality of second lower surface pads 222LP. The upper surfaces of the plurality of solder balls 60 are in contact with the plurality of second lower surface pads 222LP, and the lower surfaces of the plurality of solder balls 60 are in contact with the plurality of first upper surface pads 122UP. The plurality of solder balls 60 are made of conductive solder. For example, the plurality of solder balls 60 contain at least one substance selected from Sn, Bi, Ag, and Zn. The vertical height of the plurality of solder balls 60 is from about 100 μm to about 440 μm.

[0079] The upper package UP includes a third package substrate 300, a second semiconductor chip 410 attached to the upper surface of the third package substrate 300, a second encapsulant 470 covering the second semiconductor chip 410, and a plurality of package connection members 350 attached to the lower surface of the third package substrate 300. The plurality of package connection members 350 are connected to the plurality of second upper surface pads 226U. The third package substrate 300 includes a third substrate base 310, a plurality of third wiring patterns 322 disposed on the upper and lower surfaces of the third substrate base 310, and a third wiring structure 320 including a plurality of third substrate vias 324 penetrating at least a part of the third substrate base 310. In one embodiment, the third package substrate 300 has a stacked structure of a plurality of third substrate bases 310, and the plurality of third wiring patterns 322 are disposed on the upper and / or lower surfaces of each of the plurality of third substrate bases. A part of the plurality of third wiring patterns 322 is a third upper surface pad 322UP disposed on the upper surface of the third package substrate 300, and another part is a third lower surface pad 322LP disposed on the lower surface of the third package substrate 300. Among the plurality of third upper surface pads 322UP and the plurality of third lower surface pads 322LP, the corresponding third upper surface pad 322UP and third lower surface pad 322LP are electrically connected through a part of the plurality of third substrate vias 324, or are electrically connected through a part of the plurality of third wiring patterns 322 and a part of the plurality of third substrate vias 324.

[0080] In one embodiment, the third package substrate 300 further includes a third solder resist layer 330 covering the upper and lower surfaces of the third substrate base 310. The third solder resist layer 330 includes a third upper surface solder resist layer 332 that exposes the plurality of third upper surface pads 322UP and covers the upper surface of the third substrate base 310, and a third lower surface solder resist layer 334 that exposes the plurality of third lower surface pads 322LP and covers the lower surface of the third substrate base 310. A plurality of package connection members 350 are arranged on the plurality of third lower surface pads 322LP. For example, the plurality of package connection members 350 are interposed between the plurality of second upper surface pads 222UP and the plurality of third lower surface pads 322LP. Each of the third package substrate 300, the third substrate base 310, the third wiring structure 320, and the third solder resist layer 330 is substantially the same as each of the first package substrate 100, the first substrate base 110, the first wiring structure 120, and the first solder resist layer 130, and duplicate descriptions are omitted.

[0081] The second semiconductor chip 410 includes a second semiconductor substrate 412 having an active surface and an inactive surface facing each other, a second semiconductor element 414 formed on the active surface of the second semiconductor substrate 412, and a plurality of second chip pads 416 arranged on the first surface of the second semiconductor chip 410. The second semiconductor chip 410 and the third package substrate 300 are electrically connected through a plurality of second chip connection members 450 connecting the plurality of second chip pads 416 and the plurality of third upper surface pads 322UP. The second semiconductor chip 410 is substantially the same as the first semiconductor chip 10, and duplicate descriptions are omitted. In one embodiment, the first semiconductor chip 10 may be a central processing unit chip, a graphics processing unit chip, or an application processor chip, and the second semiconductor chip 410 may be a memory semiconductor chip. In one embodiment, between the second surface of the second semiconductor chip 410, that is, the lower surface, and the third package substrate 300, a second underfill layer 460 covering a plurality of second chip connection members 450 is interposed. In one embodiment, the second encapsulant 470 may cover the upper surface of the third package substrate 300 and wrap the second semiconductor chip 410 and the second underfill layer 460.

[0082] FIG. 13 shows the second semiconductor chip 410 as being disposed on the upper surface of the third package substrate 300 with a face-up arrangement, but is not limited thereto. For example, the second semiconductor chip 410 may be disposed on the upper surface of the third package substrate 300 with a face-down arrangement. The capacitor structure 1000 is connected to a plurality of element connection pads 122SP of the package substrate 100 via a plurality of bump structures 980. FIG. 13 shows the semiconductor package 2 as including the capacitor structure 1000 shown in FIG. 1J, but is not limited thereto. For example, instead of the capacitor structure 1000 shown in FIG. 1J, the semiconductor package 2 may include any one of the capacitor structures 1000a shown in FIG. 2I, the capacitor structures 1000b shown in FIG. 3I, the capacitor structure 1002 shown in FIG. 4, the capacitor structure 1004 shown in FIG. 5, the capacitor structure 1006 shown in FIG. 6, the capacitor structure 1008 shown in FIG. 7, the capacitor structure 1002a shown in FIG. 8, the capacitor structure 1004a shown in FIG. 9, the capacitor structure 1006a shown in FIG. 10, and the capacitor structure 1008a shown in FIG. 11.

[0083] Furthermore, the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.

Explanation of Reference Numerals

[0084] 1, 2 Semiconductor package 10 Semiconductor chip 50 Encapsulant 100 Package substrate, First package substrate 200 Second package substrate 300 Third package substrate 410 Second semiconductor chip 900 Base substrate 900a First base substrate 900b Second base substrate 900P Preliminary base substrate 905 Through-hole via 905a, 907a First through-hole via 905b, 907b Second through-hole via 910, 910a First base conductive layer 920, 920a First sub-capacitor structure 922 First conductive pillar 924 First capacitor dielectric film 926 First upper electrode 928, 928a First mold layer 930 Connection conductive layer 935, 935a, 940 (First) protective layer 945, 945a First connection via 950, 910b Second base conductive layer 960, 920b Second sub-capacitor structure 962 Second conductive pillar 964 Second capacitor dielectric film 966 Second upper electrode 968, 927b Second mold layer 935b, 970 Second protective layer 970O Bump opening 975, 975a Second connection via 980 Bump structure 982 Connection Pad Layer 984 UBM Layer 986 Conductive Cap 990 Connection Bump 995 Insulating Adhesive Layer 1000, 1000a, 1000b, 1002, 1002a, 1004, 1004a, 1006, 1006a, 1008, 1008a Capacitor Structures LP Lower Package SUB Sub - Structure SUB1 First Sub - Structure SUB2 Second Sub - Structure UP Upper Package

Claims

1. A base substrate, A through-via that penetrates the base substrate and extends vertically, A first lower electrode, a first upper electrode, and a first capacitor dielectric film interposed between the first lower electrode and the first upper electrode, which are electrically connected to the through-via below the lower surface of the base substrate, a first sub-capacitor structure, A second lower electrode, a second upper electrode, and a second capacitor dielectric film interposed between the second lower electrode and the second upper electrode, which are electrically connected to the through-via above the upper surface of the base substrate, a second sub-capacitor structure, a capacitor structure characterized by having.

2. The capacitor structure according to claim 1, wherein the first sub-capacitor structure and the second sub-capacitor structure have a symmetrical structure with respect to each other in the vertical direction.

3. The capacitor structure according to claim 1, further comprising a first bump structure disposed on the second upper electrode and electrically connected to the second upper electrode.

4. The capacitor structure according to claim 3, wherein the through-via has a tapered shape in which the horizontal width increases from the upper surface to the lower surface of the base substrate.

5. Further comprising a connection bump, The base substrate includes a first base substrate and a second base substrate disposed on the first base substrate, The through-via includes a first through-via that penetrates the first base substrate and a second through-via that penetrates the second base substrate, which are electrically connected to each other via the connection bump, The capacitor structure according to claim 3, wherein the first through-via and the second through-via have a symmetrical structure with respect to each other centered on the connection bump.

6. The capacitor structure according to claim 5, wherein each of the first through-via and the second through-via has a tapered shape in which the horizontal width decreases as it approaches the connection bump.

7. The capacitor structure according to claim 5, wherein each of the first through-via and the second through-via has a tapered shape in which the horizontal width increases as it approaches the connection bump.

8. The first lower electrode includes a first base conductive layer and a plurality of first conductive pillars connected to the lower surface of the first base conductive layer and spaced apart from each other in the horizontal direction, The capacitor structure according to claim 1, wherein the second lower electrode includes a second base conductive layer and a plurality of second conductive pillars connected to the upper surface of the second base conductive layer and horizontally spaced apart from each other.

9. The capacitor structure according to claim 8, wherein the lower surface of the through via is in contact with the upper surface of the first base conductive layer, and the upper surface of the through via is in contact with the lower surface of the second base conductive layer.

10. A base substrate, A first sub-capacitor structure disposed under the lower surface of the base substrate, comprising a first lower electrode, a first upper electrode, and a first capacitor dielectric film interposed between the first lower electrode and the first upper electrode; A first mold layer disposed under the lower surface of the base substrate and surrounding the first sub-capacitor structure; A second sub-capacitor structure disposed on the upper surface of the base substrate, comprising a second lower electrode, a second upper electrode, and a second capacitor dielectric film interposed between the second lower electrode and the second upper electrode; A second mold layer disposed on the upper surface of the base substrate and surrounding the second sub-capacitor structure; At least two through vias penetrating the base substrate and extending vertically; A first bump structure disposed on the second upper electrode and electrically connected to the second upper electrode; A second bump structure disposed on the second mold layer, and having The capacitor structure, wherein one of the at least two through vias electrically connects the first lower electrode and the second lower electrode.

11. The capacitor structure according to claim 10, wherein the second bump structure is electrically connected to the first upper electrode.

12. A connection conductive layer disposed under the first upper electrode and electrically connected to the first upper electrode; A first connection via penetrating the first mold layer; A second connection via penetrating the second mold layer, and further having The capacitor structure according to claim 11, wherein the first upper electrode is electrically connected to the second bump structure through the connection conductive layer, the first connection via, another one of the at least two through vias, and the second connection via.

13. The capacitor structure according to claim 10, wherein the second bump structure is electrically connected to the first lower electrode and the second lower electrode.

14. Under the first upper electrode, a connection conductive layer electrically connected to the first upper electrode, a first connection via penetrating the first mold layer, and at least two second connection vias penetrating the second mold layer, and further includes, The first upper electrode is electrically connected to the first bump structure via one of the other of the connection conductive layer, the first connection via, and at least two through vias, and one of the at least two second connection vias. The capacitor structure according to claim 13, wherein:

15. The first lower electrode and the second lower electrode are electrically connected to the second bump structure via the other of the at least two second connection vias. The capacitor structure according to claim 14, wherein:

16. Each of the at least two through vias has a tapered shape in which the horizontal width increases from the upper surface to the lower surface of the base substrate. The capacitor structure according to claim 10, wherein:

17. Further having a connection bump, The base substrate includes a first base substrate and a second base substrate disposed on the first base substrate, The through vias are electrically connected to each other via the connection bump, and include a first through via penetrating the first base substrate and a second through via penetrating the second base substrate, The first through via and the second through via each have a tapered shape so as to have a symmetric structure with respect to each other centering on the connection bump. The capacitor structure according to claim 10, wherein:

18. A package substrate including a substrate base, a plurality of upper surface pads disposed on the upper surface of the substrate base, a plurality of lower surface connection pads disposed on the lower surface of the substrate base, and at least two passive element connection pads, A semiconductor chip disposed on the upper surface of the package substrate and electrically connected to the package substrate via the plurality of upper surface pads, A sealing material covering the main semiconductor chip on the upper surface of the package substrate, A plurality of external connection terminals disposed on the plurality of lower surface connection pads, A capacitor structure disposed on the lower surface of the package substrate, and having, The capacitor structure is, A base substrate, A first base conductive layer sequentially disposed under the lower surface of the base substrate, a plurality of first conductive pillars connected to the lower surface of the first base conductive layer and horizontally spaced apart from each other, a first capacitor dielectric film covering the first base conductive layer and the plurality of first conductive pillars, and a first upper electrode covering the first capacitor dielectric film, a first sub-capacitor structure; A second base conductive layer sequentially disposed on the upper surface of the base substrate, a plurality of second conductive pillars connected to the upper surface of the second base conductive layer and horizontally spaced apart from each other, a second capacitor dielectric film covering the second base conductive layer and the plurality of second conductive pillars, and a second upper electrode covering the second capacitor dielectric film, a second sub-capacitor structure; A through via that penetrates the base substrate and extends vertically to electrically connect the first base conductive layer and the second base conductive layer; At least two bump structures disposed on the at least two passive element connection pads; One of the at least two bump structures is disposed on the second upper electrode and electrically connected to the second upper electrode; The semiconductor package, wherein the first sub-capacitor structure and the second sub-capacitor structure have a symmetric structure with respect to each other in the vertical direction.

19. The through via has a tapered shape in which the horizontal width increases from the upper surface to the lower surface of the base substrate; The semiconductor package according to claim 18, wherein the horizontal width of the through via is 3 μm to 20 μm.

20. Connection bumps; And an insulating adhesive layer surrounding the connection bumps, The base substrate includes a first base substrate and a second base substrate disposed on the first base substrate, The insulating adhesive layer fills the space between the first base substrate and the second base substrate, The through via includes a first through via that penetrates the first base substrate and a second through via that penetrates the second base substrate, and is electrically connected to each other through the connection bump, The semiconductor package according to claim 18, wherein the first through via and the second through via each have a tapered shape so as to have a symmetric structure with respect to each other centered on the connection bump.

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