Imaging apparatus and camera system

Abstract

To provide an imaging device or the like, capable of suppressing a dark current.SOLUTION: An imaging apparatus 100 includes: a photoelectric conversion part 12 that converts light into charges; and a semiconductor substrate 60 having a first surface S1. The semiconductor substrate 60 includes: an n-type semiconductor layer 62n of a first conductivity type; a p-type semiconductor layer 65p of a second conductivity type different from the first conductivity type located closer to a first surface S1 than the n-type semiconductor layer 62n; an impurity region 68bn of the first conductivity type; a charge accumulation region 67n of the first conductivity type that accumulates charges; and a blocking structure 69 located between the impurity region 68bn and the charge accumulation region 67n in plan view. The n-type semiconductor layer 62n includes: a first portion 62a overlapping the blocking structure 69; and a second portion 62b including a portion not overlapping the blocking structure 69 in plan view. A shortest distance L1 between the first portion 62a and the first surface S1 is shorter than a shortest distance L2 between the second portion 62b and the first surface S1.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a camera system.

Background Art

[0002] In digital cameras and the like, CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used. These image sensors have photodiodes formed on a semiconductor substrate.

[0003] Also, as disclosed in Patent Documents 1 and 2 for example, a structure in which a photoelectric conversion layer is disposed above a semiconductor substrate instead of a photodiode has also been proposed. An imaging device having such a structure may be called a stacked imaging device. In a stacked imaging device, charges generated by photoelectric conversion are temporarily accumulated as signal charges in an impurity diffusion region or the like formed in a semiconductor substrate. A signal corresponding to the accumulated amount of signal charges is read out via a CCD circuit or a CMOS circuit formed in the semiconductor substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Charges different from the signal charges representing an image can cause noise that degrades the resulting image when they flow into the impurity diffusion region that temporarily holds the signal charges. It is beneficial to be able to suppress such unintentional charge movement. Hereinafter, such unintentional charge movement may be referred to as dark current or leakage current. Also, hereinafter, the impurity diffusion region may simply be referred to as the impurity region.

[0006] The present disclosure provides an imaging device and the like that can suppress dark current.

Means for Solving the Problem

[0007] An imaging device according to one aspect of the present disclosure includes a photoelectric conversion unit that converts light into charges, and a semiconductor substrate having a first surface. The semiconductor substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type different from the first conductivity type and located closer to the first surface than the first layer, a first impurity region of the first conductivity type located within the second layer, a second impurity region of the first conductivity type that accumulates the charges and is located within the second layer, and a blocking structure located within the second layer and positioned between the first impurity region and the second impurity region in a plan view. The first layer includes a first portion that overlaps the blocking structure in the plan view and a second portion that is located at a position different from the first portion and does not overlap the blocking structure in the plan view. The shortest distance between the first portion and the first surface is shorter than the shortest distance between the second portion and the first surface.

[0008] A camera system according to one aspect of the present disclosure includes the above imaging device.

[0009] Furthermore, the general or specific aspect may be implemented by an element, a device, a module, a system, or a method. Also, the general or specific aspect may be implemented by any combination of an element, a device, an apparatus, a module, a system, and a method.

[0010] In addition, the additional effects and advantages of the disclosed embodiments will become apparent from the specification and the drawings. The effects and / or advantages are individually provided by the various embodiments or features disclosed in the specification and the drawings, and not all are required to obtain one or more of these.

Advantages of the Invention

[0011] According to the present disclosure, dark current can be suppressed.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0013] (Background leading to one aspect of the present disclosure) As described above, in an imaging device, dark current is generated due to the inflow of charges different from signal charges into an impurity region that temporarily holds signal charges. Hereinafter, the impurity region that temporarily holds signal charges may be referred to as a charge storage region.

[0014] In addition, impurity regions other than the charge storage region, such as the source and drain in the transistors of the signal detection circuit, are also formed in the semiconductor substrate. A high voltage may be applied to such impurity regions other than the charge storage region for signal detection. In such impurity regions where a high voltage is applied, charges different from signal charges are likely to be generated as carriers. For example, in an impurity region where a high voltage is applied, charges may be generated by impact ionization, and when the generated charges flow into the charge storage region, they become dark current.

[0015] The present disclosure has been made in view of such problems, and provides an imaging device or the like that can suppress dark current by suppressing the inflow of charges generated in impurity regions other than the charge storage region into the charge storage region.

[0016] (Overview of the present disclosure) As an overview of one aspect of the present disclosure, examples of the imaging device and the camera system according to the present disclosure are shown below.

[0017] For example, the imaging device according to the first aspect of the present disclosure includes a photoelectric conversion unit that converts light into electric charges, and a semiconductor substrate having a first surface. The semiconductor substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type different from the first conductivity type and located closer to the first surface than the first layer, a first impurity region of the first conductivity type located within the second layer, a second impurity region of the first conductivity type located within the second layer and accumulating the electric charges, and a blocking structure located within the second layer and positioned between the first impurity region and the second impurity region in a plan view. The first layer includes a first portion that overlaps the blocking structure in the plan view, and a second portion that is at a position different from the first portion in the plan view and does not overlap the blocking structure. The shortest distance between the first portion and the first surface is shorter than the shortest distance between the second portion and the first surface.

[0018] Thereby, even when a charge different from the signal charge generated by the photoelectric conversion unit is generated near the interface between the first impurity region and the second layer, such as when a high voltage is applied to the first impurity region, the inflow of the charge into the second impurity region that accumulates the signal charge can be suppressed. Specifically, the presence of the blocking structure between the first impurity region and the second impurity region can suppress the inflow of a charge different from the signal charge into the second impurity region. Further, the presence of the first portion that is relatively close to the first surface in the first layer at a position overlapping the blocking structure can facilitate the inflow of the charge directed toward the second impurity region, which is different from the signal charge, into the first portion. Therefore, the inflow of a charge different from the signal charge into the second impurity region can be suppressed. Thus, according to the imaging device of the present aspect, dark current can be suppressed.

[0019] Further, for example, the imaging device according to the second aspect of the present disclosure is the imaging device according to the first aspect, and the first portion is a convex portion in the first layer.

[0020] Thereby, the structure of the first layer having the first portion can be easily realized only by ion implanting at the position corresponding to the first portion.

[0021] Further, for example, the imaging device according to the third aspect of the present disclosure is the imaging device according to the first aspect or the second aspect, and in the plan view, the second impurity region overlaps with the second portion.

[0022] Thereby, the distance between the second impurity region and the first layer becomes longer, and the inflow of charges from the first layer to the second impurity region due to the proximity of the second impurity region and the first layer can be suppressed.

[0023] Further, for example, the imaging device according to the fourth aspect of the present disclosure is the imaging device according to any one of the first aspect to the third aspect, and the blocking structure is implantation separation.

[0024] Thereby, the inflow of charges generated in the vicinity of the first impurity region into the second impurity region can be suppressed by the blocking structure using implantation separation.

[0025] Further, for example, the imaging device according to the fifth aspect of the present disclosure is the imaging device according to any one of the first aspect to the fourth aspect, and further includes a voltage supply circuit that supplies a constant voltage to the first layer.

[0026] Thereby, the voltage of the first layer becomes constant, and the charges generated in the vicinity of the first impurity region and heading for the second impurity region can be stably made to easily flow into the first portion.

[0027] Further, for example, the imaging device according to the sixth aspect of the present disclosure is the imaging device according to any one of the first aspect to the fifth aspect, and further includes a transistor having a gate connected to the photoelectric conversion unit, and the transistor includes the first impurity region as one of a source and a drain.

[0028] Thereby, the inflow of charges generated near one of the source and the drain in the transistor capable of outputting a signal according to the amount of charges generated in the photoelectric conversion unit into the second impurity region can be suppressed.

[0029] Further, for example, the imaging device according to the seventh aspect of the present disclosure is the imaging device according to any one of the first aspect to the sixth aspect, and the photoelectric conversion unit is located above the semiconductor substrate.

[0030] Thereby, dark current can be suppressed in the stacked imaging device.

[0031] Further, for example, the imaging device according to the eighth aspect of the present disclosure is the imaging device according to any one of the first aspect to the seventh aspect, and the first portion overlaps with any straight line connecting a point in the first impurity region and a point in the second impurity region in the plan view.

[0032] Thereby, any charge generated at any position near the first impurity region can easily flow into the first portion when the charge goes toward the second impurity region.

[0033] Further, for example, the camera system according to the ninth aspect of the present disclosure includes the imaging device according to any one of the first aspect to the eighth aspect.

[0034] Thereby, since the camera system according to the present aspect includes the imaging device capable of suppressing the above dark current, a camera system with reduced noise can be realized.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below show all-inclusive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components, steps, orders of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in this specification can be combined with each other as long as no contradiction occurs. Among the components in the following embodiments, components not described in the independent claims are described as optional components. In the following description, components having substantially the same function are denoted by the same reference numerals, and the description thereof may be omitted. Also, in order to avoid making the drawings overly complicated, the illustration of some elements may be omitted.

[0036] In addition, the various elements shown in the drawings are only schematically shown for the purpose of understanding the present disclosure, and dimensions, ratios, appearances, etc. may differ from the actual ones. That is, each drawing is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, scales in each drawing do not necessarily match.

[0037] Also, in this specification, terms indicating relationships between elements such as parallel or uniform, terms indicating the shapes of elements such as circular or rectangular, and numerical ranges are not expressions representing only strict meanings, but are expressions meaning ranges that are substantially equivalent, for example, including differences of about several percent.

[0038] Also, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by relative positional relationships based on the stacking order in a stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper", and the side opposite to the light-receiving side is defined as "lower". Similarly, for the "upper surface" and "lower surface" of each member, the surface facing the light-receiving side of the imaging device is defined as the "upper surface", and the surface facing the side opposite to the light-receiving side is defined as the "lower surface". Note that terms such as "upper", "lower", "upper surface", and "lower surface" are used only to specify the mutual arrangement between members and are not intended to limit the posture of the imaging device during use. Also, the terms "upper" and "lower" are applicable not only when two components are arranged with a space between them and there is another component between the two components, but also when two components are arranged in close contact with each other and the two components are in contact. Also, in this specification, "plan view" refers to the direction perpendicular to the main surface of the semiconductor substrate, in other words, when viewed from the thickness direction of the semiconductor substrate.

[0039] Also, in this specification, when a transistor is arranged on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are arranged with a certain surface interposed therebetween.

[0040] (Embodiment 1) Hereinafter, the imaging device according to Embodiment 1 will be described.

[0041] [Overall Configuration] First, the overall configuration of the imaging device according to the present embodiment will be described.

[0042] FIG. 1 is a diagram showing an exemplary configuration of an imaging device 100 according to Embodiment 1. The imaging device 100 shown in FIG. 1 includes a plurality of pixels 10 and a peripheral circuit 40 formed on a semiconductor substrate 60.

[0043] Each pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 receives light incidence and generates positive and negative charges, typically, hole - electron pairs. That is, the photoelectric conversion unit 12 converts light into charges. The photoelectric conversion unit 12 can be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 60, or a photodiode formed in the semiconductor substrate 60. In FIG. 1, the photoelectric conversion units 12 of the respective pixels 10 are shown to be spatially separated from each other, but this is only for convenience of explanation, and the photoelectric conversion units 12 of the plurality of pixels 10 may be continuously arranged on the semiconductor substrate 60 without any space between them.

[0044] In the example shown in FIG. 1, the pixels 10 are arranged in a plurality of rows and columns of m rows and n columns. Here, m and n independently represent integers of 1 or more. The pixels 10 form an imaging region R1 by being arranged two - dimensionally on the semiconductor substrate 60, for example. When each pixel 10 has a photoelectric conversion unit 12 disposed above the semiconductor substrate 60, for example, the imaging region R1 can be defined as the region of the semiconductor substrate 60 covered by the photoelectric conversion unit 12.

[0045] The number and arrangement of pixels 10 are not limited to the illustrated example. For example, the number of pixels 10 included in the imaging device 100 may be one. In this example, the centers of the respective pixels 10 are located on the lattice points of a square lattice. However, for example, a plurality of pixels 10 may be arranged such that the centers of the respective pixels 10 are located on the lattice points of a triangular lattice, a hexagonal lattice, or the like. For example, the pixels 10 may be arranged in one dimension. In this case, the imaging device 100 can be used as a line sensor.

[0046] In the configuration illustrated in FIG. 1, the peripheral circuit 40 includes a vertical scanning circuit 42 and a horizontal signal readout circuit 44. As illustrated in FIG. 1, the peripheral circuit 40 may additionally include a control circuit 46. Further, the peripheral circuit 40 may further include a voltage supply circuit that supplies a predetermined voltage to, for example, the pixels 10. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, and the like. The peripheral circuit 40 is arranged in the peripheral region R2. The peripheral region R2 is a region around the imaging region R1 in the semiconductor substrate 60. Note that at least a part of the peripheral circuit 40 may be arranged on another semiconductor substrate different from the semiconductor substrate 60 on which the pixels 10 are formed. That is, at least a part of the peripheral circuit 40 may not be arranged in the peripheral region R2. In this case, the other semiconductor substrate may be laminated on the semiconductor substrate 60.

[0047] The vertical scanning circuit 42, also called a row scanning circuit, has a connection with address signal lines 34 provided corresponding to each row of the plurality of pixels 10. As will be described later, the signal lines provided corresponding to each row of the plurality of pixels 10 are not limited to the address signal lines 34, and a plurality of types of signal lines may be connected to the vertical scanning circuit 42 for each row of the plurality of pixels 10. The horizontal signal readout circuit 44, also called a column scanning circuit, has a connection with vertical signal lines 35 provided corresponding to each column of the plurality of pixels 10.

[0048] The control circuit 46 receives, for example, command data, a clock, etc. given from the outside of the imaging device 100 and controls the entire imaging device 100. The control circuit 46 has, for example, a timing generator and supplies drive signals to the vertical scanning circuit 42, the horizontal signal readout circuit 44, the voltage supply circuit, etc. In FIG. 1, the arrows extending from the control circuit 46 schematically represent the flow of output signals from the control circuit 46. The control circuit 46 can be realized by, for example, a microcontroller including one or more processors. The functions of the control circuit 46 may be realized by a combination of a general-purpose processing circuit and software, or may be realized by hardware specialized for such processing.

[0049] FIG. 2 is a schematic diagram schematically showing an exemplary circuit configuration of the imaging device 100 according to Embodiment 1. In FIG. 2, in order to avoid complication of the drawing, four pixels 10 arranged in two rows and two columns are representatively shown. Each of these pixels 10 is an example of the pixel 10 shown in FIG. 1. Each pixel 10 has a photoelectric conversion unit 12 and includes a signal detection circuit 14 electrically connected to the photoelectric conversion unit 12. As will be described in detail later with reference to FIG. 3, the photoelectric conversion unit 12 includes a photoelectric conversion layer 12b disposed above the semiconductor substrate 60. That is, here, a stacked imaging device is exemplified as the imaging device 100.

[0050] The photoelectric conversion unit 12 of each pixel 10 has a connection with the accumulation control line 31. During the operation of the imaging device 100, a predetermined voltage is applied to the accumulation control line 31. For example, when positive charges among the positive and negative charges generated by photoelectric conversion are used as signal charges, a positive voltage of about 10V can be applied to the accumulation control line 31 during the operation of the imaging device 100. Hereinafter, the case where holes are used as signal charges will be exemplified.

[0051] In the configuration illustrated in FIG. 2, the signal detection circuit 14 includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. As will be described in detail with reference to the drawings later, the signal detection transistor 22, the address transistor 24, and the reset transistor 26 are, for example, field effect transistors (FETs: Field Effect Transistors) formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12. Hereinafter, an example in which an N-channel MOSFET (Metal Oxide Semiconductor FET) is used as the transistor will be described unless otherwise specified. Note that which of the two impurity regions of the FET corresponds to the source and the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and the drain can vary depending on the operating state of the FET. That is, each of the signal detection transistor 22, the address transistor 24, and the reset transistor 26 includes an impurity region as one of the source and the drain and an impurity region as the other of the source and the drain.

[0052] As schematically shown in FIG. 2, the gate of the signal detection transistor 22 is electrically connected to the photoelectric conversion unit 12. The signal detection transistor 22 is an example of a transistor that includes a first impurity region as one of the source and the drain. In the illustrated example, the charge storage node FD that connects the gate of the signal detection transistor 22 to the photoelectric conversion unit 12 has a function of temporarily holding the charges generated by the photoelectric conversion unit 12. By applying a predetermined voltage to the charge storage control line 31 during operation, holes can be accumulated in the charge storage node FD as signal charges, for example. As will be described with reference to the drawings later, the charge storage node FD includes a part of an impurity region formed in the semiconductor substrate 60.

[0053] The drain of the signal detection transistor 22 is connected to a power supply wiring 32 that supplies a power supply voltage VDD to each pixel 10 during the operation of the imaging device 100. The source of the signal detection transistor 22 is connected to the drain of the address transistor 24 and is connected to the vertical signal line 35 via the address transistor 24. The signal detection transistor 22 outputs a signal voltage corresponding to the amount of signal charges accumulated in the charge accumulation node FD by receiving the supply of the power supply voltage VDD. The power supply voltage VDD is, for example, a voltage higher than a reset voltage described later. As a specific example, the power supply voltage VDD is 2V or more and 5V or less, and as an example, it is about 3.3V. The power supply voltage VDD may be 3V or more and 5V or less.

[0054] An address signal line 34 is connected to the gate of the address transistor 24 connected between the signal detection transistor 22 and the vertical signal line 35. The vertical scanning circuit 42 applies a row selection signal for controlling on and off of the address transistor 24 to the address signal line 34. By this, the output of the signal detection transistor 22 of the selected pixel 10 can be read out to the corresponding vertical signal line 35. Note that the arrangement of the address transistor 24 is not limited to the example shown in FIG. 2, and it may be between the drain of the signal detection transistor 22 and the power supply wiring 32.

[0055] The vertical signal line 35 is connected to the source of the address transistor 24. A load circuit 45 and a column signal processing circuit 47 are connected to each of the vertical signal lines 35. The load circuit 45 forms a source follower circuit together with the signal detection transistor 22. The column signal processing circuit 47, also called a row signal accumulation circuit, performs noise suppression signal processing typified by correlated double sampling and analog-digital conversion. The horizontal signal readout circuit 44 sequentially reads signals from a plurality of column signal processing circuits 47 to a horizontal common signal line 49. The load circuit 45 and the column signal processing circuit 47 may be a part of the above-described peripheral circuit 40.

[0056] A reset signal line 36 having a connection with a vertical scanning circuit 42 is connected to the gate of the reset transistor 26. The reset signal line 36 is provided for each row of a plurality of pixels 10, similar to the address signal line 34. The vertical scanning circuit 42 can select, in row units, the pixels 10 to be reset by applying a row selection signal to the address signal line 34. Further, the vertical scanning circuit 42 can switch on and off the reset transistors 26 in the selected rows by applying a reset signal to the gates of the reset transistors 26 via the reset signal line 36. When the reset transistor 26 is turned on, the potential of the charge storage node FD is reset.

[0057] In this example, one of the drain and the source of the reset transistor 26 is connected to the charge storage node FD, and the other of the drain and the source is connected to a corresponding one of the feedback lines 53 provided for each column of the plurality of pixels 10. That is, in this example, the voltage of the feedback line 53 is supplied to the charge storage node FD as a reset voltage for initializing the charges of the photoelectric conversion unit 12.

[0058] In the configuration illustrated in FIG. 2, the imaging device 100 has a feedback circuit 16 including an inverter amplifier 50 as part of a feedback path. As shown in FIG. 2, the inverter amplifier 50 is provided for each column of the plurality of pixels 10, and the above-described feedback line 53 is connected to an output terminal of a corresponding one of the plurality of inverter amplifiers 50. The inverter amplifier 50 can be a part of the above-described peripheral circuit 40.

[0059] As shown in the figure, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the corresponding column, and an input voltage Vref, which is a positive voltage of, for example, 1 V or in the vicinity of 1 V, is supplied to the non-inverting input terminal of the inverting amplifier 50 during the operation of the imaging device 100. As the input voltage Vref, a voltage of any magnitude within the range of the power supply voltage VDD and the ground can be used. By turning on the address transistor 24 and the reset transistor 26, a feedback path for negatively feeding back the output of the pixel 10 can be formed. By forming the feedback path, the voltage of the vertical signal line 35 converges to the input voltage Vref to the non-inverting input terminal of the inverting amplifier 50. In other words, by forming the feedback path, the voltage of the charge storage node FD is reset to a voltage such that the voltage of the vertical signal line 35 becomes Vref. The voltage when the voltage of the charge storage node FD is reset is also referred to as the reset voltage. The reset voltage is, for example, about 0.5 V. By forming the feedback path, it is possible to reduce the reset noise generated when the reset transistor 26 is turned off. Details of the suppression of the reset noise using feedback are described in Patent Document 1. For reference, the entire disclosure of Patent Document 1 is incorporated herein by reference.

[0060] [Device Structure of Pixel] Next, the device structure of the pixel 10 will be described.

[0061] FIG. 3 is a cross-sectional view schematically showing an example of the device structure of the pixel 10 of the imaging device 100 according to Embodiment 1. In FIG. 3, for clarity, the cross-hatching showing the cross-section of the first insulating layer 71 and the interlayer insulating layer 90 is omitted.

[0062] The pixel 10 generally includes a semiconductor substrate 60, a photoelectric conversion unit 12 located above the semiconductor substrate 60, and a conductive structure 89. As shown in the figure, the photoelectric conversion unit 12 is supported by an interlayer insulating layer 90 that covers the semiconductor substrate 60, and the conductive structure 89 is disposed inside the interlayer insulating layer 90. In the illustrated example, the interlayer insulating layer 90 includes a plurality of insulating layers, and the conductive structure 89 includes a part of each of a plurality of wiring layers disposed inside the interlayer insulating layer 90. The plurality of wiring layers disposed in the interlayer insulating layer 90 may include, for example, a wiring layer having an address signal line 34 and a reset signal line 36 as a part thereof, a vertical signal line 35, a power supply wiring 32, and a feedback line 53 as a part thereof. The number of insulating layers and the number of wiring layers in the interlayer insulating layer 90 are not limited to this example and can be arbitrarily set. Also, the wiring layers in which the address signal line 34, the reset signal line 36, the vertical signal line 35, the power supply wiring 32, and the feedback line 53 are disposed can be arbitrarily set.

[0063] The photoelectric conversion unit 12 is disposed on the light incident side of the semiconductor substrate 60. The photoelectric conversion unit 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, a counter electrode 12c disposed on the light incident side, and a photoelectric conversion layer 12b disposed between the pixel electrode 12a and the counter electrode 12c. The photoelectric conversion layer 12b is formed of an organic material or an inorganic material such as amorphous silicon, receives light incident through the counter electrode 12c, and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is continuously formed, for example, across a plurality of pixels 10. The photoelectric conversion layer 12b is formed in a single flat plate shape that covers most of the imaging region R1 of the semiconductor substrate 60 in plan view. That is, the photoelectric conversion layer 12b is shared by a plurality of pixels 10. In other words, the photoelectric conversion unit 12 provided for each pixel 10 includes different parts of the photoelectric conversion layer 12b for each pixel 10. Also, the photoelectric conversion layer 12b may include a layer composed of an organic material and a layer composed of an inorganic material. The photoelectric conversion layer 12b may be provided separately for each pixel 10.

[0064] The counter electrode 12c is a translucent electrode formed from a transparent conductive material such as ITO (Indium Tin Oxide). The term "translucency" as used in this specification means transmitting at least a part of the light of wavelengths that can be absorbed by the photoelectric conversion layer 12b, and it is not essential to transmit light over the entire wavelength range of visible light. The counter electrode 12c is formed continuously over a plurality of pixels 10, for example, in the same manner as the photoelectric conversion layer 12b. That is, the counter electrode 12c is shared by the plurality of pixels 10. In other words, the photoelectric conversion section 12 provided for each pixel 10 has different portions of the counter electrode 12c for each pixel 10. The counter electrode 12c may be provided separately for each pixel 10.

[0065] Although not shown in FIG. 3, the counter electrode 12c has a connection with the above-described accumulation control line 31. During the operation of the imaging device 100, by controlling the potential of the accumulation control line 31 to make the potential of the counter electrode 12c higher than the potential of the pixel electrode 12a, the positive charge among the positive and negative charges generated by photoelectric conversion can be selectively collected by the pixel electrode 12a. By forming the counter electrode 12c in the form of a single continuous layer over a plurality of pixels 10, it becomes possible to apply a predetermined voltage to the counter electrodes 12c of the plurality of pixels 10 all at once. The signal charges collected by the pixel electrode 12a are accumulated in a charge accumulation region 67n, which will be described later, that is electrically connected to the photoelectric conversion section 12 via a conductive structure 89. Note that when negative charges are used as the signal charges, a voltage is applied to the counter electrode 12c such that the potential of the counter electrode 12c is lower than the potential of the pixel electrode 12a.

[0066] The pixel electrode 12a is an electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to impart conductivity. The pixel electrode 12a is electrically separated from the pixel electrodes 12a of other adjacent pixels 10 by being spatially separated from them.

[0067] The conductive structure 89 includes, for example, a plurality of wirings and plugs formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide, and a polysilicon plug, and one end thereof is connected to the pixel electrode 12a. By connecting the other end of the conductive structure 89 to a circuit element formed on the semiconductor substrate 60, the pixel electrode 12a of the photoelectric conversion unit 12 and the circuit on the semiconductor substrate 60 are electrically connected to each other.

[0068] Here, attention is paid to the semiconductor substrate 60. As schematically shown in FIG. 3, the semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61. The semiconductor substrate 60 has, as one or more semiconductor layers, an n-type semiconductor layer 62n on the support substrate 61 and a p-type semiconductor layer 65p on the n-type semiconductor layer 62n. The support substrate 61 and the p-type semiconductor layer 65p are electrically connected to each other by a p-type region 64a having a relatively high impurity concentration. The impurity concentration of the p-type region 64a is, for example, higher than the impurity concentration of the p-type semiconductor layer 65p.

[0069] The semiconductor substrate 60 has a first surface S1. The first surface S1 is a surface on which circuit elements such as transistors are arranged. In the example shown in FIG. 3, each transistor of the signal detection circuit 14 is arranged on the first surface S1. Also, in the example shown in FIG. 3, the first surface S1 is the upper surface of the semiconductor substrate 60 and is the main surface of the semiconductor substrate 60 on the side where light is incident. Note that the first surface S1 may be the lower surface of the semiconductor substrate 60. In this case, the top and bottom of the semiconductor substrate 60 are reversed compared to the example shown in FIG. 3, and the conductive structure 89 includes a through electrode that penetrates the semiconductor substrate 60.

[0070] The support substrate 61 contains an impurity of a second conductivity type different from the first conductivity type described later. In the present embodiment, the second conductivity type is p-type. Here, a p-type silicon substrate is exemplified as the support substrate 61. The p-type impurity contained in the support substrate 61 is, for example, boron.

[0071] The support substrate 61 has a connection with a substrate contact provided outside the imaging region R1, not shown in FIG. 3. During the operation of the imaging device 100, the potentials of the support substrate 61 and the p-type semiconductor layer 65p are controlled via the substrate contact. During the operation of the imaging device 100, for example, the potentials of the support substrate 61 and the p-type semiconductor layer 65p are controlled to about 0V.

[0072] The n-type semiconductor layer 62n contains impurities of the first conductivity type. The n-type semiconductor layer 62n is an example of the first layer. The n-type semiconductor layer 62n is located between the p-type semiconductor layer 65p and the support substrate 61. In the present embodiment, the first conductivity type is n-type. The n-type impurities contained in the n-type semiconductor layer 62n are, for example, phosphorus. Details of the n-type semiconductor layer 62n will be described later.

[0073] Although not shown in FIG. 3, a well contact (not shown) is connected to the n-type semiconductor layer 62n. The well contact is provided outside the imaging region R1, and during the operation of the imaging device 100, the potential of the n-type semiconductor layer 62n is constantly controlled via the well contact. That is, a constant voltage is applied to the n-type semiconductor layer 62n during the operation of the imaging device 100. During the operation of the imaging device 100, for example, the potential of the n-type semiconductor layer 62n is controlled to about 0.5V. By providing the n-type semiconductor layer 62n, the inflow of carriers from the support substrate 61 or the peripheral circuit 40 to the charge storage region 67n, which stores signal charges, is suppressed. That is, since the n-type semiconductor layer 62n is provided between the support substrate 61 and the p-type semiconductor layer 65p, the dark current flowing into the charge storage region 67n can be suppressed.

[0074] As shown in FIG. 3, the imaging device 100 includes a voltage supply circuit 39. The voltage supply circuit 39 applies a constant voltage to the n-type semiconductor layer 62n. Note that a constant voltage may be applied to the n-type semiconductor layer 62n from an external voltage supply circuit.

[0075] The p-type semiconductor layer 65p is an example of a second layer positioned closer to the first surface S1 than the n-type semiconductor layer 62n. That is, the p-type semiconductor layer 65p is provided on the first surface S1 side of the n-type semiconductor layer 62n. The upper surface of the p-type semiconductor layer 65p, which is the surface opposite to the n-type semiconductor layer 62n side of the p-type semiconductor layer 65p, constitutes at least a part of the first surface S1, for example. In the example shown in FIG. 3, the p-type semiconductor layer 65p is the layer closest to the photoelectric conversion unit 12 among the semiconductor layers included in the semiconductor substrate 60. Also, the p-type semiconductor layer 65p is provided in contact with the upper surface of the n-type semiconductor layer 62n.

[0076] Each of the n-type semiconductor layer 62n and the p-type semiconductor layer 65p is formed, for example, by ion implantation of impurities into a semiconductor layer on the support substrate 61 formed by epitaxial growth.

[0077] The impurity concentration of the p-type semiconductor layer 65p is higher than that of the support substrate 61, for example. The impurity concentration of the support substrate 61 can be, for example, about 10 15 cm -3 or so. The impurity concentration of the p-type semiconductor layer 65p can be, for example, about 10 17 cm -3 or so. Note that the impurity concentration of the support substrate 61 may be higher than that of the p-type semiconductor layer 65p.

[0078] As schematically shown in FIG. 3, the semiconductor substrate 60 further includes a charge storage region 67n, an impurity region 68an, an impurity region 68bn, an impurity region 68cn, an impurity region 68dn, and a blocking structure 69. The charge storage region 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the blocking structure 69 are located in the p-type semiconductor layer 65p. Each of the charge storage region 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the blocking structure 69 is provided near the first surface S1 of the p-type semiconductor layer 65p, and a part thereof is located on the first surface S1. The charge storage region 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the blocking structure 69 are provided at different positions in a plan view. The blocking structure 69 is also called an element isolation region. Details of the blocking structure 69 will be described later.

[0079] The charge storage region 67n is an impurity region of the first conductivity type and is an example of a second impurity region that stores charges photoelectrically converted by the photoelectric conversion unit 12. In the example shown in FIG. 3, the charge storage region 67n includes a first region 67a and a second region 67b that is located within the first region 67a and has a higher impurity concentration than the first region 67a. The impurity concentration of the first region 67a is, for example, 10 17 cm -3 or so, and the impurity concentration of the second region 67b is, for example, 3×10 18 cm -3 or so. Here, "×" means multiplication.

[0080] An insulating layer is disposed on the first surface S1 of the semiconductor substrate 60. In the example shown in FIG. 3, the first surface S1 of the semiconductor substrate 60 is covered by a first insulating layer 71, a second insulating layer 72, and a third insulating layer 73. The first insulating layer 71 is, for example, a thermal oxide film of silicon. The second insulating layer 72 is, for example, a silicon dioxide layer, and the third insulating layer 73 is, for example, a silicon nitride layer. The second insulating layer 72 may have a stacked structure including a plurality of insulating layers. Similarly, the third insulating layer 73 may also have a stacked structure including a plurality of insulating layers.

[0081] The stacked structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 has a contact hole h1 over the second region 67b of the charge storage region 67n. In the example shown in FIG. 3, a contact plug Cp1, which is part of the conductive structure 89, is connected to the second region 67b through the contact hole h1. As a result, the charge storage region 67n is electrically connected to the pixel electrode 12a of the photoelectric conversion unit 12 through the conductive structure 89. Signal charges generated in the photoelectric conversion unit 12 are stored in the charge storage region 67n.

[0082] The junction capacitance formed by the pn junction between the p-type semiconductor layer 65p as a p-well and the n-type charge storage region 67n functions as a charge storage region that temporarily holds signal charges. Also, it can be said that the conductive structure 89 and the n-type charge storage region 67n constitute at least part of the above-described charge storage node FD.

[0083] Note that the formation of the second region 67b in the charge storage region 67n is not essential. However, by connecting the contact plug Cp1 to the second region 67b having a relatively high impurity concentration, an effect of reducing contact resistance can be obtained.

[0084] On the first surface S1 of the semiconductor substrate 60, the signal detection transistor 22, the address transistor 24, and the reset transistor 26 of the above-described signal detection circuit 14 are formed. The signal detection circuit 14 in the pixel 10 is electrically separated from the signal detection circuits 14 in other adjacent pixels 10 by arranging a blocking structure 69 between the adjacent pixels 10. Also, by arranging a blocking structure 69 between the signal detection transistor 22 and the reset transistor 26, the signal detection transistor 22 and the reset transistor 26 are electrically separated.

[0085] Among the signal detection circuits 14, the reset transistor 26 includes an n-type charge storage region 67n as one of the drain and the source, and an n-type impurity region 68an as the other of the drain and the source. The reset transistor 26 further includes a gate electrode 26e on the first insulating layer 71, and a portion of the first insulating layer 71 located between the gate electrode 26e and the semiconductor substrate 60 functions as a gate insulating film of the reset transistor 26. The gate electrode 26e is electrically connected to the reset signal line 36.

[0086] A contact plug Cp2 is connected to the impurity region 68an through a contact hole h2 formed in the impurity region 68an formed in the stacked structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73. The contact plug Cp2 is electrically connected to the feedback line 53.

[0087] The impurity concentrations of the impurity region 68an, the impurity region 68bn, the impurity region 68cn, and the impurity region 68dn are, for example, higher than the impurity concentration of the first region 67a of the charge storage region 67n.

[0088] The signal detection transistor 22 includes an impurity region 68bn, an impurity region 68cn, and a gate electrode 22e on the first insulating layer 71. The impurity region 68bn functions as, for example, the drain of the signal detection transistor 22, and the impurity region 68cn functions as, for example, the source of the signal detection transistor 22. The portion of the first insulating layer 71 located between the gate electrode 22e and the semiconductor substrate 60 functions as the gate insulating film of the signal detection transistor 22. Also, as schematically shown by a solid line in FIG. 4 described later, the gate electrode 22e is electrically connected to the contact plug Cp1. In this example, the gate electrode 22e is connected at a position not shown in the illustrated cross section in the layer where the address signal line 34 and the reset signal line 36 are located, with respect to the portion of the conductive structure 89 that connects the pixel electrode 12a and the contact plug Cp1 to each other. In other words, the conductive structure 89 also has an electrical connection with the gate electrode 22e. Note that the layer involved in the connection between the gate electrode 22e, the pixel electrode 12a, and the contact plug Cp1 is not particularly limited.

[0089] A contact plug Cp3 is connected to the impurity region 68bn through a contact hole h3 on the impurity region 68bn formed in a stacked structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73. The above-described power supply wiring 32 as a source follower power supply is electrically connected to the contact plug Cp3. Therefore, during the operation of the imaging device 100, the power supply voltage VDD is applied to the impurity region 68bn through the contact plug Cp3. The impurity region 68bn is an example of a first impurity region of a first conductivity type.

[0090] The address transistor 24 includes an impurity region 68cn, an impurity region 68dn, and a gate electrode 24e on the first insulating layer 71. In the example shown in FIG. 3, the address transistor 24 is electrically connected to the signal detection transistor 22 by sharing the impurity region 68cn with the signal detection transistor 22. The n-type impurity region 68cn functions as, for example, the drain of the address transistor 24, and the n-type impurity region 68dn functions as, for example, the source of the address transistor 24. The portion of the first insulating layer 71 located between the gate electrode 24e and the semiconductor substrate 60 functions as the gate insulating film of the address transistor 24. Note that although the signal detection transistor 22 and the address transistor 24 share the impurity region 68cn, they each include an impurity region that functions as a source or a drain, and these impurity regions may be electrically connected by plugs, wirings, or the like.

[0091] A contact plug Cp4 is connected to the impurity region 68dn via a contact hole h4 formed in the impurity region 68dn having a stacked structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73. The contact plug Cp4 is electrically connected to the vertical signal line 35.

[0092] Next, in addition to FIG. 3, the blocking structure 69 and the n-type semiconductor layer 62n will be described in detail with reference to FIG. 4 showing the planar layout of the pixel 10. Also, in the following, the layout of each element of the pixel 10 will be described.

[0093] FIG. 4 is a schematic plan view showing an example of the layout of each element in the pixel 10 of the imaging device 100 according to the first embodiment and the first portion 62a of the n-type semiconductor layer 62n. FIG. 4 schematically shows the arrangement of each element of the pixel 10 formed on the first surface S1 of the semiconductor substrate 60 when viewed from a direction perpendicular to the semiconductor substrate 60. In FIG. 4, the contour of the first portion 62a of the n-type semiconductor layer 62n is indicated by a broken line. In FIG. 4, for the sake of explanation, only the signal detection transistor 22 and the reset transistor 26 among the transistors of the signal detection circuit 14 are shown, and the illustration of the address transistor 24 is omitted. Also, in FIG. 4, for ease of viewing, each configuration shown in the plan view is given the same hatching as that of each configuration shown in the cross section of FIG. 3. Also, in FIG. 3 described above, the signal detection transistor 22, the address transistor 24, and the reset transistor 26 are shown so as to appear in one cross section, but this is only for the convenience of explanation. Therefore, there may be a portion that does not match between the cross section obtained when the element layout shown in FIG. 4 is cut along a certain line and the cross section shown in FIG. 3.

[0094] In the example shown in FIG. 4, the impurity region 68bn is arranged closer to the charge storage region 67n than the impurity region 68cn. Also, in the example shown in FIG. 4, the direction in which the charge storage region 67n and the impurity region 68an are arranged in the reset transistor 26 and the direction in which the impurity region 68bn and the impurity region 68cn are arranged in the signal detection transistor 22 are orthogonal, but are not particularly limited. For example, the direction in which the charge storage region 67n and the impurity region 68an are arranged in the reset transistor 26 and the direction in which the impurity region 68bn and the impurity region 68cn are arranged in the signal detection transistor 22 may be parallel.

[0095] As shown in FIGS. 3 and 4, in a plan view, the isolation structure 69 is located between the impurity region 68bn and the charge storage region 67n. Further, the isolation structure 69 is also located between the impurity region 68bn and the impurity region 68an. In this specification, "A is located between B and C" means that at least one of a plurality of line segments connecting any point in B and any point in C passes through A.

[0096] As shown in FIG. 4, in a plan view, the isolation structure 69 is disposed around each of the signal detection transistor 22 and the reset transistor 26. Although not shown, in a plan view, the address transistor 24 is surrounded by the isolation structure 69 together with the signal detection transistor 22. Further, the isolation structure 69 is disposed about 50 nm away from the edge of the impurity region which is the source and drain of each transistor in a plan view. The isolation structure 69 is not in contact with any of, for example, the charge storage region 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, and the impurity region 68dn.

[0097] For the isolation structure 69, for example, implantation separation in which impurities such as p-type impurities are implanted is used. That is, the isolation structure 69 is, for example, an impurity region in which p-type impurities are diffused at a higher concentration than the p-type semiconductor layer 65p. The impurity concentration of the isolation structure 69 can be, for example, 1×10 17 cm -3 or more. The isolation structure 69 may include two or more regions having different impurity concentrations from each other. Note that STI (Shallow Trench Isolation) may be used for the isolation structure 69.

[0098] As shown in FIGS. 3 and 4, the n-type semiconductor layer 62n includes a first portion 62a that overlaps the isolation structure 69 in a plan view and a second portion 62b that is at a position different from the first portion 62a in a plan view.

[0099] The first part 62a is a part where the distance to the first surface S1 is shorter than that of the second part 62b. That is, the shortest distance L1 between the first part 62a and the first surface S1 is shorter than the shortest distance L2 between the second part 62b and the first surface S1.

[0100] As described above, the impurity region 68bn is the drain of the signal detection transistor 22, and when the imaging device 100 operates, for example, a power supply voltage VDD of about 3.3V is applied. Therefore, near the interface between the impurity region 68bn and the p-type semiconductor layer 65p, impact ionization occurs due to a high electric field, and charges different from the signal charges are generated. Such charges different from the signal charges also flow into the charge storage region 67n and the n-type semiconductor layer 62n. By the presence of the blocking structure 69 between the impurity region 68bn and the charge storage region 67n, the inflow of charges different from the signal charges into the charge storage region 67n can be suppressed. Further, by including the first part 62a protruding toward the first surface S1 in the n-type semiconductor layer 62n at a position overlapping the blocking structure 69, charges different from the signal charges heading toward the charge storage region 67n can be made to easily flow into the first part 62a. Thus, the inflow of charges different from the signal charges into the charge storage region 67n, that is, the dark current, can be suppressed.

[0101] The shortest distance L1 is, for example, 450 nm or less. The shortest distance L1 may be 400 nm or less, or may be 350 nm or less. Also, the shortest distance L1 is, for example, 200 nm or more. The difference between the shortest distance L1 and the shortest distance L2 is, for example, 50 nm or more.

[0102] The difference between the shortest distance L1 and the shortest distance L2 may be 100 nm or more, or may be 150 nm or more. Also, the difference between the shortest distance L1 and the shortest distance L2 is, for example, 300 nm or less. The difference between the shortest distance L1 and the shortest distance L2 is the protruding amount of the first part 62a in the n-type semiconductor layer 62n.

[0103] In the examples shown in FIGS. 3 and 4, the first portion 62a entirely overlaps the blocking structure 69 in a plan view. The first portion 62a may have a portion that does not overlap the blocking structure 69 as long as at least a part of the first portion 62a overlaps the blocking structure 69 in a plan view. Further, the first portion 62a does not overlap any of the charge storage region 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, and the impurity region 68dn in a plan view, for example. In the example shown in FIG. 3, the first portion 62a is separated from the blocking structure 69, but the first portion 62a and the blocking structure 69 may be in contact with each other.

[0104] Also, in the example shown in FIG. 3, the first portion 62a is a convex portion in the n-type semiconductor layer 62n. That is, the thickness of the first portion 62a is greater than the thickness around the portion of the first portion 62a in the n-type semiconductor layer 62n due to the first portion 62a protruding toward the first surface S1.

[0105] As shown in FIGS. 3 and 4, the first portion 62a is located between the impurity region 68bn and the charge storage region 67n in a plan view. Also, in the plan view, the first portion 62a overlaps neither the straight line A nor the straight line B that connect a point in the impurity region 68bn and a point in the charge storage region 67n. The straight line A is the line passing through the uppermost side in the drawing plane among the straight lines that connect a point in the impurity region 68bn and a point in the charge storage region 67n in the region between the impurity region 68bn and the charge storage region 67n. The straight line B is the line passing through the lowermost side in the drawing plane among the straight lines that connect a point in the impurity region 68bn and a point in the charge storage region 67n in the region between the impurity region 68bn and the charge storage region 67n. Therefore, since the first portion 62a overlaps neither the straight line A nor the straight line B in the plan view, it overlaps any straight line that connects a point in the impurity region 68bn and a point in the charge storage region 67n. As a result, for any charge different from the signal charge generated at any position near the impurity region 68bn, it becomes easier to flow into the first portion 62a, and the dark current can be further suppressed. Also, in the example shown in FIG. 4, the blocking structure 69 also overlaps any straight line that connects a point in the impurity region 68bn and a point in the charge storage region 67n, similar to the first portion 62a.

[0106] The impurity concentration of the first portion 62a is, for example, 5×10 16 cm -3 or more. The impurity concentration of the first portion 62a may be 1×10 17 cm -3 or more. Also, the impurity concentration of the first portion 62a is, for example, 5×10 17 cm -3 or less. Also, the impurity concentration of the first portion 62a may be higher than or the same as the impurity concentration of the second portion 62b.

[0107] Also, in the example shown in FIG. 4, in addition to the first portion 62a of the n-type semiconductor layer 62n that is located between the impurity region 68bn and the charge storage region 67n in plan view, the first portion 62a includes another first portion 62a that is positioned so as to sandwich the charge storage region 67n. Thereby, the inflow of charges from other pixels 10 into the charge storage region 67n can be suppressed. The two first portions 62a are, for example, parallel to each other in plan view.

[0108] The second portion 62b is a portion having a longer distance to the first surface S1 than the first portion 62a. The second portion 62b is located around the first portion 62a in plan view and includes a portion that does not overlap with the blocking structure 69. The second portion 62b is, for example, a portion other than the first portion 62a in the n-type semiconductor layer 62n and is a flat layer having a substantially constant thickness.

[0109] As shown in FIG. 3, the charge storage region 67n overlaps with the second portion 62b in plan view. Thereby, the distance between the charge storage region 67n and the n-type semiconductor layer 62n becomes longer, and it is possible to suppress the occurrence of charge movement between the charge storage region 67n and the n-type semiconductor layer 62n due to the proximity of the charge storage region 67n and the n-type semiconductor layer 62n. The charge storage region 67n, for example, entirely overlaps with the second portion 62b in plan view. Also, the n-type impurity regions in the p-type semiconductor layer 65p other than the charge storage region 67n may also overlap with the second portion 62b. In the example shown in FIG. 3, the impurity regions 68an, 68bn, 68cn, and 68dn all entirely overlap with the second portion 62b.

[0110] The n-type semiconductor layer 62n is formed, for example, as follows. First, in the region where the pixel 10 is formed, n-type impurities such as phosphorus are ion-implanted into the entire semiconductor layer on the support substrate 61 formed by epitaxial growth, with an implantation energy of about 500 keV. As a result, a portion that does not protrude more than the second portion 62b in the first portion 62a and the second portion 62b are formed. Next, n-type impurities such as phosphorus are ion-implanted at an implantation energy lower than that of the above ion implantation, with respect to the position where the first portion 62a is formed in a plan view of the semiconductor layer. The implantation energy at this time is, for example, 200 keV or more and 400 keV or less. As a result, the remaining portion of the first portion 62a is formed, and the n-type semiconductor layer 62n is formed. The dose amount of the n-type impurities in the ion implantation is, for example, 1×10 13 cm -2 or so.

[0111] Here, regarding the dark current suppression effect by the first portion 62a of the n-type semiconductor layer 62n, the results of evaluating the dark current by simulation will be described. FIG. 5 is a diagram showing the results of simulating the current flowing through the charge storage region 67n. The simulation was performed using commercially available software, TSUPREM-4 and Medici. Specifically, the impurity concentration profile of the device structure was calculated using TSUPREM-4, and the electrical characteristics were obtained using Medici from the calculated impurity concentration profile of the device structure. As the electrical characteristics, when the voltages applied to the charge storage region 67n, the impurity region 68bn, the n-type semiconductor layer 62n, and the support substrate 61 are 0.5 V, 3.3 V, 0.5 V, and 0 V, respectively, the currents flowing through the charge storage region 67n, the impurity region 68bn, and the n-type semiconductor layer 62n were obtained.

[0112] The FD current ratio indicated by the vertical axis in FIG. 5 is a value represented by IFD / (INL + IGW + IFD), where the currents flowing through the charge storage region 67n, the impurity region 68bn, and the n-type semiconductor layer 62n are IFD, INL, and IGW, respectively. Therefore, the lower the FD current ratio, the more the dark current is suppressed.

[0113] The ion implantation energy indicated by the horizontal axis in FIG. 5 is the ion implantation energy of phosphorus when forming the first portion 62a in the calculation of the impurity concentration profile of the device structure. As this ion implantation energy increases, the shortest distance L1 between the first portion 62a and the first surface S1 becomes longer. That is, the first portion 62a is farther from the first surface S1. Also, the vertical axis in FIG. 5 is a logarithmic axis. In the calculation of the impurity concentration profile of the device structure, the ion implantation energy when forming the second portion 62b was set to 500 keV.

[0114] Also, in FIG. 5, in the calculation of the impurity concentration profile of the device structure, the dose amount of phosphorus to be ion implanted is 1×10 13 cm -2 The results when is used are indicated by triangular markers, and the results when the dose amount of phosphorus to be ion implanted is 5×10 12 cm -2 are indicated by round markers. Also, the dashed-dotted line in FIG. 5 indicates the value of the FD current ratio when the first portion 62a is not formed, that is, when an n-type semiconductor layer 62n without protrusion is formed.

[0115] As shown in FIG. 5, it can be seen that the formation of the first portion 62a reduces the FD current ratio and suppresses the dark current. Also, as shown in FIG. 5, as the ion implantation energy decreases, the FD current ratio becomes lower, indicating that the reduction effect of the dark current is high. That is, it is shown that the shorter the shortest distance L1 between the first portion 62a and the first surface S1, the more the dark current can be suppressed. Also, as shown in FIG. 5, it can be seen that the larger the dose amount of phosphorus, the lower the FD current ratio and the higher the reduction effect of the dark current. That is, it is shown that the higher the impurity concentration of the first portion 62a, the more the dark current can be suppressed.

[0116] FIG. 6 is a diagram showing an example of the impurity concentration profile of the device structure used in the simulation. In FIG. 6, the ion implantation energy of phosphorus when forming the first portion 62a is 200 keV, and the dose amount of phosphorus is 1×10 13cm -2 The calculation results of the impurity concentration profile of the device structure when [conditions are met] are shown. Also, in FIG. 6, a dotted pattern is applied to the region where the n-type impurity has diffused, and no pattern is applied to the region where the p-type impurity has diffused. Also, the lines in FIG. 6 are lines connecting points with the same impurity concentration.

[0117] As shown in FIG. 6, it can be seen that in the region overlapping the blocking structure 69 between the charge storage region 67n and the impurity region 68bn in plan view, the first portion 62a protruding more than the second portion 62b is formed. The shortest distance L1 between the first portion 62a and the first surface S1 at this time is about 350 nm. Also, the protruding amount of the first portion 62a in the n-type semiconductor layer 62n is about 150 nm.

[0118] [Another example of the layout of the first portion] Next, another example of the layout of the first portion 62a in the pixel 10 will be described. FIG. 7 is a schematic plan view showing another example of the layout of each element in the pixel 10 of the imaging device 100 according to the first embodiment and the first portion 62a of the n-type semiconductor layer 62n. FIG. 8 is a schematic plan view showing still another example of the layout of each element in the pixel 10 of the imaging device 100 according to the first embodiment and the first portion 62a of the n-type semiconductor layer 62n. In the examples of the layouts shown in FIGS. 7 and 8, the layouts other than the first portion 62a are the same as those in the example of the layout shown in FIG. 4.

[0119] As shown in FIG. 7, the first portion 62a may surround the reset transistor 26 including the charge storage region 67n in plan view. Thereby, the inflow of charges other than the signal charges into the charge storage region 67n can be further suppressed.

[0120] Further, as shown in FIG. 8, the first portion 62a may extend from one end to the other end of the pixel 10 in a predetermined direction in a plan view. In the example shown in FIG. 8, the first portion 62a is continuously formed between two adjacent pixels 10. This facilitates the formation of the first portion 62a and further suppresses the inflow of charges other than signal charges into the charge storage region 67n. Further, the first portion 62a may be continuously formed over all the pixels 10 arranged in the column direction or the row direction. Also, in the example shown in FIG. 8, two first portions 62a completely sandwich the reset transistor 26.

[0121] (Embodiment 2) Next, Embodiment 2 will be described. In Embodiment 1, a camera system including the imaging device according to the present disclosure was described.

[0122] FIG. 9 is a block diagram showing an example of the configuration of a camera system 400 according to Embodiment 2.

[0123] The camera system 400 includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 can be, for example, a smartphone, a digital camera, a video camera, an in-vehicle camera, or the like.

[0124] The lens optical system 601 condenses light on the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, an autofocus lens, a lens group including a zoom lens, and a diaphragm. As the imaging device 602, for example, the imaging device 100 according to Embodiment 1 described above is used.

[0125] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit and is, for example, a CPU (Central Processing Unit).

[0126] The camera signal processing circuit 604 has a function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data from the imaging device 602 and performs processes such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). According to such a configuration, an electronic device including the imaging device 602 as a part thereof can be made smaller.

[0127] Since the camera system 400 according to the present embodiment includes the imaging device 602 using the imaging device 100 according to the above-described Embodiment 1, a camera system with suppressed dark current can be realized.

[0128] (Other embodiments) As described above, the imaging device and the camera system according to one or more aspects have been described based on the embodiments. However, the present disclosure is not limited to these embodiments. As long as the gist of the present disclosure is not deviated from, various modifications conceived by those skilled in the art applied to these embodiments, and forms constructed by combining components in different embodiments are also included in the scope of the present disclosure.

[0129] For example, each of the above-described signal detection transistor 22, address transistor 24, and reset transistor 26 may be an N-channel MOSFET or a P-channel MOSFET. When each transistor is a P-channel MOSFET, the conductivity types of the wells and impurity regions in the semiconductor substrate 60 are reversed from the above description. Therefore, the first conductivity type is p-type and the second conductivity type is n-type. Also, it is not necessary for all of these transistors to be unified into either N-channel MOSFETs or P-channel MOSFETs. When each transistor in the pixel 10 is an N-channel MOSFET and electrons are used as signal charges, the source and drain arrangements in each of these transistors may be swapped with each other.

[0130] Also, for example, in the above embodiment, the imaging device 100 had the feedback circuit 16, but it is not limited to this. The imaging device according to the present disclosure may have a reset voltage supplied from the voltage supply circuit to the charge storage node FD via the reset transistor 26 during the reset operation without having the feedback circuit 16.

[0131] Also, for example, in the above embodiment, the first portion 62a was the convex portion in the n-type semiconductor layer 62n, but it is not limited to this. The first portion 62a may be provided by the substantially constant-thickness n-type semiconductor layer 62n being curved or bent.

[0132] Also, various changes, replacements, additions, omissions, etc. can be made to the above embodiments within the scope of the claims or their equivalents.

Industrial Applicability

[0133] The present disclosure can be used as an imaging device capable of suppressing dark current, and can be used, for example, in image sensors mounted in cameras, surveillance cameras, in-vehicle cameras, etc.

Explanation of Reference Numerals

[0134] 10 pixels 12 Photoelectric conversion section 12a Pixel electrode 12b Photoelectric conversion layer 12c Counter electrode 14 Signal detection circuit 16 Feedback circuit 22 Signal detection transistor 22e, 24e, 26e Gate electrode 24 Address transistor 26 Reset transistor 31 Accumulation control line 32 Power supply wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 39 Voltage supply circuit 40 Peripheral circuit 42 Vertical scanning circuit 44 Horizontal signal readout circuit 45 Load circuit 46 Control circuit 47 Column signal processing circuit 49 Horizontal common signal line 50 Inverting amplifier 53 Feedback line 60 Semiconductor substrate 61 Support substrate 62a First part 62b Second part 62n n-type semiconductor layer 64a p-type region 65p p-type semiconductor layer 67a First region 67b Second region 67n Charge storage region 68an, 68bn, 68cn, 68dn Impurity region 69 Blocking structure 71 First insulating layer 72 Second insulating layer 73 Third insulating layer 89 Conductive structure 90 Interlayer insulating layer 100, 602 Imaging device 400 Camera System 601 Lens Optical System 603 System Controller 604 Camera Signal Processing Circuit Cp1, Cp2, Cp3, Cp4 Contact Plug FD Charge Accumulation Node h1, h2, h3, h4 Contact Hole S1 First Surface

Claims

1. A photoelectric conversion unit that converts light into electric charge, A semiconductor substrate having a first surface, Comprising, The semiconductor substrate, A first layer of a first conductivity type, A second layer of a second conductivity type different from the first conductivity type, located closer to the first surface than the first layer, A first impurity region of the first conductivity type located within the second layer, A second impurity region of the first conductivity type located within the second layer for accumulating the electric charge, A blocking structure located within the second layer and positioned between the first impurity region and the second impurity region in a plan view, Including, The first layer, In the plan view, a first portion overlapping the blocking structure, In the plan view, a second portion at a position different from the first portion and including a portion that does not overlap the blocking structure, Including, The shortest distance between the first portion and the first surface is shorter than the shortest distance between the second portion and the first surface, An imaging device.

2. The first portion is a convex portion in the first layer, The imaging device according to claim 1.

3. The second impurity region overlaps the second portion in the plan view, The imaging device according to claim 1.

4. The blocking structure is implantation separation, The imaging device according to claim 1.

5. Further comprising a voltage supply circuit for supplying a constant voltage to the first layer, The imaging device according to claim 1.

6. Further comprising a transistor having a gate connected to the photoelectric conversion unit, The transistor includes the first impurity region as one of the source and the drain, The imaging device according to claim 1.

7. The photoelectric conversion unit is located above the semiconductor substrate, The imaging device according to claim 1.

8. The first portion does not overlap any straight line connecting a point within the first impurity region and a point within the second impurity region in the plan view, The imaging device according to claim 1.

9. A camera system comprising the imaging device according to any one of claims 1 to 8.

Images