Nitride semiconductor device

Abstract

To provide a nitride semiconductor device in which both increased gate breakdown voltage and reduced on-resistance can be achieved.SOLUTION: A nitride semiconductor device 10 includes: a substrate 18; an electron transit layer 22; an electron supply layer 24; a gate layer 28; a gate electrode 30; a passivation layer 32 covering the electron supply layer 24 and the gate layer 28; a source electrode 34; a drain electrode 36; and a gate electrode 30 formed on the gate layer 28. The gate layer 28 includes a ridge 40 and extensions 42, 44 thinner than the ridge 40. The nitride semiconductor device 10 further includes a gate wiring layer 61 provided on the passivation layer 32. The gate wiring layer 61 is electrically connected to the gate electrode 30 via a gate connection 62 provided within a gate opening 32C formed in the passivation layer 32.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing. A HEMT uses a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conduction path (channel). Power devices using HEMTs are recognized as devices that enable low on-resistance and high-frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron traveling layer composed of a gallium nitride (GaN) layer, and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer. In the electron traveling layer, a 2DEG is formed near the interface of the heterojunction between the electron traveling layer and the electron supply layer. Further, in the nitride semiconductor device of Patent Document 1, a GaN layer doped with acceptor-type impurities (p-type GaN layer) is provided on the electron supply layer and directly under the gate electrode. In this configuration, the p-type GaN layer raises the energy level of the conduction band near the heterojunction interface between the electron traveling layer and the electron supply layer in the region directly below it, so that the channel directly below the p-type GaN layer can be eliminated. Thereby, the normally-off operation of the nitride semiconductor device is realized.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In a HEMT as described in Patent Document 1, in order to achieve more reliable normally-off operation, it is desirable to increase the gate breakdown voltage. However, it is difficult to achieve both an increase in the gate breakdown voltage of the HEMT and a low on-resistance.

[0006] A semiconductor device according to an aspect of the present disclosure includes a substrate, an electron traveling layer formed above the substrate, an electron supply layer formed on the electron traveling layer and having a larger bandgap than the electron traveling layer, a gate layer formed on the electron supply layer and having acceptor impurities, a gate electrode formed on the gate layer, a passivation layer covering the electron supply layer and the gate layer and including a source opening, a gate opening, and a drain opening arranged to be aligned in a first direction, a gate wiring layer provided on the passivation layer, a source electrode in contact with the electron supply layer through the source opening, and a drain electrode in contact with the electron supply layer through the drain opening. The gate layer includes a ridge portion in contact with the electron supply layer and including an upper surface of the gate layer, and an extending portion in contact with the electron supply layer and extending in the first direction from the ridge portion and thinner than the ridge portion. The gate layer and the gate opening are located between the source opening and the drain opening in the first direction, and the gate wiring layer is electrically connected to the gate electrode through a gate connection portion provided in the gate opening. [Brief Description of the Drawings]

[0007]

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[0008] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, in order to make the drawings and description concise and clear, the components shown in the drawings are not necessarily drawn to scale. Further, in order to make the drawings concise and clear, hatching may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0010] [Schematic Structure of Nitride Semiconductor Device] With reference to FIGS. 1 to 5, an exemplary nitride semiconductor device 10 according to an embodiment will be described. In this embodiment, the nitride semiconductor device 10 may be configured as a semiconductor chip on which a high electron mobility transistor (HEMT) is formed. FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to an embodiment. FIG. 2 is an enlarged plan view of the nitride semiconductor device 10. FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 in FIG. 2. FIG. 4 is an enlarged view of a part of FIG. 3. FIG. 5 is an enlarged view of a part of FIG. 4.

[0011] The Z-axis direction of the XYZ axes orthogonal to each other shown in FIGS. 1 to 5 is a direction orthogonal to the plane of the substrate 18 (see FIG. 3). Note that the term "plan view" used in this specification means viewing the nitride semiconductor device 10 from above along the Z-axis direction unless otherwise explicitly specified.

[0012] As shown in FIG. 1, the nitride semiconductor device 10 may include a gate pad 12, a source pad 14, and a drain pad 16 formed on a rectangular upper surface 10A in plan view. The gate pad 12, the source pad 14, and the drain pad 16 may be electrically connected to the gate electrode, the source electrode, and the drain electrode of the HEMT formed in the semiconductor chip, respectively. The gate pad 12, the source pad 14, and the drain pad 16 can constitute external connection terminals of the nitride semiconductor device 10.

[0013] In the example of FIG. 1, the nitride semiconductor device 10 includes a plurality of source pads 14 and a plurality of drain pads 16. The plurality of source pads 14 and the plurality of drain pads 16 may be alternately arranged in the X-axis direction. The number of pads 12, 14, 16 arranged on the upper surface 10A can be arbitrarily determined according to the requirements of a specific application.

[0014] The layout of the gate pad 12, the source pad 14, and the drain pad 16 is not limited to the example shown in FIG. 1. The gate pad 12, the source pad 14, and the drain pad 16 can be arranged in any other layout.

[0015] FIG. 3 shows a schematic cross-sectional view of the active region of the HEMT located below the source pad 14 or the drain pad 16 shown in FIG. 1. As shown in FIG. 3, the nitride semiconductor device 10 may include a substrate 18 and a buffer layer 20 formed on the substrate 18.

[0016] The substrate 18 can be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the substrate 18 may be a Si substrate. The thickness of the substrate 18 can be, for example, 200 μm or more and 1500 μm or less.

[0017] The buffer layer 20 may include one or more nitride semiconductor layers. The buffer layer 20 can be composed of any material that can suppress the warping and cracking of the nitride semiconductor device 10 caused by the difference in the coefficient of thermal expansion between the substrate 18 and the layer formed on the buffer layer 20 (such as the electron traveling layer 22 described later). For example, the buffer layer 20 can include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 20 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0018] In one example, the buffer layer 20 can include a first buffer layer that is an AlN layer formed on the substrate 18 and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be, for example, an AlN layer having a thickness of 100 nm to 300 nm, while the second buffer layer may include a plurality of AlGaN layers having different compositions and each having a thickness of 100 nm to 300 nm. In order to suppress the leakage current in the buffer layer 20, impurities may be introduced into a part of the buffer layer 20 to make the buffer layer 20 semi-insulating. In that case, the impurities are, for example, carbon (C) or iron (Fe), and the concentration of the impurities can be, for example, 4×10 16 cm -3 or more.

[0019] The nitride semiconductor device 10 further includes an electron traveling layer 22 and an electron supply layer 24 formed on the electron traveling layer 22. The electron transport layer 22 may be formed on the buffer layer 20. The electron transport layer 22 is composed of a first nitride semiconductor. The first nitride semiconductor may contain GaN. In one example, the thickness of the electron transport layer 22 may be 0.5 μm or more and 2 μm or less. In addition, in order to suppress the leakage current in the electron transport layer 22, by introducing impurities into a part of the electron transport layer 22, the region other than the surface layer region of the electron transport layer 22 may be made semi-insulating. In this case, the impurity may be, for example, C. The impurity concentration in the electron transport layer 22 may be, for example, 4×10 16 cm -3 or more.

[0020] That is, the electron transport layer 22 may include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer may be formed on the buffer layer 20. The C-doped GaN layer can have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer can be 5×10 17 cm -3 or more and 9×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer and can have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer is in contact with the electron supply layer 24. In one example, the electron transport layer 22 may include a C-doped GaN layer with a thickness of 0.4 μm and an undoped GaN layer with a thickness of 0.4 μm. Also, the C concentration in the C-doped GaN layer may be about 2×10 19 cm -3 or so.

[0021] The electron supply layer 24 is composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The second nitride semiconductor may contain AlGaN. In one example, the electron supply layer 24 is composed of Al x Ga 1-x N, where x is 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The electron supply layer 24 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 24 may have a thickness of 8 nm or more.

[0022] The first nitride semiconductor (e.g., GaN) constituting the electron transport layer 22 and the second nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 24 have different lattice constants from each other. Therefore, the electron transport layer 22 and the electron supply layer 24 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 22 and the electron supply layer 24 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 22 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 26 spreads in the electron transport layer 22 at a position close to the hetero-junction interface between the electron transport layer 22 and the electron supply layer 24 (for example, within a range of about several nm from the interface). The 2DEG 26 in the electron transport layer 22 functions as a channel of the nitride semiconductor device 10. The sheet carrier density of the 2DEG 26 generated in the electron transport layer 22 can be increased by increasing at least one of the Al composition and the thickness of the electron supply layer 24.

[0023] (Gate layer) The nitride semiconductor device 10 further includes a gate layer 28 formed on the electron supply layer 24. The gate layer 28 may be formed on a part of the electron supply layer 24. The gate layer 28 includes a lower surface 28B in contact with the electron supply layer 24 and an upper surface 28A opposite to the lower surface 28B. Details of the shape of the gate layer 28 will be described later.

[0024] The gate layer 28 is composed of a third nitride semiconductor containing acceptor-type impurities. The third nitride semiconductor may include GaN. In the present embodiment, the gate layer 28 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 28 is 7×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0025] (Gate electrode) As shown in FIGS. 3 and 4, the nitride semiconductor device 10 further includes a gate electrode 30 in contact with the upper surface 28A of the gate layer 28. The gate electrode 30 has an upper surface 30A and a lower surface on the opposite side of the upper surface 30A. The lower surface of the gate electrode 30 is in contact with the upper surface 28A of the gate layer 28.

[0026] The gate electrode 30 is composed of one or a plurality of metal layers. The gate electrode 30 is, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode 30 may be composed of a first metal layer formed of a material containing Ti and a second metal layer laminated on the first metal layer and formed of a material containing TiN. The gate electrode 30 forms a Schottky junction with the gate layer 28. Details of the shape of the gate electrode 30 will be described later.

[0027] (Passivation layer) As shown in FIG. 3, the nitride semiconductor device 10 may further include a passivation layer 32 that covers the electron supply layer 24 and the gate layer 28. As shown in FIG. 4, the passivation layer 32 may cover a part of the gate electrode 30, for example, the side surface 30C and the peripheral portion of the upper surface 30A.

[0028] As shown in FIG. 3, the passivation layer 32 has a source opening 32A, a drain opening 32B, and a gate opening 32C arranged side by side in the X-axis direction. In this specification, the X-axis direction corresponds to the first direction in which the source opening 32A, the drain opening 32B, and the gate opening 32C are arranged.

[0029] The source opening 32A and the drain opening 32B are separated in the X-axis direction. The gate layer 28 is located between the source opening 32A and the drain opening 32B. Specifically, the gate layer 28 may be between the source opening 32A and the drain opening 32B and closer to the source opening 32A than the drain opening 32B.

[0030] The gate opening 32C is located between the source opening 32A and the drain opening 32B, and is formed on the gate layer 28 with the gate electrode 30 interposed therebetween. The gate opening 32C is located between the source opening 32A and the drain opening 32B in the X-axis direction, and is spaced apart from each of the source opening 32A and the drain opening 32B in the X-axis direction.

[0031] The passivation layer 32 may be formed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON).

[0032] The passivation layer 32 has a first passivation layer 32D formed on the electron supply layer 24 and a second passivation layer 32E formed on the first passivation layer 32D.

[0033] An example of the first passivation layer 32D is formed on the region in the electron supply layer 24 where the gate layer 28 is not formed and on the region in the gate layer 28 where the gate electrode 30 is not formed. It can be said that the first passivation layer 32D is in contact with and covers the upper surfaces of the above regions of the gate layer 28 and the electron supply layer 24. The first passivation layer 32D may be formed on the peripheral portion of the upper surface 30A of the gate electrode 30.

[0034] The second passivation layer 32E is formed on the first passivation layer 32D. A field plate electrode 53 is embedded between the first passivation layer 32D and the second passivation layer 32E in the passivation layer 32. Details of the field plate electrode 53 will be described later.

[0035] The thickness of the first passivation layer 32D is, for example, 80 nm or more and 120 nm or less. The thickness of the second passivation layer 32E is, for example, 100 nm or more and 200 nm or less. The thickness of the passivation layer 32, that is, the sum of the thickness of the first passivation layer 32D and the thickness of the second passivation layer 32E is, for example, 180 nm or more and 220 nm or less. An example of the first passivation layer 32D is thicker than the second passivation layer 32E. An example of the first passivation layer 32D has the same thickness as the second passivation layer 32E. An example of the first passivation layer 32D is thinner than the second passivation layer 32E.

[0036] The thickness of the first passivation layer 32D, the thickness of the second passivation layer 32E, and the thickness of the passivation layer 32 may be the thickness of the portion formed over the region where the gate layer 28 is not formed in the electron supply layer 24. Alternatively, the thickness of the first passivation layer 32D, the thickness of the second passivation layer 32E, and the thickness of the passivation layer 32 may be the thickness of the portion formed over the region where the gate layer 28 is formed in the electron supply layer 24.

[0037] The first passivation layer 32D and the second passivation layer 32E may be formed of the same material or may be formed of different materials. An example of the first passivation layer 32D and the second passivation layer 32E are both formed of SiN.

[0038] (Source electrode and drain electrode) The nitride semiconductor device 10 includes a source electrode 34 in contact with the electron supply layer 24 through the source opening 32A. Since at least a part of the source electrode 34 is filled in the source opening 32A, it can make an ohmic contact with the 2DEG 26 directly under the electron supply layer 24 through the source opening 32A.

[0039] The nitride semiconductor device 10 includes a drain electrode 36 in contact with the electron supply layer 24 through the drain opening 32B. Since at least a part of the drain electrode 36 is filled in the drain opening 32B, an ohmic contact can be made with the 2DEG 26 directly below the electron supply layer 24 through the drain opening 32B.

[0040] The source electrode 34 and the drain electrode 36 can be composed of one or a plurality of metal layers. Examples of the above metal layers include a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. An example of the source electrode 34 and the drain electrode 36 composed of a plurality of metal layers is a structure (Ti layer / AlCu layer / Ti layer / TiN layer) in which a Ti layer, an AlCu layer, a Ti layer, and a TiN layer are laminated in this order. An example of the source electrode 34 and the drain electrode 36 is formed of the same material. The source electrode 34 and the drain electrode 36 may be formed of different materials.

[0041] (Field plate electrode) The nitride semiconductor device 10 includes a field plate electrode 53 located between the gate opening 32C and the drain opening 32B, that is, between the gate electrode 30 and the drain electrode 36. The field plate electrode 53 is embedded in the passivation layer 32 between the gate opening 32C and the drain opening 32B in the X-axis direction and between the first passivation layer 32D and the second passivation layer 32E. The field plate electrode 53 serves to relieve the electric field concentration near the end of the gate layer 28 when a drain voltage is applied to the drain electrode 36 in a zero-bias state where no gate voltage is applied to the gate electrode 30. Although not shown in the drawings, the field plate electrode 53 is electrically connected to the source electrode 34.

[0042] The field plate electrode 53 includes a first end portion 53A which is an end portion in the X-axis direction, and a second end portion 53B located on the opposite side of the first end portion 53A. The first end portion 53A is an end portion on the side closer to the gate opening 32C in the field plate electrode 53. The second end portion 53B is an end portion on the side closer to the drain opening 32B in the field plate electrode 53.

[0043] The first end portion 53A of the field plate electrode 53 is located above the gate layer 28 and is spaced apart from the gate opening 32C. An example of the first end portion 53A is located above a second extending portion 44, which will be described later, in the gate layer 28. The second end portion 53B of the field plate electrode 53 is located between the gate layer 28 and the drain electrode 36 and is spaced apart from the drain opening 32B. The second end portion 53B is located, for example, at a position close to the gate opening 32C between the gate opening 32C and the drain opening 32B.

[0044] The field plate electrode 53 can be composed of one or a plurality of metal layers. For example, the field plate electrode 53 is composed of a TiN layer or a combination of a Ti layer and a TiN layer. An example of the field plate electrode 53 is formed of a material different from that of the source electrode 34. An example of the field plate electrode 53 is formed of the same material as the gate electrode 30.

[0045] The thickness of the field plate electrode 53 is, for example, 20 nm or more. The thickness of the field plate electrode 53 is, for example, 50 nm or less. (Gate wiring) The nitride semiconductor device 10 includes a gate wiring 60. The gate wiring 60 includes a gate wiring layer 61 provided on the passivation layer 32 and a gate connection portion 62 provided in the gate opening 32C. The gate wiring layer 61 is formed on the passivation layer 32 and is electrically connected to the gate pad 12 shown in FIG. 1. The gate connection portion 62 is filled in the gate opening 32C. The gate wiring layer 61 is electrically connected to the gate electrode 30 via the gate connection portion 62. The thicknesses of the gate wiring layer 61 and the gate connection portion 62 will be described later.

[0046] The gate wiring 60 can be composed of one or a plurality of metal layers. Examples of the metal layer include, for example, a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. An example of the gate wiring 60 is a structure in which a Ti layer, an AlCu layer, a Ti layer, and a TiN layer are laminated in this order. In the gate wiring 60, the gate wiring layer 61 and the gate connection portion 62 may be formed of the same material or different materials. An example of the gate wiring layer 61 and the gate connection portion 62 is formed of the same material. An example of the gate wiring layer 61 and the gate connection portion 62 is formed of the same material and is formed of the same material as either one or both of the source electrode 34 and the drain electrode 36.

[0047] (Cross-sectional shape of the gate layer) As shown in FIG. 4, the gate layer 28 includes a ridge portion 40 that is in contact with the electron supply layer 24 and includes an upper surface 28A, and a first extending portion 42 and a second extending portion 44 that are in contact with the electron supply layer 24 and extend outward in plan view from the ridge portion 40 and are thinner than the ridge portion 40. In the present disclosure, the first extending portion 42 and the second extending portion 44 may be collectively referred to as an “extending portion”. Since the first extending portion 42 and the second extending portion 44 are thinner than the ridge portion 40, the upper surface 42A of the first extending portion 42 and the upper surface 44A of the second extending portion 44 are located below the upper surface 28A of the gate layer 28 in the Z-axis direction. The side surface 28C of the gate layer 28 connects the upper surface 28A of the gate layer 28 to the upper surface 42A of the first extending portion 42 and the upper surface 44A of the second extending portion 44.

[0048] The first extending portion 42 extends from the ridge portion 40 toward the source opening 32A. The first extending portion 42 partially covers the surface of the electron supply layer 24 between the ridge portion 40 and the source opening 32A in plan view. The first extending portion 42 does not reach the source electrode 34 embedded in the source opening 32A.

[0049] The second extending portion 44 extends from the ridge portion 40 toward the drain opening 32B. The second extending portion 44 partially covers the surface of the electron supply layer 24 between the ridge portion 40 and the drain opening 32B in plan view. The second extending portion 44 does not reach the drain electrode 36 embedded in the drain opening 32B.

[0050] The ridge portion 40 is between the first extending portion 42 and the second extending portion 44, and is integrally formed with the first extending portion 42 and the second extending portion 44. Due to the presence of the first extending portion 42 and the second extending portion 44, the lower surface 28B of the gate layer 28 has a larger area than the upper surface 28A. In the example shown in FIG. 4, the second extending portion 44 may extend longer toward the outside of the ridge portion 40 in plan view than the first extending portion 42. That is, the second extending portion 44 may have a dimension in the X-axis direction larger than that of the first extending portion 42. The first extending portion 42 may have a dimension in the X-axis direction, for example, of 0.2 μm or more and 0.3 μm or less. On the other hand, the second extending portion 44 may have a dimension in the X-axis direction, for example, of 0.2 μm or more and 0.6 μm or less.

[0051] The ridge portion 40 corresponds to a relatively thick portion of the gate layer 28. The thickness of the ridge portion 40 is, for example, 80 nm or more and 150 nm or less. In one example, the ridge portion 40 may have a thickness greater than 110 nm. The first extending portion 42 and the second extending portion 44 have a thickness smaller than that of the ridge portion 40. In one example, the first extending portion 42 and the second extending portion 44 may have a thickness of half or less of the thickness of the ridge portion 40. Each of the thicknesses of the first extending portion 42 and the second extending portion 44 is, for example, 20 nm or less. Each of the thicknesses of the first extending portion 42 and the second extending portion 44 is, for example, 5 nm or more.

[0052] As shown in FIG. 4, an example of the first extending portion 42 includes a first step portion 46 having a substantially constant thickness and a first tapered portion 48 connecting the first step portion 46 to the ridge portion 40. Here, in this specification, "substantially constant thickness" means that the thickness is within the range of manufacturing variations (for example, 20%). The thickness of the first step portion 46 is, for example, 5 nm or more and 20 nm or less.

[0053] The first tapered portion 48 is formed at the connection portion of the first extending portion 42 with the ridge portion 40. The first tapered portion 48 has a shape in which the thickness gradually decreases toward the tip side of the first extending portion 42. In other words, the first tapered portion 48 has a shape in which the thickness gradually decreases as it moves away from the ridge portion 40. The thickness of the first tapered portion 48 is equal to or greater than the thickness of the first stepped portion 46 and less than the thickness of the ridge portion 40. The first extending portion 42 may have a shape without the first tapered portion 48.

[0054] Similarly, an example of the second extending portion 44 includes a second stepped portion 50 having a substantially constant thickness and a second tapered portion 52 connecting the second stepped portion 50 to the ridge portion 40. The thickness of the second stepped portion 50 is, for example, 5 nm or more and 20 nm or less. The thickness of the second tapered portion 52 may be equal to or greater than the thickness of the second stepped portion 50 and less than the thickness of the ridge portion 40. The thickness of the second stepped portion 50 is, for example, 5 nm or more and 20 nm or less.

[0055] The second tapered portion 52 is formed at the connection portion of the second extending portion 44 with the ridge portion 40. The second tapered portion 52 has a shape in which the thickness gradually decreases toward the tip side of the second extending portion 44. In other words, the second tapered portion 52 has a shape in which the thickness gradually decreases as it moves away from the ridge portion 40. The thickness of the second tapered portion 52 is equal to or greater than the thickness of the second stepped portion 50 and less than the thickness of the ridge portion 40. The second extending portion 44 may have a shape without the second tapered portion 52.

[0056] The first tapered portion 48 and the second tapered portion 52 correspond to tapered portions that are formed at the connection portion with the ridge portion 40 and whose thickness gradually decreases toward the tip side of the extending portion. Note that one or both of the first tapered portion 48 and the second tapered portion 52 may be omitted.

[0057] As shown in FIG. 5, an example of the extending portion includes a trench 55 formed at the connection portion with the ridge portion 40. Hereinafter, with reference to FIG. 5, the trench 55 provided in the second extending portion 44 will be described.

[0058] The trench 55 is a groove formed at the connection portion with the ridge portion 40 in the second extending portion 44. The trench 55 may extend in the Y-axis direction along the ridge portion 40. An example of the trench 55 has a shape in which the depth varies in the X-axis direction. Specifically, the second tapered portion 52 has a shape in which the thickness gradually decreases toward the tip side of the second extending portion 44, and the tip portion thereof is thinner than the second step portion 50. The portion of the second tapered portion 52 that is thinner than the second step portion 50 and the portion where the thickness of the second extending portion 44 gradually increases from this portion toward the second step portion 50 form a substantially V-shaped trench 55. Note that the shape of the trench 55 is not limited to the above shape, and for example, it may have a shape in which the depth is constant in the X-axis direction.

[0059] The depth D1 of the trench 55 is, for example, 0 nm or more and 5 nm or less. The depth D1 of the trench 55 is the distance from the upper surface of the second step portion 50 to the deepest portion in the trench 55. The depth D1 of the trench 55 is, for example, 25% or less of the thickness of the second step portion 50. The minimum value Tmin of the thickness of the second extending portion 44 in the portion where the trench 55 is formed is, for example, 5 nm or more.

[0060] The trench 55 formed in the first extending portion 42 and the trench 55 formed in the second extending portion 44 have the same configuration except that the directions in the X-axis direction are opposite. Therefore, the description of the trench 55 formed in the second extending portion 44 is omitted. In the case of the trench 55 formed in the first extending portion 42, the depth D1 of the trench 55 is the distance from the upper surface of the first step portion 46 to the deepest portion in the trench 55, and the minimum value Tmin is the minimum value of the thickness of the first extending portion 42. Hereinafter, the minimum value Tmin may be described as the minimum value of the thickness of the extending portion.

[0061] (Details of the shape of the gate electrode, the thickness of the gate wiring layer, and the thickness of the gate connection portion 62) With reference to FIG. 4, details of the shape of the gate electrode and the thickness of the gate wiring layer will be described.

[0062] The gate electrode 30 may be formed on a part of the upper surface 28A of the gate layer 28, or may be formed on the entire upper surface 28A of the gate layer 28. FIG. 4 illustrates, as an example, a case where the gate electrode 30 is formed on a part of the upper surface of the ridge portion 40 of the gate layer 28. In this case, the length of the gate electrode 30 in the X-axis direction is shorter than the length of the upper surface of the ridge portion 40 in the X-axis direction. And, in the X-axis direction, both end portions of the gate electrode 30 are located inside both end portions of the upper surface of the ridge portion 40. In other words, the gate electrode 30 has an area smaller than the upper surface of the ridge portion 40 in plan view.

[0063] The thickness of the gate electrode 30 is, for example, 30 nm or more. The thickness of the gate electrode 30 is, for example, 50 nm or less. In one example, the thickness of the gate electrode 30 is thinner than the thickness of the gate wiring layer 61. In one example, the thickness of the gate electrode 30 is thinner than the thickness of the ridge portion 40.

[0064] The thickness of the gate wiring layer 61 is, for example, 100 nm or more. The thickness of the gate wiring layer 61 is, for example, 500 nm or less. The combined thickness of the thickness of the gate electrode 30 and the gate wiring layer 61 (hereinafter, may be referred to as the above total thickness) is, for example, 130 nm or more. The above total thickness is, for example, 550 nm or less. The thickness of the gate connection portion 62 is substantially equal to that of the gate wiring layer 61.

[0065] (Planar layout of nitride semiconductor device) Next, with reference to FIG. 2, an example of the planar layout of the nitride semiconductor device 10 will be described. FIG. 2 mainly shows the active region of the HEMT located below the source pad 14 or the drain pad 16 shown in FIG. 1. In FIG. 2, the gate electrode 30, the source electrode 34, and the drain electrode 36 are drawn with broken lines. For the passivation layer 32, the source opening 32A and the drain opening 32B are drawn with solid lines, and the other portions are shown transparently. Note that, in FIG. 2, the field plate electrode 53, the first extending portion 42, and the second extending portion 44 are omitted.

[0066] As shown in FIG. 2, the gate layer 28 may be formed so as to surround the drain electrode 36 in plan view. The gate layer 28 may include a main body portion 28D extending in the Y-axis direction and a connection portion 28E connecting two adjacent main body portions 28D. The main body portion 28D of the gate layer 28 is disposed between the source opening 32A and the drain opening 32B of the passivation layer 32.

[0067] The gate electrode 30 is disposed so as to overlap the gate layer 28 in plan view. Similar to the gate layer 28, the gate electrode 30 may be formed so as to surround the drain electrode 36 in plan view. The gate electrode 30 may include a main body portion extending in the Y-axis direction and a connection portion connecting two adjacent main body portions.

[0068] The gate opening 32C, the gate connection portion 62 (not shown), and the gate wiring layer 61 include a portion formed on the main body portion of the gate electrode 30. The gate opening 32C, the gate connection portion 62 (not shown), and the gate wiring layer 61 extend in the Y-axis direction along the upper surface of the gate electrode 30 on the main body portion of the gate electrode 30. In this specification, the Y-axis direction corresponds to a second direction orthogonal to the first direction in plan view. The gate wiring layer 61 is electrically connected to the gate pad 12 shown in FIG. 1 in the portion extending in the Y-axis direction described above. An example of the gate wiring layer 61 is in contact with the gate pad 12.

[0069] Although not shown, the nitride semiconductor device 10 may include a source wiring and a drain wiring. The source wiring and the drain wiring are located above the source electrode 34 and the drain electrode 36 in the Z-axis direction. The source electrode 34 and the field plate electrode 53 are electrically connected to the source wiring via vias, for example. The drain electrode 36 is electrically connected to the drain wiring via vias, for example. The source wiring and the drain wiring are electrically connected to the source pad 14 and the drain pad 16 shown in FIG. 1, respectively.

[0070] The planar layout of the nitride semiconductor device 10 is not limited to the example shown in FIG. 2. Any other planar layout can be applied to the nitride semiconductor device 10. (Method for manufacturing a nitride semiconductor device) Next, with reference to FIGS. 6 to 16, an example of a method for manufacturing the nitride semiconductor device 10 will be described. FIGS. 6 to 16 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 10. For ease of understanding, in FIGS. 6 to 16, the same components as those in FIGS. 3 to 5 are denoted by the same reference numerals.

[0071] The method for manufacturing the nitride semiconductor device 10 includes forming a first nitride semiconductor layer 78, forming a second nitride semiconductor layer 80 having a larger bandgap than the first nitride semiconductor layer 78 on the first nitride semiconductor layer 78, and forming a third nitride semiconductor layer 82 containing acceptor-type impurities on the second nitride semiconductor layer 80.

[0072] As shown in FIG. 6, for example, a buffer layer 20, a first nitride semiconductor layer 78, a second nitride semiconductor layer 80, and a third nitride semiconductor layer 82 are sequentially stacked on a substrate 18 which is a Si substrate. The buffer layer 20, the first nitride semiconductor layer 78, the second nitride semiconductor layer 80, and the third nitride semiconductor layer 82 can be epitaxially grown using a Metal Organic Chemical Vapor Deposition (MOCVD) method.

[0073] Although detailed illustration is omitted, in one example, the buffer layer 20 may be a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the substrate 18 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer can be formed, for example, by stacking three AlGaN layers having Al compositions of 75%, 50%, and 25% in order from the side closer to the AlN layer.

[0074] The first nitride semiconductor layer 78 formed on the buffer layer 20 may be a GaN layer. Also, the second nitride semiconductor layer 80 formed on the first nitride semiconductor layer 78 may be an AlGaN layer. The second nitride semiconductor layer 80 has a larger bandgap than the first nitride semiconductor layer 78. The first nitride semiconductor layer 78 and the second nitride semiconductor layer 80 respectively correspond to the electron traveling layer 22 and the electron supply layer 24 shown in FIG. 3.

[0075] The third nitride semiconductor layer 82 may be a GaN layer containing acceptor-type impurities. In one example, by doping magnesium during the growth of the third nitride semiconductor layer 82, the third nitride semiconductor layer 82 containing acceptor-type impurities can be formed. The amount of magnesium doped into the third nitride semiconductor layer 82 can be adjusted, for example, by controlling the flow rate of the doping gas (e.g., bis(cyclopentadienyl)magnesium (Cp2Mg)) introduced into the growth chamber, the growth temperature, etc. In one example, the third nitride semiconductor layer 82 may contain magnesium as an impurity at a concentration of 1×10 18 cm -3 or more and less than 1×10 20 cm -3

[0076] The method for manufacturing the nitride semiconductor device 10 further includes forming the gate electrode 30 on the third nitride semiconductor layer 82 and forming the gate layer 28 by selectively removing the third nitride semiconductor layer 82.

[0077] As shown in FIG. 6, a first metal layer 83 is formed on the third nitride semiconductor layer 82. The first metal layer 83 is formed, for example, by sputtering. Then, as shown in FIG. 7, the first metal layer 83 is selectively removed. As a result, the gate electrode 30 is formed as the remaining portion of the first metal layer 83. The first metal layer 83 is selectively removed, for example, by performing lithography and etching using a mask.

[0078] ​Next, as shown in FIG. 8, the third nitride semiconductor layer 82 is selectively removed. As a result, as a remaining portion of the third nitride semiconductor layer 82, a first portion 82A corresponding to the ridge portion 40 of the gate layer 28 and a second portion 82B thinner than the first portion 82A are formed. The thickness of the second portion 82B may be less than or equal to half of the thickness of the first portion 82A. Next, as shown in FIG. 9, the third nitride semiconductor layer 82 is selectively removed so that a part of the second portion 82B corresponding to the first extending portion 42 and the second extending portion 44 remains. As a result, the gate layer 28 including the ridge portion 40, the first extending portion 42, and the second extending portion 44 is formed. The third nitride semiconductor layer 82 is selectively removed, for example, by performing lithography and etching using a mask.

[0079] The method for manufacturing the nitride semiconductor device 10 further includes forming a second nitride semiconductor layer 80 (electron supply layer 24) and a first passivation layer 32D covering the gate layer 28, forming a field plate electrode 53 on the first passivation layer 32D, and forming a second passivation layer 32E on the first passivation layer 32D and the field plate electrode 53.

[0080] As shown in FIG. 10, a first insulator layer 84 covering the second nitride semiconductor layer 80, the gate layer 28, and the gate electrode 30 is formed. The first insulator layer 84 is a layer for forming the first passivation layer 32D. The first insulator layer 84 is, for example, a SiN layer. The first insulator layer 84 is formed, for example, by a low-pressure chemical vapor deposition (LPCVD) method.

[0081] Next, as shown in FIG. 11, a second metal layer 85 is formed on the first insulator layer 84. The second metal layer 85 is a layer for forming the field plate electrode 53 and is, for example, a TiN layer. The second metal layer 85 is formed, for example, by a Plasma-Enhanced Chemical Vapor Deposition (PECVD) method. Next, as shown in FIG. 12, the second metal layer 85 is selectively removed. As a result, the remaining portion of the second metal layer 85 is formed as the field plate electrode 53. The second metal layer 85 is selectively removed, for example, by performing lithography and etching using a mask.

[0082] Next, as shown in FIG. 13, a second insulator layer 86 covering the first insulator layer 84 and the field plate electrode 53 is formed. The second insulator layer 86 is a layer for forming the second passivation layer 32E. The second insulator layer 86 is, for example, a SiN layer. The second insulator layer 86 is formed, for example, by the PECVD method.

[0083] Next, as shown in FIG. 14, the first insulator layer 84 and the second insulator layer 86 are selectively removed so as to expose a part of the upper surface of the second nitride semiconductor layer 80 and a part of the upper surface of the gate electrode 30. As a result, the source opening 32A and the drain opening 32B of the passivation layer 32 are formed in a manner that exposes the upper surface of the second nitride semiconductor layer 80, and the gate opening 32C is formed in a manner that exposes the upper surface of the gate electrode 30. That is, a passivation layer 32 including the source opening 32A, the drain opening 32B, and the gate opening 32C is formed. Also, a passivation layer 32 in which the field plate electrode 53 is embedded is formed.

[0084] The method for manufacturing the nitride semiconductor device 10 further includes forming a source electrode 34 and a drain electrode 36 so as to contact the electron supply layer 24, forming a gate connection portion 62 so as to contact the gate electrode 30, and forming a gate wiring layer 61 so as to contact the gate connection portion 62.

[0085] As shown in FIG. 15, a third metal layer 87 is formed to cover the passivation layer 32, the second nitride semiconductor layer 80 exposed in the source opening 32A and the drain opening 32B, and the gate electrode 30 exposed in the gate opening 32C. The third metal layer 87 is a layer for forming the source electrode 34, the drain electrode 36, the gate connection portion 62, and the gate wiring layer 61, and is, for example, a Ti layer / AlCu layer / Ti layer / TiN layer. The third metal layer 87 is formed, for example, by the PECVD method.

[0086] The third metal layer 87 is formed over the entire upper surface of the passivation layer 32. The third metal layer 87 fills the source opening 32A of the passivation layer 32 and contacts the upper surface of the second nitride semiconductor layer 80 in the source opening 32A. The third metal layer 87 fills the drain opening 32B of the passivation layer 32 and contacts the upper surface of the second nitride semiconductor layer 80 within the drain opening 32B. The third metal layer 87 fills the gate opening 32C of the passivation layer 32 and contacts the upper surface of the gate electrode 30 within the gate opening 32C.

[0087] Next, as shown in FIG. 16, the third metal layer 87 is selectively removed. Thereby, as the remaining portions of the third metal layer 87, the source electrode 34, the drain electrode 36, the gate connection portion 62, and the gate wiring layer 61 are formed. The gate connection portion 62 and the gate wiring layer 61 are formed as a gate wiring 60 integrated with the same material. The third metal layer 87 is selectively removed by performing lithography and etching using a mask. Through the above steps, the nitride semiconductor device 10 shown in FIG. 3 is manufactured.

[0088] (Operation) Next, the operation of the nitride semiconductor device 10 of the embodiment will be described. The gate layer 28 includes extending portions 42 and 44 that are thinner than the ridge portion 40. When a voltage is applied to the gate electrode 30, a part of the equipotential lines in the ridge portion 40 passes through the extending portions 42 and 44. Accordingly, it is possible to suppress local electric field concentration in the vicinity of the end of the ridge portion 40 (for example, in the electron supply layer 24) that may occur when the extending portions 42 and 44 do not exist. As a result, the generation of gate leakage current when a voltage is applied is suppressed, and thus the gate breakdown voltage of the nitride semiconductor device 10 can be improved.

[0089] When the extending portions 42 and 44 are formed thick, the on-resistance of the gate increases. Therefore, it is preferable that the extending portions 42 and 44 be made thin, for example, 20 nm or less. However, when the extending portions 42 and 44 are designed to be thin, it becomes difficult to leave the extending portions 42 and 44 over the entire desired range in the etching for forming the extending portions 42 and 44 during manufacturing. Therefore, in the above etching, a part of the extending portions 42 and 44 may be partially lost, and a portion where the electron supply layer 24 is exposed may occur in the range where the extending portions 42 and 44 should be formed.

[0090] Specifically, in the etching of the third nitride semiconductor layer 82 for forming the first portion 82A and the second portion 82B (see FIG. 8), the connection portion of the second portion 82B with the first portion 82A may be etched deeply in part. As a result, a trench 55 as shown in FIG. 5 is formed in the connection portion of the extending portion with the ridge portion 40.

[0091] Also, at the final stage of the etching of the first metal layer 83 (see FIG. 7), which is a process for forming the gate electrode 30 and is performed before the etching of the third nitride semiconductor layer 82, the upper surface of the third nitride semiconductor layer 82 is exposed. At this time, the upper surface of the third nitride semiconductor layer 82 may be damaged by etching (for example, physical etching such as plasma etching). In particular, a recessed portion 82C (not shown) that is partially recessed is formed around the first metal layer 83 on the upper surface of the third nitride semiconductor layer 82 exposed by the etching. In FIG. 5, the recessed portion 82C is indicated by a two-dot chain line.

[0092] The shape of the upper surface including the recess 82C of the third nitride semiconductor layer 82 is carried over to the upper surface of the second portion 82B in the etching of the third nitride semiconductor layer 82 for forming the first portion 82A and the second portion 82B. At this time, the position of the trench 55 formed by the etching and the position where the shape of the recess 82C on the upper surface of the second portion 82B is carried over overlap, so that a deep trench 55 is formed. When the extending portions 42 and 44 are thin, the depth D1 of the trench 55 exceeds the thickness of the extending portions 42 and 44, so that the extending portions 42 and 44 disappear in the portion where the trench 55 is formed and the electron supply layer 24 is exposed. Hereinafter, the occurrence of a portion where the extending portions 42 and 44 disappear and the electron supply layer 24 is exposed may be described as partial disappearance of the extending portions.

[0093] As a method for solving the partial disappearance of the extending portions, it is conceivable to thin the first metal layer 83, that is, the gate electrode 30. The recess 82C becomes deeper depending on the etching amount for removing the first metal layer 83. That is, the thicker the first metal layer 83, the deeper the recess 82C is formed. Therefore, when the gate electrode 30 is thinned, the etching amount for removing the first metal layer 83 is reduced, so that the formation of a deep recess 82C can be suppressed. As a result, the formation of a deep trench 55 formed by carrying over the shape of the upper surface including the recess 82C can be suppressed. However, when the gate electrode 30 is thinned, there arises a problem that the on-resistance of the gate becomes high.

[0094] Here, in the nitride semiconductor device 10 of the embodiment, a gate wiring layer 61 is provided on the passivation layer 32. Then, the gate electrode 30 and the gate wiring layer 61 are electrically connected via a gate connection portion 62 provided in a gate opening 32C formed in the passivation layer 32. According to this configuration, the on-resistance can be reduced by the gate connection portion 62 disposed on the gate electrode 30 and the gate wiring layer 61 connected to the gate connection portion 62. Therefore, due to the effect of reducing the on-resistance by the gate connection portion 62 and the gate wiring layer 61, part or all of the increase in the on-resistance caused by thinning the gate electrode 30 can be offset. Thus, it becomes possible to form the gate electrode 30 thinner while suppressing the increase in the on-resistance and suppressing the partial disappearance of the extending portions in the thin extending portions 42 and 44.

[0095] (Effect) According to the nitride semiconductor device 10 of the embodiment, the following effects can be obtained. (1) The nitride semiconductor device 10 includes a substrate 18, an electron traveling layer 22, an electron supply layer 24, a gate layer 28, a gate electrode 30, a passivation layer 32 that covers the electron supply layer 24 and the gate layer 28, a source electrode 34, a drain electrode 36, and a gate electrode 30 formed on the gate layer 28. The gate layer 28 includes a ridge portion 40 and extending portions 42 and 44 that are thinner than the ridge portion 40. The nitride semiconductor device 10 further includes a gate wiring layer 61 provided on the passivation layer 32. The gate wiring layer 61 is electrically connected to the gate electrode 30 via a gate connection portion 62 provided in a gate opening 32C formed in the passivation layer 32.

[0096] According to this configuration, the thin extending portions 42 and 44 can be formed without causing partial disappearance of the extending portions or while suppressing the occurrence of partial disappearance of the extending portions. Therefore, it is possible to achieve both a high gate breakdown voltage based on providing the thin extending portions 42 and 44 and a low on-resistance. Thus, a nitride semiconductor device 10 having characteristics of high-speed switching operation and high gate breakdown voltage can be realized.

[0097] (2) The ridge portion 40 and the gate electrode 30 are formed to extend in the Y-axis direction orthogonal to the X-axis direction in a plan view. The gate opening 32C, the gate connection portion 62, and the gate wiring layer 61 extend in the Y-axis direction along the upper surface 30A of the gate electrode 30 in a plan view. According to this configuration, the effect of reducing the on-resistance by the gate connection portion 62 and the gate wiring layer 61 can be obtained more remarkably. Therefore, the gate electrode 30 can be formed thinner without significantly increasing the on-resistance.

[0098] (3) The gate wiring layer 61 and the gate connection portion 62 are formed of the same material. According to this configuration, since the gate wiring layer 61 and the gate connection portion 62 can be formed by a common process, the manufacturing cost can be reduced.

[0099] (4) The gate wiring layer 61 and the gate connection portion 62 are made of the same material as the source electrode 34 and the drain electrode 36. According to this configuration, since the gate wiring layer 61, the gate connection portion 62, the source electrode 34, and the drain electrode 36 can be formed by a common process, the manufacturing cost can be further reduced.

[0100] (5) The thickness of the gate electrode 30 is thinner than the thickness of the gate wiring layer 61. According to this configuration, the effect of being able to form the thin extending portions 42, 44 can be obtained more remarkably without causing partial disappearance of the extending portions or suppressing the occurrence of partial disappearance of the extending portions. Therefore, the characteristics of high gate breakdown voltage based on providing the thin extending portions 42, 44 can be obtained more reliably.

[0101] (6) The thickness of the gate electrode 30 is thinner than the thickness of the ridge portion 40. According to this configuration, the effect of being able to form the thin extending portions 42, 44 can be obtained more remarkably without causing partial disappearance of the extending portions or suppressing the occurrence of partial disappearance of the extending portions. Therefore, the characteristics of high gate breakdown voltage based on providing the thin extending portions 42, 44 can be obtained more reliably.

[0102] (7) The length of the gate electrode 30 in the X-axis direction is shorter than the length of the upper surface of the ridge portion 40 of the gate layer 28 in the X-axis direction. In the X-axis direction, both ends of the gate electrode 30 are located inside both ends of the upper surface of the ridge portion 40.

[0103] The recess 82C is formed around the first metal layer 83 on the upper surface of the third nitride semiconductor layer 82, that is, around the gate electrode 30. Therefore, in the case of the above configuration, part or all of the recess 82C is formed at a position exposed from the gate electrode 30 on the upper surface of the first portion 82A. As a result, in the X-axis direction, the position of the trench 55 formed by etching the third nitride semiconductor layer 82 for forming the first portion 82A and the second portion 82B can be shifted in the X-axis direction from the position where the recess 82C is formed. Thus, it is possible to suppress the formation of a deep trench 55 due to the overlap between the position of the trench 55 and the position where the shape of the recess 82C on the upper surface of the second portion 82B is inherited on the upper surface of the second portion 82B. As a result, the effect of suppressing the partial disappearance of the extending portion is obtained more remarkably.

[0104] (8) The extending portions 42, 44 include tapered portions 48, 52 that are formed at the connection portions with the ridge portion 40 and gradually become thinner toward the tip sides of the extending portions 42, 44. According to this configuration, the electric field concentration in the vicinity of the corner where the extending portions 42, 44 are connected to the ridge portion 40 can be alleviated. As a result, the effect of improving the gate breakdown voltage based on providing the extending portions 42, 44 is obtained more remarkably.

[0105] (9) It includes a field plate electrode 53 disposed between the gate electrode 30 and the drain electrode 36 and formed of a material different from that of the source electrode 34. According to this configuration, the degree of freedom in selecting the material for forming the field plate electrode 53 is improved. For example, the field plate electrode 53 can be formed of a material that allows for denser patterning than the material for forming the source electrode 34. In this case, by making the field plate electrode 53 into a finer shape, it is possible to improve the effect of alleviating the electric field concentration in the vicinity of the end of the gate layer 28. Therefore, a field plate electrode 53 capable of further increasing the drain-source breakdown voltage can be formed.

[0106] (10) The passivation layer 32 includes a first passivation layer 32D and a second passivation layer 32E formed on the first passivation layer 32D. The field plate electrode 53 is disposed between the first passivation layer 32D and the second passivation layer 32E. According to this configuration, in the Z-axis direction, the field plate electrode 53 can be disposed at a position close to the gate layer 28.

[0107] (Modified Example) The above embodiment can be implemented with the following modifications. · The gate layer 28 only needs to have at least one of the first extending portion 42 and the second extending portion 44. That is, the gate layer 28 may have a configuration including only the first extending portion 42 among the first extending portion 42 and the second extending portion 44, or may have a configuration including only the second extending portion 44.

[0108] · As shown in FIG. 17, instead of the configuration in which the field plate electrode 53 is embedded in the passivation layer 32, the field plate electrode 53 may be provided on the passivation layer 32. In this case, the passivation layer 32 may have a single-layer structure. An example of the field plate electrode 53 in this case is formed of the same material as the source electrode 34. According to this configuration, since the field plate electrode 53 and the source electrode 34 can be formed simultaneously by a common process, the manufacturing cost can be reduced.

[0109] One or more of the various examples described in this specification can be combined within a technically non-contradictory range. In this specification, the description "at least one of A and B" should be understood to mean "only A, or only B, or both A and B".

[0110] As used in this specification, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Therefore, the expression "the first layer is formed on the second layer" is intended that in some embodiments the first layer may be in contact with the second layer and disposed directly on the second layer, while in other embodiments the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which other layers are formed between the first layer and the second layer.

[0111] The terms indicating directions such as "vertical", "horizontal", "above", "below", "up", "down", "front", "rear", "longitudinal", "lateral", "left", "right", "forward", "backward" used in this specification depend on the specific orientation of the device being described and illustrated. In the present disclosure, various alternative orientations can be assumed, and therefore, these terms indicating directions should not be construed narrowly.

[0112] For example, the Z-axis direction used in this specification does not necessarily have to be the vertical direction and does not have to exactly coincide with the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0113] (Appendix) The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than limiting, the components described in the appendix are given the reference signs of the corresponding components in the embodiments. The reference signs are shown as examples for assisting understanding, and the components described in each appendix should not be limited to the components indicated by the reference signs.

[0114] [Appendix 1] a substrate (18), an electron transport layer (22) formed above the substrate (18), an electron supply layer (24) formed on the electron transport layer (22) and having a larger bandgap than the electron transport layer (22), a gate layer (28) formed on the electron supply layer (24) and having acceptor impurities, a gate electrode (30) formed on the gate layer (28), a passivation layer (32) covering the electron supply layer (24) and the gate layer (28) and including a source opening (32A), a gate opening (32C), and a drain opening (32B) arranged to be aligned in a first direction, a gate wiring layer (61) provided on the passivation layer (32), a source electrode (34) in contact with the electron supply layer (24) through the source opening (32A), a drain electrode (36) in contact with the electron supply layer (24) through the drain opening (32B), the gate layer (28) a ridge portion (40) in contact with the electron supply layer (24) and including the upper surface (28A) of the gate layer (28), An extension portion (42, 44) that is in contact with the electron supply layer (24) and extends in the first direction from the ridge portion (40) and is thinner than the ridge portion (40). The gate layer (28) and the gate opening (32C) are located between the source opening (32A) and the drain opening (32B) in the first direction. The gate wiring layer (61) is electrically connected to the gate electrode (30) via a gate connection portion (62) provided in the gate opening (32C). A nitride semiconductor device (10).

[0115] [Appendix 2] The ridge portion (40) and the gate electrode (30) are formed to extend in a second direction orthogonal to the first direction in a plan view. The gate opening (32C), the gate connection portion (62), and the gate wiring layer (61) extend in the second direction along the upper surface (30A) of the gate electrode (30) in a plan view. The nitride semiconductor device (10) according to Appendix 1.

[0116] [Appendix 3] The gate wiring layer (61) and the gate connection portion (62) are formed of the same material. The nitride semiconductor device (10) according to Appendix 1 or Appendix 2.

[0117] [Appendix 4] The gate wiring layer (61) and the gate connection portion (62) are formed of the same material as the source electrode (34) and the drain electrode (36). The nitride semiconductor device (10) according to any one of Appendices 1 to 3.

[0118] [Appendix 5] The thickness of the gate electrode (30) is thinner than the thickness of the gate wiring layer (61). The nitride semiconductor device (10) according to any one of Appendices 1 to 4.

[0119] [Appendix 6] The thickness obtained by combining the thickness of the gate electrode (61) and the thickness of the gate wiring layer (61) is 100 nm or more, and the nitride semiconductor device (10) according to any one of Appendices 1 to 5.

[0120] [Appendix 7] The thickness of the gate wiring layer (61) is 100 nm or more and 300 nm or less, The thickness (30) of the gate electrode is 30 nm or more and 70 nm or less, and the nitride semiconductor device (10) according to Appendix 6.

[0121] [Appendix 8] The thickness of the gate electrode (30) is thinner than the thickness of the ridge portion (40), and the nitride semiconductor device (10) according to any one of Appendices 1 to 7.

[0122] [Appendix 9] The thickness of the extending portions (42, 44) is 5 nm or more and 20 nm or less, The thickness of the gate electrode (30) is 30 nm or more and 70 nm or less, and the nitride semiconductor device (10) according to any one of Appendices 1 to 8.

[0123] [Appendix 10] The length of the gate electrode (30) in the first direction is shorter than the length of the upper surface of the ridge portion (40) of the gate layer (28) in the first direction, In the first direction, both ends of the gate electrode (30) are located inside both ends of the upper surface of the ridge portion (40), and the nitride semiconductor device (10) according to any one of Appendices 1 to 9.

[0124] [Appendix 11] The extending portions (42, 44) are formed at the connection portions with the ridge portion (40) and include tapered portions (48, 52) whose thickness gradually decreases toward the tip side of the extending portions (42, 44), and the nitride semiconductor device (10) according to any one of Appendices 1 to 10.

[0125] [Appendix 12] The nitride semiconductor device (10) according to any one of Appendices 1 to 11, comprising a field plate electrode (53) disposed between the gate electrode (30) and the drain electrode (36) and formed of a material different from that of the source electrode (34).

[0126] [Appendix 13] The passivation layer (32) includes a first passivation layer (32D) and a second passivation layer (32E) formed on the first passivation layer (32D). The nitride semiconductor device (10) according to Appendix 12, wherein the field plate electrode (53) is disposed between the first passivation layer (32D) and the second passivation layer (32E).

[0127] [Appendix 14] The nitride semiconductor device (10) according to any one of Appendices 1 to 11, comprising a field plate electrode (53) disposed between the gate electrode (30) and the drain electrode (36) and formed of the same material as the source electrode (34).

[0128] [Appendix 15] The nitride semiconductor device (10) according to any one of Appendices 1 to 14, wherein the extending portions (42, 44) include trenches (55) formed at connection portions with the ridge portion (40).

Explanation of Reference Numerals

[0129] D1, D2... Depth Tmin... Minimum value of the thickness of the extending portion 10... Nitride semiconductor device 10A... Upper surface 12... Gate pad 14... Source pad 16... Drain pad 18... Substrate 20... Buffer layer 22... Electron traveling layer 24... Electron supply layer 26... Two-dimensional electron gas 28... Gate layer 28A…Above 28B…Below 28C…Side 28D…Body part 28E…Connection part 30…Gate electrode 30A…Above 30C…Side 32…Passivation layer 32A…Source opening 32B…Drain opening 32C…Gate opening 32D…First passivation layer 32E…Second passivation layer 34…Source electrode 36…Drain electrode 40…Ridge part 42…First extending part 42A…Above 44…Second extending part 44A…Above 46…First step part 48…First taper part 50…Second step part 52…Second taper part 53…Field plate electrode 53A…First end 53B…Second end 55…Trench 60…Gate wiring 61…Gate wiring layer 62…Gate connection part 78…First nitride semiconductor layer 80…Second nitride semiconductor layer 82…Third nitride semiconductor layer 82A…First part 82B…Second part 82C…Recessed part 83…First metal layer 84…First insulator layer 85…Second metal layer 86…Second insulator layer 87…Third metal layer

Claims

1. A substrate, An electron transport layer formed above the substrate, An electron supply layer formed on the electron transport layer and having a larger bandgap than the electron transport layer, A gate layer formed on the electron supply layer and having acceptor impurities, A gate electrode formed on the gate layer, A passivation layer covering the electron supply layer and the gate layer and including a source opening, a gate opening, and a drain opening arranged to be aligned in a first direction, A gate wiring layer provided on the passivation layer, A source electrode in contact with the electron supply layer through the source opening, A drain electrode in contact with the electron supply layer through the drain opening, comprising: The gate layer, A ridge portion in contact with the electron supply layer and including the upper surface of the gate layer, An extending portion in contact with the electron supply layer and extending in the first direction from the ridge portion and thinner than the ridge portion, The gate layer and the gate opening are located between the source opening and the drain opening in the first direction, The gate wiring layer is electrically connected to the gate electrode through a gate connection portion provided in the gate opening. A nitride semiconductor device.

2. The ridge portion and the gate electrode are formed to extend in a second direction orthogonal to the first direction in a plan view, The gate opening, the gate connection portion, and the gate wiring layer extend in the second direction along the upper surface of the gate electrode in a plan view. The nitride semiconductor device according to Claim 1.

3. The gate wiring layer and the gate connection portion are formed of the same material. The nitride semiconductor device according to Claim 1.

4. The gate wiring layer and the gate connection portion are formed of the same material as the source electrode and the drain electrode. The nitride semiconductor device according to Claim 3.

5. The thickness of the gate electrode is thinner than the thickness of the gate wiring layer. The nitride semiconductor device according to any one of Claims 1 to 4.

6. The combined thickness of the gate electrode and the gate wiring layer is 100 nm or more. The nitride semiconductor device according to any one of Claims 1 to 4.

7. The thickness of the gate wiring layer is 100 nm or more and 300 nm or less, The thickness of the gate electrode is 30 nm or more and 70 nm or less. The nitride semiconductor device according to Claim 6.

8. The nitride semiconductor device according to any one of claims 1 to 4, wherein the thickness of the gate electrode is thinner than the thickness of the ridge portion.

9. The thickness of the extending portion is 5 nm or more and 20 nm or less, The nitride semiconductor device according to any one of claims 1 to 4, wherein the thickness of the gate electrode is 30 nm or more and 70 nm or less.

10. The first-direction length of the gate electrode is shorter than the first-direction length of the upper surface of the ridge portion of the gate layer, In the first direction, both ends of the gate electrode are located inside both ends of the upper surface of the ridge portion. The nitride semiconductor device according to any one of claims 1 to 4.

11. The nitride semiconductor device according to any one of claims 1 to 4, wherein the extending portion includes a tapered portion formed at a connection portion with the ridge portion and gradually decreasing in thickness toward the tip side of the extending portion.

12. The nitride semiconductor device according to any one of claims 1 to 4, further comprising a field plate electrode disposed between the gate electrode and the drain electrode and formed of a material different from that of the source electrode.

13. The passivation layer includes a first passivation layer and a second passivation layer formed on the first passivation layer, The nitride semiconductor device according to claim 12, wherein the field plate electrode is disposed between the first passivation layer and the second passivation layer.

14. The nitride semiconductor device according to any one of claims 1 to 4, further comprising a field plate electrode disposed between the gate electrode and the drain electrode and formed of the same material as the source electrode.

15. The nitride semiconductor device according to any one of claims 1 to 4, wherein the extending portion includes a trench formed at a connection portion with the ridge portion.

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