Nonvolatile memory protection device
The non-volatile memory protection device uses logical product circuits and protection release keys to secure data against tampering by disabling the debug port and on-chip functions, addressing the risk of unauthorized access in existing technologies.
JP2025113038APending Publication Date: 2025-08-01ROHM CO LTD
Patent Information
- Application Number
- JP2024007659
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-01-22
- Publication Date
- 2025-08-01
AI Technical Summary
Technical Problem
The risk of malicious users accessing the debug port or on-chip debug function in non-volatile memory devices, leading to potential tampering of programs and data, is not adequately addressed by existing technologies.
Method used
A non-volatile memory protection device that includes a protection area with parameters and a logical product circuit to control write access, using a protection release key and logical product circuits to ensure secure access and prevent unauthorized erasure or rewriting of protected data.
Benefits of technology
Prevents tampering of protected information by disabling the debug port and on-chip debug function, ensuring secure data integrity and protection against unauthorized access.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure 2025113038000001_ABST
Abstract
To provide a nonvolatile memory protection device capable of preventing falsification of information to be protected by invalidating a debug port and an on-chip debug function.SOLUTION: A nonvolatile memory protection device 10 includes: a first AND circuit 56 for operating an AND of code option data 126 stored in a protected area 16 and a first write access signal from a CPU 60 to output a first write access signal; a second AND circuit 58 for operating an AND of the code option data 126 and a second write access signal to the protected area 16 received from the CPU 60 to output a second write access signal; and a lock key control circuit 50 for collating a protection release key included in the first write access signal output from the first AND circuit 56 with a release key of the protected area 16 to permit write access to the protected area 16 by the second write access signal.SELECTED DRAWING: Figure 1
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Citation Information
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