Semiconductor device

Abstract

To provide a method for manufacturing a highly reliable semiconductor device having a stable electric property and a thin film transistor arranged by use of an oxide semiconductor.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: forming an oxide semiconductor film on a gate electrode with a gate insulative film interposed therebetween over an insulative plane; forming a first conductive film including titanium, molybdenum or tungsten on the oxide semiconductor film; forming a second conductive film including a metal lower than hydrogen in electronegativity on the first conductive film; forming a source electrode and a drain electrode by etching the first and second conductive films; and forming a dielectric film on the oxide semiconductor film, the source electrode and the drain electrode, which is in contact with the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

Background Art

[0002] A thin film transistor using a semiconductor film formed on an insulating surface is an essential semiconductor element for semiconductor devices. Since the manufacturing of thin film transistors is restricted by the heat resistance temperature of the substrate, thin film transistors having an active layer made of amorphous silicon, polycrystalline silicon obtained by crystallization using laser light or a catalyst element, etc., which can be formed at a relatively low temperature, have become the mainstream of transistors used in semiconductor display devices. In recent years, as a new semiconductor material having both high mobility obtained by polycrystalline silicon and uniform element characteristics obtained by amorphous silicon, attention has been focused on metal oxides called oxide semiconductors, which exhibit semiconductor characteristics. Metal oxides are used in various applications. For example, indium oxide, which is a well-known metal oxide, is used as a transparent electrode material in liquid crystal display devices. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using such metal oxides exhibiting semiconductor characteristics in the channel formation region are already known (Patent Document 1 and Patent Document 2).

[0003]

[0003]

[0004]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] Transistors used in semiconductor devices are desired to have a small variation in threshold voltage due to degradation over time, and also to have good characteristics such as on-current. By using a transistor with a small variation in threshold voltage due to degradation over time, the reliability of the semiconductor device can be improved. Also, by using a transistor with good characteristics such as on-current, the semiconductor device can be driven at a higher frequency.

[0006] One object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device. Alternatively, one object of the present invention is to provide a method for manufacturing a semiconductor device capable of high-speed driving. Alternatively, one object of the present invention is to provide a highly reliable semiconductor device. Alternatively, one object of the present invention is to provide a semiconductor device capable of high-speed driving.

MEANS FOR SOLVING THE PROBLEMS

[0007] The present inventors focused on the fact that impurities such as hydrogen and water present in the oxide semiconductor film are factors causing degradation over time such as a shift in the threshold voltage in the transistor. Then, by using a conductive film made of a metal with a low electronegativity, specifically a metal with a lower electronegativity than hydrogen, as the conductive film for the source electrode and the drain electrode, and forming it above or below the oxide semiconductor film, impurities such as hydrogen and water present in the oxide semiconductor film are drawn out to the above conductive film, and the purity of the oxide semiconductor film is increased. As a result, the transistor caused by impurities such as hydrogen and water I thought that deterioration over time might be suppressed. By processing the above conductive film into a desired shape by etching or the like, source electrodes and drain electrodes can be formed.

[0008] Specifically, in one aspect of the present invention, in the fabrication of a semiconductor device having a transistor using an oxide semiconductor film as an active layer, a first conductive film made of a metal material such as titanium, tungsten, or molybdenum, which has a low contact resistance with the oxide semiconductor film, is formed so as to be in contact with the oxide semiconductor film. Further, a second conductive film made of a metal, metal compound, or alloy having a low electronegativity is formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween. Then, by processing the first conductive film and the second conductive film into a desired shape by etching or the like, source electrodes and drain electrodes are formed. Alternatively, the first conductive film is formed so as to be in contact with the oxide semiconductor film, and after the second conductive film is formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween, the second conductive film is removed by etching. In this case, after removing the second conductive film, a third conductive film made of a metal, metal compound, or alloy having a low electronegativity is newly formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween. Then, by processing the first conductive film and the third

[0009] conductive film into a desired shape by etching or the like, source electrodes and drain electrodes are formed.

[0010] Alternatively, the first conductive film is formed so as to be in contact with the oxide semiconductor film, and after the second conductive film is formed so as to overlap the oxide semiconductor film with the first conductive film interposed therebetween, the second The first conductive film is removed by etching. Then, after removing the second conductive film, A third conductive film made of a metal, metal compound or alloy having a low resistance is sandwiched between the first conductive film. The third conductive film is formed so as to overlap with the oxide semiconductor film. The fourth type uses metallic materials such as titanium, tungsten, or molybdenum, which have low contact resistance. The conductive film is formed to overlap with the oxide semiconductor film. The fifth type uses metallic materials such as titanium, tungsten, or molybdenum, which have low contact resistance. A conductive film may be formed between the first conductive film and the third conductive film. the first conductive film, the third conductive film and the fourth conductive film, or the first conductive film, the third conductive film and the fourth conductive film The first conductive film and the fifth conductive film are processed into a desired shape by etching or the like, thereby forming a saw. A source electrode and a drain electrode are formed.

[0011] In one embodiment of the present invention, the first conductive film constituting the source electrode and the drain electrode is formed of an oxide. A metal material with low contact resistance with the semiconductor film is used, and the metal material is in contact with the oxide semiconductor film. Therefore, the contact resistance between the source electrode or the drain electrode and the oxide semiconductor film is low. Therefore, the on-current and field effect mobility of the TFT can be increased. The second conductive film and the third conductive film are made of a metal, a metal compound, or an alloy having low electronegativity. Therefore, the oxide semiconductor film, the gate insulating film, or the oxide semiconductor film and other insulating films Impurities such as moisture or hydrogen present at the interface and its vicinity may cause damage to the second conductive film, the third conductive film, and the Therefore, impurities such as moisture and hydrogen are absorbed or adsorbed in the conductive film. It is possible to obtain an oxide semiconductor that is almost i-type or an intrinsic semiconductor. This prevents the accelerated degradation of transistor characteristics, such as threshold voltage shift, and reduces the off-current can be reduced.

[0012] Examples of metals with low electronegativity include aluminum and magnesium. A mixture, metal compound or alloy containing one or more of the following is formed on the second conductive film, the third conductive film, In addition, titanium, tantalum, tungsten, molybdenum, etc. can be used as a conductive film. An element selected from the group consisting of silicon, chromium, neodymium, and scandium, or one or more of the above elements. Heat-resistant conductive materials such as alloys containing several elements or nitrides containing the above elements as components may be used in combination with aluminum as the second conductive film and the third conductive film.

[0013] Among the above metals with low contact resistance with the oxide semiconductor film, titanium has a lower electronegativity than hydrogen. Since the temperature is low, impurities such as moisture or hydrogen are easily extracted from the oxide semiconductor film. Therefore, by using titanium for the first conductive film, the fourth conductive film, and the fifth conductive film, the oxidation It is possible to reduce impurities in the compound semiconductor film and also to reduce the contact resistance with the oxide semiconductor film. This makes it possible to form a thin source electrode or drain electrode.

[0014] In addition to the above configuration, the second conductive film, the third conductive film, or the fourth conductive film may be exposed. In this state, a heat treatment is performed under a reduced pressure atmosphere and an inert gas atmosphere to form the second conductive film and the third conductive film. In order to remove moisture and oxygen adsorbed on the surface or inside of the first conductive film or the fourth conductive film, The temperature range of the heat treatment is 200° C. to 450° C. By performing this, it is possible to form a thin film in the oxide semiconductor film, in the gate insulating film, or between the oxide semiconductor film and other insulating films. Impurities such as moisture or hydrogen present at the interface and in its vicinity can be easily occluded or adsorbed by the second conductive film, the third conductive film, or the fourth conductive film.

[0015] After forming the source electrode and the drain electrode, a single insulating film or a plurality of stacked insulating films may be formed so as to cover the source electrode, the drain electrode, and the oxide semiconductor film. It is desirable to use a material with high barrier properties for the above-mentioned insulating film. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of stacked insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the above-mentioned insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film. And, with an insulating film with a lower nitrogen ratio sandwiched in between, a barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the conductive film. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity. Also, between the gate electrode and the oxide semiconductor film, there is a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked. A gate insulating film may be formed. The insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the barrier insulating film and the oxide semiconductor film. The barrier insulating film is formed on the side closer to the oxide semiconductor film. And, with an insulating film with a lower nitrogen ratio sandwiched in between, a barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the conductive film. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the conductive film. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity. Also, between the gate electrode and the oxide semiconductor film, there is a structure in which an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked. is formed on the side closer to the oxide semiconductor film. And, with an insulating film with a lower nitrogen ratio sandwiched in between, a barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the conductive film. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity.

[0016] Also, between the gate electrode and the oxide semiconductor film, an insulating film made of a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio are stacked. A gate insulating film having such a structure may be formed. The insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the barrier insulating film and the oxide semiconductor film. The barrier insulating film is formed on the side closer to the oxide semiconductor film. And, with an insulating film with a lower nitrogen ratio sandwiched in between, a barrier insulating film is formed so as to overlap the source electrode, the drain electrode, and the oxide semiconductor film. By using a barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the conductive film. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity. By using this, it is possible to prevent impurities such as moisture, impurities in the atmosphere such as hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate from entering into the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof.

[0017] Furthermore, in order to reduce moisture or impurities such as hydrogen in the oxide semiconductor film, after forming the oxide semiconductor film, a heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) with the oxide semiconductor film exposed. The temperature range of the above heat treatment is desirably 500°C or higher and 750°C or lower (or a temperature equal to or lower than the strain point of the glass substrate). Note that this heat treatment should not exceed the heat-resistant temperature of the substrate used.

[0018] The oxide semiconductor can be a quaternary metal oxide In-Sn-Ga-Zn-O-based oxide semiconductor, a ternary metal oxide In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn-O-based oxide semiconductor, a binary metal oxide In-Zn-O-based oxide semiconductor, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, In-O-based oxide semiconductor, Sn-O-based oxide semiconductor, Zn-O-based oxide semiconductor, etc. In this specification, for example, the In-Sn-Ga-Zn-O-based oxide semiconductor refers to indium (In), tin (Sn), gallium (Ga), zinc (Zn) ​It means a metal oxide having [the following composition], and its composition ratio is not particularly limited. Further, the above oxide The semiconductor may contain silicon.

[0019] Alternatively, the oxide semiconductor can be represented by the chemical formula InMO3(ZnO) m (m > 0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co

[0020] Note that in the oxide semiconductor film, impurities such as moisture are desorbed by heat treatment, resulting in an increase in carrier concentration and a decrease in resistance. Thereafter, when an insulating film such as silicon oxide or silicon oxynitride is formed in contact with the low-resistance oxide semiconductor film, oxygen is supplied to at least the region of the low-resistance oxide semiconductor film in contact with the insulating film, so that the carrier concentration decreases (preferably less than 1×10 / cm 18 3 and more preferably less than 1×10 14 / cm 3 ), and the resistance increases. Thus, during the process of the semiconductor device, by forming an insulating film such as silicon oxide or silicon oxynitride etc., the carrier concentration and resistance of the oxide semiconductor film can be controlled, so that it is possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0021] Also, the transistor may be of a bottom gate type, a top gate type, or a bottom contact type. A bottom gate type transistor includes a gate electrode on an insulating surface, a gate insulating film on the gate electrode, an oxide semiconductor film overlapping the gate electrode on the gate insulating film, a source electrode and a drain electrode on the oxide semiconductor film, and a source electrode a drain electrode and an insulating film over the oxide semiconductor film. an oxide semiconductor film on an insulating surface, a gate insulating film on the oxide semiconductor film, and a gate insulating film A gate electrode overlapping with the oxide semiconductor film and functioning as a conductive film and a drain The bottom electrode includes a source electrode, a drain electrode, and an insulating film on the oxide semiconductor film. A semiconductor contact transistor has a gate electrode on an insulating surface and a gate insulator on the gate electrode. a source electrode and a drain electrode on the gate insulating film; and an oxide semiconductor film overlapping the gate electrode on the gate insulating film, and a source electrode. , a drain electrode, and an insulating film over the oxide semiconductor film.

[0022] The heat treatment is performed in a furnace or by rapid thermal annealing (RTA). The RTA method uses a lamp light source, and moves the substrate through a heated gas for a short time. There is a method for performing heat treatment. When the RTA method is used, the time required for heat treatment is reduced to less than 0.1 hours. However, if a glass substrate is used, the time can be set to 300°C or more. The heat treatment is carried out at a temperature equal to or lower than the distortion point of the glass substrate. [Effects of the Invention]

[0023] It is possible to provide a method for manufacturing a highly reliable semiconductor device. It is possible to provide a method for manufacturing a semiconductor device. Furthermore, it is possible to provide a semiconductor device that can be driven at high speed. [Brief explanation of the drawings]

[0024]

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Mode for Carrying Out the Invention

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0026] Note that the present invention can be used for manufacturing various semiconductor devices such as integrated circuits such as microprocessors and image processing circuits, RF tags, semiconductor display devices, etc. A semiconductor device means all devices that can function by utilizing semiconductor characteristics. Semiconductor display devices, semiconductor circuits and electronic devices are all semiconductor devices. Semiconductor display devices include liquid crystal display devices, light-emitting devices having a light-emitting element such as an organic light-emitting element (OLED) provided in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Displa y), and other semiconductor display devices having circuit elements using a semiconductor film in their drive circuits are included in that category.

[0027] (Embodiment 1) Taking a bottom-gate type thin film transistor with a channel etch structure as an example, the fabrication method of the semiconductor device will be described with reference to FIGS. 1 to 3.

[0028] As shown in FIG. 1(A), a gate electrode 101 is formed on a substrate 100.

[0029] An insulating film serving as an underlayer film may be formed between the substrate 100 and the gate electrode 101. The underlayer film may be, for example, a single layer of any one of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, a aluminum nitride film, or an aluminum oxynitride film, or a plurality of them may be stacked and used. In particular, for the underlayer film, an insulating film with high barrier properties, such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film, etc. is used to prevent moisture, impurities in the atmosphere such as hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate 100 from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof.

[0030] In this specification, an oxynitride means a substance having a higher oxygen content than nitrogen in its composition, and a nitride oxide means a substance having a higher nitrogen content than oxygen in its composition.

[0031] The material of the gate electrode 101 is molybdenum, titanium, chromium, tantalum, tungsten, ne Metal materials such as osmium and scandium, and alloy materials mainly composed of these metal materials can be used for the conductive film, or nitrides of these metals can be used either singly or in layers. If it can withstand the temperature of the heat treatment performed in the subsequent process, aluminum and copper can also be used as the above metal materials. Aluminum or copper is preferably used in combination with a high melting point metal material in order to avoid problems of heat resistance and corrosion resistance. Examples of the high melting point metal material include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used.

[0032] For example, as the gate electrode 101 having a two-layer laminated structure, a two-layer laminated structure in which a molybdenum film is laminated on an aluminum film, or a two-layer structure in which a molybdenum film is laminated on a copper film, or a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film, or a two-layer structure in which a titanium nitride film and a molybdenum film are laminated is preferred. As the gate electrode 101 having a three-layer laminated structure, it is preferable to have a structure in which an aluminum film, an alloy film of aluminum and silicon, an alloy film of aluminum and titanium or an alloy film of aluminum and neodymium is used as an intermediate layer, and a tungsten film, a tungsten nitride film, a titanium nitride film or a titanium film is laminated as upper and lower layers.

[0033] In addition, by using a transparent oxide conductive film such as indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, or gallium zinc oxide for the gate electrode 101, the aperture ratio of the pixel portion can be improved.

[0034] ​​​​​​​The film thickness of the gate electrode 101 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after forming a conductive film for the gate electrode with a thickness of 150 nm by a sputtering method using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching to form the gate electrode 101.

[0035] Next, a gate insulating film 102 is formed on the gate electrode 101. The gate insulating film 102 can be formed by using a plasma CVD method, a sputtering method, or the like to form a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, aluminum oxide, or tantalum oxide. It is desirable that the gate insulating film 102 contains as few impurities such as moisture and hydrogen as possible. The gate insulating film 102 may have a structure in which an insulating film using a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio are laminated. In this case, the insulating films such as the silicon oxide film and the silicon oxynitride film are formed between the insulating film with barrier properties and the oxide semiconductor film. Examples of the insulating film with high barrier properties include a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. By using an insulating film with barrier properties, it is possible to prevent impurities such as moisture or hydrogen in the atmosphere or impurities such as alkali metals and heavy metals contained in the substrate from entering the oxide semiconductor film, the gate insulating film 102, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof. Also, by forming an insulating film such as a silicon nitride oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor film, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor film. ​

[0036] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 10 having a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 2.

[0037] Next, an oxide semiconductor film is formed over the gate insulating film 102. The oxide semiconductor film is formed by a sputtering method using a semiconductor as a target. In a rare gas (e.g., argon) atmosphere, in an oxygen atmosphere, or in a rare gas (e.g., argon) and It can be formed by sputtering in an oxygen atmosphere.

[0038] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating film 102 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma on the substrate and modify the surface. It should be noted that nitrogen, helium, etc. may be used instead of the argon atmosphere. Alternatively, the heating may be performed in an argon atmosphere to which oxygen, hydrogen, nitrous oxide, or the like has been added. The treatment may be carried out in an argon atmosphere to which chlorine, carbon tetrafluoride, or the like has been added.

[0039] For the oxide semiconductor film, any of the above oxide semiconductors can be used.

[0040] The thickness of the oxide semiconductor film is 10 nm to 300 nm, preferably 20 nm to 100 nm. In this embodiment, the oxide semiconductor film is formed using an oxide semiconductor film containing indium (In), gallium (Ga), An oxide semiconductor target containing In (indium) and Zn (zinc) (molar ratio: In2O3:Ga2O3: ZnO = 1:1:1, In2O3:Ga2O3:ZnO = 1:1:2) is used for sputtering to obtain an In-Ga-Zn-O-based oxide semiconductor with a film thickness of 30 nm. In this embodiment, the DC sputtering method is used, the flow rate of argon is 30 sccm, the flow rate of oxygen is 1 5 sccm, and the substrate temperature is room temperature.

[0041] The gate insulating film 102 and the oxide semiconductor film may be continuously formed without exposing them to the atmosphere. By continuously forming the film without exposing it to the atmosphere, the interface can form each laminated interface without being contaminated by atmospheric components such as water and hydrocarbons and impurity elements floating in the air, so that the variation in thin film transistor characteristics can be reduced.

[0042] Next, as shown in Fig. 1(A), the oxide semiconductor film is processed (patterned) into a desired shape by etching or the like, and an island-shaped oxide semiconductor film 103 is formed on the gate insulating film 102 at a position overlapping the gate electrode 101.

[0043] Next, the oxide semiconductor film 103 may be heat-treated in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.). By heat-treating the oxide semiconductor film 103 an oxide semiconductor film 104 from which moisture and hydrogen have desorbed is formed. Specifically, under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra-dry air atmosphere. When measured using a dew point meter of the CRDS (Cavity Ring Down Laser Spectroscopy) method, the moisture content is 20 ppm (dew point conversion of -55 °C) or less, preferably 1 ppm or less, preferably Or in an atmosphere of air with a concentration of 10 ppb or less), in an atmosphere of air with a concentration of 10 ppb or less), at a temperature of 500 °C or higher and 750 °C or lower (if or a temperature below the strain point of the glass substrate), for about 1 minute or more and 10 minutes or less, preferably 600 °C and perform a Rapid Thermal Anneal (RTA) treatment for about 3 minutes or more and 6 minutes or less. By using the RTA method, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate. Note that the above heat treatment is not limited to the timing after the formation of the island-shaped oxide semiconductor film 103, and may be performed on the oxide semiconductor film before the formation of the island-shaped oxide semiconductor film 103. Further, the above heat treatment may be performed multiple times after the formation of the oxide semiconductor film 104. The island-shaped oxide semiconductor film 104 has impurities such as moisture and hydrogen desorbed by the above heat treatment, and becomes an i-type (intrinsic semiconductor) or extremely close to the i-type. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced.

[0044] In this embodiment, in a nitrogen atmosphere, at 600 °C, when the substrate temperature reaches the above set temperature, the heat treatment is performed for 6 minutes. The heat treatment can use a heating method using an electric furnace, a Gas Rapid Thermal Anneal (GRTA) method using a heated gas, or an instant heating method such as a Lamp Rapid Thermal Anneal (LRTA) method using lamp light. For example, when performing the heat treatment using an electric furnace, it is preferable that the temperature increase characteristic is 0.1 °C / min or more and 20 °C / min or less, and the temperature decrease characteristic is 0.1 °C / min or more and 15 °C / min or less.

[0045] ​In the heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water moisture, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0046] Next, as shown in FIG. 1(C), a conductive film for a source electrode and a drain electrode is formed on the island-shaped oxide semiconductor film 104. In this embodiment, a conductive film 105a made of a metal material such as titanium, tungsten, or molybdenum with low contact resistance to the oxide semiconductor film 104 is used and a conductive film 105b made of a metal, metal compound, or alloy with low electronegativity is formed thereon. As the metal with low electronegativity, aluminum or magnesium can also be used. A mixture, metal compound, or alloy containing any one or more of the above metals can be used as the conductive film 105b . Also, when using a material with low heat resistance such as aluminum, the heat resistance of the conductive film 105b can be increased by combining aluminum with an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium

[0047] or an alloy containing one or more of the above elements as components, or a heat-resistant conductive material such as a nitride containing the above elements as components. The film thickness of the conductive film 105a is preferably 10 nm to 200 nm, more preferably 50 nm to 150 nm. Also, the film thickness of the conductive film 105b is 100 nm to 300 nm, preferably

[0048] It is desirable to set it to 150 nm to 250 nm. In this embodiment, as the conductive film 105a, , a titanium film with a thickness of 100 nm formed by sputtering is used. As the conductive film 105b, , an aluminum film with a thickness of 200 nm formed by sputtering is used.

[0049] In one aspect of the present invention, since a metal, metal compound or alloy with a low electronegativity is used as the conductive film 105b, impurities such as moisture or hydrogen present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof are occluded or adsorbed by the conductive film 105b. Therefore, by desorbing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is extremely close to the i-type can be obtained, and deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. In addition to the above configuration, with the conductive film 105b exposed, heat treatment may be performed in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or

[0050] a noble gas (argon, helium, etc.) to remove moisture, oxygen, etc. adsorbed on the surface and inside of the conductive film 105b. The temperature range of the heat treatment is set to 200°C to 450°C. By performing the above heat treatment, impurities such as moisture and hydrogen present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof can be more easily occluded or adsorbed by the conductive film 105b. substantially occluded or adsorbed by the conductive film 105b. Then, as shown in Fig. 1(D), the conductive film 105a and the conductive film 105 are etched or the like.

[0051] Next, as shown in Fig. 1(D), the conductive film 105a and the conductive film 105 are etched or the like. By processing (patterning) b into a desired shape, the source electrode 106 and the drain electrode 1 07 are formed. For example, when a titanium film is used for the conductive film 105a and an aluminum film is used for the conductive film 105b, after wet-etching the conductive film 105b using a solution containing phosphoric acid , the conductive film 105a may be wet-etched using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid , and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for ammonia peroxide, , specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5: 2:2 is used. Alternatively, the conductive film 105a and the conductive film 105b may be dry-etched using a gas containing chlorine (Cl2), boron trichloride (BCl3), or the like. When forming the source electrode 106 and the drain electrode 107 by the above patterning, a part of the exposed portion of the island-shaped

[0052] oxide semiconductor film 104 may be etched, thereby forming a groove portion (recess). In this embodiment, a case where an island-shaped oxide semiconductor film 108 having a groove portion (recess) is formed by the above etching is exemplified. The conductive film 105a used for a part of the source electrode 106 and the drain electrode 107 is in contact with the oxide semiconductor film 108. And, since a metal material having a low contact resistance with the oxide semiconductor film 108 as described above is used for the conductive film 105a, the contact resistance between the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased. ​​​​​

[0053] Note that, as shown in FIG. 1(E), after forming the source electrode 106 and the drain electrode 107, an insulating film 109 is formed so as to cover the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108. It is desirable that the insulating film 109 contains as little moisture and impurities such as hydrogen as possible, and it may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. It is desirable to use a material with high barrier properties for the insulating film 109. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the above-mentioned insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 108. Then, with the insulating film with a lower nitrogen ratio sandwiched therebetween, a barrier insulating film is formed so as to overlap the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108. By using the barrier insulating film, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 106 and the drain electrode 107. Also, it is possible to prevent impurities such as moisture or hydrogen from entering into the oxide semiconductor film 108, the gate insulating film 102, or the interface between the oxide semiconductor film 108 and other insulating films and the vicinity thereof. Further, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio in contact with the oxide semiconductor film 108, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor film 108. In this embodiment, on a silicon oxide film with a thickness of 200 nm formed by sputtering, sputtering

[0054] ​ An insulating film 109 having a structure in which a silicon nitride film with a thickness of 100 nm formed by a method is laminated is formed. The substrate temperature during film formation may be from room temperature to 300 °C, and in this embodiment it is set to 100 °C.

[0055] By providing contact between the exposed region of the oxide semiconductor film 108 provided between the source electrode 106 or the drain electrode 107 and the silicon oxide constituting the insulating film 109, oxygen is supplied to the region of the oxide semiconductor film 108 in contact with the insulating film 109, resulting in an increase in resistance (a decrease in carrier concentration, preferably less than 1×10 / cm ), and an oxide semiconductor film 108 having a channel formation region with increased resistance can be formed. 18 / cm 3 3 and having a channel formation region with increased resistance. The oxide semiconductor film 108 can be formed.

[0056] Note that after forming the insulating film 109, a heat treatment may be performed. The heat treatment is performed in an air atmosphere , a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra-dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm or less (dew point conversion of -55 °C), preferably 1 ppm or less , preferably 10 ppb or less of air) atmosphere, preferably at 200 °C or higher and 400 °C or lower (for example, 250 °C or higher and 350 °C or lower). In this embodiment, for example, a heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. Alternatively, before forming the conductive film 105a and the conductive film 105 b, an RTA treatment with a high temperature and short time may be performed in the same manner as the previous heat treatment performed on the oxide semiconductor film. When this heat treatment is performed, the oxide semiconductor film 108 is heated in a state of being in contact with the silicon oxide constituting the insulating film 109, and further, the oxide semiconductor film 108 is heated in a state of being in contact with the silicon oxide constituting the insulating film 109, and further, the oxide semiconductor film 108 To increase the resistance and improve the electrical characteristics of the transistor and reduce the variation in the electrical characteristics This can be achieved. The timing of performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 109 and can be carried out in combination with other processes, such as the heat treatment during resin film formation or the heat treatment for reducing the resistance of the transparent conductive film, without increasing the number of processes.

[0057] Fig. 2 shows a top view of the semiconductor device shown in Fig. 1(E). Fig. 1(E) corresponds to a cross-sectional view taken along the dashed line A1 - A2 in Fig. 2.

[0058] The transistor 110 includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101 , an oxide semiconductor film 108 on the gate insulating film 102, a source electrode 106 and a drain electrode 107 on the oxide semiconductor film 108, and an insulating film 109 on the source electrode 106, the drain electrode 107, and the oxide semiconductor film 108.

[0059] Next, after forming a conductive film on the insulating film 109, by patterning the conductive film, as shown in Fig. 3(A), a back gate electrode 111 may be formed at a position overlapping the oxide semiconductor film 108. The back gate electrode 111 can be formed using the same material and structure as the gate electrode 101, or the source electrode 10 6 and the drain electrode 107.

[0060] The film thickness of the back gate electrode 111 is 10 nm to 400 nm, preferably 100 nm to 20 0 nm. In this embodiment, a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are laminated is formed. Then, a resist mask is formed by photolithography, and unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning ing).​​​​​ By performing (etching), the back gate electrode 111 is formed.

[0061] Next, as shown in Fig. 3(B), an insulating film 112 is formed so as to cover the back gate electrode 111. The insulating film 112 preferably uses a highly barrier material that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor 110. For example, As a highly barrier insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film, etc. can be formed as a single layer or laminated by a plasma CVD method, a sputtering method, etc. In order to obtain the effect of the barrier property, the insulating film 112 is preferably formed with a film thickness of, for example, 15 nm to 400 nm.

[0062] In this embodiment, an insulating film with a thickness of 300 nm is formed by the plasma CVD method. The film formation conditions are such that the flow rate of silane gas is 4 sccm and the flow rate of dinitrogen monoxide (N2O) is 800 sccm and the substrate temperature is 400°C.

[0063] Fig. 3(C) shows a top view of the semiconductor device shown in Fig. 3(B). Fig. 3(B) corresponds to a cross-sectional view taken along the dashed line A1 - A2 in Fig. 3(C).

[0064] Note that in Fig. 3(B), the case where the back gate electrode 111 covers the entire oxide semiconductor film 108 is illustrated, but the present invention is not limited to this configuration. The back gate electrode 111 only needs to overlap at least a part of the channel formation region of the oxide semiconductor film 108.

[0065] The back gate electrode 111 may be in a floating state where it is electrically insulated. Moreover, it may be in a state where a potential is applied. In the latter case, the back gate electrode 111 may be applied with the same potential as the gate electrode 101, or may be applied with a fixed potential such as ground. By controlling the height of the potential applied to the back gate electrode 111, the threshold voltage of the transistor 110 can be controlled. Even if the same potential as the gate electrode 101 is applied, or a fixed potential such as ground may be applied. By controlling the height of the potential applied to the back gate electrode 111, the threshold voltage of the transistor 110 can be controlled.

[0066] As in this embodiment, removing impurities such as hydrogen and water contained in the oxide semiconductor film as much as possible and purifying the oxide semiconductor film highly affect the characteristics of the transistor, which will be described below. How does it affect the characteristics of the transistor? This will be described below.

[0067] FIG. 27 shows a longitudinal sectional view of an inverted staggered thin film transistor using an oxide semiconductor. An oxide semiconductor film (OS) is provided on a gate electrode (GE) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon.

[0068] FIG. 28 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 27. FIG. 28(A) shows the case where the voltage between the source electrode and the drain electrode is set to an equipotential (VD = 0V), and FIG. 28(B) shows the case where a positive potential (VD> 0) is applied to the drain electrode with respect to the source electrode.

[0069] FIG. 29 is an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 27. FIG. 29(A) shows a state where a positive potential (+ VG) is applied to the gate (GE), and shows an on state in which carriers (electrons) flow between the source electrode and the drain electrode. Further, FIG. 29(B) shows a state where a negative potential (-VG) is applied to the gate (G1), and shows a case of an off state (where few carriers flow). ​

[0070] Figure 30 shows the relationship between the vacuum level, the work function (φM) of the metal, and the electron affinity (χ) of the oxide semiconductor. It is shown.

[0071] Since the metal is degenerate, the conduction band and the Fermi level coincide. On the other hand, conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (Ef) is located away from the intrinsic Fermi level (Ei) located at the center of the band gap and closer to the conduction band (Ec). Note that in the oxide semiconductor, hydrogen is a donor and is known to be one of the factors for the n-type conversion of the oxide semiconductor. In contrast, the oxide semiconductor according to the present invention uses a metal having an electronegativity lower than that of hydrogen for the source electrode or the conductive film for the drain electrode, thereby removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. Thus, the oxide semiconductor is intended to be intrinsic (i-type) or intrinsic type. That is, instead of adding impurities to make the oxide semiconductor i-type, by removing impurities such as hydrogen and water as much as possible and purifying it to a high purity, it is characterized by obtaining an oxide semiconductor that is extremely close to i-type (intrinsic semiconductor) or i-type (intrinsic semiconductor). With the above configuration, as shown by the arrow, the Fermi level (Ef) can be made extremely close to the same level as the intrinsic Fermi level (Ei). When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work of titanium (Ti) constituting the source electrode and the drain electrode In the oxide semiconductor, hydrogen is a donor and is known to be one of the factors for the n-type conversion of the oxide semiconductor. It is known.

[0072] In contrast, the oxide semiconductor according to the present invention uses a metal having an electronegativity lower than that of hydrogen for the source electrode or the conductive film for the drain electrode, thereby removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. By doing so, the oxide semiconductor is made as pure as possible without containing impurities other than the main component of the oxide semiconductor. By removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that impurities other than the main component of the oxide semiconductor are not contained as much as possible. As a result, the oxide semiconductor is intended to be intrinsic (i-type) or intrinsic type. That is, Instead of adding impurities to make the oxide semiconductor i-type, By removing impurities such as hydrogen and water as much as possible and purifying it to a high purity, An oxide semiconductor that is extremely close to i-type (intrinsic semiconductor) or i-type (intrinsic semiconductor) is obtained. With the above configuration, as shown by the arrow, The Fermi level (Ef) can be made extremely close to the same level as the intrinsic Fermi level (Ei). It is possible.

[0073] When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work of titanium (Ti) constituting the source electrode and the drain electrode The work function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons. That is, when the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 28(A) is shown.

[0074] That is, when the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 28(A) is shown. That is, when the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 28(A) is shown.

[0075] In Fig. 28(B), the black circles (●) indicate electrons. When a positive potential is applied to the drain electrode, the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain electrode. In this case, the height of the barrier (h) changes depending on the gate voltage and the drain voltage. However, when a positive drain voltage is applied, the height of the barrier in Fig. 28(A) without voltage application, that is, the height (h) of the barrier is smaller than 1 / 2 of the band gap (Eg).

[0076] At this time, the electrons move to the lowest energy-stable part on the oxide semiconductor side at the interface between the gate insulating film and the highly purified oxide semiconductor as shown in Fig. 29(A). At this time, the electrons move to the lowest energy-stable part on the oxide semiconductor side at the interface between the gate insulating film and the highly purified oxide semiconductor as shown in Fig. 29(A).

[0077] Also, in Fig. 29(B), when a negative potential (reverse bias) is applied to the gate electrode (G1), since the number of minority carriers, holes, is substantially zero, the current becomes a value extremely close to zero. That is, the current becomes a value extremely close to zero.

[0078] For example, even for an element with a channel width W of a thin film transistor of 1×10 4 μm and a channel length of 3 μm, the off-current is 10 -13 A or less, and a subthreshold swing value (S value ) of 0.1 V / dec. (gate insulating film thickness 100 nm) can be obtained.

[0079] In this way, by minimizing the inclusion of impurities such as water and hydrogen other than the main component of the oxide semiconductor, purifying the oxide semiconductor film can improve the operation of the thin film transistor.

[0080] (Embodiment 2) Taking a bottom gate type thin film transistor with a channel etch structure as an example, the manufacturing method of the semiconductor device will be described with reference to FIG. 4.

[0081] First, according to the manufacturing method shown in Embodiment 1, as shown in FIG. 4(A), on the island-shaped oxide semiconductor film 104, a conductive film 105b made of a metal material such as titanium, tungsten or molybdenum with low contact resistance to the oxide semiconductor film 104 is formed on a conductive film 105a. On the conductive film 105a, a conductive film 105b made of a metal, metal compound or alloy with low electronegativity is formed. Regarding the types of materials, structures, and the range of film thicknesses used for the conductive film 105a and the conductive film 105b, they have already been described in Embodiment 1, so the description will be omitted here. In this embodiment, as the conductive film 105a, a titanium film with a thickness of 100 nm formed by sputtering is used, and as the conductive film 105b, an aluminum film with a thickness of 200 nm formed by sputtering is used.

[0082] After forming the conductive film 105a and the conductive film 105b, with the conductive film 105b exposed, heat treatment may be performed in a reduced pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium). The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1.

[0083] Next, as shown in FIG. 4(B), the conductive film 105b is removed by etching or the like.​​​​ For the recording etching, wet etching is preferably used to prevent the conductive film 105a from being etched. Specifically, in the present embodiment, since an aluminum film is used for the conductive film 105b, a solution containing phosphoric acid, for example, a mixed acid aluminum solution manufactured by Wako Pure Chemical Industries, Ltd. ( aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used for wet etching to remove the conductive film 105b. When dry etching is used to remove the conductive film 105b, a gas containing chlorine (Cl2), boron trichloride (BCl 3), etc. may be used. However, in the case of dry etching, since there is no difference in the selectivity between the conductive film 105a which is a titanium film and the conductive film 105b which is an aluminum film, the dry etching time may be controlled so that the conductive film 105a remains during the etching. etching. etching is used to remove the conductive film 105b, a gas containing chlorine (Cl2), boron trichloride (BCl 3), etc. may be used. However, in the case of dry etching, since there is no difference in the selectivity between the conductive film 105a which is a titanium film and the conductive film 105b which is an aluminum film, the dry etching time may be controlled so that the conductive film 105a remains during the etching. etching. etching time may be controlled so that the conductive film 105a remains during the etching. That's fine.

[0084] In the conductive film 105b, impurities such as moisture or hydrogen existing inside the oxide semiconductor film 104, inside the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof are occluded or adsorbed. Therefore, by removing the conductive film 105b, the moisture or impurities such as hydrogen occluded or adsorbed in the conductive film 10 5b can also be removed together. 5b can also be removed together. That's possible.

[0085] Next, as shown in FIG. 4(C), a conductive film 105c using a metal, metallized compound or alloy having a low electronegativity is newly formed on the conductive film 105a. The type of material used for the conductive film 105c and the range of its film thickness are the same as those of the conductive film 105b. In the present embodiment, an aluminum film with a film thickness of 200 nm formed by sputtering is used as the conductive film 10 5c. 5c. That's it.

[0086] In one aspect of the present invention, after removing the conductive film 105b, a metal, metal compound, or alloy having a low electronegativity is used to newly form the conductive film 105c. The conductive film 105c is more likely to occlude or adsorb impurities such as moisture or hydrogen than the conductive film 105b in which impurities are already occluded or adsorbed. Therefore, the impurities present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof can be reduced more than in the case of Embodiment 1. Therefore, by desorbing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is extremely close to the i-type can be obtained, preventing deterioration of transistor characteristics such as threshold voltage shift caused by the above impurities, and reducing the off-current. After forming the conductive film 105c, in a state where the conductive film 105c is exposed, heat treatment may be performed again in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium). The temperature range of the heat treatment is 200°C to 450°C as in Embodiment 1. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof can be made more likely to be occluded or adsorbed by the conductive film 105c.

[0087] After forming the conductive film 105c, in a state where the conductive film 105c is exposed, heat treatment may be performed again in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium). The temperature range of the heat treatment is 200°C to 450°C as in Embodiment 1. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and another insulating film and in the vicinity thereof can be made more likely to be occluded or adsorbed by the conductive film 105c.

[0088] Next, as shown in FIG. 4(D), by processing (patterning) the conductive film 105a and the conductive film 105c into a desired shape by etching or the like, the source electrode 126 and the drain electrode 1 ​​​​​​​​​​​​​​Form 27. For example, a titanium film is used for the conductive film 105a and an aluminum film is used for the conductive film 105c. When using such, after wet - etching the conductive film 105c with a solution containing phosphoric acid , use a solution containing ammonia and hydrogen peroxide water (ammonia peroxide water) to wet - etch the conductive film 105a. Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid , and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for ammonia peroxide water, specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5: 2:2 is used. Alternatively, a gas containing chlorine (Cl2), boron trichloride (BCl3), etc. may be used to dry - etch the conductive film 105a and the conductive film 105c.

[0089] When forming the source electrode 126 and the drain electrode 127 by the above patterning, when a part of the exposed portion of the island - shaped oxide semiconductor film 104 is etched, a groove portion (recess) may be formed. In this embodiment, a case where an island - shaped oxide semiconductor film 128 having a groove portion (recess) is formed by the above etching is exemplified. A part of the conductive film 105a used for the source electrode 126 and the drain electrode 127 is in contact with the oxide semiconductor film 128. And, since a metal material with low contact resistance with the oxide semiconductor film 128 is used for the conductive film 105a as described above, the contact resistance between the source electrode 126, the drain electrode 127, and the oxide semiconductor film 128 is reduced. Therefore, the on - current and the field - effect mobility of the TFT can be increased.

[0090] Then, after forming the source electrode 126 and the drain electrode 127, an insulating film 129 is formed so as to cover the source electrode 126, the drain electrode 127, and the oxide semiconductor film 128. Regarding the type, structure, and thickness range of the material used for the insulating film 129, it is the same as the insulating film 109 described in Embodiment 1. In this embodiment, a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering to form an insulating film 129 having a structure. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is 100°C.

[0091] By providing contact between the exposed region of the oxide semiconductor film 128 provided between the source electrode 126 or the drain electrode 127 and the silicon oxide constituting the insulating film 129, the region of the oxide semiconductor film 128 in contact with the insulating film 129 becomes highly resistive (the carrier concentration decreases, preferably less than 1×10 / cm 18 ), and an oxide semiconductor film 128 having a highly resistive channel formation region can be formed. 3

[0092] After forming the insulating film 129, a heat treatment may be performed. For the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1.

[0093] The thin film transistor 120 formed according to the above manufacturing method includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 128 on the gate insulating film 102, a source electrode 126 and a drain electrode 127 on the oxide semiconductor film 128, and a source electrode It has a drain electrode 126, an insulating film 129 on the oxide semiconductor film 128, and the like.

[0094] Next, after forming a conductive film on the insulating film 129, the conductive film is patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 128. The type, structure, and thickness range of the material used for the back gate electrode are the same as those of the back gate electrode 111 described in Embodiment 1, so the description is omitted here. When forming the back gate electrode, an insulating film may be formed so as to cover the back gate electrode. The type, structure, and thickness range of the material used for the insulating film covering the back gate electrode are the same as those of the insulating film 112 described in Embodiment 1, so the description is omitted here. This embodiment can be implemented in appropriate combination with the above embodiments.

[0095]

[0096]

[0097] (Embodiment 3) Taking a bottom gate type thin film transistor with a channel etch structure as an example, the manufacturing method of the semiconductor device will be described with reference to FIG. 5.

[0098] First, according to the manufacturing method shown in Embodiment 1, as shown in FIG. 5(A), on the island-shaped oxide semiconductor film 104, a conductive film 105b made of a metal, metal compound, or alloy with a low electronegativity is formed on a conductive film 105a made of a metal material such as titanium, tungsten, or molybdenum having a low contact resistance with the oxide semiconductor film 104. The type, structure, and thickness range of the material used for the conductive film 105a and the conductive film 105b have already been described in Embodiment 1, so the description is omitted here. In this embodiment, as the conductive film 105a ​​​​​​​​​​​ Then, using a titanium film with a thickness of 100 nm formed by sputtering, as the conductive film 105b, use an aluminum film with a thickness of 200 nm formed by sputtering.

[0099] After forming the conductive film 105a and the conductive film 105b, in a state where the conductive film 105b is exposed, under reduced pressure atmosphere, heat treatment may be performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon, helium, etc.). The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1.

[0100] Next, as shown in FIG. 5(B), remove the conductive film 105b by etching or the like. For the above mentioned etching, in order to prevent the conductive film 105a from being etched, it is desirable to use wet etching. Specifically, in this embodiment, since an aluminum film is used for the conductive film 105b, a solution containing phosphoric acid, for example, a mixed acid aluminum solution manufactured by Wako Pure Chemical Industries, Ltd. ([[]] aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used for wet etching to remove the conductive film 105b. When removing the conductive film 105b using dry etching, it is advisable to use a gas containing chlorine (Cl2), boron trichloride (BCl 3), etc. However, in the case of dry etching, since there is no difference in the selectivity ratio between the titanium film conductive film 105a and the aluminum film conductive film 105b, the dry etching time can be controlled so that the conductive film 105a remains during etching. That's all right. The conductive film 105b is formed within the oxide semiconductor film 104, within the gate insulating film 102, or within the oxide or good.

[0101] In the conductive film 105b, within the oxide semiconductor film 104, within the gate insulating film 102, or in the oxide Impurities such as moisture or hydrogen present at the interface between the semiconductor film 104 and other insulating films and in the vicinity thereof are occluded or adsorbed. Therefore, by removing the conductive film 105b, the impurities such as moisture or hydrogen occluded or adsorbed in the conductive film 105b can also be removed together. Next, as shown in FIG. 5(C), a conductive film 105c made of a metal, metallized compound or alloy having a low electronegativity and a conductive film 105d made of a metal material such as titanium, tungsten or molybdenum capable of preventing oxidation of the conductive film 105c are newly formed on the conductive film 105a. The type of material used for the conductive film 105c and the range of its film thickness are the same as those of the conductive film 105b. Also, the film thickness of the conductive film 105d is desirably 10 nm to 200 nm, preferably 50 nm to 150 nm. In the present embodiment, an aluminum film with a film thickness of 200 nm formed by sputtering is used as the conductive film 105c, and a titanium film with a film thickness of 100 nm formed by sputtering is used as the conductive film 105d.

[0102] Next, as shown in FIG. 5(C), a conductive film 105c made of a metal, metallized compound or alloy having a low electronegativity and a conductive film 105d made of a metal material such as titanium, tungsten or molybdenum capable of preventing oxidation of the conductive film 105c are newly formed on the conductive film 105a. The type of material used for the conductive film 105c and the range of its film thickness are the same as those of the conductive film 105b. Also, the film thickness of the conductive film 105d is desirably 10 nm to 200 nm, preferably 50 nm to 150 nm. In the present embodiment, an aluminum film with a film thickness of 200 nm formed by sputtering is used as the conductive film 105c, and a titanium film with a film thickness of 100 nm formed by sputtering is used as the conductive film 105d. In one aspect of the present invention, after removing the conductive film 105b, a conductive film 105c is newly formed using a metal, metallized compound or alloy having a low electronegativity. The conductive film 105c is more likely to occlude or adsorb impurities such as moisture or hydrogen than the conductive film 105b that already has impurities occluded or adsorbed. Therefore, the impurities present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof can be reduced more than in the case of Embodiment 1. Therefore, by desorbing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is infinitely close to the i-type can be obtained.

[0103] In one aspect of the present invention, after removing the conductive film 105b, a conductive film 105c is newly formed using a metal, metallized compound or alloy having a low electronegativity. The conductive film 105c is more likely to occlude or adsorb impurities such as moisture or hydrogen than the conductive film 105b that already has impurities occluded or adsorbed. Therefore, the impurities present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof can be reduced more than in the case of Embodiment 1. Therefore, by desorbing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is infinitely close to the i-type can be obtained.​​​​​​​​​​ can be achieved, and deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced.

[0104] After forming the conductive film 105d, in a state where the conductive film 105d is exposed, under a reduced-pressure atmosphere, in an inert gas atmosphere of nitrogen, or a rare gas (such as argon or helium), heat treatment may be performed again. The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1. By performing the above heat treatment, moisture or hydrogen or other impurities present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof can be more easily occluded or adsorbed by the conductive film 105c.

[0105] Next, as shown in FIG. 5(D), by processing (patterning) the conductive film 105a, the conductive film 105c, and the conductive film 105d into a desired shape, the source electrode 136 and the drain electrode 137 are formed. For example, when a titanium film is used for the conductive film 105a, an aluminum film is used for the conductive film 105c, and a titanium film is used for the conductive film 105d, a solution containing ammonia and hydrogen peroxide (ammonia peroxide) is used to wet-etch the conductive film 105d. After that, a solution containing phosphoric acid is used to wet-etch the conductive film 105c, and then a solution containing ammonia and hydrogen peroxide (ammonia peroxide) is used to wet-etch the conductive film 105a. Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (2.0 wt% nitric acid, 9.8 wt% acetic acid, 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. An aqueous solution containing % by weight of phosphoric acid is used. Specifically, the aqueous ammonia peroxide is an aqueous solution obtained by mixing 31% by weight of hydrogen peroxide solution, 28% by weight of aqueous ammonia, and water in a volume ratio of 5:2:2. Alternatively, a gas containing chlorine (Cl2), boron trichloride (BCl3), etc. may be used to dry-etch the conductive films 105a, 105c, and 105d.

[0106] When forming the source electrode 136 and the drain electrode 137 by the above patterning, a groove (concave portion) may be formed by partially etching the exposed portion of the island-shaped oxide semiconductor film 104. In this embodiment, a case where an island-shaped oxide semiconductor film 138 having a groove (concave portion) is formed by the above etching is illustrated. The conductive film 105a used for a part of the source electrode 136 and the drain electrode 137 is in contact with the oxide semiconductor film 138. And since a metal material having a low contact resistance with the oxide semiconductor film is used for the conductive film 105a as described above, the contact resistance between the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased. [[ID=…]]

[0107] After forming the source electrode 136 and the drain electrode 137, an insulating film 139 is formed so as to cover the source electrode 136, the drain electrode 137, and the oxide semiconductor film 138. Regarding the type, structure, and thickness range of the material used for the insulating film 139, it is the same as the insulating film 109 described in Embodiment 1. In this embodiment, a silicon nitride film having a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film having a thickness of 200 nm formed by sputtering. ​​​​​​​​​​​The substrate temperature during film formation is set to a value higher than room temperature and higher than 300° C. In this embodiment, the temperature is set to 100°C.

[0108] Exposure of the oxide semiconductor film 138 provided between the source electrode 136 or the drain electrode 137 The region is in contact with the silicon oxide constituting the insulating film 139, Oxygen is supplied to the region of the oxide semiconductor film 138 in contact with the oxide semiconductor film 39, and the region becomes highly resistive (the carrier concentration is Lower, preferably 1×10 18 / cm 3 (less than 1000 MHz) and have a highly resistive channel formation region. The oxide semiconductor film 138 can be formed in this manner.

[0109] After the insulating film 139 is formed, heat treatment may be performed. The conditions for the heat treatment are as follows: In the first embodiment, the conditions for the heat treatment performed after forming the insulating film 109 are as follows: That's good.

[0110] The thin film transistor 130 formed according to the above manufacturing method comprises a gate electrode 101 and a gate electrode 102. The gate insulating film 102 on the gate electrode 101 and the oxide semiconductor film 138 on the gate insulating film 102 a source electrode 136 and a drain electrode 137 on the oxide semiconductor film 138; 136 , a drain electrode 137 , and an insulating film 139 over an oxide semiconductor film 138 .

[0111] Next, a conductive film is formed on the insulating film 139, and then the conductive film is patterned. A back gate electrode may be formed at a position overlapping the nitride semiconductor film 138. The type of material used for the electrode, the structure, and the range of the film thickness are the same as those of the first embodiment. Since it is similar to the back gate electrode 111, the explanation will be omitted here.

[0112] When the back gate electrode is formed, an insulating film is formed so as to cover the back gate electrode. The type, structure, and film thickness range of the material used for the insulating film covering the back gate electrode are the same as those of the insulating film 112 described in Embodiment 1, and thus the description thereof is omitted here.

[0113] This embodiment can be implemented in appropriate combination with the above-described embodiment.

[0114] (Embodiment 4) Taking a bottom gate type thin film transistor with a channel etch structure as an example, the manufacturing method of the semiconductor device will be described with reference to FIG. 6.

[0115] First, according to the manufacturing method shown in Embodiment 1, as shown in FIG. 6(A), on the island-shaped oxide semiconductor film 104, a conductive film 105b made of a metal material such as titanium, tungsten ten, or molybdenum, which has a low contact resistance with the oxide semiconductor film 104, is formed on a conductive film 105a. On the conductive film 105a, a conductive film 105b made of a metal, metal compound, or alloy having a low electronegativity is formed. The type, structure, and film thickness range of the materials used for the conductive film 105a and the conductive film 105b have already been described in Embodiment 1, and thus the description thereof is omitted here. In this embodiment, as the conductive film 105a, a titanium film with a thickness of 100 nm formed by sputtering is used, and as the conductive film 105b, an aluminum film with a thickness of 200 nm formed by sputtering is used.

[0116] After forming the conductive film 105a and the conductive film 105b, in a state where the conductive film 105b is exposed, under a reduced pressure atmosphere, in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) The temperature range for the heat treatment is 200° C. or more, as in the first embodiment. Up to 450°C.

[0117] Next, as shown in FIG. 6(B), the conductive film 105b is removed by etching or the like. In the etching, wet etching is used to prevent the conductive film 105a from being etched. Specifically, in this embodiment, aluminum is used for the conductive film 105b. Since a membrane is used, it is not possible to use a solution containing phosphoric acid, such as the aluminum mixed acid solution ( Contains 2.0% by weight of nitric acid, 9.8% by weight of acetic acid, and 72.3% by weight of phosphoric acid. The conductive film 105b is removed by wet etching using a dry etching solution. When the conductive film 105b is removed by etching, chlorine (Cl), boron chloride (BCl 3) It is recommended to use a gas containing titanium. Since there is no difference in the selectivity between the conductive film 105a and the conductive film 105b, which is an aluminum film, The dry etching time may be controlled so that the conductive film 105a remains during the etching. stomach.

[0118] The conductive film 105b may include a film formed in the oxide semiconductor film 104, the gate insulating film 102, or the oxide Impurities such as moisture or hydrogen present at the interface between the semiconductor film 104 and other insulating films and in the vicinity thereof Therefore, by removing the conductive film 105b, the conductive film 1 It can also remove impurities such as moisture or hydrogen absorbed or adsorbed by 05b. can.

[0119] Next, as shown in FIG. 6C, a conductive film 105a is formed on the conductive film 105a so as to contact the oxide semiconductor film 104. The conductive film 105 made of a metal material such as titanium, tungsten or molybdenum with low resistance e, the conductive film 105c made of a metal, metal compound or alloy with low electronegativity, and the conductive film 105c, a conductive film 105d made of a metal material such as titanium, tungsten or molybdenum that can prevent oxidation of the conductive film is newly formed. The thickness range of the conductive film 105e or the conductive film 105d is the same as that of the conductive film 105a. The type of material used for the conductive film 105c and its thickness range are the same as those of the conductive film 105b. In this embodiment, as the conductive film 105c , an aluminum film with a thickness of 200 nm formed by sputtering is used, and as the conductive film 105 d, a titanium film with a thickness of 100 nm formed by sputtering is used, and as the conductive film 105e a titanium film with a thickness of 100 nm formed by sputtering is used.

[0120] In one aspect of the present invention, after removing the conductive film 105b, a conductive film 105c is newly formed using a metal, metal compound or alloy with low electronegativity. The conductive film 105c is more likely to occlude or adsorb impurities such as moisture or hydrogen than the conductive film 105b that already occludes or adsorbs impurities. Therefore, the above impurities present in the oxide semiconductor film 104, in the gate insulating film 102 , or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof can be reduced more than in the case of Embodiment 1. Therefore, by desorbing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 104 that is extremely close to the i-type can be obtained, and the deterioration of transistor characteristics such as the shift of the threshold voltage due to the above impurities can be prevented, and the off-current can be reduced.

[0121] ​​​​​​After forming the conductive film 105d, in a state where the conductive film 105d is exposed, in a reduced-pressure atmosphere or an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), heat treatment may be performed again. The temperature range of the heat treatment is 200°C to 450°C, similar to that in Embodiment 1. By performing the above heat treatment, moisture or hydrogen and other impurities present in the oxide semiconductor film 104, in the gate insulating film 102, or at the interface between the oxide semiconductor film 104 and other insulating films and in the vicinity thereof can be easily occluded or adsorbed by the conductive film 105c.

[0122] Next, as shown in FIG. 6(D), by processing (patterning) the conductive films 105a, 105c, 105d, and 105e of the desired shape, the source electrode 146 and the drain electrode 147 are formed. For example, when a titanium film is used for the conductive film 105a, an aluminum film for the conductive film 105c, a titanium film for the conductive film 105d, and a titanium film for the conductive film 105e, a solution containing ammonia and hydrogen peroxide water (ammonia peroxide) is used. After wet-etching the conductive film 105d, a solution containing phosphoric acid is used to wet-etch the conductive film 105c, and then a solution containing ammonia and hydrogen peroxide water (ammonia peroxide) is used to wet-etch the conductive films 105e and 105a. Specifically, in the present embodiment, as the solution containing phosphoric acid, a mixed acid alumite solution manufactured by Wako Pure Chemical Industries, Ltd. (an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used. Also, specifically for ammonia peroxide, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5:2:2 is used. Specifically, in the present embodiment, as the solution containing phosphoric acid, a mixed acid alumite solution manufactured by Wako Pure Chemical Industries, Ltd. (an aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) is used. Also, specifically for ammonia peroxide, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5:2:2 is used. an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5:2:2 is used. ​. Alternatively, a gas containing chlorine (Cl2), boron trichloride (BCl3), etc. is used to form the conductive film 10 5a, the conductive film 105c, the conductive film 105d, and the conductive film 105e may be dry-etched .

[0123] When forming the source electrode 146 and the drain electrode 147 by the above patterning, the exposed portion of the island-shaped oxide semiconductor film 104 is partially etched, and thus a groove portion (concave portion) may be formed. In the present embodiment, a case where an island-shaped oxide semiconductor film 148 having a groove portion (concave portion) is formed by the above etching is exemplified. The conductive film 105a used for a part of the source electrode 146 and the drain electrode 147 is in contact with the oxide semiconductor film 148 . And, since a metal material having a low contact resistance with the oxide semiconductor film 148 as described above is used for the conductive film 105a, the contact resistance between the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased. . And, after forming the source electrode 146 and the drain electrode 147, an insulating film 149 is formed so as to cover the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148. Regarding the type, structure, and range of the film thickness of the material used for the insulating film 149, it is the same as the insulating film 109 described in Embodiment 1 . In the present embodiment, an insulating film 149 having a structure in which a silicon nitride film having a film thickness of 100 nm formed by sputtering is laminated on a silicon oxide film having a film thickness of 20 0 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in the present embodiment, it is 100 °C.

[0124] . And, after forming the source electrode 146 and the drain electrode 147, an insulating film 149 is formed so as to cover the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148. Regarding the type, structure, and range of the film thickness of the material used for the insulating film 149, it is the same as the insulating film 109 described in Embodiment 1 . In the present embodiment, an insulating film 149 having a structure in which a silicon nitride film having a film thickness of 100 nm formed by sputtering is laminated on a silicon oxide film having a film thickness of 20 0 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in the present embodiment, it is 100 °C. 0 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in the present embodiment, it is 100 °C. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in the present embodiment, it is 100 °C. It is sufficient that the substrate temperature during film formation is room temperature or higher and 300 °C or lower, and in the present embodiment, it is 100 °C.

[0125] Exposure of the oxide semiconductor film 148 provided between the source electrode 146 or the drain electrode 147 and the silicon oxide constituting the insulating film 149 are provided in contact with each other, so that the insulating film 1 Oxygen is supplied to the region of the oxide semiconductor film 148 in contact with the insulating film 149, resulting in an increase in resistance (the carrier concentration decreases, preferably to less than 1×10 / cm 18 / cm 3 / cm³), and an oxide semiconductor film 148 having a channel formation region with increased resistance can be formed. An oxide semiconductor film 148 having a channel formation region with increased resistance can be formed.

[0126] After forming the insulating film 149, a heat treatment may be performed. For the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. For the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. That's all.

[0127] The thin film transistor 140 formed according to the above manufacturing method includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 148 on the gate insulating film 102, a source electrode 146 and a drain electrode 147 on the oxide semiconductor film 148, and an insulating film 149 on the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148. The thin film transistor 140 formed according to the above manufacturing method includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 148 on the gate insulating film 102, a source electrode 146 and a drain electrode 147 on the oxide semiconductor film 148, and an insulating film 149 on the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148. The thin film transistor 140 formed according to the above manufacturing method includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 148 on the gate insulating film 102, a source electrode 146 and a drain electrode 147 on the oxide semiconductor film 148, and an insulating film 149 on the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148. The thin film transistor 140 formed according to the above manufacturing method includes a gate electrode 101, a gate insulating film 102 on the gate electrode 101, an oxide semiconductor film 148 on the gate insulating film 102, a source electrode 146 and a drain electrode 147 on the oxide semiconductor film 148, and an insulating film 149 on the source electrode 146, the drain electrode 147, and the oxide semiconductor film 148.

[0128] Next, after forming a conductive film on the insulating film 149, the conductive film is patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 148. For the type, structure, and thickness range of the material used for the back gate electrode, it is the same as the back gate electrode 111 described in Embodiment 1, so the description is omitted here. Next, after forming a conductive film on the insulating film 149, the conductive film is patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 148. For the type, structure, and thickness range of the material used for the back gate electrode, it is the same as the back gate electrode 111 described in Embodiment 1, so the description is omitted here. Next, after forming a conductive film on the insulating film 149, the conductive film is patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 148. For the type, structure, and thickness range of the material used for the back gate electrode, it is the same as the back gate electrode 111 described in Embodiment 1, so the description is omitted here. Next, after forming a conductive film on the insulating film 149, the conductive film is patterned to form a back gate electrode at a position overlapping the oxide semiconductor film 148. For the type, structure, and thickness range of the material used for the back gate electrode, it is the same as the back gate electrode 111 described in Embodiment 1, so the description is omitted here.

[0129] When the back gate electrode is formed, an insulating film is formed so as to cover the back gate electrode. Regarding the type, structure, and thickness range of the material used for the insulating film covering the hook gate electrode , it is the same as the insulating film 112 described in Embodiment 1, so the description is omitted here.

[0130] This embodiment can be implemented in appropriate combination with the above embodiments.

[0131] (Embodiment 5) In this embodiment, a bottom gate type thin film transistor of the channel protection structure will be taken as an example, and a method for manufacturing a semiconductor device will be described with reference to FIGS. 7, 8, and 9. Note that the same parts or parts having similar functions as those in Embodiment 1, and the processes can be carried out in the same manner as in Embodiment 1 , so repeated descriptions are omitted.

[0132] As shown in FIG. 7(A), a gate electrode 301 is formed on a substrate 300 having an insulating surface . An insulating film serving as an underlayer film may be provided between the substrate 300 and the gate electrode 301. Regarding the material, structure, and thickness of the gate electrode 301, reference may be made to the description of the gate electrode 301 shown in Embodiment 1. Regarding the material, structure, and thickness of the underlayer film, reference may be made to the description of the underlayer film shown in Embodiment 1 .

[0133] Next, a gate insulating film 302 is formed on the gate electrode 301. Regarding the material, thickness, and structure of the gate insulating film 302, and the manufacturing method, reference may be made to the description of the gate insulating film 302 shown in Embodiment 1 .

[0134] Next, an island-shaped oxide semiconductor film 303 is formed on the gate insulating film 302. Regarding the material, thickness, and structure of the island-shaped oxide semiconductor film 303, and the manufacturing method, reference may be made to the description of the oxide ​Refer to the description of the oxide semiconductor film 103.

[0135] Next, in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or ultra-dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method), with a water content of 20 ppm or less (dew point conversion: -55 °C), preferably 1 ppm or less, and more preferably 10 ppb or less of air), the island-shaped oxide semiconductor film 3 03 is heat-treated. Regarding the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. m or less, preferably 10 ppb or less of air) atmosphere, the island-shaped oxide semiconductor film 3 03 is heat-treated. For the heat treatment of the oxide semiconductor film 303, refer to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1. Referring to the description of the heat treatment of the oxide semiconductor film 103 shown in Embodiment 1 is sufficient. By heat-treating the oxide semiconductor film 303 in the above atmosphere, as shown in FIG. 7(B), an island-shaped oxide semiconductor film 304 from which moisture and hydrogen contained in the oxide semiconductor film 303 have desorbed is formed. The island-shaped oxide semiconductor film 304 is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen due to the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. The island-shaped oxide semiconductor film 304 is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen due to the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. The island-shaped oxide semiconductor film 304 is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen due to the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. The island-shaped oxide semiconductor film 304 is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen due to the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. The island-shaped oxide semiconductor film 304 is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen due to the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. The island-shaped oxide semiconductor film 304 is formed. The island-shaped oxide semiconductor film 304 desorbs impurities such as moisture and hydrogen due to the above heat treatment and becomes type i (intrinsic semiconductor) or extremely close to type i. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced.

[0136] Next, as shown in FIG. 7(C), a channel protection film 311 is formed on the oxide semiconductor film 304 so as to overlap with the portion that becomes the channel formation region of the oxide semiconductor film 304. By providing the channel protection film 311, damage (such as film loss due to plasma or etching agent during etching) to the portion that becomes the channel formation region of the oxide semiconductor film 304 during subsequent processes can be prevented. Therefore, the reliability of the thin film transistor can be improved. Next, as shown in FIG. 7(C), a channel protection film 311 is formed on the oxide semiconductor film 304 so as to overlap with the portion that becomes the channel formation region of the oxide semiconductor film 304. By providing the channel protection film 311, damage (such as film loss due to plasma or etching agent during etching) to the portion that becomes the channel formation region of the oxide semiconductor film 304 during subsequent processes can be prevented. By providing the channel protection film 311, damage (such as film loss due to plasma or etching agent during etching) to the portion that becomes the channel formation region of the oxide semiconductor film 304 during subsequent processes can be prevented. By providing the channel protection film 311, damage (such as film loss due to plasma or etching agent during etching) to the portion that becomes the channel formation region of the oxide semiconductor film 304 during subsequent processes can be prevented. Therefore, the reliability of the thin film transistor can be improved.

[0137] For the channel protection film 311, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. The channel protection film 311 can be formed using a vapor deposition method such as plasma CVD method or thermal CVD method, or a sputtering method. The shape of the channel protection film 311 is processed by etching after film formation. Here, a silicon oxide film is formed by sputtering method, and the channel protection film 311 is formed by etching using a mask by photolithography.

[0138] Also, when a channel protection film 311, which is an insulating film such as silicon oxide or silicon oxynitride, is formed by sputtering method or PCVD method in contact with the island-shaped oxide semiconductor film 304, oxygen is supplied to at least the region in contact with the channel protection film 311 in the island-shaped oxide semiconductor film 304, and the carrier concentration preferably becomes lower than 1×10 18 / cm 3 1 4 / cm 3 By forming the channel protection film 311, the oxide semiconductor film 304 can have a high-resistance oxide semiconductor region near the interface with the channel protection film 311.

[0139] Next, on the island-shaped oxide semiconductor film 304, a conductive film 305a made of a metal material such as titanium, tungsten, or molybdenum with a low contact resistance with the oxide semiconductor film 304, and a conductive film 305b made of a metal, metal compound, or alloy with a low electron negativity are formed in this order. The types, structures, film thickness ranges of the materials used for the conductive film 305a and the conductive film 305b, and their production ​​​​​​​​​​​​​​Regarding the method, refer to the description of the conductive films 105a and 105b shown in Embodiment 1. In this embodiment, as the conductive film 305a, a titanium film with a thickness of 100 nm formed by sputtering is used. As the conductive film 305b, an aluminum film with a thickness of 200 nm formed by sputtering is used.

[0140] In one aspect of the present invention, since a metal, metal compound, or alloy with a low electronegativity is used as the conductive film 305b, moisture, hydrogen, or other impurities present in the oxide semiconductor film 304, within the gate insulating film 302, or at the interface between the oxide semiconductor film 304 and other insulating films and in the vicinity thereof are occluded or adsorbed by the conductive film 305b. Therefore, by removing impurities such as moisture and hydrogen, an i-type (intrinsic semiconductor) or an oxide semiconductor film 304 that is extremely close to the i-type can be obtained, and deterioration of transistor characteristics such as threshold voltage shift caused by the above impurities can be prevented, and the off-current can be reduced.

[0141] After forming the conductive film 305a and the conductive film 305b, in a state where the conductive film 305b is exposed, heat treatment may be performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) under a reduced pressure atmosphere. The temperature range of the heat treatment is 200°C to 450°C, similar to Embodiment 1.

[0142] Next, as shown in FIG. 7(D), by processing (patterning) the conductive film 305a and the conductive film 305b into a desired shape by etching or the like, the source electrode 306 and the drain electrode 3 07 are formed. For example, a titanium film for the conductive film 305a and an aluminum film for the conductive film 305b When using [a certain method], after wet etching the conductive film 305b with a solution containing phosphoric acid , the conductive film 305a can be wet-etched using a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (aqueous solution containing 2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for the ammonia peroxide, specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5: 2:2 is used. Alternatively, the conductive film 305a and the conductive film 305b may be dry-etched using a gas containing chlorine (Cl2), boron trichloride (BCl3), etc.

[0143] The conductive film 305a used for a part of the source electrode 306 and the drain electrode 307 is in contact with the oxide semiconductor film 304. And, as described above, since a metal material with low contact resistance with the oxide semiconductor film is used for the conductive film 305a, the contact resistance between the source electrode 306, the drain electrode 307, and the oxide semiconductor film 304 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased.

[0144] And, as shown in FIG. 7(E), after forming the source electrode 306 and the drain electrode 307, an insulating film 309 is formed so as to cover the oxide semiconductor film 304, the source electrode 306, the drain electrode 307, and the channel protection film 311. Regarding the type, structure, and the range of the film thickness of the material used for the insulating film 309, it is the same as the insulating film 109 described in Embodiment 1. In this embodiment, on a silicon oxide film with a film thickness of 200 nm formed by sputtering, by sputtering An insulating film 309 having a structure in which a silicon nitride film with a thickness of 100 nm formed thereon is laminated is formed. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 1 00°C.

[0145] After forming the insulating film 309, heat treatment may be performed. Regarding the conditions of the above heat treatment, refer to the conditions of the heat treatment performed after forming the insulating film 109 in Embodiment 1. That's all.

[0146] FIG. 8 shows a top view of the semiconductor device shown in FIG. 7(E). FIG. 7(E) corresponds to a cross-sectional view taken along the dashed line C1- C2 in FIG. 8.

[0147] The thin film transistor 310 formed according to the above manufacturing method includes a gate electrode 301, a gate insulating film 302 on the gate electrode 301, an oxide semiconductor film 304 on the gate insulating film 302, a channel protection film 311 on the oxide semiconductor film 304, a source electrode 306 and a drain electrode 307 on the oxide semiconductor film 304, and an insulating film 309 on the oxide semiconductor film 304, the source electrode 306, the drain electrode 307, and the channel protection film 311.

[0148] Next, as shown in FIG. 9(A), after forming a conductive film on the insulating film 309, the conductive film is patterned to form a back gate electrode 312 at a position overlapping the oxide semiconductor film 304. The type, structure, and thickness range of the material used for the back gate electrode 312 are the same as those of the back gate electrode 111 described in Embodiment 1, so the description is omitted here.

[0149] When the back gate electrode 312 is formed, as shown in FIG. 9(B), the back gate electrode 3

[0149] ​ An insulating film 313 is formed so as to cover 12. Regarding the type and structure of the material used for the insulating film 313 , and the range of its film thickness, it is the same as the insulating film 112 described in Embodiment 1, so the description thereof is omitted here.

[0150] FIG. 9(C) shows a top view of the semiconductor device shown in FIG. 9(B). FIG. 9(B) is a cross-sectional view taken along the dashed line C1-C2 of FIG. 9(C).

[0151] In this embodiment, an example is shown in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1, but the present invention is not limited to this configuration. The source electrode and the drain electrode may be formed according to the manufacturing methods shown in Embodiments 2 to 4 .

[0152] This embodiment can be implemented in appropriate combination with the above embodiments.

[0153] (Embodiment 6)[[ID= 30]] In this embodiment, a bottom contact type thin film transistor will be taken as an example, and the manufacturing method of the semiconductor device will be described with reference to FIGS. 10 and 11. Note that the same parts or parts having the same functions, and the processes as those in Embodiment 1 can be carried out in the same manner as in Embodiment 1, so the repeated description is omitted.

[0154] As shown in FIG. 10(A), a gate electrode 401 is formed on a substrate 400 having an insulating surface. An insulating film serving as an underlayer may be provided between the substrate 400 and the gate electrode 401. Regarding the material, structure, and film thickness of the gate electrode 401, reference may be made to the description of the gate electrode 401 shown in Embodiment 1. Regarding the material, structure, and film thickness of the underlayer film, those in Embodiment 1 ​​​​​​​Refer to the description of the shown base film.

[0155] Next, a gate insulating film 402 is formed on the gate electrode 401. For the material, film thickness, structure, and manufacturing method of the gate insulating film 402, refer to the description of the gate insulating film 402 shown in Embodiment 1. Refer to the description of the gate insulating film 402 shown in Embodiment 1. Refer to the description of the gate insulating film 402 shown in Embodiment 1.

[0156] Next, on the gate insulating film 402, a conductive film 405a made of a metal, metal compound, or alloy with a low electronegativity and a conductive film 405b made of a metal material such as titanium, tungsten, or molybdenum, which has a low contact resistance with the oxide semiconductor film 404, are formed in sequence. For the types of materials, structures, film thickness ranges, and manufacturing methods used for the conductive film 405b and the conductive film 405a, refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. In this embodiment, as the conductive film 405a, an aluminum film with a film thickness of 200 nm formed by sputtering is used, and as the conductive film 405b, a titanium film with a film thickness of 100 nm formed by sputtering is used. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1.

[0157] After forming the conductive film 405a and the conductive film 405b, heat treatment may be performed in a reduced pressure atmosphere or an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.) with the conductive film 405b exposed. The temperature range of the heat treatment is 200°C to 450°C as in Embodiment 1. For example, when an aluminum film is used for the conductive film 405a and a titanium film is used for the conductive film 405b, after wet-etching the conductive film 405b using a solution containing ammonia and hydrogen peroxide solution (ammonia peroxide), the conductive film 405a is etched using a solution containing phosphoric acid. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. Refer to the description of the conductive film 105a and the conductive film 105b shown in Embodiment 1. It may be wet-etched. Specifically, in this embodiment, as a solution containing phosphoric acid , a mixed acid aluminum solution (2.0 wt% nitric acid, 9.8 wt% acetic acid , and 72.3 wt% phosphoric acid) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, for the ammonia peroxide , specifically, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide solution, 28 wt% ammonia water, and water at a volume ratio of 5 :2:2 is used. Alternatively, the conductive film 405a and the conductive film 405b may be dry-etched using a gas containing chlorine (Cl2), boron trichloride (BCl3), or the like . .

[0158] Next, as shown in FIG. 10(B), by processing (patterning) the conductive film 405a and the conductive film 40 5b into a desired shape by etching or the like, the source electrode 406 and the drain electrode 407 are formed.

[0159] Next, as shown in FIG. 10(C), an island-shaped oxide semiconductor film 403 is formed over the gate insulating film 402, the source electrode 406, and the drain electrode 407. Regarding the material, film thickness, structure, and manufacturing method of the island-shaped oxide semiconductor film 403, reference may be made to the description of the oxide semiconductor film 10 3 in Embodiment 1.

[0160] Next, in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or ultra-dry air (air with a moisture content of 20 ppm (dew point conversion: -55°C) or less, preferably 1 pp m or less, preferably 10 ppb or less, measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method) atmosphere, the island-shaped oxide semiconductor film 4 03 is heat-treated. Regarding the heat treatment of the oxide semiconductor film 403, refer to Embodiment 1. Refer to the description of the heat treatment of the oxide semiconductor film 103 shown above. Acid By heat-treating the oxide semiconductor film 403 in the above atmosphere, as shown in Fig. 10(D), An island-shaped oxide semiconductor film 404 from which moisture and hydrogen contained in the oxide semiconductor film 403 have desorbed is formed. The island-shaped oxide semiconductor film 404 desorbs impurities such as moisture and hydrogen by the above heat treatment, and becomes an i-type (intrinsic semiconductor) or extremely close to the i-type. Therefore, deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. In one aspect of the present invention, since a metal, metal compound, or alloy with a low electronegativity is used as the conductive film 405a, moisture or impurities such as hydrogen present in the oxide semiconductor film 404, in the gate insulating film 402, or at the interface between the oxide semiconductor film 404 and another insulating film and in the vicinity thereof are occluded or adsorbed by the conductive film 405a. Therefore, an i-type (intrinsic semiconductor) or an oxide semiconductor film 404 extremely close to the i-type can be obtained by desorption of impurities such as moisture and hydrogen, and deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. Moreover, the conductive film 405b used for a part of the source electrode 406 and the drain electrode 407 is in contact with the oxide semiconductor film 404. And since a metal material having a low contact resistance with the oxide semiconductor film as described above is used for the conductive film 405b, the contact resistance between the source electrode 406, the drain electrode 407, and the oxide semiconductor film 404 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased.

[0161] In one aspect of the present invention, since a metal, metal compound, or alloy with a low electronegativity is used as the conductive film 405a, moisture or impurities such as hydrogen present in the oxide semiconductor film 404, in the gate insulating film 402, or at the interface between the oxide semiconductor film 404 and another insulating film and in the vicinity thereof are occluded or adsorbed by the conductive film 405a. Therefore, an i-type (intrinsic semiconductor) or an oxide semiconductor film 404 extremely close to the i-type can be obtained by desorption of impurities such as moisture and hydrogen, and deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. Moreover, the conductive film 405b used for a part of the source electrode 406 and the drain electrode 407 is in contact with the oxide semiconductor film 404. And since a metal material having a low contact resistance with the oxide semiconductor film as described above is used for the conductive film 405b, the contact resistance between the source electrode 406, the drain electrode 407, and the oxide semiconductor film 404 is reduced. Therefore, an i-type (intrinsic semiconductor) or an oxide semiconductor film 404 extremely close to the i-type can be obtained by desorption of impurities such as moisture and hydrogen, and deterioration of transistor characteristics such as threshold voltage shift due to the above impurities is prevented, and the off-current can be reduced. Moreover, the conductive film 405b used for a part of the source electrode 406 and the drain electrode 407 is in contact with the oxide semiconductor film 404. And since a metal material having a low contact resistance with the oxide semiconductor film as described above is used for the conductive film 405b, the contact resistance between the source electrode 406, the drain electrode 407, and the oxide semiconductor film 404 is reduced.

[0162] In addition, the conductive film 405b used for a part of the source electrode 406 and the drain electrode 407 is in contact with the oxide semiconductor film 404. And since a metal material having a low contact resistance with the oxide semiconductor film as described above is used for the conductive film 405b, the contact resistance between the source electrode 406, the drain electrode 407, and the oxide semiconductor film 404 is reduced. Therefore, the on-current and the field-effect mobility of the TFT can be increased. Therefore, the on-current and the field-effect mobility of the TFT can be increased.

[0163] Next, as shown in FIG. 10(E), a source electrode 406 and a drain electrode 407 were formed. Then, an insulating film is formed to cover the oxide semiconductor film 404, the source electrode 406, and the drain electrode 407. The type of material used for the insulating film 409, its structure, and the range of its thickness are described below. The insulating film 109 is the same as that of the insulating film 109 described in the first embodiment. A silicon oxide film with a thickness of 100 nm was formed by sputtering on a silicon oxide film with a thickness of 200 nm formed by the annealing method. The insulating film 409 has a structure in which silicon nitride films of 100 nm thick are stacked. The temperature may be set to a temperature above room temperature and below 300°C, and is set to 100°C in this embodiment.

[0164] After the insulating film 409 is formed, heat treatment may be performed. In the first embodiment, the conditions for the heat treatment performed after forming the insulating film 109 are as follows: That's good.

[0165] 11 shows a top view of the semiconductor device shown in FIG. 10(E). This corresponds to a cross-sectional view taken along line B1-B2.

[0166] The thin film transistor 410 formed according to the above manufacturing method includes a gate electrode 401 and a gate electrode 402. A gate insulating film 402 on the gate electrode 401, a source electrode 406 on the gate insulating film 402, and The drain electrode 407, the gate insulating film 402, the source electrode 406, and the drain electrode 407 The oxide semiconductor film 404, the source electrode 406, and the drain electrode and an insulating film 409 on the electrode 407.

[0167] Next, a conductive film is formed on the insulating film 409, and then the conductive film is patterned to form an oxide film. A back gate electrode may be formed at a position overlapping with the compound semiconductor film 404. Regarding the type of material, structure, and the range of its film thickness used for the back gate electrode, it is the same as the back gate electrode 111 described in Embodiment 1, so the description is omitted here.

[0168] When the back gate electrode is formed, an insulating film is formed so as to cover the back gate electrode. Regarding the type of material, structure, and the range of its film thickness used for the above insulating film, it is the same as the insulating film 112 described in Embodiment 1, so the description is omitted here.

[0169] This embodiment can be implemented in appropriate combination with the above embodiments.

[0170] (Embodiment 7) In this embodiment, a method for manufacturing a semiconductor display device according to an aspect of the present invention will be described with reference to FIGS. 12 to 17.

[0171] In this specification, continuous film formation means that during a series of processes from the first film formation step performed by sputtering to the second film formation step performed by sputtering, the atmosphere in which the substrate to be processed is placed does not come into contact with a contaminated atmosphere such as air, and is always controlled in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere). By performing continuous film formation, reattachment of moisture and the like to the cleaned substrate to be processed can be avoided, and film formation can be performed.

[0172] Performing a series of processes from the first film formation step to the second film formation step within the same chamber is considered to be within the scope of continuous film formation in this specification.

[0173] Also, performing a series of processes from the first film formation step to the second film formation step in different chambers In the case of [the above], after the first film-forming step, the substrate is transported between chambers without being exposed to the atmosphere, and it is assumed that performing the second film-forming also falls within the scope of continuous film-forming in this specification.

[0174] Note that between the first film-forming step and the second film-forming step, there may be a substrate transport step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc., and it is assumed that this also falls within the scope of continuous film-forming in this specification.

[0175] However, if a step using a liquid such as a cleaning step, wet etching, or resist formation is present between the first film-forming step and the second film-forming step, it is not considered to fall within the scope of continuous film-forming as referred to in this specification.

[0176] In FIG. 12(A), for the light-transmissive substrate 800, in addition to a glass substrate produced by the fusion method or the float method, a substrate having an insulating film provided on the surface of a metal substrate such as a stainless steel alloy may also be applied. Further, a substrate made of a flexible synthetic resin such as plastic generally has a tendency of a low heat-resistant temperature, but if it can withstand the processing temperature in the subsequent manufacturing steps, it can be used as the substrate 800. As the plastic substrate, polyesters typified by polyethylene terephthalate (PET), polyethersulfone (PES) , polyethylene naphthalate (PEN), polycarbonate (PC), polyether ether ketone (PEEK), polysulfone (PSF), polyetherimide (PEI), poly arylate (PAR), polybutylene terephthalate (PBT), polyimide, acry lonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate can be used. ​, examples include acrylic resins.

[0177] In addition, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use one with a strain point of 730 °C or higher. Further, for the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. By including more barium oxide (BaO) compared to boric acid, a more practical heat-resistant glass can be obtained.

[0178] Alternatively, instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can also be used.

[0179] Next, after forming a conductive film on the entire surface of the substrate 800, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wiring and electrodes (gate wiring including the gate electrode 801, capacitor wiring 822, and the first terminal 821). At this time, etching is performed so that at least a tapered shape is formed at the end of the gate electrode 801.

[0180] As the material of the conductive film, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, alloy materials mainly composed of these metal materials, or nitrides of these metals can be used either singly or in a stacked layer. Note that if it can withstand the temperature of the heat treatment performed in the subsequent process, aluminum or copper can also be used as the above metal material.

[0181] For example, as a conductive film having a two-layer stacked structure, molybdenum is stacked on aluminum a two-layer stacked structure, or a two-layer structure with molybdenum stacked on a copper layer, or a two-layer structure with titanium nitride or tantalum nitride stacked on copper, or a two-layer structure with titanium nitride and molybdenum stacked is preferred. As the three-layer stacked structure, aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as the intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is used as the upper and lower layers and stacked to form a structure. Also, the aperture ratio can be improved by using a transparent oxide conductive film for some electrodes and wirings. For example, indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc oxide-aluminum oxide, aluminum zinc oxynitride or gallium zinc oxide can be used for the oxide conductive film. The film thicknesses of the gate electrode 801, the capacitive wiring 822, and the first terminal 821 are 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after forming a 100-nm conductive film for the gate electrode by sputtering using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching to form the gate electrode 801

[0182] the capacitive wiring 822, and the first terminal 821. Note that an insulating film serving as an underlying film may be provided between the substrate 800 and the gate electrode 801, the capacitive wiring 822, and the first terminal 821. As the underlying film, for example, a silicon oxide film, a silicon oxynitride film a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film can be used.

[0183] The film thicknesses of the gate electrode 801, the capacitive wiring 822, and the first terminal 821 are 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after forming a 100-nm conductive film for the gate electrode by sputtering using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching to form the gate electrode 801 the capacitive wiring 822, and the first terminal 821. the capacitive wiring 822, and the first terminal 821. After forming a 100-nm conductive film for the gate electrode by sputtering using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching to form the gate electrode 801 the capacitive wiring 822, and the first terminal 821.

[0184] Note that an insulating film serving as an underlying film may be provided between the substrate 800 and the gate electrode 801, the capacitive wiring 822, and the first terminal 821. As the underlying film, for example, a silicon oxide film, a silicon oxynitride film a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film can be used. Any one of them can be used singly or in multiple layers stacked. In particular, on the base film, an insulating film with high barrier properties, such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or also an aluminum oxynitride film, etc., is used to prevent impurities in the atmosphere such as moisture or hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate 800 from entering into the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and other insulating films and its vicinity.

[0185] Next, as shown in FIG. 12(B), a gate insulating film 802 is formed on the gate electrode 801, the capacitor wiring 822, and the first terminal 8 21. The gate insulating film 802 can be formed by using the plasma CVD method or the sputtering method, etc., as a single layer or a stack of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, aluminum oxide or tantalum oxide. The gate insulating film 802 desirably contains as few impurities such as moisture and hydrogen as possible. A gate insulating film 802 having a structure in which an insulating film using a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio are stacked may be formed. In this case, the insulating films such as the silicon oxide film and the silicon oxynitride film are formed between the insulating film having barrier properties and the oxide semiconductor film. Examples of the insulating film with high barrier properties include a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. By using an insulating film having barrier properties, impurities in the atmosphere such as moisture or hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate are prevented from entering into the oxide semiconductor film, the gate insulating film 80 2, or the interface between the oxide semiconductor film and other insulating films and its vicinity. prevented.​​​ This is possible. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio in contact with the oxide semiconductor film, it is possible to prevent an insulating film made of a highly barrier material from directly contacting the oxide semiconductor film.

[0186] In this embodiment, a gate insulating film 802 having a structure in which a 100-nm-thick silicon oxide film formed by sputtering is laminated on a 50-nm-thick silicon nitride film formed by sputtering is formed.

[0187] Next, after forming an oxide semiconductor film on the gate insulating film 802, the oxide semiconductor film is processed into a desired shape by etching or the like to form an island-shaped oxide semiconductor film 803. The oxide semiconductor film is formed by sputtering using an oxide semiconductor as a target. Also, the oxide semiconductor film can be formed by sputtering in an inert gas (e.g., argon) atmosphere, an oxygen atmosphere, or an atmosphere of an inert gas (e.g., argon) and oxygen.

[0188] Before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove dust adhering to the surface of the gate insulating film 802. Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma on the substrate and modify the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, it may be performed in an atmosphere in which oxygen, hydrogen, nitrous oxide, etc. are added to the argon atmosphere. Also, it may be performed in an atmosphere in which chlorine, carbon tetrafluoride, etc. are added to the argon atmosphere. ​​​​​​​​​​​​​

[0189] For the oxide semiconductor film for forming the channel formation region, an oxide material having semiconductor characteristics as described above may be used. That's all.

[0190] The film thickness of the oxide semiconductor film is 10 nm to 300 nm, preferably 20 nm to 100 nm. In this embodiment, here, an oxide semiconductor target (molar ratio is In2O3:Ga2O3:ZnO = 1:1:1, In2O3:Ga2O3: ZnO = 1:1:2) is used, the distance between the substrate and the target is 100 mm, and the pressure is 0. 6 Pa, a DC power supply of 0.5 kW, and film formation is performed in an oxygen (oxygen flow ratio 100%) atmosphere. Note that using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor target is used, and an In-Ga-Zn-O based polycrystalline film with a film thickness of 30 nm is formed by a sputtering apparatus. Note that by forming the oxide semiconductor film without exposing it to the atmosphere after plasma treatment, it is possible to prevent dust and moisture from adhering to the interface between the gate insulating film 802 and the oxide semiconductor film. Also using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform.

[0191] Note that by forming the oxide semiconductor film without exposing it to the atmosphere after plasma treatment, it is possible to prevent dust and moisture from adhering to the interface between the gate insulating film 802 and the oxide semiconductor film. Also using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. Note that by forming the oxide semiconductor film without exposing it to the atmosphere after plasma treatment, it is possible to prevent dust and moisture from adhering to the interface between the gate insulating film 802 and the oxide semiconductor film. Also using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform.

[0192] In addition, the relative density of the oxide semiconductor target is 80% or more, preferably 95% or more, and more preferably 99.9% or more. Using a target with a high relative density can reduce the impurity concentration in the formed oxide semiconductor film and obtain a thin film transistor with high electrical characteristics or reliability. That's all. That's all.

[0193] There are also multi-source sputtering apparatuses that can install multiple targets made of different materials. In a multi-source sputtering apparatus, it is possible to stack and form different material films in the same chamber, or to simultaneously discharge multiple types of materials in the same chamber to form a film.

[0194] There are also sputtering apparatuses that use the magnetron sputtering method with a magnet mechanism inside the chamber, and ECR sputtering apparatuses that use plasma generated by using microwaves without using glow discharge.

[0195] In addition, as a film formation method using the sputtering method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0196] During film formation by the sputtering method, the substrate may be heated to 400°C or higher and 700°C or lower by light or a heater. By heating during film formation, damage caused by sputtering can be repaired simultaneously with film formation.

[0197] Before forming an oxide semiconductor film, it is advisable to perform a preheating treatment to remove moisture or hydrogen remaining on the inner wall of the sputtering apparatus, the target surface, or in the target material. As the preheating treatment, there are methods such as heating the inside of the film formation chamber to 200°C to 600°C under reduced pressure, or a method of repeatedly introducing and exhausting nitrogen or an inert gas while heating. After the preheating treatment is completed, the substrate or the sputtering apparatus is cooled and then the oxide semiconductor film is formed without being exposed to the atmosphere. In this case, it is preferable to use a coolant for the target other Repeated nitrogen introduction and evacuation without heating can produce a certain effect, but And even better.

[0198] In addition, before, during, or after the formation of the oxide semiconductor film, It is preferable to remove the moisture remaining therein using a cryopump.

[0199] In the second photolithography process, a solution of, for example, phosphoric acid, acetic acid, and nitric acid is used. The oxide semiconductor film is processed into a desired shape by wet etching, and an island-shaped oxide semiconductor is formed. The island-shaped oxide semiconductor film 803 can be formed on the gate electrode 801. The oxide semiconductor film is etched using citric acid or oxalic acid. In this embodiment, an organic acid such as ITO07N can be used for etching. By wet etching using a material called 'Kanto Chemical Co., Ltd.', unnecessary parts are removed and the resulting oxide islands are formed. The semiconductor film 803 is formed. The etching here is not limited to wet etching. Alternatively, dry etching may be used.

[0200] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0201] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0202] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that the desired processing shape can be etched. Moreover, the etching solution after wet etching is removed by washing together with the etched material. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing the materials such as indium contained in the oxide semiconductor film from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced. The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired shape can be processed.

[0203] Also, the etching solution after wet etching is removed by washing together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing the materials such as indium contained in the oxide semiconductor film from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0204] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired shape can be processed.

[0205] Next, as shown in FIG. 12(C), under a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra-dry air (the moisture content when measured using a dew point meter of the CRDS (Cavity Ring-Down Spectroscopy) method is 20 ppm (dew point conversion of -55 °C ) or less, preferably 1 ppm or less, preferably 10 ppb or less of air) atmosphere, the oxide semiconductor film 803 may be heat-treated. By heat-treating the oxide semiconductor film 803, the oxide semiconductor film 804 is formed. Specifically, in an inert gas atmosphere (nitrogen or under helium, neon, argon, etc., at 500°C or higher and 750°C or lower (if the temperature is below the strain point of the glass substrate), for about 1 minute or more and 10 minutes or less, preferably 650°C and perform Rapid Thermal Anneal (RTA) treatment for about 3 minutes or more and 6 minutes or less. By using the RTA method, dehydration or dehydrogenation can be performed in a short time, so that it can be processed even at a temperature exceeding the strain point of the glass substrate. Note that the above heat treatment is not limited to the timing after the formation of the island-shaped oxide semiconductor film 803, and can also be performed on the oxide semiconductor film before etching. Also, the above heat treatment can be performed multiple times after the formation of the island-shaped oxide semiconductor film 803.

[0206] In this embodiment, under a nitrogen atmosphere, heat treatment is performed at 600°C for 6 minutes in a state where the substrate temperature has reached the above set temperature. The heat treatment can use a heating method using an electric furnace, a Gas Rapid Thermal Anneal (GRTA) method using heated gas or an instant heating method such as a Lamp Rapid Thermal Anneal (LRTA) method using lamp light. For example, when performing heat treatment using an electric furnace, it is preferable that the temperature increase characteristic is 0.1°C / min or more and 20°C / min or less, and the temperature decrease characteristic is 0.1°C / min or more and 15°C / min or less.

[0207] Note that in the heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water or hydrogen. Or, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, (that is, the impurity concentration is 1 ppm or less, preferably ​ It is preferably 0.1 ppm or less).

[0208] Note that the cross-sectional view within the range of the dashed line D1 - D2 in Fig. 12(C) and the cross-sectional view within the range of the dashed line E1 - E2 are equivalent to the cross-sectional view at the dashed line D1 - D2 and the cross-sectional view at the dashed line E1 - E2 in the plan view shown in Fig. 15.

[0209] Next, as shown in Fig. 13(A), a conductive film 806 to be used as a source electrode or a drain electrode is formed on the oxide semiconductor film 804 by a sputtering method or a vacuum evaporation method. In this embodiment, a conductive film 806 in which a conductive film 806b using a metal material such as titanium, tungsten, or molybdenum, which has a low contact resistance with the oxide semiconductor film 804, is laminated on a conductive film 806a using a metal, a metal compound, or an alloy having a low electronegativity is used. As the metal having a low electronegativity, aluminum or magnesium can also be used. A mixture, a metal compound, or an alloy containing any one or more of the above metals can be used as the conductive film 806b. Further, when using a material with low heat resistance such as aluminum, the heat resistance of the conductive film 806b may be increased by combining aluminum with an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, or an alloy containing one or more of the above elements as components, or a heat-resistant conductive material such as a nitride containing the above elements as components.

[0210] The film thickness of the conductive film 806a is desirably 10 nm to 200 nm, preferably 50 nm to 150 nm. Also, the film thickness of the conductive film 806b is 100 nm to 300 nm, preferably

[0211] ​​​​​​​​​It is desirable to be 150 nm to 250 nm. In the present embodiment, as the conductive film 806a, , a titanium film with a thickness of 100 nm formed by sputtering is used. As the conductive film 806b, , an aluminum film with a thickness of 200 nm formed by sputtering is used.

[0212] In one aspect of the present invention, since a metal, metal compound, or alloy with a low electronegativity is used as the conductive film 806b, in the oxide semiconductor film 804, in the gate insulating film 802, or at the interface between the oxide semiconductor film 804 and other insulating films and in the vicinity thereof, impurities such as moisture or hydrogen are occluded or adsorbed by the conductive film 806b. Therefore, by desorbing impurities such as moisture and hydrogen, it is possible to obtain an i-type (intrinsic semiconductor) or an oxide semiconductor film 804 that is extremely close to the i-type, and it is possible to prevent the deterioration of transistor characteristics such as the threshold voltage shift caused by the above impurities, and reduce the off-current. In addition to the above configuration, with the conductive film 806b exposed, heat treatment may be performed in a reduced-pressure atmosphere or in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.),

[0213] to remove moisture, oxygen, etc. adsorbed on the surface or inside of the conductive film 806b. The temperature range of the heat treatment is 200°C to 450°C. By performing the above heat treatment, impurities such as moisture or hydrogen present in the oxide semiconductor film 804, in the gate insulating film 802, or at the interface between the oxide semiconductor film 804 and other insulating films and in the vicinity thereof can be more easily occluded or adsorbed by the conductive film 806b. Subsequently, as shown in FIG. 13(B), a third photolithography process is performed for etching.

[0214] Next, as shown in FIG. 13(B), a third photolithography process is performed, and etching The conductive film 806a and the conductive film 806b are processed (patterned) into a desired shape by, etc. In this way, the source electrode 807 and the drain electrode 808 are formed. For example, when a titanium film is used for the conductive film 806a and an aluminum film is used for the conductive film 806b, after wet-etching the conductive film 806b with a solution containing phosphoric acid, the conductive film 806a may be wet-etched with a solution containing ammonia and hydrogen peroxide water (ammonia peroxide). Specifically, in this embodiment, as the solution containing phosphoric acid, a mixed acid aluminum solution (2.0 wt% nitric acid, 9.8 wt% acetic acid, and 72.3 wt% phosphoric acid, an aqueous solution containing) manufactured by Wako Pure Chemical Industries, Ltd. is used. Also, specifically for ammonia peroxide, an aqueous solution obtained by mixing 31 wt% hydrogen peroxide water, 28 wt% ammonia water, and water in a volume ratio of 5:2:2 is used. Alternatively, the conductive film 806a and the conductive film 806b may be dry-etched using a gas containing chlorine (Cl2), boron trichloride (BCl3), etc. When forming the source electrode 807 and the drain electrode 808 by the above patterning, a part of the exposed portion of the island-shaped oxide semiconductor film 804 may be etched, thereby forming a groove portion (recess). In this embodiment, a case where an island-shaped oxide semiconductor film 805 having a groove portion (recess) is formed by the above etching is exemplified. A part of the conductive film 806a used for the source electrode 807 and the drain electrode 808 is in contact with the oxide semiconductor film 805. And since a metal material having a low contact resistance with the oxide semiconductor film is used for the conductive film 806a as described above, the contact resistance between the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 is reduced. Therefore, the on-current of the TFT and

[0215] When forming the source electrode 807 and the drain electrode 808 by the above patterning, a part of the exposed portion of the island-shaped oxide semiconductor film 804 may be etched, thereby forming a groove portion (recess). In this embodiment, a case where an island-shaped oxide semiconductor film 805 having a groove portion (recess) is formed by the above etching is exemplified. A part of the conductive film 806a used for the source electrode 807 and the drain electrode 808 is in contact with the oxide semiconductor film 805. And since a metal material having a low contact resistance with the oxide semiconductor film is used for the conductive film 806a as described above, the contact resistance between the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 is reduced. Therefore, the on-current of the TFT and is in contact with the oxide semiconductor film 8,05. And since a metal material having a low contact resistance with the oxide semiconductor film is used for the conductive film 806a as described above, the contact resistance between the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 is reduced. Therefore, the on-current of the TFT and the contact resistance between the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805 is reduced. Therefore, the on-current of the TFT and The field-effect mobility can be increased.

[0216] Also, in this third photolithography process, a second terminal 820 made of the same material as the source electrode 807 or the drain electrode 808 is left at the terminal portion. Note that the second terminal 820 is electrically connected to the source wiring (source wiring including the source electrode 807 or the drain electrode 808). It is connected.

[0217] In addition, when using a resist mask having regions of a plurality of (for example, two types) thicknesses formed by a multi-tone mask, the number of resist masks can be reduced, so that the process can be simplified and the cost can be reduced. Reduced.

[0218] Note that the cross-sectional view within the range of the broken line D1 - D2 in FIG. 13(B) and the cross-sectional view within the range of the broken line E1 - E2 correspond to the cross-sectional view at the broken line D1 - D2 and the cross-sectional view at the broken line E1 - E2 of the plan view shown in FIG. 16. It corresponds to the cross-sectional view.

[0219] Note that in this embodiment, an example in which the source electrode and the drain electrode are formed according to the manufacturing method shown in Embodiment 1 is shown, but they may be formed according to the manufacturing methods shown in Embodiments 2 to 4. Therefore, it may be formed according to the manufacturing methods shown in Embodiments 2 to 4. It may be formed accordingly.

[0220] As shown in FIG. 14(A), after forming the source electrode 807 and the drain electrode 808, an insulating film 80 9 is formed so as to cover the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. The insulating film 809 desirably contains as few impurities such as moisture and hydrogen as possible, and may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. It is desirable that the insulating film 809 contains as few impurities such as moisture and hydrogen as possible, and may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. It is preferably a single-layer insulating film or may be composed of a plurality of laminated insulating films. It is desirable to use a material with high barrier properties for the insulating film 809. For example, a material with high barrier properties As the high insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of stacked insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, by sandwiching the insulating film with a lower nitrogen ratio in between, an insulating film having barrier properties is formed so as to overlap with the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. By using the insulating film having barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film 805, the gate insulating film 802, or the interface between the oxide semiconductor film 805 and other insulating films and the vicinity thereof. Further, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio in contact with the oxide semiconductor film 805, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor film 805. In the present embodiment, an insulating film 809 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to 100 °C. By providing the exposed region of the oxide semiconductor film 805 provided between the source electrode 807 or the drain electrode 808 in contact with the silicon oxide constituting the insulating film 809,

[0221] As the high insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of stacked insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio than the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film 805. Then, by sandwiching the insulating film with a lower nitrogen ratio in between, an insulating film having barrier properties is formed so as to overlap with the source electrode 807, the drain electrode 808, and the oxide semiconductor film 805. By using the insulating film having barrier properties, it is possible to prevent moisture and oxygen from adsorbing on the surface and inside of the source electrode 807 and the drain electrode 808. Also, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film 805, the gate insulating film 802, or the interface between the oxide semiconductor film 805 and other insulating films and the vicinity thereof. Further, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen ratio in contact with the oxide semiconductor film 805, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor film 805. In the present embodiment, an insulating film 809 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to 100 °C.

[0222] By providing the exposed region of the oxide semiconductor film 805 provided between the source electrode 807 or the drain electrode 808 in contact with the silicon oxide constituting the insulating film 809, ​​​​​​​​​​​​Oxygen is supplied to the region of the oxide semiconductor film 805 in contact with 09, resulting in an increase in resistance (a decrease in carrier concentration, preferably less than 1×10 / cm 18 ), and an oxide semiconductor film 805 having a channel formation region with increased resistance can be formed. 3

[0223] Next, after forming the insulating film 809, a heat treatment may be performed. The heat treatment is performed in a reduced pressure atmosphere, in an air atmosphere, or in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) at a temperature preferably in the range of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower). For example, a second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. Alternatively, an RTA treatment with high temperature and short time may be performed in the same manner as the previous heat treatment. When this heat treatment is performed, the oxide semiconductor film 805 is heated in contact with the silicon oxide constituting the insulating film 809, and further increases the resistance of the oxide semiconductor film 805, improving the electrical characteristics of the transistor and reducing the variation in electrical characteristics. This heat treatment is not particularly limited as long as it is performed after the formation of the insulating film 809, and can be performed without increasing the number of steps by combining it with other processes, for example, the heat treatment during the formation of the resin film or the heat treatment for reducing the resistance of the transparent conductive film.

[0224] The thin film transistor 813 can be fabricated through the above processes.

[0225] Next, a fourth photolithography process is performed to form a resist mask, and contact holes are formed by etching the insulating film 809 and the gate insulating film 802, exposing a part of the drain electrode 80 8, a part of the first terminal 821, and a part of the second terminal 820. Next, the After removing the resist mask, a transparent conductive film is formed. As materials for the transparent conductive film, indium oxide (In2O3), indium oxide - tin oxide alloy (In2O3―SnO2, abbreviated as ITO), etc. are formed using a sputtering method, a vacuum evaporation method, or the like. The etching treatment of such materials is performed with a hydrochloric acid - based solution. However, especially for the etching of ITO, residues are likely to occur. Therefore, an indium oxide - zinc oxide alloy (In2O3―ZnO) may be used to improve the etching processability. Also, when performing a heat treatment to reduce the resistance of the transparent conductive film, it can be combined with a heat treatment that increases the resistance of the oxide semiconductor film 805 to improve the electrical characteristics of the transistor and reduce the variation in electrical characteristics. indium (In2O3), indium oxide - tin oxide alloy (In2O3―SnO2, abbreviated as ITO ), etc. are formed using a sputtering method, a vacuum evaporation method, or the like. The etching treatment of such materials is performed with a hydrochloric acid - based solution. However, especially for the etching of ITO, residues are likely to occur . Therefore, an indium oxide - zinc oxide alloy (In2 O3―ZnO) may be used to improve the etching processability. Also, when performing a heat treatment to reduce the resistance of the transparent conductive film, it can be combined with a heat treatment that increases the resistance of the oxide semiconductor film 805 to improve the electrical characteristics of the transistor and reduce the variation in electrical characteristics. O3―ZnO) may be used to improve the etching processability. Also, when performing a heat treatment to reduce the resistance of the transparent conductive film, it can be combined with a heat treatment that increases the resistance of the oxide semiconductor film 805 to improve the electrical characteristics of the transistor and reduce the variation in electrical characteristics. Next, a fifth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form a pixel electrode 814 connected to the drain electrode 808, a transparent conductive film 815 connected to the first terminal 821, and a transparent conductive film 81

[0226] 6 connected to the second terminal 820. Next, a fifth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form a pixel electrode 814 connected to the drain electrode 808, a transparent conductive film 815 connected to the first terminal 821, and a transparent conductive film 81 6 connected to the second terminal 820.

[0227] The transparent conductive film 815 and the transparent conductive film 816 serve as electrodes or wirings used for connection to the FPC. The transparent conductive film 815 formed on the first terminal 821 serves as a terminal electrode for connection that functions as an input terminal of the gate wiring. The transparent conductive film 816 formed on the second terminal 820 is a terminal electrode for connection that functions as an input terminal of the source wiring. The transparent conductive film 815 formed on the first terminal 821 serves as a terminal electrode for connection that functions as an input terminal of the gate wiring. The transparent conductive film 816 formed on the second terminal 820 is a terminal electrode for connection that functions as an input terminal of the source wiring.

[0228] In this sixth photolithography process, a holding capacitor 819 is formed by the capacitive wiring 822 and the pixel electrode 814, using the gate insulating film 802 and the insulating film 809 as dielectrics. In this sixth photolithography process, a holding capacitor 819 is formed by the capacitive wiring 822 and the pixel electrode 814, using the gate insulating film 802 and the insulating film 809 as dielectrics.

[0229] A cross-sectional view at the stage where the resist mask is removed is shown in FIG. The cross-sectional view within the range of the dashed line D1-D2 and the cross-sectional view within the range of the dashed line E1-E2 are shown in FIG. It corresponds to the cross-sectional view taken along dashed lines D1-D2 and E1-E2 in the plan view. .

[0230] In this way, six photolithography processes were performed using six photomasks to create the bottom A pixel having a thin film transistor 813, which is a gate-type thin film transistor with an inverse staggered structure. The thin film transistor portion and the storage capacitor 819 can be completed. By configuring the pixel section in a matrix corresponding to the pixels, an active matrix It can be used as one of the substrates for manufacturing a glass-type display device. Such a substrate is called an active matrix substrate.

[0231] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The opposing substrate is fixed.

[0232] In addition, the capacitance wiring is not provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel and the insulating film and gate insulating film. A storage capacitor may be formed by stacking the layers with a film interposed therebetween.

[0233] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is recognized by the observer as such.

[0234] When manufacturing a light-emitting display device, a partition using an organic resin film may be provided between each organic light-emitting element. In that case, since the organic resin film is heat-treated, the oxide semiconductor film 805 can be made highly resistive and can serve as a heat treatment for improving the electrical characteristics of the transistor and reducing variations in the electrical characteristics. By forming with a thin-film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, in order to increase the purity of the oxide semiconductor film by reducing impurities such as moisture, hydrogen, and OH by heat treatment, a special sputtering apparatus with a lowered dew point in the film formation chamber or an ultra-high-purity oxide semiconductor target is used. Even without using them, a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability can be manufactured. can also serve as

[0235] Since the semiconductor film in the channel formation region is a high-resistance region, the electrical characteristics of the thin-film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability. This embodiment can be implemented in combination with the above-described embodiment. This embodiment can be implemented in combination with the above embodiment. Even without using a special sputtering apparatus with a lowered dew point in the film formation chamber or an ultra-high-purity oxide semiconductor target, a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability can be manufactured. Since the semiconductor film in the channel formation region is a high-resistance region, the electrical characteristics of the thin-film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability.

[0236] Since the semiconductor film in the channel formation region is a high-resistance region, the electrical characteristics of the thin-film transistor are stabilized, and an increase in the off-current can be prevented. Thus, it is possible to obtain a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability. The electrical characteristics of the thin-film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability. Since the semiconductor film in the channel formation region is a high-resistance region, the electrical characteristics of the thin-film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, it is possible to obtain a semiconductor display device having a thin-film transistor with good electrical characteristics and high reliability.

[0237] This embodiment can be implemented in combination with the above embodiment.

[0238] (Embodiment 8) In this embodiment, the configuration of a semiconductor display device, which is one of the semiconductor display devices formed using the manufacturing method of the present invention and is called an electronic paper or a digital paper, will be described. The configuration of a semiconductor display device called an electronic paper or a digital paper will be described. .

[0239] An electronic paper uses a display element that can control gradation by applying a voltage and has a memory property. Specifically, as the display element used for the electronic paper, a non-aqueous electrophoresis type display element, a PDLC (polymer dispersed liquid crystal) type display element in which droplets of liquid crystal are dispersed in a polymer material between two electrodes, a display element having a chiral nematic liquid crystal or a cholesteric liquid crystal between two electrodes, a display element having charged fine particles between two electrodes and moving the fine particles in a powder by an electric field, such as a powder movement type display element, can be used. Further, as the non-aqueous electrophoresis type display element, a display element sandwiching a dispersion liquid in which charged fine particles are dispersed between two electrodes, a display element having a dispersion liquid in which charged fine particles are dispersed on two electrodes sandwiching an insulating film, a display element in which a twisting ball having two hemispheres charged with different charges is dispersed in a solvent between two electrodes, a display element having a microcapsule in which a plurality of charged fine particles are dispersed between two electrodes, etc. are included.

[0240] FIG. 18(A) shows a top view of a pixel portion 700, a signal line driving circuit 701, and a scanning line driving circuit 702 of the electronic paper.

[0241] The pixel portion 700 has a plurality of pixels 703. Further, a plurality of signal lines 707 are routed into the pixel portion 700 from the signal line driving circuit 701. A plurality of scanning lines 708 are routed into the pixel portion 700 from the scanning line driving circuit 702.

[0242] Each pixel 703 has a transistor 704, a display element 705, and a holding capacitor 706. This is the case. The gate electrode of the transistor 704 is connected to one of the scanning lines 708. Also, one of the source electrode and the drain electrode of the transistor 704 is connected to one of the signal lines 707, and the other is connected to the pixel electrode of the display element 705.

[0243] In FIG. 18(A), in order to maintain the voltage applied between the pixel electrode and the counter electrode of the display element 705, a holding capacitor 706 is connected in parallel with the display element 705. However, if the memory property of the display element 705 is high enough to maintain the display, it is not necessarily necessary to provide the holding capacitor 706.

[0244] In FIG. 18(A), the configuration of the pixel portion of the active matrix type in which one transistor functioning as a switching element is provided for each pixel has been described. However, the electronic paper according to one aspect of the present invention is not limited to this configuration. The number of transistors provided in the pixel may be plural, and elements such as a capacitor, a resistor, and a coil may be connected in addition to the transistor.

[0245] In FIG. 18(B), an electrophoretic type electronic paper having microcapsules is taken as an example, and a cross-sectional view of the display element 705 provided in each pixel 703 is shown.

[0246] The display element 705 includes a pixel electrode 710, a counter electrode 711, and microcapsules 712 to which a voltage is applied by the pixel electrode 710 and the counter electrode 711. One of the source electrode or the drain electrode 713 of the transistor 704 is connected to the pixel electrode 710.

[0247] Inside the microcapsules 712, there are white pigments charged positively such as titanium oxide and carbon A negatively charged black pigment such as carbon black is encapsulated together with a dispersion medium such as oil. According to the voltage of the video signal applied to the pixel electrode 710, a voltage is applied between the pixel electrode and the counter electrode to attract the black pigment to the positive electrode side and the white pigment to the negative electrode side, thereby enabling grayscale display.

[0248] Also, in FIG. 18(B), the microcapsules 712 are fixed by a resin 714 having translucency between the pixel electrode 710 and the counter electrode 711. However, the present invention is not limited to this configuration, and the space formed by the microcapsules 712, the pixel electrode 710, and the counter electrode 711 may be filled with a gas such as air or an inert gas. However, in this case, it is desirable to fix the microcapsules 712 to both or either one of the pixel electrode 710 and the counter electrode 711 with an adhesive or the like. Moreover, the number of microcapsules 712 included in the display element 705 is not necessarily plural as shown in FIG. 18(B). One display element 705 may have a plurality of microcapsules 712, or a plurality of display elements 705 may have one microcapsule 712. For example, if two display elements 705 share one microcapsule 712, and a positive voltage is applied to the pixel electrode 710 of one display element 705 and a negative voltage is applied to the pixel electrode 710 of the other display element 705. In this case, in the region overlapping with the pixel electrode 710 to which the positive voltage is applied, the black pigment in the microcapsule 712 is attracted to the pixel electrode 710 side, and the white pigment is attracted to the counter electrode 711 side.

[0249] ​​​​​​​​​​Conversely, in the region overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcap In the cell 712, the white pigment is attracted to the pixel electrode 710 side, and the black pigment is attracted to the counter electrode 71 1 side.

[0250] Next, regarding the specific driving method of the electronic paper, the electrophoretic type electronic paper described above will be described by way of example.

[0251] The operation of the electronic paper can be described separately for the initialization period, the writing period, and the holding period. It can be done.

[0252] Before switching the image to be displayed, first, in the initialization period, the gradation of each pixel in the pixel portion is once unified to initialize the display element. By initializing the display element, it is possible to prevent the remaining image from remaining. Specifically, in the electrophoretic type, the gradation displayed by the microcapsules 712 included in the display element 705 is adjusted so that the display of each pixel becomes white or black.

[0253] In this embodiment, after inputting an initialization video signal for displaying black to the pixel, the operation of initialization when inputting an initialization video signal for displaying white to the pixel will be described. For example, in the case of an electrophoretic type electronic paper in which the image is displayed toward the counter electrode 711 side, first, a voltage is applied to the display element 705 so that the black pigment in the microcapsule 712 faces the counter electrode 711 side and the white pigment faces the pixel electrode 710 side. Next, a voltage is applied to the display element 705 so that the white pigment in the microcapsule 712 faces the counter electrode 711 side and the black pigment faces the pixel electrode 710 side.

[0254] Also, if the input of the initialization video signal to the pixel is only once, depending on the gradation displayed before the initialization period, the movement of the white pigment and the black pigment in the microcapsule 712 may be incomplete and end halfway, and there may be a difference in the gradation displayed between pixels even after the initialization period ends. Therefore, it is desirable to display black by applying a negative voltage - Vp to the pixel electrode 710 multiple times, and display white by applying a positive voltage Vp to the pixel electrode 710 multiple times with respect to the common voltage Vcom.

[0255] Note that if the gradation displayed by the display element of each pixel before the initialization period is different, the minimum number of times required to input the initialization video signal will also be different. Therefore, it is also possible to change the number of times the initialization video signal is input between pixels according to the gradation displayed before the initialization period. In this case, it is advisable to input the common voltage Vcom to the pixels that no longer require the input of the initialization video signal.

[0256] Note that in order to apply the voltage Vp or the voltage -Vp of the initialization video signal to the pixel electrode 710 multiple times, a series of operations of inputting the initialization video signal to the pixels of the line having the scanning line during the period when the pulse of the selection signal is applied to each scanning line are performed multiple times. By applying the voltage Vp or the voltage -Vp of the initialization video signal to the pixel electrode 710 multiple times, the movement of the white pigment and the black pigment in the microcapsule 712 can be converged to prevent a difference in gradation between pixels, and the pixels in the pixel portion can be initialized.

[0257] ​​​​​​​​​​​​During the initialization period, each pixel does not display black and then white. Alternatively, in the initialization period, the pixels may be configured to display black after the initial state. It is also possible to display white, then black, and then white again.

[0258] The timing at which the initialization period starts is the same for all pixels in the pixel section. For example, it is not necessary to do it for each pixel, or for each pixel that belongs to the same line. The timing at which the initialization period starts may be varied.

[0259] Next, in the writing period, a video signal having image information is input to the pixels.

[0260] When an image is displayed on the entire pixel area, power is applied to all the scanning lines in sequence during one frame period. A selection signal with a shifted voltage pulse is input. Then, a pulse appears in the selection signal. During one line period, video signals containing image information are input to all signal lines. do.

[0261] The white light in the microcapsules 712 changes in response to the voltage of the video signal applied to the pixel electrode 710. The color pigment and the black pigment move to the pixel electrode 710 side or the counter electrode 711 side, thereby forming a display element. The child 705 displays the gray scale.

[0262] In the writing period, as in the initialization period, the voltage of the video signal is applied to the pixel electrode 710 multiple times. Therefore, during the period when the pulse of the selection signal is applied to each scanning line, In this case, a series of operations of inputting a video signal to pixels of a line having the scanning line is performed as follows: Do this multiple times.

[0263] Next, during the holding period, after applying a common voltage Vcom to all pixels via signal lines, no selection signal is input to the scanning lines or video signal is input to the signal lines. Therefore, the white pigment and black pigment in the microcapsules 712 of the display element 705 are held in their arrangement unless a positive or negative voltage is applied between the pixel electrode 710 and the counter electrode 711. Thus, the gradation displayed by the display element 705 is maintained. Therefore, the image written in the writing period is also maintained during the holding period. Note that for the display element used in the electronic paper, the voltage required to change the gradation is

[0264] higher than that of light-emitting elements such as liquid crystal elements used in liquid crystal display devices and organic light-emitting elements used in light-emitting devices. Therefore, the transistor 704 of the pixel used as a switching element has a large potential difference between its source electrode and drain electrode during the writing period, so the off-current becomes high, and as a result, the potential of the pixel electrode 710 fluctuates and display disturbance is likely to occur. To prevent the potential of the pixel electrode 710 from fluctuating due to the off-current of the transistor 704, it is effective to increase the capacitance of the holding capacitor 706. Also, not only the voltage between the pixel electrode 710 and the counter electrode 711 but also the voltage generated between the signal line 707 and the counter electrode 711 is applied to the microcapsule 712, which may cause noise in the display of the display element 705. To prevent the occurrence of this noise, it is effective to ensure a wide area of the pixel electrode 710 and prevent the voltage generated between the signal line 707 and the counter electrode 711 from being applied to the microcapsule 712. However, as described above, the potential of the pixel electrode 710 changes Increasing the capacitance of the holding capacitor 706 to prevent movement, or noise occurring in the display If the area of the pixel electrode 710 is increased to prevent , the writing current value to be supplied to the pixel during the writing period will increase, and it will take time to input the video signal. In one aspect of the present invention In the electronic paper according to this aspect, since the transistor 704 used for the pixel as the switching element has a high field-effect mobility, a high on-current can be obtained. Therefore Even if the capacitance of the holding capacitor 706 is increased or the area of the pixel electrode 710 is increased The video signal can be quickly input to the pixel. Therefore, the length of the writing period can be suppressed, and the switching to the displayed image can be smoothly performed. Also, the transistor 704 of the pixel used as the switching element has a large potential difference between its source electrode and drain electrode during the writing period, so it is likely to deteriorate. However, in one aspect of the present invention The variation in the threshold voltage due to the deterioration of the transistor 704 over time can be greatly suppressed So, the reliability of the electronic paper can be improved This embodiment can be implemented in combination with the above embodiment (Embodiment 9) An example of the block diagram of the active matrix type semiconductor display device is shown in Fig. 19(A). On the substrate 5300 of the display device There are a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304. A plurality of signal lines extend from the signal line driving circuit 5304 and are arranged in the pixel portion A plurality of scanning lines extend from the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 and are arranged

[0265]

[0266] (Embodiment 9) An example of the block diagram of the active matrix type semiconductor display device is shown in Fig. 19(A). On the substrate 5300 of the display device There are a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304. A plurality of signal lines extend from the signal line driving circuit 5304 and are arranged in the pixel portion A plurality of scanning lines extend from the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 and are arranged Note that In the intersection region of the scanning lines and the signal lines, pixels each having a display element are arranged in a matrix. Further, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0267] In FIG. 19(A), the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on a single substrate 5300 together with the pixel portion 5301. Therefore, the number of components such as driving circuits provided externally is reduced, so that not only the display device can be miniaturized, but also the cost can be reduced by reducing the assembly process and the inspection process. Also, when a driving circuit is provided outside the substrate 5300, the number of connections at the connection portion can be reduced by extending the wiring. Thus, it is possible to prevent a reduction in yield due to a connection failure between the driving circuit and the pixel portion, and to prevent a reduction in reliability due to low mechanical strength at the connection portion.

[0268] Note that the timing control circuit 5305 supplies, for example, a first scanning line driving circuit start signal (GSP1) and a scanning line driving circuit clock signal (GCK1) to the first scanning line driving circuit 5302. Also, the timing control circuit 5305 supplies, for example, a second scanning line driving circuit start signal (GSP2) (also referred to as a start pulse) and a scanning line driving circuit clock signal (GCK2) to the second scanning line driving circuit 5303. To the signal line driving circuit 5304, a signal line driving circuit start signal (SSP), a signal line driving circuit clock signal (SCK), video signal data (simply referred to as a video signal), and a latch signal (LAT) are supplied. It is assumed that a latch signal (LAT) is supplied. Note that either one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 can be omitted.

[0269] In FIG. 19(B), a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303) is formed on one substrate 5300 together with the pixel section 5301, and a configuration is shown in which the signal line driving circuit 5304 is formed on a substrate different from the pixel section 5301. Further, among the signal line driving circuit 5304, a circuit with a low driving frequency such as an analog switch used in the sampling circuit is partially formed on one substrate 5300 together with the pixel section 5301. In this way, by partially adopting the system-on-panel, it is possible to avoid the reduction in yield due to the above-described connection failure, the low mechanical strength at the connection point, etc., and to reduce costs by reducing the assembly process and the inspection process, and to enjoy some of the advantages of the system-on-panel. Furthermore, compared with a system-on-panel in which all of the pixel section 5301, the scanning line driving circuit 5302, the scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on one substrate, it is possible to further improve the performance of a circuit with a high driving frequency, and it is possible to form a pixel section with a large area, which is difficult to achieve when using a single crystal semiconductor.

[0270] Next, the configuration of a signal line driving circuit using an n-channel type transistor will be described.

[0271] The signal line driving circuit shown in FIG. 20(A) includes a shift register 5601 and a sampling circuit 5602. The sampling circuit 5602 includes a plurality of switching circuits 5602_1 ​​​​​​It has ~5602_N (N is a natural number). Switching circuits 5602_1 to 5602_N each have a plurality of n-channel transistors 5603_1 to 5603_k (k is a natural number) having.

[0272] Regarding the connection relationship of the signal line driving circuit, switching circuit 5602_1 will be taken as an example for explanation Among the source electrode and the drain electrode of the transistor, either one is the first terminal, and the other is the second terminal, and the following description will be given

[0273] The first terminals of transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 56 04_k. Video signals are input to wirings 5604_1 to 5604_k respectively . The second terminals of transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gate electrodes of transistors 5603_1 to 5603_k are connected to the shift register 5601 .

[0274] The shift register 5601 outputs a timing signal having a high-level voltage (H level) in the order of wirings 5605_1 to 5605_N, and has a function of sequentially selecting switching circuits 5602_1 to 560 2_N .

[0275] Switching circuit 5602_1 controls the conduction state (conduction between the first terminal and the second terminal) between wirings 5604_1 to 5604_k and signal lines S1 to Sk by switching transistors 5603_1 to 5603_k, that is, it has a function of controlling whether to supply the potential of wirings 5604_1 to 5604_k to signal lines S1 to Sk . . .

[0276] Next, the operation of the signal line driving circuit in Fig. 20(A) will be described with reference to the timing chart in Fig. 20(B). In Fig. 20(B), the timing signals Sout_1 to Sout_N respectively input to wirings 5605_1 to 5605_N from the shift register 5601, and the timing chart of the video signals Vdata_1 to Vdata_k respectively input to wirings 5604_1 to 5604_k are shown as an example.

[0277] Note that one operation period of the signal line driving circuit corresponds to one line period in the display device. In Fig. 20(B), the case where one line period is divided into periods T1 to TN is illustrated. Periods T1 to TN are respectively periods for writing a video signal to one pixel belonging to the selected row. That is.

[0278] During periods T1 to TN, the shift register 5601 sequentially outputs a high-level timing signal to wirings 5605_1 to 5605_N. For example, during period T1, the shift register 5601 outputs a high-level signal to wiring 5605_1. Then, the transistors 5603_1 to 5603_k of the switching circuit 5602_1 turn on, and wirings 5604_1 to 5604_k and signal lines S1 to Sk become conductive. At this time, Data(S1) to Data(Sk) are input to wirings 5604_1 to 5604_k. Data(S1) to Data(Sk) are respectively written to the pixels of the 1st to kth columns among the pixels belonging to the selected row through the transistors 5603_1 to 5603_k. In this way, during periods T1 to TN, the video signal is written to the pixels belonging to the selected row, k columns at a time in sequence.

[0279] ​​​​​ As described above, by writing the video signal into pixels in multiple columns at a time, the number of video signals or the number of wirings can be reduced. Therefore, the number of connections with an external circuit such as a controller can be reduced. Also, by writing the video signal into pixels in multiple columns at a time, the writing time can be lengthened, preventing insufficient writing of the video signal.

[0280] Next, one form of the shift register used in the signal line drive circuit or the scanning line drive circuit will be described with reference to FIGS. 21 and 22.

[0281] The shift register has a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more) (see FIG. 21(A)). The first pulse output circuit 10_ 1 to the N-th pulse output circuit 10_N are supplied with a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. Also, in the n-th pulse output circuit 10_n (n is a natural number of 2 or more and N or less) from the second stage onward, a signal (referred to as a previous stage signal OUT(n - 1)) from the pulse output circuit 10_n - 1 in the previous stage is input. Also, in the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 in the two-stage subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, a signal (referred to as a subsequent stage signal OUT(n + 2)) from the (n + 2)-th pulse output circuit 10_(n 1, the second wiring 12 supplies the second clock signal CK2, the third wiring 13 supplies the third clock signal CK3, and the fourth wiring 14 supplies the fourth clock signal CK4. Also, in the first pulse output circuit 10_1, the start pulse SP1 (the first start pulse) from the fifth wiring 15 is input. Also, in the n-th pulse output circuit 10_n (n is a natural number greater than or equal to 2 and less than or equal to N) from the second stage onward, the signal from the pulse output circuit 10_n - 1 in the previous stage (the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 in the two-stage subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, the signal from the (n + 2)-th pulse output circuit 10_(n + 2) (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, for each stage of the pulse output circuit 10_1, the start pulse SP1 (the first start pulse) from the fifth wiring 15 is input. Also, in the n-th pulse output circuit 10_n (n is a natural number greater than or equal to 2 and less than or equal to N) from the second stage onward, the signal from the pulse output circuit 10_n - 1 in the previous stage (the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 in the two-stage subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, the signal from the (n + 2)-th pulse output circuit 10_(n + 2) (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, for each stage of the pulse output circuit 10_n (n is a natural number greater than or equal to 2 and less than or equal to N) from the second stage onward, the signal from the pulse output circuit 10_n - 1 in the previous stage (the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 in the two-stage subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, the signal from the (n + 2)-th pulse output circuit 10_(n + 2) (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, for each stage of the pulse output circuit 10_n (n is a natural number greater than or equal to 2 and less than or equal to N) from the second stage onward, the signal from the pulse output circuit 10_n - 1 in the previous stage (the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 in the two-stage subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, the signal from the (n + 2)-th pulse output circuit 10_(n + 2) (referred to as the subsequent stage signal OUT(n + 2)) is input. Therefore, for each stage of the pulse output circuit 10_n (n is a natural number greater than or equal to 2 and less than or equal to N) from the second stage onward, the signal from the pulse output circuit 10_n - 1 in the previous stage (the previous stage signal OUT(n - 1)) is input. Also, in the first pulse output circuit 10_1, the signal from the third pulse output circuit 10_3 in the two-stage subsequent stage is input. Similarly, in the n-th pulse output circuit 10_n from the second stage onward, the signal from the (n + 2)-th pulse output circuit 10_(n​​ From the LSI output circuit, first output signals OUT(1)(SR) to OUT(N)(SR) for input to the subsequent-stage and two-previous-stage pulse output circuits, and second output signals (OUT(1) to OUT(N)) for input to other circuits and the like are output. As shown in Fig. 21(A), since the subsequent-stage signal OUT(n + 2) is not input to the two final stages of the shift register, as an example, a configuration may be adopted in which a second start pulse SP2 and a third start pulse SP3 are separately input.

[0282] The clock signal (CK) is a signal that repeats between H level and L level (low voltage level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal may also be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK.

[0283] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in Fig. 21(A), for the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, for the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14, which is electrically connected to the wire 13. There is.

[0284] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 21(B)). In the first pulse output circuit 10_1, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the input terminal 23, a start pulse is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, and a first output signal OUT(1)(SR) is output from the first output terminal 26, and a second output signal OUT(1) is output from the second output terminal 27. Next, an example of the specific circuit configuration of the pulse output circuit is shown in FIG. 22(A). Each pulse output circuit has first to thirteenth transistors 31 to 43 (see FIG. 22(A)). In addition to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 described above, a first high power supply potential VDD is supplied

[0285] to the power supply line 51, a second high power supply potential VCC is supplied to the power supply line 52, and a low power supply potential VSS is supplied

[0286] to the power supply line 53. Signals or power supply potentials are supplied from the power supply lines 51, 52, and 53 to the first to thirteenth transistors 31 to 43. Here, the relationship between the heights of the power supply potentials of the respective power supply lines in FIG. 22(A) is ​​​​The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is set to a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, but it is assumed that they are at VDD when at the H level and at VSS when at the L level. By setting the potential V DD of the power supply line 51 higher than the potential VCC of the power supply line 52, without affecting the operation it is possible to keep the potential applied to the gate electrode of the transistor low, reduce the shift of the threshold voltage of the transistor, and suppress degradation.

[0287] In FIG. 22(A), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. For the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. For the fourth transistor 34, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. For the fifth transistor 35, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34, and the gate electrode is electrically connected to the fourth input terminal 24. The sixth The transistor 36 has its first terminal electrically connected to the power line 52 and its second terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34, and its gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power line 52, its second terminal electrically connected to the second terminal of the eighth transistor 38, and its gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34, and its gate electrode is electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, its second terminal electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40, and its gate electrode is electrically connected to the power line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and its gate electrode is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode is electrically connected to the gate electrode of the seventh transistor 37. The thirteenth transistor 43 has its first terminal electrically connected to the power line 53 and its second terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 and its gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power line 52 its second terminal electrically connected to the second terminal of the eighth transistor 38 and its gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34 and its gate electrode is electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32 its second terminal electrically connected to the gate electrodes of the third transistor 33 and the tenth transistor 40 and its gate electrode is electrically connected to the power line 52. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21 its second terminal electrically connected to the second output terminal 27 and its gate electrode is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53 its second terminal electrically connected to the second output terminal 27 and its gate electrode is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53 its second terminal electrically connected to the second output terminal 27 and its gate electrode is electrically connected to the gate electrode of the seventh transistor 37. The thirteenth transistor 43 has its first terminal electrically connected to the power line 53 and its second terminal electrically connected to the second output terminal 27 and its gate electrode is electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53 its second terminal electrically connected to the second output terminal 27 and its gate electrode is electrically connected to the gate electrode of the seventh transistor 37. The thirteenth transistor 43 has its first terminal electrically connected to the power line 53 and its second terminal electrically connected to the second output terminal 27 is electrically connected, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37.

[0288] In FIG. 22(A), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 0, and the second terminal of the ninth transistor 39 is defined as node A. Also, the connection point of the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the connection point of the eleventh transistor 41 is defined as node B (see FIG. 2 2(A)).

[0289] Regarding the timing chart of the shift register including a plurality of pulse output circuits shown in FIG. 22(A), it is shown in FIG. 22(B).

[0290] As shown in FIG. 22(A), by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, there are the following advantages before and after the bootstrap operation. as follows.

[0291] When there is no ninth transistor 39 to which the second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source electrode, which is the second terminal of the first transistor 31, rises and becomes higher than the first power supply potential VDD. Then, the source electrode of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate electrode and the source electrode, between the gate electrode and the source electrode ​​​A large stress is applied between the gate electrode and the drain electrode, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VC C is applied, the potential of node A rises due to the bootstrap operation , but the potential of the second terminal of the first transistor 31 can be prevented from rising. That is, by providing the ninth transistor 39 , the value of the negative bias voltage applied between the gate electrode and the source electrode of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of the present embodiment , the negative bias voltage applied between the gate electrode and the source electrode of the first transistor 31 can also be reduced, so that deterioration of the first transistor 31 due to stress can be suppressed . Regarding the location where the ninth transistor 39 is provided, it may be configured to be connected between the second terminal of the first transistor 31 and the gate electrode of the third transistor 33 via the first terminal and the second terminal. In the case of a shift register having a plurality of pulse output circuits in the present embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, which has the advantage of reducing the number of transistors .

[0292] By using an oxide semiconductor as the active layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the transistor can be reduced, and the on-current and the field-effect mobility can be increased, and furthermore, the degree of deterioration can be reduced. Therefore, within the circuit

[0293] ​​​​​​Malfunctions can be reduced. In addition, a transistor using an oxide semiconductor has less degradation of the transistor due to the application of a high potential to the gate electrode compared to a transistor using amorphous silicon. Therefore, even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, a similar operation can be obtained, and since the number of power supply lines routed between circuits can be reduced, the circuit can be miniaturized. Note that the clock signal supplied to the gate electrode of the seventh transistor 37 by the third input terminal 23 and the clock signal supplied to the gate electrode of the eighth transistor 38 by the second input terminal 22 can be interchanged in their connection relationship so that they are the clock signal supplied to the gate electrode of the seventh transistor by the second input terminal 22 and the clock signal supplied to the eighth gate electrode by the third input terminal 23, and the same effect can be obtained. At this time, in the shift register shown in Fig. 22

[0294] (A), when both the seventh transistor 37 and the eighth transistor 38 are turned on and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned on, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential of the second input terminal 22 and the third input terminal 23 decreases, and as a result, the potential of node B decreases twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, as in the period of Fig. 22(B) for the shift register shown in Fig. 22(A), when both the seventh transistor 37 and the eighth transistor 38 are turned on and then the seventh transistor 37 and the eighth transistor 38 are both turned on and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned on, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential of the second input terminal 22 and the third input terminal 23 decreases, and as a result, the potential of node B decreases twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, as in the period of Fig. 22(B) for the shift register shown in Fig. 22(A), when both the seventh transistor 37 and the eighth transistor 38 are turned on and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned on, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential of node B decreases twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, for the shift register shown in Fig. 22(A), as in the period of Fig. 22(B), when both the seventh transistor 37 and the eighth transistor 38 are turned on and then the seventh transistor When the seventh transistor 37 is on and the eighth transistor 38 is off, and then the seventh transistor 37 is turned off and the eighth transistor 38 is off, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 can be reduced at once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, a clock signal is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrode ( the lower gate electrode and the upper gate electrode) of the eighth transistor 38. It is preferable to have such a connection relationship. This is because the number of fluctuations in the potential of node B is reduced, and noise can also be reduced. In this way, by configuring such that a signal of H level is periodically supplied to node B during the period when the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, malfunctions of the pulse output circuit can be suppressed.

[0295] This embodiment can be implemented in combination with the above embodiment.

[0296] This embodiment can be implemented in combination with the above embodiment.

[0297] (Embodiment 10) The liquid crystal display device according to one aspect of the present invention uses a thin film transistor with high mobility and on-current, and high reliability, so it has high contrast and visibility. In this embodiment, the configuration of the liquid crystal display device according to one aspect of the present invention will be described.

[0298] FIG. 23 shows, as an example, a cross-sectional view of a pixel of the liquid crystal display device according to one aspect of the present invention. FIG. 2 ​​​​​The thin film transistor 1401 shown in Fig. 3 includes a gate electrode 1402 formed on an insulating surface, a gate insulating film 1403 on the gate electrode, and an oxide semiconductor film 1404 overlapping with the gate electrode 1 402 on the gate insulating film 1403. A pair of conductive films 140 6a and 1406b are formed so as to be laminated in order on the oxide semiconductor film 1404 and function as a source electrode or a drain electrode. Further, the thin film transistor 1401 may include an insulating film 1407 formed on the oxide semiconductor film 1404 among its components. The insulating film 1407 is formed so as to cover the gate electrode 1402, the gate insulating film 1403, the oxide semiconductor film 1404 , and the conductive films 1406a and 1406b. Note that in this embodiment, source and drain electrodes formed according to the manufacturing method shown in Embodiment 1 are taken as an example, but source and drain electrodes formed according to the manufacturing methods shown in Embodiments 2 to 4 may be used. An insulating film 1408 is formed on the insulating film 1407. Openings are provided in a part of the insulating film 1407 and the insulating film 140

[0299] 8, and a pixel electrode 1410 is formed so as to be in contact with one of the conductive films 1406b at the opening. Also, a spacer 141 7 for controlling the cell gap of the liquid crystal element is formed on the insulating film 1408. The spacer 1417 can be formed by etching the insulating film into a desired shape, but the cell gap may be controlled by dispersing a filler on the insulating film 1408.

[0300]

[0301]

[0302] ​​​​​​​And an alignment film 1411 is formed on the pixel electrode 1410. Also, at a position facing the pixel electrode 14 10, a counter electrode 1413 is provided, and an alignment film 1414 is formed on the side of the counter electrode 1413 closer to the pixel electrode 1410. The alignment films 1411 and 1414 can be formed using organic resins such as polyimide and polyvinyl alcohol, and on their surfaces, alignment treatment for aligning liquid crystal molecules in a certain direction, such as rubbing, is performed. Rubbing can be carried out by rotating a roller wrapped with a cloth such as nylon while applying pressure to the alignment film to rub the surface of the alignment film in a certain direction. In addition, it is also possible to directly form the alignment films 1411 and 1414 having alignment characteristics by vapor deposition using an inorganic material such as silicon oxide without performing alignment treatment.

[0303] And liquid crystal 1415 is provided in a region surrounded by a sealing material 1416 between the pixel electrode 1410 and the counter electrode 1413. The liquid crystal 1415 can be injected using a dispenser type (droplet type) or a dip type (suction type). Note that a filler may be mixed into the sealing material 1416.

[0304] Also, the liquid crystal element formed by the pixel electrode 1410, the counter electrode 1413, and the liquid crystal 1415 may overlap with a color filter that can transmit light in a specific wavelength region. The color filter may be formed on a substrate (counter substrate) 1420 on which the counter electrode 1413 is formed. The color filter can be selectively formed using photolithography after applying an organic resin such as an acrylic resin in which a pigment is dispersed on the substrate 1420. Also After applying a polyimide resin in which a pigment is dispersed onto the substrate 1420, it can also be selectively formed by etching. Alternatively, by using a droplet ejection method such as inkjet, a color filter can also be selectively formed. It can also be selectively formed by etching. Alternatively, by using a droplet ejection method such as inkjet, a color filter can also be selectively formed. It can also be selectively formed by etching. Alternatively, by using a droplet ejection method such as inkjet, a color filter can also be selectively formed.

[0305] In addition, in order to prevent disclination caused by the disorder of the alignment of the liquid crystal 1415 between pixels from being visually recognized, a shielding film that can shield light may be formed between the pixels. In addition, in order to prevent disclination caused by the disorder of the alignment of the liquid crystal 1415 between pixels from being visually recognized, a shielding film that can shield light may be formed between the pixels. An organic resin containing a black pigment such as carbon black or low-order titanium oxide can be used for the shielding film. An organic resin containing a black pigment such as carbon black or low-order titanium oxide can be used for the shielding film. Alternatively, a film using chromium can also be used to form the shielding film.

[0306] The pixel electrode 1410 and the counter electrode 1413 can be made of a transparent conductive material such as indium tin oxide (ITSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or zinc oxide added with gallium (GZO). In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. The pixel electrode 1410 and the counter electrode 1413 can be made of a transparent conductive material such as indium tin oxide (ITSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or zinc oxide added with gallium (GZO). In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. The pixel electrode 1410 and the counter electrode 1413 can be made of a transparent conductive material such as indium tin oxide (ITSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or zinc oxide added with gallium (GZO). In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type. In this embodiment, a conductive film that transmits light is used for the pixel electrode 1410 and the counter electrode 1413, and an example of manufacturing a transmissive liquid crystal element is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a transflective type or a reflective type.

[0307] In this embodiment, a TN (Twisted Nematic) type is shown as the liquid crystal display device, but the thin film transistor of the present invention can also be used for other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In this embodiment, a TN (Twisted Nematic) type is shown as the liquid crystal display device, but the thin film transistor of the present invention can also be used for other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In this embodiment, a TN (Twisted Nematic) type is shown as the liquid crystal display device, but the thin film transistor of the present invention can also be used for other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In this embodiment, a TN (Twisted Nematic) type is shown as the liquid crystal display device, but the thin film transistor of the present invention can also be used for other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type. In this embodiment, a TN (Twisted Nematic) type is shown as the liquid crystal display device, but the thin film transistor of the present invention can also be used for other liquid crystal display devices such as a VA (Vertical Alignment) type, an OCB (optically compensated Birefringence) type, and an IPS (In-Plane Switching) type.

[0308] Further, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for Liquid Crystal 1415 in order to improve the temperature range. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency. and is used for Liquid Crystal 1415. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μsec or more and 100 μsec or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency. . or more and 100 μsec. or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency. The viewing angle dependency is small.

[0309] FIG. 24 is an example of a perspective view showing the structure of the liquid crystal display device of the present invention. The liquid crystal display device shown in FIG. 24 includes a liquid crystal panel 1601 in which liquid crystal elements are formed between a pair of substrates, a first diffusion plate 1 602, a prism sheet 1603, a second diffusion plate 1604, a light guide plate 1605, a reflector 1606, a light source 1607, and a circuit board 1608. The liquid crystal panel 1601, the first diffusion plate 1602, the prism sheet 1603, the second diffusion plate 1604, the light guide plate 1605, and the reflector 1606 are laminated in this order. The light source 1

[0310] 607 is provided at an end of the light guide plate 1605, and the light from the light source 1607 diffused inside the light guide plate 1605 is uniformly irradiated onto the liquid crystal panel 1601 by the first diffusion plate 1602, the prism sheet 1603, and the second diffusion plate 1604. 607 is provided at an end of the light guide plate 1605, and the light from the light source 1607 diffused inside the light guide plate 1605 is uniformly irradiated onto the liquid crystal panel 1601 by the first diffusion plate 1602, the prism sheet 1603, and the second diffusion plate 1604. 1604.

[0311] In this embodiment, the first diffusion plate 1602 and the second diffusion plate 1604 are used However, the number of diffusion plates is not limited to this, and it may be singular or three or more. And the diffusion The scattering plate may be provided between the light guide plate 1605 and the liquid crystal panel 1601. Even if the diffusion plate is provided only on the side closer to the liquid crystal panel 1601 than the reflective sheet 1603, The diffusing plate is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603. It's okay to have it.

[0312] The cross section of the prism sheet 1603 is not limited to the sawtooth shape shown in FIG. It is sufficient if the shape can condense the light from the plate 1605 onto the liquid crystal panel 1601 side.

[0313] The circuit board 1608 includes a circuit for generating various signals to be input to the liquid crystal panel 1601, In FIG. 24, the circuit board 16 is provided with circuits for processing these signals. 08 and the LCD panel 1601 are connected by FPC (Flexible Printed Circuit) The above circuit is connected via a COG (Chip On Ground) 1609. The liquid crystal panel 1601 may be connected using the glass method, or one of the above circuits may be connected using the glass method. Even if the part is connected to FPC1609 using the COF (Chip On Film) method, good.

[0314] In FIG. 24, a control circuit for controlling the driving of a light source 1607 is provided on a circuit board 1608. The control circuit and the light source 1607 are connected via an FPC 1610. However, the control circuit may be formed on the liquid crystal panel 1601. In this case, the liquid crystal panel 1601 and the light source 1607 are connected by an FPC or the like. do.

[0315] 24 shows an edge-light type light source in which a light source 1607 is arranged at the edge of a liquid crystal panel 1601. Although a light source is illustrated, the liquid crystal display device of the present invention may be a direct - type in which the light source 1607 is disposed directly below the liquid crystal panel 1601. It may be a direct - type arrangement where it is disposed directly below.

[0316] This embodiment can be implemented in appropriate combination with the above - described embodiment.

[0317] (Embodiment 11) In this embodiment, a configuration of a light - emitting device using a thin - film transistor according to an aspect of the present invention for a pixel will be described. In this embodiment, a transistor for driving a light - emitting element will be described with reference to FIG. 25 for the cross - sectional structure of a pixel in the case of an n - type transistor. Note that FIG. 25 illustrates the case where the first electrode is a cathode and the second electrode is an anode, but the first electrode may be an anode and the second electrode may be a cathode.

[0318] FIG. 25(A) shows a cross - sectional view of a pixel in the case where the transistor 6031 is n - type and the light emitted from the light - emitting element 6033 is taken out from the side of the first electrode 6034. The transistor 6031 is covered with an insulating film 6037, and a partition wall 6038 having an opening is formed on the insulating film 6037. A part of the first electrode 6034 is exposed at the opening of the partition wall 6038 , and at this opening, the first electrode 6034, the electroluminescent layer 6035, and the second electrode 6036 are stacked in this order.

[0319] The first electrode 6034 is formed of a material or film thickness that transmits light, and can be formed of a metal, alloy, electroconductive compound, and a mixture thereof having a small work function . Specifically, it can be formed of an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr , an alloy containing these (such as Mg:Ag, Al:Li, Mg:In), and a chemical compound thereof In addition to compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er can also be used. When an electron injection layer is provided, other conductive layers such as aluminum may be used. The first electrode 6034 is formed to a thickness that allows light to pass through (preferably 5 Furthermore, the conductive layer is formed to a thickness of about 1000 nm to 3000 nm. A conductive layer having light-transmitting properties is formed by using a conductive oxide material so as to be in contact with the upper or lower surface of the substrate. In this case, the sheet resistance of the first electrode 6034 may be reduced. Oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-added Only conductive layers using other transparent oxide conductive materials such as zinc oxide (GZO) are used. It is also possible to use ITO and indium tin oxide containing silicon oxide (hereinafter referred to as ITS O) or indium oxide containing silicon oxide, and further 2 to 20% zinc oxide (Zn When a transparent oxide conductive material is used, the electroluminescent layer 6 It is desirable to provide an electron injection layer in 035.

[0320] The second electrode 6036 is formed of a material and a film thickness that reflects or blocks light. It is made of a material suitable for use as an anode, such as titanium nitride, zirconium nitride, One or more of titanium, tungsten, nickel, platinum, chromium, silver, aluminum, etc. In addition to the single layer film, titanium nitride and aluminum-based films are also available. The three-layer structure of the film, the film mainly composed of aluminum, and the titanium nitride film is formed as the second electrode 6036. It can be used for.

[0321] The electroluminescent layer 6035 is composed of one or more layers. In this case, these layers are classified into a hole injection layer, a hole transport layer, a light emitting layer, and a It can be classified into an electron transport layer, an electron injection layer, etc. The electroluminescent layer 6035 is a light-emitting layer as well as When the layer has any one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, From the first electrode 6034, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed in this order. The boundaries between the layers do not necessarily need to be clear, and the layers that make up each other may be stacked one on top of the other. In some cases, the materials are mixed together and the interface is unclear. Organic materials can be used. It is possible to use any material of molecular type. The number of repeats (degree of polymerization) corresponds to a low polymer of about 2 to 20. The distinction between these is not necessarily strict, and these are the types in which hole transport properties (hole mobility) are particularly important. For convenience, the hole injection layer is the layer that contacts the anode, and the The layer in contact with the hole injection layer is called the hole transport layer to distinguish it from the electron transport layer and electron injection layer. Similarly, the layer in contact with the cathode is called the electron injection layer, and the layer in contact with the electron injection layer is called the electron transport layer. The light-emitting layer may also function as an electron transport layer, and is therefore also called a light-emitting electron transport layer.

[0322] In the case of the pixel shown in FIG. 25(A), light emitted from the light emitting element 6033 is indicated by a white arrow. As shown, it can be taken out from the first electrode 6034 side.

[0323] Next, in FIG. 25(B), a transistor 6041 is an n-type transistor, and a light emitting element 6043 emits light. 10 is a cross-sectional view of a pixel in the case where light is extracted from the second electrode 6046 side. 41 is covered with an insulating film 6047, and a partition wall 604 8 having an opening is formed on the insulating film 6047. At the opening of the partition wall 6048, a part of the first electrode 6044 is exposed and the first electrode 6044, the electroluminescent layer 6045, and the second electrode 6046 are laminated in this order.

[0324] The first electrode 6044 is formed of a material and film thickness that reflect or shield light, and is also formed of a metal, alloy, electrically conductive compound, and a mixture thereof having a small work function. Specifically, it can be formed of an alkali metal such as Li or Cs, and an al kaline earth metal such as Mg, Ca, or Sr, an alloy containing these (such as Mg:Ag, Al:Li, Mg:In, etc.), and these compounds (calcium fluoride, calcium nitride), as well as rare earth metals such as Yb or Er can be used. When providing an electron injection layer, other conductive layers such as aluminum can also be used.

[0325] In addition, the second electrode 6046 is formed of a material or film thickness that transmits light, and is also formed of a material suitable for use as an anode . For example, indium tin oxide (ITO), zinc oxide ( ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), etc other light-transmitting oxide conductive materials can be used for the second electrode 6046. In addition to the above light-transmitting oxide conductive materials, for example, titanium nitride , zirconium nitride, titanium, tungsten, nickel, platinum, chromium, silver, aluminum can also be used for the second electrode 6046 by mixing 2 to 20% of zinc oxide (ZnO) into indium tin oxide containing silicon oxide (hereinafter referred to as ITSO) or indium oxide containing silicon oxide . In addition to the above light-transmitting oxide conductive materials, for example, titanium nitride , zirconium nitride, titanium, tungsten, nickel, platinum, chromium, silver, aluminum In addition to a single-layer film composed of one or more of tantalum nitride, etc., a film mainly composed of titanium nitride and aluminum Stacked with, a three-layer structure of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. Can also be used for the second electrode 6046. However, materials other than the translucent oxide conductive material When used, the second electrode 6046 is formed with a film thickness (preferably about 5 nm to 30 nm) such that light can pass through.

[0326] The electroluminescent layer 6045 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 25(A).

[0327] In the case of the pixel shown in FIG. 25(B), the light emitted from the light-emitting element 6043 can be taken out from the second electrode 6046 side as indicated by the white arrow.

[0328] Next, FIG. 25(C) shows a cross-sectional view of a pixel when the transistor 6051 is n-type and the light emitted from the light-emitting element 6053 is taken out from the first electrode 6054 side and the second electrode 6056 side. The transistor 6051 is covered with an insulating film 6057, and a partition wall 6058 having an opening is formed on the insulating film 6057. At the opening of the partition wall 6058, a part of the first electrode 6054 is exposed, and at the opening, the first electrode 6054, the electroluminescent layer 60 55, and the second electrode 6056 are laminated in this order.

[0329] The first electrode 6054 can be formed in the same manner as the first electrode 6034 in FIG. 25(A). Also, the second electrode 6056 can be formed in the same manner as the second electrode 6046 in FIG. 25(B). The electroluminescent layer 6055 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 25(A). ​​​​​​

[0330] In the case of the pixel shown in Fig. 25(C), the light emitted from the light-emitting element 6053 can be extracted from the side of the first electrode 6054 and the side of the second electrode 6056 as indicated by the white arrow . .

[0331] This embodiment can be implemented in appropriate combination with other embodiments

Example

[0332] By using the semiconductor device according to one aspect of the present invention, it is possible to provide an electronic device with high reliability and high-speed driving . Further, by using the semiconductor display device according to one aspect of the present invention , it is possible to provide an electronic device capable of displaying with high reliability, high contrast, and high visibility .

[0333] In addition, in the semiconductor device of the present invention, the temperature of the heat treatment in the manufacturing process can be suppressed . Therefore, even on a substrate made of a flexible synthetic resin such as plastic, which has inferior heat resistance to glass , it is possible to fabricate a thin-film transistor with excellent characteristics and high reliability . Therefore, by using the manufacturing method according to one aspect of the present invention, it is possible to provide a highly reliable, lightweight and flexible semiconductor device. As the plastic substrate , polyesters typified by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), poly ether ether ketone (PEEK), polysulfone (PSF), polyetherimide ( PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide , polyamide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, poly Examples include vinyl acetate and acrylic resin.

[0334] A semiconductor device according to one embodiment of the present invention can be used in a display device, a notebook personal computer, an image playback device having a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying the image). In addition, electronic devices that can use the semiconductor device according to one embodiment of the present invention include mobile phones, portable game machines, personal digital assistants, electronic books, video cameras, digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (such as car audio and digital audio players), copiers, facsimiles, printers, printer copiers, automated teller machines (A TM), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 26.

[0335] FIG. 26(A) shows an electronic book, which has a housing 7001, a display unit 7002, etc. A semiconductor display device according to one embodiment of the present invention can be used for the display unit 7002. By using the semiconductor display device according to one embodiment of the present invention for the display unit 7002, an electronic book with high reliability, high contrast, and high visibility can be provided. In addition, a semiconductor device according to one embodiment of the present invention can be used for an integrated circuit for controlling the driving of an electronic book. By using the semiconductor device according to one embodiment of the present invention for an integrated circuit for controlling the driving of an electronic book, an electronic book with high reliability and capable of high-speed driving can be provided. Further, by using a flexible substrate, the semiconductor device and the semiconductor display device can be made flexible. Therefore, it is possible to provide a flexible, lightweight, and user-friendly e-book.

[0336] FIG. 26(B) is a display device, which includes a housing 7011, a display unit 7012, a support base 7013, etc. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7012. By using the semiconductor display device according to one aspect of the present invention for the display unit 7012, a display device with high reliability, high contrast, and high visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of the display device. By using the semiconductor device according to one aspect of the present invention for the integrated circuit for controlling the driving of the display device, a display device with high reliability and capable of high-speed driving can be provided. Note that the display device includes all display devices for information display such as for personal computers, TV broadcast reception, and advertisement display.

[0337] FIG. 26(C) is a display device, which includes a housing 7021, a display unit 7022, etc. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7022. By using the semiconductor display device according to one aspect of the present invention for the display unit 7022, a display device with high reliability, high contrast, and high visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of the display device. By using the semiconductor device according to one aspect of the present invention for the integrated circuit for controlling the driving of the display device, a display device with high reliability and capable of high-speed driving can be provided. Further, by using a flexible substrate, flexibility can be imparted to the semiconductor device and the semiconductor display device. Therefore, a flexible, lightweight, and user-friendly display device can be provided. Thus , as shown in Fig. 26(C), the display device can be fixed to a fabric or the like for use, and the range of applications of the display device is significantly expanded.

[0338] Fig. 26(D) shows a portable game console, which includes a housing 7031, a housing 7032, a display unit 7033, a display unit 7034, a microphone 7035, a speaker 7036, operation keys 7037, a start button 7038, etc. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7033 and the display unit 7034. By using the semiconductor display device according to one aspect of the present invention for the display unit 7033 and the display unit 7034, a portable game console with high reliability, high contrast, and high visibility can be provided. In addition, the semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the driving of a portable game console. By using the semiconductor device according to one aspect of the present invention in an integrated circuit for controlling the driving of a portable game console, a portable game console with high reliability and capable of high-speed driving can be provided. Note that the portable game console shown in Fig. 26(D) has two display units 7033 and 7034, but the number of display units of the portable game console is not limited to this.

[0339] Fig. 26(E) shows a mobile phone, which includes a housing 7041, a display unit 7042, an audio input unit 7043, an audio output unit 7044, operation keys 7045, a light receiving unit 7046, etc. By converting the light received by the light receiving unit 7046 into an electrical signal, an external image can be captured. The semiconductor display device according to one aspect of the present invention can be used for the display unit 7042. The display unit 7 042. By using the semiconductor display device according to one aspect of the present invention in 042, a mobile phone with high reliability and high contrast and visibility can be provided. Further, the semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the driving of a mobile phone. By using the semiconductor device according to one aspect of the present invention in an integrated circuit for controlling the driving of a mobile phone, a mobile phone with high reliability and capable of high-speed driving can be provided. This embodiment can be implemented in appropriate combination with the above-described embodiment.

[0340]

Explanation of Reference Numerals

[0341] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power supply line 52 Power supply line 53 Power supply line 100 Substrate 101 Gate electrode 102 Gate insulating film 103 Oxide semiconductor film 104 Oxide semiconductor film 105a Conductive film 105b Conductive film 105c Conductive film 105d Conductive film 105e Conductive film 106 Source electrode 107 Drain electrode 108 Oxide semiconductor film 109 Insulating film 110 Transistor 111 Back gate electrode 112 Insulating film 120 Thin film transistor 126 Source electrode 127 Drain electrode 128 Oxide semiconductor film 129 Insulating film 130 Thin film transistor 136 Source electrode 137 Drain electrode 138 Oxide semiconductor film 139 Insulating film 140 Thin film transistor 146 Source electrode 147 Drain electrode 148 Oxide semiconductor film 149 Insulating film 300 Substrate 301 Gate electrode 302 Gate insulating film 303 Oxide semiconductor film 304 Oxide semiconductor film 305a Conductive film 305b Conductive film 306 Source electrode 307 Drain electrode 309 Insulating film 310 Thin film transistor 311 Channel protection film 312 Back gate electrode 313 Insulating film 400 Substrate 401 Gate electrode 402 Gate insulating film 403 Oxide semiconductor film 404 Oxide semiconductor film 405a Conductive film 405b Conductive film 406 Source electrode 407 Drain electrode 409 Insulating film 410 Thin film transistor 700 Pixel section 701 Signal line drive circuit 702 Scan line drive circuit 703 Pixel 704 Transistor 705 Display element 706 Holding capacitor 707 Signal line 708 Scan line 710 Pixel electrode 711 Counter electrode 712 Microcapsule 713 Drain electrode 714 Resin 800 Substrate 801 Gate electrode 802 Gate insulating film 803 Oxide semiconductor film 804 Oxide semiconductor film 805 Oxide semiconductor film 806 Conductive film 806a Conductive film 806b Conductive film 807 Source electrode 808 Drain electrode 809 Insulating film 813 Thin film transistor 814 Pixel electrode 815 Transparent conductive film 816 Transparent conductive film 819 Holding capacitor 820 Terminal 821 Terminal 822 Capacitance wiring 1401 Thin film transistor 1402 Gate electrode 1403 Gate insulating film 1404 Oxide semiconductor film 1406a Conductive film 1406b Conductive film 1407 Insulating film 1408 Insulating film 1410 Pixel electrode 1411 Alignment film 1413 Counter electrode 1414 Alignment film 1415 Liquid crystal 1416 Sealant 1417 Spacer 1420 Substrate 1601 Liquid crystal panel 1602 Diffusion plate 1603 Prism sheet 1604 Diffusion plate 1605 Light guide plate 1606 Reflector 1607 Light source 1608 Circuit board 1609 FPC 1610 FPC 5300 Substrate 5301 Pixel section 5302 Scanning line drive circuit 5303 Scanning line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5601 Shift register 5602 Sampling circuit 5603 Transistor 5604 Wiring 5605 Wiring 6031 Transistor 6033 Light emitting element 6034 Electrode 6035 Electroluminescent layer 6036 Electrode 6037 Insulating film 6038 Partition wall 6041 Transistor 6043 Light-emitting element 6044 Electrode 6045 Electroluminescent layer 6046 Electrode 6047 Insulating film 6048 Partition wall 6051 Transistor 6053 Light-emitting element 6054 Electrode 6055 Electroluminescent layer 6056 Electrode 6057 Insulating film 6058 Partition wall 7001 Housing 7002 Display unit 7011 Housing 7012 Display unit 7013 Support stand 7021 Housing 7022 Display unit 7031 Housing 7032 Housing 7033 Display unit 7034 Display unit 7035 Microphone 7036 Speaker 7037 Operation key 7038 Stylus 7041 Housing 7042 Display unit 7043 Voice input section 7044 Voice output section 7045 Operation key 7046 Light-receiving section

Claims

1. An oxide semiconductor film containing In, Ga, and Zn, a first conductive film and a second conductive film each having a region positioned so as to sandwich the oxide semiconductor film therebetween, a first silicon oxide film positioned between the oxide semiconductor film and the first conductive film and having a region in contact with the oxide semiconductor film, a second silicon oxide film positioned between the oxide semiconductor film and the second conductive film and having a region in contact with the oxide semiconductor film, a third conductive film having a region in contact with the oxide semiconductor film, a fourth conductive film having a region in contact with the oxide semiconductor film, and the first conductive film and the second conductive film each have a function as a gate electrode, the third conductive film has a function as a source electrode, the fourth conductive film has a function as a drain electrode, in a cross-sectional view in the channel length direction, a first end portion of the second conductive film is positioned outside a second end portion of the oxide semiconductor film, and the second end portion of the oxide semiconductor film is positioned outside a third end portion of the first conductive film, a potential other than a fixed potential is applied to the second conductive film, the third conductive film or the fourth conductive film contains titanium, tungsten, or molybdenum, a semiconductor device.

2. An oxide semiconductor film containing indium oxide, a first conductive film and a second conductive film each having a region positioned so as to sandwich the oxide semiconductor film therebetween, a first silicon oxide film positioned between the oxide semiconductor film and the first conductive film and having a region in contact with the oxide semiconductor film, a second silicon oxide film positioned between the oxide semiconductor film and the second conductive film and having a region in contact with the oxide semiconductor film, a third conductive film having a region in contact with the oxide semiconductor film, a fourth conductive film having a region in contact with the oxide semiconductor film, and the first conductive film and the second conductive film each have a function as a gate electrode, the third conductive film has a function as a source electrode, the fourth conductive film has a function as a drain electrode, in a cross-sectional view in the channel length direction, a first end portion of the second conductive film is positioned outside a second end portion of the oxide semiconductor film, and the second end portion of the oxide semiconductor film is positioned outside a third end portion of the first conductive film, a potential other than a fixed potential is applied to the second conductive film, The semiconductor device, wherein the third conductive film or the fourth conductive film contains titanium, tungsten, or molybdenum.

Images