Semiconductor device

Abstract

To provide a semiconductor device having improved avalanche resistance.SOLUTION: A semiconductor device comprises; a silicon carbide layer having a first surface and a second surface; and a first-conductivity-type first silicon carbide region which includes a first region, and second and third regions positioned between the first region and the first surface, wherein the first-conductivity-type impurity concentration in the second region is equal to or higher than that of the first region, and the first-conductivity-type impurity concentration in the third region is higher than that of the second region. The semiconductor device further comprises: a second-conductivity-type second silicon carbide region which is positioned between the first silicon carbide region and the first surface, and includes a fourth region in contact with the second region and a fifth region in contact with the third region and having a second-conductivity-type impurity concentration higher than that of the fourth region; a first-conductivity-type third silicon carbide region between the second silicon carbide region and the first surface; a first gate electrode which is opposite to the second silicon carbide region; a first gate insulation layer; a first electrode including a first portion in contact with the second silicon carbide region and the third silicon carbide region; and a second electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Silicon carbide is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as a bandgap about three times that of silicon, a breakdown electric field strength about ten times that of silicon, and a thermal conductivity about three times that of silicon. By utilizing these characteristics, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) capable of high breakdown voltage, low loss, and high-temperature operation can be realized.

[0003] In a MOSFET using silicon carbide, an improvement in avalanche tolerance is desired.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device with improved avalanche tolerance.

Means for Solving the Problems

[0006] The semiconductor device according to the embodiment includes a silicon carbide layer having a first surface and a second surface facing the first surface, a first silicon carbide region of a first conductivity type provided in the silicon carbide layer, the first silicon carbide region including a first region, a second region, and a third region, the second region being located between the first region and the first surface, the third region being located between the first region and the first surface, the first conductivity type impurity concentration of the second region being equal to or higher than the first conductivity type impurity concentration of the first region, and the first conductivity type impurity concentration of the third region being higher than that of the second region; a second silicon carbide region of a second conductivity type provided in the silicon carbide layer and located between the first silicon carbide region and the first surface, the second silicon carbide region including a fourth region and a fifth region, the fourth region being in contact with the second region, the fifth region being in contact with the third region, and the second conductivity type impurity concentration of the fifth region being higher than that of the fourth region; a third silicon carbide region of the first conductivity type provided in the silicon carbide layer and located between the second silicon carbide region and the first surface; a first gate electrode provided on the side of the first surface with respect to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface; a second gate electrode provided on the side of the first surface with respect to the silicon carbide layer, extending in the first direction, provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region on the first surface; a first gate insulating layer provided between the second silicon carbide region and the first gate electrode; a second gate insulating layer provided between the second silicon carbide region and the second gate electrode; a first electrode provided on the side of the first surface with respect to the silicon carbide layer, the first electrode including a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region; and a second electrode provided on the side of the second surface with respect to the silicon carbide layer.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0009] Also, in the following description, when there is notation of n ++ n + n, n - and p ++ p + p, p - these notations represent the relative levels of impurity concentrations in each conductivity type. That is, n ++ has a relatively higher n-type impurity concentration than n + , n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p ++ has a relatively higher p-type impurity concentration than p + , and p +has a relatively higher p-type impurity concentration than p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that n + type, n - type may simply be referred to as n-type, p + type, p - type may also simply be referred to as p-type in some cases.

[0010] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative high or low of the impurity concentration can be determined, for example, from the high or low of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Also, distances such as the width and depth of the impurity region can be obtained, for example, by SIMS. Also, distances such as the width and depth of the impurity region can be obtained, for example, from the images of SCM or Scanning Electron Microscope (SEM). Also, the thickness of the insulating layer, etc. can be measured, for example, on the images of SIMS, SEM, or Transmission Electron Microscope (TEM).

[0011] Note that in this specification, the "p-type impurity concentration" of the p-type silicon carbide region means the net p-type impurity concentration obtained by subtracting the n-type impurity concentration of the region from the p-type impurity concentration of the region. Also, the "n-type impurity concentration" of the n-type silicon carbide region means the net n-type impurity concentration obtained by subtracting the p-type impurity concentration of the region from the n-type impurity concentration of the region.

[0012] Also, unless otherwise specified in the specification, the impurity concentration of a specific region shall be represented by the impurity concentration at the center of the region.

[0013] (First Embodiment) The semiconductor device according to the first embodiment includes a silicon carbide layer having a first surface and a second surface facing the first surface, and a first silicon carbide region of a first conductivity type provided in the silicon carbide layer. The first silicon carbide region includes a first region, a second region, and a third region. The second region is located between the first region and the first surface, and the third region is located between the first region and the first surface. The first conductivity type impurity concentration in the second region is equal to or higher than the first conductivity type impurity concentration in the first region, and the first conductivity type impurity concentration in the third region is higher than that in the second region. The semiconductor device also includes a second silicon carbide region of a second conductivity type provided in the silicon carbide layer and located between the first silicon carbide region and the first surface. The second silicon carbide region includes a fourth region and a fifth region. The fourth region is in contact with the second region, and the fifth region is in contact with the third region. The second conductivity type impurity concentration in the fifth region is higher than that in the fourth region. The semiconductor device further includes a third silicon carbide region of a first conductivity type provided in the silicon carbide layer and located between the second silicon carbide region and the first surface, a first gate electrode provided on the side of the first surface with respect to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface, a second gate electrode provided on the side of the first surface with respect to the silicon carbide layer, extending in the first direction, and provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region on the first surface, a first gate insulating layer provided between the second silicon carbide region and the first gate electrode, a second gate insulating layer provided between the second silicon carbide region and the second gate electrode, and a first electrode provided on the side of the first surface with respect to the silicon carbide layer, including a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region, and a second electrode provided on the side of the second surface with respect to the silicon carbide layer.

[0014] The semiconductor device according to the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 according to the first embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) that forms a body region and a source region by ion implantation.

[0015] Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. The MOSFET 100 is a vertical n-channel MOSFET using electrons as carriers.

[0016] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. FIGS. 2 and 3 are schematic top views of the semiconductor device according to the first embodiment. FIG. 2 is a schematic diagram showing the patterns of the gate electrode and the impurity regions on the upper surface of the silicon carbide layer. FIG. 3 is a schematic diagram showing the pattern of the impurity regions on the upper surface of the silicon carbide layer excluding the gate electrode from FIG. 2. FIG. 1 is a cross-sectional view taken along the line AA' of FIGS. 2 and 3.

[0017] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate insulating layer 16a, a second gate insulating layer 16b, a third gate insulating layer 16c, a first gate electrode 18a, a second gate electrode 18b, a third gate electrode 18c, and an interlayer insulating layer 20. The source electrode 12 includes a contact electrode portion 12x (first portion).

[0018] In the silicon carbide layer 10, an n + -type drain region 22, an n-type drift region 24 (first silicon carbide region), a p-type body region 26 (second silicon carbide region), and an n ++ -type source region 30 (third silicon carbide region) are provided.

[0019] The n-type drift region 24 includes an n - -type lower region 24x (first region), an n-type first low-concentration n region 24y1 (second region), an n-type second low-concentration n region 24y2 (sixth region), an n-type third low-concentration n region 24y3, and an n + -type first high-concentration n region 24z1 (third region) and an n + -type second high-concentration n region 24z2 (seventh region).

[0020] The p-shaped body region 26 includes a first low-concentration p-region 26x1 (the fourth region) of p-type, a second low-concentration p-region 26x2 (the eighth region) of p-type, a third low-concentration p-region 26x3 of p-type, a first high-concentration p-region 26y1 (the fifth region) of p-type, a second high-concentration p-region 26y2 (the ninth region) of p-type, and a contact region 26z (the tenth region) of p-type. + A first high-concentration p-region 26y1 (the fifth region) of p-type, + a second high-concentration p-region 26y2 (the ninth region) of p-type, ++ and a contact region 26z (the tenth region) of p-type.

[0021] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is single-crystalline SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

[0022] The silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). Hereinafter, the first surface F1 may be referred to as the front surface, and the second surface F2 may be referred to as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" means the depth in the direction from the first surface toward the second surface.

[0023] The first direction and the second direction are parallel to the first surface F1. The second direction is perpendicular to the first direction. The direction from the first surface F1 toward the second surface F2 is the third direction. The third direction is perpendicular to the first direction and the second direction.

[0024] The first surface F1 is, for example, a surface inclined 0 degrees or more and 8 degrees or less with respect to the (0001) plane. The second surface F2 is, for example, a surface inclined 0 degrees or more and 8 degrees or less with respect to the (000-1) plane. The (0001) plane is called the silicon plane. The (000-1) plane is called the carbon plane.

[0025] n + The n-shaped drain region 22 is provided on the back surface side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm-3 1×10 or less 21 cm -3 is as follows.

[0026] The n-type drift region 24 is provided between the drain region 22 and the first surface F1. The n-type drift region 24 is provided between the source electrode 12 and the drain electrode 14.

[0027] The n-type drift region 24 is provided on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 24 is lower than the n-type impurity concentration of the drain region 22. The thickness of the drift region 24 is, for example, 3 μm or more and 150 μm or less.

[0028] The drift region 24 is n - -type lower region 24x (first region), n-type first low-concentration n region 24y1 (second region), n-type second low-concentration n region 24y2 (sixth region), n-type third low-concentration n region 24y3, n + -type first high-concentration n region 24z1 (third region), n + -type second high-concentration n region 24z2 (seventh region).

[0029] n - -type lower region 24x is provided on the side of the second surface F2 of the drift region 24. The lower region 24x is in contact with the drain region 22.

[0030] The lower region 24x contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the lower region 24x is, for example, 4×10 14 cm -3 or more and 1×10 17 cm -3 or less.

[0031] The n-type first low-concentration n-region 24y1, the n-type second low-concentration n-region 24y2, and the n-type third low-concentration n-region 24y3 are located between the lower region 24x and the first surface F1. The first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 are located between the lower region 24x and the body region 26. The first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 are in contact with the body region 26. The first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 extend in the first direction.

[0032] The first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 contain, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 is equal to or higher than the n-type impurity concentration of the lower region 24x. The n-type impurity concentration of the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3 is, for example, 4×10 14 cm -3 or more and 2×10 17 cm -3 or less.

[0033] n + type first high-concentration n-region 24z1, n + type second high-concentration n-region 24z2 are located between the lower region 24x and the first surface F1. The first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are located between the lower region 24x and the body region 26. The first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are in contact with the body region 26. The first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 extend, for example, in the first direction.

[0034] The first high-concentration n-region 24z1 is located between the first low-concentration n-region 24y1 and the second low-concentration n-region 24y2. The second high-concentration n-region 24z2 is located between the second low-concentration n-region 24y2 and the third low-concentration n-region 24y3.

[0035] The first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 contain, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentrations of the first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are higher than the n-type impurity concentrations of the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3.

[0036] The n-type impurity concentrations of the first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are, for example, 1.5 times or more and 10 times or less the n-type impurity concentrations of the first low-concentration n-region 24y1, the second low-concentration n-region 24y2, and the third low-concentration n-region 24y3. The n-type impurity concentrations of the first high-concentration n-region 24z1 and the second high-concentration n-region 24z2 are, for example, 1×10 15 cm -3 or more and 2×10 17 cm -3 or less.

[0037] The p-type body region 26 is provided between the drift region 24 and the first surface F1. The body region 26 extends in the first direction. The body region 26 functions as the channel region of the MOSFET 100.

[0038] A part of the body region 26 is in contact with the first surface F1. A part of the body region 26 faces the first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c. A part of the body region 26 becomes the channel region of the MOSFET 100.

[0039] The body region 26 contains, for example, aluminum (Al) as a p-type impurity. The depth of the body region 26 is, for example, 500 nm or more and 900 nm or less. The body region 26 is electrically connected to the source electrode 12. The body region 26 is fixed to the potential of the source electrode 12.

[0040] The body region 26 includes a p-type first low-concentration p-region 26x1 (the fourth region), a p-type second low-concentration p-region 26x2 (the eighth region), a p-type third low-concentration p-region 26x3, a p + -type first high-concentration p-region 26y1 (the fifth region), a p +a second high-concentration p-region 26y2 (ninth region) of the type, p ++ and a contact region 26z (tenth region) of the type, p.

[0041] The first low-concentration p-region 26x1 is in contact with the first low-concentration n-region 24y1. The first low-concentration p-region 26x1 is located in the third direction of the first low-concentration n-region 24y1.

[0042] The second low-concentration p-region 26x2 is in contact with the second low-concentration n-region 24y2. The second low-concentration p-region 26x2 is located in the third direction of the second low-concentration n-region 24y2.

[0043] The third low-concentration p-region 26x3 is in contact with the third low-concentration n-region 24y3. The third low-concentration p-region 26x3 is located in the third direction of the third low-concentration n-region 24y3.

[0044] The first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3 of the p-type contain, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the third low-concentration p-region 26x3 of the p-type is, for example, 5×10 16 cm -3 or more and 5×10 19 cm -3 or less.

[0045] The first high-concentration p-region 26y1 is in contact with the first high-concentration n-region 24z1. The first high-concentration p-region 26y1 is located in the third direction of the first high-concentration n-region 24z1. The first high-concentration p-region 26y1 is located between the first low-concentration p-region 26x1 and the second low-concentration p-region 26x2.

[0046] The first high-concentration p-region 26y1 is located, for example, in the third direction of the contact electrode portion 12x. The first high-concentration p-region 26y1 is located, for example, directly below the contact electrode portion 12x.

[0047] The first high-concentration p-region 26y1 is located, for example, in the third direction of the contact region 26z. The first high-concentration p-region 26y1 is located, for example, directly below the contact region 26z. The first high-concentration p-region 26y1 is in contact with the contact region 26z, for example.

[0048] The second high-concentration p-region 26y2 is in contact with the second high-concentration n-region 24z2. The second high-concentration p-region 26y2 is located in the third direction of the second high-concentration n-region 24z2. The second high-concentration p-region 26y2 is located between the second low-concentration p-region 26x2 and the third low-concentration p-region 26x3.

[0049] The second high-concentration p-region 26y2 is located, for example, in the third direction of the contact electrode portion 12x. The second high-concentration p-region 26y2 is located, for example, directly below the contact electrode portion 12x.

[0050] The second high-concentration p-region 26y2 is located, for example, in the third direction of the contact region 26z. The second high-concentration p-region 26y2 is located, for example, directly below the contact region 26z. The second high-concentration p-region 26y2 is in contact with the contact region 26z, for example.

[0051] The first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 contain, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentrations of the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are higher than the p-type impurity concentrations of the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the p-type third low-concentration p-region 26x3.

[0052] The p-type impurity concentrations of the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are, for example, 1.5 times or more and 10 times or less the p-type impurity concentrations of the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the p-type third low-concentration p-region 26x3. The p-type impurity concentrations of the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are, for example, 5×10 16 cm -3 or more and 1×10 20 cm -3 or less.

[0053] p ++ The contact region 26z of the p-type is located between the first high-concentration p-region 26y1 and the first surface F1. The contact region 26z is located between the first high-concentration p-region 26y1 and the source electrode 12. The contact region 26z is located between the first high-concentration p-region 26y1 and the contact electrode portion 12x of the source electrode 12. The contact region 26z is located in the third direction of the first high-concentration p-region 26y1. The contact region 26z is in contact with the first high-concentration p-region 26y1.

[0054] The contact region 26z is located between the second high-concentration p-region 26y2 and the first surface F1. The contact region 26z is located between the second high-concentration p-region 26y2 and the source electrode 12. The contact region 26z is located between the second high-concentration p-region 26y2 and the contact electrode portion 12x of the source electrode 12. The contact region 26z is located in the third direction of the second high-concentration p-region 26y2. The contact region 26z is in contact with the second high-concentration p-region 26y2.

[0055] The contact region 26z is in contact with the source electrode 12. The contact region 26z is electrically connected to the source electrode 12. The contact between the contact region 26z and the source electrode 12 is, for example, an ohmic contact. The contact region 26z is fixed to the potential of the source electrode 12.

[0056] The contact region 26z is in contact with the contact electrode portion 12x of the source electrode 12. The depth of the contact region 26z is, for example, 200 nm or more and 500 nm or less.

[0057] The contact region 26z contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 26z is higher than the p-type impurity concentrations of the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2. The p-type impurity concentration of the contact region 26z is, for example, 1×10 19 cm -3 or more and 5×10 21 cm-3 The following is the case.

[0058] n + The source region 30 in the shape of n is provided between the body region 26 and the first surface F1. The source region 30 is provided, for example, between the first low-concentration p region 26x1 and the first surface F1. The source region 30 is provided, for example, between the first high-concentration p region 26y1 and the first surface F1.

[0059] The source region 30 is provided, for example, between the third low-concentration p region 26x3 and the first surface F1. The source region 30 is provided, for example, between the second high-concentration p region 26y2 and the first surface F1.

[0060] The source region 30 contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The n-type impurity concentration of the source region 30 is higher than the n-type impurity concentration of the drift region 24.

[0061] The n-type impurity concentration of the source region 30 is, for example, 1×10 19 cm -3 or more and 5×10 21 cm -3 or less. The depth of the source region 30 is shallower than the depth of the body region 26. The depth of the source region 30 is, for example, 80 nm or more and 200 nm or less.

[0062] The source region 30 is in contact with the source electrode 12. The source region 30 is electrically connected to the source electrode 12. The contact between the source region 30 and the source electrode 12 is, for example, an ohmic contact. The source region 30 is fixed to the potential of the source electrode 12. The source region 30 is in contact with the contact electrode portion 12x of the source electrode 12.

[0063] The first gate electrode 18a is provided on the side of the first surface F1 with respect to the silicon carbide layer 10. The first gate electrode 18a extends in the first direction. The first gate electrode 18a faces the body region 26 on the first surface F1.

[0064] The second gate electrode 18b is provided on the side of the first surface F1 with respect to the silicon carbide layer 10. The second gate electrode 18b extends in the first direction. The second gate electrode 18b is provided in the second direction with respect to the first gate electrode 18a. The second gate electrode 18b faces the body region 26 on the first surface F1.

[0065] The third gate electrode 18c is provided on the side of the first surface F1 with respect to the silicon carbide layer 10. The third gate electrode 18c extends in the first direction. The third gate electrode 18c is provided in the second direction with respect to the second gate electrode 18b. The second gate electrode 18b is provided between the first gate electrode 18a and the third gate electrode 18c. The third gate electrode 18c faces the body region 26 on the first surface F1.

[0066] The first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c are conductive layers. The first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c are, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0067] The first gate insulating layer 16a is provided between the first gate electrode 18a and the body region 26. The second gate insulating layer 16b is provided between the second gate electrode 18b and the body region 26. The third gate insulating layer 16c is provided between the third gate electrode 18c and the body region 26.

[0068] The first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c include, for example, silicon oxide. The first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c include, for example, a silicon oxide layer. It is also possible to apply, for example, a high-k dielectric material to the first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c. Further, it is also possible to apply, for example, a stacked structure of a silicon oxide layer and a high-k dielectric layer to the first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c.

[0069] The thicknesses of the first gate insulating layer 16a, the second gate insulating layer 16b, and the third gate insulating layer 16c are, for example, 30 nm or more and 100 nm or less.

[0070] The interlayer insulating layer 20 is provided over the first gate electrode 18a, the second gate electrode 18b, and the third gate electrode 18c. The interlayer insulating layer 20 is provided between the first gate electrode 18a and the source electrode 12, between the second gate electrode 18b and the source electrode 12, and between the third gate electrode 18c and the source electrode 12.

[0071] The interlayer insulating layer 20 electrically isolates the first gate electrode 18a from the source electrode 12, the second gate electrode 18b from the source electrode 12, and the third gate electrode 18c from the source electrode 12. The interlayer insulating layer 20 contains, for example, silicon oxide. The interlayer insulating layer 20 is, for example, a silicon oxide layer.

[0072] The source electrode 12 is provided on the side of the first surface F1 with respect to the silicon carbide layer 10. The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the contact region 26z and the source region 30.

[0073] The source electrode 12 includes a contact electrode portion 12x. The contact electrode portion 12x is provided between the first gate electrode 18a and the second gate electrode 18b. The contact electrode portion 12x is in contact with the contact region 26z and the source region 30.

[0074] The source electrode 12 contains a metal. The source electrode 12 has, for example, a stacked structure of a barrier metal film and a metal film.

[0075] The barrier metal film contains, for example, titanium (Ti), tungsten (W), or tantalum (Ta). The barrier metal film is, for example, a titanium film, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

[0076] The metal film contains, for example, aluminum (Al). The metal film is, for example, an aluminum film.

[0077] The contact electrode portion 12x of the source electrode 12 includes, for example, a metal silicide layer. The metal silicide layer is in contact with, for example, the contact region 26z. The metal silicide layer is in contact with, for example, the source region 30.

[0078] The metal silicide layer includes, for example, nickel (Ni), titanium (Ti), or cobalt (Co). The metal silicide layer is, for example, a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer.

[0079] The drain electrode 14 is provided on the second surface F2 side with respect to the silicon carbide layer 10. The drain electrode 14 is provided on the second surface F2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface F2.

[0080] The drain electrode 14 includes, for example, a metal or a metal semiconductor compound. The drain electrode 14 includes, for example, a nickel silicide layer, a titanium layer, a nickel layer, a silver layer, or a gold layer.

[0081] The drain electrode 14 is electrically connected to the drain region 22. The drain electrode 14 is in contact with, for example, the drain region 22.

[0082] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0083] FIG. 4 is a schematic cross-sectional view of a semiconductor device of a comparative example. FIG. 4 is a diagram corresponding to FIG. 1 of the first embodiment.

[0084] The semiconductor device of the comparative example is a planar gate type vertical MOSFET 900 using silicon carbide.

[0085] In the MOSFET 900, the n-type drift region 24 has an n + type first high-concentration n region 24z1, n +The MOSFET 900 is different from the MOSFET 100 of the first embodiment in that it does not include the second high-concentration n-region 24z2 of the n-type. Also, the p-type body region 26 of the MOSFET 900 does not include the first high-concentration p-region 26y1 of the p-type and the second high-concentration p-region 26y2 of the p-type, which is different from the MOSFET 100 of the first embodiment. + the first high-concentration p-region 26y1 of the p-type and + the second high-concentration p-region 26y2 of the p-type, which is different from the MOSFET 100 of the first embodiment.

[0086] When a reverse bias voltage exceeding the breakdown voltage is applied to the MOSFET, avalanche breakdown occurs at the pn junction and an avalanche current flows. When the avalanche current flows, for example, the temperature of the MOSFET rises, and the MOSFET may be destroyed. The current or energy that the MOSFET can withstand when avalanche breakdown occurs is called the avalanche tolerance.

[0087] In the MOSFET 900, for example, the breakdown voltage of the pn junction between the p-type body region 26 and the n-type drift region 24 provided in the cell portion becomes too high, so that the reverse bias voltage at which avalanche breakdown occurs increases, and the avalanche tolerance may decrease. In particular, if avalanche breakdown occurs at the pn junction in the termination region (not shown) surrounding the cell portion of the MOSFET 900 before the cell portion, the avalanche tolerance decreases. This is because the area of the termination region is smaller than the area of the cell portion, so the current that the MOSFET 900 can conduct is limited.

[0088] In the MOSFET 100 of the first embodiment, the n-type drift region 24 includes the first high-concentration n-region 24z1 of the n-type and the second high-concentration n-region 24z2 of the n-type. Also, the p-type body region 26 includes the first high-concentration p-region 26y1 of the p-type and the second high-concentration p-region 26y2 of the p-type. + the first high-concentration n-region 24z1 of the n-type and + the second high-concentration n-region 24z2 of the n-type. Also, the p-type body region 26 includes the first high-concentration p-region 26y1 of the p-type and + the first high-concentration p-region 26y1 of the p-type and + the second high-concentration p-region 26y2 of the p-type.

[0089] The MOSFET 100 is formed by a pn junction formed by the first high-concentration n-region 24z1 of the n-type and the first high-concentration p-region 26y1 of the p-type, and + the first high-concentration n-region 24z1 of the n-type and the first high-concentration p-region 26y1 of the p-type, and + the pn junction formed by the first high-concentration p-region 26y1 of the p-type, and, the n-type +A second high-concentration n-region 24z2 of the type and p + It includes a pn junction formed by a second high-concentration p-region 26y2 of the p-type. The MOSFET 100 partially includes a pn junction with a high impurity concentration in the cell portion, making avalanche breakdown likely to occur in the cell portion. Therefore, the avalanche withstand voltage of the MOSFET 100 is improved.

[0090] From the viewpoint of improving the avalanche withstand voltage, for one contact electrode portion 12x, two pn junctions are preferably provided: a pn junction formed by the first high-concentration n-region 24z1 and the first high-concentration p-region 26y1, and a pn junction formed by the second high-concentration n-region 24z2 and the second high-concentration p-region 26y2. By providing two pn junctions, the path of the avalanche current flowing into one contact electrode portion 12x is dispersed, suppressing heat generation in the contact electrode portion 12x. Thus, the avalanche withstand voltage is improved.

[0091] From the viewpoint of improving the avalanche withstand voltage, the first high-concentration p-region 26y1 is preferably located in the third direction of the contact region 26z. In other words, the first high-concentration p-region 26y1 is preferably located directly below the contact region 26z. Also, the first high-concentration p-region 26y1 preferably contacts the contact region 26z. With the above configuration, the electrical resistance of the path through which the avalanche current flows is reduced. Thus, heat generation in the contact electrode portion 12x is suppressed, and the avalanche withstand voltage is improved.

[0092] Similarly, from the viewpoint of improving the avalanche withstand voltage, the second high-concentration p-region 26y2 is preferably located in the third direction of the contact region 26z. In other words, the second high-concentration p-region 26y2 is preferably located directly below the contact region 26z. Also, the second high-concentration p-region 26y2 preferably contacts the contact region 26z. With the above configuration, the electrical resistance of the path through which the avalanche current flows is reduced. Thus, heat generation in the contact electrode portion 12x is suppressed, and the avalanche withstand voltage is improved.

[0093] From the perspective of improving the avalanche withstand voltage, the p-type impurity concentrations of the first high-concentration p-region 26y1 and the second high-concentration p-region 26y2 are preferably 1.5 times or more, more preferably 2 times or more, the p-type impurity concentrations of the first low-concentration p-region 26x1, the second low-concentration p-region 26x2, and the p-type third low-concentration p-region 26x3.

[0094] (Modified Example) FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a modified example of the first embodiment. FIG. 5 corresponds to FIG. 1 of the first embodiment.

[0095] The semiconductor device of the modified example is a planar gate type vertical MOSFET 101 using silicon carbide.

[0096] The MOSFET 101 is different from the MOSFET 100 of the first embodiment in that the n-type drift region 24 does not include the n-type second low-concentration n-region 24y2 and the n + type second high-concentration n-region 24z2. Also, the MOSFET 900 is different from the MOSFET 100 of the first embodiment in that the p-type body region 26 does not include the p-type second low-concentration p-region 26x2 and the p + type second high-concentration p-region 26y2.

[0097] By the same operation as the MOSFET 100 of the first embodiment, the avalanche withstand voltage of the MOSFET 101 is improved.

[0098] As described above, according to the first embodiment and the modified example, a MOSFET with improved avalanche withstand voltage can be realized.

[0099] (Second Embodiment) The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that the first silicon carbide region further includes an eleventh region in contact with the first surface, the first electrode further includes a second portion in contact with the eleventh region, the second portion is provided between the first gate electrode and the second gate electrode, and the second portion is located in the first direction of the first portion. Hereinafter, some descriptions may be omitted for the content overlapping with the first embodiment.

[0100] The semiconductor device of the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 of the second embodiment is a DIMOSFET. Further, the MOSFET 200 of the second embodiment includes a Schottky Barrier Diode (SBD) as a built-in diode.

[0101] Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. The MOSFET 200 is a vertical n-channel MOSFET having electrons as carriers.

[0102] FIGS. 6 and 7 are schematic cross-sectional views of the semiconductor device of the second embodiment. FIGS. 8 and 9 are schematic top views of the semiconductor device of the second embodiment. FIG. 8 is a schematic diagram showing the patterns of the gate electrode and the impurity regions on the upper surface of the silicon carbide layer. FIG. 9 is a schematic diagram showing the pattern of the impurity regions on the upper surface of the silicon carbide layer excluding the gate electrode from FIG. 8. FIG. 6 is a cross-sectional view taken along the line BB' of FIGS. 8 and 9. FIG. 7 is a cross-sectional view taken along the line BB' of FIGS. 8 and 9.

[0103] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate insulating layer 16a, a second gate insulating layer 16b, a third gate insulating layer 16c, a first gate electrode 18a, a second gate electrode 18b, a third gate electrode 18c, and an interlayer insulating layer 20. The source electrode 12 includes a contact electrode portion 12x (first portion) and a diode electrode portion 12y (second portion).

[0104] In the silicon carbide layer 10, an n + -type drain region 22, an n-type drift region 24 (first silicon carbide region), a p-type body region 26 (second silicon carbide region), and an n ++ -type source region 30 (third silicon carbide region) are provided.

[0105] The n-type drift region 24 is an n -The lower region 24x (the first region) of the shape, the first low-concentration n region 24y1 of n-type (the second region), the second low-concentration n region 24y2 of n-type (the sixth region), the third low-concentration n region 24y3 of n-type, n + the first high-concentration n region 24z1 of n-type (the third region), n + the second high-concentration n region 24z2 of n-type (the seventh region), and the JBS region 24s (the eleventh region).

[0106] The p-type body region 26 includes a first low-concentration p region 26x1 of p-type (the fourth region), a second low-concentration p region 26x2 of p-type (the eighth region), a third low-concentration p region 26x3 of p-type, p + the first high-concentration p region 26y1 of p-type (the fifth region), p + the second high-concentration p region 26y2 of p-type (the ninth region), p ++ and the contact region 26z of p-type (the tenth region).

[0107] The source electrode 12 includes a contact electrode portion 12x and a diode electrode portion 12y. The contact electrode portion 12x and the diode electrode portion 12y are provided between the first gate electrode 18a and the second gate electrode 18b. The contact electrode portion 12x and the diode electrode portion 12y are provided between the second gate electrode 18b and the third gate electrode 18c.

[0108] The diode electrode portion 12y is located in the first direction of the contact electrode portion 12x.

[0109] n - The n-type drift region 24 includes the JBS region 24s. The JBS region 24s is in contact with the first surface F1. The JBS region 24s is surrounded by the body region 26.

[0110] The JBS region 24s is in contact with the diode electrode portion 12y of the source electrode 12. The JBS region 24s functions as the cathode region of the SBD.

[0111] In the drift region 24 surrounding the JBS region 24s, n + the first high-concentration n region 24z1 of n-type, n+ There is no second high-concentration n region 24z2 of this type. Also, in the body region 26 surrounding the JBS region 24s, there is no p + type first high-concentration p region 26y1, p + type second high-concentration p region 26y2 of this type.

[0112] Next, the operation and effects of the MOSFET 200 of the second embodiment will be described.

[0113] FIG. 10 is an equivalent circuit diagram of the semiconductor device of the second embodiment. In the MOSFET 200, a pn diode and an SBD are connected as built-in diodes in parallel with the transistor between the source electrode 12 and the drain electrode 14. The body region 26 is the anode region of the pn junction diode, and the drift region 24 is the cathode region of the pn junction diode. Also, the source electrode 12 is the anode electrode of the SBD, and the JBS region 24s is the cathode region of the SBD.

[0114] For example, consider the case where the MOSFET 200 is used as a switching element connected to an inductive load. When the MOSFET 200 is off, a voltage that is positive with respect to the drain electrode 14 may be applied to the source electrode 12 due to the inductive current caused by the inductive load. In this case, a forward current flows through the built-in diode. This state is also referred to as a reverse conduction state.

[0115] If the MOSFET does not include an SBD, a forward current flows through the pn junction diode. The pn junction diode operates in a bipolar manner. When a reflux current is passed through the pn junction diode operating in a bipolar manner, stacking defects grow in the silicon carbide layer due to the recombination energy of carriers. When stacking defects grow in the silicon carbide layer, there arises a problem that the on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

[0116] The MOSFET 200 is provided with an SBD. The forward voltage (Vf) at which a forward current starts to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, a forward current flows through the SBD prior to the pn junction diode.

[0117] The forward voltage (Vf) of the SBD is, for example, 1.0 V or more and less than 2.0 V. The forward voltage (Vf) of the pn junction diode is, for example, 2.0 V or more and 3.0 V or less.

[0118] The SBD operates in a unipolar manner. Therefore, even when a forward current flows, stacking defects do not grow in the silicon carbide layer 10 due to the carrier recombination energy. Accordingly, an increase in the on-resistance of the MOSFET 200 is suppressed. Thus, the reliability of the MOSFET 200 is improved.

[0119] Also, the MOSFET 200, similar to the MOSFET 100 of the first embodiment, has a pn junction formed by an n + -type first high-concentration n-region 24z1 and a p + -type first high-concentration p-region 26y1, and a pn junction formed by an n + -type second high-concentration n-region 24z2 and a p + -type second high-concentration p-region 26y2. Therefore, by the same action as the MOSFET 100, the avalanche breakdown voltage of the MOSFET 200 is improved.

[0120] Also, in the drift region 24 surrounding the JBS region 24s of the MOSFET 200, there is no n + -type first high-concentration n-region 24z1 and no n + -type second high-concentration n-region 24z2. Also, in the body region 26 surrounding the JBS region 24s, there is no p + -type first high-concentration p-region 26y1 and no p + -type second high-concentration p-region 26y2.

[0121] Therefore, near the JBS region 24s, avalanche breakdown is suppressed from occurring, and the flow of avalanche current is suppressed. Thus, degradation of the characteristics of the Schottky junction of the SBD due to heat generation can be suppressed.

[0122] In the first and second embodiments, the case of 4H-SiC as the crystal structure of SiC has been described as an example. However, the present invention can also be applied to devices using SiC having other crystal structures such as 6H-SiC and 3C-SiC. Also, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0123] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, it is also possible to make the first conductivity type p-type and the second conductivity type n-type.

[0124] In the first and second embodiments, aluminum (Al) has been exemplified as the p-type impurity. However, it is also possible to use boron (B). Also, nitrogen (N) and phosphorus (P) have been exemplified as the n-type impurities. However, it is also possible to apply arsenic (As), antimony (Sb), etc.

[0125] It is also possible to apply the present invention to an Insulated Gate Bipolar Transistor (IGBT).

[0126] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with those of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0127] 10 Silicon carbide layer 12 Source electrode (first electrode) 12x Contact electrode portion (first portion) 12y Diode electrode portion (second portion) 14 Drain electrode (second electrode) 16a First gate insulating layer 16b Second gate insulating layer 16c Third gate insulating layer 18a First gate electrode 18b Second gate electrode 18c Third gate electrode 24 Drift region (first silicon carbide region) 24x Lower region (first region) 24y1 First low-concentration n region (second region) 24y2 Second low-concentration n region (sixth region) 24z1 First high-concentration n region (third region) 24z2 Second high-concentration n region (seventh region) 24s JBS region (eleventh region) 26 Body region (second silicon carbide region) 26x1 First low-concentration p region (fourth region) 26x2 Second low-concentration p region (eighth region) 26y1 First high-concentration p region (fifth region) 26y2 Second high-concentration p region (ninth region) 26z Contact region (tenth region) 30 Source region (third silicon carbide region) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) F1 First surface F2 Second surface

Claims

1. A silicon carbide layer having a first surface and a second surface facing the first surface; A first silicon carbide region of a first conductivity type provided in the silicon carbide layer, including a first region, a second region, and a third region, wherein the second region is located between the first region and the first surface, the third region is located between the first region and the first surface, the first conductivity type impurity concentration of the second region is equal to or higher than the first conductivity type impurity concentration of the first region, and the first conductivity type impurity concentration of the third region is higher than that of the second region; a first silicon carbide region; A second silicon carbide region of a second conductivity type provided in the silicon carbide layer and located between the first silicon carbide region and the first surface, including a fourth region and a fifth region, wherein the fourth region is in contact with the second region, the fifth region is in contact with the third region, and the second conductivity type impurity concentration of the fifth region is higher than that of the fourth region; a second silicon carbide region; A third silicon carbide region of a first conductivity type provided in the silicon carbide layer and located between the second silicon carbide region and the first surface; A first gate electrode provided on the side of the first surface with respect to the silicon carbide layer, extending in a first direction parallel to the first surface, and facing the second silicon carbide region on the first surface; A second gate electrode provided on the side of the first surface with respect to the silicon carbide layer, extending in the first direction, provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region on the first surface; A first gate insulating layer provided between the second silicon carbide region and the first gate electrode; A second gate insulating layer provided between the second silicon carbide region and the second gate electrode; A first electrode provided on the side of the first surface with respect to the silicon carbide layer, including a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region; a first electrode; A second electrode provided on the side of the second surface with respect to the silicon carbide layer; A semiconductor device comprising the above components.

2. The first silicon carbide region further includes a sixth region and a seventh region. The sixth region is located between the first region and the first surface. The seventh region is located between the first region and the first surface. The concentration of the first conductivity type impurity in the sixth region is equal to or higher than the concentration of the first conductivity type impurity in the first region. The concentration of the first conductivity type impurity in the seventh region is higher than that in the second region. The sixth region is located between the third region and the seventh region. The second silicon carbide region further includes an eighth region and a ninth region. The eighth region is in contact with the sixth region. The ninth region is in contact with the seventh region. The concentration of the second conductivity type impurity in the ninth region is higher than the concentration of the second conductivity type impurity in the eighth region. The eighth region is located between the fifth region and the ninth region. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1 or claim 2, wherein the concentration of the first conductivity type impurity in the second region is higher than the concentration of the first conductivity type impurity in the first region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the concentration of the second conductivity type impurity in the fifth region is 1.5 times or more and 10 times or less the concentration of the second conductivity type impurity in the fourth region.

5. The semiconductor device according to any one of claims 1 to 4, wherein the fifth region is located in a direction from the first surface toward the second surface with respect to the first portion.

6. The fifth region is located in a third direction from the first surface toward the second surface with respect to the first portion. The semiconductor device according to claim 2, wherein the ninth region is located in the third direction with respect to the first portion.

7. The second silicon carbide region further includes a tenth region. The tenth region is located between the fifth region and the first portion. The concentration of the second conductivity type impurity in the tenth region is higher than the concentration of the second conductivity type impurity in the fifth region. The semiconductor device according to any one of claims 1 to 6.

8. The first silicon carbide region further includes an eleventh region in contact with the first surface. The first electrode further includes a second portion in contact with the eleventh region. The semiconductor device according to any one of claims 1 to 7.

9. The second portion is provided between the first gate electrode and the second gate electrode. The second portion is located in the first direction of the first portion. The semiconductor device according to claim 8.

Images