Method for manufacturing nitride semiconductor light-emitting element, and nitride semiconductor light-emitting element

Abstract

To provide a method for manufacturing a nitride semiconductor light-emitting element, and a nitride semiconductor light-emitting element, which can suppress the occurrence of trench defects in a light-emitting layer while suppressing the thickness of a barrier layer.SOLUTION: A method for manufacturing a nitride semiconductor light-emitting element includes a quantum well layer stacking step of stacking a GaInN quantum well layer 12A containing InN, and a barrier layer stacking step of stacking a barrier layer 12B on the surface of the GaInN quantum well layer 12A. The migration of raw material atoms in the barrier layer 12B in the barrier layer stacking step is smaller than the migration of raw material atoms in the GaInN quantum well layer 12A in the quantum well layer stacking step.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a nitride semiconductor light-emitting device and a nitride semiconductor light-emitting device.

Background Art

[0002] Patent Documents 1, 2, and Non-Patent Document 1 disclose a light-emitting layer having a so-called GaInN quantum well layer containing In (indium) in a quantum well layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] GaInN quantum wells can, in principle, cover emission wavelengths from near ultraviolet to near infrared and can be used as a light-emitting layer for LEDs, lasers, etc. To date, the wavelength range in which practical applications have advanced with a configuration using GaInN quantum wells is from 400 nm to 520 nm. In the region of longer wavelengths, it is necessary to increase the In composition of the GaInN quantum wells. In this case, the crystallinity of the GaInN quantum wells is significantly reduced by growing the GaInN quantum wells at a low growth temperature or by causing lattice mismatch with the GaN substrate serving as the substrate. Therefore, in order to form GaInN quantum wells that emit light at wavelengths of 500 nm or more, generally, ingenuity is required in crystal growth.

[0005] Here, when a GaInN / GaN quantum well structure that emits light in the region of wavelengths of 500 nm or more is formed, many crystal defects called trench defects are generated in the light-emitting layer, which leads to a decrease in light-emitting efficiency. Trench defects are defects in which, as crystal growth proceeds, grooves like annular pits are formed, and as crystal growth proceeds, the groove width grows. Therefore, in order to obtain high-quality GaInN quantum wells that emit light at wavelengths of 500 nm or more, it is important to suppress the generation of trench defects. Several methods have been proposed as methods for suppressing the generation of trench defects.

[0006] A practical method is not to devise the GaInN quantum well layer but to devise the barrier layer laminated directly thereon. Specifically, by raising the growth temperature of the barrier layer higher than that of the GaInN quantum well layer, the suppression of trench defects has been successful. Furthermore, when raising the growth temperature to laminate the barrier layer, in order to prevent In in the GaInN quantum well layer from desorbing from the surface of the GaInN quantum well layer, an AlGaN cap layer with a thickness of several nm is often laminated on the surface of the GaInN quantum well layer. Since the thickness of one atomic layer in crystal growth is about 0.3 nm, in order to completely cover the surface of the GaInN quantum well layer, it is necessary to laminate several atomic layers, and it is considered that a thickness of several nm, which is sufficiently thicker than at least 0.3 nm, is required.

[0007] As one of the factors causing trench defects, the presence of In-In direct bonds due to excessive supply of In has been reported. The act of supplying In excessively is necessary when forming a GaInN quantum well layer that emits light at a long wavelength, and the supply amount of In cannot be reduced. Therefore, after forming a GaInN quantum well layer with excessive supply of In, the growth temperature is increased to remove the In-In bonds existing on the outermost surface of the GaInN quantum well layer, thereby suppressing the occurrence of trench defects.

[0008] On the other hand, as another factor causing trench defects, the formation of stacking defects is also mentioned. Stacking defects correspond to the mixing of cubic components into a hexagonal crystal, and trench defects occur starting from the places where cubic components are mixed. Interestingly, stacking defects do not occur within the GaInN quantum well layer with high internal strain, but occur within the barrier layer when the barrier layer is stacked directly above it. Non-Patent Document 2 discloses the theoretical calculations by C. Stampfl et al. Specifically, Non-Patent Document 2 discloses that the formation energy of stacking defects is lower in GaN than in GaInN. From this, it is considered that stacking defects occur in the barrier layer due to the combined effects of the strain accumulated in the GaInN quantum well layer and the low formation energy in GaN, leading to the formation of trench defects.

[0009] We intend to mainly apply a GaInN quantum well layer that emits light at a wavelength of 500 nm or more to surface-emitting lasers. In that case, by reducing the thickness of the barrier layer, it is desired to realize a light-emitting layer in which as many GaInN quantum well layers as possible are arranged at the position of the antinode of the optical standing wave in the surface-emitting laser resonator. Thereby, the light confinement factor in the laser can be increased, and furthermore, it can be connected to the improvement of the carrier injection efficiency even as an LED. For example, in order to realize such a thin light-emitting layer, a barrier layer with a thickness of about 2 nm may be required, and trench defects must be suppressed with such a thin barrier layer.

[0010] The present invention has been made in view of the above-described conventional circumstances, and an object thereof is to provide a method for manufacturing a nitride semiconductor light-emitting device capable of suppressing the generation of trench defects in a light-emitting layer while suppressing the thickness of a barrier layer, and a nitride semiconductor light-emitting device.

Means for Solving the Problems

[0011] The method for manufacturing a nitride semiconductor light-emitting device according to the first invention includes: a quantum well layer stacking step of stacking a quantum well layer containing InN; a barrier layer stacking step of stacking a barrier layer on the surface of the quantum well layer; and the migration of the source atoms of the barrier layer in the barrier layer stacking step is smaller than the migration of the source atoms of the quantum well layer in the quantum well layer stacking step.

[0012] According to the configuration of the first invention, since the migration of the source atoms of the barrier layer in the barrier layer stacking step is made smaller than the migration of the source atoms of the quantum well layer in the quantum well layer stacking step, the movement of the source atoms in the barrier layer stacking step becomes slow, and thereby, it is possible to satisfactorily suppress the generation of trench defects that are likely to occur immediately after the execution of the barrier layer stacking step. Here, migration means that the source atoms forming the layer move around on the surface of the layer being crystal-grown.

[0013] The method for manufacturing a nitride semiconductor light-emitting device according to the second invention includes: a quantum well layer stacking step of stacking a quantum well layer containing InN; a first barrier layer stacking step of stacking a first barrier layer on the surface of the quantum well layer; a second barrier layer stacking step of stacking a second barrier layer on the surface of the first barrier layer; and the migration of the source atoms of the first barrier layer in the first barrier layer stacking step is smaller than the migration of the source atoms of the quantum well layer in the quantum well layer stacking step, The migration of the source atoms of the second barrier layer in the second barrier layer stacking process is greater than the migration of the source atoms of the first barrier layer in the first barrier layer stacking process.

[0014] According to the configuration of the second invention, since the migration of the source atoms of the first barrier layer in the first barrier layer stacking process is made smaller than the migration of the source atoms of the quantum well layer in the quantum well layer stacking process, the movement of the source atoms in the first barrier layer stacking process becomes slow. As a result, the generation of trench defects that easily occur immediately after starting the execution of the first barrier layer stacking process can be favorably suppressed. And since the migration of the source atoms of the second barrier layer in the second barrier layer stacking process is made greater than the migration of the source atoms of the first barrier layer in the first barrier layer stacking process, the second barrier layer can be stacked after enhancing the crystal quality of the second barrier layer compared to the first barrier layer.

[0015] The nitride semiconductor light-emitting device of the third invention includes a quantum well layer containing InN, a first barrier layer stacked on the quantum well layer, and a second barrier layer stacked on the first barrier layer, and includes a light-emitting layer having the above, the first barrier layer contains AlN and has a thickness in the stacking direction of 0.1 nm to 0.3 nm.

[0016] According to the configuration of the third invention, since the first barrier layer contains AlN, the movement of the source atoms of the first barrier layer becomes slow. As a result, the generation of trench defects that easily occur immediately after starting the execution of the first barrier layer stacking process can be favorably suppressed. And since the second barrier layer is stacked on the first barrier layer having a thickness in the stacking direction of 0.1 nm to 0.3 nm which is less than one atomic layer, while suppressing the thickness of the first barrier layer that suppresses the generation of trench defects as much as possible, it is easy to specialize the second barrier layer in enhancing the crystal quality.

Brief Description of the Drawings

[0017]

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Embodiments for Carrying Out the Invention

[0018] Preferred embodiments of the present invention will be described.

[0019] In the first invention, the growth temperature in the barrier layer stacking step can be lower than the growth temperature in the quantum well layer stacking step. According to this configuration, since the growth temperature in the barrier layer stacking step is made smaller than the growth temperature in the quantum well layer stacking step, the movement of the raw material atoms of the barrier layer can be made slower than in the quantum well layer stacking step, and migration can be reduced. As a result, the generation of trench defects that are likely to occur immediately after starting the execution of the barrier layer stacking step can be favorably suppressed.

[0020] In the first invention, the raw material atoms of the barrier layer may include AlN. According to this configuration, since the barrier layer contains AlN, the movement of the raw material atoms of the barrier layer is slowed down and migration is reduced, thereby enabling good suppression of the occurrence of trench defects that are likely to occur immediately after the start of the barrier layer stacking process. Further, when the growth temperature in the barrier layer stacking process is made lower than the growth temperature in the quantum well layer stacking process, the occurrence of trench defects can be suppressed even better.

[0021] In the second invention, the growth temperature in the first barrier layer stacking process may be lower than the growth temperature in the quantum well layer stacking process, and the growth temperature in the second barrier layer stacking process may be higher than the growth temperature in the first barrier layer stacking process. According to this configuration, since the growth temperature in the first barrier layer stacking process is made lower than the growth temperature in the quantum well layer stacking process, the movement of the raw material atoms of the first barrier layer can be slowed down and migration can be reduced compared to the quantum well layer stacking process, thereby enabling good suppression of the occurrence of trench defects that are likely to occur immediately after the start of the first barrier layer stacking process. And since the growth temperature in the second barrier layer stacking process is made higher than the growth temperature in the first barrier layer stacking process to increase migration, it is easier to stack a second barrier layer with higher crystal quality than the first barrier layer.

[0022] In the second invention, the thickness of the first barrier layer may be from 0.1 nm to 0.3 nm. According to this configuration, it is easy to leave room to increase the thickness of the second barrier layer with good crystal quality while making the thickness of the first barrier layer for the purpose of suppressing the occurrence of trench defects as thin as possible.

[0023] In the second invention, the source atoms of the first barrier layer may include AlN. According to this configuration, the movement of the source atoms of the first barrier layer is slowed down and the migration is reduced, thereby suppressing the occurrence of trench defects that are likely to occur immediately after starting the execution of the first barrier layer stacking process. Further, when the growth temperature in the first barrier layer stacking process is made lower than the growth temperature in the quantum well layer stacking process, the occurrence of trench defects can be suppressed more favorably.

[0024] In the second invention, the growth rate of the first barrier layer in the first barrier layer stacking process is faster than the growth rate of the quantum well layer in the quantum well layer stacking process, and the growth rate of the second barrier layer in the second barrier layer stacking process may be slower than the growth rate of the first barrier layer in the first barrier layer stacking process. According to this configuration, by making the growth rate in the first barrier layer stacking process faster than the growth rate in the quantum well layer stacking process, the first barrier layer can be stacked without giving a margin for the generation of trench defects. That is, the apparent migration is reduced. Then, by making the growth rate in the second barrier layer stacking process slower than the growth rate in the first barrier layer stacking process, the apparent migration is increased, and a second barrier layer having a higher crystal quality than the first barrier layer can be stacked.

[0025] In the third invention, the total thickness of the first barrier layer and the second barrier layer in the stacking direction may be 2 nm or less. According to this configuration, the thickness of the light-emitting layer in the stacking direction can be suppressed. For example, in the case of a surface-emitting laser, it becomes possible to concentrate and arrange the well layers at the position of the antinode of the optical standing wave, and it becomes possible to realize a surface-emitting laser that can oscillate more favorably. Further, in the case of an LED, it becomes possible to lead to an improvement in carrier injection efficiency.

[0026] <Examples 1 to 7> Conventional methods for suppressing the generation of trench defects mainly remove the direct bonding between In-In and are not considered to be applicable to stacking defects. Stacking defects occur in the GaN barrier layer where the formation energy is lower, that is, stacking defects are more likely to occur. Therefore, in order to suppress the stacking defects formed in the GaN barrier layer, we considered suppressing the energy given to the raw material atoms that migrate (move) on the crystal surface in accordance with its low formation energy. For example, we considered making the growth temperature in the GaN barrier layer even lower than that in the GaInN quantum well layer. However, since this idea is the opposite of the idea of removing the direct bonding between In-In described above, there is also a possibility that the trench defects will increase.

[0027] As a result of intensive studies, it was found that trench defects can be significantly reduced by lowering the migration at a thickness of 0.3 nm or less of the GaN barrier layer directly above the GaInN quantum well layer. Furthermore, it was also found that stacking the GaN barrier layer thicker than 0.3 nm would lead to a decrease in the light-emitting characteristics. Therefore, in order to form a GaInN / GaN quantum well light-emitting layer with high luminous efficiency while suppressing migration and thus suppressing stacking defects, that is, trench defects, it was found to be effective to introduce a layer with reduced migration into the GaN barrier layer less than 0.3 nm. Migration means that the raw material atoms forming the layer move around on the surface of the layer being crystal-grown. Therefore, lowering (suppressing) the migration means suppressing and slowing down the movement of the raw material atoms forming the layer during crystal growth.

[0028] [Verification of Migration Reduction] The above hypothesis is based on the idea that by suppressing migration during the growth of the GaN barrier layer, it may be possible to suppress stacking defects, i.e., trench defects. To verify this, among the growth conditions of the conventional barrier layer, as means for suppressing migration, low-temperature growth, high-speed growth, and using AlN instead of GaN for the crystal growth of the barrier layer were investigated. The results of these investigations will be described below.

[0029] Fig. 1 shows the structure of the fabricated sample. Here, a GaInN / GaN quantum well structure formed under the above three growth conditions (low-temperature growth, high-speed growth, using AlN instead of GaN for the barrier layer) is investigated on the surface of the undoped GaN layer 11. The structure of this sample is formed by crystal-growing and stacking an undoped GaN layer 11 on the surface of a GaN substrate 10 with the c-plane set as the surface by the MOCVD method (metalorganic chemical vapor deposition method). Note that a GaN template grown on a sapphire substrate or the like may be used instead of the GaN substrate 10.

[0030] Specifically, first, the GaN substrate 10 is set in the reactor of an MOCVD apparatus capable of executing the MOCVD method. Then, NH3 (ammonia), which is a raw material of N (nitrogen), and H2 (hydrogen), which is a carrier gas, are supplied into the reactor, and the temperature in the reactor is adjusted to set the temperature of the GaN substrate 10 to 1050 °C. The gas supplied into the reactor is not stopped until otherwise specified. Then, TMGa (trimethylgallium), which is a raw material of Ga (gallium), is supplied into the reactor, and an undoped GaN layer 11 with a thickness of 0.5 μm is stacked on the surface of the GaN substrate 10. Here, the vertical direction in Fig. 1 is the stacking direction.

[0031] Next, a quantum well layer stacking step of stacking a quantum well layer containing InN is performed. Specifically, a GaInN quantum well light-emitting layer 12, which is a light-emitting layer, is stacked on the surface of the undoped GaN layer 11. As the GaInN quantum well light-emitting layer 12, a 2-nm-thick GaInN quantum well layer 12A and a 2-nm-thick barrier layer 12B are stacked in three cycles. First, the GaInN quantum well layer 12A is stacked. Specifically, the supply of H2 and TMGa into the reactor is stopped. That is, the supply of gases of raw materials other than NH3 is stopped. Then, N2 (nitrogen) is supplied as a carrier gas into the reactor. Then, the temperature in the reactor is adjusted to lower the temperature of the GaN substrate 10 to 660°C. Then, TEGa (triethylgallium), which is a raw material of Ga, and TMIn (trimethylindium), which is a raw material of In (indium), are supplied, and a 2-nm-thick GaInN quantum well layer 12A, which is a quantum well layer, is stacked on the surface of the undoped GaN layer 11 and crystal growth is performed. The growth rate of the GaInN quantum well layer 12A is 0.6 nm / min.

[0032] Next, a barrier layer stacking step of stacking a barrier layer on the surface of the GaInN quantum well layer 12A is performed. In the barrier layer stacking step, the barrier layer 12B is stacked on the surface of the GaInN quantum well layer 12A while adopting various growth conditions in which migration is suppressed compared to the growth conditions of the GaInN quantum well layer 12A. In other words, in the barrier layer stacking step, the migration of the raw material atoms of the barrier layer 12B is made smaller than the migration of the raw material atoms of the GaInN quantum well layer 12A in the quantum well layer stacking step.

[0033] Specifically, as shown in Table 1 below, while the growth temperature of the above-described GaInN quantum well layer 12A is 660°C, the barrier layer 12B is formed at growth temperatures of 635°C, 610°C, and 580°C. That is, the growth temperature in the barrier layer stacking step is made lower than the growth temperature in the quantum well stacking step, and the barrier layer 12B is stacked on the surface of the GaInN quantum well layer 12A.

[0034] In addition, for the growth rate of the above-described GaInN quantum well layer 12A being 0.6 nm / min, the barrier layer 12B is formed at growth rates of 2.6 nm / min and 9.6 nm / min. Also, as a layer containing Al with lower migration than Ga of GaN, Al 0.4 Ga 0.6 N, and AlN are laminated on the surface of the GaInN quantum well layer 12A as the barrier layer 12B. That is, a barrier layer 12B containing AlN is laminated on the surface of the GaInN quantum well layer 12A as the source atoms.

[0035]

Table 1

[0036] Specifically, after stopping the supply of TEGa and TMIn into the reactor to terminate the growth of the GaInN quantum well layer 12A, the barrier layer 12B is crystallized and laminated on the surface of the GaInN quantum well layer 12A under each growth condition in Table 1. For example, when changing the growth temperature, after growing the GaInN quantum well layer 12A by crystal growth, the growth temperature is changed from 660 °C to each temperature (635 °C, 610 °C, 580 °C), and then the supply of TEGa is resumed to grow the barrier layer 12B at low temperature on the surface of the GaInN quantum well layer 12A. The sample in which the barrier layer 12B is crystallized at a growth temperature of 635 °C is Example 1. The sample in which the barrier layer 12B is crystallized at a growth temperature of 610 °C is Example 2. The sample in which the barrier layer 12B is crystallized at a growth temperature of 580 °C is Example 3.

[0037] When changing the growth rate, after growing the GaInN quantum well layer 12A by crystal growth, the supply amount of the Ga raw material into the reactor is increased to a desired value to grow the barrier layer 12B at high speed at each growth rate (2.6 nm / min, 9.6 nm / min). The sample in which the barrier layer 12B is crystallized at a growth rate of 2.6 nm / min is Example 4. The sample in which the barrier layer 12B is crystallized at a growth rate of 9.6 nm / min is Example 5.

[0038] Also, when forming the barrier layer 12B as a mixed crystal of GaN and AlN by adding AlN to the barrier layer 12B, by supplying TEGa and TMAl (trimethylaluminum) into the reactor, Al 0.4 Ga 0.6 The barrier layer 12B of N is grown on the surface of the GaInN quantum well layer 12A. The sample in which the barrier layer 12B is formed of a mixed crystal of GaN and AlN is Example 6.

[0039] And when forming the barrier layer 12B only of AlN, by supplying TMAl, which is an Al raw material, into the reactor instead of TEGa, the barrier layer 12B formed only of AlN is grown on the surface of the GaInN quantum well layer 12A. The sample in which the barrier layer 12B is formed only of AlN is Example 7.

[0040] Taking the grown GaInN quantum well layer 12A and the barrier layer 12B as one pair, three pairs of this pair are stacked. Thus, the GaInN quantum well light-emitting layer 12 of Examples 1 to 7 in which the migration of raw material atoms during the stacking of the barrier layer 12B is suppressed is formed. Then, when the growth of the barrier layer 12B of the third pair is completed, the supply of the Ga raw material and the Al raw material (TMAl) to the reactor is stopped, and the production of the sample is completed.

[0041] The sample in which the barrier layer 12B is crystal-grown under the conventional growth conditions (barrier layer material: GaN, growth temperature: 660°C, growth rate: 0.6 nm / min) is Comparative Example 1. Electron micrographs of the surfaces of Comparative Example 1 and the eight types of samples of Examples 1 to 7 are shown in FIG. 2. Samples of low-temperature growth (635°C, 610°C, 580°C) of Examples 1, 2, and 3, samples of high-speed growth (2.6 nm / min, 9.6 nm / min) of Examples 4 and 5, and growth containing Al of Examples 6 and 7 (Al 0.4 Ga 0.6In any of the samples of (N, AlN), it was found that the trench defect D observed on the surface was significantly suppressed compared to Comparative Example 1. That is, it was found that our hypothesis that suppressing the migration during the crystal growth of the barrier layer 12B suppresses the generation of the trench defect D was correct. In addition, in FIGS. 2(A), (E), (F), and (G), the region darker than the surroundings is the trench defect D.

[0042] To grasp the detailed trends under each growth condition, a graph is shown in FIG. 3 with each parameter (low-temperature growth, high-speed growth, AlN molar fraction) on the horizontal axis and the ratio of the area occupied by the trench defect D on the vertical axis. It is considered that the smaller the ratio of the area occupied by the trench defect D, the greater the effect of suppressing the trench defect D. From FIG. 3(A), it was found that the ratio of the area occupied by the trench defect D tends to be smaller as the growth temperature is lower. From FIG. 3(B), it was found that the ratio of the area occupied by the trench defect D tends to be smaller as the growth rate is higher. From FIG. 3(C), it was found that the ratio of the area occupied by the trench defect D tends to be smaller as the AlN molar fraction in the barrier layer 12B is larger.

[0043] Next, as the luminescence characteristics of these samples, the photoluminescence spectrum (He-Cd laser excitation) at room temperature was measured. As shown in FIG. 4(A), for the sample of Example 2 and the sample of Example 7, larger peaks appear compared to the sample of Comparative Example 1. On the other hand, as shown in FIG. 4(B), there is no significant difference in the peaks of the sample of Example 3 and the sample of Example 5 compared to the peak of the sample of Comparative Example 1. From these results, it was also found at the same time that just because the trench defect D could be suppressed, the optical characteristics were not necessarily improved. This is considered to be because if the migration is suppressed too much, point defects and the like occur in the barrier layer 12B itself, resulting in a decrease in crystal quality, which affects the optical characteristics.

[0044] [[ID=]11] Next, the effects in the above examples will be described.

[0045] The method for manufacturing a nitride semiconductor light-emitting device includes a quantum well layer stacking step of stacking a GaInN quantum well layer 12A containing InN, and a barrier layer stacking step of stacking a barrier layer 12B on the surface of the GaInN quantum well layer 12A. The migration of the source atoms of the barrier layer 12B in the barrier layer stacking step is smaller than the migration of the source atoms of the GaInN quantum well layer 12A in the quantum well layer stacking step. According to this configuration, since the migration of the source atoms of the barrier layer 12B in the barrier layer stacking step is made smaller than the migration of the source atoms of the GaInN quantum well layer 12A in the quantum well layer stacking step, the movement of the source atoms in the barrier layer stacking step becomes slower, and thereby, the occurrence of trench defects D that are likely to occur immediately after the start of the execution of the barrier layer stacking step can be suppressed well.

[0046] The growth temperature in the barrier layer stacking step is lower than the growth temperature in the quantum well layer stacking step. According to this configuration, since the growth temperature in the barrier layer stacking step is made lower than the growth temperature in the quantum well layer stacking step, the movement of the source atoms of the barrier layer 12B can be made slower than that in the quantum well layer stacking step, and the migration can be reduced, and thereby, the occurrence of trench defects D that are likely to occur immediately after the start of the execution of the barrier layer stacking step can be suppressed well.

[0047] The source atoms of the barrier layer 12B contain AlN. According to this configuration, since AlN is contained, the movement of the source atoms of the barrier layer 12B is made slower and the migration is reduced, and thereby, the occurrence of trench defects D that are likely to occur immediately after the start of the execution of the barrier layer stacking step can be suppressed well. Further, when the growth temperature in the barrier layer stacking step is made lower than the growth temperature in the quantum well layer stacking step, the occurrence of trench defects D can be suppressed more favorably.

[0048] In the first barrier layer stacking process, the growth rate of the barrier layer 12B is faster than the growth rate of the GaInN quantum well layer 12A in the quantum well layer stacking process. According to this configuration, the barrier layer 12B can be stacked without giving room for the generation of the trench defect D. That is, by making the growth rate of the barrier layer 12B faster than the growth rate of the GaInN quantum well layer 12A, the apparent migration during the stacking of the barrier layer 12B can be reduced.

[0049] <Examples 8 to 12> Here, in view of the possibility that the stacking defect, which is the cause of the trench defect D, is formed directly above the GaInN quantum well layer, a device was devised to divide the role of the barrier layer into two. That is, directly above the GaInN quantum well layer, the first barrier layer with as thin a thickness as possible is grown by crystal growth to suppress migration, and in the second barrier layer grown on the surface of the first barrier layer, a method is used to promote migration and stack crystals of as high quality as possible. Samples from Example 8 to Example 12 were fabricated and examined for this method.

[0050] [Thickness Dependence of the First Barrier Layer] Samples from Example 8 to Example 12 were fabricated according to the principle of suppressing the generation of the trench defect D by the first barrier layer that suppresses migration as described above and then improving the crystal quality of the second barrier layer to be stacked next. As shown in FIG. 5, the structure of the sample is the same as that of the samples in Examples 1 to 7 in that the GaN substrate 10, the undoped GaN layer 11, and the GaInN quantum well layer 12A are concerned. As the GaInN quantum well light-emitting layer 112 which is the light-emitting layer, a first barrier layer stacking process of stacking the first barrier layer 12C on the surface of the GaInN quantum well layer 12A formed by performing the quantum well layer stacking process and a second barrier layer stacking process of stacking the second barrier layer 12D on the surface of the first barrier layer 12C are performed, which is different from the samples in Examples 1 to 7. The growth conditions of the fabricated samples are as shown in Table 2 below, and the total thickness of the first barrier layer 12C and the second barrier layer 12D was adjusted to be 2 nm.

[0051]

Table 2

[0052] The method for preparing the samples of Example 8 to Example 12 is substantially the same as that of Example 1 to Example 7. Specifically, in Example 1 to Example 7, a barrier layer 12B having a single structure throughout the thickness direction was laminated on the surface of the GaInN quantum well layer 12A. On the other hand, in Example 8 to Example 12, as the barrier layer 112B laminated on the surface of the GaInN quantum well layer 12A, a first barrier layer 12C and a second barrier layer 12D were laminated in this order and crystal growth was performed.

[0053] The first barrier layer 12C in the samples of Example 8 to Example 12 corresponds to the barrier layer 12B in the samples of Example 1 to Example 7 whose thickness was adjusted to 0.1 nm or 0.3 nm. Specifically, the first barrier layer 12C of the samples of Example 8 and 9 is the one obtained by adjusting the thickness of the barrier layer 12B of the sample of Example 7 to a thickness of 0.1 nm or 0.3 nm. The first barrier layer 12C of the samples of Example 10 and 11 is the one obtained by adjusting the thickness of the barrier layer 12B of the sample of Example 2 to a thickness of 0.1 nm or 0.3 nm. And the first barrier layer 12C of the sample of Example 12 is the one having a thickness of 0.3 nm after combining the manufacturing methods of the barrier layer 12B of the samples of Example 2 and 7.

[0054] After growing the first barrier layer 12C, GaN is laminated and crystal-grown on its surface as the second barrier layer 12D at a growth temperature of 660°C and a growth rate of 0.6 nm / min, and the growth time is adjusted so that the total thickness becomes 2 nm. That is, the second barrier layer 12D of the samples of Examples 8 to 12 has the same growth conditions as the barrier layer of the sample of Comparative Example 1. Here, the growth conditions of the second barrier layer 12D may be any growth conditions that can promote (increase) migration more than the first barrier layer 12C. For example, the growth temperature of the second barrier layer 12D may be higher than that of the first barrier layer 12C, and if necessary, a growth temperature higher than 660°C (the growth temperature of the GaInN quantum well layer 12A) used here may be adopted. In other words, the migration of the source atoms of the second barrier layer 12D in the second barrier layer stacking step is made larger than the migration of the source atoms of the first barrier layer 12C in the first barrier layer stacking step.

[0055] In the sample of Example 8, the growth temperatures of the first barrier layer 12C and the second barrier layer 12D are 660°C, and the growth rate is 0.6 nm / min. The first barrier layer 12C is composed of only 0.1 nm thick AlN, and the second barrier layer 12D is composed of only 1.9 nm thick GaN.

[0056] In the sample of Example 9, the growth temperatures of the first barrier layer 12C and the second barrier layer 12D are 660°C, and the growth rate is 0.6 nm / min. The first barrier layer 12C is composed of only 0.3 nm thick AlN, and the second barrier layer 12D is composed of only 1.7 nm thick GaN. That is, the samples of Examples 8 and 9 contain AlN as the source atoms of the first barrier layer 12C.

[0057] In the sample of Example 10, the growth temperature of the first barrier layer 12C is 610 °C, and the growth temperature of the second barrier layer 12D is 660 °C. The growth rates of the first barrier layer 12C and the second barrier layer 12D are 0.6 nm / min. The first barrier layer 12C is composed of only 0.1 nm thick GaN, and the second barrier layer 12D is composed of only 1.9 nm thick GaN.

[0058] In the sample of Example 11, the growth temperature of the first barrier layer 12C is 610 °C, and the growth temperature of the second barrier layer 12D is 660 °C. The growth rates of the first barrier layer 12C and the second barrier layer 12D are 0.6 nm / min. The first barrier layer 12C is composed of only 0.3 nm thick GaN, and the second barrier layer 12D is composed of only 1.7 nm thick GaN.

[0059] In the sample of Example 12, the growth temperature of the first barrier layer 12C is 610 °C, and the growth temperature of the second barrier layer 12D is 660 °C. The growth rates of the first barrier layer 12C and the second barrier layer 12D are 0.6 nm / min. The first barrier layer 12C is composed of only 0.3 nm thick AlN, and the second barrier layer 12D is composed of only 1.7 nm thick GaN. That is, in the first barrier layer stacking process of the samples of Examples 10, 11, and 12, the growth temperature is lower than the growth temperature in the quantum well layer stacking process, and the growth temperature in the second barrier layer stacking process is higher than the growth temperature in the first barrier layer stacking process. Also, in the samples of Examples 8 to 12, the migration of the source atoms of the first barrier layer 12C in the first barrier layer stacking process is smaller than the migration of the source atoms of the GaInN quantum well layer 12A in the quantum well layer stacking process.

[0060] The samples of Examples 8 to 12 thus formed include a GaInN quantum well layer 12A containing InN, a first barrier layer 12C laminated on the GaInN quantum well layer 12A, and a second barrier layer 12D laminated on the first barrier layer 12C, and are provided with a GaInN quantum well light-emitting layer 112. And, the first barrier layer 12C of the samples of Examples 8, 9, and 12 contains AlN. Further, the thickness in the stacking direction of the first barrier layer 12C of the samples of Examples 8 to 12 is 0.1 nm and 0.3 nm. Further, the total thickness of the first barrier layer 12C and the second barrier layer 12D of the samples of Examples 8 to 12 is 2 nm.

[0061] An electron micrograph of the sample surface is shown in FIG. 6. By reducing the thickness of the barrier layer 112B, there are also samples (Examples 8 and 9) in which small trench defects D with a width of approximately 0.1 μm remain, but the occurrence of large trench defects D (see FIG. 2(A)) exceeding a width of 0.5 μm, such as in the sample of Comparative Example 1, is suppressed.

[0062] To grasp a more detailed trend, FIG. 7 shows a graph in which the layer thickness of each first barrier layer 12C is plotted on the horizontal axis and the ratio of the area occupied by the trench defects D is plotted on the vertical axis. FIG. 7(A) plots the results of the samples of Examples 7, 8, and 9 in which the first barrier layer 12C is formed of only AlN. FIG. 7(B) plots the results of the samples of Examples 2, 10, and 11 in which the first barrier layer 12C is formed of only GaN at a growth temperature of 610°C. In each graph, the ratio of the area occupied by the trench defects D with respect to the first barrier layer 12C changes so as to be convex downward, indicating that the effect of suppressing the trench defects D is large even for the layer with a thinner first barrier layer 12C. From FIGS. 7(A) and (B), it was found that the ratio of the area occupied by the trench defects D tends to decrease as the thickness of the first barrier layer 12C increases.

[0063] Next, as the luminescence characteristics of these samples, the results of measuring the photoluminescence spectra at room temperature are shown in FIGS. 8 and 9. FIG. 8 shows the results under weak excitation (He-Cd laser excitation) close to the state of operating as an LED. FIG. 9 shows the results under strong excitation (third harmonic of YAG laser) close to the state of operating as a laser. When the growth temperature of the first barrier layer 12C is adopted as 610° C. which is low-temperature growth (Examples 10, 11, and 12), it was found that the luminescence intensity under weak excitation (see FIG. 8) is greatly improved compared to Comparative Example 1. When AlN is adopted for the first barrier layer 12C (Examples 9 and 12), it was found that the luminescence intensity under strong excitation (see FIG. 9) is greatly improved compared to Comparative Example 1. And, it was found that the sample of Example 12 in which AlN was crystal-grown at 610° C. as the first barrier layer 12C has a greatly improved luminescence intensity compared to Comparative Example 1 under any excitation in FIGS. 8 and 9.

[0064] This time, samples with the thickness of the first barrier layer 12C set between 0.1 nm and 0.3 nm (for example, 0.2 nm, 0.25 nm, etc.) have not been fabricated. However, in this way, under the growth conditions that suppress migration, if a first barrier layer 12C with a thickness of 0.1 nm to 0.3 nm is laminated directly above the GaInN quantum well layer 12A, it is considered possible to form a GaInN quantum well light-emitting layer 112 (see FIG. 5) that emits light at a light-emitting wavelength of 500 nm or more with significantly improved luminescence characteristics. By the way, for GaN and AlN, the thickness of a single atomic layer is about 0.3 nm. From this, it is considered that the first barrier layer 12C is not a continuous film when the layer thickness is 0.3 nm or less. In other words, it can be said that even when the first barrier layer 12C is not a continuous film, there is an effect of significantly reducing trench defects.

[0065] In order to suppress the migration of the first barrier layer 12C, it is possible to select from a plurality of options such as using a layer containing Al for the first barrier layer 12C, performing crystal growth at a temperature lower than the growth temperature of the GaInN quantum well layer 12A, or performing crystal growth at a rate higher than the growth rate of the GaInN quantum well layer 12A. Further, depending on the application situation, the necessary growth conditions may be appropriately changed as in Examples 8 to 12.

[0066] Next, the effects of the above embodiments will be described.

[0067] The method for manufacturing a nitride semiconductor light-emitting device includes a quantum well layer stacking step of stacking a GaInN quantum well layer 12A containing InN, a first barrier layer stacking step of stacking a first barrier layer 12C on the surface of the GaInN quantum well layer 12A, and a second barrier layer stacking step of stacking a second barrier layer 12D on the surface of the first barrier layer 12C. The migration of the raw material atoms of the first barrier layer 12C in the first barrier layer stacking step is smaller than the migration of the raw material atoms of the GaInN quantum well layer 12A in the quantum well layer stacking step. The migration of the raw material atoms of the second barrier layer 12D in the second barrier layer stacking step is larger than the migration of the raw material atoms of the first barrier layer 12C in the first barrier layer stacking step.

[0068] According to this configuration, since the migration of the raw material atoms of the first barrier layer 12C in the first barrier layer stacking step is made smaller than the migration of the raw material atoms of the GaInN quantum well layer 12A in the quantum well layer stacking step, the movement of the raw material atoms in the first barrier layer stacking step becomes slow, and thereby, the generation of trench defects D that are likely to occur immediately after the start of the execution of the first barrier layer stacking step can be well suppressed. And since the migration of the raw material atoms of the second barrier layer 12D in the second barrier layer stacking step is made larger than the migration of the raw material atoms of the first barrier layer 12C in the first barrier layer stacking step, the second barrier layer 12D can be stacked after enhancing the crystal quality of the second barrier layer 12D compared to the first barrier layer 12C.

[0069] The growth temperature in the first barrier layer stacking process is lower than the growth temperature in the quantum well layer stacking process, and the growth temperature in the second barrier layer stacking process is higher than the growth temperature in the first barrier layer stacking process. According to this configuration, since the growth temperature in the first barrier layer stacking process is made lower than the growth temperature in the quantum well layer stacking process, the movement of the source atoms of the first barrier layer 12C can be made slower than in the quantum well layer stacking process, and migration can be reduced. As a result, the occurrence of trench defects D that are likely to occur immediately after starting the execution of the first barrier layer stacking process can be suppressed well. And since the growth temperature in the second barrier layer stacking process is made higher than the growth temperature in the first barrier layer stacking process to increase migration, it is easy to stack the second barrier layer 12D with higher crystal quality than the first barrier layer 12C.

[0070] The thickness of the first barrier layer 12C is from 0.1 nm to 0.3 nm. According to this configuration, while making the thickness of the first barrier layer 12C for the purpose of suppressing the occurrence of trench defects D as thin as possible, it is easy to leave room for increasing the thickness of the second barrier layer 12D with good crystal quality.

[0071] The source atoms of the first barrier layer 12C contain AlN. According to this configuration, the movement of the source atoms of the first barrier layer 12C can be made slower and migration can be reduced. As a result, the occurrence of trench defects D that are likely to occur immediately after starting the execution of the first barrier layer stacking process can be suppressed well. Also, when the growth temperature in the first barrier layer stacking process is made lower than the growth temperature in the quantum well layer stacking process, the occurrence of trench defects D can be suppressed better, and the light emission characteristics can be made better.

[0072] <Example 13> According to the present invention, since the thickness of the barrier layer is thinner than before and a high-quality green GaInN quantum well light-emitting layer can be formed, as an example of a nitride semiconductor light-emitting device utilizing this light-emitting layer, the green LED 100 of Example 13 was fabricated. When the thickness of the barrier layer 12B is thin, electrons and holes are easily injected into the same well layer, which contributes to an improvement in luminous efficiency. The green LED 100 of Example 13 was fabricated by the following procedure.

[0073] First, as shown in FIG. 10(A), an n-GaN layer 111 with a thickness of 1 μm is grown on the surface of the GaN substrate 10 at a growth temperature of 1050° C. using an MOCVD apparatus. Subsequently, a 2-nm-thick GaInN quantum well layer 12A and a 2-nm-thick barrier layer 112B are taken as one pair, and three pairs of this pair are stacked and crystal-grown. In the quantum well layer stacking process, the GaInN quantum well layer 12A is crystal-grown at 660° C. The barrier layer 112B is formed by stacking, in this order, a first barrier layer 12C formed of AlN with a thickness of 0.3 nm crystal-grown at 610° C. in the first barrier layer stacking process and a second barrier layer 12D formed of GaN with a thickness of 1.7 nm crystal-grown at 660° C. in the second barrier layer stacking process. Then, a GaN barrier layer 13 with a thickness of 8 nm is stacked on the surface of the uppermost first barrier layer 12C. Thereafter, a p-GaN 14 with a thickness of 100 nm and a p + -GaN contact layer 15 are crystal-grown at a growth temperature of 900° C. Thus, the epitaxial growth of the green LED 100 is completed.

[0074] To make a comparison with the green LED 100, a sample of Comparative Example 2 was also fabricated (see FIG. 10(B)) in which a 2-nm-thick GaInN quantum well layer 12A and a 2-nm-thick barrier layer 50 are taken as one pair, and three pairs of this pair are stacked and crystal-grown. The barrier layer 50 is formed by crystal-growing GaN at 660° C., and the present invention is not applied. For example, the growth conditions of the barrier layer 50 are the same as those of the barrier layer 12B of Comparative Example 1.

[0075] Next, using the completed wafers of Example 13 and Comparative Example 2, an element capable of current injection is formed. First, a mesa structure having a circular shape with a diameter of 40 μm is formed. Specifically, the mesa structure is formed using photolithography technology and dry etching technology. At this time, the mesa structure is p + -Cover the surface of the GaN contact layer 15 with a circular photoresist, and perform etching (about 200 nm) to a depth at which the surface of the n-GaN layer 111 is exposed around the circular photoresist. Subsequently, an ITO layer 16 with a diameter of 30 μm and a thickness of 20 nm is laminated on the center of the surface of the mesa structure (the surface of the p + -GaN contact layer 15). This ITO layer 16 with a diameter of 30 μm is the light-emitting part of the green LED 100. Finally, a p-pad electrode Pe and an n-contact electrode Ne are formed. The p-pad electrode Pe is formed on the surface of the ITO layer 16, and the n-contact electrode Ne is formed on the surface of the n-GaN layer 111 exposed by etching. The p-pad electrode Pe and the n-contact electrode Ne are composed of Cr / Ni / Au (10 nm / 20 nm / 370 nm). Thus, a green LED 100 having a GaInN quantum well light-emitting layer 112 that generates green light and a sample of Comparative Example 2 having a conventional GaInN quantum well light-emitting layer 30 are completed.

[0076] The emission spectra and current-light output characteristics of the green LED 100 of Example 13 and the sample of Comparative Example 2 are shown in FIG. 11. All samples emit light in the wavelength range of 500 nm or more (see FIG. 11(A)). On the other hand, it was found that the light output of the green LED 100 of Example 13 to which the present invention was applied was about three times higher than that of the sample of Comparative Example 2 (see FIG. 11(B)). This result is an example that clearly shows the effect of the present invention.

[0077] Next, the functions and effects in the above embodiments will be described.

[0078] The green LED 100 includes a GaInN quantum well layer 12A containing InN, a first barrier layer 12C laminated on the GaInN quantum well layer 12A, and a second barrier layer 12D laminated on the first barrier layer 12C, and is provided with a GaInN quantum well light-emitting layer 112. The first barrier layer 12C contains AlN and has a thickness of 0.3 nm in the lamination direction.

[0079] According to this configuration, since the first barrier layer 12C contains AlN, the movement of the raw material atoms in the first barrier layer 12C becomes slow, and thus, the generation of trench defects D that are likely to occur immediately after the start of the execution of the first barrier layer lamination process can be favorably suppressed. Then, since the second barrier layer 12D is laminated on the first barrier layer 12C having a thickness of about one atomic layer, i.e., 0.3 nm, in the lamination direction, it is easy to specialize the second barrier layer 12D in enhancing the crystal quality while suppressing the thickness of the first barrier layer 12C that suppresses the generation of trench defects as much as possible.

[0080] The total thickness of the first barrier layer 12C and the second barrier layer 12D in the lamination direction is 2 nm. According to this configuration, since the thickness of the GaInN quantum well light-emitting layer 112 in the lamination direction can be suppressed, for example, in the case of a surface-emitting laser, it becomes possible to concentrate and arrange the GaInN quantum well layer 12A at the position of the antinode of the optical standing wave, and it becomes possible to realize a surface-emitting laser that can oscillate better. Also, in the case of an LED, it becomes possible to lead to an improvement in the carrier injection efficiency.

[0081] <Example 14> The GaInN quantum well light-emitting layer according to the present invention is applicable not only to LEDs but also to surface-emitting lasers. Hereinafter, as Example 14, an example in which the present invention is applied to a surface-emitting laser is shown (not shown).

[0082] First, a first multi-layer film mirror in which 50 pairs of an AlInN layer and a GaN layer are stacked is crystal-grown on the surface of a GaN substrate using a MOCVD apparatus. At this time, in order to obtain an emission wavelength of 520 nm, the thickness of each of the AlInN layer and the GaN layer is set to a thickness corresponding to an optical distance of 1 / 4 wavelength of this wavelength (520 nm). Next, an n-GaN layer for passing an electric current is crystal-grown on the surface of the first multi-layer film mirror at 1050 °C. The thickness of the n-GaN layer is set to a thickness corresponding to an optical distance of 2.7 wavelengths. Subsequently, a GaInN underlayer with a thickness of several tens of nanometers is crystal-grown on the surface of the n-GaN layer at 800 °C for the purpose of suppressing point defects. The InN molar fraction of the GaInN underlayer is about 0.05. Thereby, the emission intensity of the GaInN quantum well emission layer laminated on the surface of the GaInN underlayer can be increased.

[0083] Subsequently, on the surface of the GaInN underlayer, a combination of a 2-nm-thick GaInN quantum well layer and a 2-nm-thick barrier layer is used as one pair of the GaInN quantum well emission layer, and this pair is repeated 3 times and crystal-grown. Here, the GaInN quantum well layer is crystal-grown at 660 °C. The barrier layer is formed by stacking a first barrier layer made of 0.3-nm-thick AlN crystal-grown at 610 °C and a second barrier layer made of 1.7-nm-thick GaN grown at 660 °C in this order. At this time, the peak wavelength of the GaInN quantum well emission layer is set to 515 nm so as to emit light at a slightly shorter wavelength than the designed emission wavelength of 520 nm. After stacking 3 pairs of the GaInN quantum well layer and the barrier layer, an 8-nm GaN barrier layer is crystal-grown on the surface of the uppermost barrier layer. At this time, the thickness of the GaInN underlayer is adjusted so that the second pair (that is, the GaInN quantum well layer located at the center in the stacking direction in the emission layer) is arranged at a position corresponding to an optical distance of 3 wavelengths as measured from the first multi-layer film mirror.

[0084] Subsequently, a 20-nm-thick p-AlGaN layer is crystal-grown and stacked on the surface of the GaN barrier layer at 950 °C. Thereafter, a p-GaN layer and a 10-nm-thick p + -GaN contact layer are crystal-grown at 950 °C, and p+ When the crystal growth of the -GaN contact layer is completed, the thickness of the p-GaN layer is adjusted so that it has a thickness corresponding to an optical distance of 3.7 wavelengths as measured from the first multilayer mirror. Thus, the epitaxial growth of the surface emitting laser is completed.

[0085] Next, using the completed wafer, an element capable of current injection is formed. First, a mesa structure having a circular shape with a diameter of 40 μm is formed. Specifically, the mesa structure is formed using photolithography technology and dry etching technology. At this time, the mesa structure covers the surface of the p + -GaN contact layer with a circular photoresist, and etching is performed to a depth at which the surface of the n-GaN layer is exposed around the circular photoresist.

[0086] Subsequently, a circular mask with a diameter of 8 μm is formed by resist at the center of the surface of the mesa structure (the surface of the p + -GaN contact layer). Then, using a dry etching apparatus, the p + -GaN contact layer in the region other than the circular mask is etched by about 5 nm. As a result, current flows through the opening with a diameter of 8 μm covered by the circular mask at the center of the surface of the mesa structure, and the flow of current is blocked in the other parts. Furthermore, due to this 5 nm step, the effective refractive index of the opening with a diameter of 8 μm increases, and a light confinement structure in the lateral direction is also formed. That is, by this etching, current constriction in the lateral direction and light confinement are simultaneously achieved.

[0087] After that, about 150 nm of SiO2 is laminated as an inter-electrode insulating layer covering the side walls of the mesa structure. Next, on the opening with a diameter of 8 μm and its periphery, patterning, film formation, and lift-off are repeated using photoresist to laminate a 20 nm ITO layer and a 32 nm Nb2O5 layer that will serve as the p-contact electrode. Through these processes, the thickness of the resonator with an optical distance of four wavelengths is completed. This opening with a diameter of 8 μm is the light-emitting part of the surface-emitting laser, and on the surface of the Nb2O5 layer above this opening, a second multilayer film mirror of 10 pairs of Nb2O5 / SiO2 of a dielectric with a high reflectivity of 99.9% or more is laminated. Finally, a p-pad electrode is formed on the outer peripheral edge of the surface of the ITO layer, and an n-contact electrode is formed on the surface of the n-GaN layer. The p-pad electrode and the n-contact electrode are composed of Cr / Ni / Au (10 nm / 20 nm / 370 nm). Thus, the surface-emitting laser of Example 14 having a GaInN quantum well light-emitting layer that generates green light with a wavelength of 520 nm is completed.

[0088] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is not limited to the embodiments disclosed this time, but is indicated by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included. (1) Different from the above embodiments, it is also conceivable to control migration by changing the growth pressure and the N2 supply amount in the reactor. (2) In Examples 8 to 12, the growth rate of the first barrier layer in the first barrier layer stacking step may be made faster than the growth rate of the quantum well layer in the quantum well layer stacking step, and the growth rate of the second barrier layer in the second barrier layer stacking step may be made slower than the growth rate of the first barrier layer in the first barrier layer stacking step. According to this configuration, by making the growth rate in the first barrier layer stacking step faster than the growth rate in the quantum well layer stacking step, the first barrier layer can be stacked without giving room for the generation of trench defects. That is, the apparent migration becomes smaller. Then, by making the growth rate in the second barrier layer stacking step slower than the growth rate in the first barrier layer stacking step, the apparent migration is increased, and the second barrier layer having a higher crystal quality than the first barrier layer can be stacked. (3) Different from Examples 8 to 14 above, the total thickness of the first barrier layer and the second barrier layer in the stacking direction may be 2 nm or less. Also, the thickness of the first barrier layer is preferably 0.1 nm or more, and the thickness of the first barrier layer is preferably 0.1 nm or more. For this reason, the total thickness of the first barrier layer and the second barrier layer in the stacking direction is preferably 0.2 nm or more. (4) In Examples 13 and 14, the thickness of the first barrier layer may be set to 0.1 nm to 0.3 nm.

Description of Reference Numerals

[0089] 12, 112… GaInN quantum well light emitting layer (light emitting layer) 12A… GaInN quantum well layer (quantum well layer) 12B, 112B… Barrier layer 12C… First barrier layer 12D… Second barrier layer 100… Green LED (nitride semiconductor light emitting device)

Claims

1. A quantum well layer stacking step of stacking a quantum well layer containing InN, A barrier layer stacking step of stacking a barrier layer on the surface of the quantum well layer, comprising: A method for manufacturing a nitride semiconductor light-emitting device, wherein the migration of the raw material atoms of the barrier layer in the barrier layer stacking step is smaller than the migration of the raw material atoms of the quantum well layer in the quantum well layer stacking step.

2. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1, wherein the growth temperature in the barrier layer stacking step is lower than the growth temperature in the quantum well layer stacking step.

3. The method for manufacturing a nitride semiconductor light-emitting device according to claim 1 or claim 2, wherein the raw material atoms of the barrier layer contain AlN.

4. A quantum well layer stacking step of stacking a quantum well layer containing InN, A first barrier layer stacking step of stacking a first barrier layer on the surface of the quantum well layer, A second barrier layer stacking step of stacking a second barrier layer on the surface of the first barrier layer, comprising: In the first barrier layer stacking step, the migration of the raw material atoms of the first barrier layer is smaller than the migration of the raw material atoms of the quantum well layer in the quantum well layer stacking step, A method for manufacturing a nitride semiconductor light-emitting device, wherein the migration of the raw material atoms of the second barrier layer in the second barrier layer stacking step is larger than the migration of the raw material atoms of the first barrier layer in the first barrier layer stacking step.

5. In the first barrier layer stacking step, the growth temperature is lower than the growth temperature in the quantum well layer stacking step, The method for manufacturing a nitride semiconductor light-emitting device according to claim 4, wherein the growth temperature in the second barrier layer stacking step is higher than the growth temperature in the first barrier layer stacking step.

6. The method for manufacturing a nitride semiconductor light-emitting device according to claim 4 or claim 5, wherein the thickness of the first barrier layer is from 0.1 nm to 0.3 nm.

7. The method for manufacturing a nitride semiconductor light-emitting device according to claim 4 or claim 5, wherein the raw material atoms of the first barrier layer contain AlN.

8. The method for manufacturing a nitride semiconductor light-emitting device according to claim 7, wherein the thickness of the first barrier layer is from 0.1 nm to 0.3 nm.

9. In the first barrier layer stacking step, the growth rate of the first barrier layer is faster than the growth rate of the quantum well layer in the quantum well layer stacking step, The manufacturing method of a nitride semiconductor light-emitting device according to claim 4, wherein the growth rate of the second barrier layer in the second barrier layer stacking step is slower than the growth rate of the first barrier layer in the first barrier layer stacking step.

10. A quantum well layer containing InN, A first barrier layer stacked on the quantum well layer, A second barrier layer stacked on the first barrier layer, A light-emitting layer having, The first barrier layer contains AlN and has a thickness in the stacking direction of 0.1 nm to 0.3 nm. A nitride semiconductor light-emitting device.

11. The nitride semiconductor light-emitting device according to claim 10, wherein the total thickness of the first barrier layer and the second barrier layer in the stacking direction is 2 nm or less.

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