Digital signal processing device

Abstract

To provide a digital signal processing device capable of improving output characteristics of a DA conversion unit.SOLUTION: A digital signal processing device 1A comprises: an interpolation data calculation part 124 that calculates a third value, which is a value of an interpolation digital signal Sii[N] interpolated between a first digital signal D1[N] having a first value and a second digital signal D2[N] having a second value and input after the first digital signal D1[N], as an average value of the first value and the second value; and an interpolation timing determination part 112 that determines an interpolation timing TGi for interpolating the interpolation digital signal Sii[N] based on the first value, the second value, and the third value, and a value of a plurality of third digital signals D3[N]j input in a period between the first digital signal D1[N] and the second digital signal D2[N].SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present invention relates to a digital signal processing device that processes digital signals used in digital-to-analog conversion. [Background technology]

[0002] A digital-to-analog converter (DAC) that converts digital signals to analog signals attenuates high-frequency components of the analog output signal, resulting in degraded frequency characteristics, due to an aperture effect caused by zero-order hold during DA conversion. A known technique for improving the frequency characteristics of such DAC output is to linearly interpolate and oversample input data. For example, a known technique for an analog signal synthesis device including a DAC is to perform linear interpolation by inserting the average value of two consecutive input sampling points into the midpoint between the two sampling points, thereby oversampling the input data by two times and outputting it (see, for example, Patent Document 1). Using a DAC that oversamples input data in this way can suppress the attenuation of high-frequency components of the analog output signal and improve frequency characteristics. Furthermore, by doubling the sampling frequency, the frequency of aliasing components is also doubled, shifting the aliasing to a higher frequency range. This facilitates the removal of aliasing components using a downstream low-pass filter (LPF). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 1-261909 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional linear interpolation, the average value of two consecutive points is interpolated at the midpoint between the two points, resulting in the interpolated data having a value obtained by averaging the data before and after the two points. In this linear interpolation, if there is a large error between the original data value and the interpolated data value, the gain of the high-frequency component of the DAC output decreases.

[0005] An object of the present invention is to provide a digital signal processing device capable of improving the output characteristics of a DA conversion section. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention provides a digital signal processing device that processes digital signals used in digital-to-analog conversion, and includes: a calculation unit that calculates a third value, which is the value of an interpolated digital signal to be interpolated between a first digital signal having a first value and a second digital signal having a second value and input after the first digital signal, as an average of the first value and the second value; a determination unit that determines an interpolation timing for interpolating the interpolated digital signal based on the first value, the second value, the third value, and values of each of a plurality of third digital signals input in a period between the first digital signal and the second digital signal; and an interpolation unit that interpolates the interpolated digital signal at the interpolation timing determined by the determination unit. [Effects of the Invention]

[0007] According to one aspect of the present invention, it is possible to improve the output characteristics of a DA conversion section. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram for explaining conventional oversampling using linear interpolation. [Figure 2] 1 is a diagram for explaining the principle of oversampling in digital signal processing according to the present invention; [Figure 3]FIG. 1 is a diagram for explaining conventional DA conversion, showing an example of an input analog signal waveform, an output signal waveform obtained by DA conversion using oversampling with linear interpolation, and an output signal waveform obtained by DA conversion without using oversampling. [Figure 4] FIG. 1 is a diagram for explaining digital signal processing according to the present invention, showing an example of an input analog signal waveform, an output signal waveform obtained by DA conversion using oversampling in the present invention, and an output signal waveform obtained by DA conversion without using conventional oversampling. [Figure 5] FIG. 5 is a diagram for explaining digital signal processing according to the present invention, showing an example of the gain frequency characteristics of a DA conversion unit calculated using the signal waveforms shown in FIGS. 3 and 4. [Figure 6] FIG. 5 is a diagram for explaining digital signal processing according to the present invention, showing an example of the distortion frequency characteristics of a DA conversion unit calculated using the signal waveforms shown in FIGS. 3 and 4. [Figure 7] FIG. 10 is a diagram for explaining digital signal processing according to the present invention, showing an example of the gain frequency characteristics of the DA conversion unit when the value of the interpolated digital signal does not match the value of the original analog signal. [Figure 8] FIG. 8 is a diagram showing the gain frequency characteristics shown in FIG. 7 with the scales of the vertical and horizontal axes changed. [Figure 9] FIG. 10 is a diagram for explaining digital signal processing according to the present invention, showing an example of the gain frequency characteristics of the DA conversion section when the value of the interpolated digital signal matches the value of the original analog signal. [Figure 10] 10 is a diagram showing the gain frequency characteristics shown in FIG. 9 with the scales of the vertical and horizontal axes changed. [Figure 11] FIG. 1 is a diagram for explaining digital signal processing according to the present invention, showing an example of frequency band characteristics of a DA conversion section using oversampling in digital signal processing according to the present invention. [Figure 12] 12 is a diagram for explaining digital signal processing according to the present invention, showing the frequency band characteristics shown in FIG. 11 with the scales of the vertical and horizontal axes changed. FIG. [Figure 13] 1 is a block diagram showing a schematic configuration of a digital signal processing device according to a first embodiment of the present invention. [Figure 14] FIG. 2 is a diagram schematically showing an example of an input digital signal input to a digital signal processing unit provided in the digital signal processing according to the first embodiment of the present invention. [Figure 15] 1 is a block diagram showing a schematic configuration of a digital-to-analog conversion processing unit provided in a digital signal processing device according to a first embodiment of the present invention. [Figure 16] 4 is a timing chart showing an example of the operation of the digital signal processing device according to the first embodiment of the present invention. [Figure 17] 5 is a flowchart showing an example of the flow of processing for determining interpolation timing in the digital signal processing device according to the first embodiment of the present invention. [Figure 18] FIG. 10 is a diagram for explaining a digital signal processing device according to a modified example of the first embodiment of the present invention, and is a diagram for explaining aliasing components that occur in an output signal. [Figure 19] FIG. 10 is a block diagram showing a schematic configuration of a digital signal processing device according to a second embodiment of the present invention. [Figure 20] FIG. 10 is a diagram schematically showing an example of an input digital signal input to a digital signal processing unit provided in the digital signal processing according to the second embodiment of the present invention. [Figure 21] FIG. 10 is a block diagram showing a schematic configuration of a digital signal processing device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Principles, actions, and effects of digital signal processing according to the present invention] 1-1. Principle of digital signal processing according to the present invention The principle of digital signal processing according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram illustrating conventional oversampling using linear interpolation. FIG. 2 is a diagram illustrating the principle of oversampling in digital signal processing according to the present invention. The upper parts of each of FIGS. 1 and 2 illustrate the original analog signal SOA (i.e., the input analog signal), sampled digital signals Ss1, Ss2, Ss3, Ss4, and Ss5, and interpolated digital signals Sic1, Sic2, Sic3, and Sic4. The lower parts of each of FIGS. 1 and 2 illustrate the data selection clock signal LRCK. The data selection clock signal LRCK is a clock signal for selecting the sampled digital signals Ss1, Ss2, Ss3, Ss4, and Ss5 and the interpolated digital signals Sic1, Sic2, Sic3, and Sic4 and outputting them to a digital-to-analog converter (not shown).

[0010] The original analog signal SOA is the analog signal to be reproduced by the digital signal processing according to the present invention. The sampled digital signal is obtained by sampling the original analog signal SOA and performing analog-to-digital conversion, and is the digital signal to be processed by the digital signal processing according to the present invention. Hereinafter, the sampled digital signals Ss1, Ss2, Ss3, Ss4, and Ss5 may be abbreviated as "sampled digital signals Ss1 to Ss5," and the interpolated digital signals Sic1, Sic2, Sic3, and Sic4 may be abbreviated as "interpolated digital signals Sic1 to Sic4."

[0011] As shown in FIG. 1, in conventional oversampling using linear interpolation, the interpolation timing of the interpolated digital signals Sic1 to Sic4 is fixed to the timing of the midpoint between two consecutive sampled digital signals Ss1 to Ss5. Therefore, the value of each of the interpolated digital signals Sic1 to Sic4 is the average value of two consecutive sampled digital signals Ss1 to Ss5. Specifically, the value of the interpolated digital signal Sic1 is the average value of the sampled digital signals Ss1 and Ss2. The value of the interpolated digital signal Sic2 is the average value of the sampled digital signals Ss2 and Ss3. The value of the interpolated digital signal Sic3 is the average value of the sampled digital signals Ss3 and Ss4. The value of the interpolated digital signal Sic4 is the average value of the sampled digital signals Ss4 and Ss5.

[0012] Thus, in linear interpolation, the value of each of interpolated digital signals Sic1 to Sic4 is determined independently of the value of analog signal SOA at the timing (interpolation timing) when each of interpolated digital signals Sic1 to Sic4 is interpolated. Therefore, errors Er1, Er2, Er3, and Er4 may occur between the value of each of interpolated digital signals Sic1 to Sic4 and the value of analog signal SOA. In the example shown in FIG. 1 , the error Er1 between interpolated digital signal Sic1 and analog signal SOA and the error Er4 between interpolated digital signal Sic4 and analog signal SOA are approximately the same, while the error Er2 between interpolated digital signal Sic2 and analog signal SOA and the error Er3 between interpolated digital signal Sic3 and analog signal SOA are approximately the same. Furthermore, errors Er1 and Er4 are larger than errors Er2 and Er3.

[0013] Because the sampled digital signals Ss1-Ss5 and the interpolated digital signals Sic1-Sic4 are set alternately at equal intervals, the data selection clock signal LRCK has a signal waveform with a 50% duty cycle. The data selection clock signal LRCK outputs the sampled digital signals Ss1-Ss5 to a DA converter, for example, at the timing of the falling edges, and outputs the interpolated digital signals Sic1-Sic4 to the DA converter, for example, at the timing of the rising edges. The DA converter converts the input sampled digital signals Ss1-Ss5 and interpolated digital signals Sic1-Sic4 into analog signals. As will be described in detail later, the DA converter also converts the interpolated digital signals Sic1-Sic4, which have errors Er1, Er2, Er3, and Er4 between them and the analog signal SOA, and therefore the gain of the high-frequency components of the output signal decreases depending on the magnitude of the errors Er1, Er2, Er3, and Er4.

[0014] The digital signal processing according to the present invention relates to the processing of digital signals used in digital-to-analog conversion, and determines the interpolation timing for inserting an interpolated digital signal having the average value of each of two sampled digital signals input in time series to be the timing at which the average value is closest to the value of the original analog signal.

[0015] Specifically, as shown in Fig. 2, the timing of digital signal Sav1, which has the average value of the values of two consecutive sampled digital signals Ss1 and Ss2 obtained by conventional linear interpolation, corresponds to the midpoint between the two sampling points of period P12 of sampled digital signals Ss1 and Ss2. Therefore, in digital signal processing according to the present invention, the timing of digital signal Sav1 is corrected, as indicated by arrow Y1 in Fig. 2, so that digital signal Sav1 is closest to (coincides with) the value of original analog signal SOA during period P12 while maintaining the average value. This determines interpolation timing TG1 for interpolating interpolated digital signal Sii1.

[0016] The timing of digital signal Sav2, which has the average value of the values of two consecutive sampled digital signals Ss2 and Ss3, corresponds to the midpoint of period P23 between two sampling points of sampled digital signals Ss2 and Ss3. In digital signal processing according to the present invention, the timing of digital signal Sav2 is corrected, as indicated by arrow Y2 in Fig. 2, so that digital signal Sav2 is closest to (matches in Fig. 2) the value of original analog signal SOA during period P23 while maintaining the average value. This determines interpolation timing TG2 for interpolating interpolated digital signal Sii2.

[0017] The timing of the digital signal Sav3, which has the average value of the values of two consecutive sampled digital signals Ss3 and Ss4, is corrected in the same manner as for the digital signal Sav1, as indicated by the arrow Y3 in Fig. 2. This determines the interpolation timing TG3 for interpolating the interpolated digital signal Sii3.

[0018] The timing of digital signal Sav4, which has the average value of the values of two consecutive sampled digital signals Ss4 and Ss5, is corrected in the same manner as for digital signal Sav1, as indicated by arrow Y4 in Fig. 2. This determines interpolation timing TG4 for interpolating interpolated digital signal Sii4. The method for determining the interpolation timings TG1, TG2, TG3, and TG4 will be described in detail later.

[0019] 1-2. Functions and Effects of Digital Signal Processing According to the Present Invention The functions and effects of the digital signal processing according to the present invention will be described with reference to Figs. 3 to 12. Fig. 3 shows an example of an original analog signal waveform, an output signal waveform when the analog signal is DA converted using conventional oversampling with linear interpolation, and an output signal waveform when the analog signal is DA converted without oversampling. Fig. 4 shows an example of an original analog signal waveform, an output signal waveform when the analog signal is DA converted using oversampling in the digital signal processing according to the present invention, and an output signal waveform when the analog signal is DA converted without oversampling. In Figs. 3 and 4, the sampling rate of the original analog signal is set lower than the actual sampling rate to facilitate understanding.

[0020] The horizontal axis of the graphs shown in Figures 3 and 4 represents time, and the vertical axis of the graphs represents the amplitude of the original analog signal SOA (i.e., the input analog signal). In Figures 3 and 4, the sampling timing of the analog signal SOA is shown by a black circle, and the interpolation timing of the interpolated digital signal is shown by a white circle. In Figures 3 and 4, the output signal Son when DA conversion is performed without oversampling using linear interpolation is shown by a dashed line connecting the black circles. In Figure 3, the output signal Soc when DA conversion is performed using conventional oversampling using linear interpolation is shown by a solid line connecting the black and white circles. In Figure 4, the output signal Soi when DA conversion is performed using oversampling in digital signal processing according to the present invention is shown by a solid line connecting the black and white circles. The analog signal SOA has a sine wave signal waveform with a frequency of, for example, 6 kHz.

[0021] As shown in Figures 3 and 4, the DA-converted output signals Son, Soc, and Soi all become stepped signals, regardless of whether oversampling is performed or not. As explained using Figure 1, in conventional oversampling using linear interpolation, the interpolated digital signal is determined independently of the value of the original analog signal SOA at the sampling timing, so as shown in Figure 3, an error E may occur between the output signal Soc and the analog signal SOA at the interpolation timing of the interpolated digital signal. Note that in Figure 3, the error E is shown in only one location.

[0022] In contrast, as explained using Fig. 2, in the oversampling in the digital signal processing according to the present invention, the interpolation timing of the interpolated digital signal is determined to be the timing at which the value of the interpolated digital signal is closest to the value of the original analog signal SOA. Therefore, as shown in Fig. 4, the error between the analog signal SOA and the output signal Soi at the interpolation timing of the interpolated digital signal is reduced compared to the output signal Soc (see Fig. 3). As a result, the digital signal processing according to the present invention can improve the output characteristics after DA conversion compared to conventional digital signal processing.

[0023] Fig. 5 is a diagram showing an example of the gain frequency characteristic of a DA conversion unit (not shown) calculated using the signal waveforms shown in Figs. 3 and 4. Fig. 6 is a diagram showing an example of the distortion frequency characteristic of a DA conversion unit calculated using the signal waveforms shown in Figs. 3 and 4. The gain shown in Fig. 5 and the distortion shown in Fig. 6 are calculated, for example, by performing Fourier series expansion on the output waveform when a sine wave is input to the DA conversion unit to calculate the spectral distribution. The horizontal axis of the graphs shown in Figs. 5 and 6 represents frequency (Hz). The vertical axis of the graph shown in Fig. 5 represents gain (dB). The vertical axis of the graph shown in Fig. 6 represents distortion rate (%).

[0024] In FIG. 5, the gain frequency characteristic Cgfn when no oversampling is used (i.e., the output signal Son shown in FIGS. 3 and 4) is shown by a dashed line connecting diamonds. In FIG. 5, the gain frequency characteristic Cgfo when oversampling is used, in which the value of the original analog signal SOA is applied to the value of the interpolated digital signal, is shown by a dotted line connecting circles. For ease of explanation, the output signal when oversampling is used, in which the value of the original analog signal SOA is applied to the value of the interpolated digital signal, may be referred to as the "output signal Soo." In FIG. 5, the gain frequency characteristic Cgfc when conventional oversampling using linear interpolation is used (i.e., the output signal Soc shown in FIG. 3) is shown by a solid line connecting squares. In FIG. 5, the gain frequency characteristic Cgfi when oversampling in the digital signal processing according to the present invention is used (i.e., the output signal Soi shown in FIG. 4) is shown by a solid line connecting triangles.

[0025] In Fig. 6, the distortion frequency characteristic Cdfn of the output signal Son is shown by a dashed line connecting diamonds. In Fig. 6, the distortion frequency characteristic Cdfo of the output signal Soo is shown by a dotted line connecting circles. In Fig. 6, the distortion frequency characteristic Cdfc of the output signal Soc is shown by a solid line connecting squares. In Fig. 6, the distortion frequency characteristic Cdfi of the output signal Soi is shown by a solid line connecting triangles.

[0026] As described above, the output signal Soc is obtained by DA-converting a sampled digital signal having the same value as the original analog signal SOA and an interpolated digital signal determined independently of the value of the original analog signal SOA at the interpolation timing. Meanwhile, the output signal Soi is obtained by DA-converting a sampled digital signal having the same value as the original analog signal SOA and an interpolated digital signal with corrected interpolation timing. The interpolated digital signal is a signal having the average value of two consecutive sampled digital signals, interpolated at the timing when this average value is closest to the value of the original analog signal SOA. The output signal Son is obtained by DA-converting a sampled digital signal having the same value as the original analog signal SOA without linear interpolation. Furthermore, the output signal Soo is obtained by DA-converting a sampled digital signal having the same value as the original analog signal SOA and an interpolated digital signal having the same value as the original analog signal SOA.

[0027] For this reason, among the output signals Soc, Soi, Son, and Soo, there is a possibility that the output signal Soc is obtained by DA conversion of a digital signal having a large error with respect to the analog signal SOA. As a result, as shown in Fig. 5, the output signal Soc has a gain frequency characteristic Cgfc in which the gain is reduced on the high-frequency side compared to the gain frequency characteristics Cgfi, Cgfn, and Cgfo of the output signals Soi, Son, and Soo.

[0028] When oversampling is performed using the value of the original analog signal SOA for the value of the interpolated digital signal, it is equivalent to performing oversampling at a higher sampling frequency. In other words, the output signal Soo is a signal obtained by sampling the analog signal SOA at a higher sampling frequency than the output signal Son and then performing DA conversion. In this example, the output signal Soo is a signal obtained by sampling the analog signal SOA at a frequency twice the sampling frequency of the output signal Son and then performing DA conversion (see FIGS. 3 and 4). Therefore, the gain frequency characteristic Cgfo of the output signal Soo has improved gain in the high frequency range compared to the gain frequency characteristic Cgfn of the output signal Son.

[0029] Like the output signal Soo, the output signal Soi is a signal that has been sampled and digitally converted from the analog signal SOA at twice the sampling frequency of the output signal Son, but the interpolated digital signal may not match the analog signal SOA. For this reason, the gain frequency characteristic Cgfi of the output signal Soi does not improve in the high frequency range as much as the gain frequency characteristic Cgfo of the output signal Soo.

[0030] The output signals Soc, Soi, and Soo are obtained by DA-converting not only the sampled digital signal but also the interpolated digital signal. On the other hand, the output signal Son is obtained by DA-converting only the sampled digital signal. Therefore, the output signal Son has a lower reproducibility of the sine wave, which is the signal waveform of the analog signal SOA, compared to the output signals Soc, Soi, and Soo. As a result, as shown in Figure 6, the distortion frequency characteristic Cdfn of the output signal Son has a higher distortion rate with respect to frequency compared to the distortion frequency characteristics Cdfc, Cdfi, and Cdfo of the output signals Soc, Soi, and Soo.

[0031] Although the output signal Soc may be obtained by DA conversion of an interpolated digital signal that has a larger error with respect to the analog signal SOA than the output signals Soi and Soo, the use of the interpolated digital signal results in a distortion rate equivalent to that of the output signals Soi and Soo.

[0032] In this way, when the original analog signal is converted to digital audio using conventional oversampling with linear interpolation, the distortion rate is improved by inserting an interpolated digital signal. However, conventional oversampling with linear interpolation can result in a large error between the value of the original analog signal and the value of the interpolated digital signal, which can cause a problem of reduced gain in the high-frequency band.

[0033] In contrast, when an original analog signal is subjected to DA conversion using oversampling in digital signal processing according to the present invention, the distortion rate is improved by interpolating an interpolated digital signal. Furthermore, oversampling in digital signal processing according to the present invention can reduce the error between the value of the interpolated digital signal and the value of the original analog signal compared to oversampling using conventional linear interpolation. Furthermore, oversampling in digital signal processing according to the present invention can sometimes result in the value of the original analog signal and the value of the interpolated digital signal matching. Therefore, oversampling in digital signal processing according to the present invention can suppress gain reduction in the high-frequency band. As a result, oversampling of digital signals according to the present invention broadens the usable frequency band compared to conventional oversampling using linear interpolation.

[0034] Fig. 7 is a diagram showing an example of the frequency-gain characteristics of the output in DA conversion when the value of the interpolated digital signal does not match the value of the original analog signal in 2x oversampling using linear interpolation (average value interpolation). Fig. 8 is a diagram showing each characteristic by widening the scale of the vertical axis and narrowing the scale of the horizontal axis of the graph shown in Fig. 7. In Figs. 7 and 8, the frequency band FBa of the original analog signal is shown by a dashed line, the frequency band FBc of the interpolated digital signal is shown by a dashed-dotted line, and the frequency band FBo of the output signal output from a DA conversion unit (not shown) is shown by a solid line.

[0035] Because the frequency band of a square wave is a sinc function, the smaller the pulse width of the square wave, the wider the frequency band. For this reason, the output band can be extended by increasing the sampling frequency of the DA conversion unit and shortening the hold time of the output square wave. In other words, by increasing the sampling frequency, the frequency band of the output signal from the DA conversion unit also increases.

[0036] Because 2x oversampling doubles the sampling frequency, the frequency band FBa of the original analog signal also doubles. The interpolated digital signal is obtained by averaging two consecutive sampled digital signals. For this reason, as shown in Figure 7, the frequency band FBc of the interpolated digital signal drops in the high frequencies. The frequency band FBc of the interpolated digital signal drops to half the sampling frequency, canceling out the effect of oversampling. As a result, although the sampling frequency is doubled in the DA conversion unit, the frequency band FBo of the output signal, which is the combination of the frequency band of the sampled signal input to the DA conversion unit (i.e., the frequency band FBa of the original analog signal) and the frequency band FBc of the interpolated digital signal, also drops.

[0037] The greater the error between the value of the interpolated digital signal and the value of the original analog signal, the lower the gain in the high frequency band. As described above, by interpolating the interpolated digital signal, waveform distortion of the output signal can be reduced. However, since the interpolated digital signal has a value obtained by averaging the values of two consecutive sampled digital signals and has a value unrelated to the interpolation timing, the greater the error between the original analog signal and the frequency band FBc, which is lower in the high frequency band.

[0038] For example, as shown in Fig. 8, the frequency at which the gain drops by 3 dB is approximately 16 kHz in the frequency band FBa of the original analog signal, while it is approximately 5.5 kHz in the frequency band FBc of the interpolated digital signal. Therefore, in the frequency band FBo of the output signal obtained by combining the frequency band FBa of the analog signal and the frequency band FBc of the interpolated digital signal, the frequency at which the gain drops by 3 dB is approximately 8 kHz.

[0039] Fig. 9 is a diagram showing an example of the frequency-gain characteristics of the output in DA conversion when the value of the interpolated digital signal matches and does not match the value of the original analog signal in 2x oversampling using linear interpolation (average value interpolation). Fig. 10 is a diagram showing each characteristic by widening the vertical scale of the graph shown in Fig. 9 and narrowing the horizontal scale. In Figs. 9 and 10, the frequency band FBm of the output signal output from a DA conversion unit (not shown) when the value of the interpolated digital signal matches the value of the original analog signal is shown by a solid line, and the frequency band FBum of the output signal output from the DA conversion unit when these two values do not match is shown by a dashed line. Note that the frequency band FBon shown in Figs. 9 and 10 is the same as the frequency band FBo shown in Figs. 7 and 8.

[0040] When the value of the interpolated digital signal matches the value of the original analog signal, DA conversion operates in the same way as DA conversion with a doubled sampling frequency. Therefore, as shown in FIG. 9, when the value of the interpolated digital signal matches the value of the original analog signal in 2x oversampling using linear interpolation, the frequency band FBm of the output signal output from the DA conversion unit is the same as the frequency band of the original analog signal (see FIG. 7). Therefore, in this case, the frequency band FBo of the output signal output from the DA conversion unit is wider than the frequency band FBum of the output signal output from the DA conversion unit when these two values do not match. For example, as shown in FIG. 10, the frequency at which the gain drops by 3 dB is approximately 16 kHz in the frequency band FBm, but approximately 8 kHz in the frequency band FBum of the output signal.

[0041] Thus, in 2x oversampling using linear interpolation, the smaller the error between the value of the interpolated digital signal and the value of the original analog signal, the wider the frequency band of the output signal output from the DA conversion unit, and the more suppressed is the loss of gain at high frequencies.The oversampling of digital signals according to the present invention utilizes the fact that the magnitude of the error between the value of the interpolated digital signal and the value of the original analog signal affects the width of the frequency band of the output signal, thereby suppressing the loss of gain at high frequencies in the frequency band of the output signal after DA conversion and improving the output characteristics of the DA conversion unit.

[0042] FIG. 11 is a diagram showing an example of the frequency band characteristics of an output signal obtained by DA conversion using oversampling in digital signal processing according to the present invention. FIG. 12 is a diagram showing the respective characteristics by widening the vertical axis scale and narrowing the horizontal axis scale of the graph shown in FIG. 11. In FIGS. 11 and 12, the frequency band FBa of the original analog signal is shown by a dashed line, the frequency band FBc of the interpolated digital signal is shown by a dashed-dotted line, and the frequency band FBoc of the output signal output from a DA conversion unit (not shown) using conventional oversampling with linear interpolation is shown by a dashed-two-dot line. In FIGS. 11 and 12, the frequency band FBoi of the output signal output from the DA conversion unit using oversampling in digital signal processing according to the present invention is shown by a solid line. Note that the interpolation timing in the frequency band FBoi shown in FIGS. 11 and 12 is a timing that divides the period between two consecutive sampled digital signals at a 1:2 interval.

[0043] Compared with oversampling using conventional linear interpolation, the oversampling in the digital signal processing according to the present invention reduces the error between the interpolated digital signal value and the original analog signal value, and therefore, as shown in Figures 11 and 12, the frequency band FBoi in the digital signal processing according to the present invention is wider than the frequency band FBoc in the conventional linear interpolation.

[0044] Here, the period between the sampling timing of the sampled digital signal and the interpolation timing is sometimes referred to as the "hold time." In other words, the period from the sampling timing of the sampled digital signal to the interpolation timing is sometimes referred to as the "hold time of the sampled digital signal," and the period from the interpolation timing to the sampling timing of the sampled digital signal is sometimes referred to as the "hold time of the interpolated digital signal." With oversampling, the interpolated digital signal is inserted, which shortens the hold time of the sampled digital signal and extends the frequency band of the original analog signal to a higher frequency band compared to when oversampling is not performed.

[0045] 11 and 12, the interpolation timing of oversampling in digital signal processing according to the present invention is determined to divide the period between two consecutive sampled digital signals at an interval of 1:2. On the other hand, in conventional mean value linear interpolation, the interpolation timing of oversampling is determined to divide the period between two consecutive sampled digital signals at an interval of 1:1. Therefore, in this example, the oversampling in digital signal processing according to the present invention shortens the hold time of the sampled digital signals and lengthens the hold time of the interpolated digital signals compared to oversampling using conventional mean value linear interpolation.

[0046] In the oversampling in the digital signal processing according to the present invention, the interpolation timing is determined so as to minimize the error between the value of the interpolated digital signal and the value of the original analog signal. Therefore, in the digital signal processing according to the present invention, the hold time of the interpolated digital signal may be shortened. However, even when the hold time is shortened, the error between the value of the interpolated digital signal and the value of the original analog signal is small, so the frequency band FBoi of the output signal output from the DA conversion unit is sufficiently larger than the frequency band of the signal to be processed by the digital signal processing according to the present invention. For example, if the signal to be processed is an audio signal, the audio band is 7 kHz. In contrast, as shown in FIG. 12, the frequency at which the gain drops by 3 dB in the frequency band FBoi (i.e., the cutoff frequency) is approximately 13 kHz. Therefore, the frequency band FBoi in the digital signal processing according to the present invention can be DA converted without degrading the original audio band (i.e., the frequency band of the original analog signal).

[0047] Furthermore, in the digital signal processing according to the present invention, the error between the value of the interpolated digital signal and the value of the original analog signal is minimized during oversampling, and therefore the frequency band of the output signal from the DA converter is wider than in conventional oversampling using linear interpolation, which can result in a larger error. For example, as shown in Figure 12, in the frequency band FBoc in conventional linear interpolation, the frequency at which the gain drops by 3 dB (i.e., the cutoff frequency) is approximately 8 kHz. In contrast, in the frequency band FBoi in the digital signal processing according to the present invention, the frequency at which the gain drops by 3 dB (i.e., the cutoff frequency) is approximately 13 kHz.

[0048] As described above, the digital signal processing according to the present invention relates to processing of digital signals used in digital-to-analog conversion, and determines the timing of inserting an interpolated digital signal based on the values of two consecutively input digital signals and the value of the interpolated digital signal. This makes it possible for the digital signal processing according to the present invention to improve the output characteristics of the DA conversion unit. Below, an embodiment of a device that realizes the digital signal processing according to the present invention will be described.

[0049] [First embodiment] 2-1.Configuration of digital signal processing device A digital signal processing device according to a first embodiment of the present invention will be described with reference to Figs. 13 to 18. First, the configuration of the digital signal processing device according to this embodiment will be described with reference to Figs. 13 to 15. Fig. 13 is a block diagram showing an example of a schematic configuration of a digital signal processing device 1A according to this embodiment. Fig. 14 is a diagram schematically showing an example of an input digital signal ID[N] input to a downsampling unit 111 and an interpolation timing determination unit 112 provided in the digital signal processing device 1A. Fig. 15 is a block diagram showing an example of a schematic configuration of a digital-analog conversion processing unit 12 provided in the digital signal processing device 1A according to this embodiment.

[0050] 13, a digital signal processing device 1A according to this embodiment is a device that processes digital signals used in digital-to-analog conversion, and includes a digital signal processing unit 11A and a digital-to-analog conversion processing unit 12. Hereinafter, digital-to-analog conversion may be abbreviated as "DA conversion." As will be described in detail later, the digital signal processing unit 11A determines the interpolation timing of an interpolated digital signal, and the DA conversion processing unit 12 interpolates the interpolated digital signal at the interpolation timing determined by the digital signal processing unit 11A and outputs an analog output signal Sout obtained by DA conversion.

[0051] The digital signal processing unit 11A receives an input digital signal ID[N] output from an analog / digital signal processing device (not shown), an input clock signal ICLK, a sampling clock signal PCLK, and a serial data processing clock signal SCLK. The input digital signal D[N]j is, for example, a 16-bit (N=16) audio data signal.

[0052] The digital signal processing unit 11A provided in the digital signal processing device 1A has a downsampling unit 111, an interpolation timing determination unit 112, and a parallel-to-serial conversion unit 113. The output of the downsampling unit 111 is connected to one input of the parallel-to-serial conversion unit 113, and the output of the interpolation timing determination unit 112 is connected to the other input of the parallel-to-serial conversion unit 113. The output of the parallel-to-serial conversion unit 113 is connected to the input of the DA conversion processing unit 12.

[0053] As shown in FIG. 14, the input digital signal ID[N] includes a first digital signal D1[N], multiple third digital signals D3[N]1, D3[N]2, D3[N]3, D3[N]4, D3[N]5, D3[N]6, and D3[N]7, and a second digital signal D2[N]. Hereinafter, the third digital signals D3[N]1, D3[N]2, D3[N]3, D3[N]4, D3[N]5, D3[N]6, and D3[N]7 may be abbreviated as "third digital signal D3[N]j" (j = 1, 2, 3, 4, 5, 6, and 7). The first digital signal D1[N], multiple third digital signals D3[N]j, and second digital signal D2[N] are continuously input to the digital signal processing unit 11A, for example, at a first period P1. The reciprocal of the first period P1 is defined as a first frequency. The downsampling unit 111 samples, for example, one of 1+j consecutive (j=7 in this example) first digital signals D1[N] and multiple third digital signals D3[N]j. Therefore, the second frequency, which is the frequency related to downsampling, is the reciprocal of the second period P2. For convenience of explanation, in this embodiment, the second frequency is set to 1 / 8 times the first frequency, but it may be set to another multiple as long as it is a frequency lower than the first frequency. If the input digital signal ID[N] is, for example, an audio data signal, the first frequency is, for example, 128 kHz, and the second frequency is, for example, 16 kHz.

[0054] The downsampling unit 111 (see FIG. 13) selectively samples the first digital signal D1[N] at a second frequency lower than the first frequency from among input digital signals ID[N] including a first digital signal D1[N], a plurality of third digital signals D3[N]j, and a second digital signal D2[N] that are continuously input at a first frequency. The first digital signal D1[N] in the m-th downsampling (m is a natural number) becomes the second digital signal D2[N] in the m-1-th downsampling. Furthermore, the second digital signal D2[N] in the m-th downsampling becomes the first digital signal D1[N] in the m+1-th downsampling.

[0055] 2, for example, if the sampled digital signal Ss1 corresponds to the first digital signal D1[N], then the sampled digital signal Ss2 corresponds to the second digital signal D2[N]. Furthermore, for example, if the sampled digital signal Ss2 corresponds to the first digital signal D1[N], then the sampled digital signal Ss3 corresponds to the second digital signal D2[N]. Similarly, if the sampled digital signal Ssj (j=3, 4) corresponds to the first digital signal D1[N], then the sampled digital signal Ssj (j=4, 5) corresponds to the second digital signal D2[N].

[0056] 13 and 14, the input digital signal ID[N] is input to the downsampling unit 111 in synchronization with the sampling clock signal PCLK and the input clock signal ICLK. The downsampling unit 111 samples a first digital signal D1[N] of the input digital signal ID[N] that is input in synchronization with the falling edge of the input clock signal ICLK, and outputs the sampled first digital signal D1[N] to the parallel-to-serial conversion unit 113 (see FIG. 13) as a downsampled digital signal DD[N]. As a result, the downsampled digital signal DD[N] is input from the downsampling unit 111 to the parallel-to-serial conversion unit 113 for each cycle of the input clock signal ICLK (i.e., the second cycle P2).

[0057] The interpolation timing determiner 112 (an example of a determiner) determines the interpolation timing TGi (see FIG. 14) for interpolating the interpolated digital signal Sii based on the value V1 (an example of a first value) of the first digital signal D1[N], the value V2 (an example of a second value) of the second digital signal D2[N], the value Vi (an example of a third value) of the interpolated digital signal Sii, and the values of each of the multiple third digital signals D3[N]j input during the period between the first digital signal D1[N] and the second digital signal D2[N] (i.e., one cycle of the second cycle P2). In this embodiment, the value Vi of the interpolated digital signal Sii is the average value of the value V0 of the first digital signal D1[N] and the value V8 of the second digital signal D2[N]. As will be described in detail later, the interpolation timing determiner 112 determines the timing at which the third digital signal D3[N]j having a value closest to the value Vi of the interpolated digital signal Sii is input as the interpolation timing TGi. The interpolation timing determination unit 112 generates a data selection clock signal LRCK that falls at the timing when the first digital signal D1[N] and the second digital signal D2[N] are input and rises at the interpolation timing TGi, and outputs the generated clock signal to the parallel-to-serial conversion unit 113.

[0058] 13, the parallel-to-serial conversion unit 113 converts the N-bit downsampled digital signal DD[N] input from the downsampling unit 111 into a 1-bit serial data signal SDATA in synchronization with the data selection clock signal LRCK. The parallel-to-serial conversion unit 113 converts the downsampled digital signal DD[N] into a serial data signal SDATA in synchronization with the serial data processing clock signal SCLK input to the digital signal processing unit 11A. The parallel-to-serial conversion unit 113 outputs the converted serial data signal SDATA to the DA conversion processing unit 12 in synchronization with the serial data processing clock signal SCLK.

[0059] Although details will be described later, the parallel-to-serial conversion unit 113 delays the data selection clock signal LRCK input from the interpolation timing determination unit 112 by a predetermined period and outputs it to the DA conversion processing unit 12 so that the interpolated digital signal Sii[N] is interpolated at the interpolation timing determined by the interpolation timing determination unit 112.

[0060] 15, the DA conversion processing unit 12 includes a serial-to-parallel conversion unit 121, an interpolated data calculation unit 124, an interpolation unit 126, an output clock signal generation unit 127, a digital-to-analog conversion unit 128, a low-pass filter 129, an output amplifier 120, and delay flip-flops 122, 123a, 123b, 125a, 125b, and 125c. Hereinafter, the delay flip-flops are abbreviated as "DFF."

[0061] The input of the serial-parallel conversion section 121 is connected to one of the outputs of the parallel-serial conversion section 113 (see FIG. 13), and the output of the serial-parallel conversion section 121 is connected to the input of DFF123a. The output of DFF123a is connected to the input of DFF125a and one of the inputs of the interpolation data calculation section 124. The output of DFF125a is connected to the other input of the interpolation data calculation section 124 and one of the inputs of the interpolation section 126. The output of the interpolation data calculation section 124 is connected to the input of DFF125c. The output of DFF125c is connected to the other input of the interpolation section 126.

[0062] The input of DFF122 is connected to the other output of the parallel-serial converter 113, the output of DFF122 is connected to the input of DFF123b and the clock signal input terminals of DFF123a and DFF125a, the output of DFF123b is connected to the input of DFF125b and the clock signal input terminal of DFF125c, and the output of DFF125b is connected to the selection signal input terminal of the interpolator 126 and the input of the output clock signal generator 127.

[0063] The output of the interpolation unit 126 is connected to the input of the DA conversion unit 128. The output of the output clock signal generation unit 127 is connected to the clock signal input terminal of the DA conversion unit 128. The output of the DA conversion unit 128 is connected to the input of the low-pass filter 129. The output of the low-pass filter 129 is connected to the input of the output amplifier 120. The output of the output amplifier 120 becomes the output of the DA conversion processing unit 12, i.e., the output of the digital signal processing device 1A.

[0064] The serial-to-parallel conversion unit 121 receives as input the serial data signal SDATA output by the parallel-to-serial conversion unit 113 (see FIG. 13) and the serial data processing clock signal SCLK input via the digital signal processing unit 11A. The serial-to-parallel conversion unit 121 converts the 1-bit serial data signal SDATA input in synchronization with the serial data processing clock signal SCLK into an N-bit down-sampled digital signal DD[N]. The serial-to-parallel conversion unit 121 synchronizes the down-sampled digital signal DD[N] with the serial data processing clock signal SCLK and outputs it to DFF123a.

[0065] DFF122 has a negative logic clock signal input terminal to which the serial-data processing clock signal SCLK is input. DFF122 latches the data selection clock signal LRCK output from the parallel-to-serial converter 113 (see FIG. 13) in synchronization with the falling edge of the serial-data processing clock signal SCLK. DFF122 outputs the latched data selection clock signal LRCK to DFF123a and DFF123b.

[0066] Incidentally, when the serial-to-parallel converter 121 converts the 1-bit serial data signal SDATA into an N-bit down-sampled digital signal DD[N], a delay occurs with respect to the serial-data processing clock signal SCLK. This causes a timing discrepancy between the down-sampled digital signal DD[N] output from the serial-to-parallel converter 121 and the serial-data processing clock signal SCLK. The DA converter 12 is provided with DFF122 to adjust this timing discrepancy. That is, inputting the data selection clock signal LRCK from the digital signal processor 11A to the clock signal input terminal of DFF125a via DFF122 is slower than inputting it directly to the clock signal input terminal of DFF125a. This enables the DA converter 12 to prevent a timing discrepancy between the down-sampled digital signal DD[N] and the data selection clock signal LRCK at the input of DFF123a.

[0067] DFF123a has a negative-logic clock signal input terminal to which the data selection clock signal LRCK output by DFF122 is input. DFF123a latches the downsampled digital signal DD[N] output by the serial-to-parallel conversion unit 121 in synchronization with the falling edge of the data selection clock signal LRCK. DFF123a outputs the latched downsampled digital signal DD[N] to DFF125a and the interpolation data calculation unit 124.

[0068] DFF123b has a negative-logic clock signal input terminal to which the serial-data processing clock signal SCLK is input. DFF123b latches the data selection clock signal LRCK output by DFF122 in synchronization with the falling edge of the serial-data processing clock signal SCLK. DFF123b outputs the latched data selection clock signal LRCK to DFF125b and DFF125c (details will be described later).

[0069] DFF125a has a negative-logic clock signal input terminal to which the data selection clock signal LRCK output by DFF122 is input. DFF125a latches the downsampled digital signal DD[N] output by DFF123a in synchronization with the falling edge of the data selection clock signal LRCK. DFF125a outputs the latched downsampled digital signal DD[N] to the interpolation data calculation unit 124 and the interpolation unit 126.

[0070] The downsampled digital signal DD[N] output from DFF125a is a signal that precedes the downsampled digital signal DD[N] output from DFF123a by one cycle of the data selection clock signal LRCK. Therefore, two downsampled digital signals DD[N] that are shifted by one cycle of the data selection clock signal LRCK are input to the interpolated data calculation unit 124. For example, the second digital signal D2[N] shown in FIG. 14 is input from DFF123a as the downsampled digital signal DD[N] to the interpolated data calculation unit 124, and the first digital signal D1[N] shown in FIG. 14 is input from DFF125a as the downsampled digital signal DD[N].

[0071] The interpolated data calculation unit 124 (an example of a calculation unit) calculates, as the average value of the values V1 and V2, for example, a third value (value Vi) of an interpolated digital signal Sii (see FIG. 14) to be interpolated between a first digital signal D1[N] (see FIG. 14) having, for example, a first value (value V1) and a second digital signal D2[N] (see FIG. 14) having, for example, a second value (value V2) and input after the first digital signal D1[N]. The interpolated data calculation unit 124 outputs an N-bit interpolated digital signal Sii[N] having the calculated value Vi to DFF125c. The interpolated data calculation unit 124 calculates and outputs the value Vi to DFF125c asynchronously and not in synchronization with the data selection clock signal LRCK and the serial data processing clock signal SCLK.

[0072] DFF125c has a positive-logic clock signal input terminal to which the data selection clock signal LRCK output by DFF123b is input. DFF125c latches the interpolated digital signal Sii[N] output by the interpolated-data calculation unit 124 in synchronization with the rising edge of the data selection clock signal LRCK. DFF125c outputs the latched interpolated digital signal Sii[N] to the interpolation unit 126 in synchronization with the next rising edge of the data selection clock signal LRCK.

[0073] DFF125b has a negative-logic clock signal input terminal to which the serial-data processing clock signal SCLK is input. DFF125b latches the data selection clock signal LRCK output by DFF123b in synchronization with the falling edge of the serial-data processing clock signal SCLK. DFF125b outputs the latched data selection clock signal LRCK to the interpolation unit 126 and the output clock signal generation unit 127 (details of which will be described later).

[0074] The downsampled digital signal DD[N] output from the serial-to-parallel conversion unit 121 passes through DFF123a and 125b before being input to the interpolation unit 126. Therefore, DFF123b and 125b are provided so that the data selection clock signal LRCK output from DFF122 also passes through the same number of DFFs as the downsampled digital signal DD[N] before being input to the interpolation unit 126. This enables the DA conversion processing unit 12 to prevent a timing discrepancy between the downsampled digital signal DD[N] and the data selection clock signal LRCK at the input to the interpolation unit 126.

[0075] The interpolation unit 126 interpolates the interpolated digital signal Sii[N] at the interpolation timing TGi determined by the interpolation timing determination unit 112 (see FIG. 13). Specifically, the interpolation unit 126 outputs the downsampled digital signal DD[N] input from DFF125a to the DA conversion unit 128 in synchronization with the falling edge of the data selection clock signal LRCK input from DFF125b. On the other hand, the interpolation unit 126 outputs the interpolated digital signal Sii[N] input from DFF125c to the DA conversion unit 128 in synchronization with the rising edge of the data selection clock signal LRCK input from DFF125b.

[0076] This allows the interpolation unit 126 to output an output digital signal So[N] in which the downsampled digital signal DD[N] and the interpolated digital signal Sii[N] are arranged alternately to the DA conversion unit 128. In other words, the interpolation unit 126 can output an output digital signal So[N] in which the signal is arranged as follows: "downsampled digital signal DD[N] as first digital signal D1[N] → interpolated digital signal Sii[N] → second digital signal D2[N] → interpolated digital signal Sii[N] → first digital signal D1[N] → ..." to the DA conversion unit 128.

[0077] Furthermore, the rising edge of the data selection clock signal LRCK is the interpolation timing TGi, so the interpolation unit 126 can output the interpolated digital signal Sii[N] to the DA conversion unit 128 at the interpolation timing TGi determined by the interpolation timing determination unit 112 between the first digital signal D1[N] and the second digital signal D2[N].

[0078] The output clock signal generation unit 127 synchronizes the data selection clock signal LRCK input from DFF125b with the serial data processing clock signal SCLK, and outputs the synchronized signal as the output clock signal OCLK to the DA conversion unit 128. Therefore, the output clock signal OCLK is a signal obtained by delaying the data selection clock signal LRCK input from DFF125b by one clock of the serial data processing clock signal SCLK. This prevents a difference between the timing at which the output digital signal So[N] is input to the DA conversion unit 128 and the timing at which the output clock signal OCLK is input to the DA conversion unit 128, due to a processing delay caused by the interpolation unit 126.

[0079] The DA conversion unit 128 performs digital-to-analog conversion on the downsampled digital signal DD[N] at the falling edges of the output clock signal OCLK input from the output clock signal generation unit 127, and outputs the result to the low-pass filter 129. The DA conversion unit 128 also performs digital-to-analog conversion on the interpolated digital signal Sii[N] at the rising edges of the output clock signal OCLK input from the output clock signal generation unit 127, and outputs the result to the low-pass filter 129. The output clock signal OCLK has the same signal waveform as the data selection clock signal LRCK. Therefore, the DA conversion unit 128 can convert the downsampled digital signal DD[N] and the interpolated digital signal Sii[N] into analog signals at the timing determined by the interpolation timing determination unit 112.

[0080] The low-pass filter 129 removes aliasing components contained in the analog signal input from the DA conversion unit 128 and outputs the analog signal from which the aliasing components have been removed. The cutoff frequency of the low-pass filter 129 is set to, for example, a frequency between half the sampling frequency and the sampling frequency. In this embodiment, the sampling frequency corresponds to the second frequency. The low-pass filter 129 is formed, for example, by a Butterworth filter.

[0081] The output amplifier 120 receives the analog signal output by the low-pass filter 129. The output amplifier 120 amplifies the analog signal and outputs it as an output signal Sout to the outside of the digital-analog conversion processing unit 12 (i.e., the outside of the digital signal processing device 1A).

[0082] 2-2. Operation of the digital-to-analog conversion processing device The operation of the digital signal processing device according to this embodiment will be described using Figures 16 and 17 with reference to Figures 13 to 15. Figure 16 is a timing chart showing an example of the operation of the digital signal processing device 1A according to this embodiment. Figure 17 is a flowchart showing an example of the flow of the interpolation timing determination process executed in the interpolation timing determination unit 112.

[0083] "SCLK" shown in Fig. 16 indicates a serial data processing clock signal, "PCLK" shown in Fig. 16 indicates a sampling clock signal, and "ICLK" shown in Fig. 16 indicates an input clock signal. "ID[N]" shown in Fig. 16 indicates an input digital signal.

[0084] 16 indicates the downsampled digital signal output from the downsampling section 111, and "SDATA" shown in Fig. 16 indicates the serial data signal. "DD[N]1" shown in Fig. 16 indicates the downsampled digital signal output from the serial-to-parallel conversion section 121, "DD[N]2" shown in Fig. 16 indicates the downsampled digital signal output from DFF123a, and "DD[N]3" shown in Fig. 16 indicates the downsampled digital signal output from DFF125a. "Sii[N]" shown in Fig. 16 indicates the interpolated digital signal, and "So[N]" shown in Fig. 16 indicates the output digital signal.

[0085] 16 indicates the data selection clock signal output from the interpolation timing determination section 112, and "LRCK2" shown in Fig. 16 indicates the data selection clock signal output from the parallel-to-serial conversion section 113. "LRCK3" shown in Fig. 16 indicates the data selection clock signal output from DFF122, and "LRCK4" shown in Fig. 16 indicates the data selection clock signal output from DFF123b. "LRCK5" shown in Fig. 16 indicates the data selection clock signal output from DFF125b, and "OCLK" shown in Fig. 16 indicates the output clock signal.

[0086] Since the serial data processing clock signal SCLK is a high-frequency signal, one clock of the serial data processing clock signal SCLK is represented by a straight line in Fig. 16. Also, in Fig. 16, the number of straight lines representing one clock of the serial data processing clock signal SCLK relative to one clock of the sampling clock signal PCLK is not shown, just like the period of the serial data processing clock signal SCLK relative to one period of the sampling clock signal PCLK. Also, in Fig. 16, the frequency of the sampling clock signal PCLK is represented as eight times the frequency of the input clock signal ICLK, in line with the description in Fig. 14.

[0087] 16, the first digital signal D1[N] included in the input digital signal ID[N] is represented by the number "1" enclosed in a square, and the second digital signal D2[N] included in the input digital signal ID[N] is represented by the number "2" enclosed in a square. Similarly, the third digital signal D3[N]j (j = 1 to 7) included in the input digital signal ID[N] is represented by the number "3j" (j = 1 to 7) enclosed in a square. For example, the third digital signal D3[N]1 has j = 1, so it is represented by the number "31" enclosed in a square, and the third digital signal D3[N]2 has j = 2, so it is represented by the number "32" enclosed in a square.

[0088] A signal that is the second digital signal D2[N] in the mth second period P2 and that becomes the first digital signal D1[N] in the (m+1)th second period P2 is represented by the number "1(m)" in parentheses below the number "2" in a square. For example, the second digital signal D2[N] in the first second period P2 is the first digital signal D1[N] in the second second period P2. For this reason, in FIG. 16, the second digital signal D2[N] in the first second period P2 is represented by the number "2" in a square, and the first digital signal D1[N] in the second second period P2 is represented by the number "1(2)" in parentheses below the number "2."

[0089] 16, the downsampled digital signal DD[N] obtained by sampling the first digital signal D1[N] is represented by a square with the number 0 enclosed in a box. As described above, the downsampled digital signal DD[N] is sampled for each repeated second period P2. In FIG. 16, the downsampled digital signal DD[N] sampled in the mth second period P2 is represented as "1(m)." For example, the downsampled digital signal sampled in the first second period P2 is represented as "1(1)."

[0090] 16, the average value of the value of the downsampled digital signal sampled in the mth second period P2 and the value of the downsampled digital signal sampled in the (m+1)th second period P2 is represented as "Ave(m-(m+1)"). For example, the average value of the value of the downsampled digital signal sampled in the first second period P2 and the value of the downsampled digital signal sampled in the second second period P2 is represented as "Ave(1-2)".

[0091] As shown in FIG. 16, during the period from time t1 to time t2 (i.e., one cycle of the second cycle P2), when the first digital signal D1[N], the third digital signal D3[N]j, and the second digital signal D2[N] included in the input digital signal ID[N] are input from an analog / digital signal processing device (not shown) to the digital signal processing unit 11A (see FIG. 13), the interpolation timing determination unit 112 (see FIG. 13) provided in the digital signal processing unit 11A starts the process of determining the interpolation timing. The first digital signal D1[N] and the second digital signal D2[N] are input to the interpolation timing determination unit 112 in synchronization with the falling edges of the sampling clock signal PCLK and the rising edges of the input clock signal ICLK. Furthermore, the third digital signal D3[N]j is input to the interpolation timing determination unit 112 in synchronization with the rising edges of the input clock signal ICLK.

[0092] As shown in Figure 17, when the interpolation timing determination process is started, in step S11, the interpolation timing determination unit 112 stores the input digital signal ID[N] including the first digital signal D1[N], the third digital signal D3[N]j, and the second digital signal D2[N], and proceeds to processing in step S12.

[0093] In step S12, the interpolation timing determination unit 112 calculates the average value of the value V1 of the first digital signal D1[N] and the value V2 of the second digital signal D2[N], and stores the calculation result as the value Vi of the interpolated digital signal Sii[N]. Also in step S12, the interpolation timing determination unit 112 calculates the absolute value of the difference between the calculated value Vi and the value V31 of the third digital signal D3[N]1, and stores this absolute value as the minimum absolute value Vabs. After storing the value Vi and the minimum absolute value Vabs of the interpolation digital signal Sii[N], the interpolation timing determination unit 112 proceeds to the processing of step S13.

[0094] In step S13, the interpolation timing determination unit 112 changes the target to be compared with the value Vi of the interpolated digital signal Sii[N] to the third digital signal D3[N]2 (j←2). Further, the interpolation timing determination unit 112 sets the timing at which the third digital signal D3[N]1 is input as a provisional interpolation timing TGi (g←1), and proceeds to the process of step S14.

[0095] In step S14, the interpolation timing determination unit 112 determines whether or not the target to be compared with the value Vi of the interpolated digital signal Sii[N] is not the second digital signal D2[N]. That is, the interpolation timing determination unit 112 determines whether or not the relationship of "j<Jover" is satisfied. "Jover" is a value obtained by adding the number of the second digital signal D2[N] (that is, "1") to the number of the third digital signal D3[N]j. In the example of the timing chart shown in FIG. 16, since the number of the third digital signal D3[N]j is 7 (j = 7), the value of Jover is "8". When the interpolation timing determination unit 112 determines that the relationship of "j<Jover" is satisfied, it determines that the target to be compared with the value Vi of the interpolated digital signal Sii[N] is not the second digital signal D2[N], that is, the third digital signal D3[N]j (step S14: Yes), and proceeds to the process of step S15.

[0096] On the other hand, when the interpolation timing determination unit 112 determines that the relationship of "j<Jover" is not satisfied, it determines that the target to be compared with the value Vi of the interpolated digital signal Sii[N] is not the third digital signal D3[N]j but the second digital signal D2[N] (step S14: No). In this case, the interpolation timing determination unit 112 determines that the calculation of the absolute value of the difference between the value Vi of the interpolated digital signal Sii[N] and each value V3j (j = 1 to 7) of the third digital signal D3[N]j has been completed. The interpolation timing determination unit 112 determines the input timing of the third digital signal D[N]j set as the provisional interpolation timing TGi at the current time as the interpolation timing TGi, and ends the interpolation timing determination process.

[0097] In step S15, the interpolation timing determination unit 112 calculates the absolute value of the difference between the value V3j of the third digital signal D[N]j currently being compared and the value Vi of the interpolated digital signal Sii[N], and determines whether the calculated absolute value is smaller than the minimum absolute value Vabs. If the interpolation timing determination unit 112 determines that the calculated absolute value is smaller than the minimum absolute value Vabs (step S15: Yes), it proceeds to step S16. On the other hand, if the interpolation timing determination unit 112 determines that the calculated absolute value is larger than the minimum absolute value Vabs (step S15: No), it proceeds to step S17.

[0098] In step S16, the interpolation timing determination unit 112 sets the absolute value calculated in step S15 to the minimum absolute value Vabs, and sets the input timing of the third digital signal D[N]j that was the subject of comparison in step S15 as the tentative interpolation timing TGi (g←j), and proceeds to processing in step S17.

[0099] In step S17, the interpolation timing determination unit 112 changes the third digital signal D[N]j to be compared with the value Vi of the interpolated digital signal Sii[N] to the third digital signal D[N]j+1 (j←j+1), and returns to the processing of step S14. In this way, the interpolation timing determination unit 112 determines the input timing of the third digital signal D[N]j having the smallest difference from the value Vi of the interpolated digital signal Sii[N] as the interpolation timing TGi.

[0100] The interpolation timing determination unit 112 outputs a data selection clock signal LRCK (see LRCK1 in FIG. 16) that falls in synchronization with the falling edge of the input clock signal ICLK and rises at the interpolation timing TGi determined in the interpolation timing determination process shown in FIG. 17. The interpolation timing determination unit 112 outputs a data selection clock signal LRCK whose signal level rises at the interpolation timing TGi in the second period P2 following the second period P2 in which the interpolation timing TGi was determined. Note that until the interpolation timing TGi is determined, the interpolation timing determination unit 112 outputs the data selection clock signal LRCK having the same signal waveform as, for example, the sampling clock signal PCLK.

[0101] For example, suppose that the interpolation timing TGi is determined to be the input timing of the third digital signal D3[N]2 in the second cycle P2 from time t1 to time t2. In this case, as shown in FIG. 16, in the second cycle P2 following the second cycle P2 from time t1 to time t2, the interpolation timing determination unit 112 outputs to the parallel-to-serial conversion unit 113 (see FIG. 13) a data selection clock signal LRCK (see LRCK1 in FIG. 16) that falls at times t2 and t4 and rises at time t3, which corresponds to the input timing of the third digital signal D3[N]2. In this way, the interpolation timing determination unit 112 outputs the data selection clock signal LRCK that rises at the determined interpolation timing TGi, delayed by one cycle of the second cycle P2 from the second cycle P2 in which the interpolation timing TGi was determined.

[0102] As shown in FIG. 16, at time t2, the parallel-to-serial conversion unit 113 converts the N-bit first digital signal D1[N] sampled at time t1 (see 1(1) of DD[N]0 in FIG. 16) into a 1-bit string of serial data signal SDATA. The parallel-to-serial conversion unit 113 converts the first digital signal D1[N] into the serial data signal SDATA in synchronization with the serial data processing clock signal SCLK. Therefore, a period of N clocks of the serial data processing clock signal SCLK is required to convert the first digital signal D1[N] into the serial data signal SDATA.

[0103] The serial data signal SDATA, into which the first digital signal D1[N] has been converted, is then converted into an N-bit down-sampled digital signal DD[N] by the serial-to-parallel conversion unit 121 (see FIG. 15). The serial-to-parallel conversion unit 121 converts the serial data signal SDATA into the N-bit down-sampled digital signal DD[N] in synchronization with the serial data processing clock signal SCLK. Therefore, a period of N clocks of the serial data processing clock signal SCLK is required to convert the serial data signal SDATA into the first digital signal D1[N]. Therefore, the first digital signal D1[N], whose conversion into the serial data signal SDATA begins at time t2, is output from the serial-to-parallel conversion unit 121 as the down-sampled digital signal DD[N] (see DD[N]1 in FIG. 16) after a period twice the N clocks of the serial data processing clock signal SCLK has elapsed.

[0104] At time t4, the parallel-to-serial converter 113 starts outputting the data selection clock signal LRCK (see LRCK2 in FIG. 16) input at time t1. In this way, the parallel-to-serial converter 113 delays the data selection clock signal LRCK input from the interpolation timing determination unit 112 by two cycles of the second cycle P2 and outputs it.

[0105] Also, at time t4, the parallel-to-serial conversion unit 113 starts converting the N-bit first digital signal D1[N] sampled at time t2 (see 1(2) of DD[N]0 in Figure 16) into a 1-bit string of serial data signal SDATA.

[0106] At time t5, the downsampled digital signal DD[N] (see 1(1) of DD[N]1 in FIG. 16) output from the serial-to-parallel conversion section 121 is latched by DFF123a (see FIG. 15) in synchronization with the falling edge of the data selection clock signal LRCK (see LRCK3 in FIG. 16) output from DFF122 (see FIG. 15). DFF123a continues to output the downsampled digital signal DD[N] (see DD[N]2 in FIG. 16) latched at time t5 to the interpolated data calculation section 124 and DFF125a (see FIG. 15) while holding it, until the next downsampled digital signal DD[N] is input.

[0107] At time t6, the downsampled digital signal DD[N] (see DD[N]1 in FIG. 16) output from DFF123a is latched by DFF125a in synchronization with the falling edge of the data selection clock signal LRCK (see LRCK3 in FIG. 16) output from DFF122. DFF125a continues to output the downsampled digital signal DD[N] (see 1(1) of DD[N]3 in FIG. 16) latched at time t6 to the interpolated data calculation unit 124 and the interpolation unit 126 (see FIG. 15) while holding it, until the next downsampled digital signal DD[N] is input.

[0108] At time t6, the downsampled digital signal DD[N] (see 1(2) of DD[N]1 in FIG. 16) is latched by DFF123a in synchronization with the falling edge of the data selection clock signal LRCK (see LRCK3 in FIG. 16) output from DFF122. The downsampled digital signal DD[N] is the signal output after the serial-to-parallel conversion in the serial-to-parallel conversion section 121 has been performed on the serial data signal SDATA, for which parallel-to-serial conversion started at time t4. The downsampled digital signal DD[N] (see 1(2) of DD[N]1 in FIG. 16) latched by DFF123a is output to the interpolated data calculation section 124 and DFF125a.

[0109] At time t7, the data selection clock signal LRCK (see LRCK5 in FIG. 16) output from DFF125b (see FIG. 15) falls, causing the interpolation unit 126 to select the downsampled digital signal DD[N] (see 1(1) of DD[N]3 in FIG. 16) input from DFF125a, and output it to the DA conversion unit 128 (see FIG. 15).

[0110] The interpolated data calculation unit 124 (see FIG. 15) calculates an average value Ave(1-2) of the value of the sampling signal DD[N] input from DFF125a at time t6 and the value of the sampling signal DD[N] input from DFF123a at time t6, and outputs an interpolated digital signal Sii[N] having the average value Ave(1-2) to DFF125c (see FIG. 15). The interpolated data calculation unit 124 calculates the average value Ave(1-2) and outputs the interpolated digital signal Sii[N] asynchronously with the data selection clock signal LRCK and the serial data processing clock signal SCLK.

[0111] At time t8, when the output clock signal OCLK falls, the DA conversion unit 128 converts the downsampled digital signal DD[N] input from the interpolation unit 126 at time t7 into an analog signal and outputs it to the low-pass filter 129 (see Figure 15).

[0112] At time t9, the interpolated digital signal Sii[N] (see Ave(1-2) in FIG. 16) output from the interpolated data calculation unit 124 is latched by DFF125c in response to the rising edge of the data selection clock signal LRCK (see LRCK4 in FIG. 16) output from DFF123b. DFF125c keeps outputting the interpolated digital signal Sii[N] latched at time t9 to the interpolation unit 126 until it latches the next interpolated digital signal Sii[N].

[0113] At time t10, the data selection clock signal LRCK (see LRCK5 in FIG. 16) output from DFF125b (see FIG. 15) rises, causing the interpolation unit 126 to select the interpolated digital signal Sii[N] (see Ave(1-2) in FIG. 16) input from DFF125c, and output it to the DA conversion unit 128.

[0114] At time t11, the output clock signal OCLK rises, and the DA conversion unit 128 converts the interpolated digital signal Sii[N] input from the interpolation unit 126 at time t10 into an analog signal, and outputs it to the low-pass filter 129.

[0115] At time t12, the downsampled digital signal DD[N] (see 1(2) of DD[N]2 in FIG. 16) output from DFF123a is latched by DFF125a in synchronization with the falling edge of the data selection clock signal LRCK (see LRCK3 in FIG. 16) output from DFF122. DFF125a continues to output the downsampled digital signal DD[N] (see 1(2) of DD[N]3 in FIG. 16) latched at time t12 to the interpolated data calculation unit 124 and the interpolation unit 126 while holding it, until the next downsampled digital signal DD[N] is input.

[0116] At time t12, the downsampled digital signal DD[N] (see 1(3) of DD[N]1 in FIG. 16) is latched by DFF123a in synchronization with the falling edge of the data selection clock signal LRCK (see LRCK3 in FIG. 16) output from DFF122, and is output to the interpolated data calculation unit 124 and DFF125a. The downsampled digital signal DD[N] is the signal output after being serial-to-parallel converted in the serial-to-parallel conversion unit 121 from the serial data signal SDATA, for which parallel-to-serial conversion was started at time t6.

[0117] At time t13, the data selection clock signal LRCK (see LRCK5 in Figure 16) output from DFF125b falls, causing the interpolation unit 126 to select the downsampled digital signal DD[N] (see DD[N]3-1(2) in Figure 16) input from DFF125a, and output it to the DA conversion unit 128.

[0118] The interpolated data calculation unit 124 calculates an average value Ave(2-3) of the value of the sampling signal DD[N] (see 1(2) in FIG. 16) input from DFF 125 a at time t13 and the value of the sampling signal DD[N] (see 1(3) in FIG. 16) input from DFF 123 a at time t13, and outputs an interpolated digital signal Sii[N] having the average value Ave(2-3) to the interpolation unit 126. The interpolated data calculation unit 124 calculates the average value Ave(2-3) and outputs the interpolated digital signal Sii[N] asynchronously with the data selection clock signal LRCK and the serial data processing clock signal SCLK.

[0119] At time t14, the output clock signal OCLK falls, causing the DA conversion unit 128 to convert the downsampled digital signal DD[N] input from the interpolation unit 126 at time t13 into an analog signal and output it to the low-pass filter 129.

[0120] At time t15, the interpolated digital signal Sii[N] (see Ave(2-3) in FIG. 16) output from the interpolated data calculation unit 124 is latched by DFF125c in response to the rising edge of the data selection clock signal LRCK (see LRCK4 in FIG. 16) output from DFF123b. DFF125c keeps outputting the interpolated digital signal Sii[N] latched at time t15 to the interpolation unit 126 until it latches the next interpolated digital signal Sii[N].

[0121] At time t16, the data selection clock signal LRCK (see LRCK5 in FIG. 16) output from DFF125b rises, causing the interpolation unit 126 to select the interpolated digital signal Sii[N] (see Ave(2-3) in FIG. 16) input from DFF125c, and output it to the DA conversion unit 128.

[0122] At time t17, when the output clock signal OCLK rises, the DA conversion unit 128 converts the interpolated digital signal Sii[N] (see Ave(2-3) in Figure 16) input from the interpolation unit 126 at time t16 into an analog signal and outputs it to the low-pass filter 129.

[0123] Thereafter, the digital signal processing device 1A repeatedly executes operations similar to those performed from time t11 onward, thereby alternately outputting an analog signal based on the downsampled digital signal DD[N] and an analog signal based on the interpolated digital signal Sii[N]. The interpolated digital signal Sii[N] is sampled at the input timing of the third digital signal D3[N]j that has the smallest difference from the value Vi of the interpolated digital signal Sii[N]. This allows the digital signal processing device 1A to improve the output characteristics of the DA conversion unit 128.

[0124] As described above, the digital signal processing device 1A is a device that processes digital signals used in digital-to-analog conversion, and includes an interpolation data calculation unit 124 that calculates a third value, which is the value of an interpolated digital signal Sii[N] to be interpolated between a first digital signal D1[N] having a first value and a second digital signal D2[N] having a second value and input after the first digital signal D1[N], as the average of the first value and the second value; an interpolation timing determination unit 112 that determines an interpolation timing TGi for interpolating the interpolated digital signal Sii[N] based on the first value, the second value, the third value, and the values of each of a plurality of third digital signals D3[N]j that are input during the period between the first digital signal D1[N] and the second digital signal D2[N]; and an interpolation unit 126 that interpolates the interpolated digital signal Sii[N] at the interpolation timing TGi determined by the interpolation timing determination unit 112. With this configuration, the digital signal processing device 1A can improve the output characteristics of the DA conversion section 128.

[0125] (Variation) A digital signal processing device according to a modified example of the first embodiment of the present invention will be described with reference to FIG. 18. FIG. 18 is a diagram illustrating aliasing components that occur in an output signal in a digital signal processing device 1A according to the first embodiment. FIG. 18(a) is a diagram illustrating a spectrum of an output signal when an interpolation timing is determined so that two sampling timings are separated by a 1:1 interval. FIG. 18(b) is a diagram illustrating a spectrum of an output signal when an interpolation timing is determined so that two sampling timings are separated by a 1:2 interval. FIG. 18(c) is a diagram illustrating a spectrum of an output signal when an interpolation timing is determined so that two sampling timings are separated by a 2:1 interval. The horizontal axis of the graphs illustrated in FIGS. 18(a) to 18(c) represents frequency, and the vertical axis of the graphs represents signal intensity.

[0126] If the sampling frequency in DA conversion is not sufficiently higher than twice the signal band, the frequency gap between the signal band and the aliasing components becomes narrow. This makes it difficult for a low-pass filter provided downstream of the DA conversion to remove the aliasing components. Therefore, by doubling the sampling frequency, as in the digital signal processing according to the present invention or conventional oversampling using linear interpolation, the frequency gap between the signal band and the aliasing components becomes wider, making it easier for a low-pass filter provided downstream of the DA conversion to remove the aliasing components.

[0127] 18(a), when the interpolation timing separates two sampling timings at a 1:1 interval, the frequency interval between the signal component and the aliasing component in the output signal spectrum is a frequency fsa that is twice the sampling frequency fs. Because the bandwidth FBs of the signal component spectrum and the bandwidth FBe of the aliasing component spectrum are the same, the setting range SRa of the cutoff frequency of the low-pass filter provided in the subsequent stage of DA conversion is the range obtained by subtracting the bandwidth FBs and the bandwidth FBe from the frequency fsa.

[0128] On the other hand, although not shown, when oversampling is not performed, the setting range of the cutoff frequency of the low-pass filter provided downstream of the DA conversion is the range obtained by subtracting the bandwidth FBs and the bandwidth FBe from the sampling frequency fs. Hereinafter, for convenience of explanation, this setting range may be referred to as the "setting range SRn." The frequency fsa is twice the sampling frequency fs. Therefore, the setting range SRc is twice the setting range SRn. Therefore, when the interpolation timing separates two sampling timings at a 1:1 interval, designing the low-pass filter provided downstream of the DA conversion is easier than designing the filter when oversampling is not performed.

[0129] As shown in Figure 18(b), when the interpolation timing separates two sampling timings at a 1:2 interval, the frequency interval between the signal component and the aliasing component in the output signal spectrum is a frequency fsb that is 1.5 times the sampling frequency fs. Because the bandwidth FBs of the signal component spectrum and the bandwidth FBe of the aliasing component spectrum are the same, the setting range SRb of the cutoff frequency of the low-pass filter provided downstream of the DA conversion is the range obtained by subtracting the bandwidth FBs and the bandwidth FBe from the frequency fsb. Therefore, the setting range SRb is 1.5 times the setting range SRn. Therefore, when the interpolation timing separates two sampling timings at a 1:2 interval, designing the low-pass filter provided downstream of the DA conversion is easier than designing the filter when oversampling is not performed.

[0130] As shown in Figure 18(c), when the interpolation timing separates two sampling timings at a 2:1 interval, the frequency interval between the signal component and the aliasing component in the output signal spectrum is a frequency fsc, which is three times the sampling frequency fs. Because the bandwidth FBs of the signal component spectrum and the bandwidth FBe of the aliasing component spectrum are the same, the setting range SRc of the cutoff frequency of the low-pass filter provided downstream of the DA conversion is the range obtained by subtracting the bandwidth FBs and the bandwidth FBe from the frequency fsc. Therefore, the setting range SRc is three times the setting range SRn. Therefore, when the interpolation timing separates two sampling timings at a 2:1 interval, designing the low-pass filter provided downstream of the DA conversion is easier than designing the filter when oversampling is not performed.

[0131] In the digital signal processing device according to the first embodiment, the interpolation timing is changed according to the original analog signal, and therefore the frequency between the spectrum of the signal component and the spectrum of the aliased component is also changed. When the interpolation timing separates two sampling timings at a 1:2 interval, the period between the interpolation timing and the timing at which the first digital signal is input is shorter than when the interpolation timing separates two sampling timings at a 1:1 interval. Therefore, as shown in Figures 18(a) and 18(b), the shorter the period between the interpolation timing and the timing at which the first digital signal is input, the narrower the setting range of the cutoff frequency of the low-pass filter provided downstream of the DA conversion, making it difficult to design the low-pass filter.

[0132] Therefore, in the digital signal processing device according to this modification, if the period between the determined interpolation timing and the timing at which the first digital signal is input is shorter than one-third of the period from the first digital signal to the input of the second digital signal, the interpolation timing determiner redetermines the interpolation timing to be the timing at which one-third of the period has elapsed since the first digital signal was input. In other words, if the setting range of the cutoff frequency of the low-pass filter provided downstream of the DA conversion is shorter than the setting range SRb shown in Figure 18(b), the interpolation timing determiner redetermines the interpolation timing to be within the setting range SRb.

[0133] Furthermore, when the interpolation timing separates two sampling timings at a 2:1 interval, the period between the interpolation timing and the timing at which the first digital signal is input is longer than when the interpolation timing separates two sampling timings at a 1:1 interval. However, when the period between the interpolation timing and the timing at which the first digital signal is input is longer, the hold time of the first digital signal becomes shorter. This also makes it difficult to design the low-pass filter provided downstream of the DA conversion.

[0134] Therefore, in the digital signal processing device according to this modification, if the period between the determined interpolation timing and the timing at which the first digital signal is input is longer than two-thirds of the period from the first digital signal to the input of the second digital signal, the interpolation timing determiner redetermines the interpolation timing to be the timing at which two-thirds of the period has elapsed since the first digital signal was input. In other words, if the setting range of the cutoff frequency of the low-pass filter provided downstream of the DA conversion is longer than the setting range SRc shown in Figure 18(c), the interpolation timing determiner redetermines the interpolation timing to be within the setting range SRc.

[0135] In the digital signal processing device according to this modification, the interpolation timing may not be set to the timing that minimizes the difference between the value of the interpolated digital signal and the value of the original analog signal, but the design of the low-pass filter provided downstream of the DA conversion unit is simplified. As a result, the digital signal processing device according to this modification can remove aliasing components contained in the analog signal after DA conversion with high precision, thereby improving the precision of the output signal. This modification is also applicable to the second and third embodiments described later.

[0136] Second Embodiment 3-1.Configuration of digital signal processing device A digital signal processing device according to a second embodiment of the present invention will be described with reference to Figs. 19 and 20. First, the configuration of the digital signal processing device according to this embodiment will be described with reference to Figs. 19 and 20 while also referring to Fig. 15. Fig. 19 is a block diagram showing an example of a schematic configuration of a digital signal processing device 1B according to this embodiment. Fig. 20 is a diagram schematically showing an example of an oversampled digital signal OD[N] output from an oversampling unit 114 provided in the digital signal processing device 1B and input to a downsampling unit 111 and an interpolation timing determination unit 112. Note that components that perform the same actions and functions as those in the digital signal processing device 1A according to the first embodiment described above are given the same reference numerals, and their description will be omitted.

[0137] As shown in Fig. 19, a digital signal processing device 1B according to this embodiment is a device that processes digital signals used in digital-to-analog conversion, and includes a digital signal processing unit 11B and a digital-to-analog conversion processing unit 12. As will be described in detail later, the digital signal processing unit 11B determines the interpolation timing of an interpolated digital signal. The DA conversion processing unit 12 in this embodiment has the same configuration as the DA conversion processing unit 12 in the first embodiment, and performs the same functions.

[0138] The digital signal processing unit 11B receives an input digital signal ID[N] including a first digital signal D1[N] and a second digital signal D2[N] output from an analog / digital signal processing device (not shown), an input clock signal ICLK, a sampling clock signal PCLK, and a serial data processing clock signal SCLK. An example of the input digital signal ID[N] is a 16-bit (N=16) audio data signal.

[0139] The digital signal processing unit 11B provided in the digital signal processing device 1B has an oversampling unit 114 in addition to the configuration of the digital signal processing device 1A according to the first embodiment. An input digital signal ID[N], an input clock signal ICLK, and a sampling clock signal PCLK are input to the oversampling unit 114. The output of the oversampling unit 114 is connected to the inputs of the downsampling unit 111 and the interpolation timing determination unit 112, respectively.

[0140] The oversampling unit 114 performs interpolation filtering by inserting multiple zero points at predetermined timing between the first digital signal D1[N] and the second digital signal D2[N] (see FIG. 20), which are input consecutively at a third frequency, and then passing the signals through a low-pass filter, thereby generating an oversampled digital signal OD[N] (see FIG. 20) of a fourth frequency higher than the third frequency, which includes multiple third digital signals D3[N]j (j is a natural number) between the first digital signal D1[N] and the second digital signal D2[N]. The oversampling unit 114 outputs the generated oversampled digital signal OD[N] to the downsampling unit 111 and the interpolation timing determination unit 112. The oversampled digital signal OD[N] is an N-bit digital signal.

[0141] 20, the first digital signal D1[N] and the second digital signal D2[N] are continuously input to the digital signal processing unit 11B, for example, at a third period P3. The reciprocal of the third period P3 is set as a third frequency. The oversampling unit 114, for example, samples the continuous first digital signal D1[N]. Therefore, the third frequency, which is the frequency related to oversampling, is the reciprocal of the third period P3.

[0142] In this embodiment, the first digital signal D1[N] in the m-th (m is a natural number) oversampling becomes the second digital signal D2[N] in the (m-1)-th (m is a natural number) oversampling, and the second digital signal D2[N] in the m-th oversampling becomes the first digital signal D1[N] in the (m+1)-th (m is a natural number) oversampling.

[0143] The third digital signal D3[N]j is inserted between the first digital signal D1[N] and the second digital signal D2[N], for example, at a fourth period P4. The reciprocal of the fourth period P4 is defined as the fourth frequency. For convenience of explanation, in this embodiment, the fourth frequency is set to eight times the third frequency, but it may be set to any other multiple as long as it is a frequency higher than the third frequency. If the input digital signal ID[N] is, for example, an audio data signal, the third frequency is, for example, 16 kHz, and the fourth frequency is, for example, 128 kHz.

[0144] Returning to FIG. 19 , the oversampling unit 114 includes a zero point insertion unit 114a and a filter unit 114b. The zero point insertion unit 114a receives a first digital signal D1[N] and a second digital signal D2[N], an input clock signal ICLK, and a sampling clock signal PCLK from an analog / digital signal processing device (not shown). The zero point insertion unit 114a inserts zero points between the input first digital signal D1[N] and second digital signal D2[N] at time intervals of the fourth period P4. The zero point insertion unit 114a outputs the first digital signal D1[N], multiple zero points, and the second digital signal D2[N] to the filter unit 114b, in this order.

[0145] The filter unit 114b is configured, for example, by a low-pass filter. The filter unit 114b is provided to remove alias signals that occur in the oversampled digital signal due to oversampling in the zero point insertion unit 114a. The filter unit 114b outputs an oversampled digital signal OD[N], in which the alias signals have been removed from the signal input from the zero point insertion unit 114a, to the downsampling unit 111 and the interpolation timing determination unit 112. The oversampled digital signal OD[N] input to the downsampling unit 111 and the interpolation timing determination unit 112 includes a first digital signal D1[N], a plurality of third digital signals D3[N]j, and a second digital signal D2[N].

[0146] The downsampling unit 111 samples a first digital signal from the oversampling digital signal OD[N] continuously output from the oversampling unit 114, and generates a downsampling digital signal DD[N] having the same frequency as the third frequency. Although a signal different from that input to the downsampling unit 111 in the first embodiment (i.e., an oversampling digital signal OD[N]) is input to the downsampling unit 111, the oversampling digital signal OD[N] and the input digital signal ID[N] have similar configurations. Therefore, the downsampling unit 111 operates in the same manner as the downsampling unit 111 in the first embodiment, and can sample the first digital signal D[N] from the oversampling digital signal OD[N] and generate a downsampling digital signal DD[N] having the same frequency as the third frequency.

[0147] The oversampling unit 114 outputs the oversampled digital signal OD[N] to an interpolation timing determination unit (an example of a determination unit) 112. Therefore, a signal (i.e., an oversampled digital signal OD[N]) different from that input to the interpolation timing determination unit 112 in the first embodiment is input to the interpolation timing determination unit 112. However, the oversampled digital signal OD[N] and the input digital signal ID[N] have similar configurations. Therefore, the interpolation timing determination unit 112 determines, as the interpolation timing TGi (see FIG. 20 ), the timing at which a signal of the oversampled digital signal OD[N] having a value closest to the value Vi (an example of the third value) of the interpolated digital signal Sii[N] is input, in the same manner as the interpolation timing determination unit 112 in the first embodiment. The value Vi of the interpolated digital signal Sii[N] in this embodiment is the average value of the value V1 of the first digital signal D1[N] and the value V2 of the second digital signal D2[N], as in the first embodiment.

[0148] In the example shown in FIG. 20, the absolute value of the difference between the value Vi of the interpolated digital signal Sii[N] and the third digital signal D3[N]2 is the smallest among the third digital signals D3[N]j (j = 1 to 7) output from the oversampling unit 114. In FIG. 20, the absolute value of the difference between each value of the third digital signal D3[N]j and the value Vi of the interpolated digital signal Sii[N] is represented by the length of the up-down double arrow. Therefore, the interpolation timing determination unit 112 determines the input timing of the third digital signal D3[N]2 to be the interpolation timing TGi. The interpolation timing determination unit 112 generates a data selection clock signal LRCK having a signal waveform that falls at the input timings of the first digital signal D1[N] and the second digital signal D2[N] and rises at the interpolation timing TGi, and outputs the generated data selection clock signal LRCK to the parallel-to-serial conversion unit 113.

[0149] The data selection clock signal LRCK in this embodiment has the same rising and falling edges as the data selection clock signal LRCK in the first embodiment with respect to the input timings of the first digital signal D1[N], the second digital signal D2[N], and the interpolation timing TGi. Furthermore, the configurations of the stages subsequent to the downsampling unit 111 and the interpolation timing determination unit 112 are the same in the digital signal processing device 1B and the digital signal processing device 1A. Therefore, like the digital signal processing device 1A, the digital signal processing device 1B can improve the output characteristics of the DA conversion unit 128 (see FIG. 15) provided in the digital-analog conversion processing unit 12.

[0150] 3-2. Operation of digital signal processing device The operation of the digital signal processing device 1B is similar to that of the digital signal processing device 1A by replacing the input digital signal ID[N] with the oversampled digital signal OD[N] in the timing chart (see FIG. 16) showing an example of the operation of the digital signal processing device 1A according to the first embodiment. Furthermore, the operation of the interpolation timing determination unit 112 in this embodiment is similar to that of the interpolation timing determination unit 112 in the first embodiment. Therefore, a description of the operation of the digital signal processing device 1B will be omitted.

[0151] As described above, the digital signal processing device 1B is a device that processes digital signals used in digital-to-analog conversion, and has the same configuration as the digital signal processing device 1A according to the first embodiment. Therefore, the digital signal processing device 1B can obtain the same effects as the digital signal processing device 1A.

[0152] Furthermore, the digital signal processing device 1B is equipped with an oversampling unit 114 that performs interpolation filter processing by inserting multiple zero points at predetermined timing between a first digital signal D1[N] and a second digital signal D2[N] that are input consecutively at a third frequency, and then passing the signals through a low-pass filter, thereby generating an oversampled digital signal OD[N] of a fourth frequency higher than the third frequency, which includes multiple third digital signals D3[N]j between the first digital signal D1[N] and the second digital signal D2[N]. As a result, the digital signal processing device 1B can improve the output characteristics of the DA conversion section 128 even when the sampling rate of the input digital signal is low.

[0153] Third Embodiment 4-1.Configuration of digital signal processing device A digital signal processing device according to a third embodiment of the present invention will be described with reference to Fig. 21. First, the configuration of the digital signal processing device according to this embodiment will be described with reference to Fig. 21. Fig. 21 is a block diagram showing an example of the schematic configuration of a digital signal processing device 1C according to this embodiment. Note that components that perform the same actions and functions as those of the digital signal processing device 1A according to the first embodiment described above will be given the same reference numerals and their description will be omitted.

[0154] As shown in Fig. 21, a digital signal processing device 1C according to this embodiment is a device that processes digital signals used in digital-to-analog conversion, and includes a digital signal processing unit 11C and a digital-to-analog conversion processing unit 12. As will be described in detail later, the digital signal processing unit 11C determines the interpolation timing of an interpolated digital signal using different signal paths depending on the frequency of the input digital signal. The DA conversion processing unit 12 in this embodiment has the same configuration as the DA conversion processing unit 12 in the first embodiment, and performs the same functions.

[0155] The digital signal processing unit 11C receives an input digital signal ID[N] output from an analog / digital signal processing device (not shown), an input clock signal ICLK, a sampling clock signal PCLK, a serial data processing clock signal SCLK, and a selection signal SEL. An example of the input digital signal ID[N] is a 16-bit (N=16) audio data signal.

[0156] The digital signal processing unit 11C included in the digital signal processing device 1C has a selection unit 115 in addition to the configuration of the digital signal processing device 1B according to the second embodiment. The selection unit 115 is provided between the oversampling unit 114 and the downsampling unit 111. That is, the selection unit 115 is provided after the oversampling unit 114 and before the downsampling unit 111. The selection unit 115 receives the input digital signal ID[N], the selection signal SEL, and the oversampling digital signal OD[N]. The output of the selection unit 115 is connected to the inputs of the downsampling unit 111 and the interpolation timing determination unit 112, respectively. The input digital signal ID[N] includes a first digital signal D1[N] and a second digital signal D2[N].

[0157] The selection unit 115 selects either a first signal path RT1 that inputs the first digital signal D1[N] and the second digital signal D2[N] to the downsampling unit 111 without passing through the oversampling unit 114, or a second signal path RT2 that inputs the first digital signal D1[N] and the second digital signal D2[N] to the downsampling unit 111 via the oversampling unit 114. When the selection unit 115 selects the first signal path RT1, the first digital signal D1[N] and the second digital signal D2[N] are included in an input digital signal ID[N] that is input to the selection unit 115 through the first signal path RT1 and then input to the downsampling unit 111. On the other hand, when the selection unit 115 selects the second signal path RT2, the first digital signal D1[N] and the second digital signal D2[N] are included in an oversampled digital signal OD[N] that is generated by the oversampling unit 114 and input to the selection unit 115, by passing through the second signal path RT2, and then input to the downsampling unit 111.

[0158] The selection unit 115 selects the first signal path RT1 when the signal level of the selection signal SEL is, for example, low, and selects the second signal path RT2 when the signal level of the selection signal SEL is, for example, high. In this embodiment, the selection signal SEL is input, for example, from an analog / digital signal processing device (not shown) connected in a stage preceding the digital signal processing device 1C. However, if a predetermined sampling rate of the input digital signal ID[N] is determined, the signal level of the selection signal SEL may be set in advance to correspond to that sampling rate.

[0159] When the sampling rate of the input digital signal ID[N] is high, i.e., when the frequency of the input digital signal ID[N] is high, the analog-digital signal processing device outputs the input digital signal ID[N] and, for example, a selection signal SEL having a low signal level to the selection unit 115. As a result, the selection unit 115 outputs the input digital signal ID[N] input through the first signal path RT1 to the downsampling unit 111. The input digital signal ID[N] includes a first digital signal D1[N], a second digital signal D2[N], and a plurality of third digital signals D3[N]j (j is a natural number).

[0160] When the sampling rate of the input digital signal ID[N] is low, i.e., when the frequency of the input digital signal ID[N] is low, the analog-digital signal processing device outputs the input digital signal ID[N] together with a selection signal SEL, for example, at a high signal level. This causes the selection unit 115 to output an oversampled digital signal OD[N], which includes the input digital signal ID[N] input via the second signal path RT2, to the downsampling unit 111. The oversampled digital signal OD[N] includes a first digital signal D1[N], a plurality of third digital signals D3[N]j (j is a natural number), and a second digital signal D2[N].

[0161] When the selection unit 115 selects the first signal path RT1, the digital signal processing device 1C has a configuration similar to that of the digital signal processing device 1A according to the first embodiment. On the other hand, when the selection unit 115 selects the second signal path RT2, the digital signal processing device 1C has a configuration similar to that of the digital signal processing device 1B according to the second embodiment. Therefore, the digital signal processing device 1C can obtain the effects of both the digital signal processing devices 1A and 1B.

[0162] 4-2. Operation of digital signal processing device When the selection unit 115 selects the first signal path RT1, the operation of the digital signal processing device 1C is the same as the operation of the digital signal processing device 1A according to the first embodiment. When the selection unit 115 selects the second signal path RT2, the operation of the digital signal processing device 1C is the same as the operation of the digital signal processing device 1B according to the second embodiment. Therefore, a description of the operation of the digital signal processing device 1C will be omitted.

[0163] As described above, the digital signal processing device 1C is a device that processes digital signals used in digital-to-analog conversion, and is equipped with a selection unit 115. Depending on the frequency of the input digital signal ID[N], the digital signal processing device 1C can operate as the digital signal processing device 1A according to the first embodiment or as the digital signal processing device 1B according to the second embodiment. Therefore, the digital signal processing device 1C can obtain the same effect as the digital signal processing device 1A or the digital signal processing device 1B, depending on the frequency of the input digital signal ID[N].

[0164] The present invention is not limited to the first embodiment, the second embodiment, and the modified examples described above, and various modifications are possible. The relationship between the rising and falling edges of various signals and various clock signals is not limited to those in the first embodiment, the second embodiment, and the modified example, as long as a logical contradiction occurs in the digital signal processing device and is set accordingly.

[0165] The technical scope of the present invention is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to the object of the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of inventive features defined by the claims, but can be defined by any desired combination of specific features from among all the respective disclosed features. [Explanation of symbols]

[0166] 1A, 1B, 1C Digital signal processing device 11A, 11bB, 11C Digital signal processing unit 12 Digital-to-analog conversion processing section (DA conversion processing section) 111 Downsampling section 112 Interpolation timing determination unit 113 Parallel-serial conversion unit 114 Oversampling section 114a Zero point insertion section 114b Filter section 115 Selection Section 120 output amplifier 121 Serial-parallel conversion unit 122, 123a, 123b, 125a, 125b, 125c Delay flip-flops (DFFs) 124 Interpolation data calculation unit 126 Interpolation part 127 Output clock signal generator 128 Digital-to-analog converter (DA converter) 129 Low-pass filter Cdfc,Cdfi,Cdfn,Cdfo Distortion frequency characteristics Cgfc, Cgfi, Cgfn, Cgfo Gain frequency characteristics D1[N] First digital signal D2[N] Second digital signal D3[N]j(j=1~7) Third digital signal DD[N] Downsampled digital signal ID[N] Input digital signal E, Er1, Er2, Er3, Er4 Error FBa, FBc, FBm, FBo, FBoc, FBoi, FBon, FBum frequency bands FBe,FBs bandwidth fs sampling frequency fsa,fsb,fsc frequencies ICLK Input clock signal LRCK Data selection clock signal OCLK Output clock signal OD[N] Oversampled digital signal P1 First period P2 Second period P3 Third Cycle P4 Fourth Cycle P12,P23 period PCLK Sampling clock signal RT1 First signal path RT2 Second signal path Sav1, Sav2, Sav3, Sav4 digital signal SCLK Serial data processing clock signal Soc, Soi, Son, Soo, Sout output signals SDATA Serial Data Signal SEL selection signal Sic1,Sic2,Sic3,Sic4,Sii,Sii1,Sii2,Sii3,Sii4 Interpolated digital signals Sii[N] Interpolated digital signal SOA Analog Signal So[N] Output digital signal SRa, SRb, SRc, SRn setting range Ss1, Ss2, Ss3, Ss4, Ss5, Ssj, Sampling digital signal TG1, TG2, TG3, TG4, TGi interpolation timing

Claims

1. A digital signal processing device that processes a digital signal used for digital-to-analog conversion, a calculation unit that calculates a third value, which is a value of an interpolated digital signal to be inserted between a first digital signal having a first value and a second digital signal having a second value and input after the first digital signal, as an average value of the first value and the second value; a determination unit that determines an interpolation timing for interpolating the interpolated digital signal based on the first value, the second value, the third value, and values of each of a plurality of third digital signals that are input during a period between the first digital signal and the second digital signal; an interpolation unit that interpolates the interpolated digital signal at the interpolation timing determined by the determination unit; A digital signal processing device comprising:

2. a downsampling unit that selectively samples the first digital signal at a second frequency lower than the first frequency from input digital signals including the first digital signal, the plurality of third digital signals, and the second digital signal, which are continuously input at a first frequency; The determination unit determines, as the interpolation timing, a timing at which a signal having a value closest to the third value among the input digital signals is input.

2. The digital signal processing device according to claim 1.

3. an oversampling unit that performs interpolation filtering by inserting a plurality of zero points at a predetermined timing between the first digital signal and the second digital signal that are input consecutively at a third frequency and then passing the signals through a low-pass filter, thereby generating an oversampled digital signal of a fourth frequency higher than the third frequency, the oversampled digital signal including the plurality of third digital signals between the first digital signal and the second digital signal; a downsampling unit that samples the first digital signal from the oversampled digital signals continuously output from the oversampling unit to generate a downsampled digital signal having the same frequency as the third frequency; Equipped with the oversampling unit outputs the oversampled digital signal to the determination unit; The determination unit determines, as the interpolation timing, a timing at which a signal having a value closest to the third value among the oversampled digital signals is input.

2. The digital signal processing device according to claim 1.

4. a selection unit that selects either a first signal path that inputs the first digital signal and the second digital signal to the downsampling unit without passing through the oversampling unit, or a second signal path that inputs the first digital signal and the second digital signal to the downsampling unit via the oversampling unit.

4. The digital signal processing device according to claim 3.

5. The determination unit if the period between the determined interpolation timing and the timing at which the first digital signal is input is shorter than one-third of the period from the first digital signal to the second digital signal, re-determine the interpolation timing to be one-third of the period from the input of the first digital signal; If the period between the determined interpolation timing and the timing at which the first digital signal is input is longer than two-thirds of the period, the interpolation timing is redetermined to be the timing at which the two-thirds of the period has elapsed since the first digital signal was input. A digital signal processing device according to any one of claims 1 to 4.

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