Semiconductor device

Abstract

To provide a semiconductor device capable of optimizing switching characteristics and increasing power density.SOLUTION: A semiconductor device (100) includes: a plurality of semiconductor chips (1, 2, and 3) mounted on an insulating substrate (10); and a case (20) housing the semiconductor chips. The case (20) has: a gate terminal (21); a source sense terminal (22); a source terminal (23); and a drain terminal (24). The height of the gate terminal (21) and the height of the source sense terminal (22) are different from each other, and the height of the source terminal (23) is lower than the height of the gate terminal (21) and the height of the source sense terminal (22).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For the purpose of facilitating wire bonding in the manufacture of semiconductor devices and miniaturizing semiconductor devices, techniques have been proposed for providing different heights for multiple terminals (bus bars, leads, pads, etc.) provided on semiconductor devices (for example, Patent Documents 1 and 2 listed below). Note that the "height" of the terminals here refers to the height of the terminal attachment position, not the thickness of the terminals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-89548 [Patent Document 2] Japanese Patent Application Publication No. 6-181279 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 proposes a configuration in which the heights of two main terminals (source terminal and drain terminal) are different, but does not take into consideration the signal terminals (gate terminal, source sense terminal, etc.), leaving room for improvement in terms of switching characteristics.

[0005] In Patent Document 2, the height of the signal terminals is also taken into consideration, with the main terminals arranged in the upper row and the signal terminals arranged in the lower row. However, with this arrangement, the main wires connected to the main terminals become longer, which raises concerns about increased heat generation by the main wires. In order to achieve a high power density in semiconductor devices, it is necessary to shorten the main wires.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that can optimize switching characteristics and achieve high power density. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure comprises an insulating substrate, a drain pattern and a gate pattern formed on an upper surface of the insulating substrate, a plurality of semiconductor chips each having a drain electrode bonded to the drain pattern on its lower surface and a source electrode and a gate electrode on its upper surface, and a case that houses the plurality of semiconductor chips and has a gate terminal, a source sense terminal, a source terminal and a drain terminal, wherein the drain terminal is connected to the drain pattern via a first wire, the source terminal is connected to the source electrodes of the plurality of semiconductor chips via a second wire, the gate terminal is connected to the gate pattern via a third wire, the gate pattern is connected to the gate electrodes of the plurality of semiconductor chips via a fourth wire, and the source sense terminal is connected to the source electrode of any one of the plurality of semiconductor chips via a fifth wire, and the height of the gate terminal and the height of the source sense terminal are different from each other, and the height of the source terminal is lower than the height of the gate terminal and the height of the source sense terminal. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to optimize the switching characteristics of a semiconductor device and achieve high power density. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> 1 and 2 are diagrams showing the configuration of a semiconductor device 100 according to the first embodiment, and respectively show a plan view and a cross-sectional view of the semiconductor device 100.

[0011] The semiconductor device 100 includes a plurality of semiconductor chips mounted on an insulating substrate 10. The insulating substrate 10 is formed of, for example, ceramic. In this embodiment, an example is shown in which a first semiconductor chip 1, a second semiconductor chip 2, and a third semiconductor chip 3 are mounted on the insulating substrate 10 as the plurality of semiconductor chips. The first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are, for example, switching elements for power control, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). Note that FIG. 2 representatively shows the first semiconductor chip 1.

[0012] The first semiconductor chip 1 has a source electrode 1s and a gate electrode 1g on its top surface and a drain electrode 1d on its bottom surface. The second semiconductor chip 2 has a source electrode 2s and a gate electrode 2g on its top surface and a drain electrode 2d on its bottom surface. The third semiconductor chip 3 has a source electrode 3s and a gate electrode 3g on its top surface and a drain electrode 3d on its bottom surface.

[0013] A drain pattern 11 and a gate pattern 12 made of, for example, copper are formed on the upper surface of the insulating substrate 10, and the drain electrode 1d of the first semiconductor chip 1, the drain electrode 2d of the second semiconductor chip 2, and the drain electrode 3d of the third semiconductor chip 3 are each joined to the drain pattern 11 by a joining material 41 such as solder.

[0014] Further, a metal pattern 13 made of, for example, copper is formed on the lower surface of the insulating substrate 10, and the metal pattern 13 is joined to a copper base plate 15 by a joining material 42 such as solder.

[0015] A case 20 is bonded to the periphery of base plate 15, and houses insulating substrate 10 and first semiconductor chip 1, second semiconductor chip 2, and third semiconductor chip 3 mounted thereon. Case 20 is provided with a gate terminal 21 and a source sense terminal 22, which are signal terminals, and a source terminal 23 and a drain terminal 24, which are main terminals through which a large current flows. These terminals are insert-molded into case 20. The use of insert electrodes instead of outsert electrodes contributes to reducing the assembly flow.

[0016] The gate terminal 21, the source sense terminal 22, and the source terminal 23 are arranged along the same side of the case 20. The gate terminal 21 and the source sense terminal 22 are arranged further outward than the source terminal 23. The height of the gate terminal 21 and the height of the source sense terminal 22 are different from each other. The height of the source terminal 23 is lower than the height of the gate terminal 21 and the source sense terminal 22. In addition, the gate pattern 12 on the insulating substrate 10 is arranged between the drain pattern 11 and the source terminal 23.

[0017] The drain terminal 24 is connected to the drain pattern 11 via a first wire 31. The source terminal 23 is connected to the source electrode 1s of the first semiconductor chip 1, the source electrode 2s of the second semiconductor chip 2, and the source electrode 3s of the third semiconductor chip 3 via a second wire 32.

[0018] The gate terminal 21 is connected to the gate pattern 12 via a third wire 33. The gate pattern 12 is connected to the gate electrode 1g of the first semiconductor chip 1, the gate electrode 2g of the second semiconductor chip 2, and the gate electrode 3g of the third semiconductor chip 3 via a fourth wire 34.

[0019] The source sense terminal 22 is connected to any one of the source electrode 1s of the first semiconductor chip 1, the source electrode 2s of the second semiconductor chip 2, and the source electrode 3s of the third semiconductor chip 3 via a fifth wire 35.

[0020] The case 20 is filled with a sealing material 25, and the opening of the case 20 is covered with a lid .

[0021] In the semiconductor device 100 according to the first embodiment, the gate terminal 21 and the source sense terminal 22, which are signal terminals, are at different heights, which increases the degree of freedom in wire bonding, making it possible to realize a complex circuit configuration while maintaining commonality of components, and optimizing switching characteristics. In addition, because the source terminal 23 is located at the bottom, the second wire 32, which is the main wire through which a large current flows, can be shortened, suppressing heat generation and contributing to a higher power density of the semiconductor device 100.

[0022] Furthermore, in the first embodiment, the height of the source sense terminal 22 is made higher than the height of the gate terminal 21. That is, from highest to lowest, the order is source sense terminal 22, gate terminal 21, and source terminal 23. This allows for different reference potentials for the source sense, making it possible to appropriately control the positive feedback and negative feedback applied during switching operations.

[0023] 1, in the first embodiment, the third wire 33 connected to the gate terminal 21 and the fifth wire 35 connected to the source sense terminal 22 are parallel to each other in a plan view. The first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3, which are switching elements, are easily affected by source impedance, which can easily disrupt the current balance between the chips. However, by preventing the fifth wire 35 connected to the source sense terminal 22 from intersecting with the third wire 33 connected to the gate terminal 21, the source sense reference potential can be optimized, and an improvement in the current balance can be expected.

[0024] When the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are formed of a wide bandgap semiconductor such as silicon carbide (SiC), it is expected that they will be driven at high speed. When the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are driven at high speed, the influence of source impedance variations on switching becomes significant. Therefore, making the third wire 33 and the fifth wire 35 parallel to each other is particularly effective when the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3 are formed of a wide bandgap semiconductor.

[0025] <Embodiment 2> 3 is a plan view showing the configuration of a semiconductor device 100 according to embodiment 2. The cross-sectional view of the semiconductor device 100 is the same as FIG.

[0026] In the semiconductor device 100 according to the second embodiment, in a plan view, the fifth wire 35 connected to the source sense terminal 22 intersects both the second wire 32 connected to the source terminal 23 and the third wire 33 connected to the gate terminal 21. This makes it possible to realize a space-saving and complex circuit configuration.

[0027] However, as mentioned above, it should be noted that when the third wire 33 and the fifth wire 35 cross each other, the first semiconductor chip 1, the second semiconductor chip 2, and the third semiconductor chip 3, which are switching elements, are more susceptible to the influence of the source impedance.

[0028] <Third Embodiment> 4 is a cross-sectional view showing the configuration of a semiconductor device 100 according to embodiment 3. The plan view of the semiconductor device 100 is the same as FIG.

[0029] In the semiconductor device 100 according to the third embodiment, the distance D from the side surface of the case 20 to the source sense terminal 22 and the gate terminal 21 is set to 3.0 mm or more, thereby improving the reliability of the semiconductor device 100 and the strength of the semiconductor device 100 during assembly.

[0030] <Fourth Embodiment> 5 is a cross-sectional view showing the configuration of a semiconductor device 100 according to embodiment 4. The plan view of the semiconductor device 100 is the same as FIG.

[0031] In the semiconductor device 100 according to the fourth embodiment, the distance C between the third wire 33 connected to the gate terminal 21 and the fifth wire 35 connected to the source sense terminal 22 is set to 3.0 mm or more.

[0032] For example, a customer who purchases semiconductor device 100 may mistakenly wire source sense terminal 22 with the drain sense terminal when installing and wiring semiconductor device 100. However, by ensuring a distance C of 3.0 mm or more between third wire 33 and fifth wire 35, discharge between drain and gate or drain and source can be prevented, and discharge breakdown can be prevented. Assuming that the dielectric strength of air is 1 kV per mm, this is a design that will not cause discharge breakdown even if a voltage of 3 kV or more is applied between drain and gate or drain and source.

[0033] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0034] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0035] (Appendix 1) an insulating substrate; a drain pattern and a gate pattern formed on an upper surface of the insulating substrate; a plurality of semiconductor chips each having a drain electrode bonded to the drain pattern on its lower surface and a source electrode and a gate electrode on its upper surface; a case that houses the plurality of semiconductor chips and has a gate terminal, a source sense terminal, a source terminal, and a drain terminal; Equipped with the drain terminal is connected to the drain pattern via a first wire; the source terminal is connected to the source electrodes of the plurality of semiconductor chips via second wires; the gate terminal is connected to the gate pattern via a third wire; the gate pattern is connected to the gate electrodes of the plurality of semiconductor chips via fourth wires; the source sense terminal is connected to the source electrode of any one of the plurality of semiconductor chips via a fifth wire; the height of the gate terminal and the height of the source sense terminal are different from each other; the height of the source terminal is lower than the height of the gate terminal and the height of the source sense terminal; Semiconductor device.

[0036] (Appendix 2) The height of the source sense terminal is greater than the height of the gate terminal. 2. The semiconductor device according to claim 1.

[0037] (Appendix 3) The third wire and the fifth wire are parallel to each other in a plan view. 10. The semiconductor device according to claim 1 or 2.

[0038] (Appendix 4) The plurality of semiconductor chips are formed of wide bandgap semiconductors. 4. The semiconductor device according to claim 3.

[0039] (Appendix 5) In a plan view, the fifth wire intersects both the second wire and the third wire. 10. The semiconductor device according to claim 1 or 2.

[0040] (Appendix 6) The distance from the side surface of the case to the source sense terminal and the gate terminal is 3.0 mm or more. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0041] (Appendix 7) The distance between the third wire and the fifth wire is 3.0 mm or more. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Explanation of symbols]

[0042] 100 semiconductor device, 1 first semiconductor chip, 2 second semiconductor chip, 3 third semiconductor chip, 1s, 2s, 3s source electrode, 1d, 2d, 3d drain electrode, 1g, 2g, 3g gate electrode, 10 insulating substrate, 11 drain pattern, 12 gate pattern, 13 metal pattern, 15 base plate, 20 case, 21 gate terminal, 22 source sense terminal, 23 source terminal, 24 drain terminal, 25 sealing material, 26 lid, 31 first wire, 32 second wire, 33 third wire, 34 fourth wire, 35 fifth wire, 41, 42 bonding material.

Claims

1. an insulating substrate; a drain pattern and a gate pattern formed on an upper surface of the insulating substrate; a plurality of semiconductor chips each having a drain electrode bonded to the drain pattern on its lower surface and a source electrode and a gate electrode on its upper surface; a case that houses the plurality of semiconductor chips and has a gate terminal, a source sense terminal, a source terminal, and a drain terminal; Equipped with the drain terminal is connected to the drain pattern via a first wire; the source terminal is connected to the source electrodes of the plurality of semiconductor chips via second wires; the gate terminal is connected to the gate pattern via a third wire; the gate pattern is connected to the gate electrodes of the plurality of semiconductor chips via fourth wires; the source sense terminal is connected to the source electrode of any one of the plurality of semiconductor chips via a fifth wire; the height of the gate terminal and the height of the source sense terminal are different from each other; the height of the source terminal is lower than the height of the gate terminal and the height of the source sense terminal; Semiconductor device.

2. The height of the source sense terminal is greater than the height of the gate terminal. The semiconductor device according to claim 1 .

3. The third wire and the fifth wire are parallel to each other in a plan view.

3. The semiconductor device according to claim 1.

4. The plurality of semiconductor chips are formed of wide bandgap semiconductors. The semiconductor device according to claim 3 .

5. In a plan view, the fifth wire intersects both the second wire and the third wire.

3. The semiconductor device according to claim 1.

6. The distance from the side surface of the case to the source sense terminal and the gate terminal is 3.0 mm or more.

3. The semiconductor device according to claim 1.

7. The distance between the third wire and the fifth wire is 3.0 mm or more.

3. The semiconductor device according to claim 1.

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