Semiconductor device package and forming method

Abstract

To provide a semiconductor device package and a method of forming the same.SOLUTION: A semiconductor device package comprises a semiconductor switching device having a body including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the first side of the semiconductor switching device body, and has a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the first side of the gate terminal, and coupled electrically in series with the gate terminal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor device packages and methods of forming semiconductor device packages. [Background technology]

[0002] Power conversion devices, such as silicon carbide (SiC) power devices, are widely used in conventional electrical systems to convert electrical power from one form to another for consumption by a load. Many power electronics systems utilize various semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and other suitable transistors). Summary of the Invention [Means for solving the problem]

[0003] The switching behavior of conventional power semiconductor switching devices (e.g., MOSFETs) is controlled by gate capacitance recharge. Gate capacitance recharge is often controlled via a gate resistor placed in series with the gate terminal of the switching device. The dynamic switching performance (e.g., switching speed) of the semiconductor switching device can be adjusted based on the value of the gate resistor. The gate resistor can affect many other dynamic performance characteristics of the semiconductor switching device, including switching losses, reverse bias safe operating area, and short circuit safe operating area. [Brief explanation of the drawings]

[0004] [Figure 1] 1 is a cross-sectional view of a semiconductor device package according to various aspects described herein. [Figure 2] FIG. 2 is a cross-sectional view of another semiconductor device package in accordance with various aspects described herein. [Figure 3] FIG. 1 is an exemplary flowchart diagram of a method for manufacturing a semiconductor device package in accordance with various aspects described herein. DETAILED DESCRIPTION OF THE INVENTION

[0005] Aspects of the present disclosure may be implemented in any environment, apparatus, or method for semiconductor device packaging, regardless of the function performed by the semiconductor device.

[0006] As used herein, the term "set" or a "set" of elements may refer to any number of elements, including only one. When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to "one aspect" or "an aspect" of the present disclosure are not intended to be interpreted as excluding the existence of additional aspects that also incorporate the recited features. The shapes, positions, and alignments of the presently disclosed features are illustrated and described as relatively idealized (e.g., squares, rectangles, and hexagons depicted with perfectly straight, aligned features) for simplicity. However, as will be appreciated by those skilled in the art, process variations and technological constraints may result in designs with less than ideal or irregular features, and still be consistent with the present disclosure.

[0007] Additionally, although terms such as "voltage," "current," and "power" may be used herein, it will be apparent to those skilled in the art that these terms may be interrelated when describing aspects of electrical circuits or circuit operation.

[0008] All directional references (e.g., radial, axial, upper, lower, upward, downward, left, right, lateral, front, rear, top, bottom, above, below, vertical, horizontal, clockwise, counterclockwise) are used for identification purposes only to aid the reader's understanding of this disclosure and do not imply any limitation with respect to their particular location, orientation, or application. References to connections (e.g., attached, coupled, connected, and joined) should be interpreted broadly unless otherwise indicated and can include intermediate members between groups of elements and relative movement between the elements. Thus, references to connections do not necessarily imply that two elements are directly connected and in fixed association with each other. In non-limiting examples, connections and disconnections can be selectively configured to provide, enable, disable, etc., an electrical connection between respective elements. Additionally, as used herein, "electrical connection" or "electrical coupling" can include wired or wireless connections. The exemplary figures are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the figures attached hereto may vary.

[0009] As used herein, a controllable switching element or "switch" is an electrical device that may be controllable to switch between a first mode of operation in which the switch is "closed" to transmit current from an input switch to an output switch, and a second mode of operation in which the switch is "open" to prevent current from passing between the input switch and the output switch. In a non-limiting example, connections and disconnections, such as connections enabled or disabled by a controllable switching element, may be selectively configured to provide, enable, disable, etc., electrical connection between the respective elements.

[0010] A conventional semiconductor device package, such as a power overlay module (POL), for example, typically includes a set of semiconductor devices (e.g., MOSFETs) having conductive contacts on two opposing sides (e.g., top and bottom sides, respectively). The bottom sides of the semiconductor devices are soldered to one side (e.g., top side) of a metal-insulator substrate layer (e.g., a direct bond copper (DBC) substrate). A dielectric layer is disposed on the top sides of the semiconductor devices and may be bonded to the devices using an adhesive. A metallization or conductive layer is typically deposited on top of the dielectric layer through vias or openings defined in the dielectric layer, allowing the metallization layer to be electrically connected to the top sides of the semiconductor devices through the dielectric layer.

[0011] For example, a semiconductor device may typically include a MOSFET having a source terminal and a gate terminal formed on a top surface of the semiconductor device. Conventional semiconductor devices may be manufactured with an “in-chip” internal gate resistor located within the semiconductor device chip and coupled to the gate terminal through a conductive line located within the semiconductor device chip. However, in many cases, different values of gate resistor may be desired depending on the particular application or end use of the semiconductor device. This is typically addressed by semiconductor chip manufacturers by defining multiple MOSFET chips, each with a different respective gate resistance value and each with a different respective part number. However, this approach requires different masking processes for each chip and increased costs associated with handling additional part numbers, inventory, etc. In some cases, semiconductor device manufacturers have addressed this challenge by adding individual “off-chip” gate resistors at the gate driver level, for each die on a power board, or for multiple dies. For example, conventional POL modules may typically include individual gate resistors located “off-chip,” or in some cases, remote from the MOSFET. Typically, a metallization layer may be arranged to electrically couple the individual gate resistor to the gate terminal of the MOSFET. In some conventional arrangements, a separate gate resistor may be coupled to the gate terminal of the MOSFET via a wirebond or other conductor separate from the metallization layer.

[0012] Referring to FIG. 1 , a non-limiting embodiment of a semiconductor device package 10 is shown. The semiconductor device package 10 may include a set of semiconductor devices 12 having a first surface 12 a (e.g., a top surface) and an opposing second surface 12 b (e.g., a bottom surface). The second surfaces 12 b of the semiconductor devices may be coupled to a substrate structure 14 (e.g., to the top surface of the substrate structure 14). Each semiconductor device 12 may include a body 13 having a first surface 13 a (e.g., a top surface) and an opposing second surface 13 b (e.g., a bottom surface). Each semiconductor device 12 may further include a set of first contact pads 31 disposed on the first surface 12 a of the semiconductor device and a set of second contact pads 32 disposed on the second surface 12 b of the semiconductor device. A first gate resistor 15 may be coupled to at least one semiconductor device 12. For example, the first gate resistor 15 may be coupled to a corresponding first contact pad 31 of the at least one semiconductor device 12.

[0013] In the non-limiting embodiment shown in FIG. 1 , the substrate structure 14 may include an insulator plate 16 (e.g., disposed between a first conductive layer 18 (e.g., a top layer) and a second conductive layer 20 (e.g., a bottom layer)). The dielectric layer 24 may include a first surface 24 a (e.g., an upper surface) and an opposing second surface 24 b (e.g., a lower surface). The second surface 24 b of the dielectric layer may be disposed over the first surface 12 a of the semiconductor device 12. The dielectric layer 24 may define a set of openings 25 therethrough that extend from the first surface 24 a of the dielectric layer to the second surface 24 b of the dielectric layer. The metal interconnect layer 22 (e.g., copper traces) may include a first surface 22 a (e.g., an upper surface) and an opposing second surface 22 b (e.g., a lower surface) and may be formed and patterned over the top surface 24 a of the dielectric layer. Metal interconnect layer 22 may further extend through a set of openings 25 to define a set of vias 27 .

[0014] The semiconductor devices 12 may be in the form of dies, diodes, other power electronic devices, or passive devices such as capacitors or resistors. In addition to the set of semiconductor devices 12, embodiments of the semiconductor device package 10 may also include any number of additional circuit components, such as, for example, gate drivers (not shown). While FIG. 1 shows three semiconductor devices 12 in the semiconductor device package 10, other embodiments are not so limited, and greater or fewer semiconductor devices 12 may be included in the semiconductor device package 10. The semiconductor devices 12 may be attached to the substrate structure 14 by a soldering process, adhesive bonding, sintered silver bonding, or the like.

[0015] In a non-limiting embodiment, the body 13 may be defined by a die comprising silicon carbide. The semiconductor device 12 may include a so-called "vertical conduction" type semiconductor device 12 that allows electrical I / O interconnections to be made via first contact pads 31 disposed on a first side 13a of the semiconductor device and via second contact pads 32 disposed on an opposing second side 13b. Depending on the application, the set of first contact pads 31 and the set of second contact pads 32 may operably couple the semiconductor device 12 to an external circuit (not shown) and may be electrically coupled to internal elements within the semiconductor device 12 via the metal interconnect layer 22 and the first conductive layer 18, respectively.

[0016] For example, in a non-limiting embodiment, the semiconductor device 12 may include a MOSFET semiconductor device 12, and the first set of contact pads 31 may include a source terminal 34 and a gate terminal 35. The gate terminal 35 may define an outward-facing first surface 35a (i.e., with respect to the semiconductor device body 13) and an inward-facing second surface 35b (i.e., with respect to the semiconductor device body 13) opposite the first surface 35a. The source terminal 34 may define an outward-facing first surface 34a (i.e., with respect to the semiconductor device body 13) and an inward-facing second surface 34b opposite the first surface 34a.

[0017] Additionally, spaces or gaps defined between the sets of semiconductor devices 12 may optionally be filled with a dielectric fill material 33. In various embodiments, the dielectric fill material 33 may include, for example, an underfill (e.g., capillary underfill or no-flow underfill), an encapsulation, a polymeric material such as a silicone, a molding compound, or the like.

[0018] The first gate resistor 15 may be disposed directly on one of the first contact pads 31. For example, in a non-limiting embodiment, the first gate resistor 15 may be defined on the first surface 35a of the gate terminal 35. In this sense, the first gate resistor 15 may be disposed outside the semiconductor device body 13 in direct contact with the gate terminal 35. In an embodiment, the first gate resistor 15 may be in direct contact with the first surface 35a of the gate terminal 35. In a non-limiting embodiment, the first gate resistor 15 may be physically supported by the gate terminal 35. In an embodiment, the gate terminal 35 may be electrically coupled in series with the first gate resistor 15. In a non-limiting embodiment, the first gate resistor 15 may have a resistance value in a range of 0.1 ohms to 100 ohms in series with the gate terminal 35.

[0019] The first gate resistor 15 may be at least partially formed or applied onto one of the first contact pads 31 by a “direct-write” type application to form, define, or possibly structurally position the first gate resistor 15 on the first contact pad 31 without adding to or modifying the resistance of the first contact pad 31 itself. For example, the first gate resistor 15 may be applied onto one of the first contact pads 31 using an inkjet or aerosol jet printer type application device, where a resistive material (e.g., a carbon-based material) is precisely deposited or printed onto, on, around, or a combination thereof, one of the first contact pads 31. However, it will be recognized that any combination of jetting, dispensing, laser writing, or printing may be employed in such a direct-write application.

[0020] In other non-limiting embodiments, any other suitable additional method of applying resistive material to define a first gate resistor on the gate terminal 35 may also be used without departing from the scope of the present disclosure.

[0021] The dielectric layer 24 may be disposed on the first surface 13a (e.g., the top surface) of the set of semiconductor devices 12. For example, in a non-limiting embodiment, an adhesive (not shown) may be used to attach the dielectric layer 24 to the set of semiconductor devices 12. In a non-limiting embodiment, the dielectric layer 24 may include a lamination or a film. In some non-limiting embodiments, the dielectric layer 24 may be formed from any of a variety of dielectric materials, such as polytetrafluoroethylene (PTFE), a polysulfone material, another polymer film, such as a liquid crystal polymer (LCP) or a polyimide material. The dielectric layer 24 may be at least partially applied onto the semiconductor devices 12 by a “direct-write” type application. For example, the dielectric layer 24 may be applied onto the semiconductor devices 12 using an inkjet printer type application device, in which a dielectric material (e.g., a polymer, epoxy, or polyimide) is precisely deposited / printed above, on, and around the semiconductor devices 12 and into the spaces between the devices. However, it is recognized that any combination of jetting, dispensing, laser writing, or printing may be employed in such direct-write applications. In employing direct-write application techniques, areas on semiconductor device 12 onto which electrical connections are to be made are left open or exposed to define a set of openings 25. A cleaning process using a laser process, a dry process, or a wet process may be used to further clean the via openings for metallization, if desired.

[0022] A metal interconnect layer 22 may be formed or patterned on the top surface 24 a of the dielectric layer. The metal interconnect layer 22 may be directly coupled to the semiconductor device 12 by a set of vias 27. For example, the set of vias 27 may enable electrical connection by the metal interconnect layer 22 to first contact pads 31 of the semiconductor device 12. The vias 27 may be formed or defined at locations corresponding to the first contact pads 31 formed on the semiconductor device 12, through which electrical connection may be made to the semiconductor device 12.

[0023] In embodiments employing direct-write application techniques, the area above semiconductor device 12 upon which a resistor is formed may further remain open, i.e., via an opening 25 in the dielectric layer defined or formed corresponding to (e.g., above) first gate resistor 15. A cleaning process using a laser, dry, or wet process may be used to further clean via opening 25 for metallization as needed to allow metal interconnect layer 22 to extend through the opening to define via 27 directly coupled with first gate resistor 15.

[0024] It will be appreciated that in embodiments employing an optional adhesive to attach the set of semiconductor devices 12 to the dielectric layer 24, the set of openings 25 similarly extend through the adhesive (not shown). The set of openings 25 may be arranged to have any desired size and spacing, extending through the dielectric layer 24 or the adhesive, or both, to enable electrical connection from the metal interconnect layer 22 to one or more of the first contact pads 31 of at least one of the semiconductor devices 12. In a non-limiting embodiment, the metal interconnect layer 22 may include copper deposited (e.g., electroplated) on the dielectric layer 24 and through the set of openings 25 to enable electrical connection through the dielectric layer 24, i.e., from the metal interconnect layer 22 to the first contact pads 31 of the semiconductor devices 12. The metal interconnect layer 22 may have a thin (e.g., less than 1000 micrometers thick), planar interconnect structure equipped to form I / O connections (not shown) to and from the semiconductor devices 12.

[0025] According to one non-limiting embodiment, the metal interconnect layer 22 may be formed by applying a metal layer or material, such as using a sputtering and electroplating process, and then patterning the applied metal material into the metal interconnect layer 22 having the desired shape. That is, the metal interconnect layer 22 may be formed by applying a titanium or other suitable adhesion layer and a copper seed layer via a sputtering and / or evaporation process, followed by electroplating additional copper onto those layers to increase the thickness of the metal interconnect layer 22 and form copper traces. According to another embodiment, the metal interconnect layer 22 may be formed by a direct-write process, in which a metal material is directly written or printed to form the interconnects. In a non-limiting embodiment, the vias 27 may be filled using a via-fill material, such as a conductive ink, adhesive, or paste, which is later cured to enhance the electrical, thermal, or mechanical properties of the metal interconnect layer 22. Other additional methods of applying metal interconnects may also be used. In another embodiment, a printing and plating process may be used where a thin metal layer is printed using a metallic ink and used as a seed to plate copper, and an electrolytic or electroless process is used to plate the copper, for example.

[0026] In non-limiting embodiments, the substrate structure 14 may be in the form of an insulated metal substrate (IMS), a direct bonded copper (DBC) substrate, an active metal brazed (AMB) substrate, or a printed circuit board (PCB). According to a non-limiting embodiment shown in FIG. 1 , the substrate structure 14 may include an insulator plate 16. In non-limiting embodiments, the insulator plate 16 may be formed from a thermally conductive, electrically insulating material such as aluminum, aluminum nitride, ceramic, or a combination thereof. In non-limiting embodiments, the first conductive layer 18 and the second conductive layer 20 may include a metal sheet (e.g., a copper sheet). The first conductive layer 18 and the second conductive layer 20 may be bonded to opposite sides of the insulator plate 16, for example, by a high-temperature bonding process. In various embodiments, various brazing and direct bonding techniques may be employed to form the substrate structure 14, for example, based on the material (e.g., aluminum or aluminum nitride, silicon nitride, etc.) used to form the insulator plate 16. The second conductive layer 20 may be fully or partially exposed to provide efficient heat conduction out of the semiconductor device package 10. While the embodiment shown in Figure 1 depicts the substrate structure 14 in the form of a DBC substrate, it will be recognized that aluminum or any other suitable metallic material may be used in place of copper as the first conductive layer 18 or the second conductive layer 20, or both. It is further contemplated that ceramic tile or other suitable insulator may be used in place of alumina to form the insulator plate 16 without departing from the scope of the present disclosure.

[0027] 2, another semiconductor device package 200 is shown in cross section, by way of non-limiting example. The semiconductor device package 200 includes some components similar to those shown in the semiconductor device package 100 of FIG. 1, with some parts omitted for clarity; therefore, the numbers used to designate components in FIG. 1 are also used to designate similar components in FIG. 2.

[0028] A semiconductor device package 200 is shown with a semiconductor device 12 bonded to a substrate structure 14 (e.g., on a top surface of the substrate structure 14). A first gate resistor 15 is bonded to the semiconductor device 12. A dielectric layer 24 is disposed over the semiconductor device 12 (e.g., over a first surface 12a of the semiconductor device). The dielectric layer 24 may define a set of openings 25 therethrough. A metal interconnect layer 22 (e.g., copper traces) is formed and disposed over the first surface 24a of the dielectric layer and through the openings 25, defining a set of vias 27 therethrough.

[0029] Additionally, in non-limiting embodiments, the semiconductor device package 200 may include a second gate resistor 150. For example, in non-limiting embodiments, the semiconductor device package 200 may include a semiconductor device 12 including a gate terminal 35 electrically coupled in series with a first gate resistor 15 and a second gate resistor 150. The first gate resistor may be defined on the gate terminal 35, and the second gate resistor 150 may be spaced apart from the gate terminal 35. In embodiments, a first conductive line 151 may electrically couple the first gate resistor 15 and the second gate resistor 150 in series. In some embodiments, the metal interconnect layer 22 may define the first conductive line 151. In this manner, the second gate resistor 150 may be electrically coupled in series with the gate terminal 35 and the first gate resistor 15. In a non-limiting embodiment, first gate resistor 15 and second gate resistor 150 can add a total resistance in series with gate terminal 35 in the range of 0.1 ohms to 100 ohms.

[0030] 2 , the semiconductor device may further include a third gate resistor 152. The third gate resistor may be formed in the semiconductor device body 13. The third gate resistor 152 may further be electrically coupled in series with the first gate terminal 35 using conventional techniques. For example, in non-limiting embodiments, the third gate resistor 152 may be coupled to a second side of the gate terminal via a conductive element 154 defined in the semiconductor device body 13. In some embodiments, the third gate resistor 152 may define a segment of the conductive element 154.

[0031] The second gate resistor 150 may be applied or disposed at least partially on top of the dielectric layer 24 (e.g., on top of the dielectric layer 24) by a "direct-write" type application. For example, the second gate resistor 150 may be applied on top of the dielectric layer 24 using an inkjet printer type application device, in which a resistive material (e.g., a carbon-based material) is precisely deposited or printed above, on, around, or a combination thereof, a portion of the dielectric layer 24. However, it will be recognized that any combination of jetting, dispensing, laser writing, or printing may be employed in such a direct-write application.

[0032] In other non-limiting embodiments, other additional methods may be used as well to apply a resistive material over the dielectric layer 24 to define the second gate resistor 150. In another embodiment, a printing and plating process may be used where a thin layer of resistive material (e.g., a carbon-based material) is printed using a carbon-based ink.

[0033] Metal interconnect layer 22 may then be formed or patterned over dielectric layer 24 to further define a first conductive line 151 coupled to second gate resistor 150. In other non-limiting embodiments, second gate resistor 150 may be electrically coupled to the first gate resistor by a wire or other conductive line (not shown). In some non-limiting embodiments, the second gate resistor may be positioned to define a segment of first conductive line 151.

[0034] FIG. 3 illustrates a non-limiting method 300 for forming a semiconductor device package 100, 200 according to various embodiments. In a non-limiting embodiment, the semiconductor switching device 12 includes a body 13. The body 13 may be defined by a die including silicon carbide. The method 300 includes, at 310, disposing a first gate resistor 15 on a gate terminal 35 of the semiconductor device 12. In a non-limiting embodiment, the first gate resistor 15 may be formed in place (i.e., on a first surface 35a of the first gate terminal) in a direct-write process. In some non-limiting embodiments, the gate terminal 35 may mechanically support the first gate resistor 15. In a non-limiting embodiment, the first gate resistor 15 may thus be disposed outside the semiconductor device body 13 in direct contact with the gate terminal 35. The method 300 may include, at 320, electrically insulating the gate terminal 35 from the source terminal 34 of the semiconductor device 12 by a dielectric layer 24. The method 300 may further include, at 330, defining a second gate resistor 150 spaced apart from the gate terminal 35. For example, in a non-limiting embodiment, the second gate resistor 150 may be formed by a direct write application. In a non-limiting embodiment, the second gate resistor 150 may be disposed on the first surface 24a of the dielectric layer. The method 300 may include, at 340, electrically coupling the second gate resistor 150 in series with the first gate resistor 15 via a first conductive line 151. In a non-limiting embodiment, a metal interconnect layer 22 may be deposited on the dielectric layer 24 to define the first conductive line 151. In some non-limiting embodiments, the second gate resistor 150 may define a segment of the first conductive line.

[0035] In a non-limiting aspect, semiconductor switching device 12 may further include a third gate resistor 152 defined in semiconductor body 13 and electrically coupled in series with gate terminal 35. While the present approach may be described herein in the context of a SiC MOSFET device, it should be appreciated that the present approach may be applicable to other types of material systems (e.g., silicon (Si), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C), or any other suitable semiconductor) and other types of device structures (e.g., UMOSFET, VMOSFET, insulated gate bipolar transistor (IGBT), insulated base MOS-controlled thyristor (IBMCT), or any other suitable FET and / or MOS device) utilizing n-channel or p-channel designs.

[0036] To the extent not already described, various features and structures of the various embodiments may be used in combination with one another as desired. The fact that a feature may not necessarily be present in all of the embodiments is not meant to be construed as being impossible, but rather is done for the sake of brevity. Thus, various features of the various embodiments may be mixed and matched as desired to form new embodiments, whether or not the new embodiments are explicitly described. Combinations and rearrangements of features described herein are covered by the present disclosure.

[0037] This specification uses examples to disclose aspects of the present disclosure, including the best mode, and also enables those skilled in the art to practice aspects of the present disclosure, including making and using any device or system and performing any incorporated methods. The patentable scope of the present disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they contain structural elements that are equivalent to the literal language of the claims with minor variations. Further aspects of the present invention are provided by the subject matter of the following sections.

[0038] [Item 1] A semiconductor device package including: a semiconductor switching device having a body including a first surface and an opposing second surface coupled to a substrate; a gate terminal defined on the first surface of the semiconductor switching device body, the gate terminal having the first surface and the opposing second surface facing the body; and a first gate resistor disposed on the first surface of the gate terminal, the gate resistor being electrically coupled in series with the gate terminal.

[0039] [Item 2] The semiconductor device package of any preceding item, further comprising a dielectric layer having a first surface and an opposing second surface facing the first surface of the semiconductor switching device body, the dielectric layer defining an opening therethrough.

[0040] [Item 3] The semiconductor device package of any preceding item, further comprising a metal interconnect layer disposed on the first surface of the dielectric layer and electrically coupled to the first gate resistor through the opening.

[0041] [Item 4] The semiconductor device package of any preceding item, wherein the first gate resistor is defined by direct write application onto the first surface of the gate terminal.

[0042] [Item 5] The semiconductor device package of any preceding item, further comprising a second gate resistor disposed on the first surface of the dielectric layer and spaced apart from the semiconductor switching device.

[0043] [Item 6] The semiconductor device package of any preceding item, further comprising a first conductive line electrically coupled in series with the first gate resistor and the second gate resistor.

[0044] [Item 7] The semiconductor device package of any preceding item, wherein the second gate resistor defines a segment of the first conductive line.

[0045] [Item 8] The semiconductor device package of any preceding item, wherein the second gate resistor is formed by a direct write application.

[0046] [Item 9] The semiconductor device package of any preceding item, wherein the semiconductor switching device body comprises silicon carbide.

[0047] [Item 10] The semiconductor device package of any preceding item, further comprising a third gate resistor defined within the semiconductor device body and electrically coupled in series with the gate terminal.

[0048] [Item 11] A method of forming a semiconductor device package, the method including disposing a first gate resistor on a gate terminal defined on a first surface of a semiconductor switching device, the first gate resistor being electrically coupled in series with the gate terminal.

[0049] [Item 12] The method of any preceding item, further comprising disposing a dielectric layer having a first surface and an opposing second surface facing the semiconductor switching device, the dielectric layer defining an opening therethrough.

[0050] [Item 13] The method of any preceding item, further comprising disposing a metal interconnect layer over the first surface of the dielectric layer, the metal interconnect layer electrically coupled to the first gate resistor through the opening.

[0051] [Item 14] The method of any preceding item, wherein the first gate resistor is disposed on the gate terminal by direct write application.

[0052] [Item 15] The method of any preceding item, further comprising disposing a second gate resistor on the first surface of the dielectric layer, the second gate resistor being spaced apart from the semiconductor switching device body.

[0053] [Item 16] The method of any preceding item, wherein the metal interconnect layer defines a first conductive line electrically coupled in series with the first gate resistor and the second gate resistor.

[0054] [Item 17] The method of any preceding item, wherein the second gate resistor defines a segment of the first conductive line.

[0055] [Item 18] The method of any preceding item, wherein the second gate resistor is placed by a direct write application.

[0056] [Item 19] The method of any preceding item, wherein the semiconductor switching device body comprises silicon carbide.

[0057] [Item 20] The method of any preceding item, wherein the semiconductor switching device body further includes a third gate resistor defined within the semiconductor switching device body and electrically coupled in series with the gate terminal. [Explanation of symbols]

[0058] 12 Semiconductor Devices 12a First Side 12b Second Side 13 Main body, semiconductor device main body 13a First surface, top surface 13b Second surface, bottom surface 14 Board structure 15 First gate resistor 16 Insulator plate 18 First conductive layer 20 Second conductive layer 22 Metal Interconnect Layer 22a First surface, top surface 22b Second surface, bottom surface 24 dielectric layer 24a First surface, top surface 24b Second surface, bottom surface 25 Aperture 27 Beer 31 first contact pad 32 Second Contact Pad 33 Dielectric Filling Material 34 Source terminal 34a First Side 34b Second Side 35 Gate terminal 35a First Side 35b Second Side 100 Semiconductor device package 150 Second gate resistor 151 First conductive wire 152 Third gate resistor 154 Conductive Elements 200 Semiconductor Device Packages

Claims

1. a semiconductor switching device having a body including a first surface and an opposing second surface coupled to a substrate; a gate terminal defined on a first surface of the body of the semiconductor switching device, the gate terminal having a first surface and an opposing second surface facing the body of the semiconductor switching device; a first gate resistor disposed on a first surface of the gate terminal, the gate resistor being electrically coupled in series with the gate terminal, The semiconductor device package comprises: a dielectric layer having a first surface and an opposing second surface facing the first surface of the body of the semiconductor switching device; a metal interconnect layer disposed on the first surface of the dielectric layer and electrically coupled to the first gate resistor; a second gate resistor disposed on the first surface of the dielectric layer and spaced apart from the semiconductor switching device; The metal interconnect layer defines a first conductive line electrically coupled in series with the first gate resistor and the second gate resistor.

2. The semiconductor device package of claim 1 , wherein the dielectric layer defines an opening therethrough.

3. The semiconductor device package of claim 1 , wherein the first gate resistor is defined by direct write application onto the first surface of the gate terminal.

4. The semiconductor device package of claim 1 , wherein the second gate resistor defines a segment of the first conductive line.

5. The semiconductor device package of claim 1 , wherein the second gate resistor is placed by a direct write application.

6. The semiconductor device package of claim 1 , wherein the body of the semiconductor switching device comprises silicon carbide.

7. 7. The semiconductor device package of claim 6, further comprising a third gate resistor defined within the body of the semiconductor switching device and electrically coupled in series with the gate terminal.

8. 1. A method of forming a semiconductor device package, comprising: disposing a first gate resistor on a gate terminal defined on a first surface of a body of a semiconductor switching device, the first gate resistor being electrically coupled in series with the gate terminal; disposing a dielectric layer having a first surface and an opposing second surface facing the semiconductor switching device; disposing a metal interconnect layer over a first surface of the dielectric layer, the metal interconnect layer being electrically coupled to the first gate resistor; disposing a second gate resistor on the first surface of the dielectric layer, the second gate resistor being spaced apart from the body of the semiconductor switching device; The method, wherein the metal interconnect layer defines a first conductive line electrically coupled in series with the first gate resistor and the second gate resistor.

9. The method of claim 8 , wherein the dielectric layer defines an opening therethrough.

10. The method of claim 8 , wherein the first gate resistor is disposed on the gate terminal by a direct write application.

11. The method of claim 8 , wherein the second gate resistor defines a segment of the first conductive line.

12. The method of claim 8 , wherein the second gate resistor is placed by a direct write application.

13. The method of claim 8 , wherein the body of the semiconductor switching device comprises silicon carbide.

14. 14. The method of claim 13, wherein the body of the semiconductor switching device further includes a third gate resistor defined therein and electrically coupled in series with the gate terminal.

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