Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing degradation in electrical characteristics associated with miniaturization.SOLUTION: In a semiconductor device, a transistor 100 includes: stacked layers formed of a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 in this order on an insulating surface of a substrate 100; and a third oxide semiconductor layer 133 formed so as to cover a part of the surface of the stacked layer. The third oxide semiconductor layer has a first layer in contact with the stacked layers and a second layer on the first layer. The first layer is formed of a microcrystalline layer, and the second layer is formed of a crystalline layer in which its c-axis is oriented in a vertical direction with respect to the surface of the first layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, devices, power storage devices, storage devices, driving methods thereof, or manufacturing methods thereof, as examples. Some examples include:

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0004] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology for constructing thin-film transistors (also called thin-film transistors) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors have been attracting attention.

[0005] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0007] The miniaturization of transistors is an essential technology for increasing the density of integrated circuits. As transistors become smaller, their electrical characteristics may deteriorate and variations may occur. It is known that the yield of integrated circuits decreases as transistors are miniaturized. The ball is more likely to drop.

[0008] Therefore, one embodiment of the present invention is a structure capable of suppressing deterioration in electrical characteristics that becomes significant with miniaturization. Another object of the present invention is to provide a semiconductor device with a high manufacturing yield. It is an object of the present invention to provide a semiconductor device having a structure capable of suppressing the downward movement. Another object is to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device that reduces deterioration. One of the objects of the present invention is to provide a semiconductor device having high reliability. One of the objects is to provide a semiconductor device that retains data even when the power supply is cut off. Another object of the present invention is to provide a novel semiconductor device. It shall be one.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention relates to a semiconductor device including stacked oxide semiconductor layers.

[0011] One embodiment of the present invention is a semiconductor device including a first oxide semiconductor layer and a second oxide semiconductor layer formed in this order over an insulating surface. The laminated body, a part of the side surface of the laminated body, a part of the top surface, and a part of the side surface opposite to the side surface are and a third oxide semiconductor layer formed to cover the first oxide semiconductor layer, the third oxide semiconductor layer being a stack of a first layer in contact with the first layer and a second layer on the first layer, the first layer being formed of a microcrystalline layer; The second layer is formed of a crystalline layer whose c-axis is oriented perpendicular to the surface of the first layer. The semiconductor device is characterized in that

[0012] Another embodiment of the present invention is a semiconductor device including a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer over an insulating surface. a stack formed in this order, and a source electrode layer and a drain electrode layer in contact with a part of the stack; and a layer formed on the insulating surface, the stack, the source electrode layer, and the drain electrode layer so as to be in contact with each other. a third oxide semiconductor layer formed on the first oxide semiconductor layer; and a gate insulating film formed on the third oxide semiconductor layer. a gate electrode layer formed on the gate insulating film; a source electrode layer; a drain electrode layer; and an insulating layer formed over the gate electrode layer. The third oxide semiconductor layer is in contact with the stack. and a second layer on the first layer, the first layer being formed of a microcrystalline layer. The second layer is formed of a crystalline layer whose c-axis is oriented perpendicular to the surface of the first layer. The semiconductor device is characterized by the above.

[0013] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of convenience and are not intended to limit the number.

[0014] the first oxide semiconductor layer has a crystal layer whose c-axis is oriented in a direction perpendicular to an insulating surface, The second oxide semiconductor layer has a c-axis oriented in a direction perpendicular to the upper surface of the first oxide semiconductor layer. It is preferable that the crystal layer has a crystal structure.

[0015] In addition, in a region where the stack and the third oxide semiconductor layer are in contact with each other, The surface preferably has a curved surface.

[0016] The first oxide semiconductor layer and the third oxide semiconductor layer are thicker than the second oxide semiconductor layer. The energy of the conduction band edge is close to the vacuum level in the range of 0.05 eV to 2 eV. preferable.

[0017] The first to third oxide semiconductor layers are In-M-Zn oxide layers (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the first oxide semiconductor The conductor layer and the third oxide semiconductor layer have an atomic ratio of M to In that is equal to that of the second oxide semiconductor Preferably it is larger than the layer. [Effects of the Invention]

[0018] By using one embodiment of the present invention, it is possible to suppress deterioration of electrical characteristics that becomes significant with miniaturization. It is possible to provide a semiconductor device having such a configuration. It is possible to provide a semiconductor device having a structure that can achieve high integration. Alternatively, a semiconductor device in which deterioration of on-state current is reduced can be provided. Alternatively, a semiconductor device with low power consumption can be provided. This makes it possible to provide a highly reliable semiconductor device. It is possible to provide a semiconductor device in which the data is held. It is possible.

[0019] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a transistor. [Figure 2] FIG. 1 is a cross-sectional view of a transistor. [Figure 3] 1A and 1B are diagrams illustrating band structures of oxide semiconductor layers. [Figure 4] 1A and 1B are diagrams illustrating a crystal structure of part of a stack of oxide semiconductor layers. [Figure 5] FIG. [Figure 6] FIG. 1 is a cross-sectional view of a transistor. [Figure 7] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 9] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 10] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 11] 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 13] 1A to 1C illustrate electronic devices to which a semiconductor device can be applied. [Figure 14] 10 is a cross-sectional view of a sample for observing a stacked state of oxide semiconductor layers. [Figure 15] Cross-sectional TEM image of an oxide semiconductor layer. DETAILED DESCRIPTION OF THE INVENTION

[0021] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The following explanations may be omitted.

[0022] In this specification, when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where X and Y are directly connected. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, and may be applied to any connection relationship shown in drawings or text. This also includes connections other than those shown in the text.

[0023] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. It has the function to switch between them.

[0024] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0025] When it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (i.e., there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected across the , when X and Y are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that the

[0026] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0027] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0028] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] In this specification and the like, it is possible to form a transistor using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor. Substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, metal substrate, stainless steel substrate, stainless steel foil Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lye. An example of a flexible substrate is polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), and polyethersulfone (PES). These include plastics that can be used for bonding, and flexible synthetic resins such as acrylic. Examples of films include polypropylene, polyester, polyvinyl fluoride, or polyethylene. Examples of base films include polyester, polyamide, polyvinyl chloride, etc. In particular, semiconductor substrates, single crystal substrates, Alternatively, by manufacturing transistors using SOI substrates, etc., the characteristics, size, We manufacture small-sized transistors with high current capacity and little variation in size or shape. When a circuit is configured using such transistors, the circuit consumes less power. This allows for increased power and higher circuit integration.

[0030] Alternatively, a flexible substrate may be used as the substrate, and a transistor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After completing a semiconductor device in part or in its entirety, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be an inorganic film of, for example, a tungsten film and a silicon oxide film. The laminated structure of the above or a structure in which an organic resin film such as polyimide is formed on a substrate may be used. This can be done.

[0031] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates to which the transistor is transferred. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, and the like. Fan substrate, aramid film substrate, polyimide film substrate, stone substrate, wood substrate, fabric substrate Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more durable device.

[0032] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0033] 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. FIG. 1(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. 1(A) is the cross section of FIG. FIG. 1(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. 1(A). In the top view of FIG. 1(A), some elements are omitted for clarity. The dashed line A1-A2 direction is the channel length direction, and the dashed line A3-A4 direction is the channel length direction. This is sometimes referred to as the width direction of the panel.

[0034] The transistor 100 shown in FIGS. 1A, 1B, 1C, and 2 is formed on a substrate 110. and a first oxide semiconductor layer 1 formed on the insulating base film 120. a stack of the oxide semiconductor layer 31 and the second oxide semiconductor layer 132 formed in this order, and a second oxide semiconductor layer 133 formed in contact with the stack The source electrode layer 140 and the drain electrode layer 150 formed as above, the base insulating film 120, The stacked layer includes a first electrode layer 140 and a second electrode layer 150, which are in contact with a part of each of the source electrode layer 140 and the drain electrode layer 150. a third oxide semiconductor layer 133 and a gate insulating film 1 formed on the third oxide semiconductor layer; 60, a gate electrode layer 170 formed on the gate insulating film, a source electrode layer 140, a drain electrode layer The semiconductor device has an insulating layer 180 formed on the drain electrode layer 150 and the gate electrode layer 170 .

[0035] Here, the first oxide semiconductor layer 131 has a c-axis oriented in a direction perpendicular to the surface of the base insulating film 120. The second oxide semiconductor layer 132 has an oriented crystal layer. It is preferable to have a crystal layer with the c-axis oriented perpendicular to the surface.

[0036] The third oxide semiconductor layer 133 is formed by a first layer in contact with the stack and a second layer on the first layer. The first layer is a microcrystalline layer and the second layer is a The first layer is formed of a crystalline layer whose c-axis is oriented perpendicular to the surface.

[0037] Moreover, an insulating layer 185 made of oxide may be formed on the insulating layer 180. The insulating layer 185 may be provided as needed, and another insulating layer may be formed on top of it. In addition, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor layers 133 are collectively referred to as oxide semiconductor layers 130.

[0038] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It shall be possible to use it.

[0039] In addition, in the transistor of one embodiment of the present invention, the oxide semiconductor layer (the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132) overlapping the source electrode layer 140 or the drain electrode layer In 150, the oxide semiconductor layer 150 is formed on the surface of the source electrode layer 150. 40 or the drain electrode layer 150 to one end (ΔW) is 50 nm or less, preferably By reducing ΔW, the amount of oxygen contained in the base insulating film 120 can be reduced. The amount of diffusion into the metal material that constitutes the source electrode layer 140 or the drain electrode layer 150 is suppressed. Therefore, oxygen contained in the base insulating film 120, especially excessive oxygen, Therefore, unnecessary release of oxygen can be suppressed, and the base insulating film 120 can be formed on the oxide semiconductor layer. This allows for efficient oxygen supply.

[0040] Next, components of the transistor 100 of one embodiment of the present invention will be described in detail.

[0041] The substrate 110 is not limited to being a simple support substrate, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 170 of the transistor 100, the source electrode At least one of the layer 140 and the drain electrode layer 150 is electrically connected to the other devices described above. The power supply may be electrically connected.

[0042] The base insulating film 120 has a role of preventing the diffusion of impurities from the substrate 110 and also prevents oxidation. Therefore, the base insulating film 1 20 is preferably an insulating film containing oxygen, and the insulating film contains more oxygen than the stoichiometric composition. As described above, the substrate 110 is preferably a thin film. In the case of a substrate having such a structure, the base insulating film 120 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a planarization process by a shing method or the like.

[0043] In addition, the oxide semiconductor layer 130 in the region where the channel of the transistor 100 is formed is , the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, the third oxide semiconductor layer 133, and the third oxide semiconductor layer 134 are stacked from the substrate 110 side. The oxide semiconductor layer 133 is stacked on the oxide semiconductor layer 132. As shown in the cross-sectional view in the direction perpendicular to the plane, the third oxide semiconductor layer 133 has a first oxide semiconductor layer in the channel formation region. The side and top surfaces of the stack of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 Therefore, in the channel forming region, The second oxide semiconductor layer 132 is a layer formed by combining the first oxide semiconductor layer 131 and the third oxide semiconductor layer. The structure is surrounded by a conductor layer 133 .

[0044] Here, for example, the second oxide semiconductor layer 132 is formed by adding the first oxide semiconductor layer 131 and has a higher electron affinity (energy density from the vacuum level to the bottom of the conduction band) than the third oxide semiconductor layer 133. The electron affinity is determined by the distance between the vacuum level and the top of the valence band. From the energy difference (ionization potential), the energy between the bottom of the conduction band and the top of the valence band The difference (energy gap) can be subtracted to obtain the value.

[0045] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are made of a material selected from the group consisting of a second oxide semiconductor The layer 132 contains one or more metal elements, and for example, the energy of the bottom of the conduction band is than the oxide semiconductor layer 132 by 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV. and in the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less. It is preferable that the insulating film be formed of an oxide semiconductor having a temperature close to a vacuum level.

[0046] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 0, the second oxide semiconductor layer 132 has the smallest energy at the bottom of the conduction band. That is, a second oxide semiconductor layer 132 is formed between the second oxide semiconductor layer 132 and the gate insulating film 160. The third oxide semiconductor layer 133 is formed, and thus the channel of the transistor is The structure is such that it does not come into contact with the insulating film.

[0047] The first oxide semiconductor layer 131 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the base insulating film 120 are in contact with each other, The interface between the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 is The interface states are unlikely to form at the interface. Therefore, the first oxide semiconductor By providing the layer 131, the variation in the electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0048] The third oxide semiconductor layer 133 contains the same metal element as that of the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the gate insulating film 160 are formed by containing one or more of the following, The interface between the second oxide semiconductor layer 132 and the third oxide semiconductor layer 13 Therefore, the scattering of carriers is less likely to occur at the interface with the third oxide semiconductor layer 3. By providing the layer 133, the field effect mobility of the transistor can be increased.

[0049] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 13 3 is at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn When the first oxide is an In-M-Zn oxide layer containing a metal such as La, Ce, or Hf, The In or Zn in the oxide semiconductor layer 131 and the third oxide semiconductor layer 133 The atomic ratio of M is preferably higher than that of the second oxide semiconductor layer 132. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since M bonds more strongly with oxygen than In or Zn, oxygen vacancies form in oxide semiconductors. That is, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 have a function of suppressing the generation of the oxide semiconductor layer. The third oxide semiconductor layer 133 is less likely to have oxygen vacancies than the second oxide semiconductor layer 132. It can be said that

[0050] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The layer 133 is made of at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr When the layer is an In-M-Zn oxide layer containing a metal such as Sn, La, Ce, or Hf, The first oxide semiconductor layer 131 is formed by In:M:Zn=x1:y1:z1 [atomic ratio], and the second oxide The oxide semiconductor layer 132 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor When the conductor layer 133 has an atomic ratio of In:M:Zn=x3:y3:z3, y1 / x1 and It is preferable that y1 / x1 and y3 / x3 are greater than y2 / x2. x3 is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than y2 / x2 In this case, in the second oxide semiconductor layer 132, when y2 is equal to or greater than x2, However, if y2 is more than three times x2, y2 should be less than three times x2 because this would reduce the field effect mobility of the transistor. It is preferable that:

[0051] In this specification, the atomic ratio used to describe the composition of an oxide semiconductor layer is determined based on the atomic ratio of the base material. The film is formed by sputtering using an oxide semiconductor material as a target. In this case, the film formation depends on the sputtering gas species and their ratio, the target density, and the film formation conditions. The composition of the oxide semiconductor layer may differ from that of the base material target. Therefore, in this specification, the atomic ratio used to describe the composition of an oxide semiconductor layer is the atomic ratio of the base material. For example, when the sputtering method is used for film formation, the atomic ratio is 1:1. :1 In-Ga-Zn oxide film is an In-Ga-Zn oxide with an atomic ratio of 1:1:1. This can be rephrased as an In-Ga-Zn oxide film formed using the material as a target. .

[0052] Zn and O in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 When In and M are excluded, the atomic ratio of In to M is preferably less than 50 atomic % and 50 atomic % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more % or more of the second oxide semiconductor layer 132 except for Zn and O. In this case, the atomic ratio of In to M is preferably 25 atomic % or more and 7 atomic % or less. 5 atomic %, more preferably In is 34 atomic % or more and M is 66 atomic % or more. Less than omic%.

[0053] The thickness of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is 1 nm or more. The thickness of the second oxide semiconductor layer is set to 00 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of 132 is 1 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and More preferably, it is 3 nm or more and 50 nm or less.

[0054] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor The layer 133 is made of, for example, an oxide semiconductor containing indium, zinc, and gallium. In particular, when the second oxide semiconductor layer 132 contains indium, the carrier This is preferable because it increases the mobility.

[0055] Therefore, the oxide semiconductor layer 130 is divided into the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. The stacked structure of the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 132, which allows the formation of a channel, and provides high field-effect mobility and stable electrical properties. A transistor having such a structure can be formed.

[0056] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 13 In the band structure of 3, the energy of the conduction band edge changes continuously. The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 This can also be understood from the fact that oxygen easily diffuses between the materials due to the similar compositions. , a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, a third oxide semiconductor layer 1 Although 33 is a laminate of layers with different compositions, it can also be said to be physically continuous. In the figure, the interfaces of the laminate are indicated by dotted lines.

[0057] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, specifically, a U-shaped junction in which the energy of the bottom of the conduction band changes continuously between layers) In other words, trap centers and recombination centers are formed at the interfaces of each layer. The layered structure is formed so that there are no impurities that would form a defect level such as a center. If impurities exist between the stacked oxide semiconductor layers, the energy band Continuity is lost, and carriers are trapped or recombined at the interface and disappear.

[0058] For example, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 may contain In:Ga :Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4 or 1:9: 6 (atomic ratio), and the second oxide semiconductor layer 132 contains In:Ga:Zn=1:1:1, 5: Use In-Ga-Zn oxide with an atomic ratio of 5:6 or 3:1:2. can be done.

[0059] The second oxide semiconductor layer 132 in the oxide semiconductor layer 130 becomes a well, and the oxide In the transistor using the oxide semiconductor layer 130, the channel is formed by the second oxide semiconductor layer 1 The oxide semiconductor layer 130 is formed in a region 32 where the energy of the bottom of the conduction band changes continuously. It can also be called a U Shape Well. A channel formed in this manner can also be called a buried channel.

[0060] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are formed of silicon oxide. Trap levels due to impurities and defects can be formed near the interface with insulating films, such as silicon dioxide. The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are provided. This can distance the second oxide semiconductor layer 132 from the trap states.

[0061] However, the conduction band minimums of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are When the difference between the energy of the first oxide semiconductor layer 131 and the energy of the bottom of the conduction band of the second oxide semiconductor layer 132 is small, In this case, electrons in the second oxide semiconductor layer 132 exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating film. This causes the threshold voltage of the transistor to shift in the positive direction.

[0062] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the first oxide semiconductor layer The energy of the conduction band minimum of the second oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is It is necessary to provide a certain difference between the energy of the bottom of the conduction band of the conductor layer 132 and the energy of the bottom of the conduction band of the conductor layer 132. The respective energy differences are preferably 0.1 eV or more, more preferably 0.15 eV or more. preferable.

[0063] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The conductor layer 133 preferably includes a crystal layer oriented along the c-axis. By using such a film, stable electrical characteristics can be imparted to the transistor.

[0064] When an In-Ga-Zn oxide is used for the oxide semiconductor layer 130, the gate insulating layer 130 is formed of In. To prevent diffusion into the insulating film, the third oxide semiconductor layer 133 is It is preferable that the composition contains less In than the above.

[0065] The transistor according to one embodiment of the present invention has the buried channel as described above, and also has the structure shown in FIG. As shown, the third oxide semiconductor layer 133 is a layer formed by interposing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. A microcrystalline layer 133a in contact with the stack of the conductor layer 132 and the base insulating film 120, and the microcrystalline layer The crystal layer 133b has a c-axis oriented perpendicular to the surface.

[0066] The band structure of the oxide semiconductor layer (corresponding to the B1-B2 direction in Figure 2) in this structure is shown in detail below. The figure shows the energy of the vacuum level, Evac, and EcI1 and EcI2. EcS1 is the energy of the bottom of the conduction band of the silicon film, and EcS2 is the energy of the bottom of the conduction band of the first oxide semiconductor layer 131. EcS2 is the energy of the bottom of the conduction band of the second oxide semiconductor layer 132, EcS3 is the energy of the bottom of the conduction band of the third oxide semiconductor layer 133.

[0067] The energy changes rapidly between EcS1 and EcS2, and between EcS3 and EcS2. Instead, the slope gradually changes at the beginning and end of the change.

[0068] This is because the interface between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 and the interface between the third oxide semiconductor layer 133 and the third oxide semiconductor layer 134 are At the interface between the first oxide semiconductor layer 133 and the second oxide semiconductor layer 132, the composition interdiffuses. the composition between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, or A region having a composition between the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132 is formed. This is to achieve this.

[0069] Therefore, as shown in FIG. 3, the channel formed in the second oxide semiconductor layer 132 is The thickness of the oxide semiconductor layer 133 is slightly increased from the interface between the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132 toward the center of the film. and a position farther from the interface between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. It is formed in the region 132b between the position slightly away from the center of the film. Even if defects or impurities exist at either interface, carrier trapping and recombination are suppressed. It can be done.

[0070] In addition, in the third oxide semiconductor layer 133, the first oxide semiconductor layer 131 and the second oxide semiconductor layer The region in contact with the stack of the compound semiconductor layer 132 is a microcrystalline layer 133a. The second oxide semiconductor layer has a lower density than the crystal layer 133b formed in the second oxide semiconductor layer. The composition of the third oxide semiconductor layer 132 is easily diffused toward the third oxide semiconductor layer 133. The region having the composition between the first oxide semiconductor layer 133 and the second oxide semiconductor layer 132 increases. Therefore, the channel formed in the second oxide semiconductor layer 132 is formed in the third oxide semiconductor layer 133. A position further away from the interface between the oxide semiconductor layer 133 and the second oxide semiconductor layer 132 toward the center of the film. This effectively prevents the above-mentioned problems that may occur when there are defects or impurities at the interface. can be done.

[0071] In addition, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are crystals oriented along the c-axis. When the layer is formed, the microcrystalline layer 133a has a lower density than the crystalline layer, so Therefore, the microcrystalline layer 133a serves as a path for the diffusion of oxygen from the insulating substrate. To efficiently supply oxygen from the film 120 to the second oxide semiconductor layer 132 that serves as a channel. This allows oxygen to be added to compensate for the oxygen deficiency.

[0072] The crystalline layer 133b of the third oxide semiconductor layer 133 is formed on the surface of the microcrystalline layer 133a. Therefore, the surface of the second oxide semiconductor layer 132 is curved. By forming the second oxide semiconductor layer 132 so as to have a c-axis oriented crystal, It can densely cover the area.

[0073] FIG. 4A shows a first example of a transistor having a curved surface in the channel width direction. a second oxide semiconductor layer 132; a microcrystalline layer 133a covering the second oxide semiconductor layer; 1 is a cross-sectional view showing a schematic crystalline structure of a part of a stack of crystal layers 133b formed on the crystal layer; Here, the second oxide semiconductor layer 132 is a first oxide semiconductor layer 131 (not shown). ) is a crystalline layer oriented with its c-axis perpendicular to the surface.

[0074] As shown in the figure, the surface of the second oxide semiconductor layer 132 is formed to have a curved surface. , a dense crystal layer with c-axis orientation in the direction perpendicular to the curved surface via a microcrystalline layer 133a. The third oxide semiconductor layer 133 having the oxide semiconductor layer 133b can be formed. The third oxide semiconductor layer 133 has an effect of suppressing oxygen desorption from the second oxide semiconductor layer 132. As a result, the effect of trapping oxygen released from the base insulating film 120 can be enhanced. Oxygen vacancies in the second oxide semiconductor layer 132 can be efficiently filled with oxygen.

[0075] Note that when the second oxide semiconductor layer 132 is not formed to have a curved surface, the same process as in FIG. As shown in (B), in the third oxide semiconductor layer 133, the second oxide semiconductor layer 132 In the region where the crystal layer 133b formed on the top and the crystal layer 133b formed on the side of The sparsely crystalline region 233 is formed. Therefore, the oxide of the second oxide semiconductor layer 132 is The oxygen supplied from the base insulating film 120 to the second oxide semiconductor layer 132 is Therefore, oxygen vacancies in the second oxide semiconductor layer 132 are easily released through the oxide semiconductor layer 33. Therefore, oxygen cannot be efficiently replenished.

[0076] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0077] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The impurity concentration in the oxide semiconductor layer 133 and at the interface between the oxide semiconductor layer 133 and the oxide semiconductor layer 133 can be reduced. preferable.

[0078] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. In the analysis of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 It has a part that is less than In addition, the hydrogen concentration is preferably adjusted at a certain depth in the oxide semiconductor layer or at a certain depth in the oxide semiconductor layer. In a certain region of the nitride semiconductor layer, 20 atoms / cm3 Below, preferably 5 x10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Lower, more preferably 5 × 10 18 atoms / cm 3 It has the following parts: The nitrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor layer or In a region of the oxide semiconductor layer, 5×10 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 It has the following parts: It is preferable that:

[0079] In addition, when the oxide semiconductor layer contains crystals, if silicon or carbon is contained at a high concentration, the oxide The crystallinity of the oxide semiconductor layer may be reduced. For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, or , in a region of the oxide semiconductor layer, the carbon concentration is 1×10 19atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It is sufficient that the part is less than the above.

[0080] In addition, a transistor using the above-described highly purified oxide semiconductor layer for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or about 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0081] Note that, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not come into contact with the gate insulating film, such as a gate electrode, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field-effect mobility of the transistor. Therefore, it is preferable that the region of the oxide semiconductor layer that becomes the channel is separated from the gate insulating film. .

[0082] The source electrode layer 140 and the drain electrode layer 150 are made of a conductive material that easily bonds with oxygen. For example, it is preferable to use Al, Cr, Cu, Ta, Ti, Mo, W, etc. Among the above materials, Ti, which is particularly prone to bonding with oxygen, and It is more preferable to use W, which has a high melting point, because it can effectively increase the melting point. Conductive materials that are easily bonded also include materials through which oxygen easily diffuses.

[0083] When a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, the oxygen in the oxide semiconductor layer However, the phenomenon occurs in which the oxygen diffuses into the conductive material, which is more likely to bond with oxygen. The above phenomenon occurs remarkably because the manufacturing process of a transistor includes a heating step. The oxide semiconductor layer has an oxygen vacancy in a region near the contact with the source electrode layer or the drain electrode layer. The oxygen vacancies are combined with the hydrogen contained in the film to form the n Therefore, the region that has been made n-type acts as the source or drain of the transistor. It can be made to act by this.

[0084] The n-type region is shown in the enlarged cross section of the transistor in Figure 5 (part of the cross section in the channel length direction). , near the source electrode layer 140). The boundary 135 shown by the dotted line in the nitride semiconductor layer 132 is the boundary between the intrinsic semiconductor region and the n-type semiconductor region. In the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, The region in contact with the source electrode layer 140 is an n-type region. The boundary in Fig. 5 is shown as a schematic diagram and may not be clear in reality. 135 is located so as to extend laterally in the second oxide semiconductor layer 132. However, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are shown in a state in which they are separated. The entire region sandwiched between the base electrode layer 140 and the insulating film undercoat 120 may be converted to n-type in the thickness direction. do.

[0085] When forming a transistor with an extremely short channel length, the occurrence of the oxygen vacancies causes the n The shaped region may extend in the channel length direction of the transistor. The electrical characteristics of a transistor include the shift of the threshold voltage and the ability to control on / off by the gate voltage. Therefore, a transistor with an extremely short channel length is formed. In this case, a conductive material that easily bonds to oxygen is used for the source electrode layer and the drain electrode layer. However, this is not necessarily desirable.

[0086] In such a case, the source electrode layer 140 and the drain electrode layer 150 are made of the above-mentioned materials. It is also possible to use a conductive material that is less likely to bond with oxygen than the conductive material. For example, tantalum nitride, titanium nitride, gold, platinum, palladium, or ruthenium-containing materials. When the conductive material is in contact with the second oxide semiconductor layer 132, In this case, the source electrode layer 140 and the drain electrode layer 150 are formed of the conductive material and the oxygen Alternatively, a conductive material that easily bonds to the conductive layer may be laminated.

[0087] The gate insulating film 160 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or oxynitride. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more kinds of tantalum oxide can be used. It may also be a laminate of the above materials.

[0088] The gate electrode layer 170 may include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, and Ru. A conductive film of Ag, Ta, W, or the like can be used. The gate electrode layer may be a laminate of the above materials. It's fine.

[0089] An insulating layer 180 is formed on the gate insulating film 160 and the gate electrode layer 170. It is preferable that the insulating layer is made of aluminum oxide. The aluminum film is a barrier that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the film. Therefore, the aluminum oxide film is used during the manufacturing process of the transistor and after the manufacturing process. Later, the oxides of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the semiconductor layer 130, and preventing oxygen, which is the main component material constituting the oxide semiconductor layer 130 Preventing release of oxygen from the oxide semiconductor layer and preventing unnecessary release of oxygen from the underlying insulating film 120 In addition, the acid contained in the aluminum oxide film is suitable for use as a protective film having the above structure. The element can also be diffused into the oxide semiconductor layer.

[0090] In addition, it is preferable that an insulating layer 185 is formed on the insulating layer 180. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0091] Here, the insulating layer 185 preferably contains excess oxygen. The insulating layer containing excess oxygen is This refers to an insulating layer that can release oxygen by heat treatment, etc. For example, when the surface temperature is 1 The temperature is increased by heating at a temperature of 00°C to 700°C, preferably 100°C to 500°C. Thermal desorption spectroscopy analysis showed that the amount of released oxygen, converted to oxygen atoms, was 1.0 x 10 19 at oms / cm 3 The oxygen released from the insulating layer is transferred to the gate insulating film 16 0 and can be diffused into the channel formation region of the oxide semiconductor layer 130. Therefore, even if oxygen vacancies are formed in the channel formation region, oxygen can be compensated for. Therefore, stable electrical characteristics of the transistor can be obtained.

[0092] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate with the miniaturization of the channel width. The reduction in on-current, which is a direct result of the reduction in size, is significant.

[0093] However, in the transistor according to one embodiment of the present invention, as described above, A third oxide semiconductor layer 133 is formed so as to cover a region of the oxide layer 132 where a channel is to be formed. The channel formation layer and the gate insulating film are not in contact with each other. This can suppress the scattering of carriers that occurs at the interface between the channel forming layer and the gate insulating film, The field effect mobility of the transistor can be increased.

[0094] Furthermore, a transistor of one embodiment of the present invention has a structure as shown in the cross-sectional view in the channel width direction in FIG. The length of the upper surface of the second oxide semiconductor layer 132 in the channel width direction (W T ) is the oxide In a structure where the thickness of the semiconductor layer is reduced to the same level, it is particularly important to improve the electrical characteristics. This can be done.

[0095] For example, in the transistor shown in Figure 2, T If is small as above, the game The electric field applied from the electrode layer 170 to the side surface of the second oxide semiconductor layer 132 Since the second oxide semiconductor layer 132 is entirely covered with the second oxide semiconductor layer 132, the second oxide semiconductor layer 132 is also formed on its side surface and top surface. A channel equivalent to the channel to be formed is formed.

[0096] W T For transistors with small channel widths, W T and the second oxide in the channel width direction The side length (W S1 , W S2 ) sum (W T +W S1 +W S2 ) and The on-state current flows through the transistor in accordance with the channel width. Ta, W T When the potential difference is extremely small, a current flows through the entire second oxide semiconductor layer 132. do.

[0097] That is, W using one embodiment of the present invention T In a transistor with a small capacitance, carrier scattering is suppressed. This has the effect of increasing the capacitance and widening the channel width, making it more opto- The on-current can be increased.

[0098] In addition, W S1 =W S2 =W S When this is done, the on-current of the transistor is efficiently improved. 0.3W S ≦W T ≦3W S (W T is 0.3W S More than 3W S (See below). Or W T / W S = 0.5 or more and 1.5 or less, and more preferably W T / W S =0.7 or more 1.3 or less. W T / W S If it is greater than 3, the S value and off-state current may increase.

[0099] Therefore, the transistor of one embodiment of the present invention can be miniaturized. Even if the gate voltage is 0.01 V, a sufficiently high on-state current can be obtained.

[0100] In the transistor of one embodiment of the present invention, the second oxide semiconductor layer 132 is formed by By forming it on the conductor layer 131, it is possible to make it difficult for an interface state to be formed. By making the body layer 132 the middle layer of the three-layer structure, the influence of impurities from above and below can be eliminated. Therefore, the second oxide semiconductor layer 132 has the same effect as the first oxide semiconductor layer. The second oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are surrounded by the second oxide semiconductor layer 131 and the third oxide semiconductor layer 133. In addition to improving the on-state current, it is possible to stabilize the threshold voltage and reduce the S value. Therefore, Icut (current when gate voltage VG is 0V) can be reduced, and This reduces the power consumption of the device. In addition, the threshold voltage of the transistor is stabilized. As a result, the long-term reliability of the semiconductor device can be improved.

[0101] In addition, the transistor of one embodiment of the present invention includes an oxide semiconductor layer 130 and a substrate as shown in FIG. A conductive film 172 may be provided between the gate electrode 110 and the gate electrode 110. The conductive film is used as a second gate electrode. By using this, it is possible to further increase the on-current and control the threshold voltage. To increase the gate current, for example, the gate electrode layer 170 and the conductive film 172 are set to the same potential, and It is sufficient to drive it as a dual gate transistor. In this case, a constant potential different from that of the gate electrode layer 170 may be supplied to the conductive film 172 .

[0102] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0103] (Embodiment 2) In this embodiment, the method for manufacturing the transistor 100 illustrated in FIGS. 1A and 1B described in Embodiment 1 will be described. This will be explained with reference to FIGS. 7 and 8.

[0104] The substrate 110 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, it is possible to use a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On In) It is also possible to use a silicon insulator substrate, and semiconductor elements are mounted on these substrates. The one provided may be used.

[0105] The base insulating film 120 is formed by depositing aluminum oxide or Magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide insulating films such as tantalum oxide, silicon nitride, silicon nitride oxide, and aluminum nitride. The insulating film is made of nitride such as aluminum or aluminum nitride oxide, or a film made of a mixture of the above materials. It may also be a laminate of the above materials, and may be formed by at least an oxide semiconductor. The upper layer in contact with the oxide semiconductor layer 130 contains excess oxygen that can be a source of oxygen to the oxide semiconductor layer 130. It is preferable to form the insulating film from a material containing the compound.

[0106] In addition, the base insulating film 120 is subjected to ion implantation, ion doping, plasma immersion, and the like. Oxygen may be added by using an on-implantation method or the like. This makes it easier to supply oxygen from the base insulating film 120 to the oxide semiconductor layer 130. It is possible.

[0107] Note that the surface of the substrate 110 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no influence of diffusion, the base insulating film 120 may not be provided.

[0108] Next, a first oxide semiconductor film 3 which will become a first oxide semiconductor layer 131 is formed on the base insulating film 120. 31 and a second oxide semiconductor film 332 which will become the second oxide semiconductor layer 132 are formed by sputtering. The film is formed by the etching method, CVD method, MBE method, ALD method or PLD method (see Figure 7(A)). (see).

[0109] Next, the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched. By this, a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 are formed. (See FIG. 7(B)). At this time, the base insulating film 120 is slightly over-etched as shown in the figure. By excessively etching the base insulating film 120, the gate to be formed later may be This makes it easier to cover the second oxide semiconductor layer 132 with the electrode. In the cross section in the channel width direction, The shape has a curvature towards the center.

[0110] Note that the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched. When performing the etching, a hard mask such as a metal film may be used in addition to a photoresist. Alternatively, an organic resin may be formed on the metal film. For example, the metal film may be formed to a thickness of about 5 nm. A tungsten film or the like can be used.

[0111] The etching method may be a method for etching the first oxide semiconductor film 331 and the second oxide semiconductor film 332. It is preferable to use a dry etching method in which the difference in etching rate of the semiconductor film 332 is small. It's nice.

[0112] A continuous junction is formed in the stack of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. In order to form the film, a multi-chamber film formation apparatus (e.g., It is preferable to use a sputtering device to successively laminate each layer without exposing it to the atmosphere. Each chamber in the sputtering equipment is designed to remove water and other impurities that can be present in oxide semiconductors. To remove as much as possible, high vacuum evacuation is performed using an adsorption type vacuum evacuation pump such as a cryopump. Ki (5 x 10 -7 Pa or more 1×10 -4 Pa or less), and the film It is preferable that the substrate can be heated to 100°C or higher, preferably 500°C or higher. A turbomolecular pump and a cold trap are combined to remove carbon components from the exhaust system into the chamber. It is preferable to prevent gas containing water and moisture from flowing back.

[0113] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of sputtering gases. Oxygen gas and argon gas used as sputtering gases are , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor layer as much as possible. This can be prevented.

[0114] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and a layer formed in a later step The third oxide semiconductor layer 133 can be formed using the material described in Embodiment 1. For example, the first oxide semiconductor layer 131 may contain In:Ga:Zn=1:3:6, 1:3:4, In-Ga-Zn oxide with an atomic ratio of 1:3:3 or 1:3:2, the second oxide semiconductor The layer 132 is made of In-Ga with an atomic ratio of In:Ga:Zn=1:1:1 or 5:5:6. a-Zn oxide, and the third oxide semiconductor layer 133 is In:Ga:Zn=1:3:6, 1:3 Use In-Ga-Zn oxide with an atomic ratio of 1:4, 1:3:3, or 1:3:2. can be done.

[0115] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor that can be used as the semiconductor layer 133 contains at least indium (In It is preferable that the alloy contains In or zinc (Zn). Alternatively, it may contain both In and Zn. In addition, in order to reduce variations in electrical characteristics of transistors using the oxide semiconductor, Therefore, it is preferable to include a stabilizer together with them.

[0116] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0117] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0118] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0119] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and A material expressed by the formula (n is an integer) may be used.

[0120] However, as described in detail in the first embodiment, the first oxide semiconductor layer 131 and the third oxide semiconductor layer The oxide semiconductor layer 133 is formed so as to have a smaller electron affinity than the second oxide semiconductor layer 132. Select the material accordingly.

[0121] Note that the oxide semiconductor layer is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0122] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 13 When In-Ga-Zn oxide is used as 3, the atomic ratio of In, Ga, and Zn is as follows: For example, In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, In:Ga: Zn=3:1:2, In:Ga:Zn=5:5:6, In:Ga:Zn=1:3:2, I n:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, In:Ga:Zn=1: 3:6, In:Ga:Zn=1:4:3, In:Ga:Zn=1:5:4, In:Ga: Zn=1:6:6, In:Ga:Zn=2:1:3, In:Ga:Zn=1:6:4, I n:Ga:Zn=1:9:6, In:Ga:Zn=1:1:4, In:Ga:Zn=1: 1:2, and the first oxide semiconductor layer 131 and the third oxide semiconductor layer The electron affinity of the layer 133 may be set to be smaller than that of the second oxide semiconductor layer 132. .

[0123] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides.

[0124] The second oxide semiconductor layer 132 is a layer formed by combining the first oxide semiconductor layer 131 and the third oxide semiconductor layer 132. The indium content is preferably higher than that of the semiconductor layer 133. The s orbital of heavy metals contributes to carrier conduction, and by increasing the In content, Since more s orbitals overlap, oxides with a composition where In is more abundant than Ga have the same In content as Ga. The mobility is higher compared to oxides with equal or lesser composition. By using an oxide with a high indium content for the semiconductor layer 132, a transistor with high mobility can be obtained. It is possible to realize a register.

[0125] The structure of the oxide semiconductor film will be described below.

[0126] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0127] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0128] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0129] First, the CAAC-OS film will be described.

[0130] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is small enough to fit inside a cube with a side length of less than 100 nm. The crystal part contained in the -OS film is a cubic crystal with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. This includes cases where the size is small enough to fit inside the body.

[0131] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0132] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0133] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0134] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0135] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0136] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0137] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of metal atoms arranged in a plane parallel to the ab plane of the crystal.

[0138] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. is oriented in a direction parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the shape of the CAAC-OS film. It may not be parallel to the normal vector of the top or bottom surface.

[0139] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0140] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0141] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that constitute the oxide semiconductor film, such as fluorine, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius) is large, and when it is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier sources.

[0142] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a source of carrier generation.

[0143] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics ( It is also called normally-on.) It is rare for it to become a high-purity intrinsic or substantially high-purity The intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The impurity concentration is high and the charge is stable for a long time, so the charge may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may occur.

[0144] In addition, transistors using CAAC-OS films show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0145] Next, a microcrystalline oxide semiconductor film will be described.

[0146] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal part contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or less. , or 1 nm to 10 nm in size. Nanocrystals (nc) are microcrystals of 1 nm or less and 3 nm or less. The oxide semiconductor film having nc-OS (nanocrystalline Oxide Semiconductor Film) The nc-OS film is called a TE film. In the M observation image, the grain boundaries may not be clearly visible.

[0147] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis is performed using the D device, the crystal plane is In addition, the peaks indicating the probes larger than the crystalline part were not detected in the nc-OS film. Electron beam diffraction (also called selected area electron beam diffraction) uses an electron beam with a diameter (for example, 50 nm or more). ) a halo-like diffraction pattern is observed. On the other hand, the probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using an electron beam of Furthermore, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed for the nc-OS film. However, when nanobeam electron diffraction is performed, multiple spots are observed within the ring-shaped region. There is.

[0148] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0149] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminated film having two or more kinds of films.

[0150] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The film can be formed by sputtering. Ions collide with the sputtering target. When the sputtering target is cleaved, the crystalline region contained in the sputtering target cleaves from the ab plane and forms a crystal parallel to the ab plane. The particles may peel off as flat or pellet-shaped sputter particles with a smooth surface. In this case, the plate-shaped or pellet-shaped sputtered particles are charged and do not agglomerate in the plasma. The crystals reach the substrate while maintaining their crystalline state, thereby forming a CAAC-OS film.

[0151] The second oxide semiconductor layer 132 is an In-M-Zn oxide layer (M is Ga, Y, Zr, La, In the case of Ce or Nd), the sputtering agent used to form the second oxide semiconductor layer 132 In the target for the quartz crystal, the atomic ratio of the metal elements is In:M:Zn=a1:b1:c1. And 、 a1 / b1 is between 1 / 3 and 6, or between 1 and 6, and c1 / b1 is , preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When the ratio is 1 to 6, a CAAC-OS film is formed as the second oxide semiconductor layer 132. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn= Examples include 1:1:1, In:M:Zn=3:1:2, and In:M:Zn=5:5:6.

[0152] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are In-M-Zn oxide layers (where M is Ga, Y, Zr, La, Ce, or Nd), for the sputtering target used to form the first oxide semiconductor layer 1 31 and the third oxide semiconductor layer 133, when the atomic ratio of metal elements is In:M:Zn = a2:b2:c2, then a2 / b2 、 is < a1 / b1, and c2 / b2 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. By setting c2 / b2 to 1 or more and 6 or less, it becomes easier to form a CAAC-OS film as the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. Representative examples of the atomic ratio of metal elements in the target include In:M:Zn = 1:3:2, I n:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6 etc. After forming the second oxide semiconductor layer 132, a first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Also, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the second oxide semiconductor layer 132 can be enhanced, and impurities such as hydrogen and water can be removed from the underlying insulating film 120 and the first oxide semiconductor layer 131. Note that a first heating step may be performed before etching to form the second oxide semiconductor layer 132.

[0153]

[0154] oxide semiconductor layer 131.

[0154] ​​Next, a source electrode layer is formed on the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. A first conductive film is formed to become the drain electrode layer 140 and the drain electrode layer 150. is made of Al, Cr, Cu, Ta, Ti, Mo, W, or alloy materials whose main components are these. For example, a titanium film of 100 nm is formed by sputtering or the like. Alternatively, the tungsten film may be formed by the CVD method.

[0155] Next, the first conductive film is etched to be divided on the second oxide semiconductor layer 132. A source electrode layer 140 and a drain electrode layer 150 are formed (see FIG. 7(C)). However, excessive etching of the first conductive film may result in a part of the second oxide semiconductor layer 132 being etched. It may also be in a chipped shape.

[0156] Next, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the source electrode layer 140 and a third oxide semiconductor layer 133 is formed on the drain electrode layer 150. At this time, the second oxide semiconductor layer of the third oxide semiconductor film 333 is formed. The vicinity of the interface with 132 is a microcrystalline layer, and the c-axis oriented crystal layer is formed on the microcrystalline layer.

[0157] Note that second heat treatment may be performed after the third oxide semiconductor film 333 is formed. The heat treatment can be carried out under the same conditions as the first heat treatment. Impurities such as hydrogen and water can be removed from the third oxide semiconductor film 333. Further, hydrogen, water, etc. are released from the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Impurities can be removed.

[0158] Next, an insulating film 360 that will become the gate insulating film 160 is formed on the third oxide semiconductor film 333. The insulating film 360 may be made of aluminum oxide, magnesium oxide, silicon oxide, or oxynitride. Silicon, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, and gallium oxide tritium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and The insulating film 360 may be a laminate of the above materials. The insulating film 360 may be formed by a method such as sputtering, CVD, MBE, ALD, or PLD. It can be formed using, for example.

[0159] Next, a second conductive film 370 that will become the gate electrode layer 170 is formed on the insulating film 360 (FIG. 8). The second conductive film 370 may be made of Al, Ti, Cr, Co, Ni, Cu, Y, or the like. , Zr, Mo, Ru, Ag, Ta, W, or alloy materials containing these as the main components. The second conductive film 370 can be formed by a sputtering method, a CVD method, or the like. Furthermore, a conductive film containing nitrogen may be used as the second conductive film 370. A laminate of a conductive film containing a material and a conductive film containing nitrogen may be used.

[0160] Next, using a resist mask for forming the gate electrode layer 170, the second conductive film 37 0 is selectively etched to form the gate electrode layer 170.

[0161] Next, the insulating film 360 is selected using the resist mask or the gate electrode layer 170 as a mask. Selective etching is performed to form the gate insulating film 160.

[0162] Next, the third oxide semiconductor is formed using the resist mask or the gate electrode layer 170 as a mask. The oxide semiconductor film 333 is etched to form the third oxide semiconductor layer 133 (see FIG. 8B). .

[0163] The second conductive film 370, the insulating film 360, and the third oxide semiconductor film 333 are etched. The etching may be performed for each layer or continuously. Either dry etching or wet etching may be used, and an appropriate etching method is selected for each layer. may be selected.

[0164] Next, insulating layers are formed on the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170. The insulating layer 180 and the insulating layer 185 are formed (see FIG. 8(C)). The insulating film 185 can be formed using the same material and method as the base insulating film 120. It is particularly preferable to use aluminum oxide for the insulating layer 180.

[0165] In addition, the insulating layer 180 may be formed by ion implantation, ion doping, plasma immersion ion implantation, or the like. Oxygen may be added by implantation or the like. This makes it easier to supply oxygen from the insulating layer 180 to the oxide semiconductor layer 130. Cut.

[0166] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed by the base insulating film 120, the gate insulating film 160, Excess oxygen is easily released from the insulating layer 180, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. It can be reduced.

[0167] Through the above steps, the transistor 100 shown in FIG. 1 can be manufactured.

[0168] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0169] (Embodiment 3) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is used in a state where power is not supplied. A semiconductor device (memory device) that can retain its memory contents even under certain conditions and has no limit on the number of times it can be written. An example of the device will be described with reference to the drawings.

[0170] FIG. 9A shows a cross-sectional view of the semiconductor device, and FIG. 9B shows a circuit diagram of the semiconductor device.

[0171] The semiconductor device shown in FIG. 9(A) and FIG. 9(B) has a transistor using a first semiconductor material in the lower part. a transistor 3300 using a second semiconductor material on top; The transistor 3300 includes a capacitor element 3400. The transistor 100 described above can be used.

[0172] The capacitor 3400 has one electrode connected to the source electrode layer or the drain electrode layer of the transistor 3300. The other electrode is the gate electrode layer of the transistor 3300, and the dielectric is the transistor The same material as the gate insulating film 160 and the third oxide semiconductor layer 133 of the capacitor 3300 is used. By adopting this structure, the transistor 3300 can be formed at the same time.

[0173] Here, the first semiconductor material and the second semiconductor material have different energy gaps. For example, it is desirable to use a semiconductor material other than an oxide semiconductor (such as silicon) as the first semiconductor material. and the second semiconductor material may be the oxide semiconductor described in Embodiment 1. Transistors using materials other than oxide semiconductors can easily operate at high speed. In addition, transistors using oxide semiconductors have electrical characteristics of low off-state current, which allows them to be charged for a long time. Allows retention.

[0174] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. In order to hold the above-mentioned temperature, a transistor including an oxide semiconductor as described in Embodiment 1 is used. Others include specific configurations of semiconductor devices, such as materials used in semiconductor devices and their structures. need not be limited to those shown here.

[0175] The transistor 3200 in FIG. 9A is made of a semiconductor material (e.g., crystalline silicon). ) and a channel forming region provided on a substrate 3000 including the an impurity region, an intermetallic compound region in contact with the impurity region, and a channel forming region; and a gate electrode layer provided on the gate insulating film. In the drawings, the source electrode layer and the drain electrode layer may not be explicitly shown. For convenience, this state may also be called a transistor. In order to explain the connection relationship of the transistor, the source electrode layer including the source region and drain region is In other words, in this specification, the source electrode layer and the drain electrode layer are sometimes referred to as a The description may include a source region.

[0176] An element isolation insulating layer 3100 is provided on a substrate 3000 so as to surround a transistor 3200. An insulating layer 3150 is provided to cover the transistor 3200. The element isolation insulating layer 3100 is formed by LOCOS (Local Oxidation of Silicon) licon) and STI (Shallow Trench Isolation) It can be formed using element isolation technology.

[0177] For example, when a crystalline silicon substrate is used, the transistor 3200 can operate at high speed. Therefore, by using the transistor as a readout transistor, The readout can be performed at high speed.

[0178] A transistor 3300 is provided on the insulating layer 3150, and its source electrode layer or drain The wiring electrically connected to the gate electrode layer serves as one electrode of the capacitor 3400. In addition, the wiring is electrically connected to the gate electrode layer of the transistor 3200.

[0179] The transistor 3300 illustrated in FIG. 9A has a top surface where a channel is formed in an oxide semiconductor layer. The transistor 3300 has a small off-state current. By using this, it is possible to retain memory contents for a long period of time. Semiconductor memory that does not require a refresh operation or that requires a refresh operation very infrequently Since it is possible to form a device, power consumption can be reduced sufficiently.

[0180] In addition, an electrode 3250 is provided so as to overlap with the transistor 3300 with an insulating layer 3150 interposed therebetween. By applying an appropriate potential to this electrode as a second gate electrode, The threshold voltage of the transistor 3300 can be controlled. The long-term reliability can be improved. By operating the electrode 325 at the same potential as the electrode 325, the on-current can be increased. It is also possible to configure the system so that no 0 is set.

[0181] As shown in FIG. 9A, a transistor 330 is formed on a substrate on which a transistor 3200 is formed. 0 and the capacitor element 3400 can be formed, thereby increasing the degree of integration of the semiconductor device. This can be done.

[0182] An example of a circuit configuration corresponding to FIG. 9(A) is shown in FIG. 9(B).

[0183] In FIG. 9B, the first wiring 3001 is electrically connected to the source electrode layer of the transistor 3200. The second wiring 3002 is electrically connected to the drain electrode layer of the transistor 3200. The third wiring 3003 is connected to the source electrode layer of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrode layers of the transistor 330. 0. The gate electrode layer of the transistor 3200 is electrically connected to the The other of the source electrode layer and the drain electrode layer of the transistor 3300 is a capacitor. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. The element corresponding to the electrode 3250 is not shown in the figure. not present.

[0184] In the semiconductor device shown in FIG. 9B, the potential of the gate electrode layer of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0185] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode layer of the transistor 3200 and and the capacitor 3400. That is, the gate electrode layer of the transistor 3200 A predetermined charge is applied (write). Here, two different potential levels are applied. A charge (hereinafter referred to as a low-level charge or a high-level charge) is given to a After that, the potential of the fourth wiring 3004 is set to a value that turns off the transistor 3300. By applying a voltage to the transistor 3300 to turn it off, the transistor 3200 The charge given to the gate electrode layer is retained (retention).

[0186] Since the off-state current of the transistor 3300 is extremely small, the gate voltage of the transistor 3200 The charge in the polar layer is maintained for a long period of time.

[0187] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor The second wiring 3002 has different potentials depending on the amount of charge held in the gate electrode layer of the capacitor 3200. Generally, if the transistor 3200 is an n-channel type, the transistor 320 The apparent threshold voltage V when a high level charge is applied to the gate electrode layer of th_H indicates that a low-level charge is applied to the gate electrode layer of the transistor 3200. The apparent threshold voltage V th_L This is because the apparent The low voltage is the voltage across the fifth wiring 300 required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in writing, a high level charge is given. In this case, the potential of the fifth wiring 3005 is V0 (>V th_H ) then, Trans If a low level charge is applied, the fifth The potential of the wiring 3005 is V0( <V th_L ), transistor 3200 remains "off" Therefore, by determining the potential of the second wiring 3002, The information stored in the memory can be read.

[0188] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. Alternatively, Regardless of the potential, transistor 3200 is in the "on" state, i.e., V th_L A larger potential may be applied to the fifth wiring 3005 .

[0189] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0190] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film is unlikely to occur. In this device, there is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and it is reliable. Furthermore, the on / off state of the transistor determines the writing and reading of information. Since the data is written into the memory, high speed operation can be easily achieved.

[0191] As described above, semiconductors that have achieved miniaturization and high integration and have been endowed with high electrical properties are An apparatus can be provided.

[0192] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0193] (Fourth embodiment) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is used in a state where power is not supplied. Regarding semiconductor devices that can retain memory contents even under certain circumstances and have no limit on the number of times they can be written, A semiconductor device having a different structure from that shown in Embodiment Mode 3 will be described.

[0194] 10 is an example of a circuit configuration of a semiconductor device. In the semiconductor device, the first wiring 4 The source electrode layer of the transistor 4300 is electrically connected to the second wiring 460. 0 and the gate electrode layer of the transistor 4300 are electrically connected, and the transistor 4300 The drain electrode layer of the capacitor 4400 is electrically connected to the first terminal of the capacitor 4400. The transistor 4300 included in the semiconductor device may be the transistor described in Embodiment 1. The first wiring 4500 is a bit line, and the second wiring Line 4600 can function as a word line.

[0195] The semiconductor device (memory cell 4250) includes a transistor 3300 and a capacitor shown in FIG. The connection configuration can be the same as that of the element 3400. Therefore, the capacitor 4400 has the following configuration: In the manufacturing process of the transistor 4300, similar to the capacitor 3400 described in Embodiment 3, can be simultaneously produced.

[0196] Next, data is written and held in the semiconductor device (memory cell 4250) shown in FIG. The following explains how to do this.

[0197] First, a potential that turns on the transistor 4300 is supplied to the second wiring 4600. The transistor 4300 is turned on. As a result, the potential of the first wiring 4500 is The potential of the second wiring 4600 is then applied to the first terminal of the second wiring 4400 (write). is set as a potential at which the transistor 4300 is turned off, By setting the potential of the first terminal of the capacitor 4400 to the low potential state, the potential of the first terminal of the capacitor 4400 is held (retained).

[0198] The transistor 4300 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 4300 is turned off, the capacitor 4400 The potential of the first terminal (or the charge stored in the capacitor element 4400) is kept at 100 V for an extremely long time. It is possible to maintain the

[0199] Next, reading of information will be described. When the transistor 4300 is turned on, a floating The first wiring 4500 in the free state and the capacitor element 4400 are electrically connected to each other. Charge is redistributed between the capacitors 4400. As a result, the potential of the first wiring 4500 changes. The amount of change in the potential of the first wiring 4500 is determined by the potential of the first terminal of the capacitor 4400 ( Alternatively, it takes on different values depending on the charge stored in the capacitor element 4400.

[0200] For example, the potential of the first terminal of the capacitor 4400 is V, the capacitance of the capacitor 4400 is C, and the first The capacitance component of the first wiring 4500 is CB, and the capacitance of the first wiring 4500 before the charge is redistributed is If the potential is VB0, the potential of the first wiring 4500 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of memory cell 4250 is If the potential of the first terminal of the capacitor 4400 is in two states, V1 and V0 (V1>V0), Then, the potential of the first wiring 4500 when the potential V1 is maintained is (=(CB×VB0+C ×V1) / (CB+C)) is the potential of the first wiring 4500 when the potential V0 is maintained. It can be seen that it is higher than (=(CB×VB0+C×V0) / (CB+C)).

[0201] Then, the potential of the first wiring 4500 is compared with a predetermined potential, thereby reading out information. can be done.

[0202] In this way, the semiconductor device (memory cell 4250) shown in FIG. 10 includes the transistor 4300 Since the off-state current of the capacitor 4400 is extremely small, the charge stored in the capacitor 4400 is retained for a long time. This means that no refresh operation is required, or The frequency of refresh operations can be reduced significantly, significantly reducing power consumption. In addition, even if there is no power supply, the memory contents can be maintained for a long period of time. It is possible to retain it.

[0203] The memory cell 4250 shown in FIG. 10 includes a drive circuit for driving the memory cell 4250. It is preferable to stack a substrate on which the memory cell 4250 and the driver circuit are formed. This allows the semiconductor device to be miniaturized. The number of the driving circuits is not limited.

[0204] The transistors included in the driver circuit are made of a semiconductor material different from that of the transistor 4300. For example, silicon, germanium, silicon germanium, silicon carbide, It is preferable to use a single crystal semiconductor. A transistor using such a semiconductor material is a transistor using an oxide semiconductor. It is possible to operate at a higher speed than the memory cell 4250, and is suitable for use in configuring a drive circuit for the memory cell 4250. is doing.

[0205] As described above, semiconductors that have achieved miniaturization and high integration and have been endowed with high electrical properties are An apparatus can be provided.

[0206] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0207] (Embodiment 5) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the following.

[0208] FIG. 11(A) shows a circuit diagram of the semiconductor device, and FIGS. 11(C) and 11(D) show cross-sectional views of the semiconductor device. 11(C) and (D) show the channel of the transistor 2100 on the left side. The cross section in the longitudinal direction is shown on the right, and the cross section in the channel width direction is shown on the right. To clearly indicate that the transistor uses an oxide semiconductor, the word "OS" is used. It is attached.

[0209] The semiconductor device shown in FIGS. 11(C) and 11(D) has a transistor using a first semiconductor material in the lower part. The transistor 2200 has a second semiconductor material on top of it. Here, the transistor 2100 using the second semiconductor material is the transistor 2100 shown in Embodiment 1. An example in which the transistor 100 is applied will be described.

[0210] Here, the first semiconductor material and the second semiconductor material have different energy gaps. For example, it is desirable to use a semiconductor material other than an oxide semiconductor (such as silicon) as the first semiconductor material. gallium arsenide, silicon germanium, silicon carbide, or gallium arsenide, etc. ) and the second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors using single crystal silicon or other materials other than oxide semiconductors can operate at high speed. On the other hand, a transistor including an oxide semiconductor has a low off-state current.

[0211] Here, the transistor 2200 will be described as a p-channel transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. In addition to using the transistor including an oxide semiconductor as described in Embodiment 1, The specific configuration of a semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is described here. It is not necessary to limit the scope to those shown in .

[0212] The configurations shown in Figures 11(A), (C), and (D) are p-channel transistors and n-channel This is called CMO, in which two transistors of the same type are connected in series and their gates are connected. An example of the configuration of an S circuit is shown.

[0213] The transistor including the oxide semiconductor of one embodiment of the present invention has a high on-state current. This allows the circuit to operate at high speed.

[0214] In the structure shown in FIG. 11C, a transistor 2200 is provided with an insulating layer 2201 interposed therebetween. A transistor 2100 is provided. Also, a transistor 2200 and a transistor 2 A plurality of wirings 2202 are provided between the wirings 100. In addition, a plurality of wirings 2202 are embedded in various insulating layers. The wiring and electrodes provided on the upper and lower parts are electrically connected by a number of plugs 2203. In addition, an insulating layer 2204 covering the transistor 2100 and a thin film transistor 2206 on the insulating layer 2204 are provided. The wiring 2205 and the wiring 2202 formed by processing the same conductive film as the pair of electrodes of the transistor. 206 and are provided.

[0215] In this way, stacking two transistors reduces the area occupied by the circuit, This allows multiple circuits to be arranged at a higher density.

[0216] In FIG. 11C, one of the source and drain of the transistor 2100 and the Either the source or the drain of the capacitor 2200 is electrically connected by a wiring 2202 or a plug 2203. The gate of the transistor 2100 is connected to the wiring 2205 and the wiring 2206. 06, the gate of the transistor 2200 via the plug 2203 and the wiring 2202, etc. It is electrically connected to the

[0217] In the structure shown in FIG. 11(D), a plug 2203 is formed in the gate insulating film of the transistor 2100. An opening for embedding is provided, and the gate of the transistor 2100 and the plug 2203 are connected. This configuration makes it easy to integrate circuits, and Therefore, the number and length of wiring and plugs to be passed through can be reduced compared to the configuration shown in FIG. This allows the circuit to operate at higher speeds.

[0218] Here, in the configurations shown in FIGS. 11(C) and 11(D), the transistor 2100 and the transistor By changing the electrode connection configuration of the capacitor 2200, various circuits can be configured. For example, as shown in FIG. 11(B), the source and drain of each transistor are connected. By using a circuit configuration with this, it can function as a so-called analog switch. Cut.

[0219] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0220] (Embodiment 6) In this embodiment, an image sensor for reading information on an object using a transistor according to one embodiment of the present invention will be described. A semiconductor device having a range sensor function will be described.

[0221] FIG. 12 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0222] The photodiode 610 has one electrode connected to a photodiode reset signal line 661 and the other One electrode is electrically connected to the gate of transistor 640. In this case, one of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other input is electrically connected to either the source or the drain of the transistor 650. The transistor 650 has a gate connected to a gate signal line 662 and a source or drain connected to a gate signal line 663. The other end is electrically connected to a photosensor output signal line 671 .

[0223] The photodiode 610 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance (i A pin-type semiconductor layer is formed by stacking a semiconductor layer having a n-type conductivity and a semiconductor layer having an n-type conductivity. A photodiode can be applied.

[0224] By detecting the light incident on the photodiode 610, information on the detected object is read. When reading the information of the detected object, a light source such as a backlight is used. It is also possible to do so.

[0225] The transistors 640 and 650 are made of the same material as the oxide semiconductor layer described in the first embodiment. A transistor 100 having a channel formed in a compound semiconductor can be used. It is clearly understood that the transistor 640 and the transistor 650 include an oxide semiconductor. To clarify, the transistor symbols are marked with "OS." The transistor 650 has a high on-state current and is electrically stable with reduced fluctuations in electrical characteristics. By including the transistor, the image sensor function shown in FIG. As a semiconductor device having such a structure, a highly reliable semiconductor device can be provided.

[0226] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0227] (Embodiment 7) The transistors described in the first and second embodiments are applicable to display devices, memory devices, CPUs, DSPs, and other devices. (Digital Signal Processor), Custom LSI, PLD(P LSIs such as programmable logic devices, RF-IDs (Radio Frequency Identification io Frequency Identification), inverter, image sensor In this embodiment, the semiconductor device can be applied to a semiconductor device such as a semiconductor device having a An example of such an electronic device will be described below.

[0228] Examples of electronic devices having the semiconductor device include display devices such as televisions and monitors, lighting devices, and panels. Personal computers, word processors, image playback devices, portable audio players Radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones , transceivers, radios, game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translation Translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips , microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioners air conditioning equipment such as showers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, radiation measuring devices, dialysis machines, X-ray machines Medical equipment such as diagnostic equipment, etc. Smoke detectors, heat detectors, gas alarms, Examples include alarm devices such as burglar alarms. In addition, guide lights, traffic lights, conveyor belts, Industrial equipment such as elevators, escalators, industrial robots, and power storage systems are also included. In addition, the vehicle is propelled by an engine using fuel or an electric motor using power from a non-aqueous secondary battery. Moving objects that move forward are also included in the category of electronic devices. , electric vehicles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, Hybrid electric vehicles (PHEVs), tracked vehicles that replace these tires with tracks, Motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, Small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes Examples of these electronic devices include planetary probes and spacecraft. Some specific examples are shown in Figure 13.

[0229] A television set 8000 shown in FIG. 13A includes a housing 8001 and a display unit 8002. The display unit 8002 displays images and the speaker unit 8003 outputs audio. The memory device including the transistor of one embodiment of the present invention can be used in the display portion 80. It can be used in a drive circuit to operate the .O2.

[0230] The television device 8000 also includes a CPU 8004 for performing information communication and a memory. The CPU 8004 and the memory may include a transistor according to one embodiment of the present invention. A CPU and a storage device can be used.

[0231] The alarm device 8100 shown in FIG. 13(A) is a residential fire alarm, and includes a smoke or heat detection unit. 8102 and an example of an electronic device using a microcomputer 8101. The computer 8101 includes a memory device having a transistor according to one embodiment of the present invention and a CPU. .

[0232] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The conductor may be an electronic device including a transistor, a memory device, a CPU, or the like described in the above embodiments. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CP In FIG. 13A, the CPU 8203 is configured to The CPU 8203 is provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor according to one embodiment of the present invention may be used in a CPU of an air conditioner. This can save power.

[0233] The electric refrigerator-freezer 8300 shown in FIG. 13(A) is a transistor-type refrigerator shown in the above embodiment. This is an example of an electronic device that includes a CPU, a memory device, or a CPU. The storage 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 830 13A, a CPU 8304 is provided inside a housing 8301. The transistor of one embodiment of the present invention is used for the CPU 8304 of the electric refrigerator-freezer 8300. This will help save power.

[0234] 13B and 13C show an example of an electric vehicle, which is an example of an electronic device. The power supply 9701 is supplied to the circuit 97 The output is adjusted by the circuit 9702 and supplied to the driver 9703. The present invention is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. The use of a transistor according to one embodiment in a CPU of an electric vehicle 9700 can reduce power consumption. can be.

[0235] The drive unit 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine. The processing device 9704 is configured by combining the operation information of the driver of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., Based on input information (load information, etc.), the control signal is output to the circuit 9702. The electric energy supplied from the secondary battery 9701 is controlled by a control signal from the processor 9704. The output of the drive unit 9703 is controlled by adjusting the value of the AC motor. Although not shown, it also has a built-in inverter that converts direct current to alternating current.

[0236] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. [Example]

[0237] In this example, the stacked state of the oxide semiconductor layers described in Embodiment 1 was observed. The details will be explained below.

[0238] FIG. 14 is a cross-sectional view showing the structure of the sample used in this example. 10, a base insulating film 420, a first oxide semiconductor layer 431 and a second oxide semiconductor layer 432 on the base insulating film, a stack of the oxide semiconductor layer 432 and a third oxide semiconductor layer formed on the stack; The first oxide semiconductor layer 431 and the second oxide semiconductor layer 432 The third oxide semiconductor layer 433 is the same as the first oxide semiconductor layer 1 described in Embodiment 1. 31, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133, respectively. do.

[0239] Next, a method for producing the sample shown in FIG. 14 will be described.

[0240] First, a silicon wafer is used as the substrate 410, and the silicon wafer is thermally oxidized. A silicon oxide film was formed as the insulating base film 420 .

[0241] Next, a first In- Ga-Zn oxide film, In:Ga:Zn=1:1:1 (atomic ratio) second In-Ga- The first In-Ga-Zn oxide film was formed by sputtering. The thicknesses of the first and second In-Ga-Zn oxide films were 20 nm and 15 nm, respectively.

[0242] The deposition conditions for the first In-Ga-Zn oxide film were In:Ga:Zn=1:3:4 (atomic number Ratio) φ8 inch In-Ga-Zn oxide target, sputtering gas: argon Oxygen = 2:1 (flow ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC), The get-substrate distance was 60 mm, and the substrate temperature was 200°C.

[0243] The deposition conditions for the second In-Ga-Zn oxide film were In:Ga:Zn=1:1:1 ( The target was an In-Ga-Zn oxide (In-Ga-Zn oxide) with a diameter of 8 inches and a sputtering gas of Al. Gas:oxygen = 2:1 (flow ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC) The target-substrate distance was 60 mm, and the substrate temperature was 300°C.

[0244] Next, the first In-Ga-Zn oxide film and the second In-Ga-Zn oxide film were heated at 450 Heat treatment was performed at 450°C in a nitrogen atmosphere for 1 hour, and then heat treatment was performed at 450°C in an oxygen atmosphere for 1 hour. was carried out.

[0245] Next, a 5 nm tungsten film and a 20 nm silicon dioxide film were deposited on the second In-Ga-Zn oxide film. A resin was formed on the substrate, and a resist mask was formed by electron beam exposure.

[0246] Then, the organic resin and the tungsten film are selectively removed using the resist mask. The etching method was a two-step process using an inductively coupled dry etching device. Etching was carried out.

[0247] For the first etching step, the etching gas was 100% carbon tetrafluoride, and the pressure was 0.67 Pa, input power 2000W, bias power 50W, substrate temperature -10℃, etching The etching time was 12 seconds. In the second stage, the etching gas was 4 fl oz. Carbon fluoride: oxygen = 3:2 (flow ratio), pressure 2.0 Pa, input power 1000 W, substrate The conditions used were a bias power of 25 W, a substrate temperature of -10°C, and an etching time of 8 seconds.

[0248] Next, using the organic resin and tungsten film as a mask, a first In-Ga-Zn oxide film and the second In-Ga-Zn oxide film is selectively etched to form the first oxide semiconductor layer. A stack of a first oxide semiconductor layer 431 and a second oxide semiconductor layer 432 was formed. A dry etching system was used, and the etching gas was methane:argon = 1:2 (flow ratio ), pressure 1.0 Pa, input power 600 W, substrate bias power 100 W, substrate temperature The etching conditions were 70°C and 82 seconds.

[0249] Next, the organic resin and tungsten film were etched using an inductively coupled etching method. A dry etching system was used, and the etching gas was carbon tetrafluoride: oxygen = 3:2 (flow rate Ratio), pressure 2.0 Pa, input power 1000 W, substrate bias power 25 W, substrate temperature The etching temperature was -10°C and the etching time was 6 seconds.

[0250] Then, a 10-layer insulating film was formed on the stack of the first oxide semiconductor layer 431 and the second oxide semiconductor layer 432. A third oxide semiconductor layer 433 with a thickness of 1 nm was formed by a sputtering method.

[0251] The third oxide semiconductor layer 433 was formed under the following conditions: In:Ga:Zn=1:3:4 (atomic ratio) The sputtering gas was argon:oxygen. = 2:1 (flow ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC), target The distance between the substrate and the substrate was 60 mm, and the substrate temperature was 200°C.

[0252] A cross-sectional TEM photograph of the region surrounded by the dotted line in FIG. 14 is shown in FIG. 15(A). No crystal lattice is observed in the region of several nm from the base insulating film 420 side of the compound semiconductor layer 431. However, lattice fringes were observed in the upper portion of the second oxide semiconductor layer 432. The same lattice fringes as those of the first oxide semiconductor layer 431 were observed. Most of the second oxide semiconductor layer 431 and the entire second oxide semiconductor layer 432 are crystalline layers, and the orientation of the lattice fringes is From this, it was found that the CAAC-OS film had a c-axis orientation perpendicular to the deposition surface. Ta.

[0253] In addition, the third oxide semiconductor layer 433 is formed by the first oxide semiconductor layer 431 or the second oxide semiconductor layer 432. No crystal lattice is observed in the region of several nm on the conductor layer 432 side, but the lattice is not observed above it. Stripes were observed. That is, the third oxide semiconductor layer 433 was divided into a microcrystalline layer 433a and a crystalline layer 433b. It was confirmed to be 33b.

[0254] The lattice fringes observed in the crystal layer 433b are formed by the upper portion of the second oxide semiconductor layer 432 and the upper portion of the first oxide semiconductor layer 433b. The orientation is different at the side of the oxide semiconductor layer 431 or the second oxide semiconductor layer 432. It was found that the CAAC-OS film had its c-axis oriented perpendicular to the deposition surface.

[0255] Also, as is clear from FIG. 15(B), which is an enlarged view of the dotted line frame in FIG. 15(A), The oxide semiconductor layer 432 is provided on the curved end region thereof with the microcrystalline layer 433a interposed therebetween. Lattice fringes of the crystal layer 433b with its c-axis oriented perpendicular to the curved surface were observed.

[0256] The results of this example demonstrate that the stacked structure of oxide semiconductor layers according to one embodiment of the present invention can be fabricated. It was confirmed that this is possible.

[0257] This embodiment can be appropriately combined with the embodiment modes shown in this specification. [Explanation of symbols]

[0258] 100 transistors 110 Substrate 120 Undercoat insulating film 130 Oxide semiconductor layer 131 First oxide semiconductor layer 132 Second oxide semiconductor layer 132b area 133 Third oxide semiconductor layer 133a Microcrystalline layer 133b Crystal layer 135 Boundary 140 Source electrode layer 150 drain electrode layer 160 Gate insulating film 170 gate electrode layer 172 Conductive film 180 insulating layer 185 Insulating Layer 233 areas 331 First oxide semiconductor film 332 Second oxide semiconductor film 333 Third oxide semiconductor film 360 insulating film 370 Second conductive film 410 board 420 Undercoat insulating film 431 First oxide semiconductor layer 432 Second oxide semiconductor layer 433 Third oxide semiconductor layer 433a Microcrystalline layer 433b Crystal layer 610 Photodiode 640 transistors 650 transistors 661 Photodiode reset signal line 662 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 2100 transistors 2200 transistors 2201 Insulation layer 2202 Wiring 2203 Plug 2204 Insulation layer 2205 Wiring 2206 Wiring 3000 boards 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3100 Element isolation insulating layer 3150 Insulation layer 3200 transistors 3250 electrode 3300 transistors 3400 Capacitor 4250 memory cells 4300 transistors 4400 Capacitor 4500 Wiring 4600 Wiring 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detector 8200 indoor unit 8201 Housing 8202 Ventilation outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing equipment

Claims

1. a first conductive layer located on the insulating surface and functioning as a gate electrode of a transistor; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer; a second conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor layer includes a first layer in which no crystal lattice is observed in a cross-sectional photograph taken with a transmission electron microscope, and a second layer having a region located above the first layer and in which lattice fringes are observed in the cross-sectional photograph taken with a transmission electron microscope; the second layer has a first region disposed substantially parallel to the insulating surface and a second region disposed in a direction intersecting the insulating surface; The semiconductor device, wherein the orientation of the lattice pattern in the first region and the orientation of the lattice pattern in the second region are different from each other.

2. a first conductive layer located on the insulating surface and functioning as a gate electrode of a transistor; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer; a second conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor layer includes a first layer in which no crystal lattice is observed in a cross-sectional photograph taken with a transmission electron microscope, and a second layer disposed above and in contact with the first layer, in which lattice fringes are observed in the cross-sectional photograph taken with a transmission electron microscope; the second layer has a first region disposed substantially parallel to the insulating surface and a second region disposed in a direction intersecting the insulating surface; The semiconductor device, wherein the orientation of the lattice pattern in the first region and the orientation of the lattice pattern in the second region are different from each other.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

Images