Method for manufacturing substrate with chips and substrate processing device

Abstract

To provide a technique of reusing alignment marks.SOLUTION: A method for manufacturing a substrate with chips includes the following steps (A)-(B). (A) A stacked substrate is prepared, the stacked substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate with the plurality of chips interposed therebetween. (B) The plurality of chips bonded to the first substrate and the second substrate are separated from the first substrate to be bonded to one side including a device layer of a third substrate. The first substrate from which the chips are separated includes an alignment mark used for positioning the chips and the first substrate when bonding, and for measuring a positional shift after bonding.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a substrate with chips, and a substrate processing apparatus. [Background technology]

[0002] 20 of Patent Document 1 illustrates a chip-on-wafer manufacturing process, in which individual first memory chips are bonded one by one to a base wafer on which a plurality of second memory chips are formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2015-46569 Summary of the Invention [Problem to be solved by the invention]

[0004] One aspect of the present disclosure provides a technique for reusing alignment marks used for aligning a chip and a substrate when they are bonded together or for measuring misalignment after bonding. [Means for solving the problem]

[0005] A method for manufacturing a substrate with chips according to one embodiment of the present disclosure includes the following steps (A) and (B): (A) preparing a laminated substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips; (B) separating the plurality of chips bonded to the first substrate and the second substrate from the first substrate so as to bond them to one side of a third substrate including a device layer; and (C) the first substrate separated from the chips includes an alignment mark used for aligning the chips when bonding them to the first substrate or for measuring misalignment after bonding. [Effects of the Invention]

[0006] According to one aspect of the present disclosure, alignment marks can be reused. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a flowchart showing a method for manufacturing a chip-mounted substrate according to one embodiment. [Figure 2] FIG. 2 is a flowchart showing the details of S1 in FIG. [Figure 3] FIG. 3 is a flowchart showing the details of S6 in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing a state during S1 in FIG. [Figure 5] FIG. 5 is a cross-sectional view showing the state at the completion of S1 in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing the state upon completion of S2 in FIG. [Figure 7] FIG. 7 is a cross-sectional view showing the state upon completion of S3 in FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a state during S4 in FIG. [Figure 9] FIG. 9 is a cross-sectional view showing the state upon completion of S4 in FIG. [Figure 10] FIG. 10 is a cross-sectional view showing the state upon completion of S5 in FIG. [Figure 11] FIG. 11 is a cross-sectional view showing the state at the completion of S61 in FIG. 3, which is included in S6 in FIG. [Figure 12] FIG. 12 is a cross-sectional view showing the state at the completion of S62 in FIG. 3, which is included in S6 in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing the state at the completion of S63 in FIG. 3, which is included in S6 in FIG. [Figure 14] FIG. 14 is a cross-sectional view showing the state upon completion of S7 in FIG. [Figure 15A] FIG. 15A is a cross-sectional view showing an example of a first step of a method for forming a Ge film. [Figure 15B] FIG. 15B is a cross-sectional view showing an example of a second step of the method for forming a Ge film. [Figure 15C] FIG. 15C is a cross-sectional view showing an example of a third step of the method for forming a Ge film. [Figure 15D] FIG. 15D is a cross-sectional view showing an example of a fourth step of the method for forming a Ge film. [Figure 15E] FIG. 15E is a cross-sectional view illustrating an example of the fifth step of the method for forming a Ge film. [Figure 15F] FIG. 15F is a cross-sectional view showing an example of the sixth step of the method for forming a Ge film. [Figure 16] FIG. 16 is a diagram showing an example of the transmittance of a SiGe film. [Figure 17A] FIG. 17A is a cross-sectional view showing an example of a first step of a method for forming a metal silicide film. [Figure 17B] FIG. 17B is a cross-sectional view showing an example of a second step of the method for forming a metal silicide film. [Figure 17C] FIG. 17C is a cross-sectional view showing an example of a third step of the method for forming a metal silicide film. [Figure 17D] FIG. 17D is a cross-sectional view showing an example of the fourth step of the method for forming a metal silicide film. [Figure 17E] FIG. 17E is a cross-sectional view showing an example of the fifth step of the method for forming a metal silicide film. [Figure 17F] FIG. 17F is a cross-sectional view showing an example of the sixth step of the method for forming a metal silicide film. [Figure 17G] FIG. 17G is a cross-sectional view showing an example of the seventh step of the method for forming a metal silicide film. [Figure 18] FIG. 18 is a diagram showing an example of the absorption rate of a metal silicide film. [Figure 19A] FIG. 19A is a cross-sectional view showing an example of a first step of a method for forming an AlN film. [Figure 19B] FIG. 19B is a cross-sectional view showing an example of a second step of the method for forming an AlN film. [Figure 19C] FIG. 19C is a cross-sectional view showing an example of a third step of the method for forming an AlN film. [Figure 19D] FIG. 19D is a cross-sectional view showing an example of a fourth step of the method for forming an AlN film. [Figure 19E] FIG. 19E is a cross-sectional view illustrating an example of the fifth step of the method for forming an AlN film. [Figure 19F] FIG. 19F is a cross-sectional view showing an example of the sixth step of the method for forming an AlN film. [Figure 19G] FIG. 19G is a cross-sectional view showing an example of the seventh step of the method for forming an AlN film. [Figure 20] FIG. 20 is a diagram showing an example of the transmittance of an AlN film. [Figure 21] FIG. 21 is a plan view showing a substrate processing apparatus according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or corresponding components are denoted by the same reference numerals, and descriptions thereof may be omitted.

[0009] The method for manufacturing a substrate with chips includes, for example, steps S1 to S7 shown in Fig. 1. S1 in Fig. 1 includes, for example, steps S11 to S14 shown in Fig. 2. Furthermore, S6 shown in Fig. 1 includes, for example, steps S61 to S63 shown in Fig. 3.

[0010] First, in S1 of Fig. 1, the first substrate 1 and the chips 2A and 2B are bonded together as shown in Fig. 4 and Fig. 5. In S11 of Fig. 2, which is included in S1 of Fig. 1, the first substrate 1 and the chips 2A and 2B are prepared.

[0011] The first substrate 1 has, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13. As will be described later, the absorption layer 12 may also serve as the bonding layer 13, and the first substrate 1 may have the silicon wafer 11 and the absorption layer 12. A compound semiconductor wafer may be used instead of the silicon wafer 11. The compound semiconductor wafer is not particularly limited, but may be, for example, a GaAs wafer, a SiC wafer, a GaN wafer, an InP wafer, or an AlN wafer.

[0012] The absorption layer 12 is disposed between the silicon wafer 11 and the chips 2A and 2B. As will be described in more detail later, as shown in FIG. 11, the laser beam LB2 passes through the silicon wafer 11 and is absorbed by the absorption layer 12. Since the laser beam LB2 is absorbed by the absorption layer 12 and does not strike the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed. The absorption layer 12 is, for example, a silicon oxide layer, and is formed by thermal oxidation, CVD (Chemical Vapor Depositon), or the like.

[0013] The absorption layer 12 may be a silicon nitride layer, a silicon carbonitride layer, or the like, as long as it can absorb the laser beam LB2 to an extent that damage to the chips 2A and 2B can be suppressed. The silicon nitride layer is formed by a thermal nitridation method, a CVD method, or the like. The silicon carbonitride layer is formed by a CVD method, or the like.

[0014] As shown in FIG. 4, the bonding layer 13 is disposed between the absorption layer 12 and the chips 2A and 2B and is in contact with the chips 2A and 2B. The bonding layer 13 is, for example, an insulating layer such as a silicon oxide layer. The bonding layer 13 may be made of a different material from the absorption layer 12, or may be made of the same material. In the latter case, the absorption layer 12 may also serve as the bonding layer 13.

[0015] The first substrate 1 includes an alignment mark 15. The alignment mark 15 is used for aligning the first substrate 1 and the chips 2A and 2B when they are bonded together, or for measuring misalignment after bonding. The alignment mark 15 may be used for both alignment and misalignment measurement. The measurement result of the misalignment after bonding is used, for example, for aligning the first substrate 1 and the chips when they are bonded together next time and thereafter. The measurement result of the misalignment after bonding may also be used for quality control, such as for identifying defective products.

[0016] As shown in Figure 12, alignment mark 15 is formed between silicon wafer 11 and absorption layer 12, on the opposite side of chips 2A and 2B with respect to dividing plane D. By dividing first substrate 1 at dividing plane D, silicon wafer 11 and chips 2A and 2B can be separated. Silicon wafer 11 separated from chips 2A and 2B has alignment mark 15. Therefore, when silicon wafer 11 is reused, alignment mark 15 does not need to be formed again, and alignment mark 15 can be reused.

[0017] The alignment mark 15 absorbs the infrared rays used to image the alignment mark 15. The infrared camera captures an image of the alignment mark 15 by receiving the infrared rays that have passed through the silicon wafer 11. The wavelength of the infrared rays used for imaging is different from the wavelength of the laser beam LB2 and is, for example, 1000 nm to 2000 nm. The absorption rate of the alignment mark 15 for the infrared rays used for imaging the alignment mark 15 is, for example, 45% to 100%, preferably 50% to 100%, and more preferably 60% to 100%.

[0018] As shown in FIG. 11, the alignment mark 15 transmits a laser beam LB2. The laser beam LB2 transmits through the silicon wafer 11 and the alignment mark 15, and forms a modified layer M in the absorption layer 12. The absorption layer 12 absorbs the laser beam LB2, thereby forming the modified layer M. A plurality of modified layers M are formed on the division surface D. Division occurs starting from the plurality of modified layers M. The wavelength of the laser beam LB2 is, for example, 8800 nm to 11000 nm. The alignment mark 15 has a transmittance of the laser beam LB2 of, for example, 45% to 100%, preferably 50% to 100%, and more preferably 60% to 100%.

[0019] As described above, the alignment mark 15 is formed from a material that absorbs the infrared rays used to image the alignment mark 15 and transmits the laser beam LB2. Specifically, the alignment mark 15 includes, for example, a Ge film, a SiGe film, a metal silicide film, or an AlN film. Unlike SiO2 films and metal films, Ge films and the like absorb the infrared rays used for imaging and transmit the laser beam LB2. Incidentally, an SiO2 film transmits the infrared rays used for imaging and absorbs the laser beam LB2. Furthermore, a metal film can absorb the infrared rays used for imaging but also absorbs the laser beam LB2. A method for forming the alignment mark 15 will be described later.

[0020] The chip 2A has a silicon wafer 21A and a device layer 22A. The device layer 22A is formed on the surface of the silicon wafer 21A. The device layer 22A includes semiconductor elements, circuits, terminals, etc. After the device layer 22A is formed, the silicon wafer 21A is divided into a plurality of chips 2A.

[0021] Like chip 2A, chip 2B has a silicon wafer 21B and a device layer 22B. Device layer 22B has a different function from device layer 22A and a different thickness from chip 2A and chip 2B. After forming device layer 22B, silicon wafer 21B is diced into a plurality of chips 2B.

[0022] 2, which is included in S1 in Fig. 1, the bonding surface 14 of the first substrate 1 is surface-modified using plasma or the like. Specifically, the SiO2 bonds on the bonding surface 14 are cut, and dangling Si bonds are formed, making the bonding surface 14 hydrophilic.

[0023] For example, oxygen gas as a processing gas is excited to form plasma and ionized under a reduced pressure atmosphere. The oxygen ions are irradiated onto the bonding surface 14, thereby modifying the bonding surface 14. The processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.

[0024] In S12, the surfaces of the bonding surfaces 24A and 24B of the chips 2A and 2B may also be modified in addition to the bonding surface 14 of the first substrate 1. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is surface modified.

[0025] 2, which is included in S1 in Fig. 1, the bonding surface 14 of the first substrate 1 is hydrophilized. For example, the first substrate 1 is held by a spin chuck, and pure water such as DIW (deionized water) is supplied to the bonding surface 14 of the first substrate 1, which rotates together with the spin chuck. OH groups are attached to the dangling bonds of Si on the bonding surface 14, making the bonding surface 14 hydrophilic.

[0026] In the above S13, not only the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be hydrophilized. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is hydrophilized.

[0027] 2, which is included in S1 in FIG. 1, the chips 2A and 2B are temporarily bonded one by one to the bonding surface 14 of the first substrate 1. The chips 2A and 2B are bonded to the first substrate 1 with the device layers 22A and 22B facing the first substrate 1.

[0028] The chips 2A and 2B and the first substrate 1 are bonded together by van der Waals forces (intermolecular forces) and hydrogen bonding between OH groups. A heat treatment may then be performed to increase the bonding strength. The heat treatment causes a dehydration reaction. Because solids are directly bonded together without using a liquid adhesive, misalignment due to deformation of the adhesive and tilting due to uneven thickness of the adhesive can be prevented.

[0029] However, in Patent Document 1, unlike the technology of the present disclosure, chips 2A and 2B are permanently bonded to a third substrate 6 (described below) without taking the step of temporarily bonding chips 2A and 2B to a first substrate 1. Therefore, during bonding, it is required to simultaneously prevent air bubbles and foreign matter from getting caught and to perform accurate position control.

[0030] When chips 2A and 2B are bonded one by one to third substrate 6 as in Patent Document 1, the inclusion of air bubbles during bonding can be prevented by deforming chips 2A and 2B one by one. Bonding surfaces 24A and 24B of chips 2A and 2B are deformed into downwardly convex curved surfaces, gradually bonded to third substrate 6 from the center toward the periphery, and finally return to a flat surface.

[0031] Deforming the bonding surfaces 24A, 24B of the chips 2A, 2B into downwardly convex curved surfaces involves fixing the peripheries of the chips 2A, 2B and pressing down the centers of the chips 2A, 2B. However, because the chips 2A, 2B are small, the distance between the fixing points and the pressing points is narrow. Therefore, it is difficult to deform the chips 2A, 2B one by one.

[0032] According to this embodiment, chips 2A and 2B are temporarily bonded to first substrate 1 and then separated from first substrate 1. Therefore, even if air bubbles are trapped when bonding chips 2A and 2B to first substrate 1, this does not pose a problem. Therefore, in S14 above, bonding surfaces 24A and 24B of chips 2A and 2B can be bonded to bonding surface 14 of first substrate 1 while remaining flat. Because chips 2A and 2B are not deformed, the accuracy of positional control of chips 2A and 2B can be improved, and chips 2A and 2B can be accurately placed in the desired positions.

[0033] Furthermore, according to this embodiment, the chips 2A and 2B are temporarily bonded to the first substrate 1 and then separated from the first substrate 1. Therefore, even if particles get caught between the chips 2A and 2B and the first substrate 1 when they are bonded, it does not cause any problems. Therefore, the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be contaminated to the extent that it does not interfere with bonding. This reduces the required cleanliness level.

[0034] Next, in S2 of FIG. 1, as shown in FIG. 6, the multiple chips 2A and 2B are thinned to make their thickness uniform. In FIG. 6, the two-dot chain line indicates the state immediately before S2, and the solid line indicates the state at the completion of S2. Of the chips 2A and 2B, the silicon wafers 21A and 21B are thinned, but the device layers 22A and 22B are not thinned. Thinning includes grinding or laser processing.

[0035] Next, in S3 of Fig. 1, as shown in Fig. 7, a bonding layer 3 is formed on the surfaces of chips 2A and 2B. Like bonding layer 13 of first substrate 1, bonding layer 3 is an insulating layer such as a silicon oxide layer, and is formed by a CVD method or the like. Chips 2A and 2B are arranged at a distance from each other, and the surface underlying bonding layer 3 has an uneven surface, so the surface of bonding layer 3 also has an uneven surface.

[0036] 1, the surface of the bonding layer 3 is planarized as shown in Fig. 8 and Fig. 9. The bonding layer 3 is a silicon oxide layer or the like and has high hardness, so polishing by CMP (Chemical Mechanical Polishing) or the like takes time to planarize the surface.

[0037] Therefore, first, as shown in Fig. 8, a laser beam LB1 is irradiated onto the protrusions 31 of the bonding layer 3. The protrusions 31 absorb the laser beam LB1 and either change from a solid phase to a gas phase and scatter, or scatter while remaining in the solid phase. The laser beam LB1 may also be irradiated onto the recesses 32 of the bonding layer 3. If the irradiation intensity of the recesses 32 is lower than that of the protrusions 31, the surface of the bonding layer 3 can be flattened.

[0038] The irradiation point of the laser beam LB1 is moved by a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB1. The XYθ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis. An XYZθ stage may be used instead of the XYθ stage.

[0039] 9, the surface of the bonding layer 3 is further planarized by CMP or the like. Since the protrusions 31 have been selectively removed before CMP, waviness remaining on the surface of the bonding layer 3 after CMP can be reduced.

[0040] 1, chips 2A and 2B are bonded to second substrate 5 as shown in Fig. 10. Second substrate 5 comes into contact with the flattened surface of bonding layer 3 and is bonded to chips 2A and 2B via bonding layer 3.

[0041] The second substrate 5 has, for example, a silicon wafer 51 and a bonding layer 53. The bonding layer 53 is an insulating layer such as a silicon oxide layer, similar to the bonding layer 13 of the first substrate 1, and is formed by a CVD method or the like.

[0042] At least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3 may be subjected to surface modification and hydrophilization before bonding. The second substrate 5 and the bonding layer 3 are bonded by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded together without using a liquid adhesive, misalignment due to deformation of the adhesive can be prevented. In addition, tilting due to uneven thickness of the adhesive can be prevented.

[0043] The second substrate 5 is bonded to the first substrate 1 via the bonding layer 3, with its bonding surface 54 facing downward. That is, the substrates are bonded together. At this time, the bonding surface 54 of the second substrate 5 is deformed into a downwardly convex curved surface to prevent the inclusion of air bubbles, and is gradually bonded from the center toward the periphery, finally returning to a flat surface.

[0044] The second substrate 5 can be deformed by fixing the periphery of the second substrate 5 and pressing down on the center of the second substrate 5. When deforming the second substrate 5, the distance between the fixing point and the pressing point is wider than when deforming the chips 2A and 2B one by one, so deformation is easier. Deformation is easy because the substrates are bonded together.

[0045] The positions of the second substrate 5 and the first substrate 1 may be reversed, with the second substrate 5 being placed below the first substrate 1 and the bonding surface 54 of the second substrate 5 facing upward. In this case, the bonding surface 54 of the second substrate 5 is deformed into an upwardly convex curved surface to prevent the inclusion of air bubbles, and is gradually bonded from the center toward the periphery, finally returning to a flat surface.

[0046] The bonding of the second substrate 5 and the first substrate 1 is carried out gradually from the center to the periphery, so the second substrate 5 is bent first, but the first substrate 1 may be bent first. In this case, the substrates are also bonded together. However, from the viewpoint of protecting the chips 2A and 2B, it is preferable to hold the first substrate 1 flat and the chips 2A and 2B flat.

[0047] Next, in S6 of Fig. 1, as shown in Fig. 11, Fig. 12, and Fig. 13, chips 2A and 2B are separated from first substrate 1. In S61 of Fig. 3, which is included in S6 of Fig. 1, a plurality of modified layers M are formed with laser beam LB2 on dividing plane D along which first substrate 1 is to be divided in the thickness direction, as shown in Fig. 11. The modified layers M are formed in dots, for example, at or above the focusing point.

[0048] The laser beam LB2 passes through the silicon wafer 11 of the first substrate 1 and forms a modified layer M in the absorption layer 12 of the first substrate 1. The absorption layer 12 is disposed between the silicon wafer 11 and the chips 2A and 2B and absorbs the laser beam LB2. Because the laser beam LB2 hardly hits the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.

[0049] The laser beam LB2 has a wavelength of, for example, 8800 nm to 11000 nm so as to be transmitted through the silicon wafer 11 and the alignment mark 15 and absorbed by the absorption layer 12. The light source of the laser beam LB2 is, for example, a CO2 laser. The wavelength of the CO2 laser is approximately 9300 nm. The laser beam LB2 is pulsed.

[0050] The formation position of the modified layer M is moved by a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB2. The XYθ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis. An XYZθ stage may be used instead of the XYθ stage.

[0051] A plurality of modified layers M are formed at intervals in the circumferential and radial directions of the first substrate 1. When the modified layers M are formed, cracks CR that connect the modified layers M to each other are also formed.

[0052] 3, which is included in S6 in FIG. 1, the first substrate 1 is divided starting from the modified layer M, as shown in FIG. 12. First, the upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5. However, the first substrate 1 and the second substrate 5 may be arranged upside down, or the upper chuck 131 may hold the second substrate 5, and the lower chuck 132 may hold the first substrate 1. Next, when the upper chuck 131 is raised relative to the lower chuck 132, a crack CR spreads planarly starting from the modified layer M, and the first substrate 1 is divided at the dividing plane D.

[0053] In S62 above, the upper chuck 131 may be rotated about its vertical axis as it is raised. The first substrate 1 can be twisted off at the dividing plane D. Instead of or in addition to raising the upper chuck 131, the lower chuck 132 may be lowered. The lower chuck 132 may also be rotated about its vertical axis.

[0054] In S63 of FIG. 3, which is included in S6 of FIG. 1, residues 16 of the first substrate 1 adhering to the chips 2A and 2B are removed by CMP or the like, as shown in FIG. 13. The residues 16 include a part of the absorption layer 12 and the bonding layer 13. After the residues 16 are removed, the device layers 22A and 22B of the chips 2A and 2B are exposed again. The device layers 22A and 22B are, for example, semiconductor memories.

[0055] 1, as shown in Fig. 14, the chips 2A and 2B are bonded to one side 64 of the third substrate 6, which includes the device layer 62, while still being bonded to the second substrate 5. The third substrate 6 includes a silicon wafer 61 and a device layer 62.

[0056] The device layer 62 is formed on the surface of the silicon wafer 61. The device layer 62 includes semiconductor elements, circuits, terminals, etc., and is electrically connected to the device layers 22A and 22B of the chips 2A and 2B. The device layer 62 is, for example, a peripheral circuit (also called "peripheral") of a semiconductor memory or an input / output circuit (also called "IO") of a semiconductor memory.

[0057] At least one of the bonding surface 64 of the third substrate 6 and the bonding surfaces 24A, 24B of the chips 2A, 2B may be subjected to surface modification and hydrophilization before bonding. The third substrate 6 and the chips 2A, 2B are bonded by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded together without using a liquid adhesive, misalignment due to deformation of the adhesive can be prevented. In addition, tilting due to uneven thickness of the adhesive can be prevented.

[0058] The third substrate 6 is bonded to the second substrate 5 via the chips 2A and 2B, with its bonding surface 64 facing downward. In other words, the substrates are bonded together. At this time, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface to prevent the inclusion of air bubbles, and is gradually bonded from the center toward the periphery, finally returning to a flat surface.

[0059] The third substrate 6 can be deformed by fixing the periphery of the third substrate 6 and pressing down on the center of the third substrate 6. When deforming the third substrate 6, the distance between the fixing point and the pressing point is wider than when deforming the chips 2A, 2B one by one, so deformation is easier. Deformation is easy because the substrates are bonded together.

[0060] The positions of the third substrate 6 and the second substrate 5 may be reversed, with the third substrate 6 placed below the second substrate 5, and the bonding surface 64 of the third substrate 6 facing upward. In this case, the bonding surface 64 of the third substrate 6 is deformed into an upwardly convex curved surface to prevent the entrapment of air bubbles, and is gradually bonded from the center toward the periphery, finally returning to a flat surface. In this case as well, the substrates are bonded together.

[0061] The third substrate 6 and the second substrate 5 are bonded gradually from the center toward the periphery by first bending and deforming the third substrate 6, but it is also possible to first bend and deform the second substrate 5. In this case as well, the substrates are bonded together.

[0062] By step S7, a substrate 7 with chips is obtained. The substrate 7 with chips includes a third substrate 6 and a plurality of chips 2A and 2B. The substrate 7 with chips further includes a second substrate 5. Note that the second substrate 5 may be separated from the chips 2A and 2B, and the substrate 7 with chips only needs to include the third substrate 6 and the chips 2A and 2B.

[0063] As described above, according to this embodiment, to obtain chip-mounted substrate 7, multiple chips 2A, 2B are not bonded one by one to one side of third substrate 6, but are first temporarily bonded to one side of first substrate 1. Because air bubbles are not a problem at this stage, bonding surfaces 24A, 24B of chips 2A, 2B can be bonded to bonding surface 14 of first substrate 1 while remaining flat. Because chips 2A, 2B do not need to be forcibly deformed, the accuracy of positional control of chips 2A, 2B can be improved, and chips 2A, 2B can be accurately placed in the desired position.

[0064] Thereafter, the plurality of chips 2A, 2B bonded to the first substrate 1 are bonded to the surface of the second substrate 5 facing the first substrate 1. Subsequently, the plurality of chips 2A, 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Next, the plurality of chips 2A, 2B separated from the first substrate 1 are bonded to one surface 64 of the third substrate 6, including the device layer 62, while still bonded to the second substrate 5.

[0065] At this time, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curve to prevent the entrapment of air bubbles, and is gradually bonded from the center toward the periphery, finally returning to a flat surface. Deforming the third substrate 6 is easier than deforming the chips 2A, 2B one by one because the substrates are bonded together. Therefore, compared to the case in which the chips 2A, 2B are permanently bonded to the third substrate 6 without the step of temporarily bonding the chips 2A, 2B to the first substrate 1 as in Patent Document 1, a chip-mounted substrate 7 is obtained that is free of entrapped air bubbles and has good positional accuracy.

[0066] Furthermore, according to this embodiment, the silicon wafer 11 separated from the chips 2A and 2B has alignment marks 15. Therefore, when the silicon wafer 11 is reused, it is not necessary to re-form the alignment marks 15, and it is possible to reuse the alignment marks 15. The silicon wafer 11 separated from the chips 2A and 2B is bonded to a chip other than the chips 2A and 2B.

[0067] Next, a method for forming a Ge film that is an alignment mark will be described with reference to Figures 15A to 15F. The method includes steps 1 to 6. In the first step, a silicon wafer 11 is prepared, as shown in Figure 15A.

[0068] 15B, the surface of the silicon wafer 11 is etched to form trenches. The depth of the trenches is not particularly limited, but is, for example, 100 nm.

[0069] 15C, an SiO2 film 17 is formed on the surface of the silicon wafer 11, and the trenches are filled with the SiO2 film 17. The SiO2 film 17 is formed by a CVD method using, for example, TEOS (tetraethoxysilane). The thickness of the SiO2 film 17 is not particularly limited, but is, for example, 100 nm.

[0070] 15D, in the fourth step, the SiO2 film 17 is planarized by CMP or the like to expose a portion of the surface of the silicon wafer 11. The remaining portion of the surface of the silicon wafer 11 is covered with the SiO2 film 17. The thickness of the remaining SiO2 film 17 is not particularly limited, but is, for example, 100 nm.

[0071] 15E, the exposed surface of the silicon wafer 11 is etched to form trenches between the SiO 2 films 17. The depth of the trenches is not particularly limited, but is, for example, 100 nm.

[0072] In the sixth step, as shown in FIG. 15F, a SiGe film 15A is epitaxially grown on the bottom surface of the trench in the silicon wafer 11, and a Ge film 15B is epitaxially grown on the SiGe film 15A. An alignment mark including the SiGe film 15A and the Ge film 15B is formed. The thickness of the SiGe film 15A is not particularly limited, but is, for example, 20 nm. The thickness of the Ge film 15B is not particularly limited, but is, for example, 80 nm.

[0073] Table 1 shows an example of the optical properties of a Ge film with a film thickness of 80 nm.

[0074] [Table 1]

[0075] As shown in Table 1, an 80-nm-thick Ge film has an absorptivity of 59.0% for infrared rays with a wavelength of 1,000 nm, allowing it to absorb the infrared rays used for imaging. Furthermore, an 80-nm-thick Ge film has a transmittance of 63.0% for laser beams with a wavelength of 9,300 nm, allowing it to transmit the laser beams used to form the modified layer.

[0076] Next, a method for forming a SiGe film, which is an alignment mark, will be described. The method for forming a SiGe film is similar to the method for forming a Ge film shown in FIGS. 15A to 15F, except that in the sixth step, after epitaxially growing a 100 nm-thick SiGe film 15A, a Ge film 15B is not epitaxially grown. An alignment mark including only the SiGe film 15A is formed. This shortens the process compared to when the alignment mark includes both the SiGe film 15A and the Ge film 15B. The thickness of the SiGe film 15A is not limited to 100 nm.

[0077] Figure 16 shows an example of the optical characteristics of a 100 nm thick SiGe film. In Figure 16, the solid line shows the optical characteristics of the SiGe film, and the dashed line shows the optical characteristics of bare silicon. A 100 nm thick SiGe film has a transmittance of approximately 48% for a laser beam with a wavelength of 9300 nm, allowing it to transmit the laser beam used to form the modified layer.

[0078] Next, a method for forming a metal silicide film, which is an alignment mark, will be described with reference to Figures 17A to 17G. The method includes steps 1 to 7. Steps 1 to 4 shown in Figures 17A to 17D are the same as steps 1 to 4 shown in Figures 15A to 15D, and therefore will not be described.

[0079] 17E, a Ni film 18 is formed on the surface of the silicon wafer 11. The Ni film 18 covers not only the exposed surface of the silicon wafer 11 but also the surface of the SiO film 17. The thickness of the Ni film 18 is not particularly limited, but is, for example, 20 nm.

[0080] 17F, the silicon wafer 11 is heated to react with the Ni film 18, thereby forming a NiSi2 film 15C. The heating temperature of the silicon wafer 11 is not particularly limited, but is, for example, 500°C.

[0081] In the seventh step, as shown in FIG. 17G, the Ni film 18 is removed using SPM or the like to expose the NiSi2 film 15C. SPM is an aqueous solution containing sulfuric acid and hydrogen peroxide. The mixture ratio is, for example, 1:1:5 by mass (H2SO4:H2O2:H2O=1:1:5). The time for etching the Ni film 18 with SPM is, for example, 15 minutes.

[0082] An alignment mark including a NiSi2 film 15C is formed. Note that the metal silicide is not limited to NiSi2, and may be, for example, TiSi2 or CoSi. The film thickness of NiSi2 is, for example, 20 nm to 40 nm. The film thickness of TiSi2 is, for example, 50 nm to 80 nm. The film thickness of CoSi is, for example, 30 nm to 50 nm.

[0083] Figure 18 shows an example of the absorptance of a TiSi2 film with a thickness of 210 nm. As shown in Figure 18, a TiSi2 film with a thickness of 210 nm has an absorptance of approximately 90% for infrared rays with wavelengths of 1000 nm to 2000 nm, and can absorb the infrared rays used for imaging. In addition, a TiSi2 film with a thickness of 210 nm has an absorptance of approximately 15% for laser beams with a wavelength of 9300 nm, and can transmit the laser beams used to form the modified layer.

[0084] Generally, the thinner the film, the lower the absorption rate and the higher the transmittance. Therefore, a TiSi2 film with a thickness of 50 nm to 80 nm has an absorption rate of less than about 15% for a laser beam with a wavelength of 9300 nm, and can transmit the laser beam used to form the modified layer.

[0085] Next, a method for forming an AlN film, which is an alignment mark, will be described with reference to Figures 19A to 19G. The method includes steps 1 to 7. Steps 1 to 5 shown in Figures 19A to 19E are the same as steps 1 to 5 shown in Figures 15A to 15E, and therefore will not be described.

[0086] 19F, in a sixth step, an AlN film 15D is formed on the surface of the silicon wafer 11, and the trenches are filled with the AlN film 15D. The AlN film 15D is formed by an ALD (Atomic Layer Deopsiton) method using, for example, TMA (trimethylsilane).

[0087] Specifically, an AlN film is formed by repeatedly supplying a plasma-converted mixed gas (a mixed gas containing Ar gas, H2 gas, and N2 gas), Ar gas, TMA gas, and Ar gas in this order. The volume ratio of the mixed gas is, for example, 1:6:3 (Ar:H2:N2=1:6:3). NH groups are formed on the surface of the silicon wafer 11 by supplying the plasma-converted mixed gas. The NH groups react with the TMA gas to form an AlN film. The AlN film formed by this method exhibits a blue color, and is hereinafter also referred to as a blue AlN film. The blue AlN film contains impurities and exhibits a blue color. The thickness of the blue AlN film is not particularly limited, but is, for example, 100 nm.

[0088] In the seventh step, as shown in FIG. 19G, the AlN film 15D is planarized by CMP or the like to expose a portion of the surface of the silicon wafer 11. The remaining portion of the surface of the silicon wafer 11 is covered with the AlN film 15D. The thickness of the remaining AlN film 15D is not particularly limited, but is, for example, 100 nm. An alignment mark including the AlN film 15D is formed.

[0089] Figure 20 shows an example of the transmittance of a blue AlN film with a thickness of 100 nm. A blue AlN film with a thickness of 100 nm has a transmittance of approximately 60% for infrared rays with a wavelength of 1000 nm, and can absorb the infrared rays used for imaging. Compared to regular AlN films, the blue AlN film has a lower transmittance for infrared rays with a wavelength of 1000 nm, making it suitable for use as an alignment mark.

[0090] Next, with reference to Figure 21 etc., a substrate processing apparatus 100 that performs S61 and S62 in Figure 3 will be described. In Figure 21, the X-axis, Y-axis, and Z-axis directions are perpendicular to one another, the X-axis and Y-axis directions are horizontal, and the Z-axis direction is vertical. The substrate processing apparatus 100 has a carry-in / out section 101, a transport section 110, a laser processing section 120, a dividing section 130, and a control section 140.

[0091] The loading / unloading section 101 has a loading section 102 on which a cassette C is placed. The cassette C accommodates a plurality of laminated substrates 8, such as shown in FIG. 10 , spaced apart in the vertical direction. The laminated substrate 8 includes a plurality of chips 2A and 2B, a first substrate 1, and a second substrate 5. As shown in FIG. 12 , the laminated substrate 8 is divided into a first divided body 81 and a second divided body 82 at a dividing plane D. The first divided body 81 and the second divided body 82 are then separately accommodated in the cassette C. The first divided body 81 includes a silicon wafer 11 and can be reused as a new first substrate 1 after being unloaded outside the substrate processing apparatus 100. To reuse the silicon wafer 11 as a first substrate 1, an absorption layer 12 or the like may be re-formed on the surface of the silicon wafer 11. On the other hand, the second divided body 82 includes the chips 2A and 2B, and is transported to the outside of the substrate processing apparatus 100, and then subjected to S63 in Fig. 3, S7 in Fig. 1, etc. Note that the number of mounting portions 102 and the number of cassettes C are not limited to those shown in Fig. 21.

[0092] The transport unit 110 is disposed next to the loading / unloading unit 101, the laser processing unit 120, and the dividing unit 130, and transports the laminated substrate 8 and the like to these units. The transport unit 110 has a holding mechanism that holds the laminated substrate 8 and the like. The holding mechanism is capable of moving in the horizontal direction (both in the X-axis direction and the Y-axis direction) and the vertical direction, and of rotating about the vertical axis.

[0093] As shown in FIG. 11 , the laser processing unit 120 uses a laser beam LB2 to form multiple modified layers M on a dividing surface D along which the first substrate 1 is to be divided in the thickness direction. The modified layers M are formed in dots, for example, at or above the focusing point. The laser processing unit 120 includes, for example, a stage 121 that holds the first substrate 1, and an optical system 122 that irradiates the laser beam LB2 onto the first substrate 1 held by the stage 121. The stage 121 is, for example, an XYθ stage or an XYZθ stage. The optical system 122 includes, for example, a focusing lens. The focusing lens focuses the laser beam LB2 toward the first substrate 1. The optical system 122 may further include a galvanometer scanner.

[0094] As shown in FIG. 12 , the dividing unit 130 divides the first substrate 1 starting from the modified layer M. The dividing unit 130 includes, for example, an upper chuck 131 and a lower chuck 132. The upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5. However, the first substrate 1 and the second substrate 5 may be arranged upside down. Next, when the upper chuck 131 rises relative to the lower chuck 132, a crack CR spreads in a planar manner starting from the modified layer M, and the first substrate 1 is divided at the dividing plane D. In other words, the laminated substrate 8 is divided at the dividing plane D into a first divided body 81 and a second divided body 82. As the upper chuck 131 rises, it may be rotated about a vertical axis. The first substrate 1 can be twisted off at the dividing plane D.

[0095] 21, the control unit 140 is, for example, a computer, and includes a CPU (Central Processing Unit) 141 and a storage medium 142 such as a memory. The storage medium 142 stores programs for controlling various processes executed in the substrate processing apparatus 100. The control unit 140 controls the operation of the substrate processing apparatus 100 by causing the CPU 141 to execute the programs stored in the storage medium 142.

[0096] Although the embodiments of the method for manufacturing a chip-mounted substrate and the substrate processing apparatus according to the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These naturally fall within the technical scope of the present disclosure.

[0097] This application claims priority based on Patent Application No. 2021-013785 filed with the Japan Patent Office on January 29, 2021, and the entire contents of Patent Application No. 2021-013785 are incorporated herein by reference. [Explanation of symbols]

[0098] 1 First board 2A, 2B chips 5 Second board 6 Third board 7 Chip-attached substrate 8. Laminated substrate 15 Alignment marks 100 Substrate processing apparatus 110 Conveying section 120 Laser Processing Department 130 Split section LB2 laser beam D split plane M modified layer

Claims

1. Preparing a laminated substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips; Separating the plurality of chips bonded to the first and second substrates from the first substrate so as to bond the chips to one side of a third substrate including a device layer; and A method for manufacturing a substrate with a chip, wherein the first substrate separated from the chip includes an alignment mark used for aligning the first substrate and the chip when bonding them together or for measuring misalignment after bonding.

2. The separation of the plurality of chips from the first substrate is performed by: forming a plurality of modified layers by a laser beam on a dividing surface along which the first substrate is to be divided in a thickness direction; Dividing the first substrate at the plurality of modified layers; The method for manufacturing a substrate with chips according to claim 1 , comprising:

3. the first substrate includes a silicon wafer and an absorption layer between the silicon wafer and the chip that absorbs the laser beam; 3. The method for manufacturing a substrate with chips according to claim 2, wherein the laser beam is transmitted through the silicon wafer to form the modified layer in the absorption layer.

4. The method for manufacturing a substrate with chips according to claim 3 , wherein the alignment mark is formed between the silicon wafer and the absorption layer.

5. 5. The method for manufacturing a substrate with chips according to claim 4, wherein the laser beam is transmitted through the silicon wafer and the alignment mark to form the modified layer in the absorption layer.

6. 6. The method for manufacturing a chip-attached substrate according to claim 2, wherein the alignment mark transmits the laser beam and absorbs infrared light having a wavelength different from that of the laser beam.

7. The method for manufacturing a substrate with chips according to claim 6 , wherein the alignment mark includes a Ge film, a SiGe film, a metal silicide film, or a blue AlN film.

8. 8. The method for manufacturing a chip-attached substrate according to claim 6, wherein the wavelength of the laser beam is 8800 nm to 11000 nm.

9. 9. The method for manufacturing a chip-attached substrate according to claim 6, wherein the wavelength of the infrared light is 1000 nm to 2000 nm.

10. 10. The method for manufacturing a substrate with chips according to claim 1, further comprising bonding a chip different from the chip to the first substrate separated from the chip.

11. a transport unit configured to transport a laminated substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips; a laser processing unit that uses a laser beam to form a plurality of modified layers on a dividing surface along which the first substrate is to be divided in the thickness direction; a dividing unit that divides the first substrate at the plurality of modified layers; Equipped with the first substrate includes an alignment mark used for alignment when bonding the first substrate and the chip or for measuring misalignment after bonding; The laser processing unit forms a plurality of the modified layers on the parting surface between the alignment mark and the chip.

12. the first substrate includes a silicon wafer and an absorption layer between the silicon wafer and the chip that absorbs the laser beam; The substrate processing apparatus according to claim 11 , wherein the laser beam is transmitted through the silicon wafer to form the modified layer in the absorption layer.

13. the alignment mark is formed between the silicon wafer and the absorption layer; The substrate processing apparatus according to claim 12 , wherein the laser beam is transmitted through the silicon wafer and the alignment mark to form the modified layer in the absorption layer.

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