Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a technology that can stabilize the breakdown voltage characteristics and switching characteristics.SOLUTION: A semiconductor device includes a semiconductor substrate, a first electrode, and a second electrode. The semiconductor substrate includes a drift layer, a semiconductor layer, a first buffer layer, and a second buffer layer. When a maximum value of an oxygen concentration of the semiconductor substrate calculated using a conversion factor of Old ASTM is maximum[Oi] and an impurity concentration of a first conductive type of the drift layer is Cdrift, maximum[Oi]=9.40×1016×ln(Cdrift)-2.27×1018 is satisfied.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A broad-profile layer with a maximum impurity concentration near the center of the drift layer of a power diode or near the collector of an IGBT (Insulated Gate Bipolar Transistor) has been proposed (see, for example, Patent Document 1). This configuration allows the breakdown voltage, which is a basic performance of a semiconductor device, and the electric field strength on the backside (cathode or collector) during turn-off operation to be controlled even if the resistivity of the semiconductor wafer, i.e., the concentration of the drift layer, varies. This allows carriers to remain on the backside, suppressing oscillation during turn-off operation and improving controllability during dynamic operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-99643 Summary of the Invention [Problem to be solved by the invention]

[0004] During the manufacturing process, heat treatment in an oxygen-containing atmosphere or heat treatment after forming a thermal oxide film diffuses oxygen into the semiconductor wafer, forming a profile in which the oxygen concentration decreases in the depth direction of the semiconductor wafer. On the other hand, the hydrogen-induced donor layer, such as the proton donor layer provided in Patent Document 1, is easily affected by oxygen in the semiconductor wafer.

[0005] As a result, the impurity profile of the donor layer changes unstably in the depth direction due to the profile in which the oxygen concentration decreases in the depth direction, and the impurity concentration of the donor layer increases due to the thermal donor phenomenon caused by oxygen. As a result, the donor layer cannot be formed as designed, and there are problems in that the breakdown voltage characteristics and switching characteristics become unstable.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can stabilize the withstand voltage characteristics and switching characteristics. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a first electrode and a second electrode provided on the first main surface and the second main surface, respectively. The semiconductor substrate includes: a drift layer of a first conductivity type provided between the first main surface and the second main surface; a semiconductor layer connected to the second electrode and including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first buffer layer of the first conductivity type provided between the semiconductor layer and the drift layer; and a second buffer layer of the first conductivity type provided between the first buffer layer and the drift layer, the second buffer layer having a first conductivity type impurity concentration lower than that of the first buffer layer and higher than that of the drift layer. The semiconductor device according to the present disclosure includes a semiconductor substrate having a first electrode and a second electrode provided on the first main surface and the second main surface, the semiconductor substrate including a drift layer of a first conductivity type provided between the first electrode and the drift layer, the first buffer layer of the first conductivity type provided between the first buffer layer and the drift layer, the second buffer layer of the first conductivity type having a first conductivity type impurity concentration lower than that of the first buffer layer and higher than that of the drift layer. i ], and the first conductivity type impurity concentration of the drift layer is C drift Then, maximum[O i ]=9.40×10 16 ×ln(C drift )-2.27×10 18 is satisfied. [Effects of the Invention]

[0008] According to the present disclosure, the maximum value of the oxygen concentration in a semiconductor substrate calculated using the Old ASTM conversion factor is expressed as maximum [O i], and the first conductivity type impurity concentration of the drift layer is C drift Then, maximum[O i ]=9.40×10 16 ×ln(C drift )-2.27×10 18 According to this configuration, it is possible to stabilize the breakdown voltage characteristics and switching characteristics. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing the configuration of an IGBT and a diode according to a first embodiment. [Figure 3] FIG. 10 is a graph showing the relationship between the oxygen concentration [Oi] in the semiconductor substrate and the impurity concentration Cdrift in the n-type drift layer. [Figure 4] 3 is a diagram showing the measurement results of the impurity profile along line BB' in FIG. 2 according to the first embodiment. FIG. [Figure 5] FIG. 10 is a diagram showing the relationship between the static breakdown voltage (BVces) of an IGBT having an n-type second buffer layer of the profile (new structure 1) according to the first embodiment and the oxygen concentration ([Oi]) in an MCZ wafer. [Figure 6] FIG. 10 is a graph showing the relationship between the time-zero dielectric breakdown characteristics of a gate oxide film and the oxygen concentration ([Oi]) in an MCZ wafer. [Figure 7] FIG. 2 is a diagram showing the output characteristics of an IGBT. [Figure 8] FIG. 1 is a diagram showing the operating temperature dependence of the on-voltage (VCE(sat)) of an IGBT. [Figure 9] FIG. 1 is a diagram showing the operating temperature dependence of the breakdown voltage (BVCES) of an IGBT. [Figure 10] FIG. 1 is a diagram showing the relationship between the maximum cut-off energy (ESC) and the on-voltage (VCE(sat)) when the IGBT is in a short-circuit state. [Figure 11]FIG. 10 is a diagram showing the trade-off characteristics between the switching loss (EREC) and the on-voltage (VF) of a diode. [Figure 12] FIG. 10 is a diagram showing the relationship between the maximum cutoff power density at the time of turning off a diode and the maximum switching speed (dj / dt) at the time of turning off. [Figure 13] 3 is a diagram showing the measurement results of the impurity profile along line BB' in FIG. 2 according to the second embodiment. FIG. [Figure 14] FIG. 10 is a diagram showing the device characteristics of the diode (b). [Figure 15] FIG. 10 is a diagram showing the relationship between the diode performance and the maximum peak value C2 in the n-type second buffer layer. [Figure 16] FIG. 10 is a diagram showing the relationship between diode performance and C2 / C1. [Figure 17] FIG. 10 is a diagram showing the measurement results of the impurity profile along line BB' in FIG. 2 according to the third embodiment. [Figure 18] FIG. 1 is a diagram showing the relationship between the maximum interruption energy (ESC) and the power supply voltage (VCC) when the IGBT is in a short-circuit state. [Figure 19] FIG. 10 is a diagram showing the results of a simulation of the internal state of an IGBT device. [Figure 20] 10 is a diagram showing the relationship between the maximum cutoff energy (ESC) of an IGBT in a short-circuit state and the depth X2 of the peak of the n-type impurity concentration in the n-type second buffer layer. FIG. [Figure 21] 10(a) to 10(f) are cross-sectional views showing steps of a manufacturing method according to a fourth embodiment. [Figure 22] 10(g) to 10(j) are cross-sectional views showing steps of a manufacturing method according to the fourth embodiment. [Figure 23] 10(k) to 10(m) are cross-sectional views showing steps of a manufacturing method according to the fourth embodiment. [Figure 24] 10 is a flowchart showing some steps of a manufacturing method according to a fourth embodiment. [Figure 25] 10(a) to 10(c) are cross-sectional views showing steps of a manufacturing method according to a fifth embodiment. [Figure 26]10(d) to 10(f) are cross-sectional views showing steps of a manufacturing method according to the fifth embodiment. [Figure 27] 10(g) to 10(i) are cross-sectional views showing steps of a manufacturing method according to the fifth embodiment. [Figure 28] 10 is a flowchart showing some steps of a manufacturing method according to a fifth embodiment. [Figure 29] 10 is a flowchart showing some steps of a manufacturing method according to a fifth embodiment. [Figure 30] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 31] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 32] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 33] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 34] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 35] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 36] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 37] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In the following description, specific positions and directions, such as "top," "bottom," "left," "right," "front," or "back," may not necessarily correspond to the positions and directions in actual implementation. A higher concentration in one portion may mean, for example, that the average concentration in one portion is higher than the average concentration in another portion. Conversely, a lower concentration in one portion may mean, for example, that the average concentration in one portion is lower than the average concentration in another portion. In the following description, the first conductivity type is n-type and the second conductivity type is p-type; however, the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0011] <First Embodiment> Fig. 1 is a plan view showing the configuration of a power semiconductor chip, which is an example of a semiconductor device according to the present embodiment 1. The semiconductor device of Fig. 1 has an active region 1, an interface region 2, and a termination region 3 defined therein.

[0012] The active region 1 is a region that ensures the basic performance of the semiconductor device, and is provided with a semiconductor element that is either a first semiconductor device, such as an IGBT, or a second semiconductor device, such as a diode. The interface region 2 is a region between the active region 1 and the termination region 3, and is a region that supports the breakdown voltage tolerance during dynamic operation of the semiconductor device and supports the inherent performance of the semiconductor element provided in the active region 1. The termination region 3 is a region that ensures the stability and reliability of breakdown voltage retention and breakdown voltage characteristics in a static state, suppresses breakdown voltage tolerance defects during dynamic operation, and supports the basic performance of the semiconductor device.

[0013] 1 shows a case where an IGBT is provided in the active region 1, and the surface gate wiring portion 4 and the gate pad portion 38 are provided in the active region 1. If a diode is provided in the active region 1, the surface gate wiring portion 4 and the gate pad portion 38 do not have to be provided in the active region 1.

[0014] Fig. 2 is a cross-sectional view showing the configuration of an IGBT and a diode according to the first embodiment. Fig. 2 shows one type of IGBT and two types of diodes (diode (a) and diode (b)). The diode, which is the second semiconductor device, may be diode (a), which is a diode with a pin structure, or diode (b), which is a diode with a RFC (Relaxed Field of Cathode) structure. The diode, which is the second semiconductor device, may be called a power diode or FWD (Freewheeling diode).

[0015] First, among the components of one type of IGBT, those components that are common to the two types of diodes will be mainly described. The IGBT includes a semiconductor substrate 51, a first electrode 5, and a second electrode .

[0016] The semiconductor substrate 51 has a front surface 51a, which is a first main surface, and a back surface 51b, which is a second main surface opposite to the first main surface. The first electrode 5 is provided on the front surface 51a and is comprised of, for example, aluminum wiring. The second electrode 21 is provided on the back surface 51b and is comprised of, for example, a metal film. Note that the final device thickness (t device ) is, for example, 40 to 700 μm.

[0017] The semiconductor substrate 51 according to the first embodiment is a silicon (Si) semiconductor wafer (hereinafter sometimes referred to as an "MCZ wafer") manufactured by the MCZ (Magnetic field applied Czochralski) method. Oxygen and carbon introduced as impurities during the manufacture of the MCZ wafer are present at interstitial sites and substitutional sites in the Si single crystal, respectively. Therefore, in the following description, the first letters of interstitial and substitutional are added to represent the oxygen concentration and nitrogen concentration of the semiconductor substrate 51, respectively, as [O i ] and [C s Generally, the [O i ] is the [O i ] is two to three orders of magnitude higher than that of MCZ wafers and FZ wafers, s ] are equivalent.

[0018] The semiconductor substrate 51 is a drift layer of the first conductivity type, n - The semiconductor device includes an n-type drift layer 15, an n-type first buffer layer 16 which is a first buffer layer of a first conductivity type, an n-type second buffer layer 17 which is a second buffer layer of the first conductivity type, and a semiconductor layer described below. In this specification, the impurity concentration refers to the concentration of an element other than Si, and the element will be described appropriately. In the first embodiment, the element forming the diffusion layer is a dopant.

[0019] n - The type drift layer 15 corresponds to a portion of the MCZ wafer, which is the semiconductor substrate 51, into which no impurities (ions, dopants) have been substantially newly implanted. - The n-type impurity in the n-type drift layer 15 is, for example, phosphorus (P) or antimony (Sb), and - Impurity concentration C of the type drift layer 15 drift For example, 1.0×10 12 ~5.0×10 14 atoms / cm 3 is.

[0020] In addition, when manufacturing large-diameter semiconductor wafers, the impurity concentration in the crystal axis direction of the Si single crystal ingot (i.e., n - Impurity concentration C of the type drift layer 15 drift However, the antimony evaporation rate (1.3 × 10 -1 cm / sec) is the evaporation rate of phosphorus (1.6 × 10 -4 Therefore, if antimony is used as the n-type impurity in semiconductor wafers and a silicon single crystal is produced using evaporation control technology that takes advantage of this characteristic, the impurity concentration C drift This can suppress variations in the

[0021] n - The drift layer 15 is provided between the front surface 51a and the back surface 51b, for example, from the main junction 12 on the front surface 51a side to the junction 22 on the back surface 51b side. When a voltage is held in the semiconductor device, a reverse bias is applied to the main junction 12. When a reverse bias is applied to the main junction 12, a depletion layer extends from the main junction 12 to the back surface 51b, and the electric field strength is maximized at the main junction 12. The junction 22 is the portion where the depletion layer extending from the main junction 12 to the back surface 51b comes into contact when a voltage is held, and is the portion where the electric field strength is second highest after the main junction when a voltage is held.

[0022] The semiconductor layer is connected to the second electrode 21 and includes at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group of A, B, C, ..., and Z.

[0023] The semiconductor layers of the IGBT include a p-type collector layer 18, which is a second semiconductor layer of a second conductivity type. The p-type collector layer 18 contains p-type impurities such as boron (B), and the peak value of the impurity concentration is, for example, 1.0×10 16 ~1.0×10 20 atoms / cm3 and the depth from the rear surface 51b is, for example, 0.3 to 0.8 μm.

[0024] The semiconductor layer of the diode (a) is a first semiconductor layer of a first conductivity type, n + The cathode layer 19 includes + The n-type cathode layer 19 contains n-type impurities such as arsenic (As) or phosphorus (P), and the peak value of the impurity concentration is, for example, 1.0×10 17 ~1.0×10 19 atoms / cm 3 and the depth from the rear surface 51b is, for example, 0.3 to 0.5 μm.

[0025] The semiconductor layer of the diode (b) is a first semiconductor layer of a first conductivity type, n + The diode (b) includes an n-type cathode layer 19 and a p-type cathode layer 20, which is a second semiconductor layer of the second conductivity type. + The n-type cathode layer 19 of the diode (a) + The p-type cathode layer 20 has a p-type impurity of, for example, boron (B), and a peak value of the impurity concentration of, for example, 1.0×10 16 ~1.0×10 18 atoms / cm 3 and the depth from the rear surface 51b is, for example, 0.3 to 0.5 μm.

[0026] The two buffer layers (n-type first buffer layer 16 and n-type second buffer layer 17) are provided to stabilize the voltage holding capability in the off state, reduce power consumption in the off state, and improve controllability and breakdown resistance during dynamic operation. For example, the n-type first buffer layer 16 is provided to stabilize the voltage holding capability in the off state.

[0027] The n-type first buffer layer 16 is connected to the semiconductor layer connected to the second electrode 21 and - For example, the n-type first buffer layer 16 of the IGBT is disposed between the p-type collector layer 18 and the n-type drift layer 15. - The n-type first buffer layer 16 of the diode (a) is provided between the n-type drift layer 15 and the n-type first buffer layer 16.+ type cathode layer 19 and n - The n-type first buffer layer 16 of the diode (b) is provided between the n-type drift layer 15 and the n-type first buffer layer 16. + the p-type cathode layer 19 and the p-type cathode layer 20, respectively, and the n-type cathode layer 21. - It is provided between the semiconductor layer 10 and the drift layer 15 .

[0028] The n-type first buffer layer 16 contains n-type impurities such as arsenic (As) or phosphorus (P), and the maximum peak value (C1) of the impurity concentration is, for example, 1.0×10 15 ~5.0×10 16 atoms / cm 3 and the depth (X1) from the rear surface 51b is, for example, 1.0 to 30 μm.

[0029] The n-type second buffer layer 17 is a layer having a thickness of 100 nm and a thickness of 100 nm. - The n-type second buffer layer 17 has an n-type impurity concentration lower than that of the n-type first buffer layer 16. - The n-type impurity concentration is higher than that of n-type drift layer 15.

[0030] The n-type second buffer layer 17 contains n-type impurities such as protons (H + ), the maximum peak value (C2) of the impurity concentration is, for example, less than the above C1, preferably 0.01×C1 or less, and the depth (X2) from the rear surface 51b is, for example, 20 to 30 μm deeper than the depth (X1).

[0031] As will be explained later, n - For the n-type drift layer 15, the n-type first buffer layer 16, and the n-type second buffer layer 17, τ2<τ1≦τ t The following relationship may be satisfied: where τ2 is the carrier lifetime of the n-type second buffer layer 17, and τ1 is the carrier lifetime of the n-type first buffer layer 16. t has no effect on the on-voltage of the IGBT (i.e., the on-voltage of the gate electrode), - 1 is the carrier lifetime of the type drift layer 15.

[0032] Next, other components of the IGBT will be described. The semiconductor substrate 51 is an n-type emitter layer of the first conductivity type. + type emitter layer 7, and p + The semiconductor device further includes a p-type layer 8, a p-type base layer 9 which is a base layer of the second conductivity type, and an n-type layer 11.

[0033] The p-type base layer 9 is - The p-type base layer 9 is provided closer to the front surface 51a than the drift layer 15. The p-type impurity in the p-type base layer 9 is, for example, boron (B), and the peak value of the impurity concentration is, for example, 1.0×10 16 ~1.0×10 18 atoms / cm 3 The depth from the front surface 51a is n + It is deeper than the n-type emitter layer 7 and shallower than the n-type layer 11 .

[0034] The n-type layer 11 is connected to the p-type base layer 9 and - The n-type layer 11 is provided between the n-type drift layer 15 and the n-type impurity, for example, arsenic (As) or phosphorus (P), and the peak value of the impurity concentration is, for example, 1.0×10 15 ~1.0×10 17 atoms / cm 3 The depth from the front surface 51a is deeper than the p-type base layer 9 by, for example, 0.5 to 1.0 μm.

[0035] n + The n-type emitter layer 7 is provided closer to the front surface 51a than the p-type base layer 9. + The n-type emitter layer 7 contains, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the peak value of the impurity concentration is, for example, 1.0×10 18 ~1.0×10 21 atoms / cm 3 and the depth from the front surface 51a is, for example, 0.2 to 1.0 μm.

[0036] p + The p-type layer 8 is provided closer to the front surface 51a than the p-type base layer 9. +The mold layer 8 contains p-type impurities such as boron (B), and the surface impurity concentration is, for example, 1.0×10 18 ~1.0×10 21 atoms / cm 3 The depth from the front surface 51a is n + The depth is equal to or greater than that of the type emitter layer 7 .

[0037] The semiconductor substrate 51 of the IGBT includes a p-type base layer 9, an n + A trench 24 is provided through the n-type emitter layer 7 and the n-type layer 11. The depth D of the trench 24 from the front surface 51a is trench is, for example, 2.0 μm or more and is deeper than the n-type layer 11.

[0038] A gate electrode 14, which is a trench electrode, is provided on the inner wall of the trench 24 via a gate oxide film 13. The gate electrode 14 is electrically connected to the surface gate wiring portion 4 of FIG. 1 and is insulated from the first electrode 5 at the emitter potential by an interlayer film 6 including an oxide film or the like. As will be described later, the trench electrode provided in the trench 24 may further include a dummy electrode connected to the first electrode 5 at the emitter potential in addition to the gate electrode 14. When the trench electrode includes a dummy electrode, the saturation current density of the IGBT is suppressed and the capacitance characteristics are controlled, which is expected to suppress oscillation under no-load short-circuit conditions and improve short-circuit resistance. In addition, a reduction in on-state voltage can be expected due to an increase in the carrier concentration on the emitter side.

[0039] Next, other components of the diode (a) and the diode (b) will be described. As mentioned above, the difference between the diode (a) and the diode (b) is whether or not the p-type cathode layer 20 is present.

[0040] The semiconductor substrate 51 further includes a p-type anode layer 10, which is an anode layer of a second conductivity type. - The p-type anode layer 10 is provided closer to the front surface 51a than the p-type drift layer 15. The p-type impurity in the p-type anode layer 10 is, for example, boron (B), and the surface impurity concentration is, for example, 1.0×10 16 atoms / cm 3or more, and the peak value of the impurity concentration is, for example, 2.0 × 10 16 ~1.0×10 18 atoms / cm 3 The depth of the p-type anode layer 10 from the front surface 51a is, for example, 2.0 to 10.0 μm.

[0041] As will be described later, the p + Similar to the p-type layer 8, the p-type anode layer 10 is provided closer to the front surface 51a than the p-type anode layer 10, and is a second conductivity type impurity diffusion layer having a higher p-type impurity concentration than the p-type anode layer 10. + A mold layer 8 may be provided.

[0042] n - In addition to the n-type drift layer 15, the n-type first buffer layer 16, and the n-type second buffer layer 17, a p-type collector layer 18, an n-type + The p-type cathode layer 19 and the p-type cathode layer 20 form a vertical structure. The vertical structure is an area that guarantees stability and reliability in total loss performance (loss in on-state on-voltage plus loss in turn-on and turn-off states), voltage retention and breakdown characteristics in a static state, and leakage characteristics (off loss) when voltage is maintained at high temperatures. The vertical structure also guarantees controllability and breakdown resistance during dynamic operation, and supports the basic performance of the semiconductor device.

[0043] When oxygen is introduced into the semiconductor wafer during the manufacturing process of the Si semiconductor wafer that constitutes the IGBT and diode, the oxygen becomes a donor at a specific annealing temperature due to the thermal donor phenomenon, and n - n-type impurity concentration C of n-type drift layer 15 drift In particular, the increase is more pronounced for MCZ wafers than for semiconductor wafers produced by the FZ method.

[0044] In the first embodiment, in order to solve the problem caused by this, the maximum value of the oxygen concentration of the semiconductor substrate 51 is set to maximum[O i ], the following formula (1) is satisfied.

[0045] maximum[O i ]=9.40×10 16 ×ln(C drift )-2.27×10 18 ···(1)

[0046] In addition, in formula (1), [O i The impurity concentration C is calculated using the value detected by detecting oxygen in silicon using FTIR (Fourier Transform Infrared Spectroscopy) and the conversion factor used in ASTM (American Society for Testing and Materials) F121-79 (Old ASTM). drift For example, n - It is a representative value (for example, an average value, a median value, etc.) of the n-type impurity concentration in the n-type drift layer 15. i ] and impurity concentration C drift The units are the same as those of the -3 ]), where ln is the natural logarithm.

[0047] FIG. 3 shows the oxygen concentration [O i ] and n - Impurity concentration C of the type drift layer 15 drift FIG.

[0048] According to the configuration according to the first embodiment that satisfies this relationship, n - Impurity concentration C of the type drift layer 15 drift Even if the maximum [O i ] is formed by thermal donor formation due to oxygen in the MCZ wafer. - Impurity concentration C of the type drift layer 15drift When [O i ] can be rephrased as the limit value.

[0049] [O i ] is calculated using the Old ASTM conversion factor as described above. i When [O] is calculated using the conversion factor of ASTM F121-83 (New ASTM), the following formula (2) should be satisfied. i When [Oxygen Concentration] is calculated using the conversion coefficient of the International Oxygen Coefficient 1988 (IOC 88), the following formula (3) should be satisfied.

[0050] maximum[O i ]=4.78×10 16 ×ln(C drift )-1.16×10 18 ···(2)

[0051] maximum[O i ]=6.13×10 16 ×ln(C drift )-1.48×10 18 ···(3)

[0052] Fig. 4 is a diagram showing the measurement results of the impurity profile according to the first embodiment in the depth direction along B-B' in Fig. 2. Note that Fig. 4 shows the results measured by the SRA (Spreading Resistance Analysis) method, and the impurity concentration in p-type collector layer 18 is not detected with the measurement accuracy of SRA.

[0053] In Figure 4, new structure 1, new structure 2, and new structure with height [O i ] and the con. structure, impurity profiles are shown.

[0054] New structure 1 and new structure 2 are impurity profiles of a semiconductor device formed from a semiconductor substrate 51 that satisfies formula (1).

[0055] In the new structure 1, the n-type second buffer layer 17 includes a 2-1 buffer layer to a 2-n buffer layer. The 2-1 buffer layer to the 2-n buffer layer are formed by the n-type first buffer layer 16 to the n-type - The n-type impurity concentration peaks are C 2,1 ~C 2,n When the maximum peak value of the n-type impurity concentration in the n-type second buffer layer 17 in the new structure 1 is C2, C2 is C 2,1 The new structure 1 will be explained in the first and second embodiments.

[0056] In the new structure 2, the n-type second buffer layer 17 has a peak value of n-type impurity concentration of C 2,0 When the maximum peak value of the n-type impurity concentration in the n-type second buffer layer 17 in the new structure 2 is C2, C2 is C 2,0 The new structure 2 will be explained in the third embodiment.

[0057] new structure with height[O i ] is the same impurity profile of the semiconductor device as new structure 1 except that it does not satisfy formula (1). i Even in an MCZ wafer in which the impurity profile of [O i ] is the maximum [O i ], the maximum [O i ] or less, the impurity profile of the n-type second buffer layer 17 becomes broader in the depth direction, and the impurity concentration of the n-type second buffer layer 17 becomes higher.

[0058] As a result, it is expected that the impurity profile of the new structure 1 in FIG. 4 cannot be stably realized in the n-type second buffer layer 17. i Even in an MCZ wafer in which the impurity profile of [O i ] is the maximum[O i ] must be controlled below.

[0059] In contrast to this, in the first embodiment, the n-type buffer layer includes the n-type first buffer layer 16 and the n-type second buffer layer 17, and the semiconductor substrate 51 is made of [O i ] is the maximum [O i ] includes an MCZ wafer controlled as follows. This makes it possible to stabilize the impurity profile of the n-type second buffer layer 17.

[0060] The n-type second buffer layer 17 is formed by hydrogen and protons (H + ) interstitial Si pairs (I Si The hydrogen-induced donor (HDs) layer contains donor complex defects formed by the reaction of point defects originating from the hydrogen-induced donors (HDs). Point defects include, for example, G centers (I Si3 Cluster, 1.019 eV(*), E V +0.1 eV) and X center (I Si4 Cluster, 1.040 eV(*), E V +0.32 eV). Energy values marked with (*) are photon energies calculated from PL spectra analyzed using the photoluminescence (PL) method. The PL method is an analytical technique in which light is irradiated onto a semiconductor and the light emitted when electron-hole pairs recombine via defect levels is observed.

[0061] The con. structure is an impurity profile of a conventional semiconductor device, and the junction (X j,n1 ) near n - Impurity concentration C of the type drift layer 15 drift A crystal defect layer 23 having a lower concentration than that of the first crystal defect layer 21 is provided.

[0062] As defects in this crystal defect layer 23, point defects (G center and X center) originating from interstitial Si pairs exist, similar to the HDs layer of the n-type second buffer layer 17. However, protons (H + In the con. structure where [O i The higher the [value], the more oxygen-induced complex defects in Si (e.g., VO (Vacancy-Oxygen pair), CiOi (interstitial Carbon-interstitial Oxygen pair), V2 (di-Vacancy)) are formed. + is trapped and VOH, C i O i H n , becomes V2H2, and H + The diffusion of the silicon dioxide toward the rear surface 51b is inhibited by oxygen.

[0063] Therefore, in the con. structure of Fig. 4, [O i ] prevents hydrogen from diffusing toward the rear surface 51b. - Impurity concentration C of the type drift layer 15 drift On the other hand, in the new structure 1 of the first and second embodiments, protons (H + ) is introduced, the crystal defect layer 23 is not formed. j,n1 ) near the proton (H + ) is introduced, the crystal defect layer 23 is not formed.

[0064] FIG. 5 shows an IGBT (3.3 kV class, C drift :2.0×10 13 cm -3 ) for static withstand voltage (BV ces ) and the oxygen concentration in the MCZ wafer ([O i ]) is shown in FIG. i ] is 6.0 × 10 17 cm -3 If it is higher, the static breakdown voltage (BV ces ) decreases by 6.0×10 17 cm -3 Higher [O i ] is the maximum[O i ]. Therefore, when the n-type second buffer layer 17 has the impurity profile of the new structure 1, the maximum [O i ] is 6.0 × 10 17 cm -3 It can be seen that the lower IGBT has sufficient off-state voltage (static breakdown voltage) retention capability even at a low temperature of 218K.

[0065] FIG. 6 shows an IGBT (3.3 kV class, C drift :2.0×10 13 cm -3 , temperature 298k), the time-zero dielectric breakdown characteristics of the gate oxide film 13 and the oxygen concentration in the MCZ wafer ([O i ]) in FIG. i ] is the maximum[O i ] in Figure 6 corresponds to higher [O i ] is the maximum[O i ] is higher than lower[O i ], the probability of dielectric breakdown occurring (the probability corresponding to the cumulative frequency) is low even at relatively high voltages.

[0066] FIG. 7 shows an IGBT (6.5 kV class, C) in which the n-type second buffer layer 17 has an impurity profile of the new structure 1 or the con. structure. drift :5.0×10 12 cm -3 7 shows the output characteristics of the IGBT. In the impurity profile of the con. structure, a crystal defect layer 23 exists, and the hole injection efficiency from the back surface 51b decreases when the IGBT is initially turned on. C V CE As a result, a snap-back characteristic occurs that does not increase monotonically with respect to the impurity concentration. As a result, normal IGBT on-state operation cannot be achieved. On the other hand, in the impurity profile of new structure 1, there is no crystal defect layer 23 that inhibits hole injection from the back surface 51b of the IGBT, and as shown in Figure 7, C V CE Since the voltage Vin increases monotonically with respect to the voltage Vout, a normal IGBT ON operation can be achieved.

[0067] FIG. 8 shows an IGBT (6.5 kV class, C) in which the n-type second buffer layer 17 has an impurity profile of the new structure 1 or the con. structure. drift :5.0×10 12 cm -3 ) for the on-state voltage (V CE 7. The impurity profile of the con. structure has a crystal defect layer 23, which causes the snap-back characteristic shown in FIG. 7. Therefore, as shown in FIG. 8, the V CE (sat) decreases up to a certain temperature and then increases from that temperature. On the other hand, in the impurity profile of new structure 1, as shown in Figure 8, V CE Since the temperature dependency (i.e., the rate of change) of (sat) is maintained positive, this is effective in terms of the operation of a power module in which many semiconductor devices are incorporated in parallel.

[0068] FIG. 9 shows an IGBT (6.5 kV class, C) in which the n-type second buffer layer 17 has an impurity profile of the new structure 1 or the con. structure. drift :5.0×10 12 cm -3 ) for withstand voltage (BV CES 9 is a diagram showing the operating temperature dependence of the impurity profile of the new structure 1. As shown in FIG. 9, the off-state breakdown voltage holding capability of the impurity profile of the new structure 1 is higher than the off-state breakdown voltage holding capability of the impurity profile of the con. structure. The reason for this is thought to be that in the impurity profile of the con. structure, the depletion layer extending from the main junction 12 on the front surface 51a side to the crystal defect layer 23 becomes a leakage current source when the semiconductor device holds a voltage, resulting in a decrease in the voltage holding capability.

[0069] FIG. 10 shows an IGBT (6.5 kV class, C) in which the n-type second buffer layer 17 has an impurity profile of the new structure 1 or the con. structure. drift :5.0×10 12 cm -3 ) for the maximum breaking energy (E SC ) and on-state voltage (V CE As shown in Figure 10, the maximum cutoff energy (E SC ) is the maximum cutoff energy (E SC) is higher than that of the conventional impurity profile. In the con. structure, the presence of the crystal defect layer 23 causes the carriers on the back surface 51b side of the IGBT to disappear in a short-circuit state. This behavior reduces the carrier concentration on the back surface 51b side of the IGBT in a short-circuit state, leading to an increase in electric field strength and an imbalance in the state inside the device. For this reason, it is believed that an IGBT with the con. structure impurity profile will have a reduced breaking capability in a short-circuit state. On the other hand, an IGBT with the new structure 1 impurity profile does not have the crystal defect layer 23, so it is believed that its breakdown resistance during dynamic operation will be improved.

[0070] FIG. 11 shows a diode (b) (6.5 kV class, C) in which the n-type second buffer layer 17 has an impurity profile of the new structure 1 or the con. structure. drift :5.0×10 12 cm -3 ), the switching loss (E REC ) and on-state voltage (V F ) is shown. The diode having the impurity profile of new structure 1 has an improved waveform during recovery during turn-off operation compared to the diode having the impurity profile of the con. structure. As a result, as shown in FIG. 11, the diode having the impurity profile of new structure 1 has a lower switching loss (E REC ) can be lowered. Therefore, in the diode with the impurity profile of new structure 1, E REC and V F The trade-off characteristics are improved.

[0071] FIG. 12 shows a diode (b) (6.5 kV class, C) in which the n-type second buffer layer 17 has an impurity profile of the new structure 1 or the con. structure. drift :5.0×10 12cm -3 12 is a graph showing the relationship between the maximum blocking power density at turn-off and the maximum switching speed (dj / dt) at turn-off for the diodes of the new structure 1. As shown in FIG. 12, a diode having the impurity profile of the new structure 1 can block a higher power density at the same switching speed (dj / dt) than a diode having the impurity profile of the con. structure.

[0072] <Summary of the First Embodiment> According to the semiconductor device (IGBT, diode (a) or diode (b)) of the first embodiment described above, the maximum value of the oxygen concentration in the semiconductor substrate 51 calculated using the Old ASTM conversion coefficient is maximum[O i ] and n - The impurity concentration of the drift layer is C drift Then, maximum[O i ]=9.40×10 16 ×ln(C drift )-2.27×10 18 This configuration, for example, can achieve a sufficient off-state withstand voltage holding capability while also achieving normal on-state operation and improved breakdown resistance during dynamic operation. In other words, it is possible to stabilize the withstand voltage characteristics and switching characteristics.

[0073] <Embodiment 2> The cross-sectional configuration of the semiconductor device according to the second embodiment is the same as the cross-sectional configuration of the semiconductor device according to the first embodiment (the cross-sectional configuration of FIG. 2). Fig. 13 is a diagram showing the measurement results of the impurity profile according to the second embodiment in the depth direction along B-B' in Fig. 2.

[0074] The semiconductor device according to the second embodiment has a maximum [O i] satisfies formula (1), and the n-type second buffer layer 17 has the impurity profile of new structure 1 in FIG. 4. Therefore, the n-type second buffer layer 17 includes a 2-1 buffer layer to a 2-n buffer layer (where n≧2). The 2-1 buffer layer to the 2-n buffer layer are formed by the n-type first buffer layer 16 to the n - The n-type impurity concentration peaks are C 2,1 ~C 2,n It has.

[0075] That is, the junction (X j,n1 ) to the n-type second buffer layer 17 and n - Junction with the drift layer 15 (X j,n2n ) in the direction toward the 2-1 buffer layer to the 2-n buffer layer. 2,n <··· <C 2,2 <C 2,1 is met.

[0076] In FIG. 13, the impurity profiles are shown not only for new structure 1 but also for new structure 1-(a) and new structure 1-(b) which are compared with new structure 1. In the impurity profile of new structure 1-(a), the relationship of the peak values is reversed in the impurity profile of new structure 1, and C 2,1 <C 2,2 <··· <C 2,n In the impurity profile of new structure 1-(b), the peak values are almost the same as those of new structure 1, and C 2,n ≒···≒C 2,2 ≒C 2,1In all three impurity profiles (new structure 1, new structure 1-(a), new structure 1-(b)), the total dose, which is the sum of the doses during ion implantation to form the 2-1 buffer layer to the 2-n buffer layer, is the same.

[0077] FIG. 14 is a diagram showing the device characteristics of diode (b) (1200V class) having one of the three impurity profiles in FIG. 13. The diode having the impurity profile of new structure 1 has a lower on-voltage (V F ) is low, and the leakage current (J R ) and a wide safe operating area (SOA) under dynamic conditions.

[0078] In a diode having the impurity profile of the new structure 1, the extension of the depletion layer from the main junction 12 to the n-type second buffer layer 17 during dynamic operation is gentle, so that a carrier plasma layer is likely to remain in the back surface 51b region. - This layer is formed by conductivity modulation that occurs in the portion of the type drift layer 15 into which electrons and holes are injected when the semiconductor device is on, and is a neutral layer with approximately the same electron and hole concentrations. The behavior of the remaining carrier plasma layer can be defined as an action that controls the interaction between the carrier plasma layer and the electric field intensity during dynamic operation of the semiconductor device (IGBT, diode (a), diode (b)).

[0079] Due to the above behavior, in the diode with the impurity profile of new structure 1, the V AK The maximum voltage in the waveform (V snap-off) can be made lower than the rated voltage (1200V). This makes it possible to suppress breakdown during dynamic operation and improve controllability.

[0080] In addition, due to the above behavior, in the diode with the impurity profile of new structure 1, CC ) and the maximum breaking current density (J A (break)) increases, allowing for expansion of SOA in dynamic conditions.

[0081] FIG. 15 is a diagram showing the relationship between the diode performance and the maximum peak value C2 in the n-type second buffer layer 17 of the diode (b) (1200V class) in which the n-type second buffer layer 17 has the impurity profile of new structure 1. In FIG. 15, the diode performance is measured by the breakdown voltage (BV RRM ) and dynamic SOA, and the maximum peak value C2 is the C 2,1 The Safe Operating Temperature on the vertical axis of Figure 15 is the lowest operating temperature at which the diode can be shut down in snappy mode.

[0082] The range of the physical quantity on the horizontal axis in FIG. 15 (i.e., the range of the maximum peak value C2 of the n-type second buffer layer 17) is the range in which the physical quantity on the vertical axis does not depend on the physical quantity on the horizontal axis (1.0×10 15 cm -3 Therefore, in the second embodiment, the diode is configured to satisfy the following formula (4), so that the dynamic SOA can be guaranteed while maintaining a sufficient off-state breakdown voltage holding capability of the diode.

[0083] C drift <C2≦1.0×10 15 cm -3 ···(4)

[0084] FIG. 16 shows the diode performance (breakdown voltage (BV)) of a diode (b) (6.5 kV class) in which the n-type second buffer layer 17 has the impurity profile of new structure 1. RRM 10 is a diagram showing the relationship between the maximum peak value C2 of the n-type impurity concentration in the n-type second buffer layer 17 and the maximum peak value C1 of the n-type impurity concentration in the n-type first buffer layer 16 (the safe operating temperature in the snappy mode) and C2 / C1.

[0085] The range of the physical quantity on the horizontal axis in Fig. 16 (i.e., the range of C2 / C1) is the range in which the physical quantity on the vertical axis does not depend on the physical quantity on the horizontal axis (1.0 × 10 -4 ~1.0×10 -1 1.0×10 15 cm -3 Therefore, in the second embodiment, the diode is configured to satisfy the following formula (5), so that the dynamic SOA can be guaranteed while maintaining a sufficient off-state breakdown voltage holding capability of the diode.

[0086] 1.0×10 -4 ≦C2 / C1≦1.0×10 -1 ···(5)

[0087] <Third Embodiment> The cross-sectional configuration of the semiconductor device according to the third embodiment is the same as the cross-sectional configuration (FIG. 2) of the semiconductor device according to the first embodiment. Fig. 17 is a diagram showing the measurement results of the impurity profile according to the third embodiment in the depth direction along B-B' in Fig. 2.

[0088] The semiconductor device according to the third embodiment has a maximum [O i ] satisfies formula (1), and the n-type second buffer layer 17 has the impurity profile of new structure 2 in Fig. 4. Therefore, the n-type second buffer layer 17 is a single layer having a single peak.

[0089] 17 illustrates impurity profiles not only for new structure 1 and new structure 2, but also for new structure 2-(a) and new structure 2-(b) which are compared with new structure 2. X1 is the depth of the peak of the n-type impurity concentration in the n-type first buffer layer 16 from the back surface 51b, and X2 is the depth of the peak of the n-type impurity concentration in the n-type second buffer layer 17 from the back surface 51b. In the impurity profile of new structure 2-(a), the peak depth X2 of the n-type second buffer layer 17 is deeper than in the impurity profile of new structure 2. In the impurity profile of new structure 2-(b), the peak depth X2 of the n-type second buffer layer 17 is deeper than in the impurity profile of new structure 2-(a).

[0090] FIG. 18 shows the maximum blocking energy (E SC ) and power supply voltage (V CC ) is a diagram showing the relationship between the short-circuit state (V CC 19 is a diagram showing the results of a simulation of the internal state (carrier concentration and electric field strength) of the device at a temperature of 2000V and 298K. The left end position of the horizontal axis in FIG. 19 corresponds to the position of the front surface 51a, and the left end position of the horizontal axis corresponds to the position of the back surface 51b.

[0091] As shown in FIG. 18, in the impurity profiles of new structure 2-(a) and new structure 2-(b), V CC In the region where is 1500 to 3500V, E SCAs shown by the thin dashed-dotted line in FIG. 19 , in the impurity profiles of new structure 2-(a) and new structure 2-(b), the electric field strength in the n-buffer layer on the back surface 51b of the IGBT increases to the same level as the electric field strength in the main junction 12 on the front surface 51a. Thus, in the impurity profiles of new structure 2-(a) and new structure 2-(b), the SOA in the short-circuit mode is thought to be narrowed because the inside of the device in the short-circuit state is unbalanced. Here, the state in which the inside of the device in the short-circuit state is unbalanced refers to a state in which the electric field strength in the main junction 12 on the front surface 51a, which will be described later, is higher than the electric field strength in the n-buffer layer on the back surface 51b.

[0092] On the other hand, as shown in FIG. 18, in the impurity profiles of new structure 1 and new structure 2, the power supply voltage (V CC ) increases, the maximum breaking energy (E SC 19, in the impurity profiles of new structure 1 and new structure 2, the electric field strength at the main junction 12 on the front surface 51a is higher than the electric field strength in the n-buffer layer on the back surface 51b even in a short-circuit state, and the electric field strength distribution inside the device in a short-circuit state does not become unbalanced, so the SOA in the short-circuit mode does not become narrow.

[0093] FIG. 20 shows the maximum blocking energy (E SC 20 is a graph showing the relationship between the n-type impurity concentration profile of the new structure 1 and the peak depth X2 of the n-type impurity concentration in the n-type second buffer layer 17. - The peak (C 2,n) is the depth of the IGBT. The semiconductor device according to the third embodiment (the semiconductor device having new structure 2) is configured to satisfy the following equation (6) in consideration of the relationship in FIG. 20. With this configuration, the dynamic SOA of the IGBT can be guaranteed.

[0094] X1 <X2≦4.0μm ···(6)

[0095] The maximum peak value C2 is the single peak value (C 2,0 ), the relationship of the formula explained in the second embodiment may also be satisfied in the third embodiment within the range of consistency.

[0096] <Fourth Embodiment> In this fourth embodiment, a method for manufacturing the IGBT according to the first to third embodiments will be described. Figures 21 to 23 are cross-sectional views showing steps of the manufacturing method according to the fourth embodiment. In the manufacturing method according to the fourth embodiment, an n-type first buffer layer 16 and an n-type second buffer layer 17 are formed as diffusion layers in a semiconductor substrate 51 including an MCZ wafer, and one or more different types of acceleration energy and dose amount are used in forming the n-type second buffer layer 17.

[0097] First, as shown in FIG. 21(a), a portion of the semiconductor substrate 51 is - 21(b), the p-type base layer 9 and the n-type layer 11 are formed on the front surface 51a side of the p-type drift layer 15 by ion implantation and annealing. Next, as shown in FIG. 21(b), the n-type base layer 9 and the n-type layer 11 are formed on the front surface 51a side of the p-type base layer 9 by ion implantation and annealing. + The type emitter layer 7 is formed.

[0098] Then, as shown in Figure 21(c), the n +A trench 24 is formed through the emitter layer 7, and the inner wall of the trench 24 is cleaned, smoothed, and rounded by etching and oxidation. Next, as shown in FIG. 21(d), a gate oxide film 13 is formed on the inner wall of the trench 24, and a 1×10 19 atoms / cm 3 21(d), the gate oxide film 13 and the polysilicon film 14a are also formed on the back surface 51b side of the semiconductor substrate 51.

[0099] As will be described later, in the step of FIG. 22(h) after the steps of FIG. 21(e) to FIG. 22(g), the polysilicon film 27 and the high concentration n + A gettering layer is formed, which is made up of a mold layer 28 and a high crystal defect density layer 29. - The gettering layer is configured to have a carrier lifetime of n so that the type drift layer 15 has a value equal to or greater than the carrier lifetime calculated by the following equation (7): - The carrier lifetime of the type drift layer 15 is restored.

[0100] τ t ≧1.5×10 -5 exp(5.4×10 3 ×t n- ) ···(7)

[0101] In addition, t n- [m] is n - is the thickness of the drift layer 15, and is indicated by t in FIG. device This is the device parameter equivalent to τ t [sec] is the time when the influence of carrier lifetime on the on-voltage of the IGBT disappears, n - 1 is the carrier lifetime in the type drift layer 15.

[0102] The on-voltage of the semiconductor device (IGBT, diode (a), diode (b)) is n -There is a dependency on the carrier lifetime of the type drift layer 15, and equation (7) represents the index of the carrier lifetime required to minimize this dependency. t If equation (7) is satisfied, the influence of carrier life on switching loss and loss due to turning off can be suppressed, so that reduction in loss due to turning off and suppression of thermal runaway can be expected.

[0103] 21(e), the steps will be described in detail. First, as shown in FIG. 21(e), the upper part of the polysilicon film 14a on the front surface 51a side is removed to form the gate electrode 14. + A mold layer 8 and an interlayer film 6 are formed. Next, as shown in FIG. 21(f), in order to expose the rear surface 51b of the semiconductor substrate 51, the gate oxide film 13 and the polysilicon film 14a on the rear surface 51b side are removed by wet etching using hydrofluoric acid or a mixed acid (for example, a mixture of hydrofluoric acid / nitric acid / acetic acid).

[0104] 22(g), a polysilicon film 27 doped with an n-type element is formed by LPCVD (low pressure CVD) on the front surface 51a and the back surface 51b of the semiconductor substrate 51. This polysilicon film 27 is a high concentration n-type doped polysilicon film shown in FIG. + The n-type element (atom) is used as a source for forming the n-type layer 28 and the high crystal defect density layer 29. The n-type element (atom) is diffused into Si to form n + An element (atom) capable of forming a mold layer, such as phosphorus, arsenic, or antimony, is used, and the element (atom) is, for example, 1×10 19 atoms / cm 3 The polysilicon film 27 is doped at the above concentration. The thickness of the polysilicon film 27 is, for example, 500 nm or more.

[0105] Next, with the back surface 51b of the semiconductor substrate 51 in direct contact with the polysilicon film 27 doped with a high concentration of impurities such as n-type elements, annealing is performed in a nitrogen atmosphere at 900 to 1000°C. Then, the temperature is lowered to 500 to 700°C at an arbitrary rate, and annealing is performed in a nitrogen atmosphere at a temperature lower than the previous annealing.

[0106] As shown in FIG. 22(h), this annealing causes the high-concentration impurities in the polysilicon film 27 to diffuse to the back surface 51b of the semiconductor substrate 51 that is in direct contact with the polysilicon film 27, forming a high-concentration n + A mold layer 28 is formed. + The mold layer 28 has a surface impurity concentration of, for example, 1.0×10 20 ~1.0×10 22 atoms / cm 3 and the depth from the rear surface 51b is, for example, 1.0 to 10 μm.

[0107] high concentration n + With the formation of the mold layer 28, n - A high crystal defect density layer 29, in which high density dislocations and lattice defects are introduced, is secondarily formed in the lower part of the type drift layer 15. In addition, by performing the annealing in a state where the polysilicon film 27 and the back surface 51b of the semiconductor substrate 51 are in direct contact with each other, the polysilicon film 27 and the high concentration n-type junction, which are the Si junction, are bonded to each other. + Strain occurs in the surface layer of the mold layer 28. This causes the high-concentration n + The mold layer 28, the high crystal defect density layer 29, and the polysilicon film 27 act as gettering sites. As a result, heavy metal and contaminant atoms taken into the semiconductor substrate 51 during the annealing process diffuse into the crystal lattice and are captured at the gettering sites.

[0108] Heavy metals and contaminant atoms are captured at gettering sites, resulting in a decrease in n - The carrier lifetime in the n-type drift layer 15 can be restored as shown in equation (7). - The n-type drift layer 15 is designed so that the carrier lifetime does not affect the electrical characteristics and hence the carrier lifetime of IGBTs of various breakdown voltage classes. - This allows the carrier lifetime in the type drift layer 15 to be sufficiently long.

[0109] The front surface 51a of the semiconductor substrate 51 is not in direct contact with the polysilicon film 27 due to the interlayer film 6, and therefore the front surface 51a of the semiconductor substrate 51 is not in direct contact with the polysilicon film 27, the high-concentration n + The gettering layer including the mold layer 28 and the high crystal defect density layer 29 is not formed.

[0110] Instead of forming the high crystal defect density layer 29 using the polysilicon film 27, the high crystal defect density layer 29 may be formed in the semiconductor substrate 51 by using laser annealing, which is capable of rapid heating / rapid cooling and local annealing, using a laser with a wavelength of 500 to 1000 nm. The power density of the laser annealing is, for example, 4 J / cm. 2 That is all. After the laser annealing, the same annealing as above is performed. That is, annealing is performed at 900 to 1000°C in a nitrogen atmosphere, and then annealing is performed in a nitrogen atmosphere at a temperature lower than the previous annealing temperature, at a temperature lowered at an arbitrary rate to 500 to 700°C. Even in this case, heavy metal and contaminant atoms taken into the semiconductor substrate 51 diffuse in the crystal lattice and are captured at the gettering site, resulting in n - The carrier lifetime of the type drift layer 15 can be restored.

[0111] As will be explained below, the polysilicon film 27, the high concentration n + The gettering layer including the mold layer 28 and the high crystal defect density layer 29 is removed in the step of FIG. 23(l) before the step of FIG. 23(m) for forming the n-type first buffer layer 16, the n-type second buffer layer 17, and the p-type collector layer 18.

[0112] As shown in Figure 23(i), the polysilicon film 27 on the front surface 51a side is removed by etching. Next, as shown in Figure 23(j), the interlayer film 6 is patterned. In Figure 23(j), some of the gate electrodes 14 are exposed from the interlayer film 6, but all of the gate electrodes 14 may be covered by the interlayer film 6.

[0113] As shown in FIG. 23(k), a silicide layer 30a, a barrier metal layer 30b, and a first electrode 5 are formed in this order on a front surface 51a of a semiconductor substrate 51 and on an interlayer film 6. The gate electrode 14 exposed from the interlayer film 6 and connected to the first electrode 5 becomes a dummy electrode 41. That is, in the example of FIG. 23(k), the trench electrode provided in the trench 24 includes the gate electrode 14 and the dummy electrode 41. By the steps up to FIG. 23(k), an n-type semiconductor substrate 51 is formed, which has a front surface 51a on which the first electrode 5 is provided and a back surface 51b opposite to the front surface 51a.

[0114] As shown in FIG. 23(l), after forming a protective film 31 on the first electrode 5, the polysilicon film 27 and the high-concentration n + The mold layer 28 and the high crystal defect density layer 29 are removed, and the device thickness (t device ) is set to, for example, 40 to 700 μm. Even after the step of FIG. 23(l), n - The carrier lifetime of the type drift layer 15 satisfies the formula (7).

[0115] As shown in FIG. 23(m), an n-type first buffer layer 16, an n-type second buffer layer 17, and a p-type collector layer 18 are formed on the back surface 51b, and the protective film 31 is removed. This results in a vertical structure on the back surface 51b. The front surface 51a, where the vertical structure is not formed, already contains a trench structure for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) included in the IGBT, as well as the first electrode 5 and interlayer film 6. Therefore, when forming the n-type first buffer layer 16, the n-type second buffer layer 17, and the p-type collector layer 18 that constitute the vertical structure, it is important to keep the temperature of the first electrode 5 on the front surface 51a lower than the melting point of the metal of the first electrode 5 (e.g., the melting point of aluminum, 660°C). To achieve this, a temperature gradient exists in the depth direction of the semiconductor substrate 51. For example, laser annealing using a laser with a wavelength that does not easily transfer heat to the front surface 51a, or annealing in a diffusion furnace at a low temperature below the melting point of the metal, may be used.

[0116] In the following, a method for manufacturing the IGBT described in the first and second embodiments by performing the step of Fig. 23(m) after the step of Fig. 23(l) will be mainly described. In the IGBT described in the first and second embodiments, the n-type second buffer layer 17 is formed by dividing the n-type first buffer layer 16 into n-type - The n-type impurity concentration peaks at C 2,1 ~C 2,n The buffer layer includes a 2-1 buffer layer to a 2-n buffer layer having the above structure.

[0117] In such an IGBT manufacturing method, it is important to control point defects and complex defects in the 2-1 buffer layer to the 2-n buffer layer, and to form the 2-1 buffer layer without interfering with the n-type first buffer layer 16. To achieve this, as will be explained below, the order of forming the n-type first buffer layer 16 and the n-type second buffer layer 17 and the setting of the peak position of the acceleration energy during ion implantation into the 2-1 buffer layer to the 2-n buffer layer are important.

[0118] 24 is a flowchart showing the steps of forming the structure on the back surface 51b side in the manufacturing method according to the fourth embodiment, that is, the steps of FIG. 23(l) and FIG. 23(m). First, in step S1, as shown in FIG. 23(l), a protective film 31 is formed on the first electrode 5. By polishing in step S2 and etching in step S3, the polysilicon film 27 and the high-concentration n + The mold layer 28 and the high crystal defect density layer 29 are removed, and the device thickness (t device ) is set to, for example, 40 to 700 μm.

[0119] In step S4, n - First ions are implanted into the back surface 51b side of the n-type drift layer 15, and in step S5, a first annealing of the first ions is performed to form the n-type first buffer layer 16 as shown in Fig. 23(m). The first ions include, for example, arsenic or phosphorus.

[0120] In step S6, the n-type first buffer layer 16 and the n -Second ions are implanted between the silicon nitride layer and the silicon drift layer. The second ions are protons (H + ) In addition, a cyclotron may be used for the proton implantation instead of the general ion implantation.

[0121] In step S6, the n-type first buffer layer 16 and the n - Protons (second ions) are introduced between the silicon nitride layer and the silicon nitride drift layer at one or more different types of acceleration energy and dose. For example, protons (second ions) are implanted in the order of decreasing acceleration energy, and the dose of protons implanted at a first acceleration energy is set lower than the dose of protons implanted at a second acceleration energy lower than the first acceleration energy. This allows n - The protons are implanted in the order of increasing dose, starting with the protons that will form the 2-n buffer layer on the n-type drift layer 15 side and ending with the protons that will form the 2-1 buffer layer on the n-type first buffer layer 16 side. As a result, when the protons (second ions) are annealed, n-type second buffer layer 17 including the 2-1 buffer layer to the 2-n buffer layer can be formed.

[0122] The peak of the 2-1 buffer layer in contact with the n-type first buffer layer 16 is at the junction (X j,n1 ) than n - The junction (X j,n2n ) side. This suppresses interference between the n-type first buffer layer 16 and the 2-1 buffer layer, allowing the 2-1 buffer layer to be formed with high precision. When manufacturing the IGBT according to the third embodiment, it is sufficient to introduce protons (second ions) with one type of different acceleration energy and dose.

[0123] In this way, if proton (second ion) annealing is performed after step S6, the n-type second buffer layer 17 can be formed. However, the first annealing in step S5 for forming the n-type first buffer layer 16 and the second annealing in step S10 for forming the p-type collector layer 18 (described later) are expected to be performed at temperatures higher than the third annealing for activating and forming the n-type second buffer layer 17. Therefore, performing an annealing at a temperature higher than the third annealing after the third annealing adversely affects the impurity profile of the HDs layer and the types of point defects and complex defects introduced in the n-type second buffer layer 17 to form the n-type second buffer layer 17. As a result, carriers (electrons or holes) in the device's on-state are adversely affected.

[0124] For this reason, in this fourth embodiment, the third annealing (step S12) for forming the n-type second buffer layer 17 is performed after the first annealing (step S5) for forming the n-type first buffer layer 16 and the second annealing (step S10) for forming the p-type collector layer 18.

[0125] When protons (second ions) are introduced in step S6 and the third annealing is performed in step S12, an HDs layer is formed as in the following steps A1 to A4. First, in step A1, protons are introduced into Si to form vacancies (v) and interstitial Si pairs (I Si In step A2, the interstitial Si pairs aggregate at room temperature, and W centers (I Si3 In step A3, the interstitial Si pairs are re-aggregated by the third annealing, and the X center (I Si4 In step A4, the hydrogen introduced by the proton and the W center (I Si3 Cluster) and X Center (I Si4 The HDs layer is formed by the reaction of the ions with the donor-type complex defects (clusters).

[0126] When an HDs layer is formed on the semiconductor substrate 51 using an MCZ wafer, the thermal donor phenomenon caused by oxygen in Si is added to the process, resulting in the final formation of the n-type second buffer layer 17. When an FZ wafer is used for the semiconductor substrate 51, the HDs layer becomes the n-type second buffer layer 17 as it is. As a result, - The n-layer, which has a higher impurity concentration than the n-type drift layer 15 and has become a donor, contributes to the operation of the device as the n-type second buffer layer 17. In the fourth embodiment, an MCZ wafer is used, and the complex defects formed in the n-type second buffer layer 17 are utilized to improve the device performance.

[0127] Note that the complex defects formed in the n-type second buffer layer 17 include defects that become lifetime killers that shorten the carrier lifetime. Therefore, in the fourth embodiment, as shown in Fig. 24, after the formation of the n-type first buffer layer 16 (step S5), a second ion implantation (step S6) and a third annealing (step S12) for the n-type second buffer layer 17 are performed. According to this manufacturing method, it is possible to control the complex defects in the n-type second buffer layer 17, thereby making it possible to remove defects that become lifetime killers and stabilize the profile of the n-type second buffer layer 17.

[0128] In step S7, photolithography is performed to form a patterned resist on the back surface 51b as a mask. In step S8, third ions are implanted into the back surface 51b side of the n-type first buffer layer 16 exposed through the mask. The third ions include, for example, boron. In step S9, the resist is removed. Note that if it is not necessary to partially form the p-type collector layer 18, steps S7 and S9 may be omitted. In step S10, a second annealing of boron (third ions) is performed to form a semiconductor layer including the p-type collector layer 18. In the second annealing, for example, the same annealing as in the first annealing step is performed. In step S11, the protective film 31 on the first electrode 5 is removed.

[0129] In step S12, a third annealing of protons (second ions) is performed to form the n-type second buffer layer 17. As the third annealing for making the n-type second buffer layer 17 into donors, the protons (second ions) are annealed at a temperature of 375°C or higher and 425°C or lower for 90 minutes or longer. In the third annealing, annealing different from the first annealing step is performed.

[0130] In step S13, light etching is performed on the rear surface 51b of the semiconductor substrate 51, and in step S14, a metal film that will become the second electrode 21 is formed on the rear surface 51b of the semiconductor substrate 51 by sputtering. The metal film is, for example, an AlSi film with an Si addition amount of 1 to 3%. In step S15, fourth annealing is performed to form an alloy layer or a silicide layer between the rear surface 51b of the semiconductor substrate 51 and the metal film, thereby forming the second electrode 21. The temperature of the fourth annealing is, for example, lower than that of the third annealing, for example, a temperature less than 375°C.

[0131] In this way, the IGBTs according to the first to third embodiments are completed. i ], then equation (1) is satisfied. Also, for the carrier lifetime, n - The following formula (8) is satisfied between the n-type drift layer 15, the n-type first buffer layer 16, and the n-type second buffer layer 17.

[0132] τ2<τ1≦τ t ···(8)

[0133] Here, τ2 is the carrier lifetime of the n-type second buffer layer 17, and τ1 is the carrier lifetime of the n-type first buffer layer 16. t has no effect on the on-voltage of the IGBT (i.e., the on-voltage of the gate electrode), - 1 is the carrier lifetime of the type drift layer 15.

[0134] According to the semiconductor device manufacturing method of the fourth embodiment described above, the IGBTs according to the first to third embodiments can be formed. Furthermore, in the fourth embodiment, an n-type second buffer layer 17 can be formed from an MCZ wafer made of Si with a high oxygen concentration, which includes an HDs layer and is subjected to the thermal donor phenomenon by the third annealing of protons (second ions). Furthermore, in the fourth embodiment, the order of forming the n-type first buffer layer 16 and the n-type second buffer layer 17 and the setting of the peak position of the acceleration energy during ion implantation into the 2-1 buffer layer to the 2-n buffer layer are optimized. Therefore, point defects and complex defects in the 2-1 buffer layer to the 2-n buffer layer can be controlled, and interference between the n-type first buffer layer 16 and the 2-1 buffer layer can be suppressed.

[0135] <Fifth Embodiment> In this fifth embodiment, a method for manufacturing the diode (a) and diode (b) according to the first to third embodiments will be described. Figures 25 to 27 are cross-sectional views showing steps in the manufacturing method of this fifth embodiment, specifically, cross-sectional views showing steps in the manufacturing method of diode (b). In this fifth embodiment, as in the fourth embodiment, an n-type first buffer layer 16 and an n-type second buffer layer 17 are formed on a semiconductor substrate 51 including an MCZ wafer, and one or more different types of acceleration energy and dose amount are used to form the n-type second buffer layer 17.

[0136] 25(a), a patterned oxide film 33 is formed on the front surface 51a of the semiconductor substrate 51 by photolithography and resist removal. After that, a thin oxide film 34 is formed by re-oxidation, and the n-type oxide film 34 of the termination region 3 is formed by ion implantation, photolithography, resist removal, and annealing. - 25(b), a p-type layer 32 is formed on the front surface 51a side of the drift layer 15. Next, as shown in FIG. 25(b), the n-type layer 32 of the active region 1 is formed by ion implantation, photolithography, resist removal, and annealing. -25(c), a p-type anode layer 10 is formed on the front surface 51a side of the n-type drift layer 15. Then, as shown in FIG. 25(c), a portion of the oxide film 33 in the termination region 3 is removed, and an n-type anode layer 10 is formed on the front surface 51a by ion implantation, photolithography, resist removal, and annealing. + A mold layer 35 is formed. Then, an oxide film-based interlayer film 6 is formed on the front surface 51a, and then the polysilicon film 27 described in the fourth embodiment is formed on the front surface 51a side and the back surface 51b side.

[0137] Next, annealing is performed at 900 to 1000°C in a nitrogen atmosphere, and then annealing is performed at a temperature lower than the previous annealing in a nitrogen atmosphere at 500 to 700°C at an arbitrary temperature drop rate. As a result, as shown in FIG. 26(d), a high-concentration n-type silicon layer including a Si junction is formed on the back surface 51b side. + A gettering site is formed including the mold layer 28, the high crystal defect density layer 29, and the polysilicon film 27. As a result, the n-type silicon nitride film according to the fifth embodiment is formed. - The n-type drift layer 15 according to the fourth embodiment - As in the type drift layer 15, the carrier lifetime is restored and the formula (7) is satisfied.

[0138] 26(e), the polysilicon film 27 on the front surface 51a side is removed by etching. Next, as shown in FIG. 26(f), the interlayer film 6 and the like are patterned to expose the p-type anode layer 10, the p-type layer 32, and the n-type layer 33. + The first electrode 5 is formed on the mold layer 35 and the interlayer film 6. As in FIG. 23(k), a silicide layer 30a and a barrier metal layer 30b may be provided.

[0139] Next, as shown in Fig. 27(g), a passivation film 36 is formed on the first electrode 5. Then, as shown in Fig. 27(h), a protective film 31 is formed on the first electrode 5, and then the polysilicon film 27, the high-concentration n + The type layer 28 and the high crystal defect density layer 29 are then removed. Then, as shown in FIG. 27(i), the n-type first buffer layer 16, the n-type second buffer layer 17, and the n-type +Then, a n-type cathode layer 19 and a p-type cathode layer 20 are formed, and the protective film 31 is removed.

[0140] Fig. 28 is a flowchart showing the steps of forming the structure on the back surface 51b side of the manufacturing method for diode (b) according to the fifth embodiment, that is, the steps of Fig. 27(h) and Fig. 27(i). The steps of Fig. 28 are the same as those of Fig. 24, except that step S21 is added and steps S8 and S10 are changed to steps S8a and S10a.

[0141] In step S21 between steps S6 and S7, third ions containing, for example, boron are implanted into the back surface 51b side of the n-type first buffer layer 16. In step S8a after step S7, third ions containing, for example, arsenic or phosphorus are implanted into the back surface 51b side of the n-type first buffer layer 16 exposed from the mask. The third ions in steps 8a and S21 form a semiconductor layer connected to the second electrode 21, but the conductivity type of the third ions in step 8a is different from that of the third ions in step S21. After step S9, in step S10a, a second annealing of the third ions is performed to form the n + A semiconductor layer including a p-type cathode layer 19 and a p-type cathode layer 20 is formed.

[0142] 29 is a flowchart showing the steps of forming the structure on the back surface 51b side of the manufacturing method for the diode (a) according to the fifth embodiment. The steps in FIG. 29 are the same as those in FIG. 28 except that step S21 is deleted and step S10a is changed to step S10b. In step S10b, a second annealing of the third ions is performed, which does not include the p-type cathode layer 20 but includes n + A semiconductor layer including an n-type cathode layer 19 is formed. + If it is not necessary to partially form the mold cathode layer 19, steps S7 and S9 may be omitted.

[0143] According to the semiconductor device manufacturing method of the fifth embodiment described above, the diode (a) or diode (b) according to the first to third embodiments can be formed. Furthermore, in the fifth embodiment, an n-type second buffer layer 17 can be formed from an MCZ wafer made of Si with a high oxygen concentration, which includes an HDs layer and is subjected to the thermal donor phenomenon by the third annealing of protons (second ions). Furthermore, in the fifth embodiment, the order of forming the n-type first buffer layer 16 and the n-type second buffer layer 17 and the setting of the peak position of the acceleration energy during ion implantation into the 2-1 buffer layer to the 2-n buffer layer are optimized. Therefore, point defects and complex defects in the 2-1 buffer layer to the 2-n buffer layer can be controlled, and interference between the n-type first buffer layer 16 and the 2-1 buffer layer can be suppressed.

[0144] <Sixth Embodiment> In the semiconductor devices according to the first to third embodiments, an IGBT or a diode is provided in the active region 1 of the semiconductor substrate 51, but both an IGBT and a diode may be provided in the active region 1 of the same semiconductor substrate 51.

[0145] 30 to 37 are cross-sectional views showing the configuration of a semiconductor device according to the sixth embodiment. The semiconductor device according to the sixth embodiment is an RC-IGBT (Reverse Conducting-IGBT) having a trench gate structure and including an IGBT and a diode provided on the same semiconductor substrate 51. An IGBT region 52a that functions as an IGBT and a diode region 52b that functions as a diode are defined in the semiconductor substrate 51 of the RC-IGBT.

[0146] The IGBT region 52a has the same configuration as the IGBTs according to the first to third embodiments, including an n-type first buffer layer 16, an n-type second buffer layer 17, and a p-type collector layer 18. The diode region 52b has the same configuration as the diode (a) or diode (b) according to the first to third embodiments, including an n-type first buffer layer 16, an n-type second buffer layer 17, and a p-type collector layer 18. + Both the p-type cathode layer 19 and the p-type cathode layer 20, or +A cathode layer 19 is provided.

[0147] The diode region 52b in FIG. 30 does not include the p-type cathode layer 20. + The diode (a) has a structure similar to that of the diode (a) according to the first to third embodiments, including a p-type cathode layer 19. The p-type cathode layer 19 has a p-type impurity concentration higher than that of the p-type anode layer 10. + A mold layer 8 is provided between the first electrode 5 and the p-type anode layer 10 .

[0148] The configuration of Figure 31 is p from the configuration of Figure 30. + 31 is similar to the configuration in which the mold layer 8 is omitted, and the p-type anode layer 10 is in contact with the first electrode 5. The configuration in FIG. 31 can reduce the efficiency of hole injection from the p-type anode layer 10 when the diode is in the on state compared to the configuration in FIG. 30.

[0149] The diode region 52b in FIG. + The diode (b) has a structure similar to that of the diode (b) according to the first to third embodiments, including both the p-type cathode layer 19 and the p-type cathode layer 20. The p-type cathode layer 19 has a higher p-type impurity concentration than the p-type anode layer 10. + A mold layer 8 is provided between the first electrode 5 and the p-type anode layer 10 .

[0150] The configuration of Figure 33 is p from the configuration of Figure 32. + 32 and 33, the p-type cathode layer 20 reduces the efficiency of electron injection from the back surface 51b when the diode is in the on state compared to the configurations of FIGS. 30 and 31.

[0151] 31 to 33 can suppress the hole injection efficiency from the p-type base layer 9 or the electron injection efficiency from the rear surface 51b when the diode is in the on state more effectively than the RC-IGBT of FIG. 30. Therefore, the turn-off loss (EREC ) and on-state voltage (V F ) and the high-speed portion of the curve (low E REC and high V F This can prevent the semiconductor substrate 51 from depending on carrier lifetime control by charged particles such as electron beams. In particular, the adverse effects on diode performance caused by impurities such as oxygen and carbon in the MCZ wafer become more pronounced when carrier lifetime control by charged particles is performed. For this reason, when the semiconductor substrate 51 is an MCZ wafer, E REC and V F The configurations of FIGS. 31 to 33 are effective in preventing the performance in the high-speed portion of the curve showing the trade-off characteristics from depending on carrier lifetime control.

[0152] 34 to 37 are similar to the configurations in FIGS. 30 to 33 in that the trench electrodes in some of the trenches 24 are electrically connected to the first electrode 5, thereby forming dummy electrodes 41 that have the same emitter potential as the first electrode 5. With this configuration, oscillation in a no-load short-circuit state can be suppressed by suppressing the saturation current density of the IGBT region 52a and controlling the capacitance characteristics, thereby improving the short-circuit resistance and reducing the on-voltage by increasing the carrier concentration on the emitter side.

[0153] The sixth embodiment as described above includes the IGBT according to any one of the first to third embodiments and the diode (a) or diode (b) according to any one of the first to third embodiments. With this configuration, for example, even in an RC-IGBT, similar to the first embodiment, it is possible to achieve a normal on-state operation and improved breakdown resistance during dynamic operation while maintaining sufficient off-state withstand voltage holding capability.

[0154] <Modification> In the above description, the semiconductor substrate 51 is made of silicon, but this is not limiting. For example, the semiconductor substrate 51 may be made of a wide bandgap semiconductor such as silicon carbide (SiC). When the semiconductor substrate 51 is made of a wide bandgap semiconductor, stable operation under high temperatures and high voltages and faster switching speeds are possible. Furthermore, a MOSFET may be provided instead of the IGBT, and the diode may be an SBD (Schottky Barrier Diode) or a PND (PN junction diode).

[0155] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0156] Various aspects of the present disclosure are summarized below as appendices.

[0157] (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first electrode and a second electrode provided on the first main surface and the second main surface, respectively; Equipped with The semiconductor substrate is a drift layer of a first conductivity type provided between the first major surface and the second major surface; a semiconductor layer connected to the second electrode and including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first buffer layer of a first conductivity type provided between the semiconductor layer and the drift layer; a second buffer layer of the first conductivity type provided between the first buffer layer and the drift layer, the second buffer layer having a first conductivity type impurity concentration lower than that of the first buffer layer and higher than that of the drift layer; Including, The maximum oxygen concentration of the semiconductor substrate calculated using the old ASTM conversion factor is expressed as maximum [O i ], and the first conductivity type impurity concentration of the drift layer is C drift In this case, maximum[O i ]=9.40×10 16 ×ln(C drift )-2.27×10 18 The semiconductor device is characterized in that:

[0158] (Appendix 2) 10. The semiconductor device according to claim 1, The second buffer layer is are provided in order from the first buffer layer toward the drift layer, and have a peak value of the first conductivity type impurity concentration of C 2,1 ~C 2,n 2-1 buffer layer to 2-n buffer layer having C 2,n <··· <C 2,2 <C 2,1 The semiconductor device is characterized in that:

[0159] (Appendix 3) The semiconductor device according to claim 1 or 2, When the maximum peak value of the first conductivity type impurity concentration of the second buffer layer is C2, C drift <C2≦1.0×10 15 cm -3 The semiconductor device is characterized in that:

[0160] (Appendix 4) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, When the maximum peak value of the first conductivity type impurity concentration of the first buffer layer is C1 and the maximum peak value of the first conductivity type impurity concentration of the second buffer layer is C2, 1.0×10 -4 ≦C2 / C1≦1.0×10 -1 The semiconductor device is characterized in that:

[0161] (Appendix 5) 10. The semiconductor device according to claim 1, the second buffer layer is a single layer; When the depth of the peak of the first conductivity type impurity concentration of the first buffer layer from the second main surface is X1 and the depth of the peak of the first conductivity type impurity concentration of the second buffer layer from the second main surface is X2, X1 <X2≦4.0μm The semiconductor device is characterized in that:

[0162] (Appendix 6) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, a maximum peak value of the concentration of the first conductivity type impurities in the second buffer layer is less than a maximum peak value of the concentration of the first conductivity type impurities in the first buffer layer. (Appendix 7) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, The semiconductor device, wherein the first conductivity type impurity of the drift layer contains antimony. (Appendix 8) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, The semiconductor substrate is a second conductivity type base layer provided closer to the first main surface than the drift layer; an emitter layer of a first conductivity type provided closer to the first main surface than the base layer; further comprising a trench electrode including a gate electrode is provided in a trench that penetrates the base layer and the emitter layer; The semiconductor device, wherein the semiconductor layer includes the second semiconductor layer connected to the second electrode. (Appendix 9) 10. The semiconductor device according to claim 1, The carrier lifetime of the drift layer, the carrier lifetime of the first buffer layer, and the carrier lifetime of the second buffer layer, at which the influence on the on-voltage is eliminated, are respectively defined as τ t and τ1 and τ2, τ2<τ1≦τ t The semiconductor device is characterized in that: (Appendix 10) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, The semiconductor substrate is further including an anode layer of a second conductivity type provided closer to the first main surface than the drift layer; The semiconductor device, wherein the semiconductor layer includes the first semiconductor layer connected to the second electrode. (Appendix 11) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, The semiconductor substrate is further including an anode layer of a second conductivity type provided closer to the first main surface than the drift layer; The semiconductor device, wherein the semiconductor layer includes the first semiconductor layer and the second semiconductor layer connected to the second electrode. (Appendix 12) a first semiconductor device that is the semiconductor device according to Supplementary Note 8; a second semiconductor device, which is the semiconductor device according to Supplementary Note 10, provided on the semiconductor substrate on which the first semiconductor device is provided; A semiconductor device comprising: (Appendix 13) a first semiconductor device that is the semiconductor device according to Supplementary Note 8; a second semiconductor device, which is the semiconductor device according to Supplementary Note 11, provided on the semiconductor substrate on which the first semiconductor device is provided; A semiconductor device comprising: (Appendix 14) 14. The semiconductor device according to claim 12, The semiconductor substrate of the second semiconductor device is The semiconductor device further includes an impurity diffusion layer of a second conductivity type provided between the first electrode and the anode layer and having a higher impurity concentration of the second conductivity type than the anode layer. (Appendix 15) The semiconductor device according to any one of Supplementary Note 12 to Supplementary Note 14, The anode layer is in contact with the first electrode. (Appendix 16) The semiconductor device according to any one of Supplementary Note 12 to Supplementary Note 15, The semiconductor device, wherein the trench electrode further includes a dummy electrode electrically connected to the first electrode. (Appendix 17) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 16, the first conductivity type impurity of the first buffer layer includes arsenic or phosphorus; The semiconductor device, wherein the impurities of the first conductivity type in the second buffer layer include protons. (Appendix 18) preparing a semiconductor substrate of a first conductivity type having a first main surface on which a first electrode is provided and a second main surface opposite to the first main surface; forming a first buffer layer of a first conductivity type by implanting first ions into the second main surface side of a drift layer that is a part of the semiconductor substrate and annealing the first ions; implanting second ions between the first buffer layer and the drift layer; implanting third ions into the second main surface side of the first buffer layer; forming a semiconductor layer including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type by annealing the third ions; annealing the second ions to form a second buffer layer of the first conductivity type, the second buffer layer having a first conductivity type impurity concentration lower than that of the first buffer layer and higher than that of the drift layer; forming a second electrode on the second main surface; Equipped with The maximum oxygen concentration of the semiconductor substrate calculated using the old ASTM conversion factor is expressed as maximum [O i ], and the first conductivity type impurity concentration of the drift layer is C drift In this case, maximum[O i ]=9.40×10 16 ×ln(C drift )-2.27×10 18 The present invention provides a method for manufacturing a semiconductor device, in which the above-mentioned requirements are met. (Appendix 19) 19. A method for manufacturing a semiconductor device according to claim 18, comprising: The semiconductor layer includes the first semiconductor layer. (Appendix 20) 19. A method for manufacturing a semiconductor device according to claim 18, comprising: The semiconductor layer includes the second semiconductor layer. (Appendix 21) 19. A method for manufacturing a semiconductor device according to claim 18, comprising: A method for manufacturing a semiconductor device, wherein the semiconductor layer includes the first semiconductor layer and the second semiconductor layer. (Appendix 22) A method for manufacturing a semiconductor device according to any one of Supplementary Note 18 to Supplementary Note 21, implanting the second ions in a sequence of decreasing acceleration energies; A method for manufacturing a semiconductor device, wherein a dose of the second ions implanted at a first acceleration energy is lower than a dose of the second ions implanted at a second acceleration energy lower than the first acceleration energy. (Appendix 23) A method for manufacturing a semiconductor device according to any one of Supplementary Note 18 to Supplementary Note 22, comprising: the first ions include arsenic or phosphorus; The method for manufacturing a semiconductor device, wherein the second ions include protons. (Appendix 24) A method for manufacturing a semiconductor device according to any one of Supplementary Note 18 to Supplementary Note 23, comprising: The method for manufacturing a semiconductor device further comprises annealing the second ions at a temperature of 375° C. to 425° C. for a time of 90 minutes or more. (Appendix 25) A method for manufacturing a semiconductor device according to any one of Supplementary Note 18 to Supplementary Note 24, comprising: The semiconductor substrate includes a semiconductor wafer produced by an MCZ method. (Appendix 26) A method for manufacturing a semiconductor device according to any one of Supplementary Note 18 to Supplementary Note 25, The method for manufacturing a semiconductor device, wherein the semiconductor substrate contains antimony as a first conductivity type impurity. [Explanation of symbols]

[0163] 5 first electrode, 7 n + Type emitter layer, 8p + 9 p-type base layer; 10 p-type anode layer; 14 gate electrode; 15 n - 16 n-type first buffer layer; 17 n-type second buffer layer; 18 p-type collector layer; 19 n + 20 p-type cathode layer, 24 trench, 21 second electrode, 41 dummy electrode, 51 semiconductor substrate, 51a front surface, 51b back surface.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first electrode and a second electrode provided on the first main surface and the second main surface, respectively; Equipped with The semiconductor substrate is a drift layer of a first conductivity type provided between the first major surface and the second major surface; a semiconductor layer connected to the second electrode and including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first buffer layer of a first conductivity type provided between the semiconductor layer and the drift layer; a second buffer layer of the first conductivity type provided between the first buffer layer and the drift layer, the second buffer layer having a first conductivity type impurity concentration lower than that of the first buffer layer and higher than that of the drift layer; Including, The maximum value of the oxygen concentration of the semiconductor substrate calculated using the Old ASTM conversion factor is expressed as maximum [O ｉ ], and the first conductivity type impurity concentration of the drift layer is set to C ｄｒｉｆｔ In this case, [ON ｉ ]=9.40×10 １６ ×ln(C ｄｒｉｆｔ )-2.27×10 １８ The semiconductor device is characterized in that:

2. 2. The semiconductor device according to claim 1, The second buffer layer is The first buffer layer and the drift layer are sequentially provided, and the peak value of the first conductivity type impurity concentration is C ２，１ ~C ２，ｎ 2-1 buffer layer to 2-n buffer layer having C ２，ｎ <・・・<C ２，２ <C ２，１ The semiconductor device is characterized in that:

3. 3. The semiconductor device according to claim 1, The maximum peak value of the first conductivity type impurity concentration of the second buffer layer is C ２ In this case, C ｄｒｉｆｔ <C ２ ≦1.0×10 １５ cm －３ The semiconductor device is characterized in that:

4. 3. The semiconductor device according to claim 1, The maximum peak value of the first conductivity type impurity concentration of the first buffer layer is C １ the maximum peak value of the first conductivity type impurity concentration of the second buffer layer is C ２ In this case, 1.0×10 －４ ≦C ２ / C １ ≦1.0×10 －１ The semiconductor device is characterized in that:

5. 2. The semiconductor device according to claim 1, the second buffer layer is a single layer; The depth of the peak of the first conductivity type impurity concentration of the first buffer layer from the second main surface is defined as X １ the depth of the peak of the first conductivity type impurity concentration of the second buffer layer from the second main surface is X ２ In this case, X １ <X ２ ≦4.0μm The semiconductor device is characterized in that:

6. 3. The semiconductor device according to claim 1, a maximum peak value of the concentration of the first conductivity type impurity in the second buffer layer is less than a maximum peak value of the concentration of the first conductivity type impurity in the first buffer layer.

7. 3. The semiconductor device according to claim 1, the first conductivity type impurity of the drift layer contains antimony.

8. 2. The semiconductor device according to claim 1, The semiconductor substrate is a second conductivity type base layer provided closer to the first main surface than the drift layer; an emitter layer of a first conductivity type provided closer to the first main surface than the base layer; further comprising a trench electrode including a gate electrode is provided in a trench that penetrates the base layer and the emitter layer; The semiconductor device, wherein the semiconductor layer includes the second semiconductor layer connected to the second electrode.

9. 2. The semiconductor device according to claim 1, The carrier lifetime of the drift layer, the carrier lifetime of the first buffer layer, and the carrier lifetime of the second buffer layer, at which the influence on the on-voltage disappears, are respectively defined as τ ｔ and τ １ and τ ２ In this case, t ２ <t １ ≦t ｔ The semiconductor device is characterized in that:

10. 2. The semiconductor device according to claim 1, The semiconductor substrate is further including an anode layer of a second conductivity type provided closer to the first main surface than the drift layer; The semiconductor device, wherein the semiconductor layer includes the first semiconductor layer connected to the second electrode.

11. 2. The semiconductor device according to claim 1, The semiconductor substrate is further including an anode layer of a second conductivity type provided closer to the first main surface than the drift layer; The semiconductor device, wherein the semiconductor layer includes the first semiconductor layer and the second semiconductor layer connected to the second electrode.

12. a first semiconductor device that is the semiconductor device according to claim 8; a second semiconductor device, which is the semiconductor device according to claim 10, provided on the semiconductor substrate on which the first semiconductor device is provided; A semiconductor device comprising:

13. a first semiconductor device that is the semiconductor device according to claim 8; a second semiconductor device, which is the semiconductor device according to claim 11, provided on the semiconductor substrate on which the first semiconductor device is provided; A semiconductor device comprising:

14. 14. The semiconductor device according to claim 12, The semiconductor substrate of the second semiconductor device is The semiconductor device further includes an impurity diffusion layer of a second conductivity type provided between the first electrode and the anode layer and having a higher impurity concentration of the second conductivity type than the anode layer.

15. 14. The semiconductor device according to claim 12, The anode layer is in contact with the first electrode.

16. 14. The semiconductor device according to claim 12, The semiconductor device, wherein the trench electrode further includes a dummy electrode electrically connected to the first electrode.

17. 3. The semiconductor device according to claim 1, the first conductivity type impurity of the first buffer layer includes arsenic or phosphorus; The semiconductor device, wherein the impurities of the first conductivity type in the second buffer layer include protons.

18. preparing a semiconductor substrate of a first conductivity type having a first main surface on which a first electrode is provided and a second main surface opposite to the first main surface; forming a first buffer layer of a first conductivity type by implanting first ions into the second main surface side of a drift layer that is a part of the semiconductor substrate and annealing the first ions; implanting second ions between the first buffer layer and the drift layer; implanting third ions into the second main surface side of the first buffer layer; forming a semiconductor layer including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type by annealing the third ions; annealing the second ions to form a second buffer layer of the first conductivity type, the second buffer layer having a first conductivity type impurity concentration lower than that of the first buffer layer and higher than that of the drift layer; forming a second electrode on the second main surface; Equipped with The maximum value of the oxygen concentration of the semiconductor substrate calculated using the Old ASTM conversion factor is expressed as maximum [O ｉ ], and the first conductivity type impurity concentration of the drift layer is set to C ｄｒｉｆｔ In this case, [ON ｉ ]=9.40×10 １６ ×ln(C ｄｒｉｆｔ )-2.27×10 １８ The present invention provides a method for manufacturing a semiconductor device, in which the above-mentioned requirements are met.

19. 20. The method of manufacturing a semiconductor device according to claim 18, The semiconductor layer includes the first semiconductor layer.

20. 20. The method of manufacturing a semiconductor device according to claim 18, The semiconductor layer includes the second semiconductor layer.

21. 20. The method of manufacturing a semiconductor device according to claim 18, The semiconductor layer includes the first semiconductor layer and the second semiconductor layer.

22. 22. The method for manufacturing a semiconductor device according to claim 18, further comprising the steps of: implanting the second ions in a sequence of decreasing acceleration energies; A method for manufacturing a semiconductor device, wherein a dose of the second ions implanted at a first acceleration energy is lower than a dose of the second ions implanted at a second acceleration energy lower than the first acceleration energy.

23. 22. The method for manufacturing a semiconductor device according to claim 18, further comprising the steps of: the first ions include arsenic or phosphorus; The method for manufacturing a semiconductor device, wherein the second ions include protons.

24. 22. The method for manufacturing a semiconductor device according to claim 18, further comprising the steps of: The method for manufacturing a semiconductor device further comprises annealing the second ions at a temperature of 375° C. to 425° C. for a time of 90 minutes or more.

25. 22. The method for manufacturing a semiconductor device according to claim 18, further comprising the steps of: The semiconductor substrate includes a semiconductor wafer produced by an MCZ method.

26. 22. The method for manufacturing a semiconductor device according to claim 18, further comprising the steps of: The semiconductor substrate contains antimony as a first conductivity type impurity.

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